The European Conference on Wireless Technology, 2005., 2005
This paper presents the design of two different digital interfaces, both based on current signall... more This paper presents the design of two different digital interfaces, both based on current signalling. First the requirements for a digital interface at the baseband output of a multi-standard mobile phone RF front-end are explained. The paper gives an insight of the popular digital interfaces and presents a new concept which is more robust against the ground bounce effect. At
2007 European Conference on Wireless Technologies, 2007
The polar transmitter concept promises significant higher power efficiency utilizing nonlinear po... more The polar transmitter concept promises significant higher power efficiency utilizing nonlinear power amplifiers. RF transmitters using polar transmitter technique are currently available for EDGE systems and are under development for UMTS. The UMTS extensions HSDPA and HSUPA provide a number of additional physical uplink channels which can lead to a variety of constellations incorporating constellation points at the I/Q origin.
2009 IEEE Radio Frequency Integrated Circuits Symposium, 2009
This paper presents a wideband receiver front-end implemented in 0.13 mum CMOS technology. The fr... more This paper presents a wideband receiver front-end implemented in 0.13 mum CMOS technology. The front-end consists of a low-noise amplifier (LNA), a quadrature mixer, and a frequency divider. Multi-gated transistors have been used to enable linearity tuning. The circuit employs no inductors and operates from 0.3-2.6 GHz with a tunable baseband bandwidth. The front-end achieves conversion voltage gain of 38
2000 IEEE Ultrasonics Symposium. Proceedings. An International Symposium (Cat. No.00CH37121), 2000
ABSTRACT This paper presents the influence of signal filtering on the performance of a W-CDMA rec... more ABSTRACT This paper presents the influence of signal filtering on the performance of a W-CDMA receiver suitable for the 3rd Generation Partnership Project (3GPP) Frequency Division Duplex (FDD) mode. The impact of adjacent channel selectivity and inchannel distortions introduced by the filter is investigated. An evaluation of these parameters is especially important for IF-SAW filter design
This paper presents the impact of amplitude nonlinearities in terms of 1 dB compression point (Pl... more This paper presents the impact of amplitude nonlinearities in terms of 1 dB compression point (PldB) and third order intercept point (IP3) on the performance of a W-CDMA receiver suitable for the rd Generation Partnership Project (3GPP) Frequency Division Duplex (FDD) mode. An evaluation of these parameters is especially important in receiver front end design. The base parameters for the setup of the system simulations come from the maximum input level testcase as set forth by the 3GPP. This testcase sets the maximum tolerable bounds for inband distortions, since most of the signal consists of interference coming from other users sharing the same frequency band. First, a detailed description of the simulation chains being implemented and a review of the maximum input level testcase are given. Next, simulation results consisting of bit error rate (BER) curves versus PldB are presented
2006 European Conference on Wireless Technologies, 2006
... A positive spin-off is the high linearity CG-LNAs are known for. As we are dealing with the s... more ... A positive spin-off is the high linearity CG-LNAs are known for. As we are dealing with the second LNA in the receive chain the inferior noise figure (NF) of theCG topology can be tolerated for the benefit of a broadband input match, robustness to processvariations and stability. ...
An integrated quadrature demodulator with an on-chip frequency divider is reported. The mixer con... more An integrated quadrature demodulator with an on-chip frequency divider is reported. The mixer consists of a transconductance stage, a passive current switching stage, and an operational amplifier output stage. A complementary input architecture has been used to increase the transconductance for a given bias current. The circuit is inductorless and is capable of operating over a broad frequency range. The chip was implemented in a 0.13m CMOS technology. From 700 MHz to 2.5 GHz, the demodulator achieves 35 dB of conversion voltage gain with 250-kHz IF bandwidth, a double-sideband NF of 10 dB with 9-33 kHz 1/f-noise corner. The measured IIP3 is +4 dBm for a 0.1-MHz IF frequency and +10 dBm for a 1-MHz IF frequency.
Abstract A 9 GHz fully digitally controlled oscillator implemented in 65 nm CMOS technology is pr... more Abstract A 9 GHz fully digitally controlled oscillator implemented in 65 nm CMOS technology is presented. This is the first DCO implemented at 9 GHz which covers all transmitter (TX) and receiver (RX) bands of GSM/EDGE and UMTS except Band VII. It covers a coarse ...
The European Conference on Wireless Technology, 2005., 2005
This paper presents the design of two different digital interfaces, both based on current signall... more This paper presents the design of two different digital interfaces, both based on current signalling. First the requirements for a digital interface at the baseband output of a multi-standard mobile phone RF front-end are explained. The paper gives an insight of the popular digital interfaces and presents a new concept which is more robust against the ground bounce effect. At
2007 European Conference on Wireless Technologies, 2007
The polar transmitter concept promises significant higher power efficiency utilizing nonlinear po... more The polar transmitter concept promises significant higher power efficiency utilizing nonlinear power amplifiers. RF transmitters using polar transmitter technique are currently available for EDGE systems and are under development for UMTS. The UMTS extensions HSDPA and HSUPA provide a number of additional physical uplink channels which can lead to a variety of constellations incorporating constellation points at the I/Q origin.
2009 IEEE Radio Frequency Integrated Circuits Symposium, 2009
This paper presents a wideband receiver front-end implemented in 0.13 mum CMOS technology. The fr... more This paper presents a wideband receiver front-end implemented in 0.13 mum CMOS technology. The front-end consists of a low-noise amplifier (LNA), a quadrature mixer, and a frequency divider. Multi-gated transistors have been used to enable linearity tuning. The circuit employs no inductors and operates from 0.3-2.6 GHz with a tunable baseband bandwidth. The front-end achieves conversion voltage gain of 38
2000 IEEE Ultrasonics Symposium. Proceedings. An International Symposium (Cat. No.00CH37121), 2000
ABSTRACT This paper presents the influence of signal filtering on the performance of a W-CDMA rec... more ABSTRACT This paper presents the influence of signal filtering on the performance of a W-CDMA receiver suitable for the 3rd Generation Partnership Project (3GPP) Frequency Division Duplex (FDD) mode. The impact of adjacent channel selectivity and inchannel distortions introduced by the filter is investigated. An evaluation of these parameters is especially important for IF-SAW filter design
This paper presents the impact of amplitude nonlinearities in terms of 1 dB compression point (Pl... more This paper presents the impact of amplitude nonlinearities in terms of 1 dB compression point (PldB) and third order intercept point (IP3) on the performance of a W-CDMA receiver suitable for the rd Generation Partnership Project (3GPP) Frequency Division Duplex (FDD) mode. An evaluation of these parameters is especially important in receiver front end design. The base parameters for the setup of the system simulations come from the maximum input level testcase as set forth by the 3GPP. This testcase sets the maximum tolerable bounds for inband distortions, since most of the signal consists of interference coming from other users sharing the same frequency band. First, a detailed description of the simulation chains being implemented and a review of the maximum input level testcase are given. Next, simulation results consisting of bit error rate (BER) curves versus PldB are presented
2006 European Conference on Wireless Technologies, 2006
... A positive spin-off is the high linearity CG-LNAs are known for. As we are dealing with the s... more ... A positive spin-off is the high linearity CG-LNAs are known for. As we are dealing with the second LNA in the receive chain the inferior noise figure (NF) of theCG topology can be tolerated for the benefit of a broadband input match, robustness to processvariations and stability. ...
An integrated quadrature demodulator with an on-chip frequency divider is reported. The mixer con... more An integrated quadrature demodulator with an on-chip frequency divider is reported. The mixer consists of a transconductance stage, a passive current switching stage, and an operational amplifier output stage. A complementary input architecture has been used to increase the transconductance for a given bias current. The circuit is inductorless and is capable of operating over a broad frequency range. The chip was implemented in a 0.13m CMOS technology. From 700 MHz to 2.5 GHz, the demodulator achieves 35 dB of conversion voltage gain with 250-kHz IF bandwidth, a double-sideband NF of 10 dB with 9-33 kHz 1/f-noise corner. The measured IIP3 is +4 dBm for a 0.1-MHz IF frequency and +10 dBm for a 1-MHz IF frequency.
Abstract A 9 GHz fully digitally controlled oscillator implemented in 65 nm CMOS technology is pr... more Abstract A 9 GHz fully digitally controlled oscillator implemented in 65 nm CMOS technology is presented. This is the first DCO implemented at 9 GHz which covers all transmitter (TX) and receiver (RX) bands of GSM/EDGE and UMTS except Band VII. It covers a coarse ...
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