Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI, 2011
SMECY project is an ambitious European initiative involving 29 partners across 9 countries to ena... more SMECY project is an ambitious European initiative involving 29 partners across 9 countries to enable Europe to have a leader role in multi-core domain by developing new programming technologies enabling the exploitation of architectures offering hundreds of cores. Multi-core technologies will rapidly provide to the parallel computing field improved performance, energy saving and cost reduction and will become of strategic value in winning market share in all areas of embedded systems. Given the need, SMECY lays the focus on targeting programming multi-core architecture for consumer electronics with efficient resources management. The first presentation describes the overall project while the two others are respectively dedicated to the multi-core platforms targeted in the project and the description of the tools constituting the bricks of the tool chains.
Jürgen Becker, University of Karlsruhe, Germany Koen Bertels, Technical University of Delft, Neth... more Jürgen Becker, University of Karlsruhe, Germany Koen Bertels, Technical University of Delft, Netherlands Eduardo Boemo, Universidad Autonoma de Madrid, Spain Peter YK Cheung, Imperial College London, UK Martin Danek, UTIA AV CR, Czech Republic Fabrizio Ferrandi, Politecnico di Milano, Italy Manfred Glesner, Darmstadt University of Technology, Germany John Gray, Independent Consultant, UK Reiner Hartenstein, University of Kaiserslautern, Germany Andres Keevallik, Tallinn Technical University, Estonia Wayne Luk, Imperial College, London, UK Patrick ...
To meet the needs of innovative sensor network applications, sensor nodes have long evolved from ... more To meet the needs of innovative sensor network applications, sensor nodes have long evolved from underpowered single microcontroller designs into complex architectures that accommodate multiple processors and Field Programmable Gate Arrays (FPGAs). We address the problem of conceiving and implementing programs for such sensor node architectures. We rely on a universal, layered hardware/software interface that provides seamless interconnection between tasks running on a micro-controller and tasks running on a FPGA. Resource sharing is handled transparently through a shared-bus communication architecture. We demonstrate our methodology, through a heterogeneous sensor node simulator called SUNSHINE [1] for an application running the sensor nodes. We validate SUNSHINE by demonstrating the applications on a multiprocessor sensor node's testbed, which consists of a FPGA, a microcontroller and a radio front-end.
This paper presents an integrated programming toolset for application implementation on an hetero... more This paper presents an integrated programming toolset for application implementation on an heterogeneous reconfigurable architecture. The objectives of the toolset are to optimize the application implementation productivity and to enable the dynamic reconfiguration on reconfigurable units of the target architecture. The proposed solution is based on the combination of a compilation concept permitting to call function implemented on these reconfigurable units, an operating system dynamically managing the units reconfigurations, a formal specification tool and a design tool for the implementation of the accelerated functions. The paper gives an overview of these tools, that are combined to take benefit of their facilitated reciprocal interactions.
Performance improvement on heterogeneous reconfigurable architectures depends on application anal... more Performance improvement on heterogeneous reconfigurable architectures depends on application analysis for parallel execution. This paper describes a performance analysis methodology for video encoding applications to estimate the expected performance of parallel execution on reconfigurable architectures. We formulate the performance estimation of a video encoding application on a target architecture with an equation. The equation shows the overhead factors that hinder the speed-up of parallel execution.
Although many techniques have been proposed for power reduction in fieldprogrammable devices (FPD... more Although many techniques have been proposed for power reduction in fieldprogrammable devices (FPDs), they are all based on conventional logic elements (LEs). In the conventional LE, the output of the combinational logic (e.g. the lookup table (LUT) in many FPGAs) is connected to the input of the storage element; while the D flip-flop (DFF) is always clocked even when it is not necessary. Such unnecessary transitions waste power. To address this problem, we propose a novel low power LE. The differences between our LE and the conventional LE are in the type of flip-flops used and the internal organization. Instead of using DFFs, we use T flip-flops with the input T permanently connected to logic value one. Instead of connecting the output of the combinational logic to the input of the FF, we connect it to the clock input of the FF. Transistor-level circuit simulations on MCNC benchmark circuits indicate that the FPD using the proposed LEs not only consumes up to 42% less total power by avoiding the unnecessary activities of the clock, logic, and interconnect, but performs up to 33% faster than the FPD using conventional LEs.
ABSTRACT Although various techniques have been proposed for power reduction in field-programmable... more ABSTRACT Although various techniques have been proposed for power reduction in field-programmable devices (FPDs), they are still all based on conventional logic elements (LEs). In the conventional LE, the output of the combinational logic (e.g. the look-up table (LUT) in many field-programmable gate arrays (FPGAs)) is connected to the input of the storage element; while the D flip-flop (DFF) is always clocked even when not necessary. Such unnecessary transitions waste power. To address this problem, we propose a novel productivity-driven LE with reduced number of transitions. The differences between our LE and the conventional LE are in the FFs-type used and the internal LE organisation. In our LEs, DFFs have been replaced by T flip-flops with the T input permanently connected to logic value 1. Instead of connecting the output of the combinational logic to the FF input, we use it as the FF clock. The proposed LE has been validated via Simulation Program with Integrated Circuit Emphasis (SPICE) simulations for a 45-nm Complementary Metal–Oxide–Semiconductor (CMOS) technology as well as via a real Computer-Aided Design (CAD) tools on a real FPGA using the standard Microelectronic Center of North Carolina (MCNC) benchmark circuits. The experimental results show that FPDs using our proposal not only have 48% lower total power but also run 17% faster than conventional FPDs on average.
Because of strong interest in designing audio systems for automobiles, an audio laboratory instal... more Because of strong interest in designing audio systems for automobiles, an audio laboratory installed in a real car has been developed using professional equipment. The proposed method aims to create a foundation for a holistic end-to-end approach for real-time embedded system design (hArtes) using the modern algorithm tools and reconfigurable hardware. Proof-of-concept tests show that the equivalent results are achieved with significantly less time and effort.
2010 5th International Design and Test Workshop, 2010
ABSTRACT Sequence alignment is an essential, but compute-intensive application in Bioinformatics.... more ABSTRACT Sequence alignment is an essential, but compute-intensive application in Bioinformatics. Hardware implementation speeds up this application by exploiting its inherent parallelism, where the performance of the hardware depends on its capability to align long sequences. In hardware terms, the length of a biological query sequence that can be aligned against a database sequence depends on the number of Processing Elements (PEs) available, which in turn depends on the amount of available hardware resources. In addition, the amount of available bandwidth to transfer the data processed by these PEs plays a significant role in defining the maximum performance. In this paper, we carry out a detailed performance and bandwidth analysis for biological sequence alignment and formulate theoretical performance boundaries for various cases. Further, we optimize the performance gain and memory bandwidth requirements and develop generalized equations for this optimization.
2008 3rd International Design and Test Workshop, 2008
In this paper we adapted a novel approach for accelerating the Smith-Waterman (S-W) algorithm usi... more In this paper we adapted a novel approach for accelerating the Smith-Waterman (S-W) algorithm using Recursive Variable Expansion (RVE), which exposes extra parallelism in the algorithm, as compared to any other technique. The results demonstrate that applying the recursive variable expansion technique speeds up the performance by a factor of 1.36 to 1.41, as compared to traditional acceleration approaches at the cost of using 1.25 to 1.28 times more hardware resources.
IFIP International Federation for Information Processing, 2007
The evolution of networks and Internet has introduced highly scalable and available services maki... more The evolution of networks and Internet has introduced highly scalable and available services making operational environments more complex. The increasing complexity, cost and heterogeneity of distributed computing systems have motivated researchers to investigate new ideas to cope with the management of this complexity. One such idea is autonomic computing. This paper provides a thorough survey of autonomic computing systems, presenting their characteristics, effects on quality factors, their building block architecture and challenges.
Biological sequence alignment is one of the most important problems in computational biology. Giv... more Biological sequence alignment is one of the most important problems in computational biology. Given two sequences of varying length are aligned such that the alignment score is maximum. The alignment score is calculated based on the number of matches, mismatches and gaps in the alignment suggested. The basic sequence alignment algorithms are Needleman-Wunsch (NW) algorithm and Smith-Waterman (SW) algorithm, which find the optimal global and local alignment, respectively. In this paper, we have accelerated the Needleman-Wunsch by applying the Recursive Variable Expansion partially, which can be easily implemented on FPGA. This method extract more parallelism than other prevalent parallel implementations and we are able to achieve a speed up of 1.55 times.
The MOLEN Programming Paradigm was proposed to offer a general function like execution of the com... more The MOLEN Programming Paradigm was proposed to offer a general function like execution of the computation intensive parts of the programs on the reconfigurable fabric of the polymorphic computing platforms. Within the MOLEN programming paradigm, the MOLEN SET and EXECUTE primitives are employed to map an arbitrary function on the reconfigurable hardware. However, these instructions in their current status are intended for single application execution scenario. In this paper, we extended the semantic of MOLEN SET and EXECUTE to have a more generalized approach and support multi application, multitasking scenarios. This way, the new SET and EXECUTES are APIs added to the operating system runtime. We use these APIs to abstract the concept of the task from its actual implementation. Our experiments show that the proposed approach has a negligible overhead over the overall applications execution.
Hardware/Software Co-design for Heterogeneous Multi-core Platforms, 2012
ABSTRACT It is clear the that the Multi-core Era has already started some time ago. Multi-core pr... more ABSTRACT It is clear the that the Multi-core Era has already started some time ago. Multi-core processor architectures clearly solve a number of issues related to power dissipation, the frequency wall etc. However, the adoption of the such platforms poses a number of new challenges of which programmability is definitely one of the toughest ones to crack. Even more so because parallelising compilers and parallel programming languages were a hot research topic in the eighties/nineties and no dominant technology or solution has emanated from that effort. Evidently and maybe most importantly because each time the next generation processor, with an ever higher operating frequency and transistor density, provided the necessary performance upgrade needed. With the arrival of the multi-core architectures, we are witnessing a renaissance of the parallel computing and programming paradigm. Where many research initiatives explore the possibility of designing a new language that would provide the necessary constructs and hooks to efficiently exploit the available hardware resources, they usually represent a radical rupture with the past leading to incompatibility between the existing code base and the latest programming languages. And exactly this incompatibility may turn out to be the show-stopper for many of those emerging approaches. Especially in the Embedded Systems industry, applications tend to have life span covering decades during which period both software and hardware have to be maintained and upgraded when necessary.
Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI, 2011
SMECY project is an ambitious European initiative involving 29 partners across 9 countries to ena... more SMECY project is an ambitious European initiative involving 29 partners across 9 countries to enable Europe to have a leader role in multi-core domain by developing new programming technologies enabling the exploitation of architectures offering hundreds of cores. Multi-core technologies will rapidly provide to the parallel computing field improved performance, energy saving and cost reduction and will become of strategic value in winning market share in all areas of embedded systems. Given the need, SMECY lays the focus on targeting programming multi-core architecture for consumer electronics with efficient resources management. The first presentation describes the overall project while the two others are respectively dedicated to the multi-core platforms targeted in the project and the description of the tools constituting the bricks of the tool chains.
Jürgen Becker, University of Karlsruhe, Germany Koen Bertels, Technical University of Delft, Neth... more Jürgen Becker, University of Karlsruhe, Germany Koen Bertels, Technical University of Delft, Netherlands Eduardo Boemo, Universidad Autonoma de Madrid, Spain Peter YK Cheung, Imperial College London, UK Martin Danek, UTIA AV CR, Czech Republic Fabrizio Ferrandi, Politecnico di Milano, Italy Manfred Glesner, Darmstadt University of Technology, Germany John Gray, Independent Consultant, UK Reiner Hartenstein, University of Kaiserslautern, Germany Andres Keevallik, Tallinn Technical University, Estonia Wayne Luk, Imperial College, London, UK Patrick ...
To meet the needs of innovative sensor network applications, sensor nodes have long evolved from ... more To meet the needs of innovative sensor network applications, sensor nodes have long evolved from underpowered single microcontroller designs into complex architectures that accommodate multiple processors and Field Programmable Gate Arrays (FPGAs). We address the problem of conceiving and implementing programs for such sensor node architectures. We rely on a universal, layered hardware/software interface that provides seamless interconnection between tasks running on a micro-controller and tasks running on a FPGA. Resource sharing is handled transparently through a shared-bus communication architecture. We demonstrate our methodology, through a heterogeneous sensor node simulator called SUNSHINE [1] for an application running the sensor nodes. We validate SUNSHINE by demonstrating the applications on a multiprocessor sensor node's testbed, which consists of a FPGA, a microcontroller and a radio front-end.
This paper presents an integrated programming toolset for application implementation on an hetero... more This paper presents an integrated programming toolset for application implementation on an heterogeneous reconfigurable architecture. The objectives of the toolset are to optimize the application implementation productivity and to enable the dynamic reconfiguration on reconfigurable units of the target architecture. The proposed solution is based on the combination of a compilation concept permitting to call function implemented on these reconfigurable units, an operating system dynamically managing the units reconfigurations, a formal specification tool and a design tool for the implementation of the accelerated functions. The paper gives an overview of these tools, that are combined to take benefit of their facilitated reciprocal interactions.
Performance improvement on heterogeneous reconfigurable architectures depends on application anal... more Performance improvement on heterogeneous reconfigurable architectures depends on application analysis for parallel execution. This paper describes a performance analysis methodology for video encoding applications to estimate the expected performance of parallel execution on reconfigurable architectures. We formulate the performance estimation of a video encoding application on a target architecture with an equation. The equation shows the overhead factors that hinder the speed-up of parallel execution.
Although many techniques have been proposed for power reduction in fieldprogrammable devices (FPD... more Although many techniques have been proposed for power reduction in fieldprogrammable devices (FPDs), they are all based on conventional logic elements (LEs). In the conventional LE, the output of the combinational logic (e.g. the lookup table (LUT) in many FPGAs) is connected to the input of the storage element; while the D flip-flop (DFF) is always clocked even when it is not necessary. Such unnecessary transitions waste power. To address this problem, we propose a novel low power LE. The differences between our LE and the conventional LE are in the type of flip-flops used and the internal organization. Instead of using DFFs, we use T flip-flops with the input T permanently connected to logic value one. Instead of connecting the output of the combinational logic to the input of the FF, we connect it to the clock input of the FF. Transistor-level circuit simulations on MCNC benchmark circuits indicate that the FPD using the proposed LEs not only consumes up to 42% less total power by avoiding the unnecessary activities of the clock, logic, and interconnect, but performs up to 33% faster than the FPD using conventional LEs.
ABSTRACT Although various techniques have been proposed for power reduction in field-programmable... more ABSTRACT Although various techniques have been proposed for power reduction in field-programmable devices (FPDs), they are still all based on conventional logic elements (LEs). In the conventional LE, the output of the combinational logic (e.g. the look-up table (LUT) in many field-programmable gate arrays (FPGAs)) is connected to the input of the storage element; while the D flip-flop (DFF) is always clocked even when not necessary. Such unnecessary transitions waste power. To address this problem, we propose a novel productivity-driven LE with reduced number of transitions. The differences between our LE and the conventional LE are in the FFs-type used and the internal LE organisation. In our LEs, DFFs have been replaced by T flip-flops with the T input permanently connected to logic value 1. Instead of connecting the output of the combinational logic to the FF input, we use it as the FF clock. The proposed LE has been validated via Simulation Program with Integrated Circuit Emphasis (SPICE) simulations for a 45-nm Complementary Metal–Oxide–Semiconductor (CMOS) technology as well as via a real Computer-Aided Design (CAD) tools on a real FPGA using the standard Microelectronic Center of North Carolina (MCNC) benchmark circuits. The experimental results show that FPDs using our proposal not only have 48% lower total power but also run 17% faster than conventional FPDs on average.
Because of strong interest in designing audio systems for automobiles, an audio laboratory instal... more Because of strong interest in designing audio systems for automobiles, an audio laboratory installed in a real car has been developed using professional equipment. The proposed method aims to create a foundation for a holistic end-to-end approach for real-time embedded system design (hArtes) using the modern algorithm tools and reconfigurable hardware. Proof-of-concept tests show that the equivalent results are achieved with significantly less time and effort.
2010 5th International Design and Test Workshop, 2010
ABSTRACT Sequence alignment is an essential, but compute-intensive application in Bioinformatics.... more ABSTRACT Sequence alignment is an essential, but compute-intensive application in Bioinformatics. Hardware implementation speeds up this application by exploiting its inherent parallelism, where the performance of the hardware depends on its capability to align long sequences. In hardware terms, the length of a biological query sequence that can be aligned against a database sequence depends on the number of Processing Elements (PEs) available, which in turn depends on the amount of available hardware resources. In addition, the amount of available bandwidth to transfer the data processed by these PEs plays a significant role in defining the maximum performance. In this paper, we carry out a detailed performance and bandwidth analysis for biological sequence alignment and formulate theoretical performance boundaries for various cases. Further, we optimize the performance gain and memory bandwidth requirements and develop generalized equations for this optimization.
2008 3rd International Design and Test Workshop, 2008
In this paper we adapted a novel approach for accelerating the Smith-Waterman (S-W) algorithm usi... more In this paper we adapted a novel approach for accelerating the Smith-Waterman (S-W) algorithm using Recursive Variable Expansion (RVE), which exposes extra parallelism in the algorithm, as compared to any other technique. The results demonstrate that applying the recursive variable expansion technique speeds up the performance by a factor of 1.36 to 1.41, as compared to traditional acceleration approaches at the cost of using 1.25 to 1.28 times more hardware resources.
IFIP International Federation for Information Processing, 2007
The evolution of networks and Internet has introduced highly scalable and available services maki... more The evolution of networks and Internet has introduced highly scalable and available services making operational environments more complex. The increasing complexity, cost and heterogeneity of distributed computing systems have motivated researchers to investigate new ideas to cope with the management of this complexity. One such idea is autonomic computing. This paper provides a thorough survey of autonomic computing systems, presenting their characteristics, effects on quality factors, their building block architecture and challenges.
Biological sequence alignment is one of the most important problems in computational biology. Giv... more Biological sequence alignment is one of the most important problems in computational biology. Given two sequences of varying length are aligned such that the alignment score is maximum. The alignment score is calculated based on the number of matches, mismatches and gaps in the alignment suggested. The basic sequence alignment algorithms are Needleman-Wunsch (NW) algorithm and Smith-Waterman (SW) algorithm, which find the optimal global and local alignment, respectively. In this paper, we have accelerated the Needleman-Wunsch by applying the Recursive Variable Expansion partially, which can be easily implemented on FPGA. This method extract more parallelism than other prevalent parallel implementations and we are able to achieve a speed up of 1.55 times.
The MOLEN Programming Paradigm was proposed to offer a general function like execution of the com... more The MOLEN Programming Paradigm was proposed to offer a general function like execution of the computation intensive parts of the programs on the reconfigurable fabric of the polymorphic computing platforms. Within the MOLEN programming paradigm, the MOLEN SET and EXECUTE primitives are employed to map an arbitrary function on the reconfigurable hardware. However, these instructions in their current status are intended for single application execution scenario. In this paper, we extended the semantic of MOLEN SET and EXECUTE to have a more generalized approach and support multi application, multitasking scenarios. This way, the new SET and EXECUTES are APIs added to the operating system runtime. We use these APIs to abstract the concept of the task from its actual implementation. Our experiments show that the proposed approach has a negligible overhead over the overall applications execution.
Hardware/Software Co-design for Heterogeneous Multi-core Platforms, 2012
ABSTRACT It is clear the that the Multi-core Era has already started some time ago. Multi-core pr... more ABSTRACT It is clear the that the Multi-core Era has already started some time ago. Multi-core processor architectures clearly solve a number of issues related to power dissipation, the frequency wall etc. However, the adoption of the such platforms poses a number of new challenges of which programmability is definitely one of the toughest ones to crack. Even more so because parallelising compilers and parallel programming languages were a hot research topic in the eighties/nineties and no dominant technology or solution has emanated from that effort. Evidently and maybe most importantly because each time the next generation processor, with an ever higher operating frequency and transistor density, provided the necessary performance upgrade needed. With the arrival of the multi-core architectures, we are witnessing a renaissance of the parallel computing and programming paradigm. Where many research initiatives explore the possibility of designing a new language that would provide the necessary constructs and hooks to efficiently exploit the available hardware resources, they usually represent a radical rupture with the past leading to incompatibility between the existing code base and the latest programming languages. And exactly this incompatibility may turn out to be the show-stopper for many of those emerging approaches. Especially in the Embedded Systems industry, applications tend to have life span covering decades during which period both software and hardware have to be maintained and upgraded when necessary.
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Papers by Koen Bertels