A mixed-mode esd protection circuit simulation-design methodology

IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 38, NO. 6, JUNE 2003 995 A Mixed-Mode ESD Protection Circuit Simulation-Design Methodology Haigang Feng, Student Member, IEEE, Guang Chen, Rouying Zhan, Qiong Wu, Xiaokang Guan, Haolu Xie, Albert Z. H. Wang, Senior Member, IEEE, and Roman Gafiteanu Abstract—On-chip electrostatic discharge (ESD) protection design becomes a major design challenge as IC technologies continue to migrate into very-deep-submicron (VDSM) regime. However, trial-and-error approaches still dominate in ESD protection circuit design. This paper discusses a new mixed-mode ESD protection simulation-design methodology, aiming to design prediction, which involves multiple-level coupling in ESD protection simulation by solving complex electrothermal equations self-consistently at process, device, and circuit levels in a coupled fashion to investigate ESD protection circuit details without any pre-assumption. Practical ESD protection design examples, implemented in commercial 0.18/0.35- m CMOS and BiCMOS processes, are presented. Index Terms—BiCMOS, CMOS, electrostatic discharge (ESD) protection, mixed-mode, mixed-signal, NMOS. Fig. 1. Typical ESD protection scheme. I. INTRODUCTION A. Electrostatic Discharge (ESD) Failure Problem T HE ESD phenomenon originates from transfer of electrostatic charges between two objects of different electrical potentials, which results in damage to integrated circuit (IC) parts due to large energy dissipation in an extremely short time of less than 150 ns. It is reported that up to 35% of all IC field failures are associated with ESD damages [1], [2]. Common ESD failures are catastrophic, leading to immediate malfunction of IC chips caused by either thermal breakdown in silicon and/or metal interconnects due to high current transients or dielectric breakdown in gate oxide due to high voltage overstress. Therefore, dedicated on-chip ESD protection circuits are required to protect IC chips against ESD damages. With continuous scaling down in IC technologies, on-chip ESD protection design becomes a major challenge in IC design. Unfortunately, trial-and-error approaches still dominate in current ESD protection design practices that are extremely time consuming and costly. A rational simulation-based ESD design methodology is, therefore, highly desirable. B. On-Chip ESD Protection On-chip ESD protection structures are needed to protect IC chips against ESD pulses of all types. The principle of Manuscript received September 27, 2002; revised February 6, 2003. This work was supported in part by the National Science Foundation under Grant ECS-0132869. H. Feng, G. Chen, R. Zhan, Q. Wu, X. Guan, H. Xie, and A. Z. H. Wang are with the Integrated Electronics Laboratory, Department of Electrical and Computer Engineering, Illinois Institute of Technology, Chicago, IL 60616 USA (e-mail: awang@ece.iit.edu). R. Gafiteanu is with Synopsys Inc., Mountain View, CA 94043 USA. Digital Object Identifier 10.1109/JSSC.2003.811978 Fig. 2. Typical snapback I –V characteristic for ESD protection structure. Critical features include triggering, holding, second breakdown, and lowimpedance discharging. ESD protection is twofold: to provide active low-impedance discharging paths to shunt high ESD currents safely and to clamp pad voltage to a sufficiently low level to avoid dielectric breakdown. Pad voltage clamping also serves to avoid accidental turn-on of internal devices. Generally, an ESD protection structure acts as a two-terminal device connected between an I/O pad and a power supply, as shown in Fig. 1, which remains in off state in normal operation. Typical on-chip ESD protection devices are diodes, grounded-gate NMOS/PMOS (ggNMOS/ggPMOS), and silicon-controlled rectifiers (SCRs). Fig. 2 illustrates a typical snapback – characteristic of an ESD protection structure. Under ESD stresses, the terminal voltage increases gradually until reaching its trigger threshold ( , ) at a trigger time ( ), then snaps back into a holding ) shunting point ( , ) and creates a low-impedance ( 0018-9200/03$17.00 © 2003 IEEE 996 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 38, NO. 6, JUNE 2003 Fig. 5. Fig. 3. Typical ESD stressing modes at I/O pad. Typical HBM ESD discharging waveform. charged up and then discharges, through a human body resistor ) and a discharging inductor ( H) ( network, into the device under test (DUT). Fig. 5 shows a typical HBM ESD discharging current waveform under 2000-V HBM stress. D. ESD Protection Design Challenge Fig. 4. Simplified HBM ESD model circuit. path to discharge ESD transients safely. After the ESD pulse is over, the ESD protection device will be turned off automatically to avoid latch-up. ESD protection level is determined by its ). The goal of ESD second breakdown threshold ( , protection circuit design is to precisely define the above critical operational parameters and to provide ESD design prediction, which may only be done by performing mixed-mode ESD simulation. C. ESD Stress and Test Models Fig. 3 illustrates the five typical ESD stressing modes usually positively/negatively experienced by IC chips, e.g., I/O-topositively/negatively (PS and ND), (PD and ND), I/O-to-to(DS). Basically, one active ESD protection and unit is needed to form an active low-impedance conducting path to safely discharge ESD pulse of each mode and to clamp the I/O pad voltage to a sufficiently low level. A well-designed full chip ESD protection scheme should be able to protect ICs against all these five types of ESD stresses. Apparently, should this ideal ESD protection scheme be adopted, a large number of ESD protection devices may be needed, particularly for high-pin-count chips, resulting in significant silicon consumption and ESD-induced parasitic effects that must be addressed in design phase. Hence, an efficient ESD simulation-design approach is highly desirable for designers to explore novel protection structures and to conduct predictive ESD protection design to meet the tremendous design challenges. Existing ESD testing models include human body model (HBM), machine model (MM), charged device model (CDM), and IEC (International Electrotechnical Commission) model. The widely accepted HBM model simulates ESD events occurring as a charged human body contacts an electronic part directly, with its equivalent circuit shown in Fig. 4, pF) is where human-body-related capacitance ( A good on-chip ESD protection structure should feature the following characteristics: 1) fast triggering to avoid premature ESD failure due to accidental turn-on of competing internal parasitic structure; 2) high current handling capability, good heat dissipation capability, and low discharging impedance to boost the ESD robustness; and 3) low parasitic effects to minimize negative impacts on core circuits. All these ESD features are critical to ESD protection design evaluation, which, unfortunately, cannot be characterized by using existing trial-and-error design approaches. Since ESD phenomena involve multiple-level coupling effects (i.e., electro-thermal-process-device-circuit-layout) and are device physics related, a mixed-mode approach must be used in ESD protection circuit design. This concept becomes even more critical to very-deep-submicron (VDSM) IC technologies where coupling effects dominate. The major challenge is to investigate ESD protection using a mixed-mode ESD simulation approach that accounts for the electro-thermal-process-device-circuit-layout coupling effects. Because of its complicated coupling effects, the procedure should integrate numerical simulation (i.e., TCAD process and device simulation) with circuit simulation (i.e., ECAD). This paper is organized as follows. After a brief introduction to ESD protection concepts in Section I, Section II discusses the new mixed-mode ESD simulation-design methodology. Section III presents a few practical design examples to demonstrate the new methodology, followed by conclusions in Section IV. II. MIXED-MODE ESD SIMULATION-DESIGN METHODOLOGY Fig. 6 illustrates the traditional experience-based trial-anderror ESD protection design approach where real ESD protection design begins with partial and independent simulation at either device level or circuit level, followed by intensive testing, debugging, and design iterations. It is a very costly and time-consuming ESD design procedure. Our new mixed-mode ESD protection simulation-design methodology resolves this problem and provides design prediction. Fig. 7 is a flow chart FENG et al.: MIXED-MODE ESD PROTECTION CIRCUIT 997 Fig. 6. Flow chart for traditional trial-and-error ESD design approach that features design iterations and limited simulation. of the mixed-mode ESD simulation-design methodology that consists of the following steps. The first step is to define ESD design specifications that include the following parameters as illustrated in Fig. 2: the trigger voltage and current ( , ), the trigger time ( ), the holding voltage and current ( , ), and the thermal breakdown voltage and current ( , ). is typically set to be around 110% of the power supply to ensure enough safety margins in order to avoid the ESD protection structure being mistriggered by may delay ESD triggering non-ESD signals. Too high a and cause early ESD failures. is typically related to junction breakdown voltage. The trigger time should be significantly shorter than the rising time of the ESD pulse to ensure prompt turn-on of the ESD protection structure under ESD is the starting point of low-impedance ESD disstressing. charging process and should be low enough to ensure sufficient voltage clamping in order to avoid dielectric breakdown and to prevent accidental triggering of internal devices. plays a role in eliminating post-ESD latch-up. should be greater than in multifinger ESD protection design to ensure uniform trigdetermines the ESD protection level (comgering [3], [4]. monly labeled as ESDV). For example, referring to the HBM of 1.33 A corresponds to an ESDV of about model in Fig. 4, 2 kV, as given by ESDV (1) of the DUT is ignorable compared with assuming the . human body resistance of The second step is to select initial possible ESD protection structures according to process features and core circuit specifications. These may be common ESD protection structures such as diodes, ggNMOS, gcNMOS (gate-coupled NMOS), SCRs, etc. The third step is to generate ESD protection structures by process simulation. A commercial TCAD tool, TSUPREM4 [5], was used in this paper, which solves process model equations at each node of the device mesh and produces detailed impurity doping profiles. As an example, Fig. 8 shows the generated Fig. 7. Flow chart for the mixed-mode ESD simulation methodology featuring comprehensive pre-Si ESD simulation and enabling design prediction. mesh of a ggNMOS ESD protection structure made of p-well, n source (left) and drain (right) diffusions, poly gate, dielectric regions, metal interconnect, and a body pick-up doping at the left. Running process simulation to generate the ESD devices is critical because many process features may have significant influences on performance of the ESD protection structures. For instance, the drain contact to gate spacing (DCGS) spacing of the ggNMOS structure must be optimized for better ESD performance. The fourth step is to conduct mixed-mode ESD simulation at the device circuit level, which is the core of the new design methodology. The novelty of this new ESD simulation approach lies in its non-assumption and mixed-mode features that include both static and transient simulation as indicated by its simulation schematics shown in Fig. 9, where a proper ESD model circuit, e.g., an HBM model, instead of any artificial waveforms, is used to produce real-world ESD pulses to stress the ESD protection structure (DUT) in simulations. This approach can automatically locate heating sources in numerical simulation, without making any assumption [6]. The key feature of the new mixed-mode ESD simulation-design methodology is that the complex electrothermal equations are solved self-consistently at process, device, and circuit levels in a coupled fashion in simulating ESD protection circuit behaviors. These include process 998 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 38, NO. 6, JUNE 2003 Fig. 8. Sample 2-D mesh plot of a ggNMOS ESD protection structure with body pick-up generated by process simulation. and (6) , (cm /s) are electron and hole generation rates where caused by external influence such as the optical excitation with high-energy photons or impact ionization under large electric and are electron and hole recombination rate in fields. and are the p- and n-type semiconductors, respectively. electron and hole current densities given by (7) Fig. 9. Sample mixed-mode ESD simulation schematic. and simulation as discussed previously, various device physics equations, and Kirchhoff circuit equations, listed later. The thermal equation for heat distribution is (8) and are mobility of electron and hole, respectively. where Kirchhoff circuit equations: (2) number of paths at one node where is the mass density (g/cm ), is the specific heat is the heat generation term (W/cm ), and is the (J/g K), thermal conductivity of the material (W/cm K). Poisson’s equation for intrinsic Fermi potential is (3) where is electrostatic potential, is electron charge, and is conduction-band energy. However, (3) is not applicable since the lattice temperature is not spatially constant. A revised equation is used instead: (4) where is permittivity, and are carrier concentrations, and are ionized impurity concentrations, is fixed-charge density, and is band structure parameter for the material. Continuity equations: (5) (9) and number of branches in a closed loop (10) Lattice temperature distribution in ESD devices as well as the distributions of potential and carrier concentrations will be obtained as results of the simulation. A commercial TCAD tool, Medici [7], is used. As output, the two-dimensional (2-D) distributions of potential and carrier concentrations in a device could be modeled. The ESD simulation can be performed as both steady-static simulation and transient simulation. The two ESD failure criteria used in our design methodology are associated with dielectric breakdown and thermal melting. The dielectric rupture is monitored by examining whether a gate exceeds its breakdown voltage level . While the voltage thermal failure is studied by monitoring the hot spots in the ESD ). If structures (i.e., maximum lattice temperature FENG et al.: MIXED-MODE ESD PROTECTION CIRCUIT 999 TABLE I CRITICAL MATERIAL PARAMETERS USED IN MIXED-MODE ESD SIMULATION Fig. 10. V =J DCGS curves for a ggNMOS protection structure from steady-static simulation. at any location exceeds the known material melting point of either silicon or metal, as listed in Table I, ESD thermal failure occurs. Steady-static simulation can be done by performing dc sweeping and provides a rough time-independent characterization of ESD protection behaviors. Calibration to steady-static simulation can be done by comparing with quasi-dc curve tracing measurement data. Results from steady-static sweeping simulation usually do not correspond well to real ESD protection characteristics because a real ESD stressing is a transient event that must be evaluated in time domain. However, the trends obtained from steady-static simulation offer insightful information to early-stage design and are fairly reliable. For instance, the trend for variation of trigger voltage and thermal breakdown current versus physical layout dimensions, e.g., DCGS, source contact to gate spacing (SCGS), or body pick-up edge to source edge spacing (BESS) in ggNMOS can be studied by performing steady-static ESD simulation. Fig. 10 versus DCGS study in a 0.35- m demonstrates an CMOS ESD design. A gradual saturation trend of DCGS is clearly observed, which suggests an optimized DCGS value of around 5 m in ggNMOS ESD structure as reported in many experimental studies [8]. In another example, steady-static ESD simulation clearly illustrates the troublesome hot spot location in a ggNMOS structure as shown in Fig. 11, which is of great value in guiding designers to optimize ESD protection design by relocating the hot spot in order to achieve higher ESD protection level. Though simple and very useful, application of steady-static ESD simulation is rather limited because of its dc nature that is different from any transient real ESD event. Transient ESD simulation is therefore required in practical design. In transient ESD simulation, an ESD equivalent model subcircuit is used to generate real ESD pulse to stress an ESD protection subcircuit as shown in Fig. 9. Both single ESD protection structure and simple ESD protection circuit can be simulated in transient ESD simulation. In addition, part of the core circuit protected may also be included in transient simula- 1000 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 38, NO. 6, JUNE 2003 Fig. 11. 2-D lattice temperature contour for a ggNMOS protection structure from ESD simulation illustrates the possible hot-spot defect location. = Fig. 12. I –V curve for the ggNMOS structure (W 80 m, L = 0:4 m, DCGS = 5 m, SCGS = 0.4 m, BSES = 0.8 m) from transient ESD simulation when it passes 2-kV HBM ESD stressing. tion for more accurate study. In an example study of a ggNMOS ESD protection structure in a 0.35- m CMOS, instantaneous – characteristics of the ggNMOS structure under 2000-V HBM ESD stressing are investigated using the transient ESD simulation. Fig. 12 shows the – curve where the ggNMOS passed the 2-kV HBM ESD stressing, which covers the whole ESD pulse cycle, including both the rising and falling portions of the ESD pulse. Fig. 13 shows the – characteristic in a case where the ggNMOS failed the 2-kV HBM stressing, in which a broken – curve is observed that corresponds thermal breakdown in ggNMOS. It is noteworthy to point out that the does not occur concurrently with the peak current due to the heat accumulation and dissipation procedure. According to the failure criteria, whenever the thermal monitor detected a exceeding the melting temperature in simulation, it stops ESD simulation automatically and reports an ESD failure. The fifth step is simulation calibration, which is one of the most complicated yet most critical steps in mixed-mode ESD simulation that includes both process calibration and device characteristic calibration. Process calibrations focus on the parameters related to IC processes, such as doping profiles and voltage threshold values. Device characteristic calibrations Fig. 13. I –V Curve for the ggNMOS structure (W = 70 m, L = 0:4 m, DCGS = 5 m, SCGS = 0.4 m, BSES = 0.8 m) from transient ESD simulation as it fails 2-kV HBM ESD stressing. are made by comparing steady-static and transient simulation results with related testing data performed using curve tracer, transmission line pulsing (TLP) tester, and ESD zapping tester. The main calibration covers mobility model parameters, material parameters, and thermal coefficients. Mobility model and , calibrations will fit the carrier mobility values, accounting for scattering mechanisms in carrier transport, as described in equations (7) and (8). Material parameter calibrations associate physical parameters with the materials in the device structure, including semiconductor parameters, energy balance equation parameters, lattice temperature model parameters, etc. ESD-related models, such as recombination model and impact ionization model, will be calibrated in this step. Calibrating the impact ionization coefficients is a critical step in ESD device characteristic calibrations. To ensure accurate simulation, different ESD protection structures require different calibration parameter set due to different triggering mechanisms. For example, an ESD diode structure triggers based upon p-n junction breakdown, hence, requires use of impact ionization data that fits p-n junction breakdown testing data well. Through manipulating the thermal coefficients, such as thermal boundary condition, the ESD operation region and FENG et al.: MIXED-MODE ESD PROTECTION CIRCUIT 1001 Fig. 14. Universal ESD testing diagram includes curve tracer testing, TLP testing, and ESD zapping test. thermal breakdown point in – curve could be calibrated properly. The sixth step is to generate ESD test patterns including both ESD protection structures and core circuit layout cells for testing and calibration purpose. Generally, these ESD test structures should be as simple as possible in order to ensure reliable calibration to ESD simulation. The last step is to perform complete ESD testing. Full ESD simulation calibration can only be conducted when the fabricated ESD test structures are available for testing. For example, by calibrating junction breakdown voltage, snapback – curve, – curve, etc., the electrical characteristic calibration will be accomplished. ESD simulation calibration is performed by matching ESD simulation results with ESD measurement data. Three types of ESD measurements are involved with a universal test setup illustrated in Fig. 14 that includes quasi-dc (Tektronix 370 curve tracer), TLP (TLP 4002 tester), and ESD zapping (IMCS 10 000 model) testing. Curve , , and tracers are used to collect dc parameters (e.g., ) that will be matched with steady-static ESD simulation , , , , , results. The transient parameters ( , ) are collected by conducting TLP tests that provide and insights into both thermal failure threshold and instantaneous – characteristics. Compared with ESD zapping, TLP test is quasi-nondestructive due to the short duration of TLP pulses . These transient that allows recovery after reaching to testing data will be calibrated with transient ESD simulation results. The final ESD protection level is evaluated by performing ESD zapping tests. III. DESIGN EXAMPLES In this section, practical ESD protection design examples using the new mixed-mode ESD simulation-design methodology are described. These examples show the advantages and flexibility of using the mixed-mode ESD simulation for design prediction in practical ESD protection circuit design. A. Full-Chip ESD Protection Circuit Design in CMOS As the first example, a full-chip ESD protection solution was developed for a commercial 0.35- m 3.3-V CMOS technology. The starting point was an original gcNMOS ESD protection m/0.35 m for 1000-V structure with a size of HBM ESD protection, designed by using the trial-and-error method. The design goal was to shrink the gcNMOS size, to predict ESD performance and to evaluate ESD performance at full-chip level. First, mixed-mode ESD simulation was (a) (b) Fig. 15. Schematics for a full-chip ESD protection circuit example. (a) Original two-stage internal inverter of concern plus the ESD power clamp. (b) Its equivalent circuit with low logic input. performed to verify the gcNMOS behaviors and its size was m/0.35 m that, however, successfully reduced to achieves a 2000-V HBM ESD protection. Next, mixed-mode ESD simulation was conducted to investigate a special circuit operation case, where a small internal two-stage inverter logic m/0.35 m and circuit block, with a PMOS of m/0.35 m, is placed nearby the an NMOS of gcNMOS power clamp, as shown in Fig. 15(a). When the input pin sees a logic “0” signal, its equivalent circuit is given by Fig. 15(b), since nmos2 is in off state while pmos2 acts as an active resistor. The concern is that when an ESD pulse stresses the power rail, will the gate voltage of nmos1, (5), exceed the gate breakdown voltage that was given as 8 V as typical and 7 V as minimum for the 0.35- m CMOS used, hence, resulting gate dielectric failure in the core circuit? Ideally, the gate voltage of nmos1, (5), should be clamped at below 7 V in order to avoid (5) is probed in mixed-mode any gate ESD damage. The ESD simulation. Fig. 16 shows the – characteristics for both , and (5) of the nmos1, the gcNMOS power clamp denoted as . It is observed that of the nmos1 is indeed lower than the gate breakdown of 8 V. However, in a briefly exceeds very brief period of less than 1 ns, the minimum gate breakdown of 7 V by a fraction of 1 V. It would lower than 7 V, which be perfect if one could ensure a is not the case in this design. However, fortunately, data from (5) lifetime analysis suggests that this brief overshoot in does not cause failure in application. On the other hand, the 1002 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 38, NO. 6, JUNE 2003  Fig. 16. V t curves from full-chip transient ESD simulation for the circuit shown in Fig. 15 where voltage at V (5) node. Fig. 17. T as designed. V - is the power rail voltage and V - is the t characteristics for each individual transistors in the circuit of Fig. 15 show that the ESD power clamp unit is the main ESD discharging device curves obtained for all MOSFETs involved, as shown in Fig. 17, clearly show that significant temperature increase only occurs in the gcNMOS power clamp as it should be, while all other MOSFETs almost remain in room temperature operation during the ESD stressing period. Therefore, mixed-mode ESD simulation confirms successful full-chip ESD protection in this design. HBM zapping test shows that the individually m/0.35 m achieves optimized gcNMOS clamp of 2500-V HBM ESD protection stressing level. B. ESD Simulation Including Metal Interconnects The second example is an ESD protection design implemented in a 0.18- m six-metal commercial CMOS with both aluminum and copper interconnects, where mixed-mode ESD simulation was performed for not only silicon semiconductor, but also metal interconnects, which have never been involved in ESD simulation before. First, individual metal line behaviors under ESD stresses are investigated by mixed-mode ESD simulation. Fig. 18 shows a simulated metal line structure example, 20- m long and 0.3- m thick, which is sandwiched between different interlayer dielectrics (ILD) to mimic the real-world thermal distribution situation. Table I lists the critical material parameters [9], [10] used in simulation. ESD simulation for both Cu and Al metal lines were performed under 2- and 4-kV ESD stressing by applying was the ESD pulses across its two opposite electrodes. The extracted and compared with the melting temperature of the metals to decide whether the metal lines pass or fail the ESD stresses. The important observations from the simulation are as follows. 1) The metal linewidth needed is much narrower than 20 m for 2 kV, commonly used in practical design without ESD simulation, which seems to be an over-conservative design rule. 2) For the same ESD protection level, copper interconnects are more ESD robust than aluminum, showing either an increase in maximum sustainable current density ( 30%) or a reduction in width ( 30%). Therefore, much narrower metals can be used for same ESD protection when using Cu interconnects than using Al. The significance of the earlier observations is FENG et al.: MIXED-MODE ESD PROTECTION CIRCUIT Fig. 18. 1003 Simulation study of a sample single metal line sandwich structure under ESD stressing. (a) The sandwich structure created. (b) Current flow. Fig. 19. Maximum sustainable current per width versus metal linewidth data from simulation and measurements for all six metal layers in the 0.18-m CMOS studied. that mixed-mode ESD simulation ensures that only adequate, e.g., narrow metal interconnects, are used in practical ESD protection design, resulting in much less ESD-induced parasitic capacitance effect. A group of metal line test patterns with 3, 5, 7, 10, 14, 16, and 20 specially tailored linewidths ( m) was designed for all Cu metal layers (M1–M6) to verify the simulation results. TLP tests were conducted for these Cu metal line test patterns. Fig. 19 shows the maximum sustainable current per linewidth (representing ESDV) versus Cu metal width from both simulation and measurements. It is found that simulation agrees with measurements reasonably well within a factor of about two, which can be addressed in calibration, for all six metal layers across a broad range of linewidth. This indicates that the mixed-mode ESD simulation method used in this study works properly. After individual metal line simulation, complete ESD protection structures including both metal lines and Si structure were simulated to study performance of a real-world ESD protection structure, as shown in Fig. 20 for a complete data for ggNMOS ESD structure. During ESD stressing, reaches both silicon and metals are extracted. Whichever the melting point first will cause the ESD protection structure failure. Fig. 20 shows an example temperature contour from simulation, which clearly demonstrates the self-heating effect occurring both in silicon near the drain channel and in metals. Fig. 20. Simulated temperature contour shows possible thermal defects in both metal interconnect and Si channel. This example shows that the new mixed-mode ESD simulation approach provides useful insights for IC designers to optimize ESD protection design at whole chip scale, hence, realizing ESD protection design prediction. C. ESD Protection Circuit Design in BiCMOS The third practical design example is an output ESD protection circuit in a commercial 0.35- m BiCMOS. Fig. 21(a) 1004 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 38, NO. 6, JUNE 2003 (a) (b) Fig. 21. Schematics for an output ESD protection circuit in BiCMOS. (a) Full schematic. (b) Simplified circuit for ESD simulation. Fig. 22. Simulated I t characteristics under a 5-kV HBM ESD stress shows that almost all ESD current discharges into the SCR ESD protection structure.   Fig. 23. Simulated T t curves shows that the lattice temperature increases in the SCR ESD protection structure only during the ESD stress, while all internal transistors remain at room temperature. shows the simplified topology, which is a typical open-collector differential output stage with SCR-type ESD protection structures connected at the output pads. The ESD protection level was targeted at 5-kV HBM. Mixed-mode ESD simulation was conducted to optimize the SCR ESD protection structures, resulting in a minimized device size of 27- m wide for the SCRs. Next, mixed-mode simulation was performed to verify that the full circuit works under ESD stressing. One special design concern was whether these small-size internal transistors (M1–M3, 4- m wide) might be damaged under an ESD stress even though SCR ESD protection devices are used. Mixed-mode simulation was conducted using a simplified circuit as shown in Fig. 21(b) to investigate this design concern. Fig. 22 shows the currents flowing through the internal M1 and M2, as well as the SCR ESD device, which clearly show that almost all ESD current flows into the SCR ESD protection curves for all device upon triggering. Fig. 23 gives the the devices under a 5-kV HBM ESD stress, indicating that M1 FENG et al.: MIXED-MODE ESD PROTECTION CIRCUIT 1005 and M1 remain at room temperature while the SCR was heated up due to large ESD current conduction. The simulation results confirmed that this output ESD protection circuit operates well under the 5-kV HBM ESD stress and the design was successful. Guang Chen received the B.S. degree in electrical engineering from Tsinghua University, Beijing, China, in 1999. He is currently working toward the M.S. degree in the Department of Electrical and Computer Engineering, Illinois Institute of Technology, Chicago. His research covers RFIC design and RF ESD protection design. IV. CONCLUSION This paper discusses a new mixed-mode ESD protection simulation-design methodology that allows IC designers to predict ESD protection circuit performance in early design phase. The mixed-mode design approach involves multiple-level coupling in ESD protection simulation by solving complex electrothermal equations self-consistently at process, device, and circuit levels in a coupled fashion to investigate ESD protection circuit behaviors without any pre-assumption. Several practical ESD protection design examples, implemented in commercial 0.18/0.35- m CMOS and BiCMOS technologies, are presented to demonstrate the usefulness of this mixed-mode ESD simulation methodology. This new design approach, used properly, allows IC designers to conduct predictive ESD protection design that delivers adequate ESD protection while suppresses ESD-induced parasitic effects, which is critical to VDSM IC designs, particularly for parasitic-sensitive mixed-signal and RF ICs. Rouying Zhan received the B.S. degree in electrical engineering from Central South University, China, in 1994, and the M.S. degree in electrical engineering from the University of Electronic Science and Technology (UEST), China, in 1997. She is currently working toward the Ph.D. degree in electrical engineering at the Illinois Institute of Technology, Chicago. From 1997 to 2000, she was with the State Key Lab of Optical Fiber Transmission and Communication System of UEST, where her research focused on telecommunication network management and network survivability. Her research interests are IC CAD, ESD protection circuits, and RF IC design. ACKNOWLEDGMENT The authors would like to thank Synopsys for TCAD software donation, AKM and UMC for wafer fabrication, and Barth Electronics for TLP testing. Qiong Wu received the B.S. degree in electrical engineering from Nankai University, Tianjin, China, in 1997 and the M.S. degree in microelectronics from the Chinese Academy of Sciences, Beijing, China, in 2000. She is currently working toward the Ph.D. degree in the Department of Electrical and Computer Engineering, Illinois Institute of Technology, Chicago. She was an ASIC Design Engineer with Huawei Technologies Corporation, Shenzhen, China, from 2000 to 2001. Her research interest is mixed-signal REFERENCES [1] R. Merri and E. Issaq, “ESD design methodology,” in Proc. EOS/ESD Symp., 1993, pp. 233–237. [2] T. Green, “A review of EOS/ESD field failures in military equipment,” in Proc. EOS/ESD Symp., 1988, pp. 7–14. [3] A. Wang, C. Tsay, and P. Deane, “A study of NMOS behaviors under ESD stress: Simulation and characterization,” Microelectron. Reliabil., vol. 38, pp. 1183–1186, 1998. [4] A. Wang, “A new design for complete on-chip ESD protection,” in Proc. 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Haigang Feng (S’00) received the B.S. degree in electrical engineering from Tsinghua University, Beijing, China, in 1998 and the M.S. degree with honors in electrical and computer engineering from the Illinois Institute of Technology (IIT), Chicago, in 2001. He is currently working toward the Ph.D. degree at IIT working on developing multiband multistandard universal RF chips. His research interests center on analog, mixed-signal, and RF IC design and ESD protection design. He contributed to more than ten papers. IC design. Xiaokang Guan received the B.S.E.E. and M.S.E.E. degrees in electrical engineering from Tianjin University, Tianjin, China, in 1997 and 2000, respectively. He is currently working toward the Ph.D. degree with the Department Electrical and Computer Engineering, Illinois Institute of Technology, Chicago. His research interests are mixed-signal and RF IC design and multimedia signal processing. Haolu Xie received the B.S.E.E. degree from Zhejiang University, Zhejiang, China, in 2001. He is currently working toward the M.S. degree with the Department of Electrical and Computer Engineering, Illinois Institute of Technology, Chicago. His research interests include ESD protection simulation-design methodology, 3-D ESD protection modeling, and mixed-signal IC design. 1006 Albert Z. H. Wang (M’95–SM’00) received the B. Eng. degree in electrical engineering from Tsinghua University, Beijing, China, in 1985, the M.S.E.E. degree from The Chinese Academy of Sciences, Beijing, in 1988, and the Ph.D. degree in electrical engineering from The State University of New York at Buffalo in 1995. He was was with National Semiconductor Corporation until 1998, when he joined the Faculty of Electrical and Computer Engineering, Illinois Institute of Technology (IIT), Chicago, where he is currently directing the Integrated Electronics Laboratory. His research interests center on analog/mixed-signal/RF ICs, advanced on-chip ESD protection, IC CAD and modeling, SoCs and semiconductor devices, etc. He is a frequent speaker at various industrial, academic, and international forums and a frequent consultant to the IC industry. He is the author of the book On-Chip ESD Protection for Integrated Circuits (Boston, MA: Kluwer, 2002) and more than 60 papers in the field. He holds several U.S. patents. Dr. Wang received the CAREER Award from the National Science Foundation in 2002 and the Sigma Xi Award for Excellence in University Research from the IIT in 2003. He is an Editor for the IEEE ELECTRON DEVICE LETTERS and an Associate Editor for the IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II. He is an IEEE Distinguished Lecturer for the Electron Devices Society (EDS) and the Solid-State Circuits Society, an IEEE EDS AdCom Member, Vice Chair of EDS Regions and Chapters Committee for North America West, and a Member of the EDS VLSI Technology and Circuits Committee. He serves as Technical Program Committee Member, Sub-Committee Chair, and Session Chair for many conferences, including IEEE CICC, RFIC, APC-CAS, and ASP-DAC. IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 38, NO. 6, JUNE 2003 Roman Gafiteanu received the M.Sc. degree in mechanical engineering from the University of Ploiesti, Romania, in 1988 and the Ph.D. degree in electronic materials from Duke University, Durham, NC, in 1997. In 1997, he joined Technology Modeling Associates as an Application Engineer for TCAD software tools. He is currently managing the corporate applications engineering with Synopsys, Mountain View, CA, working on the TCAD and Mask Synthesis product lines. His research interests are in the areas of process and device modeling, design for manufacturability, and novel electronic devices at the nanometer scale.