Electrostatic Discharge

This paper presents a chip-level charged device model (CDM) electrostatic discharge (ESD) simulation method. The chiplevel simulation is formulated as a DC analysis problem. A network reduction algorithm based on random walks is proposed for rapid analysis, and to support incremental design. A benchmark with a 2.3M-node VDD net and 1000 I/O pads is checked in 13 minutes, and 10 re-simulations for incremental changes take a total of 9 minutes.

The response of experimental thin-film (TF) recording head structures to excessive current and/or voltage during an electrostatic discharge (ESD) event is studied. Inductive and magnetoresistive-like (MR-like) magnetic recording head structures are tested and modeled from the viewpoint of electrostatic theory. An electrical model for the shielded MR-like head structure is proposed and used in circuit simulations to study the current flow during a human body model (HBM) and machine model (MM) transients. A testing methodology is defined using standard HBM and MM ESD transients. A thermal model for TF resistor burnout is compared with experiment and predicts a higher failure current than is measured. Results show that the MR structure can fail due to metalization burnout or air breakdown. The HBM metalization burnout failure voltage ranged from 100 to 300 V, while MM damage stated at 27 V. Air breakdown ranged from 550 to 650 V.

A new on-chip transient detection circuit for systemlevel electrostatic discharge (ESD) protection is proposed in this paper. The circuit performance to detect different positive and negative fast electrical transients has been investigated by HSPICE simulator and verified in silicon chip. The experimental results in a 0.13-µm CMOS process have confirmed that the proposed on-chip transient detection circuit can detect fast electrical transients during system-level ESD zapping. The proposed transient detection circuit can be further cooperated with power-on reset circuit to improve the immunity of CMOS IC products against system-level ESD stress.

Saturn inhabits a dynamical regime of rapidly rotating, internally heated atmospheres similar to Jupiter. Zonal winds have remained fairly steady since the time of Voyager except in the equatorial zone and slightly stronger winds occur at deeper levels. Eddies supply energy to the jets at a rate somewhat less than on Jupiter and mix potential vorticity near westward jets. Convective clouds exist preferentially in cyclonic shear regions as on Jupiter but also near jets, including major outbreaks near 35°S associated with Saturn electrostatic discharges, and in sporadic giant equatorial storms perhaps generated from frequent events at depth. The implied meridional circulation at and below the visible cloud tops consists of upwelling (downwelling) at cyclonic (anti-cyclonic) shear latitudes. Thermal winds decay upward above the clouds, implying a reversal of the circulation there. Warm-core vortices with associated cyclonic circulations exist at both poles, including surrounding thick high clouds at the south pole. Disequilibrium gas concentrations in the tropical upper troposphere imply rising motion there. The radiativeconvective boundary and tropopause occur at higher pressure in the southern (summer) hemisphere due to greater penetration of solar heating there. A temperature "knee" of warm air below the tropopause, perhaps due to haze heating, is stronger south of the equator as well. Saturn's south polar stratosphere is warmer than predicted by radiative models and enhanced in ethane, suggesting subsidence-driven adiabatic warming there. Recent modeling advances suggest that shallow weather layer theories of jet pumping may be viable if water condensation is the source of energy input driving the flow, and that deep convective cylinder models with a sufficiently large tangent cylinder radius can reproduce observed flow features as well.

Triboelectric charge accumulation both poses problems and offers opportunities for dry particulate processing. It generates hazards in many industrial systems, but is exploited in several important applications, including electrophotographic toner charging and triboelectric separation. However, the charging of continuous particulate flows on solid surfaces is poorly understood, and design of devices to optimise triboelectric behaviour is often qualitative or based on trial and error. This study attempts to identify the main charging mechanisms for a continuous particulate flow on a flat surface. The proposed charging models incorporate contact time, velocity and mode of contact. A model incorporating contact area effects arising from sliding and rolling contact is consistent with experimental data, as long as a charge limit is imposed on bouncing particles. A mechanism for this charge limit, involving separation discharge, is proposed. The effect of delocalised image charge on the system is estimated and found to be negligible. Some general design principles are proposed for triboelectric optimisation of particle processing devices.Triboelectrification produces hazards and offers opportunities for dry particle processing. Charging mechanisms for a continuous particulate flow on a flat surface are identified and modelled, for sliding, rolling and bouncing contact. These models are then validated using existing experimental data. Some general design principles are proposed for triboelectric optimisation of particle processing devices.

All explosives, under all conditions must be considered vulnerable to generation, accumulation and discharge of static charge. The low energy static hazards of the order as low as 2-3 mJ need to be guarded against in case of highly sensitive compounds namely primary explosives. The hazard is normally associated with manufacturing and filling operations due to discharge of static charge accumulated on a person supplying energy up to 20 mJ. To reduce the risk associated with static initiation hazard in the processing and handling of the explosives, the electrostatic sensitivity tests can provide an important input regarding electrostatic hazards. This paper presents electrostatic sensitivity data in terms of zero ignition probability data (E SE0 ) of some of the initiatory explosives such as nickel/cobalt hydrazinium nitrate, silver azide, lead azide and mercury salt of 5-nitro tetrazole. Similar data has also been presented for samples coated with polyvinyl pyrrolidone to study its effect on electrostatic sensitivity. The electrostatic spark sensitivity of some conventional and novel made to explain the increased spark sensitivity behavior on the basis of the possible primary explosives has been studied. The electrostatic spark sensitivity of primary explosives decreased in the order of AgN 3 = NHN > PbN 6 > MNT > CoHN > BNCP. A possible correlation of spark energy with approximation and assumption has been drawn with thermal, detonation and mechanical properties. The polyvinyl pyrrolidone coated samples followed the same order but interestingly with increased spark sensitivity. An attempt has been reasoning of dielectric nature of the materials or exothermic effects of decomposition products of PVP. The present work also reports the electrostatic spark sensitivity of cap compositions.

A guard ring (GR) protected InGaAs p-i-n photodiode with high linearity is fabricated and the effect of the GR protection structure on the linearity of the photodiode is studied. For the electrostatic discharge (ESD) protected photodiode, both the single second order (SSO) intermodulation and the single triple beat intermodulation are below 80 dBc. The GR can enhance the ESD robustness of the photodiode but degrades the photodiode's linearity about 3.5 dB for SSO at 854 MHz. The photodiode's nonlinearity is mainly due to the photodiode junction capacitance variation, which is caused by the photocurrent and bias voltage changes that are resulted from the change of incident laser power. The distortion caused by the photodiode's bias voltage is much larger than that caused by the photocurrent. The GR integrated into the photodiode aggregates the capacitance variation with the bias voltage and therefore increases the distortion. The calculated SSO distortion using the experimentally measured differential capacitances matches the experimental data.

The root causes of the high voltage (HV) LDMOS (Fig. 2) failed at the low voltage electrostatic-discharge (ESD) zap is found. One is caused by the bulk layout and one is caused by the intrinsic characteristic of the device. From the findings, a new structure is proposed to eliminate the root causes without sacrificing the IV characteristics and dimension of the device. I. Jian-Hsing Lee 303 7-1

Space Systems/Loral (SS/L) successfully completed electrostatic discharge (ESD) tests of Multi-junction (MJ) GaAs/Ge solar array design in geosynchronous space environment. This ESD test was based on ISO-11221, Space systems-Space solar panels-Spacecraft Charging Induced Electrostatic Discharge Test Methods. In addition to the ISO reference for the test schematic, SS/L implemented modified test circuitry to better simulate the on-orbit operational conditions of our solar array design. The ESD test circuit also included simulated solar array panel coverglass flashover. The ESD test program utilized a 25-cell coupon that had been subjected to 2,000 thermal cycles caused by earth eclipses in GEO orbit and >12,000 thermal cycles caused by the shadow of the spacecraft antennas. Other ESD test coupons are 4-cell coupons that, after baseline ESD experiments, can later be subjected to combined space environmental exposures tests. To demonstrate design robustness, we performed ESD tests to voltages and currents that are higher than that of on-orbit solar array operational voltages and currents. This paper discusses the coverglass flashover simulation, ESD test setup, the importance of the electrical test design in simulating the on-orbit operational conditions, and the test results.

In this paper, the impact of ball bonding (BB) induced voltage transient on the reliability test including Electro-Migration (EM), Time Dependent Dielectric Breakdown (TDDB), Negative Bias Temperature Instability (NBTI) and Electro-Static Discharge (ESD) are investigated. During the Electronic Flame-Off (EFO) of ball bonding process, a spark discharge current, which applies a high electric field between the wire and wand, is used to melt the wire to form a free air ball (FAB). In the mean time, however, the spark may generate ions in the air and some of them may charge to die for package. After free air ball was bonded to pad, a BB-induced voltage transient can be measured and may impose an electrical stress to devices, then to degrade the device lifetime if without suitable I/0 protection circuits. The degradation mechanism can be considered as charge device model (CDM) electrostatic-discharge (ESD) event. To remove or reduce this packageinduced damage, ionizers had been put closely to the bonding tool and showed very good package yield, compared to those without ionizer.

Thunderstorm activity on Saturn is associated with optically detectable clouds that are atypically dark throughout the near-infrared. As observed by Cassini/VIMS, these clouds are $20% less reflective than typical neighboring clouds throughout the spectral range from 0.8 mm to at least 4.1 mm. We propose that active thunderstorms originating in the 10-20 bar water-condensation region vertically transport dark materials at depth to the $1 bar level where they can be observed. These materials in part may be produced by chemical processes associated with lightning, likely within the water clouds near the $10 bar freezing level of water, as detected by the electrostatic discharge of lightning flashes observed by Cassini/RPWS (e.g., Fischer et al. 2008, Space Sci. Rev., 137, 271-285). We review lightning-induced pyrolytic chemistry involving a variety of Saturnian constituents, including hydrogen, methane, ammonia, hydrogen sulfide, phosphine, and water. We find that the lack of absorption in the 1-2 mm spectral region by lightning-generated sulfuric and phosphorous condensates renders these constituents as minor players in determining the color of the dark storm clouds. Relatively small particulates of elemental carbon, formed by lightning-induced dissociation of methane and subsequently upwelled from depth-perhaps embedded within and on the surface of spectrally bright condensates such as ammonium hydrosulfide or ammonia-may be a dominant optical material within the dark thunderstorm-related clouds of Saturn.

TVS components are widely used to protect electronic systems from ESD. However, there are various technologies of TVS components as well as numerous manufacturers for each technology. Choosing the right component is not easy, as a typical TVS data sheet does not always provide all the relevant information. This paper presents the pros and cons of different technologies as well as empirical data to facilitate the design of adequate and economical ESD protection.

Realization of on-chip electrostatic discharge (ESD) protection requires extensive technical experience and know-how. A technology computer-aided design (TCAD) methodology aimed to assist in the design and implementation of robust ESD devices is developed and presented. The methodology provides a systematic and practical means for the evaluation and optimization of ESD devices in a simulation environment. Advanced siliconcontrolled-rectifier devices are considered to illustrate the approach, and experimental data measured from these devices are also included in support of the TCAD development.

that time. Most solar system material available for us to examine has been processed (e.g., by incorporation into a Chondrules constitute a significant fraction of primitive meteorites. Their thermal history includes rapid melting followed planet and subsequent metamorphosis) in ways that oblitby cooling on timescales of minutes to hours. The mechanism erated preexisting structures and reset nucleogenic clocks. underlying such extreme, short-lived thermal excursions away We do, however, have access to small quantities of primifrom the prevailing, much milder nebular equilibrium conditive meteoritic material, which is believed to consist of tions has eluded understanding for many decades. Among the more or less unaltered samples of early solar system matter. prime candidate mechanisms long thought to provide a possible Primitive meteorites show startling evidence for tranexplanation of chondrule formation is lightning-large-scale sient high-energy phenomena in the early solar system, electrostatic discharges-in the protoplanetary nebula. before the formation of planetary bodies. Many primitive In this paper, we explore the possible occurrence of such meteorites contain high concentrations of chondrules (milelectrostatic discharges in the protoplanetary nebula powered by precipitation or other processes analogous to that believed limeter-sized beads of glassy silicate) in a matrix of essento cause lightning on Earth and other planets. Our analysis tially unprocessed material. The chondrules were apparincorporates charge separation in collisions of water-ice or other ently melted in the early Solar System by some unknown solid particles, and includes a self-consistent nebular electrical process, then incorporated along with unheated dust into conductivity determined by a balance between production of larger bodies. Evidence indicates that the gaseous nebula free electrons and ions and loss to grain surfaces. We find that was still present at the time of chondrule formation (Taylor development of a large-scale electric field strong enough to et al. 1983). produce discharges does not occur under conditions character-Chondrules were apparently melted and cooled rapidly, istic of protostellar nebulae. This is mainly a result of the fact that the high electrical conductivity of the environment and on timescales as short as minutes to hours (Hewins 1983; the relatively low density of solid particles combine to yield a Grossman 1988). This indicates that they were formed in situation in which the large scale electric fields, as well as the short-lived transitory events, with time scales much shorter electric charges segregated on the particles are short circuited than those characterizing typical nebular thermal and dyby the highly mobile electrons and ions. We also consider the namical time scales. Among the several mechanisms propossibility of lightning in altered nebula environments with posed to account for such transitory heating events in the higher than canonical dust density, such as a dust subdisk. nebula have been high-velocity impacts (Kieffer 1976),

There are several approaches for ESD protection of integrated circuits. This paper provides practical guidelines to I/O library designers to choose the right methodology for ESD protection of I/O libraries in advanced CMOS technologies. Guidelines are provided predominantly for low-voltage I/O libraries that are commonly used for general purpose interfaces and industrial low-voltage interfaces such as DDR, MLB, USB, etc. Additionally, some general background issues of ESD protection methodologies used in the industry are considered. This paper is focused on HBM and MM ESD protection solutions. Special CDM ESD protection solutions are not considered.

This paper will first focus on the guard ring structures, design methodology, integration, experimental results and analysis. In this paper, the focus will be on test structure design issues, electrical characterization, and computer aided design (CAD) methodologies for advanced digital design, and mixed signal applications. The integration of ''parameterized cell'' guard ring structures concept into a Cadence TM based design methodology for the construction of electrostatic discharge (ESD) structures, I/O design, and latchup for radio frequency (RF) CMOS and Silicon Germanium technology will be discussed. The importance of the guard ring p-cell allows for evaluation of internal and external latchup, and the ability to verify the presence of the guard ring for whole chip design checking, verification and synthesis will be addressed. Additionally, this independent guard ring concept opens the door for a new methodology for RF design of primitive and hierarchical implementations. r

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Electrostatic discharge protection in semiconductors have undergone both revolutionary and evolutionary changes to maintain pace with the rapidly scaling and changing environment of advanced semiconductor technologies. As a result, it is an area of continuous discovery in both semiconductor development, and design. ESD phenomenon remains a research and development arena for new innovation, invention, and initiatives. In this paper, an introduction to electrostatic discharge protection in semiconductors will be reviewed.

Considering gate-oxide reliability, a new electrostatic discharge (ESD) protection scheme with an on-chip ESD bus (ESD_BUS) and a high-voltage-tolerant ESD clamp circuit for 1.2/2.5 V mixed-voltage I/O interfaces is proposed. The devices used in the high-voltage-tolerant ESD clamp circuit are all 1.2 V low-voltage N-and P-type MOS devices that can be safely operated under the 2.5-V bias conditions without suffering from the gate-oxide reliability issue. The four-mode (positive-to-V SS , negative-to-V SS , positive-to-V DD , and negative-to-V DD ) ESD stresses on the mixed-voltage I/O pad and pin-to-pin ESD stresses can be effectively discharged by the proposed ESD protection scheme. The experimental results verified in a 0.

The generation of electrostatic charge is considered
for the cases of standing up from a chair and for taking off a
sweater. The charge voltages have been recorded at 27°C with
relative humidity (RH) of 8%, 25% and 45% and at 38°C with
8% RH. Different footwear and flooring systems have been used
to cover both ESD and non-ESD mitigating footwear and
flooring combinations. The voltages caused by the activity (event voltage) and the decay times are discussed.

This paper discusses state-of-the-art electrostatic discharge (ESD) protection in advanced semiconductor technologies and emerging technologies. ESD physics, semiconductor process issues, device and circuit simulation, circuits, and devices will be examined.

A novel macro model approach for modeling ESD MOS snapback is introduced. The macro model consists of standard components only. It includes a MOS transistor modeled by BSIM3v3, a bipolar transistor modeled by VBIC, and a resistor for substrate resistance. No external current source, which is essential in most publicly reported macro models, is included since both BSIM3vs and VBIC have formulations built in to model the relevant effects. The simplicity of the presented macro model makes behavior languages, such as Verilog_A, and special ESD equations not necessary in model implementation. This offers advantages of high simulation speed, wider availability, and less convergence issues. Measurement and simulation of the new approach indicates that good silicon correlation can be achieved.

A substrate-triggered technique is proposed to improve ESD protection efficiency of the stacked-NMOS device in the mixed-voltage I/O circuit. The substrate-triggered technique can further lower the trigger voltage of the stacked-NMOS device to ensure effective ESD protection for the mixed-voltage I/O circuit. The proposed ESD protection circuit with the substrate-triggered technique for 2.5V/3.3V tolerant mixed-voltage I/O circuit has been fabricated and verified in a 0.25-µm salicided CMOS process. Experimental results have confirmed that the HBM ESD robustness of the mixed-voltage I/O circuit can be increased ~ 65% by this substrate-triggered design.

On-chip electrostatic discharge (ESD) protection design becomes a major design challenge as IC technologies continue to migrate into very-deep-submicron (VDSM) regime. However, trial-and-error approaches still dominate in ESD protection circuit design. This paper discusses a new mixed-mode ESD protection simulation-design methodology, aiming to design prediction, which involves multiple-level coupling in ESD protection simulation by solving complex electrothermal equations self-consistently at process, device, and circuit levels in a coupled fashion to investigate ESD protection circuit details without any pre-assumption. Practical ESD protection design examples, implemented in commercial 0.18/0.35-m CMOS and BiCMOS processes, are presented. His research interests include ESD protection simulation-design methodology, 3-D ESD protection modeling, and mixed-signal IC design.

In this letter, the dynamic turn-on mechanism of the n-MOSFET under high-current-stress event is investigated by using a real-time current and voltage measurement. Results reveal the existence of "self-consistent effect," i.e., the turn-on region of the parasitic n-p-n bipolar can change from one region to another region and increases with the stress current (I D ). Furthermore, experimental data show that the minimum substrate potential to sustain a stable snapback phenomenon is 0.9 V and increases with I D instead of 0.6-0.8 V and independent of I D as reported in early literatures.

A guard ring (GR) structure is used to protect a planar InGaAs pin photodiode. The human body model (HBM) measurement results show that a photodiode with a GR, which is shorted to the cathode, is able to withstand an electrostatic discharge (ESD) threshold voltage of up to 200 V, whereas a similar photodiode without a GR structure can only withstand 50 V ESD threshold voltage. The capacitance and bandwidth measurement results show that the GR has negligible negative effects on the pin diode performance.

This study relates to the delay of secondary electrostatic discharges (ESDs). The first motivation for this study is the fact that the delay value is a required input parameter for the simulation of the secondary ESD. The second motivation is that this delay is one limiting factor for the usage of spark gaps as protection devices. The objective is to determine the delay for different intended and unintended spark gap structures as this time delay will influence the peak current and rise time of the secondary ESD across these gaps. The intended application is ESD protection in consumer products, for that reason 0.5-3 mm gap distances and voltages up to 14 kV are considered at different humidity levels. Very long time lags are observed for clean sphere-to-sphere gaps requiring average field strengths >200 kV/cm to achieve a breakdown in a few nanoseconds in dry air. Humidity is shown to strongly reduce the time lag. However, if printed circuit board (PCB) spark gap geometries are considered the time lags are much smaller. Similar shorter lag times have been found in geometries that resemble more unintentional breakdown locations in a product.

Electrostatic discharge (ESD) protection design for mixed-voltage I/O interfaces has been one of the key challenges of system-on-achip (SOC) implementation in nanoscale CMOS processes. The on-chip ESD protection circuit for mixed-voltage I/O interfaces should meet the gate-oxide reliability constraints and prevent the undesired leakage current paths. This paper presents an overview on the design concept and circuit implementations of ESD protection designs for mixed-voltage I/O interfaces with only low-voltage thin-oxide CMOS transistors. Especially, the ESD protection designs for mixed-voltage I/O interfaces with ESD bus and high-voltage-tolerant power-rail ESD clamp circuits are presented and discussed.

This paper provides a SPICE-compatible circuit model for characterizing electrostatic discharge (ESD) clamping performance of protection devices mounted on printed circuit boards (PCBs). An equivalent circuit model for a commercial ESD generator is introduced and a simulation methodology of an ESD protection device with non-linear resistance characteristic using voltage controlled current source is described. These models combined to create a full circuit model with a PCB model in a SPICE-like circuit simulator. Comparison results between the simulated and measured are presented to verify the accuracy of the proposed circuit model. A trade-off analysis between the ESD clamping performance and signal integrity with the ESD protection device in high-speed applications is also presented as a case study.

A new on-chip CR-based electrostatic discharge (ESD) detection circuit for system-level ESD protection design is proposed in this work. The circuit performance to detect positive or negative electrical transients generated by system-level ESD tests has been analyzed in HSPICE simulation and verified in silicon chip. The experimental results in a 0.13-Pm CMOS process have confirmed that the proposed detection circuit can detect ESD-induced transient disturbance during system-level ESD zapping. The detection results can be used as system recovery firmware index to improve the immunity of CMOS IC products against system-level ESD stress.

The dynamic topology of a mobile ad hoc network (MANET) poses a real challenge in the design of a MANET routing protocol. Over the last 10 years, a variety of routing protocols have been developed and their performance simulations are made by network researchers. Most of the previous research on MANET routing protocols have focused on simulation study by varying network parameters, such as network size (node density), pause times, or node mobility independently. This paper considers the problem from a different perspective, using a simulation model the combined effect of node density and packet length; node density and mobility on the performance of a typical 802.11 MANET is investigated. This is a common and realistic scenario in MANETs where nodes move around, join and leave the network at any time. Based on the QoS (end-to-end delay, throughput), routing load and packet retransmissions, this paper systematically analyzes the performance of four diverse MANET routing protocols with the different simulation model and configurations, and drew more complete conclusions.

A novel self-substrate-triggered technique for on-chip ESD protection design is proposed to solve the non-uniform turn-on phenomenon of multi-finger gate-grounded nMOS (GGnMOS). The center-finger nMOS transistors in the multi-finger GGnMOS structure are always turned on first under ESD stress, so its source terminal is connected to the base (substrate) terminals of the other parasitic lateral n-p-n bipolar transistors (BJTs in the GGnMOS structure) to form the self-substrate-triggered design. With the proposed self-substrate-triggered technique, the first turned-on center-finger nMOS transistors are used to trigger on the others. Therefore, all fingers of GGnMOS can be triggered on simultaneously to discharge ESD current. From the experimental results verified in a 0.13-m CMOS process with the thin gate oxide of 25 A, the turn-on uniformity and ESD robustness of the GGnMOS can be greatly improved without increasing extra layout area through the proposed self-substrate-triggered technique.

Susceptibility scanning is an increasingly adopted method for root cause analysis of system-level immunity sensitivities. It allows localizing affected nets and integrated circuits (ICs). Further, it can be used to compare the immunity of functionally identical or similar ICs or circuit boards. This paper explains the methodology as applied to electrostatic discharge and provides examples of scan maps and signals probed during immunity scanning. Limitations of present immunity analysis methods are discussed.

This paper presents an electrostatic discharge (ESD)protected ultra-wideband (UWB) low-noise amplifier (LNA) for full-band (170-to-1700 MHz) mobile TV tuners. It features a PMOS-based open-source input structure to optimize the I/O swings under a mixed-voltage ESD protection while offering an inductorless broadband input impedance match. The amplification core exploiting double current reuse and single-stage thermal-noise cancellation enhances the gain and noise performances with high power efficiency. Optimized in a 90-nm 1.2/2.5-V CMOS process with practical issues taken into account, the LNA using a constant-bias circuit achieves competitive and robust performances over process, voltage and temperature variation. The simulated voltage gain is 20.6 dB, noise figure is 2.4 to 2.7 dB, and IIP3 is +10 8 dBm. The power consumption is 9.6 mW at 1.2 V. S 11 10 dB is achieved up to 1.9 GHz without needing any external resonant network. Human Body Model ESD zapping tests of 4 kV at the input pins cause no failure of any device.

The electrostatic-discharge sensitivity of fully depleted SOI MOSFETs with ultrathin silicon body and ultrathin gate oxide is studied. An original and detailed electrical analysis is carried out in order to investigate the degradation of the electrical dc parameters and classify the observed failure modes and mechanisms. The impact of device geometry and strain engineering is also analyzed.

Aluminum-water reactions have been proposed and studied for several decades for underwater propulsion systems and applications requiring hydrogen generation. Aluminum and water have also been proposed as a frozen propellant, and there have been proposals for other refrigerated propellants that could be mixed, frozen in situ, and used as solid propellants. However, little work has been done to determine the feasibility of these concepts. With the recent availability of nanoscale aluminum, a simple binary formulation with water is now feasible. Nanosized aluminum has a lower ignition temperature than micronsized aluminum particles, partly due to its high surface area, and burning times are much faster than micron aluminum. Frozen nanoscale aluminum and water mixtures are stable, as well as insensitive to electrostatic discharge, impact, and shock. Here we report a study of the feasibility of an nAl-ice propellant in small-scale rocket experiments. The focus here is not to develop an optimized propellant; however improved formulations are possible. Several static motor experiments have been conducted, including using a flight-weight casing. The flight weight casing was used in the first sounding rocket test of an aluminum-ice propellant, establishing a proof of concept for simple propellant mixtures making use of nanoscale particles.