LEON3

The LEON3 integer unit implements the full SPARC V8 manual, including hardware multiply and divide instructions. The number of register windows is configurable within the limit of the SPARC manual (2 - 32), with a default setting of 8. The pipeline consists of 7 stages with a separate instruction and data cache interface (Harvard architecture).

LEON3 has a highly configurable cache system, consisting of a separate instruction and data cache. Both caches can be configured with 1 - 4 ways, 1 - 256 KiB/way, 16 or 32 bytes per line. The instruction cache maintains one valid bit per 32-bit word and uses streaming during line-refill to minimize refill latency.  The data cache has one valid bit per cache line, uses write-through policy and implements a double-word write-buffer. Bus-snooping on the AHB bus can be used to maintain cache coherency for the data cache. Local scratch pad ram can be added to either of the instruction and data caches to allow 0-waitstates access instruction or data memory without any AHB bus access.

The LEON3 integer unit provides interfaces for a floating-point unit (FPU), and a custom co-processor. Two FPU controllers are available, one for the high-performance GRFPU and one for the GRFPU-Lite core. The floating-point processors and co-processor execute in parallel with the integer unit, and does not block the operation unless a data or resource dependency exists.

The LEON3 processor can be synthesised with common synthesis tools from vendors such as Synopsys, Mentor, Xilinx, Microsemi, Lattice and NanoXplore.

LEON3 is part of the GRLIB IP library. The open-source version of the library is distributed under the GNU GPL license and can be downloaded here. The open source version of the LEON3 does not include features such as fault-tolerance and high-performance FPU.

The LEON3 can be obtained under commercial licensing conditions, enabling proprietary designs and taking advantage of a support agreement. Please see the GRLIB IP Core User's Manual - Processor license overview for the license types.

Contact us if you want to use LEON3 in a commercial product

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Being SPARC V8 conformant, compilers and kernels for SPARC V8 can be used with  LEON3 (kernels will need a LEON BSP). To simplify software development,
We provide several toolchains and operating systems. Check the software overview webpage for all the details.

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The GRMON monitor interfaces to the LEON3 on-chip debug support unit (DSU), implementing a large range of debug functions as well as a GDB gateway. Debugging is generally done using the GDB debugger, and a graphical front-end. It is possible to perform source-level symbolic debugging, either on a simulator or using real target hardware.  

The LEON3 processor is also supported by our TSIM3 simulator.

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The LEON3 processor is fully parametrizable through the use of VHDL generics and does not rely on any  global configuration package. It is thus possible to instantiate several processor cores in the same design with different configurations. The LEON3 template designs can be configured using a graphical tool built. This allows new users to quickly define a suitable custom configuration. The configuration tool not only configures the processor, but also other on-chip peripherals such as memory controllers and network interfaces.

The GRLIB IP library contains LEON3 template designs for several popular FPGA prototyping boards.

Pre-synthesized FPGA programming files are also provided, see LEON-RTG4.

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Probabilistic platform
The LEON3 processor was extended within the PROXIMA project to build a platform with hardware support that enables probabilistic timing analysis. These extensions, including extensions for GRLIB's Level-2 cache, can also be obtained from us.