DDR SDRAM

Generic DDR-266 memory in the 184-pin DIMM form

Corsair DDR-400 memory with heat spreaders

Double data rate synchronous dynamic random-access memory (DDR SDRAM) is a class of memory integrated circuits used in computers. DDR SDRAM (sometimes referred to as DDR1 SDRAM) has been superseded by DDR2 SDRAM and DDR3 SDRAM, neither of which is either forward or backward compatible with DDR SDRAM, meaning that DDR2 or DDR3 memory modules will not work in DDRequipped motherboards, and vice versa. Compared to single data rate (SDR) SDRAM, the DDR SDRAM interface makes higher transfer rates possible by more strict control of the timing of the electrical data and clock signals. Implementations often have to use schemes such as phase-locked loops and self-calibration to reach the required timing accuracy.[1][2] The interface uses double pumping (transferring data on both the rising and falling edges of the clock signal) to lower the clock frequency. One advantage of keeping the clock frequency down is that it reduces the signal integrity requirements on the circuit board connecting the memory to the controller. The name "double data rate" refers to the fact that a DDR SDRAM with a certain clock frequency achieves nearly twice the bandwidth of a SDR SDRAM running at the same clock frequency, due to this double pumping. With data being transferred 64 bits at a time, DDR SDRAM gives a transfer rate of (memory bus clock rate) 2 (for dual rate) 64 (number of bits transferred) / 8 (number of bits/byte). Thus, with a bus frequency of 100 MHz, DDR SDRAM gives a maximum transfer rate of 1600 MB/s. "Beginning in 1996 and concluding in June 2000, JEDEC developed the DDR (Double Data Rate) SDRAM specification (JESD79)."[3] JEDEC has set standards for data rates of DDR SDRAM, divided into two parts. The first specification is for memory chips, and the second is for memory modules.

Specification standards

Comparison of memory modules for desktop PCs (DIMM).

Physical DDR layout

Comparison of memory modules for portable/mobile PCs (SO-DIMM).

Chips and modules

Standard name Memory clock
(MHz)

Cycle time[4]
(ns)

I/O clock
(MHz)

bus Data rate

(MT/s)

VDDQ
(V)

Module name

Peak transfer Timings (CL-tRCDrate

(MB/s) tRP)

DDR-200 DDR-266 DDR-333 DDR-400A DDR-400B DDR-400C

100 133 166

10 7.5 6

100 133 166

200 266 333

PC-1600 2.50.2 PC-2100 PC-2700

1600 2133 2666 2.5-3-3 3-3-3 3-4-4

200

200

400

2.60.1 PC-3200

3200

Note: All above listed are specified by JEDEC as JESD79F.[5] All RAM data rates in-between or above these listed specifications are not standardized by JEDECoften they are simply manufacturer optimizations using tighter-tolerance or overvolted chips. The package sizes in which DDR SDRAM is manufactured are also standardized by JEDEC. There is no architectural difference between DDR SDRAM designed for different clock frequencies, for example, PC-1600, designed to run at 100 MHz, and PC-2100, designed to run at 133 MHz. The number simply designates the data rate at which the chip is guaranteed to perform, hence DDR SDRAM is guaranteed to run at lower (underclocking) and can possibly run at higher (overclocking) clock rates than those for which it was made.[6] DDR SDRAM modules for desktop computers, commonly called DIMMs, have 184 pins (as opposed to 168 pins on SDRAM, or 240 pins on DDR2 SDRAM), and can be differentiated from SDRAM DIMMs by the number of notches (DDR SDRAM has one, SDRAM has two). DDR SDRAM for notebook computers, SODIMMs, have 200 pins, which is the same number of pins as DDR2 SO-DIMMs. These two specifications are notched very similarly and care must be taken during insertion if unsure of a correct match. DDR SDRAM operates at a voltage of 2.5 V, compared to 3.3 V for SDRAM. This can significantly reduce power consumption. Chips and modules with DDR-400/PC-3200 standard have a nominal voltage of 2.6 V. Increasing operating voltage slightly can increase maximum speed, at the cost of higher power dissipation and heating, and at the risk of malfunctioning or damage. Many new chipsets use these memory types in multi-channel configurations.

Chip characteristics
DRAM density Size of the chip are measured in megabits. Nearly all motherboards only recognize 1 GB modules if they contain 64M8 chips (low density). If 128M4 (high density) 1 GB modules are used, they most likely will

not work. The JEDEC standard allows 128M4 only for slower buffered/registered modules designed specifically for some servers, but some generic manufacturers do not comply.[7][verification needed] Organization The notation like 64M4 means that the memory matrix has 64 million (the product of banks x rows x columns) 4-bit storage locations. There are 4, 8, and 16 DDR chips. The 4 chips allow the use of advanced error correction features like Chipkill, memory scrubbing and Intel SDDC in server environments, while the 8 and 16 chips are somewhat less expensive. x8 chips are mainly used in desktops/notebooks but are making entry into the server market. There are normally 4 banks and only one row can be active in each bank.

Module characteristics
Ranks

To increase memory capacity and bandwidth, chips are combined on a module. For instance, the 64-bit data bus for DIMM requires eight 8-bit chips, addressed in parallel. Multiple chips with the common address lines are called a memory rank. The term was introduced to avoid confusion with chip internal rows and banks. A memory module may bear more than one rank. The term sides would also be confusing because it incorrectly suggests the physical placement of chips on the module. All ranks are connected to the same memory bus (address+data). The Chip Select signal is used to issue commands to specific rank. Adding modules to the single memory bus creates additional electrical load on its drivers. To mitigate the resulting bus signaling rate drop and overcome the memory bottleneck, new chipsets employ the multichannel architecture.
Capacity Number of DRAM Devices The number of chips is a multiple of 8 for non-ECC modules and a multiple of 9 for ECC modules. Chips can occupy one side (single sided) or both sides (dual sided) of the module. The maximum number of chips per DDR module is 36 (94) for ECC and 32 (8x4) for non-ECC. ECC vs non-ECC Modules that have error correcting code are labeled as ECC. Modules without error correcting code are labeled non-ECC. Timings CAS latency (CL), clock cycle time (tCK), row cycle time (tRC), refresh row cycle time (tRFC), row active time (tRAS). Buffering registered (or buffered) vs unbuffered Packaging

Typically DIMM or SO-DIMM Power consumption A test with DDR and DDR2 RAM in 2005 found that average power consumption appeared to be of the order of 1-3W per 512MB module. Increases with clock rate, and when in use rather than idling. [8] A manufacturer has produced calculators to estimate the power used by various types of RAM.[9]

Module and chip characteristics are inherently linked. Total module capacity is a product of one chip's capacity by the number of chips. ECC modules multiply it by 8/9 because they use one bit per byte for error correction. A module of any particular size can therefore be assembled either from 32 small chips (36 for ECC memory), or 16(18) or 8(9) bigger ones. DDR memory bus width per channel is 64 bits (72 for ECC memory). Total module bit width is a product of bits per chip by number of chips. It also equals number of ranks (rows) multiplied by DDR memory bus width. Consequently a module with greater amount of chips or using 8 chips instead of 4 will have more ranks.
Example: Variations of 1 GB PC2100 Registered DDR SDRAM module with ECC Module size (GB) Number of chips Chip size (Mbit) Chip organization Number of ranks 1 1 1 36 18 18 256 512 512 64M4 64M8 128M4 2 2 1

This example compares different real-world server memory modules with a common size of 1 GB. One should definitely be careful buying 1 GB memory modules, because all these variations can be sold under one price position without stating whether they are 4 or 8, single or dual ranked. There is a common belief that number of module ranks equals number of sides. As above data shows, this is not true. One can find 2-side/1-rank or 2-side/4-rank modules. One can even think of a 1-side/2-rank memory module having 16(18) chips on single side 8 each, but it's unlikely such a module was ever produced.

History
Double data rate (DDR) SDRAM specification

From JEDEC Board Ballot JCB-99-70, and modified by numerous other Board Ballots, formulated under the cognizance of Committee JC-42.3 on DRAM Parametrics. Standard No. 79 Revision Log:

Release 1, June 2000 Release 2, May 2002 Release C, March 2003 JEDEC Standard No. 79C.[10]

"This comprehensive standard defines all required aspects of 64Mb through 1Gb DDR SDRAMs with X4/X8/X16 data interfaces, including features, functionality, ac and dc parametrics, packages and pin assignments. This scope will subsequently be expanded to formally apply to x32 devices, and higher density devices as well."

High density vs low density

High density memory here means non-ECC 184 pin SDRAM memory.[citation needed]

Organization
PC3200 is DDR SDRAM designed to operate at 200 MHz using DDR-400 chips with a bandwidth of 3,200 MB/s. Because PC3200 memory transfers data on both the rising and falling clock edges, its effective clock rate is 400 MHz. 1 GB PC3200 non-ECC modules are usually made with sixteen 512 Mbit chips, 8 down each side (512 Mbits 16 chips) / (8 bits (per byte)) = 1,024 MB. The individual chips making up a 1 GB memory module are usually organized with 64 Mbits and a data width of 8 bits for each chip, commonly expressed as 64M8. Memory manufactured in this way is low density RAM and will usually be compatible with any motherboard specifying PC3200 DDR-400 memory.[citation needed]

High density RAM

In the context of the 1 GB non-ECC PC3200 SDRAM module, there is very little visually to differentiate low density from high density RAM. High density DDR RAM modules will, like their low density counterparts, usually be double-sided with eight 512 Mbit chips per side. The difference is that for each chip, instead of being organized in a 64M8 configuration, it is organized with 128 Mbits and a data width of 4 bits, or 128M4. High density memory modules are assembled using chips from multiple manufacturers. These chips come in both the familiar 22 10 mm (approx.) TSOP2 and smaller squarer 12 9 mm (approx.) FBGA package sizes. High density chips can be identified by the numbers on each chip. High density RAM devices were designed to be used in registered memory modules for servers. JEDEC standards do not apply to high-density DDR RAM in desktop implementations.[citation needed] JEDEC's technical documentation, however, supports 128M4 semiconductors as such that contradicts 1284 being classified as high density. As such, high density is a relative term, which can be used to describe memory which is not supported by a particular motherboard's memory controller.[citation needed]

Variations
DDR SDRAM Standard DDR DDR2 Bus clock (MHz) Internal rate (MHz) Prefetch (min burst) 2n 4n Transfer Rate (MT/s) 200400 4001066 SODIMM Voltage DIMM pins pins 2.5/2.6 184 1.8 240 200 200 MicroDIMM pins 172 214

100200 100200 200533 100266

DDR3

4001066 100266

8n

8002133

1.5

240

204

214

DDR (DDR1) was superseded by DDR2 SDRAM, which had modifications for higher clock frequency and again doubled throughput, but operates on the same principle as DDR. Competing with DDR2 was Rambus XDR DRAM. DDR2 dominated due to cost and support factors. DDR2 was in turn superseded by DDR3 SDRAM which offered higher performance for increased bus speeds and new features. DDR3 will likely be superseded by DDR4 SDRAM, which was first produced in 2011 and whose standards are still in flux (2012) with significant architectural changes. DDR's prefetch buffer depth is 2(bits), while DDR2 uses 4. Although the effective clock rates of DDR2 are higher than DDR, the overall performance was no greater in the early implementations, primarily due to the high latencies of the first DDR2 modules. DDR2 started to be effective by the end of 2004, as modules with lower latencies became available.[11] Memory manufacturers stated that it was impractical to mass-produce DDR1 memory with effective transfer rates in excess of 400 MHz (i.e. 400MT/s and 200 MHz external clock) due to internal speed limitations. DDR2 picks up where DDR1 leaves off, utilizing internal clock rates similar to DDR1, but is available at effective transfer rates of 400 MHz and higher. DDR3 advances extended the ability to preserve internal clock rates while providing higher effective transfer rates by again doubling the prefetch depth. RDRAM was a particularly expensive alternative to DDR SDRAM, and most manufacturers dropped its support from their chipsets. DDR1 memory's prices substantially increased since Q2 2008 while DDR2 prices declined. In January 2009, 1 GB DDR1 was 23 times more expensive than 1 GB DDR2. High density DDR RAM will suit about 10% of PC motherboards on the market while low density will suit almost all motherboards on the PC Desktop market.

MDDR
MDDR is an acronym that some enterprises use for Mobile DDR SDRAM, a type of memory used in some portable electronic devices, like mobile phones, handhelds, and digital audio players. Through techniques including reduced voltage supply and advanced refresh options, Mobile DDR can achieve greater power efficiency.

DDR2 SDRAM

Two PC2-6400 modules encased in heat spreaders

PC2-6400 DDR2 SO-DIMM (for notebooks) DDR2 SDRAM is a double data rate synchronous dynamic random-access memory interface. It supersedes the original DDR SDRAM specification and has itself been superseded by DDR3 SDRAM. DDR2 is neither forward nor backward compatible with either DDR or DDR3. In addition to double pumping the data bus as in DDR SDRAM (transferring data on the rising and falling edges of the bus clock signal), DDR2 allows higher bus speed and requires lower power by running the internal clock at half the speed of the data bus. The two factors combine to require a total of four data transfers per internal clock cycle. With data being transferred 64 bits at a time, DDR2 SDRAM gives a transfer rate of (memory clock rate) 2 (for bus clock multiplier) 2 (for dual rate) 64 (number of bits transferred) / 8 (number of bits/byte). Thus with a memory clock frequency of 100 MHz, DDR2 SDRAM gives a maximum transfer rate of 3200MB/s. Since the DDR2 internal clock runs at half the DDR external clock rate, DDR2 memory operating at the same external data bus clock rate as DDR results in DDR2 being able to provide the same bandwidth but with higher latency. Alternatively, DDR2 memory operating at twice the external data bus clock rate as DDR may provide twice the bandwidth with the same latency. The best-rated DDR2 memory modules are at least twice as fast as the best-rated DDR memory modules.

Overview

Comparison of memory modules for desktop PCs (DIMM).

Comparison of memory modules for portable/mobile PCs (SO-DIMM). Like all SDRAM implementations, DDR2 stores data in memory cells that are activated with the use of a clock signal to synchronize their operation with an external data bus. Like DDR before it, the DDR2 I/O buffer transfers data both on the rising and falling edges of the clock signal (a technique called "double pumping"). The key difference between DDR and DDR2 is that for DDR2 the memory cells are clocked at 1 quarter (rather than half) the rate of the bus. This requires a 4-bit-deep prefetch queue, but, without changing the memory cells themselves, DDR2 can effectively operate at twice the bus speed of DDR. DDR2's bus frequency is boosted by electrical interface improvements, on-die termination, prefetch buffers and off-chip drivers. However, latency is greatly increased as a trade-off. The DDR2 prefetch buffer is 4 bits deep, whereas it is two bits deep for DDR and eight bits deep for DDR3. While DDR SDRAM has typical read latencies of between 2 and 3 bus cycles, DDR2 may have read latencies between 4 and 6 cycles. Thus, DDR2 memory must be operated at twice the data rate to achieve the same latency. Another cost of the increased bandwidth is the requirement that the chips are packaged in a more expensive and more difficult to assemble BGA package as compared to the TSSOP package of the previous memory generations such as DDR SDRAM and SDR SDRAM. This packaging change was necessary to maintain signal integrity at higher bus speeds. Power savings are achieved primarily due to an improved manufacturing process through die shrinkage, resulting in a drop in operating voltage (1.8 V compared to DDR's 2.5 V). The lower memory clock frequency may also enable power reductions in applications that do not require the highest available data rates. According to JEDEC[1] the maximum recommended voltage is 1.9 volts and should be considered the absolute maximum when memory stability is an issue (such as in servers or other mission critical devices). In addition, JEDEC states that memory modules must withstand up to 2.3 volts before incurring permanent damage (although they may not actually function correctly at that level).

Specification standards

Chips and modules

For use in computers, DDR2 SDRAM is supplied in DIMMs with 240 pins and a single locating notch. Laptop DDR2 SO-DIMMs have 200 pins and often come identified by an additional S in their designation. DIMMs are identified by their peak transfer capacity (often called bandwidth). Standard name Memory clock
(MHz)

Cycle time
(ns)

I/O bus Data clock rate

(MHz) (MT/s)

Module name

Peak Timings[2][3] CAS transfer rate latency

(MB/s) (CL-tRCDtRP) (ns)

DDR2-400B 100 DDR2-400C DDR2-533B 133 DDR2-533C DDR2-667C 166 DDR2-667D DDR2-800C DDR2-800D 200 DDR2-800E DDR21066E DDR21066F 266

10 7 6 5

200 266 333 400

400 533 666 800

PC2-3200 3200 PC24200* PC25300* 4266 5333

3-3-3 4-4-4 3-3-3 4-4-4 4-4-4 5-5-5 4-4-4 5-5-5 6-6-6 6-6-6 7-7-7

15 20 11 15 12 15 10 12 15 11 13

PC2-6400 6400

533

1066

PC28500*

8533

* Some manufacturers label their DDR2 modules as PC2-4300, PC2-5400 or PC2-8600 instead of the respective names suggested by JEDEC. At least one manufacturer has reported this reflects successful testing at a higher-than standard data rate[4] whilst others simply round up for the name. Note: DDR2-xxx denotes data transfer rate, and describes theoretical bandwidth (with the last two digits truncated), Bandwidth is calculated by taking transfers per second and memory modules transfer data on a bus that is 64 data bits equates to 8 bytes of data per transfer. In addition to bandwidth and capacity variants, modules can 1. Optionally implement ECC, which is an extra data byte lane used for correcting minor errors and detecting major errors for better reliability. Modules with ECC are identified by an additional ECC in their designation. PC2-4200 ECC is a PC2-4200 module with ECC. 2. Be "registered" ("buffered"), which improves signal integrity (and hence potentially clock rates and physical slot capacity) by electrically buffering the signals at a cost of an extra clock of increased latency. Those modules are identified by an additional R in their designation, whereas non-registered (a.k.a. "unbuffered") RAM may be identified by an additional U in the designation. PC2-4200R is a registered PC2-4200 module, PC2-4200R ECC is the same module but with additional ECC. 3. Be fully buffered modules, which are designated by F or FB and do not have the same notch position as other classes. Fully buffered modules cannot be used with motherboards that are made for registered modules, and the different notch position physically prevents their insertion. Note: registered and un-buffered SDRAM generally cannot be mixed on the same channel. raw DDR chips, whereas PC2-xxxx denotes and is used to describe assembled DIMMs. multiplying by eight. This is because DDR2 wide, and since a byte comprises 8 bits, this

Note that the highest-rated DDR2 modules in 2009 operate at 533 MHz (1066 MT/s), compared to the highest-rated DDR modules operating at 200 MHz (400 MT/s). At the same time, the CAS latency of 11.2 ns = 6 / (Bus clock rate) for the best PC2-8500 modules is comparable to that of 10 ns = 4 / (Bus clock rate) for the best PC-3200 modules.

Debut
DDR2 was introduced in the second quarter of 2003 at two initial clock rates: 200 MHz (referred to as PC23200) and 266 MHz (PC2-4200). Both performed worse than the original DDR specification due to higher latency, which made total access times longer. However, the original DDR technology tops out at a clock rate around 200 MHz (400 MT/s). Higher performance DDR chips exist, but JEDEC has stated that they will not be standardized. These modules are mostly manufacturer optimizations of highest-yielding chips, drawing significantly more power than slower-clocked modules, and usually do not offer much, if any, greater real-world performance. DDR2 started to become competitive with the older DDR standard by the end of 2004, as modules with lower latencies became available.[5]

Backward compatibility
DDR2 DIMMs are not designed to be backward compatible with DDR DIMMs. The notch on DDR2 DIMMs is in a different position from DDR DIMMs, and the pin density is higher than DDR DIMMs in desktops. DDR2 is a 240-pin module, DDR is a 184-pin module. Notebooks have 200-pin modules for DDR and DDR2, however the notch on DDR modules is in a slightly different position than that on DDR2 modules. Higher-speed DDR2 DIMMs are compatible with lower-speed DDR2 DIMMs although the motherboard or CPU memory controller will be bound to the limits of the lower-performance modules

DDR3 SDRAM

PC3-10600 DDR3 SO-DIMM (204 pins) In computing, DDR3 SDRAM, an abbreviation for double data rate type three synchronous dynamic random access memory, is a modern kind of dynamic random access memory (DRAM) with a high bandwidth interface, and has been in use since 2007. DDR3 SDRAM is neither forward nor backward compatible with any earlier type of random access memory (RAM) due to different signaling voltages, timings, and other factors. DDR3 is a DRAM interface specification. The actual DRAM arrays that store the data are similar to earlier types, with similar performance.

The primary benefit of DDR3 SDRAM over its immediate predecessor, DDR2 SDRAM, is its ability to transfer data at twice the rate (eight times the speed of its internal memory arrays), enabling higher bandwidth or peak data rates. With two transfers per cycle of a quadrupled clock, a 64-bit wide DDR3 module may achieve a transfer rate of up to 64 times the memory clock speed in megabytes per second (MB/s). With data being transferred 64 bits at a time per memory module, DDR3 SDRAM gives a transfer rate of (memory clock rate) 4 (for bus clock multiplier) 2 (for data rate) 64 (number of bits transferred) / 8 (number of bits/byte). Thus with a memory clock frequency of 100 MHz, DDR3 SDRAM gives a maximum transfer rate of 6400 MB/s. In addition, the DDR3 standard permits chip capacities of up to 8 gigabytes.

Overview

Comparison of memory modules for desktop PCs (DIMM).

Comparison of memory modules for portable/mobile PCs (SO-DIMM). Compared to DDR2 memory, DDR3 memory uses 30% less power. This reduction comes from the difference in supply voltages: 1.8V or 2.5V for DDR2, and 1.5V for DDR3. The 1.5 V supply voltage works

well with the 90 nanometer fabrication technology used in the original DDR3 chips. Some manufacturers further propose using "dual-gate" transistors to reduce leakage of current.[1] According to JEDEC[2], 1.575 volts should be considered the absolute maximum when memory stability is the foremost consideration, such as in servers or other mission-critical devices. In addition, JEDEC states that memory modules must withstand up to 1.975 volts before incurring permanent damage, although they are not required to function correctly at that level. The main benefit of DDR3 comes from the higher bandwidth made possible by its prefetch buffer, which is 8-burst-deep. In contrast, the prefetch buffer of DDR2 is 4-burst-deep, and the prefetch buffer of DDR is 2burst-deep. DDR3 modules can transfer data at a rate of 8002133 MT/s using both rising and falling edges of a 400 1066 MHz I/O clock. Sometimes, a vendor may misleadingly advertise the I/O clock rate by labeling the MT/s as MHz. The MT/s is normally twice that of MHz by double sampling, one on the rising clock edge, and the other, on the falling. In comparison, DDR2's current range of data transfer rates is 400 1066 MT/s using a 200533 MHz I/O clock, and DDR's range is 200400 MT/s based on a 100200 MHz I/O clock. High-performance graphics was an initial driver of such bandwidth requirements, where high bandwidth data transfer between framebuffers is required. DDR3 does use the same electric signaling standard as DDR and DDR2, Stub Series Terminated Logic, albeit at different timings and voltages. Specifically, DDR3 uses SSTL_15.[3] DDR3 prototypes were announced in early 2005. Products in the form of motherboards appeared on the market in June 2007[4] based on Intel's P35 "Bearlake" chipset with DIMMs at bandwidths up to DDR31600 (PC3-12800).[5] The Intel Core i7, released in November 2008, connects directly to memory rather than via a chipset. The Core i7 supports only DDR3. AMD's first socket AM3 Phenom II X4 processors, released in February 2009, were their first to support DDR3. DDR3 DIMMs have 240 pins and are electrically incompatible with DDR2. The two are prevented from being accidentally interchanged by different key notch positions on the DIMMs.[6] DDR3 SO-DIMMs have 204 pins.[7] GDDR3 memory, sometimes incorrectly referred to as "DDR3" due to its similar name, is an entirely different technology, as it is designed for use in graphics cards and is based on DDR2 SDRAM.

DDR3L
The "L" in DDR3L stands for low-voltage. JEDEC introduced two low-voltage standards. The DDR3L standard is 1.35V and has the label PC3L for its modules. Examples include DDR3L800, DDR3L1066, DDR3L1333, and DDR3L1600. The DDR3U standard is 1.25V and has the label PC3U for its modules.

Latencies
While the typical latencies for a JEDEC DDR2 device were 5-5-5-15, some standard latencies for JEDEC DDR3 devices include 7-7-7-20 for DDR3-1066 and 8-8-8-24 for DDR3-1333. DDR3 latencies are numerically higher because the I/O bus clock cycles by which they are measured are shorter; the actual time interval is similar to DDR2 latencies (around 10 ns). There is some improvement

because DDR3 generally uses more recent manufacturing processes, but this is not directly caused by the change to DDR3. As with earlier memory generations, faster DDR3 memory became available after the release of the initial versions. DDR3-2000 memory with 9-9-9-28 latency (9 ns) was available in time to coincide with the Intel Core i7 release.[8] CAS latency of 9 at 1000 MHz (DDR3-2000) is 9 ns, while CAS latency of 7 at 667 MHz (DDR3-1333) is 10.5 ns. (CAS / Frequency (MHz)) 1000 = X ns Example: (7 / 667) 1000 = 10.4948 ns

Extensions
Intel Corporation officially introduced the eXtreme Memory Profile (XMP) Specification on March 23, 2007 to enable enthusiast performance extensions to the traditional JEDEC SPD specifications for DDR3 SDRAM.[9]

Modules
JEDEC standard modules
Standard name Memory clock
(MHz)

Cycle time
(ns)

I/O bus Data clock rate

(MHz) (MT/s)

Module name

Peak Timings transfer rate

(MB/s) (CL-tRCDtRP)

CAS latency
(ns)
1

DDR3-800D 100 DDR3-800E DDR31066E DDR31066F DDR31066G DDR31333F* DDR31333G DDR31333H DDR31333J* DDR31600G* DDR31600H

10

400

800

PC3-6400 6400

5-5-5 6-6-6 6-6-6 7-7-7 8-8-8

12 15 11 13 15

1 1

133

7 12

533

1066

PC3-8500 8533

4 8

166

666

1333

PC3-10600 10666

7-7-7 8-8-8 9-9-9 10-10-10

10 12 13 15

2 2

200

800

1600

PC3-12800 12800

8-8-8 9-9-9 10-10-10 11-11-11

10 11 12 13 34

1 1

4 2

DDR31600J DDR31600K DDR31866J* DDR31866K DDR31866L DDR31866M* DDR32133K* DDR32133L DDR32133M DDR32133N* * optional CL - Clock cycles between sending a column address to the memory and the beginning of the data in response tRCD - Clock cycles between row activate and reads/writes tRP - Clock cycles between row precharge and activate Fractional frequencies are normally rounded down, but rounding up to -667 is common due to the exact number being -666 and rounding to the nearest whole number. Some manufacturers also round to a certain precision or round up instead. For example, PC3-10666 memory could be listed as PC3-10600 or PC310700.[10] Note: All items listed above are specified by JEDEC as JESD79-3D.[11] All RAM data rates in-between or above these listed specifications are not standardized by JEDECoften they are simply manufacturer optimizations using higher-tolerance or overvolted chips. Of these non-standard specifications, the highest reported speed reached was equivalent to DDR3-2544, as of May 2010.[12] DDR3-xxx denotes data transfer rate, and describes raw DDR chips, whereas PC3-xxxx denotes theoretical bandwidth (with the last two digits truncated), and is used to describe assembled DIMMs. Bandwidth is calculated by taking transfers per second and multiplying by eight. This is because DDR3 memory modules transfer data on a bus that is 64 data bits wide, and since a byte comprises 8 bits, this equates to 8 bytes of data per transfer. In addition to bandwidth and capacity variants, modules can

233

4 27

933

1866

PC3-14900 14933

10-10-10 11-11-11 12-12-12 13-13-13

5 10 7 11 11 14 6 12 7 13 1314

266

3 34

1066

2133

PC3-17000 17066

11-11-11 12-12-12 13-13-13 14-14-14

10 11 12 13 18

16 4 3 16
1

1. Optionally implement ECC, which is an extra data byte lane used for correcting minor errors and detecting major errors for better reliability. Modules with ECC are identified by an additional ECC or E in their designation. For example: "PC3-6400 ECC", or PC3-8500E.[13] 2. Be "registered", which improves signal integrity (and hence potentially clock rates and physical slot capacity) by electrically buffering the signals with a register, at a cost of an extra clock of increased latency. Those modules are identified by an additional R in their designation, whereas non-registered (a.k.a. "unbuffered") RAM may be identified by an additional U in the designation. PC3-6400R is a registered PC3-6400 module, and PC3-6400R ECC is the same module with ECC. 3. Be fully buffered modules, which are designated by F or FB and do not have the same notch position as other classes. Fully buffered modules cannot be used with motherboards that are made for registered modules, and the different notch position physically prevents their insertion.

Feature summary
DDR3 SDRAM components

Introduction of asynchronous RESET pin Support of system-level flight-time compensation On-DIMM mirror-friendly DRAM pinout Introduction of CWL (CAS write latency) per clock bin On-die I/O calibration engine READ and WRITE calibration

DDR3 modules

Fly-by command/address/control bus with on-DIMM termination High-precision calibration resistors Are not backwards compatibleDDR3 modules do not fit into DDR2 sockets; forcing them can damage the DIMM and/or the motherboard[14]

Technological advantages compared to DDR2

Higher bandwidth performance, up to 2133 MT/s standardized Slightly improved latencies, as measured in nanoseconds Higher performance at low power (longer battery life in laptops) Enhanced low-power features

Development and market penetration

In May 2005, Desi Rhoden, chairman of the JEDEC committee responsible for creating the DDR3 standard, stated that DDR3 had been under development for "about 3 years".[15] DDR3 was launched in 2007, but sales were not expected to overtake DDR2 until the end of 2009, or possibly early 2010, according to Intel strategist Carlos Weissenberg, speaking during the early part of their roll-out in August 2008.[16] (The same timescale for market penetration had been stated by market intelligence company DRAMeXchange over a year earlier in April 2007,[17] and by Desi Rhoden in 2005.[15]) The primary driving force behind the increased usage of DDR3 has been new Core i7 processors from Intel and Phenom II processors from AMD, both of which have internal memory controllers: the latter recommends DDR3, the former requires it. IDC stated in January 2009 that DDR3 sales will account for 29 percent of the total DRAM units sold in 2009, rising to 72% by 2011.[18]

DDR4 SDRAM
.

The first DDR4 memory module was manufactured by Samsung and announced in January 2011. In computing, DDR4 SDRAM, an abbreviation for double data rate type four synchronous dynamic random-access memory, is a type of dynamic random-access memory (DRAM) with a high bandwidth interface currently under development and expected to be released to market in 2012.[1][2] As a "next generation" successor to DDR3 SDRAM, it is one of several variants of DRAM which have been in use since the early 1970s.[3] It is not directly compatible with any earlier type of random access memory (RAM) due to different signaling voltages, timings, physical interface, and other factors. DDR4 itself is a DRAM interface specification. Its primary benefits compared to DDR3 include a higher range of clock frequencies and data transfer rates (21334266 MT/s compared to DDR3's 800 and higher[4][5][6]) and significantly lower voltage (1.051.2 V for DDR4,[5] compared to 1.21.5 V for DDR3). DDR4 also anticipates a change in topology. It discards the multiple DIMMs per channel approach in favor of a point-to-point topology where each channel in the memory controller is connected to a single DIMM.[5][7] Switched memory banks are also an anticipated option for servers.[5]

Development and market history

Standards body JEDEC began working on a successor to DDR3 around 2005,[8] about 2 years before the launch of DDR3 in 2007.[9][10] The high-level architecture of DDR4 was planned for completion in 2008.[11] The final specification is expected in mid-2012.[12] Some advance information was published in 2007,[13] and a guest speaker from Qimonda provided further public details in a presentation at the August 2008 San Francisco Intel Developer Forum (IDF).[13][14][15][16] DDR4 was described as involving a 30 nm process at 1.2 volts, with bus frequencies of 2133 MT/s "regular" speed and 3200 MT/s "enthusiast" speed, and reaching market in 2012, before transitioning to 1 volt in 2013.[14][16] Subsequently, further details were revealed at MemCon 2010, Tokyo (a computer memory industry event), at which a presentation by a JEDEC director titled "Time to rethink DDR4" [17] with a slide titled "New roadmap: More realistic roadmap is 2015" led some websites to report that the introduction of DDR4 was probably[18] or definitely[19][20] delayed until 2015. However, DDR4 test samples were announced in line with the original schedule in early 2011 at which time manufacturers began to advise that large scale commercial production and release to market was scheduled for 2012.[1] DDR4 is expected to represent 5% of the DRAM market in 2013,[1] and to reach mass market adoption and 50% market penetration around 2015;[1] the latter is comparable with the approximately 5 years taken for DDR3 to achieve mass market transition over DDR2.[5] In part, this is because changes required to other

components would impact all other parts of computer systems, which would need to be updated to work with DDR4.[4] In February 2009, Samsung validated 40 nm DRAM chips, considered a "significant step" towards DDR4 development[21] since in 2009, DRAM chips were only beginning to migrate to a 50 nm process.[22] In January 2011, Samsung announced the completion and release for testing of a 2 GB DDR4 DRAM module based on a process between 30 and 39 nm.[23] It has a maximum data transfer rate of 2133 Mb/s at 1.2 V, uses pseudo open drain technology (adapted from graphics DDR memory[24]) and draws 40% less power than an equivalent DDR3 module.[23][25][26] Three months later in April 2011, Hynix announced the production of 2 GB DDR4 modules at 2400 MT/s, also running at 1.2 V on a process between 30 and 39 nm (exact process unspecified),[1] adding that it anticipated commencing high volume production in the second half of 2012.[1] Semiconductor processes for DDR4 are expected to transition to sub-30 nm at some point between late 2012 and 2014.[5][27] In May 2012 Micron announced[2] it is aiming at starting production in late 2012 of 30 nm modules. In July 2012, Samsung Electronics Co., Ltd., announced that it has begun sampling the industry's first 16GB registered dual inline memory modules (RDIMMs) using DDR4 SDRAM for enterprise server systems.[28][29]

Technical description
The new chips are expected to run at 1.2 V or less,[30][31] versus the 1.5 V of DDR3 chips, and are capable of at least 2.13 billion data transfers per second. They are expected to be introduced at transfer rates of 2133 MT/s, estimated to rise to a potential 4266 MT/s [4] and lowered voltage of 1.05 V [32] by 2013. DDR4 is likely to be initially commercialized using 32 36 nm processes,[4] and according to a roadmap by PC Watch (Japan) and comments by Samsung, as 4 Gbit chips.[23][27] Increased memory density was also anticipated, possibly using TSV ("through-silicon via") or other 3D stacking processes.[4][5][7][33] The DDR4 specification will include standardized 3D stacking "from the start" according to JEDEC. [33] Xbit Labs commented that "as a result DDR4 memory chips with very high density will become relatively inexpensive".[4] Prefetch an 8n prefetch with bank groups, including the use of two or four selectable bank groups.[12] DDR4 also anticipates a change in topology. It discards the multi-drop bus approach used in previous generations in favor of point-to-point where each channel in the memory controller is connected to a single module.[5][7] This mirrors the trend also seen in the earlier transition from PCI to PCI Express, where parallelism was moved from the interface to the controller,[7] and is likely to simplify timing in modern high-speed data buses.[7] Switched memory banks are also an anticipated option for servers.[5][7] The minimum transfer rate of 2133 MT/s was said to be due to progress made in DDR3 speeds which, being likely to reach 2133 MT/s, left little commercial benefit to specifying DDR4 below this speed.[4][5] Techgage interpreted Samsung's January 2011 engineering sample as having CAS latency of 13 clock cycles, described as being comparable to the move from DDR2 to DDR3.[24] In 2008, concerns were raised in the book Wafer Level 3-D ICs Process Technology that non-scaling analog elements such as charge pumps and voltage regulators, and additional circuitry "have allowed significant increases in bandwidth but they consume much more die area". Examples include CRC error-detection, ondie termination, burst hardware, programmable pipelines, low impedance, and increasing need for sense

amps (attributed to a decline in bits per bitline due to low voltage). The authors noted that as a result, the amount of die used for the memory array itself has declined over time from 70-80% with SDRAM and DDR1, to 38% for DDR3 and potentially to less than 30% for DDR4.[34]

SIMM

30- (top) and 72-pin (bottom) SIMMs. Early 30-pin modules commonly had either 256 KB or 1 MB of memory.

A SIMM, or single in-line memory module, is a type of memory module containing random access memory used in computers from the early 1980s to the late 1990s. It differs from a dual in-line memory module (DIMM), the most predominant form of memory module today, in that the contacts on a SIMM are redundant on both sides of the module. SIMMs were standardised under the JEDEC JESD-21C standard.

30-pin SIMM, 256kB capacity

Most early PC motherboards (8088-based PCs, XTs, and early ATs) used socketed DIP chips. With the introduction of 286-based IBM XT/286, which could use larger amounts of memory, memory modules evolved to save motherboard space and to ease memory expansion. Instead of plugging in eight or nine single DIP DRAM chips, only one additional memory module was needed to increase the memory of the computer. A few 286-based computers used (often non-standard) memory modules like SIPP memory (single in-line pin package). The SIPP's 30 pins often bent or broke during installation, which is why they were quickly replaced by SIMMs which used contact plates rather than pins. SIMMs were invented and patented by Wang Laboratories. Wang invented what was to become the basic memory module, now known as a SIMM (single in-line memory module) in 1983. The original memory modules were built upon ceramic and had pins. Later the pins were removed and the modules were built on standard PCB material. The first variant of SIMMs has 30 pins and provides 8 bits of data (plus a 9th error-detection bit in parity SIMMs). They were used in AT (286), 386, 486, Macintosh Plus, Macintosh II, Quadra, Atari STE and Wang VS systems.

The second variant of SIMMs has 72 pins and provides 32 bits of data (36 bits in parity and ECC versions). These appeared first in the early 1990s in the IBM PS/2, and later in systems based on the 486, Pentium, Pentium Pro, early Pentium II, and contemporary/competing chips of other brands. By the mid 90s, 72-pin SIMMs had replaced 30-pin SIMMs in new-build computers, and were starting to themselves be replaced by DIMMs. Non-IBM PC computers such as UNIX workstations may use proprietary non-standard SIMMs. The Macintosh IIfx use proprietary non-standard SIMMs with 64 pins. DRAM technologies used in SIMMs include FPM (Fast Page Mode Memory, used in all 30-pin and early 72-pin modules), and the higher-performance EDO DRAM (used in later 72-pin modules). Due to the differing data bus widths of the memory modules and some processors, sometimes several modules must be installed in identical pairs or in identical groups of four to fill a memory bank. The general rule of thumb is a 286, 386SX, 68000 or low-end 68020 / 68030 (e.g. Atari, Mac LC) system (using a 16 bit wide data bus) would require two 30-pin SIMMs for a memory bank. On 386DX, 486, and full-spec 68020 through 68060 (e.g. Mac II) systems (32 bit data bus), either four 30-pin SIMMs or one 72-pin SIMM are required for one memory bank. On Pentium systems (data bus width of 64 bits), two 72-pin SIMMs are required. However, some Pentium systems have support for a "half bank mode", in which the data bus would be shortened to only 32-bits to allow operation of a single SIMM. Conversely, some 386 and 486 systems use what is known as "memory interleaving", which requires twice as many SIMMs and effectively doubles the bandwidth. The earliest SIMM sockets were conventional push-type sockets. These were soon replaced by ZIF sockets in which the SIMM was inserted at an angle, then tilted into an upright position. To remove one, the two metal or plastic clips at each end must be pulled to the side, then the SIMM must be tilted back and pulled out (low-profile sockets reversed this convention somewhat, like SODIMMs - the modules are inserted at a "high" angle, then pushed down to become more flush with the motherboard). The earlier sockets used plastic retainer clips which were found to break, so steel clips replaced them. Some SIMMs support presence detect (PD). Connections are made to some of the pins that encode the capacity and speed of the SIMM, so that compatible equipment can detect the properties of the SIMM. PD SIMMs can be used in equipment which does not support PD; the information is ignored. Standard SIMMs can easily be converted to support PD by fitting jumpers, if the SIMMs have solder pads to do so, or by soldering wires on.[1]

30-pin SIMMs

30-pin SIMM, 256 KB capacity

Standard sizes: 256 KB, 1 MB, 4 MB, 16MB 30-pin SIMMS have 12 address lines, which can provide a total of 24 address bits. With an 8 bit data width, this leads to an absolute maximum capacity of 16 MB for both parity and non-parity modules (the additional redundancy bit chip usually does not contribute to the useful capacity).

30-pin SIMM Memory Module Pin # Name Signal Description 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 VCC +5VDC Pin # Name Signal Description 16 DQ4 A8 A9 A10 DQ5 /WE VSS DQ6 A11 DQ7 QP* /RAS Data 4 Address 8 Address 9 Address 10 Data 5 Write Enable Ground Data 6 Address 11 Data 7 Data parity out Row Address Strobe

/CAS Column Address Strobe 17 DQ0 Data 0 A0 A1 Address 0 Address 1 18 19 20 21 22 23 24 25 26 27 28 29 30

DQ1 Data 1 A2 A3 VSS Address 2 Address 3 Ground

DQ2 Data 2 A4 A5 Address 4 Address 5

DQ3 Data 3 A6 A7 Address 6 Address 7

/CASP* Parity Column Address Strobe DP* VCC Data parity in +5VDC

Pins 26, 28 and 29 are not connected on non-parity SIMMs.

72-pin SIMMs

72-pin EDO DRAM SIMM

Standard sizes: 1 MB, 2 MB, 4 MB, 8 MB, 16 MB, 32 MB, 64 MB, 128 MB With 12 address lines, which can provide a total of 24 address bits, two ranks of chips, and 32 bit data output, the absolute maximum capacity is 227 = 128 MB.

5V 72-pin SIMM Memory Module Pin Name # 1 2 3 4 5 6 7 8 9 10 11 VSS MD0 MD16 MD1 MD17 MD2 MD18 MD3 MD19 VCC NU [PD5#] MA0 MA1 MA2 MA3 MA4 MA5 MA6 MA10 MD4 MD20 MD5 Signal Description Ground Data 0 Data 16 Data 1 Data 17 Data 2 Data 18 Data 3 Data 19 +5 VDC Pin Name # 37 38 39 40 41 42 43 44 45 46 MDP1* MDP3* VSS /CAS0 /CAS2 /CAS3 /CAS1 /RAS0 /RAS1 NC /WE Signal Description Data Parity 1 (MD8..15) Data Parity 3 (MD24..31) Ground Column Address Strobe 0 Column Address Strobe 2 Column Address Strobe 3 Column Address Strobe 1 Row Address Strobe 0 Row Address Strobe 1 Not Connected Read/Write Enable Not Connected [ECC presence (if grounded) (3v3)] Data 8 Data 24 Data 9 Data 25 Data 10 Data 26 Data 11 Data 27 Data 12 Data 28

Not Used [Presence Detect 5 47 (3v3)] Address 0 Address 1 Address 2 Address 3 Address 4 Address 5 Address 6 Address 10 Data 4 Data 20 Data 5 48 49 50 51 52 53 54 55 56 57 58

12 13 14 15 16 17 18 19 20 21 22

NC [/ECC#] MD8 MD24 MD9 MD25 MD10 MD26 MD11 MD27 MD12 MD28

23 24 25 26 27 28 29 30 31 32 33 34 35 36

MD21 MD6 MD22 MD7 MD23 MA7 MA11 VCC MA8 MA9 /RAS3 /RAS2 MDP2* MDP0*

Data 21 Data 6 Data 22 Data 7 Data 23 Address 7 Address 11 +5 VDC Address 8 Address 9 Row Address Strobe 3 Row Address Strobe 2 Data Parity 2 (MD16..23) Data Parity 0 (MD0..7)

59 60 61 62 63 64 65 66 67 68 69 70 71 72

VCC D29 MD13 MD30 MD14 MD31 MD15 NC [/EDO#] PD1x PD2x PD3x PD4x NC [PD(ref)#] VSS

+5 VDC Data 29 Data 13 Data 30 Data 14 Data 31 Data 15 Not Connected [EDO presence (if grounded) (3v3)] Presence Detect 1 Presence Detect 2 Presence Detect 3 Presence Detect 4 Not Connected [Presence Detect (ref) (3v3)] Ground

Pins 35, 36, 37 and 38 are not connected on non-parity SIMMs. [2] /RAS1 and /RAS3 are only used on two-rank SIMMS: 2, 8, 32, and 128 MB. These lines are only defined on 3.3V modules. Presence Detect signals are detailed in JEDEC Standard.

Proprietary SIMMs
GVP 64-pin
Several CPU cards from Great Valley Products for the Commodore Amiga used special 64-pin SIMMs (32 bits wide, 1, 4 or 16 MB, 60 ns).

Apple 64-pin
Dual-ported 64-pin SIMMs were used in Apple Macintosh IIfx computers to allow overlapping read/write cycles (1, 4, 8, 16 MB, 80 ns).[3][4]

5V 64-pin Mac IIfx SIMM Memory Module[5] Pin # Name Signal Description 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 GND Ground NC Not connected Pin # Name Signal Description 33 34 35 36 37 38 39 Q4 /W4 A8 NC A9 A10 A11 D5 Q5 /W5 NC NC Data output bus, bit 4 Write-enable input for RAM IC 4 Address bus, bit 8 Not connected Address bus, bit 9 Address bus, bit 10 Address bus, bit 11 Data input bus, bit 5 Data output bus, bit 5 Write-enable input for RAM IC 5 Not connected Not connected

+5V +5 volts +5V +5 volts /CAS Column address strobe D0 Q0 /W0 A0 NC A1 D1 Q1 /W1 A2 NC A3 Data input bus, bit 0 Data output bus, bit 0

Write-enable input for RAM IC 0 40 Address bus, bit 0 Not connected Address bus, bit 1 Data input bus, bit 1 Data output bus, bit 1 41 42 43 44 45

GND Ground D6 Q6 /W6 NC D7 Q7 /W7 /QB NC Data input bus, bit 6 Data output bus, bit 6 Write-enable input for RAM IC 6 Not connected Data input bus, bit 7 Data output bus, bit 7 Write-enable input for RAM IC 7 Reserved (parity) Not connected

Write-enable input for RAM IC 1 46 Address bus, bit 2 Not connected Address bus, bit 3 47 48 49 50 51 52 53

GND Ground GND Ground D2 Q2 /W2 A4 Data input bus, bit 2 Data output bus, bit 2

Write-enable input for RAM IC 2 54 Address bus, bit 4 55

/RAS Row address strobe

24 25 26 27 28 29 30 31 32

NC A5 D3 Q3 /W3 A6 NC A7 D4

Not connected Address bus, bit 5 Data input bus, bit 3 Data output bus, bit 3

56 57 58 59

NC NC Q

Not connected Not connected Parity-check output

/WWP Write wrong parity PDCI Parity daisy-chain input +5V +5V +5 volts +5 volts

Write-enable input for RAM IC 3 60 Address bus, bit 6 Not connected Address bus, bit 7 Data input bus, bit 4 61 62 63 64

PDCO Parity daisy-chain output GND Ground