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    Diagrama Xbox360

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    HILARIO
    The document appears to be a schematic for a system called Xenon. It consists of 64 pages covering different components of the system including the CPU, GPU, memory, Ethernet, audio, and power delivery. Page 1 is a cover page with release information. The pages are organized by component or subsystem, with page numbers and titles listed in the contents section. Diagrams on the early pages cover the clocking structure and reset/enable signals. Later pages describe power delivery and voltage regulation, debug interfaces, and mounting details.

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as PDF, TXT or read online from Scribd

    Diagrama Xbox360

    Uploaded by

    HILARIO
    39K views67 pages
    The document appears to be a schematic for a system called Xenon. It consists of 64 pages covering different components of the system including the CPU, GPU, memory, Ethernet, audio, and power delivery. Page 1 is a cover page with release information. The pages are organized by component or subsystem, with page numbers and titles listed in the contents section. Diagrams on the early pages cover the clocking structure and reset/enable signals. Later pages describe power delivery and voltage regulation, debug interfaces, and mounting details.

    Original Description:

    Diagrama Xbox 360

    Original Title

    Diagrama xbox360

    Copyright

    © Attribution Non-Commercial (BY-NC)

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    PDF, TXT or read online from Scribd

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    The document appears to be a schematic for a system called Xenon. It consists of 64 pages covering different components of the system including the CPU, GPU, memory, Ethernet, audio, and power delivery. Page 1 is a cover page with release information. The pages are organized by component or subsystem, with page numbers and titles listed in the contents section. Diagrams on the early pages cover the clocking structure and reset/enable signals. Later pages describe power delivery and voltage regulation, debug interfaces, and mounting details.

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    39K views67 pages

    Diagrama Xbox360

    Uploaded by

    HILARIO
    The document appears to be a schematic for a system called Xenon. It consists of 64 pages covering different components of the system including the CPU, GPU, memory, Ethernet, audio, and power delivery. Page 1 is a cover page with release information. The pages are organized by component or subsystem, with page numbers and titles listed in the contents section. Diagrams on the early pages cover the clocking structure and reset/enable signals. Later pages describe power delivery and voltage regulation, debug interfaces, and mounting details.

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    of 67
    At a glance
    Powered by AI
    The document describes a circuit schematic for a device, outlining various components and their connections as well as design rules and conventions.

    The main components described include the CPU, GPU, memory, Southbridge, voltage regulators, and debug/test circuitry.

    Design rules mentioned include grouping signals, inputs on the left and outputs on the right, suffix conventions for signals, and page organization.

    SCHEMATIC REV PB NUMBER VER BOM RELEASE DATE

    K7 X803600-011 RETAIL XX/XX/XX


    PAGE CONTENTS PAGE CONTENTS
    [1] COVER PAGE [33] SB, PCIEX + SMM GPIO + JTAG
    [2] CLOCK DIAGRAM [34] SB, SMC
    [3] RESET/ENABLE DIAGRAM [35] SB, FLASH + USB + SPI
    [4] CPU, CLOCKS + EEPROM + STRAPPING [36] SB, ETHERNET + AUDIO + SATA
    [5] CPU, FSB [37] SB, STANDBY POWER + DECOUPLE

    XENON
    [6] CPU, FSB POWER + PLL POWER [38] SB, MAIN POWER + DECOUPLE
    [7] CPU, CORE POWER [39] SB OUT, ETHERNET
    [8] CPU, POWER [40] SB OUT, AUDIO
    [9] CPU, DECOUPLING [41] SB OUT, FLASH
    [10]
    [11]
    [12]
    CPU, DECOUPLING
    CPU, DECOUPLING
    GPU, FSB
    [42]
    [43]
    [44]
    SB OUT, FAN + INFRARED + BUTTONS
    CONN, AVIP
    CONN, RJ45 + USB COMBO
    RETAIL
    [13]
    [14]
    GPU, VIDEO + PCIEX + EEPROM
    GPU, MEMORY CONTROLLER A + B
    [45]
    [46]
    CONN, GAME PORTS + MEMORY PORTS
    BACKUP CLOCK + V_5P0 DUAL
    REV K7
    [15]
    [16]
    GPU, MEMORY CONTROLLER C + D
    GPU, PLL POWER + FSB POWER
    [47]
    [48]
    CONN, ODD AND HDD
    CONN, ARGON + POWER FAB K
    [17] GPU, CORE POWER + MEM POWER [49] VREGS, INPUT + OUTPUT FILTERS
    [18] GPU, DECOUPLING [50] VREGS, CPU CONTROLLER
    [19] DUAL ETHERNET PHY [51] VREGS, GPU OUTPUT PHASE 1,2,3
    [20] MEMORY, A (TOP) [52] VREGS, GPU CONTROLLER
    [21] MEMORY, A MIRRORED (BOTTOM) [53] VREGS, GPU OUTPUT PHASE 1,2
    [22] MEMORY, B (TOP) [54] VREGS, SWITCHED 1.8, 5.0V
    [23] MEMORY, B MIRRORED (BOTTOM) [55] VREGS, LINEAR REGULATORS
    [24] MEMORY, C (TOP) [56] XDK, DEBUG CONN
    [25] MEMORY, C MIRRORED (BOTTOM) [57] DEBUG BOARD, CPU + GPU BREAKOUT
    [26] MEMORY, D (TOP) [58] DEBUG BOARD, CPU CONN
    [27] MEMORY, D MIRRORED (BOTTOM) [59] DEBUG BOARD, CPU CONN + TERM
    [28] ANA, CLOCKS + STRAPPING [60] DEBUG BOARD, CPU TERM
    [29] ANA, VIDEO + FAN + JTAG [61] DEBUG BOARD, TITAN + YETI CONN
    [30] ANA, POWER + DECOUPLING [62] DEBUG BOARD, GPU CONN + TERM
    [31] DEBUG MAPPING, WN DBG VS WN XDK [63] XDK, LEDS
    [32] POWER TRACE EMI CAPS [64] LABELS AND MOUNTING

    RULES:
    1.)
    2.)
    3.)
    (APPLIED WHEN POSSIBLE)
    MSB TO LSB IS TOP TO BOTTOM
    WHEN POSSIBLE: INPUTS
    ORDER OF PAGES=CHIP
    ON LEFT,
    INTERFACES,
    OUTPUTS ON RIGHT
    TERMINATION, POWER, DECOUPLING PLEASE REFER
    XENONTO THE XENON DESIGN SPEC
    4.) AVOID USING OFF PAGE CONNECTORS FOR ON PAGE CONNECTIONS
    5.) LANED SIGNALS ARE GROUPED ON SYMBOLS
    6.) TRANSIMITTER NAME USED AS PREFIX WITH RX AND TX CONNECTIONS
    7.) SUFFIX V_ IS USED FOR VOLTAGE RAIL SIGNAL NAMES
    8.) SUFFIX _DP AND _DN ARE USED FOR DIFFERIENTAL PAIRS BOM RELEASE DATE XX/XX/XX PB NUMBER X803600-011
    9.) UNNAMED NETS ARE NAMED WITH /2 TEXT SIZE SIGNATURE DATE
    10.) SUFFIX _N FOR ACTIVE LOW OR N JUNCTION
    12.)
    13.)
    SUFFIX
    SUFFIX
    _P FOR P JUNCTION
    _EN FOR ENABLE
    DRN BY MICROSOFT XBOX
    14.) 'CLK' FOR CLOCKS, 'RST' FOR RESETS CHK BY TITLE
    15.) PWRGD FOR POWER GOOD SCH, PBA, XENON
    ENGR
    APVD
    DRAWING
    PROJECT NAME PAGE REV
    XENON_FABK APVD MICROSOFT
    [PAGE_TITLE=COVER PAGE] Wed Aug 24 09:41:55 2005
    APVD
    CONFIDENTIAL
    XENON_RETAIL 1/73 K7
    RJ45/USB AVIP
    CONN CONN POWER
    FAN CONN
    CONN

    ENET
    ENET_CLK(25MHZ) CLOCK DIAGRAM
    PHY

    I2S_MCLK(12.288MHZ) AUDIO ANA_XTAL_IN(27MHZ)


    I2S_BCLK(3.072MHZ) DAC

    GPU VR
    DEBUG
    CONN ANA
    ANA
    BCKUP
    STBY_CLK(48MHZ) GPU VR
    CNTL
    SB SATA_CLK_REF(25MHZ)
    SATA_CLK_DP/DN(100MHZ)
    DVD PCIEX_CLK_DP/DN(100MHZ)
    SATA AUD_CLK(24.576MHZ)
    CONN CPU_CLK_DP/DN(100MHZ) RISCWATCH
    PIX_CLK_OUT_DP/DN(100MHZ) CONN
    GPU_CLK_DP/DN (100MHZ)
    DVD
    PWR
    CONN MC_CLK1_DP/DN(800MHZ)
    MC_CLK0_DP/DN(800MHZ)
    ANA
    BCKUP MEM
    CLAM C+D
    MD_CLK1_DP/DN(800MHZ)
    MD_CLK0_DP/DN(800MHZ)
    GPU CPU CPU
    VR

    MA_CLK1_DP/DN(800MHZ)
    MA_CLK0_DP/DN(800MHZ)
    MB_CLK1_DP/DN(800MHZ)
    MB_CLK0_DP/DN(800MHZ)
    1P8 VR

    FLSH

    HDD
    CONN

    TITAN JTAG
    3P3 VR CONN

    VMEM VR MEM EFUSE VR


    CLAM A+B CPU VR
    5P0 VR CNTL
    MPORT VR

    GAME
    CONN

    IR EJECT MEM MEM BIND ARGON


    SW CONN CONN SW CONN

    DRAWING
    PROJECT NAME PAGE REV
    XENON_FABK MICROSOFT
    <PAGE_TITLE=CLOCK DIAGRAM> Wed Jul 27 21:53:30 2005 XENON_RETAIL 2/73 K7
    CONFIDENTIAL
    RJ45/USB AVIP
    CONN CONN POWER
    FAN CONN
    CONN

    RESET/ENABLE DIAGRAM
    EXT_PWR_ON_N
    ENET AUD_CLAMP
    PHY ENET_RST_N AUDIO PSU_V12P0_EN
    AUD_RST_N DAC

    GPU VR
    ANA_CLK_OE
    ANA_RST_N
    ANA VREG_GPU_EN_N
    GPU VR
    CNTL
    SMC_RST_N
    SB_RST_N

    DVD
    SATA
    SB VREG_GPU_PWRGD
    EXT_PWR_ON_N
    CONN CPU_CHECKSTOP_N
    CPU_RST_N
    CPU_PWRGD
    GPU_RST_N RISCWATCH
    DVD GPU_RST_DONE CONN
    PWR
    SMC_DBG_EN

    CONN
    VREG_CPU_PWRGD

    MEM_RST CPU
    VREG_3P3_EN

    VR
    MEM_SCAN_EN
    MEM
    CLAM C+D
    MEM_SCAN_TOP_EN
    MEM_SCAN_BOT_EN
    GPU CPU

    MEM_SCAN_TOP_EN
    MEM_SCAN_BOT_EN
    MEM_SCAN_EN
    MEM_RST
    HDD 3P3
    CONN VR
    CPU_PWRGD

    TITAN JTAG
    MEM CONN
    DEBUG CLAM A+B
    CONN VREG_1P8_EN_N VMEM VR EFUSE VR
    VREG_5P0_EN_N CPU VR
    5P0 VR CNTL
    VREG_EFUSE_EN
    VREG_CPU_EN
    GAME
    CONN

    IR EJECT MEM MEM BIND ARGON


    SW CONN CONN SW CONN

    DRAWING
    PROJECT NAME PAGE REV
    MICROSOFT
    [PAGE_TITLE=RESET/ENABLE DIAGRAM] XENON_FABK
    Wed Jul 27 21:53:44 2005
    CONFIDENTIAL
    XENON_RETAIL 3/73 K7
    56 CPU_RST_V1P1_N
    OUT
    CPU_RST_N 1 R7R4 2
    CPU, CLOCKS + EEPROM + STRAPPING
    34 IN
    3.92K 1%
    402 CH 1 46 IN CPU_CLK_DP
    1 1 R7R16 2 C7R112 N: STUFF C?,C? WITH ZERO OHM R'S FOR WN
    FT2P11 FTP 360PF N: STUFF C?,C? WITH .01UF CAPS FOR SHIVA
    6.19K 1% 10%
    1 50V
    FT2P12 FTP 402 CH 2 NPO
    603
    CPU_PWRGD 1 R7R10 2 CPU_PWRGD_V1P1_N
    34 IN CPU_CLK_DN
    46 IN
    3.92K 1%
    402 CH 1
    V_GPUCORE 1 R7R11 2 C7R113 V_GPUCORE
    360PF U7D1 1 OF 10 IC
    6.19K 1% 10%
    V_GPUCORE 402 CH 50V TP7R1
    2 NPO CPU VERSION 20
    2 R6R4 1 603 PROBE
    AJ25 CORE_CLK_DP CORE_IF_BGR_PLL AK17 CPU_CORE_IF_BGR_PLL 1
    1K 5% TP6D1 AH25 2
    2 1
    1 402 CH CORE_CLK_DN
    1 PROBE R6D1 R6D2
    1 931 1.07K
    R6R9 R6R6 2 AJ2 HARD_RESET_B EFU_POWERON C6 VREG_EFUSE_EN OUT 55 SMT
    10K 2 R6R5 1 AF16 1% 1%
    10K 5% POWER_GOOD
    5% CH CH
    EMPTY 1K 5% SMT 402 402
    CH 402 CH FSB_CLK_DP AK23 FSB_CLK_DP FSB_HF_CLKOUT_DP AH22 CPU_FSB_HF_CLKOUT_DP 1 2
    402 FSB_CLK_DN CPU_FSB_HF_CLKOUT_DN OUT
    402 2 AK22 FSB_CLK_DN FSB_HF_CLKOUT_DN AJ22
    2 OUT
    CPU_FSB_CLK_SEL AG18 FSB_CLK_SEL FSB_IMPED_CAL_DP AK25 CPU_FSB_IMPED_CAL_DP
    FSB_IMPED_CAL_DN AK24 CPU_FSB_IMPED_CAL_DN
    CPU_EXT_CLK_EN AF18 EXT_CLK_EN
    1 TP7R3
    R6R8 CPU_PLL_BYPASS AH16 PROBE
    1 PLL_BYPASS AK14 CPU_RES0_DP 1
    10K RESISTOR0_DP
    5% 1 RESISTOR0_DN AK15 CPU_RES0_DN 2
    R6R7 CPU_PULSE_LIMIT_BYPASS AJ16 PULSE_LIMIT_BYPASS
    EMPTY 10K R7R17 TP7R4
    402 5% 10K 1 1 R7R24 2 SMT PROBE
    2 CPU_TRIGGER_IN AG16 TRIGGER_IN
    CH 5% R7D1 VDDS0_DP AH13 CPU_VDDS0_DP 1
    402 CH 10K 5% VDDS0_DN AK12 CPU_VDDS0_DN 2
    2 10K 402 CH TP7R2
    402 5% V_GPUCORE PROBE
    2 CH CPU_SYS_CONFIG0 AK3 SYS_CONFIG0 VDDS1_DP AJ4 CPU_VDDS1_DP SMT 1
    402 CPU_SYS_CONFIG1 AH1 SYS_CONFIG1 VDDS1_DN AK5 CPU_VDDS1_DN 2
    2
    CPU_POST_IN<0..4> SMT DB7R1
    0 AH10 POST_IN0
    TP
    OUT 1 AJ10 POST_IN1 CPU_PSRO0_OUT
    1 1 PSRO0_OUT AK16 1
    2 AK9 POST_IN2
    R7R15 R7R8 TP6R1 3 AK10 POST_IN3
    10K 10K PROBE 1
    4 AK11 POST_IN4
    5% 5% 1 2 CPU_ANL_1 R7R9
    EMPTY EMPTY 10K
    402 402 SMT 5%
    2 2 4 IN CPU_SPI_SI B3 SPI_SI SPI_CLK A2 CPU_SPI_CLK OUT 4
    B2 CPU_SPI_EN CH
    LAYOUT: MUST BE ACCESSIBLE SPI_EN OUT 4 402
    1 2 R6R10 1 SPI_SO A3 CPU_SPI_SO 4 2 2
    C6R46 CPU_ANL_1_R OUT
    1 10UF R6E1
    1 10% 5.11K 1% TEMP_P AK20 CPU_TEMP_P 29
    R7R6 6.3V 402 EMPTY IN 10K
    10K 2 AG24 ANL_1 TEMP_N AK21 CPU_TEMP_N 29 5%
    R7R7 EMPTY OUT
    5% 10K 1206 CPU_ANL_2 AF24 ANL_2 CH
    CH 5% VID0 C4 CPU_VREG_APS0 OUT 49 402
    402 CPU_SPARE0 AK1 B5 CPU_VREG_APS1 1
    CH SPARE0 VID1 OUT 49
    2 402 TP6R2 CPU_SPARE1 AJ1 A4 CPU_VREG_APS2
    SPARE1 VID2 OUT 49
    2 PROBE
    VID3 B4 CPU_VREG_APS3 49
    1 2 CPU_VREG_APS4 OUT
    CPU_TEST_EN AH4 TE VID4 A5 49
    V_GPUCORE OUT
    SMT VID5 C5 CPU_VREG_APS5 OUT 49
    1 1
    1 FTP FT7T5
    R7R14 X02046-002 1 FTP FT7T2 1
    FTP FT7T4
    10K J7F1 1 FTP FT7T1 1
    FTP FT7T3
    5% 2X3HDR FTP FT7T7
    1 1 1 1 1 1 1
    CH 1 2 CPU_SPI_SI
    R7R1 R7R2 402 OUT 4
    R7R21 R7R12 R7R13 R7R22 R7R23 0 0 2 3 4 CPU_SPI_WP_N OUT 4 V_MEM V_MEM
    10K 10K 10K 10K 10K 5% 5% 5 6
    5% 5% 5% 5% 5%
    EMPTY EMPTY
    CH CH CH CH CH 402 402 EMPTY
    402 402 402 402 402 2 2
    2 2 2 2 2 1 1
    V_MEM C6F1
    .1UF R7F3
    0 1 2 3 4 10% 10K
    U7E1 IC 6.3V
    2 X5R 5%
    1 1 1 1 1 AT25020A 402 EMPTY
    CPU_SPI_CLK R6E2 CPU_SPI_CLK_R 6 8 402
    4 IN SCK VCC
    R7R20 R7R5 R7R3 R7R19 R7R18 CPU_SPI_SO_R 5 SDI
    2
    1K 5% 2 R7F7 1
    10K 10K 10K 10K 10K 402 CH SDO 2 CPU_SPI_SI_R CPU_SPI_SI 4
    5% 5% 5% 5% 5% OUT
    7 HOLD_N* 1K 5%
    EMPTY EMPTY EMPTY EMPTY EMPTY CPU_SPI_SO R7E7 CPU_SPI_EN_R 1 402 CH
    402 402 402 402 402 4 IN CS_N* 1
    2 2 2 2 2 1K 5% 3 WP_N* GND 4
    1 4 V_MEM 402 CH R7F4
    FT7R4 FTP V_MEM 100
    1 3
    FT7R6 FTP X800552-001 5%
    1 2
    FT7R2 FTP 2 R7E8 1 CH
    1 1 1
    FT7R1 FTP 1 402
    0 R7U3 10K 5% 2
    FT7R5 FTP
    10K 402 CH
    5%
    CH 2 R7F1 1
    402
    2 R7F2 10K 5%
    4 IN CPU_SPI_EN 402 EMPTY CPU_SPI_WP_N IN 4
    1K 5%
    402 CH
    DRAWING
    PROJECT NAME PAGE REV
    XENON_FABK MICROSOFT
    [PAGE_TITLE=CPU, CLOCKS + EEPROM + STRAPPING] Wed Aug 24 09:27:00 2005 XENON_RETAIL 4/73 K7
    CONFIDENTIAL
    CPU, FSB

    U7D1 2 OF 10 IC
    CPU VERSION 20

    12 IN FSB_GP_CP0_CLK_DP Y30 GP_CP0_CLK_DP CP_GP0_CLK_DP AG29 FSB_CP_GP0_CLK_DP OUT 12


    12 IN FSB_GP_CP0_CLK_DN Y29 GP_CP0_CLK_DN CP_GP0_CLK_DN AG30 FSB_CP_GP0_CLK_DN OUT 12

    12 FSB_GP_CP0_FLAG_DP AD29 GP_CP0_FLAG_DP CP_GP0_FLAG_DP AK27 FSB_CP_GP0_FLAG_DP 12


    IN FSB_GP_CP0_FLAG_DN FSB_CP_GP0_FLAG_DN OUT
    12 AD30 GP_CP0_FLAG_DN CP_GP0_FLAG_DN AK28 12
    IN OUT
    12 IN FSB_GP_CP0_DATA0_DP V28 GP_CP0_DATA0_DP CP_GP0_DATA0_DP AD28 FSB_CP_GP0_DATA0_DP OUT 12
    12 IN FSB_GP_CP0_DATA0_DN V27 GP_CP0_DATA0_DN CP_GP0_DATA0_DN AD27 FSB_CP_GP0_DATA0_DN OUT 12
    12 FSB_GP_CP0_DATA1_DP V30 GP_CP0_DATA1_DP CP_GP0_DATA1_DP AE29 FSB_CP_GP0_DATA1_DP 12
    IN FSB_GP_CP0_DATA1_DN FSB_CP_GP0_DATA1_DN OUT
    12 V29 GP_CP0_DATA1_DN CP_GP0_DATA1_DN AE30 12
    IN FSB_GP_CP0_DATA2_DP FSB_CP_GP0_DATA2_DP OUT
    12 W29 GP_CP0_DATA2_DP CP_GP0_DATA2_DP AF30 12
    IN OUT
    12 IN FSB_GP_CP0_DATA2_DN W30 GP_CP0_DATA2_DN CP_GP0_DATA2_DN AF29 FSB_CP_GP0_DATA2_DN OUT 12
    12 IN FSB_GP_CP0_DATA3_DP Y28 GP_CP0_DATA3_DP CP_GP0_DATA3_DP AF27 FSB_CP_GP0_DATA3_DP OUT 12
    12 IN FSB_GP_CP0_DATA3_DN Y27 GP_CP0_DATA3_DN CP_GP0_DATA3_DN AF28 FSB_CP_GP0_DATA3_DN OUT 12
    12 FSB_GP_CP0_DATA4_DP AA29 GP_CP0_DATA4_DP CP_GP0_DATA4_DP AH30 FSB_CP_GP0_DATA4_DP 12
    IN FSB_GP_CP0_DATA4_DN FSB_CP_GP0_DATA4_DN OUT
    12 AA30 GP_CP0_DATA4_DN CP_GP0_DATA4_DN AH29 12
    IN FSB_GP_CP0_DATA5_DP FSB_CP_GP0_DATA5_DP OUT
    12 AB28 GP_CP0_DATA5_DP CP_GP0_DATA5_DP AH27 12
    IN OUT
    12 IN FSB_GP_CP0_DATA5_DN AB27 GP_CP0_DATA5_DN CP_GP0_DATA5_DN AH28 FSB_CP_GP0_DATA5_DN OUT 12
    12 IN FSB_GP_CP0_DATA6_DP AB30 GP_CP0_DATA6_DP CP_GP0_DATA6_DP AJ29 FSB_CP_GP0_DATA6_DP OUT 12
    12 IN FSB_GP_CP0_DATA6_DN AB29 GP_CP0_DATA6_DN CP_GP0_DATA6_DN AJ30 FSB_CP_GP0_DATA6_DN OUT 12
    12 FSB_GP_CP0_DATA7_DP AC29 GP_CP0_DATA7_DP CP_GP0_DATA7_DP AK30 FSB_CP_GP0_DATA7_DP 12
    IN FSB_GP_CP0_DATA7_DN FSB_CP_GP0_DATA7_DN OUT
    12 AC30 GP_CP0_DATA7_DN CP_GP0_DATA7_DN AK29 12
    IN OUT
    12 IN FSB_GP_CP1_CLK_DP G30 GP_CP1_CLK_DP CP_GP1_CLK_DP P30 FSB_CP_GP1_CLK_DP OUT 12
    12 IN FSB_GP_CP1_CLK_DN G29 GP_CP1_CLK_DN CP_GP1_CLK_DN P29 FSB_CP_GP1_CLK_DN OUT 12

    12 FSB_GP_CP1_FLAG_DP L28 GP_CP1_FLAG_DP CP_GP1_FLAG_DP U30 FSB_CP_GP1_FLAG_DP 12


    IN FSB_GP_CP1_FLAG_DN FSB_CP_GP1_FLAG_DN OUT
    12 L27 GP_CP1_FLAG_DN CP_GP1_FLAG_DN U29 12
    IN OUT
    12 IN FSB_GP_CP1_DATA0_DP E28 GP_CP1_DATA0_DP CP_GP1_DATA0_DP L30 FSB_CP_GP1_DATA0_DP OUT 12
    12 IN FSB_GP_CP1_DATA0_DN E27 GP_CP1_DATA0_DN CP_GP1_DATA0_DN L29 FSB_CP_GP1_DATA0_DN OUT 12
    12 FSB_GP_CP1_DATA1_DP E30 GP_CP1_DATA1_DP CP_GP1_DATA1_DP M30 FSB_CP_GP1_DATA1_DP 12
    IN FSB_GP_CP1_DATA1_DN FSB_CP_GP1_DATA1_DN OUT
    12 E29 GP_CP1_DATA1_DN CP_GP1_DATA1_DN M29 12
    IN FSB_GP_CP1_DATA2_DP FSB_CP_GP1_DATA2_DP OUT
    12 F29 GP_CP1_DATA2_DP CP_GP1_DATA2_DP N27 12
    IN FSB_GP_CP1_DATA2_DN FSB_CP_GP1_DATA2_DN OUT
    12 F30 GP_CP1_DATA2_DN CP_GP1_DATA2_DN N28 12
    IN OUT
    12 IN FSB_GP_CP1_DATA3_DP G28 GP_CP1_DATA3_DP CP_GP1_DATA3_DP N30 FSB_CP_GP1_DATA3_DP OUT 12
    12 IN FSB_GP_CP1_DATA3_DN G27 GP_CP1_DATA3_DN CP_GP1_DATA3_DN N29 FSB_CP_GP1_DATA3_DN OUT 12
    12 FSB_GP_CP1_DATA4_DP H29 GP_CP1_DATA4_DP CP_GP1_DATA4_DP R27 FSB_CP_GP1_DATA4_DP 12
    IN FSB_GP_CP1_DATA4_DN FSB_CP_GP1_DATA4_DN OUT
    12 H30 GP_CP1_DATA4_DN CP_GP1_DATA4_DN R28 12
    IN FSB_GP_CP1_DATA5_DP FSB_CP_GP1_DATA5_DP OUT
    12 J28 GP_CP1_DATA5_DP CP_GP1_DATA5_DP R30 12
    IN FSB_GP_CP1_DATA5_DN FSB_CP_GP1_DATA5_DN OUT
    12 J27 GP_CP1_DATA5_DN CP_GP1_DATA5_DN R29 12
    IN OUT
    12 IN FSB_GP_CP1_DATA6_DP J30 GP_CP1_DATA6_DP CP_GP1_DATA6_DP T30 FSB_CP_GP1_DATA6_DP OUT 12
    12 IN FSB_GP_CP1_DATA6_DN J29 GP_CP1_DATA6_DN CP_GP1_DATA6_DN T29 FSB_CP_GP1_DATA6_DN OUT 12
    12 FSB_GP_CP1_DATA7_DP K29 GP_CP1_DATA7_DP CP_GP1_DATA7_DP U27 FSB_CP_GP1_DATA7_DP 12
    IN FSB_GP_CP1_DATA7_DN FSB_CP_GP1_DATA7_DN OUT
    12 K30 GP_CP1_DATA7_DN CP_GP1_DATA7_DN U28 12
    IN OUT

    X02046-002

    V_GPUCORE

    1 1 1 1 1 1 1 1 1
    C6R14 C6R25 C6R37 C6T19 C6T7 C6T27 C6T33 C6T32 C6R6
    .1UF .1UF .1UF .1UF .1UF .1UF .1UF .1UF .1UF
    10% 10% 10% 10% 10% 10% 10% 10% 10%
    6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
    2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R
    402 402 402 402 402 402 402 402 402

    DRAWING PROJECT NAME PAGE REV


    MICROSOFT
    [PAGE_TITLE=CPU, FSB] XENON_FABK XENON_RETAIL 5/73 K7
    Wed Aug 24 09:27:01 2005 CONFIDENTIAL
    CPU, FSB POWER + PLL POWER

    V_1P8

    V_GPUCORE
    V_CPUPLL
    U7D1 4 of 10 IC
    FB7R1 1 1 1 CPU VERSION 20
    1 2 C7R115 C7R116 C7R114 AA27
    .1UF .1UF .1UF VDD_FSB0
    1K FB 10% 10% 10% VDD_FSB1 AB26
    0.2A 603 2 6.3V 2 6.3V 2 6.3V AC27
    X5R X5R X5R VDD_FSB2
    1 0.7DCR 1 402 402 402 VDD_FSB3 AD26
    C7R1 C7R7 AE27
    .1UF 2.2UF VDD_FSB4
    10% 10% VDD_FSB5 AF26
    2 6.3V 2 6.3V AG27
    X5R X5R VDD_FSB6
    402 ST7R1 603 VDD_FSB7 AH26
    1 2 VDD_FSB8 AJ27
    V_EFUSE VDD_FSB9 AK26
    SHORT VDD_FSB10 B9
    2 R7T2 1 VDD_FSB11 B12
    CPU_VDDE
    VDD_FSB12 B15
    FB6D1 10K 5% VDD_FSB13 B18
    1 2 402 CH AK6 B21
    VDD_IO VDD_FSB14
    1K FB VDD_FSB15 B24
    0.2A 603 A6 VDDE VDD_FSB16 B27
    1 0.7DCR 1 B6 VDDE_SEC VDD_FSB17 C8
    C6D1 C6D4 C11
    .1UF 2.2UF VDD_FSB18
    10% 10% V_CPU_CORE_HF_VDDA_PLL AJ19 CORE_HF_VDDA_PLL VDD_FSB19 C14
    6.3V 6.3V AH19 C17
    2 X5R 2 X5R V_CPU_CORE_HF_GNDA_PLL CORE_HF_GNDA_PLL VDD_FSB20
    402 603 VDD_FSB21 C20
    ST6D1 V_CPU_CORE_IF_VDDA_PLL AK19 CORE_IF_VDDA_PLL VDD_FSB22 C23
    1 2 V_CPU_CORE_IF_GNDA_PLL AK18 CORE_IF_GNDA_PLL VDD_FSB23 C26
    VDD_FSB24 D10
    SHORT V_CPU_FSB_HF_VDDA_PLL AF22 FSB_HF_VDDA_PLL VDD_FSB25 D13
    V_CPU_FSB_HF_GNDA_PLL AG22 FSB_HF_GNDA_PLL VDD_FSB26 D17
    VDD_FSB27 D21
    FB6R1 V_CPU_FSB_IF_VDDA_PLL AF20 FSB_IF_VDDA_PLL VDD_FSB28 D25
    1 2 V_CPU_FSB_IF_GNDA_PLL AG20 FSB_IF_GNDA_PLL VDD_FSB29 D27
    1K FB VDD_FSB30 D29
    0.2A 603 V_CPU_VDDA_RNG AK13 VDDA_RNG VDD_FSB31 E26
    1 0.7DCR 1 V_CPU_GNDA_RNG AJ13 GNDA_RNG VDD_FSB32 F27
    C6R2 C6R4 G26
    .1UF 2.2UF VDD_FSB33
    10% 10% VDD_FSB34 H27
    2 6.3V 2 6.3V J26
    X5R X5R VDD_FSB35
    402 ST6R1 603 VDD_FSB36 K27
    1 2 VDD_FSB37 L26
    VDD_FSB38 M27
    SHORT VDD_FSB39 N26
    VDD_FSB40 P27
    VDD_FSB41 R26
    VDD_FSB42 T27
    FB6R2 VDD_FSB43 U26
    1 2 VDD_FSB44 V26
    1K FB VDD_FSB45 W27
    0.2A 603 VDD_FSB46 Y26
    1 0.7DCR 1
    C6R3 C6R5
    .1UF 2.2UF
    10% 10% X02046-002
    6.3V 6.3V
    2 X5R 2 X5R
    402 603
    ST6R2
    1 2

    SHORT

    FB7D1
    1 2
    1K FB
    0.2A 603
    1 0.7DCR 1
    C7D1 C7D2
    1UF 2.2UF
    10% 10%
    2 50V 2 6.3V
    EMPTY X5R
    603 603
    ST7D1
    1 2

    SHORT

    DRAWING
    PROJECT NAME PAGE REV
    XENON_FABK MICROSOFT
    [PAGE_TITLE=CPU, FSB POWER + PLL POWER] Wed Aug 24 09:27:01 2005 XENON_RETAIL 6/73 K7
    CONFIDENTIAL
    CPU, CORE POWER

    V_CPUCORE U7D1 IC V_CPUCORE V_CPUCORE V_CPUCORE V_CPUCORE U7D1 IC V_CPUCORE


    U7D1 IC
    5 of 10 6 of 10 7 of 10
    CPU VERSION 20 CPU VERSION 20 CPU VERSION 20
    AA2 VDD0 VDD48 AD23 D7 VDD96 VDD143 J20 N14 VDD190 VDD237 U8
    AA4 VDD1 VDD49 AD25 D9 VDD97 VDD144 J22 N16 VDD191 VDD238 U10
    AA6 VDD2 VDD50 AE2 E2 VDD98 VDD145 J24 N18 VDD192 VDD239 U12
    AA8 VDD3 VDD51 AE4 E4 VDD99 VDD146 K1 N20 VDD193 VDD240 U14
    AA10 VDD4 VDD52 AE6 E6 VDD100 VDD147 K3 N22 VDD194 VDD241 U16
    AA12 VDD5 VDD53 AE8 E8 VDD101 VDD148 K5 N24 VDD195 VDD242 U18
    AA14 VDD6 VDD54 AE10 E10 VDD102 VDD149 K7 P1 VDD196 VDD243 U20
    AA16 VDD7 VDD55 AE12 F1 VDD103 VDD150 K9 P3 VDD197 VDD244 U22
    AA18 VDD8 VDD56 AE14 F3 VDD104 VDD151 K11 P5 VDD198 VDD245 U24
    AA20 VDD9 VDD57 AE16 F5 VDD105 VDD152 K13 P7 VDD199 VDD246 V1
    AA22 VDD10 VDD58 AE18 F7 VDD106 VDD153 K15 P9 VDD200 VDD247 V3
    AA24 VDD11 VDD59 AE20 F9 VDD107 VDD154 K17 P11 VDD201 VDD248 V5
    AB1 VDD12 VDD60 AE22 F11 VDD108 VDD155 K19 P13 VDD202 VDD249 V7
    AB3 VDD13 VDD61 AE24 G2 VDD109 VDD156 K21 P15 VDD203 VDD250 V9
    AB5 VDD14 VDD62 AF1 G4 VDD110 VDD157 K23 P17 VDD204 VDD251 V11
    AB7 VDD15 VDD63 AF3 G6 VDD111 VDD158 K25 P19 VDD205 VDD252 V13
    AB9 VDD16 VDD64 AF5 G8 VDD112 VDD159 L2 P21 VDD206 VDD253 V15
    AB11 VDD17 VDD65 AF7 G10 VDD113 VDD160 L4 P23 VDD207 VDD254 V17
    AB13 VDD18 VDD66 AF9 G12 VDD114 VDD161 L6 P25 VDD208 VDD255 V19
    AB15 VDD19 VDD67 AF11 G14 VDD115 VDD162 L8 R2 VDD209 VDD256 V21
    AB17 VDD20 VDD68 AF13 G16 VDD116 VDD163 L10 R4 VDD210 VDD257 V23
    AB19 VDD21 VDD69 AF15 G18 VDD117 VDD164 L12 R6 VDD211 VDD258 V25
    AB21 VDD22 VDD70 AF17 G20 VDD118 VDD165 L14 R8 VDD212 VDD259 W2
    AB23 VDD23 VDD71 AF19 G22 VDD119 VDD166 L16 R10 VDD213 VDD260 W4
    AB25 VDD24 VDD72 AF21 G24 VDD120 VDD167 L18 R12 VDD214 VDD261 W6
    AC2 VDD25 VDD73 AF23 H1 VDD121 VDD168 L20 R14 VDD215 VDD262 W8
    AC4 VDD26 VDD74 AF25 H3 VDD122 VDD169 L22 R16 VDD216 VDD263 W10
    AC6 VDD27 VDD75 AG2 H5 VDD123 VDD170 L24 R18 VDD217 VDD264 W12
    AC8 VDD28 VDD76 AG4 H7 VDD124 VDD171 M1 R20 VDD218 VDD265 W14
    AC10 VDD29 VDD77 AG6 H9 VDD125 VDD172 M3 R22 VDD219 VDD266 W16
    AC12 VDD30 VDD78 AG8 H11 VDD126 VDD173 M5 R24 VDD220 VDD267 W18
    AC14 VDD31 VDD79 AG10 H13 VDD127 VDD174 M7 T1 VDD221 VDD268 W20
    AC16 VDD32 VDD80 AG12 H15 VDD128 VDD175 M9 T3 VDD222 VDD269 W22
    AC18 VDD33 VDD81 AG14 H17 VDD129 VDD176 M11 T5 VDD223 VDD270 W24
    AC20 VDD34 VDD82 AH3 H19 VDD130 VDD177 M13 T7 VDD224 VDD271 Y1
    AC22 VDD35 VDD83 AH6 H21 VDD131 VDD178 M15 T9 VDD225 VDD272 Y3
    AC24 VDD36 VDD84 AH9 H23 VDD132 VDD179 M17 T11 VDD226 VDD273 Y5
    AD1 VDD37 VDD85 AH12 H25 VDD133 VDD180 M19 T13 VDD227 VDD274 Y7
    AD3 VDD38 VDD86 AH15 J2 VDD134 VDD181 M21 T15 VDD228 VDD275 Y9
    AD5 VDD39 VDD87 AJ5 J4 VDD135 VDD182 M23 T17 VDD229 VDD276 Y11
    AD7 VDD40 VDD88 AJ8 J6 VDD136 VDD183 M25 T19 VDD230 VDD277 Y13
    AD9 VDD41 VDD89 AJ11 J8 VDD137 VDD184 N2 T21 VDD231 VDD278 Y15
    AD11 VDD42 VDD90 AJ14 J10 VDD138 VDD185 N4 T23 VDD232 VDD279 Y17
    AD13 VDD43 VDD91 B1 J12 VDD139 VDD186 N6 T25 VDD233 VDD280 Y19
    AD15 VDD44 VDD92 C2 J14 VDD140 VDD187 N8 U2 VDD234 VDD281 Y21
    AD17 VDD45 VDD93 D1 J16 VDD141 VDD188 N10 U4 VDD235 VDD282 Y23
    AD19 VDD46 VDD94 D3 J18 VDD142 VDD189 N12 U6 VDD236 VDD283 Y25
    AD21 VDD47 VDD95 D5

    X02046-002 X02046-002
    X02046-002

    DRAWING
    PROJECT NAME PAGE REV
    XENON_FABK MICROSOFT
    [PAGE_TITLE=CPU, CORE POWER] Wed Aug 24 09:27:01 2005
    CONFIDENTIAL
    XENON_RETAIL 7/73 K7
    CPU, POWER

    U7D1 IC U7D1 IC
    U7D1 IC
    9 of 10 10 of 10
    8 of 10
    CPU VERSION 20 CPU VERSION 20
    CPU VERSION 20
    B14 VSS117 VSS175 H2 M10 VSS233 VSS291 T18
    AA1 VSS0 VSS58 AE9
    B17 VSS118 VSS176 H4 M12 VSS234 VSS292 T20
    AA3 VSS1 VSS59 AE11
    B20 VSS119 VSS177 H6 M14 VSS235 VSS293 T22
    AA5 VSS2 VSS60 AE13
    B23 VSS120 VSS178 H8 M16 VSS236 VSS294 T24
    AA7 VSS3 VSS61 AE15
    B26 VSS121 VSS179 H10 M18 VSS237 VSS295 T26
    AA9 VSS4 VSS62 AE17
    B29 VSS122 VSS180 H12 M20 VSS238 VSS296 T28
    AA11 VSS5 VSS63 AE19
    C1 VSS123 VSS181 H14 M22 VSS239 VSS297 U1
    AA13 VSS6 VSS64 AE21
    C3 VSS124 VSS182 H16 M24 VSS240 VSS298 U3
    AA15 VSS7 VSS65 AE23
    C9 VSS125 VSS183 H18 M26 VSS241 VSS299 U5
    AA17 VSS8 VSS66 AE25
    C12 VSS126 VSS184 H20 M28 VSS242 VSS300 U7
    AA19 VSS9 VSS67 AE26
    C15 VSS127 VSS185 H22 N1 VSS243 VSS301 U9
    AA21 VSS10 VSS68 AE28
    C18 VSS128 VSS186 H24 N3 VSS244 VSS302 U11
    AA23 VSS11 VSS69 AF2
    C21 VSS129 VSS187 H26 N5 VSS245 VSS303 U13
    AA25 VSS12 VSS70 AF4
    C24 VSS130 VSS188 H28 N7 VSS246 VSS304 U15
    AA26 VSS13 VSS71 AF6
    C27 VSS131 VSS189 J1 N9 VSS247 VSS305 U17
    AA28 VSS14 VSS72 AF8
    D2 VSS132 VSS190 J3 N11 VSS248 VSS306 U19
    AB2 VSS15 VSS73 AF10
    D4 VSS133 VSS191 J5 N13 VSS249 VSS307 U21
    AB4 VSS16 VSS74 AF12
    D6 VSS134 VSS192 J7 N15 VSS250 VSS308 U23
    AB6 VSS17 VSS75 AF14
    D8 VSS135 VSS193 J9 N17 VSS251 VSS309 U25
    AB8 VSS18 VSS76 AG1
    D11 VSS136 VSS194 J11 N19 VSS252 VSS310 V2
    AB10 VSS19 VSS77 AG3
    D15 VSS137 VSS195 J13 N21 VSS253 VSS311 V4
    AB12 VSS20 VSS78 AG5
    D19 VSS138 VSS196 J15 N23 VSS254 VSS312 V6
    AB14 VSS21 VSS79 AG7
    D23 VSS139 VSS197 J17 N25 VSS255 VSS313 V8
    AB16 VSS22 VSS80 AG9
    D26 VSS140 VSS198 J19 P2 VSS256 VSS314 V10
    AB18 VSS23 VSS81 AG11
    D28 VSS141 VSS199 J21 P4 VSS257 VSS315 V12
    AB20 VSS24 VSS82 AG13
    D30 VSS142 VSS200 J23 P6 VSS258 VSS316 V14
    AB22 VSS25 VSS83 AG15
    E1 VSS143 VSS201 J25 P8 VSS259 VSS317 V16
    AB24 VSS26 VSS84 AG17
    E3 VSS144 VSS202 K2 P10 VSS260 VSS318 V18
    AC1 VSS27 VSS85 AG19
    E5 VSS145 VSS203 K4 P12 VSS261 VSS319 V20
    AC3 VSS28 VSS86 AG21
    E7 VSS146 VSS204 K6 P14 VSS262 VSS320 V22
    AC5 VSS29 VSS87 AG23
    E9 VSS147 VSS205 K8 P16 VSS263 VSS321 V24
    AC7 VSS30 VSS88 AG25
    F2 VSS148 VSS206 K10 P18 VSS264 VSS322 W1
    AC9 VSS31 VSS89 AG26
    F4 VSS149 VSS207 K12 P20 VSS265 VSS323 W3
    AC11 VSS32 VSS90 AG28
    F6 VSS150 VSS208 K14 P22 VSS266 VSS324 W5
    AC13 VSS33 VSS91 AH2
    F8 VSS151 VSS209 K16 P24 VSS267 VSS325 W7
    AC15 VSS34 VSS92 AH5
    F10 VSS152 VSS210 K18 P26 VSS268 VSS326 W9
    AC17 VSS35 VSS93 AH8
    F12 VSS153 VSS211 K20 P28 VSS269 VSS327 W11
    AC19 VSS36 VSS94 AH11
    F14 VSS154 VSS212 K22 R1 VSS270 VSS328 W13
    AC21 VSS37 VSS95 AH14
    F16 VSS155 VSS213 K24 R3 VSS271 VSS329 W15
    AC23 VSS38 VSS96 AH17
    F18 VSS156 VSS214 K26 R5 VSS272 VSS330 W17
    AC25 VSS39 VSS97 AH18
    F20 VSS157 VSS215 K28 R7 VSS273 VSS331 W19
    AC26 VSS40 VSS98 AH20
    F22 VSS158 VSS216 L1 R9 VSS274 VSS332 W21
    AC28 VSS41 VSS99 AH21
    F24 VSS159 VSS217 L3 R11 VSS275 VSS333 W23
    AD2 VSS42 VSS100 AH23
    F26 VSS160 VSS218 L5 R13 VSS276 VSS334 W25
    AD4 VSS43 VSS101 AH24
    F28 VSS161 VSS219 L7 R15 VSS277 VSS335 W26
    AD6 VSS44 VSS102 AJ3
    G1 VSS162 VSS220 L9 R17 VSS278 VSS336 W28
    AD8 VSS45 VSS103 AJ6
    G3 VSS163 VSS221 L11 R19 VSS279 VSS337 Y2
    AD10 VSS46 VSS104 AJ9
    G5 VSS164 VSS222 L13 R21 VSS280 VSS338 Y4
    AD12 VSS47 VSS105 AJ12
    G7 VSS165 VSS223 L15 R23 VSS281 VSS339 Y6
    AD14 VSS48 VSS106 AJ15
    G9 VSS166 VSS224 L17 R25 VSS282 VSS340 Y8
    AD16 VSS49 VSS107 AJ17
    G11 VSS167 VSS225 L19 T2 VSS283 VSS341 Y10
    AD18 VSS50 VSS108 AJ18
    G13 VSS168 VSS226 L21 T4 VSS284 VSS342 Y12
    AD20 VSS51 VSS109 AJ20
    G15 VSS169 VSS227 L23 T6 VSS285 VSS343 Y14
    AD22 VSS52 VSS110 AJ21
    G17 VSS170 VSS228 L25 T8 VSS286 VSS344 Y16
    AD24 VSS53 VSS111 AJ23
    G19 VSS171 VSS229 M2 T10 VSS287 VSS345 Y18
    AE1 VSS54 VSS112 AJ24
    G21 VSS172 VSS230 M4 T12 VSS288 VSS346 Y20
    AE3 VSS55 VSS113 AJ26
    G23 VSS173 VSS231 M6 T14 VSS289 VSS347 Y22
    AE5 VSS56 VSS114 AJ28
    G25 VSS174 VSS232 M8 T16 VSS290 VSS348 Y24
    AE7 VSS57 VSS115 B8
    VSS116 B11
    X02046-002 X02046-002
    X02046-002

    DRAWING
    PROJECT NAME PAGE REV
    XENON_FABK MICROSOFT
    [PAGE_TITLE=CPU, POWER] Wed Aug 24 09:27:02 2005 XENON_RETAIL 8/73 K7
    CONFIDENTIAL
    V_CPUCORE V_CPUCORE

    CPU, DECOUPLING

    C7D21 C7R122 C7T85 C7R6 C7D9 C7R27 C7D10 C7R3


    1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 C7T79 C7T1
    1 2 1 2
    4.7UF 10% 4.7UF 10% 4.7UF 10% 4.7UF 10% 4.7UF 10% 4.7UF 10% 4.7UF 10% 4.7UF 10%
    6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V .1UF 10% .1UF 10%
    X5R X5R X5R X5R X5R X5R X5R X5R 6.3V 6.3V
    805 805 805 805 805 805 805 805 X5R X5R
    402 402

    C7T94 C7E8 C7E6 C7R94 C7R5 C7D8 C7R4 C7R30


    1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 C7T78 C7T45
    1 2 1 2
    4.7UF 10% 4.7UF 10% 4.7UF 10% 4.7UF 10% 4.7UF 10% 4.7UF 10% 4.7UF 10% 4.7UF 10%
    6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V .1UF 10% .1UF 10%
    X5R X5R X5R X5R X5R X5R X5R X5R 6.3V 6.3V
    805 805 805 805 805 805 805 805 X5R X5R
    402 402

    C7T101 C7E14 C7D12 C7E1 C7T34 C7D4 C7T35 C7R90


    1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 C7T77 C7R16
    1 2 1 2
    4.7UF 10% 4.7UF 10% 4.7UF 10% 4.7UF 10% 4.7UF 10% 4.7UF 10% 4.7UF 10% 4.7UF 10%
    6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V .1UF 10% .1UF 10%
    X5R X5R X5R X5R X5R X5R X5R X5R 6.3V 6.3V
    805 805 805 805 805 805 805 805 X5R X5R
    402 402

    C7T93 C7R119 C7D18 C7E2


    C7T87 1 2 C7D19 1 2 C7R26 1 2 C7D5 1 2
    1 2 1 2 1 2 1 2 C7T76
    1 2
    4.7UF 10% 4.7UF 10% 4.7UF 10% 4.7UF 10%
    4.7UF 10% 6.3V 4.7UF 10% 6.3V 4.7UF 10% 6.3V 4.7UF 10% 6.3V
    6.3V X5R 6.3V X5R 6.3V X5R 6.3V X5R .1UF 10%
    X5R 805 X5R 805 X5R 805 X5R 805 6.3V
    805 805 805 805 X5R
    402

    C7R2 C7D16 C7T36 C7E7 C7R117 C7D7 C7R93 C7E15


    1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 C7T88
    1 2
    4.7UF 10% 4.7UF 10% 4.7UF 10% 4.7UF 10% 4.7UF 10% 4.7UF 10% 4.7UF 10% 4.7UF 10%
    6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V .1UF 10%
    X5R X5R X5R X5R X5R X5R X5R X5R 6.3V
    805 805 805 805 805 805 805 805 X5R
    402

    C7E3 C7E12 C7R118 C7D13 C7T96 C7E16 C7T95 C7E9


    1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 C7R12
    1 2
    4.7UF 10% 4.7UF 10% 4.7UF 10% 4.7UF 10% 4.7UF 10% 4.7UF 10% 4.7UF 10% 4.7UF 10%
    6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V .1UF 10%
    X5R X5R X5R X5R X5R X5R X5R X5R 6.3V
    805 805 805 805 805 805 805 805 X5R
    402

    C7T32 C7E10 C7E5 C7T83 C7R92 C7R91 C7D3 C7T86


    1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 C7R10
    1 2
    4.7UF 10% 4.7UF 10% 4.7UF 10% 4.7UF 10% 4.7UF 10% 4.7UF 10% 4.7UF 10% 4.7UF 10%
    6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V .1UF 10%
    X5R X5R X5R X5R X5R X5R X5R X5R 6.3V
    805 805 805 805 805 805 805 805 X5R
    402

    C7R28 C7E11 C7D14 C7D11 C7D6 C7R29 C7R120 C7T97


    1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 C7R11
    1 2
    4.7UF 10% 4.7UF 10% 4.7UF 10% 4.7UF 10% 4.7UF 10% 4.7UF 10% 4.7UF 10% 4.7UF 10%
    6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V .1UF 10%
    X5R X5R X5R X5R X5R X5R X5R X5R 6.3V
    805 805 805 805 805 805 805 805 X5R
    402

    C7D20 C7T33 C7R121 C7T84 C7D17 C7E4 C7D15 C7D22


    1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 C7R13
    1 2
    4.7UF 10% 4.7UF 10% 4.7UF 10% 4.7UF 10% 4.7UF 10% 4.7UF 10% 4.7UF 10% 4.7UF 10%
    6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V .1UF 10%
    X5R X5R X5R X5R X5R X5R X5R X5R 6.3V
    805 805 805 805 805 805 805 805 X5R
    402

    DRAWING
    PROJECT NAME PAGE REV
    XENON_FABK MICROSOFT
    [PAGE_TITLE=CPU, DECOUPLING] Wed Aug 24 09:27:03 2005 XENON_RETAIL 9/73 K7
    CONFIDENTIAL
    V_CPUCORE

    CPU, DECOUPLING

    C7R36 C7R62 C7R49 C7T9 C7R80 C7R52 C7T20 C6R44 C6T10 C7T21 C7T69
    1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2

    .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10%
    6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
    X5R X5R X5R X5R X5R X5R X5R X5R X5R X5R X5R
    402 402 402 402 402 402 402 402 402 402 402

    C7R22 C7R78 C7R72 C7R55 C6R32 C7R51 C7T22 C6T2 C7T19 C7T71 C7T70
    1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2

    .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10%
    6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
    X5R X5R X5R X5R X5R X5R X5R X5R X5R X5R X5R
    402 402 402 402 402 402 402 402 402 402 402

    C7R23 C7R70 C6R29 C7R35 C6R31 C7R50 C7T27 C6T1 C7R66 C6R42 C7T75
    1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2

    .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10%
    6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
    X5R X5R X5R X5R X5R X5R X5R X5R X5R X5R X5R
    402 402 402 402 402 402 402 402 402 402 402

    C7R24 C7R53 C6R28 C7R34 C6T5 C6T6 C7R48 C6R43 C7R111 C7R67 C7T74
    1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2

    .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10%
    6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
    X5R X5R X5R X5R X5R X5R X5R X5R X5R X5R X5R
    402 402 402 402 402 402 402 402 402 402 402

    C7R25 C7R47 C6R27 C7R19 C7R68 C6R22 C6T4 C7R102 C7R110 C7T3 C7T73
    1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2

    .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10%
    6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
    X5R X5R X5R X5R X5R X5R X5R X5R X5R X5R X5R
    402 402 402 402 402 402 402 402 402 402 402

    C7R38 C7R63 C7R76 C7R43 C7R69 C6R23 C7T37 C7R81 C7T2 C7T5 C7T72
    1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2

    .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10%
    6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
    X5R X5R X5R X5R X5R X5R X5R X5R X5R X5R X5R
    402 402 402 402 402 402 402 402 402 402 402

    C7R37 C7R79 C7T15 C6R16 C7R57 C7R58 C7R89 C6R36 C6R35 C7T82 C6R33
    1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2

    .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10%
    6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
    X5R X5R X5R X5R X5R X5R X5R X5R X5R X5R X5R
    402 402 402 402 402 402 402 402 402 402 402

    C7R44 C7R77 C7R64 C6R19 C6R20 C7R59 C6T25 C7T81 C7T10 C6R40 C7R88
    1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2

    .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10%
    6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
    X5R X5R X5R X5R X5R X5R X5R X5R X5R X5R X5R
    402 402 402 402 402 402 402 402 402 402 402

    C6R11 C6R17 C7R71 C7R61 C6R21 C7R60 C7R99 C7R100 C6R39 C6R38 C6R45
    1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2

    .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10%
    6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
    X5R X5R X5R X5R X5R X5R X5R X5R X5R X5R X5R
    402 402 402 402 402 402 402 402 402 402 402

    C7R46 C7R45 C7R84 C7R54 C6T26 C6R30 C6T23 C7R74 C6R18 C6R34 C7T8
    1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2

    .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10%
    6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
    X5R X5R X5R X5R X5R X5R X5R X5R X5R X5R X5R
    402 402 402 402 402 402 402 402 402 402 402

    N: EMPTY FOR
    CPU SOCKET

    DRAWING
    PROJECT NAME PAGE REV
    XENON_FABK MICROSOFT
    [PAGE_TITLE=CPU, DECOUPLING] Wed Aug 24 09:27:03 2005 XENON_RETAIL 10/73 K7
    CONFIDENTIAL
    V_CPUCORE
    CPU, DECOUPLING

    C7R31 C6T11 C7T38 C7T58 C7T30 C7T54 C6T13 C7R95 C7T51 C6T15 C6T28
    1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2

    .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10%
    6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
    X5R X5R X5R X5R X5R X5R X5R X5R X5R X5R X5R
    402 402 402 402 402 402 402 402 402 402 402

    C7T12 C7R17 C7R65 C6R24 C7T29 C6T24 C7T14 C7R103 C7T47 C6T16 C6T29
    1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2

    .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10%
    6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
    X5R X5R X5R X5R X5R X5R X5R X5R X5R X5R X5R
    402 402 402 402 402 402 402 402 402 402 402

    C7R82 C7R18 C6T14 C7T56 C7T50 C7T53 C7T80 C7R104 C7T46 C7T43 C6T30
    1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2

    .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10%
    6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
    X5R X5R X5R X5R X5R X5R X5R X5R X5R X5R X5R
    402 402 402 402 402 402 402 402 402 402 402

    C7R56 C7R20 C7T28 C7R98 C7R106 C7T52 C7T11 C7R96 C7R97 C7T44 C7T62
    1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2

    .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10%
    6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
    X5R X5R X5R X5R X5R X5R X5R X5R X5R X5R X5R
    402 402 402 402 402 402 402 402 402 402 402

    C6R26 C7R42 C7T31 C6T8 C6T20 C6R9 C7T40 C7R108 C7T57 C7T42 C7T63
    1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2

    .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10%
    6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
    X5R X5R X5R X5R X5R X5R X5R X5R X5R X5R X5R
    402 402 402 402 402 402 402 402 402 402 402

    C6T9 C7R41 C6R10 C7T17 C7T49 C6R7 C7R75 C7R109 C7T55 C7R83 C7T64
    1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2

    .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10%
    6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
    X5R X5R X5R X5R X5R X5R X5R X5R X5R X5R X5R
    402 402 402 402 402 402 402 402 402 402 402

    C6T3 C7R40 C7R8 C7T41 C6T22 C7T61 C7R85 C7R105 C7T18 C7T24 C7T65
    1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2

    .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10%
    6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
    X5R X5R X5R X5R X5R X5R X5R X5R X5R X5R X5R
    402 402 402 402 402 402 402 402 402 402 402

    C7R21 C7R39 C7R15 C6T12 C7T13 C7T60 C7R101 C7T4 C7T39 C7T25 C7T66
    1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2

    .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10%
    6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
    X5R X5R X5R X5R X5R X5R X5R X5R X5R X5R X5R
    402 402 402 402 402 402 402 402 402 402 402

    C7R107 C6T21 C7R33 C6R15 C7R14 C7T59 C6R8 C6T18 C7T26 C6T17 C7T67
    1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2

    .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10%
    6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
    X5R X5R X5R X5R X5R X5R X5R X5R X5R X5R X5R
    402 402 402 402 402 402 402 402 402 402 402

    C6R13 C6R12 C7R32 C6R41 C7R9 C7R86 C7R73 C7T16 C7T48 C7T23 C7T68
    1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2

    .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10%
    6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
    X5R X5R X5R X5R X5R X5R X5R X5R X5R X5R X5R
    402 402 402 402 402 402 402 402 402 402 402

    DRAWING
    PROJECT NAME PAGE REV
    XENON_FABK MICROSOFT
    [PAGE_TITLE=CPU, DECOUPLING] Wed Aug 24 09:27:05 2005 XENON_RETAIL 11/73 K7
    CONFIDENTIAL
    V_MEM
    V_GPUCORE GPU, FSB
    2 R5C12 1
    1K 5% V_MEM
    1 402 CH 1 R2E5 2
    1
    R5R1 U4D1 1 OF 8 IC 0 5%
    1K 2 R5C11 1 C2E4 402 CH R2R5
    5% GPU VERSION 57 1 2 0
    1K 5% 5%
    EMPTY 402 CH
    402 FSB_BYPCLK_DP B29 .1UF 10% CH
    FSB_BYPCLK_DP 6.3V U2E2 EMPTY 402
    2 FSB_BYPCLK_DN A29 X5R
    FSB_BYPCLK_DN 2
    FSB_BYPCLK_SEL D25 402 SN74LVC1G125
    FSB_BYPCLK_SEL
    5 VCC
    1 MEM_SCAN_EN 26 27
    5 IN FSB_CP_GP0_CLK_DP J34 CP_GP0_CLK_DP GP_CP0_CLK_DP P33 FSB_GP_CP0_CLK_DP OUT 5 13 IN MEM_SCAN_EN_BUFF 2 IN OUT 4 OUT 20 21 22
    R5R2 5 IN FSB_CP_GP0_CLK_DN J33 CP_GP0_CLK_DN GP_CP0_CLK_DN P34 FSB_GP_CP0_CLK_DN OUT 5 3 GND OE_N 1 23 24 25
    1K 5 FSB_CP_GP0_FLAG_DP J30 CP_GP0_FLAG_DP GP_CP0_FLAG_DP L34 FSB_GP_CP0_FLAG_DP 5
    5% IN FSB_CP_GP0_FLAG_DN FSB_GP_CP0_FLAG_DN OUT
    5 IN J29 CP_GP0_FLAG_DN GP_CP0_FLAG_DN L33
    OUT 5 1 1
    CH X801565-001
    402 FSB_CP_GP0_DATA0_DP FSB_GP_CP0_DATA0_DP R4F8 R2D11
    2 5 M29 CP_GP0_DATA0_DP GP_CP0_DATA0_DP T29 5 1K 1K
    IN OUT
    5 IN FSB_CP_GP0_DATA0_DN M30 CP_GP0_DATA0_DN GP_CP0_DATA0_DN T30 FSB_GP_CP0_DATA0_DN OUT 5 5% 5%
    5 IN FSB_CP_GP0_DATA1_DP L32 CP_GP0_DATA1_DP GP_CP0_DATA1_DP T31 FSB_GP_CP0_DATA1_DP OUT 5 CH CH
    5 FSB_CP_GP0_DATA1_DN L31 CP_GP0_DATA1_DN GP_CP0_DATA1_DN T32 FSB_GP_CP0_DATA1_DN 5 402 402
    IN FSB_CP_GP0_DATA2_DP FSB_GP_CP0_DATA2_DP OUT 2 2
    5 K33 CP_GP0_DATA2_DP GP_CP0_DATA2_DP R34 5
    IN FSB_CP_GP0_DATA2_DN FSB_GP_CP0_DATA2_DN OUT
    5 K34 CP_GP0_DATA2_DN GP_CP0_DATA2_DN R33 5
    IN OUT
    5 IN FSB_CP_GP0_DATA3_DP L30 CP_GP0_DATA3_DP GP_CP0_DATA3_DP R29 FSB_GP_CP0_DATA3_DP OUT 5
    5 IN FSB_CP_GP0_DATA3_DN L29 CP_GP0_DATA3_DN GP_CP0_DATA3_DN R30 FSB_GP_CP0_DATA3_DN OUT 5
    5 IN FSB_CP_GP0_DATA4_DP J31 CP_GP0_DATA4_DP GP_CP0_DATA4_DP N34 FSB_GP_CP0_DATA4_DP OUT 5
    5 FSB_CP_GP0_DATA4_DN J32 CP_GP0_DATA4_DN GP_CP0_DATA4_DN N33 FSB_GP_CP0_DATA4_DN 5
    IN FSB_CP_GP0_DATA5_DP FSB_GP_CP0_DATA5_DP OUT
    5 K30 CP_GP0_DATA5_DP GP_CP0_DATA5_DP P29 5
    IN FSB_CP_GP0_DATA5_DN FSB_GP_CP0_DATA5_DN OUT
    5 K29 CP_GP0_DATA5_DN GP_CP0_DATA5_DN P30 5
    IN OUT
    5 IN FSB_CP_GP0_DATA6_DP H34 CP_GP0_DATA6_DP GP_CP0_DATA6_DP N31 FSB_GP_CP0_DATA6_DP OUT 5
    5 IN FSB_CP_GP0_DATA6_DN H33 CP_GP0_DATA6_DN GP_CP0_DATA6_DN N32 FSB_GP_CP0_DATA6_DN OUT 5
    5 IN FSB_CP_GP0_DATA7_DP H31 CP_GP0_DATA7_DP GP_CP0_DATA7_DP M34 FSB_GP_CP0_DATA7_DP OUT 5 V_MEM
    5 FSB_CP_GP0_DATA7_DN H32 CP_GP0_DATA7_DN GP_CP0_DATA7_DN M33 FSB_GP_CP0_DATA7_DN 5 1 R2D12 2
    IN OUT
    5 FSB_CP_GP1_CLK_DP V33 CP_GP1_CLK_DP GP_CP1_CLK_DP AC33 FSB_GP_CP1_CLK_DP 5 0 5%
    IN OUT C2R12 402 CH
    5 IN FSB_CP_GP1_CLK_DN V34 CP_GP1_CLK_DN GP_CP1_CLK_DN AC34 FSB_GP_CP1_CLK_DN OUT 5 1 2
    5 IN FSB_CP_GP1_FLAG_DP T33 CP_GP1_FLAG_DP GP_CP1_FLAG_DP Y29 FSB_GP_CP1_FLAG_DP OUT 5
    5 IN FSB_CP_GP1_FLAG_DN T34 CP_GP1_FLAG_DN GP_CP1_FLAG_DN Y30 FSB_GP_CP1_FLAG_DN OUT 5 .1UF 10%
    6.3V U2D1 EMPTY
    FSB_CP_GP1_DATA0_DP AA31 AC28 FSB_GP_CP1_DATA0_DP X5R
    5 IN CP_GP1_DATA0_DP GP_CP1_DATA0_DP OUT 5 402 SN74LVC1G125
    5 FSB_CP_GP1_DATA0_DN AA32 CP_GP1_DATA0_DN GP_CP1_DATA0_DN AC29 FSB_GP_CP1_DATA0_DN 5
    IN OUT 5 VCC
    5 IN FSB_CP_GP1_DATA1_DP Y33 CP_GP1_DATA1_DP GP_CP1_DATA1_DP AD29 FSB_GP_CP1_DATA1_DP OUT 5 MEM_SCAN_TOP_EN_BUFF 2 4 MEM_SCAN_TOP_EN
    FSB_CP_GP1_DATA1_DN Y34 AD30 FSB_GP_CP1_DATA1_DN 13 IN IN OUT OUT 20 22 24
    5 IN CP_GP1_DATA1_DN GP_CP1_DATA1_DN OUT 5 3 1 26
    FSB_CP_GP1_DATA2_DP W30 AD34 FSB_GP_CP1_DATA2_DP GND OE_N
    5 IN CP_GP1_DATA2_DP GP_CP1_DATA2_DP OUT 5 1 1
    5 FSB_CP_GP1_DATA2_DN W29 CP_GP1_DATA2_DN GP_CP1_DATA2_DN AD33 FSB_GP_CP1_DATA2_DN 5
    IN FSB_CP_GP1_DATA3_DP FSB_GP_CP1_DATA3_DP OUT R4F7 R2T2
    5 W33 CP_GP1_DATA3_DP GP_CP1_DATA3_DP AB29 5 X801565-001
    IN FSB_CP_GP1_DATA3_DN FSB_GP_CP1_DATA3_DN OUT 1K 1K
    5 W34 CP_GP1_DATA3_DN GP_CP1_DATA3_DN AB30 5
    IN OUT 5% 5%
    5 IN FSB_CP_GP1_DATA4_DP V29 CP_GP1_DATA4_DP GP_CP1_DATA4_DP AC32 FSB_GP_CP1_DATA4_DP OUT 5
    FSB_CP_GP1_DATA4_DN V28 AC31 FSB_GP_CP1_DATA4_DN CH CH
    5 IN CP_GP1_DATA4_DN GP_CP1_DATA4_DN OUT 5 402 402
    5 FSB_CP_GP1_DATA5_DP V31 CP_GP1_DATA5_DP GP_CP1_DATA5_DP AA29 FSB_GP_CP1_DATA5_DP 5 2 2
    IN FSB_CP_GP1_DATA5_DN FSB_GP_CP1_DATA5_DN OUT
    5 V32 CP_GP1_DATA5_DN GP_CP1_DATA5_DN AA30 5
    IN FSB_CP_GP1_DATA6_DP FSB_GP_CP1_DATA6_DP OUT
    5 U33 CP_GP1_DATA6_DP GP_CP1_DATA6_DP AB33 5
    IN FSB_CP_GP1_DATA6_DN FSB_GP_CP1_DATA6_DN OUT
    5 U34 CP_GP1_DATA6_DN GP_CP1_DATA6_DN AB34 5
    IN OUT
    5 IN FSB_CP_GP1_DATA7_DP U30 CP_GP1_DATA7_DP GP_CP1_DATA7_DP AA34 FSB_GP_CP1_DATA7_DP OUT 5
    5 IN FSB_CP_GP1_DATA7_DN U29 CP_GP1_DATA7_DN GP_CP1_DATA7_DN AA33 FSB_GP_CP1_DATA7_DN OUT 5

    FSB_IMPED_CAL T28 FSB_IMPED_PCAL


    FSB_IMPED_NCAL AA28 FSB_IMPED_NCAL
    1
    R5R3
    4.87K X02056-010 V_MEM
    1%
    CH V_MEM
    402 1 R2R6 2
    2
    0 5% 1 1
    C2D5 402 CH
    1 2 R4U6 R2T1
    1K 1K
    .1UF 10% 5% 5%
    6.3V U2R1 EMPTY
    X5R CH CH
    402 SN74LVC1G125 402 402
    V_GPUCORE 2 2
    FSB DECOUPLING 5 VCC
    13 IN MEM_SCAN_BOT_EN_BUFF 2 IN OUT 4 OUT 21 23 25
    3 GND OE_N 1 27
    MEM_SCAN_BOT_EN

    X801565-001
    C4R27 C4R33 C4R45 C4T22 C5R18 C4R65 C4R60 C4T13
    .1UF .1UF .1UF .1UF .1UF .1UF .1UF .1UF
    10% 10% 10% 10% 10% 10% 10% 10%
    6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
    X5R X5R X5R X5R X5R X5R X5R X5R
    402 402 402 402 402 402 402 402 13 GPU_SCAN_BUFF_EN_N
    IN

    DRAWING
    PROJECT NAME PAGE REV
    XENON_FABK MICROSOFT
    [PAGE_TITLE=GPU, FSB] Wed Aug 24 09:27:06 2005 XENON_RETAIL 12/73 K7
    CONFIDENTIAL
    1 R4D3 2
    49.9
    402
    1%
    EMPTY
    GPU, VIDEO + PCIEX + EEPROM + JTAG
    1 R4D4 2
    49.9 1% U4D1 2 OF 12 IC
    402 EMPTY C4D1
    GPU VERSION 57 1 2 PEX_GPU_SB_L1_DP
    1 GPU_CLK_DP A25 1 OUT 33
    FT2P14 FTP 46 IN NB_CLK_DP FTP FT2P13
    46 GPU_CLK_DN A24 NB_CLK_DN .1UF 10%
    IN 6.3V
    GPU_RST_N E11 D14 GPU_RST_DONE X5R
    34 IN RST_IN_N* RST_DONE OUT 34 402

    33 PEX_SB_GPU_L1_DP B22 PEX_RX1_DP PEX_TX1_DP B23 PEX_GPU_SB_L1_DP_C


    C4D2
    IN PEX_SB_GPU_L1_DN 1 2 PEX_GPU_SB_L1_DN
    33 A22 PEX_RX1_DN PEX_TX1_DN A23 PEX_GPU_SB_L1_DN_C 33
    IN PEX_SB_GPU_L0_DP OUT
    33 B26 PEX_RX0_DP PEX_TX0_DP B27 PEX_GPU_SB_L0_DP_C
    IN .1UF 10%
    33 IN PEX_SB_GPU_L0_DN A26 PEX_RX0_DN PEX_TX0_DN A27 PEX_GPU_SB_L0_DN_C
    6.3V
    X5R
    1 R5D1 2 PEX_PCAL A28 402
    PEX_PCAL
    562 1% 1 R5D2 2 B28 PEX_NCAL C4D3
    PEX_NCAL
    402 CH V_GPUPCIE B21 PEX_ICAL 1 2 PEX_GPU_SB_L0_DP 33
    2K 1% GPU_PIX_CLK_1X OUT
    PIX_CLK_OUT B14 29
    402 CH OUT .1UF 10%
    D10 PIX_CLK_IN_DP PIX_DATA<14..0> 6.3V
    C10 B17 14 OUT 29
    1 R4R3 2 PEX_ICAL PIX_CLK_IN_DN PIX_DATA14 X5R
    PIX_DATA13 A17 13 402
    1.47K 1% V_MEM
    PIX_DATA12 D16 12 C5D1
    402 CH ANA_PIX_CLK_2X_DP B16 11 1 2 PEX_GPU_SB_L0_DN
    28 IN PIX_DATA11 OUT 33
    28 ANA_PIX_CLK_2X_DN PIX_DATA10 A16 10 1
    IN .1UF 10%
    29 IN GPU_TEMP_P C22 NB_THERMD_P PIX_DATA9 D15 9 R4D1 6.3V
    29 OUT GPU_TEMP_N C23 NB_THERMD_N PIX_DATA8 B15 8 1K X5R
    29 EDRAM_TEMP_P G14 ED_THERMD_P PIX_DATA7 A15 7 5% 402
    IN EDRAM_TEMP_N
    29 G15 ED_THERMD_N PIX_DATA6 A14 6 EMPTY
    OUT
    PIX_DATA5 D13 5 402
    PIX_DATA4 B13 4 2 DB4D1
    1
    PIX_DATA3 A13 3 TP
    PIX_DATA2 B12 2 1
    1 R3C28 2 DBG_LED3 A12 1
    IN 34 56 PIX_DATA1 R4D2
    1.27K 1% PIX_DATA0 D11 0 1K
    402 CH 5%
    VSYNC_OUT A11 GPU_VSYNC_OUT 29 CH
    OUT
    HSYNC_OUT B11 GPU_HSYNC_OUT OUT 29 402
    2
    13 GPU_SPI_SI G16 SROM_SO SROM_EN_PSRO_OUT G17 GPU_SROM_EN_PSRO_OUT
    IN GPU_SPI_SO
    SROM_SI E16 13
    GPU_SPI_CLK OUT
    1 R4T1 2 SROM_SCLK E15 13
    MEM_CALA
    GPU_SPI_CS_N OUT
    SROM_CS E14 13
    40.2 1% OUT
    402 CH 1 R4R8 2 MEM_CALB

    40.2 1% AG16 MEM_CALA MEM_RST AG11 MEM_RST 20 21 22 23 24 25 26 27


    MEM_SCAN_EN_BUFF OUT
    402 CH V8 MEM_CALB MEM_SCAN_EN AN13 12
    MEM_SCAN_TOP_EN_BUFF OUT
    MEM_SCAN_OEN_A G9 12
    OUT
    GPU_TCLK E13 TCLK MEM_SCAN_OEN_B G10 MEM_SCAN_BOT_EN_BUFF OUT 12
    GPU_TDO D12 TDO
    GPU_TDI 2 2
    E12 TDI
    GPU_TMS G12 TMS R2E1 R4F6
    GPU_TRST G11 TRST 1K 1K
    V_MEM V_MEM GPU_TRST_ED G13 5% 5%
    TRST_ED
    CH CH
    402 402
    X02056-010
    1 1
    1 1
    R2E2 R2E4
    1.5K 1.5K
    1% 1%
    CH CH J5C2
    402 J2D2 402
    2X4HDR V_1P8 2X3HDR
    2 2
    1 2 GPU_SPI_SI OUT 13
    1 2 V_1P8
    3 4 GPU_SPI_WP_N OUT 13
    3 4
    5 6
    5 6
    1
    7 8
    1 R4C7 EMPTY
    1 1 10K
    R2D10 EMPTY 5%
    1.5K R2D9 R2E3 1
    1.5K 1.5K CH C5C3 V_MEM
    1% 402 V_1P8 .1UF
    1% 1% 10%
    CH 2
    402 CH CH 2 6.3V
    402 402 U4C1 EMPTY X5R
    2 VIDEO DECOUPLING
    GPU_SCAN_BUFF_EN_N

    2 2 402
    AT25020A
    GPU_SPI_CLK R5C5 GPU_SPI_CLK_R 6 8
    13 IN SCK VCC
    1K 5% GPU_SPI_SO_R 5 SDI
    402 CH SDO 2 GPU_SPI_SI OUT 13 C3C2 C4R2 C4R26 C4R1
    7 HOLD_N* 10UF .1UF .1UF .1UF
    GPU_SPI_SO R5C8 GPU_SPI_CS_N_R 1
    20% 10% 10% 10%
    13 IN CS_N* 6.3V 6.3V 6.3V 6.3V
    1K 5% 3 WP_N* GND 4 2 X5R X5R X5R X5R
    805 402 402 402
    402 CH V_1P8 R4C6
    R4C3 X800552-001 10K
    13 GPU_SPI_CS_N 5%
    IN 2 R4C4 1
    1K 5% CH
    1 1 402 CH 10K 5% 402
    402 CH 1
    R5C10 R5P3
    12
    10K 10K
    OUT 5% 5% 2 R4C5 1 GPU_SPI_WP_N
    IN 13
    CH CH
    402 402 10K 5%
    2 2 402 EMPTY

    DRAWING
    PROJECT NAME PAGE REV
    XENON_FABK MICROSOFT
    [PAGE_TITLE=GPU, VIDEO + PCIEX + EEPROM + JTAG] Wed Aug 24 09:27:07 2005 XENON_RETAIL 13/73 K7
    CONFIDENTIAL
    GPU, MEMORY CONTROLLER 0 PARTITION A & B
    U4D1 3 OF 8 IC U4D1 4 OF 8 IC
    GPU VERSION 57 GPU VERSION 57
    21 20 MA_DQ31 AP19 MA_DQ31 23 22 MB_DQ31 AN27 MB_DQ31
    BI BI
    21 20 BI MA_DQ30 AN19 MA_DQ30 23 22 BI MB_DQ30 AP28 MB_DQ30
    21 20 BI MA_DQ29 AL18 MA_DQ29 23 22 BI MB_DQ29 AP27 MB_DQ29
    21 20 BI MA_DQ28 AN20 MA_DQ28 23 22 BI MB_DQ28 AP29 MB_DQ28
    21 20 MA_DQ27 AN18 MA_DQ27 23 22 MB_DQ27 AL25 MB_DQ27
    BI MA_DQ26 BI MB_DQ26
    21 20 AM20 MA_DQ26 23 22 AP31 MB_DQ26
    BI MA_DQ25 BI MB_DQ25
    21 20 AN17 MA_DQ25 23 22 AM25 MB_DQ25
    BI BI
    21 20 BI MA_DQ24 AL20 MA_DQ24 23 22 BI MB_DQ24 AP32 MB_DQ24
    21 20 OUT MA_WDQS3 AP20 MA_WDQS3 23 22 OUT MB_WDQS3 AP30 MB_WDQS3
    21 20 IN MA_RDQS3 AM18 MA_RDQS3 23 22 IN MB_RDQS3 AN26 MB_RDQS3
    21 20 MA_DM3 AP18 MA_DM3 23 22 MB_DM3 AP26 MB_DM3
    OUT OUT
    21 20 MA_DQ23 AP15 MA_DQ23 MA_CLK1_DP AH10 MA_CLK1_DP 21 23 22 MB_DQ23 AM23 MB_DQ23 MB_CLK1_DP AM33 MB_CLK1_DP 23
    BI OUT BI OUT
    21 20 BI MA_DQ22 AN15 MA_DQ22 MA_CLK1_DN AK10 MA_CLK1_DN OUT 21 23 22 BI MB_DQ22 AP23 MB_DQ22 MB_CLK1_DN AM34 MB_CLK1_DN OUT 23
    21 20 BI MA_DQ21 AM15 MA_DQ21 MA_CLK0_DP AN12 MA_CLK0_DP OUT 20 23 22 BI MB_DQ21 AL23 MB_DQ21 MB_CLK0_DP AL33 MB_CLK0_DP OUT 22
    21 20 BI MA_DQ20 AN14 MA_DQ20 MA_CLK0_DN AP12 MA_CLK0_DN OUT 20 23 22 BI MB_DQ20 AN23 MB_DQ20 MB_CLK0_DN AL34 MB_CLK0_DN OUT 22
    21 20 MA_DQ19 AN16 MA_DQ19 23 22 MB_DQ19 AN25 MB_DQ19
    BI MA_DQ18 MA_A<12..0> OUT 20 21 BI MB_DQ18 MB_A<12..0> OUT 22 23
    21 20 AL13 MA_DQ18 MA_A12 AN4 12 23 22 AP22 MB_DQ18 MB_A12 AK32 12
    BI MA_DQ17 BI MB_DQ17
    21 20 AP17 MA_DQ17 MA_A11 AP7 11 23 22 AP25 MB_DQ17 MB_A11 AE29 11
    BI BI
    21 20 BI MA_DQ16 AM13 MA_DQ16 MA_A10 AP4 10 23 22 BI MB_DQ16 AN21 MB_DQ16 MB_A10 AE34 10
    21 20 OUT MA_WDQS2 AP14 MA_WDQS2 MA_A9 AP8 9 23 22 OUT MB_WDQS2 AN22 MB_WDQS2 MB_A9 AJ30 9
    21 20 MA_RDQS2 AL15 MA_RDQS2 MA_A8 AN11 8 23 22 MB_RDQS2 AP24 MB_RDQS2 MB_A8 AK33 8
    IN MA_DM2 IN MB_DM2
    21 20 AP16 MA_DM2 MA_A7 AP9 7 23 22 AN24 MB_DM2 MB_A7 AJ33 7
    OUT OUT
    MA_A6 AN10 6 MB_A6 AK34 6
    21 20 MA_DQ15 AH16 MA_DQ15 MA_A5 AP11 5 23 22 MB_DQ15 AH26 MB_DQ15 MB_A5 AM32 5
    BI BI
    21 20 BI MA_DQ14 AK20 MA_DQ14 MA_A4 AN9 4 23 22 BI MB_DQ14 AN32 MB_DQ14 MB_A4 AJ34 4
    21 20 BI MA_DQ13 AK16 MA_DQ13 MA_A3 AN8 3 23 22 BI MB_DQ13 AK26 MB_DQ13 MB_A3 AE30 3
    21 20 MA_DQ12 AH20 MA_DQ12 MA_A2 AN7 2 23 22 MB_DQ12 AN31 MB_DQ12 MB_A2 AF28 2
    BI MA_DQ11 BI MB_DQ11
    21 20 AH17 MA_DQ11 MA_A1 AN5 1 23 22 AN29 MB_DQ11 MB_A1 AE33 1
    BI MA_DQ10 BI MB_DQ10
    21 20 AJ19 MA_DQ10 MA_A0 AP6 0 23 22 AN30 MB_DQ10 MB_A0 AF29 0
    BI MA_DQ9 BI MB_DQ9
    21 20 AJ18 MA_DQ9 23 22 AK28 MB_DQ9
    BI MA_BA<2..0> 20 21 BI MB_BA<2..0> 22 23
    21 20 BI MA_DQ8 AH18 MA_DQ8 MA_BA2 AP10 2 OUT 23 22 BI MB_DQ8 AK29 MB_DQ8 MB_BA2 AH30 2 OUT
    21 20 OUT MA_WDQS1 AK19 MA_WDQS1 MA_BA1 AM10 1 23 22 OUT MB_WDQS1 AK30 MB_WDQS1 MB_BA1 AH33 1
    21 20 MA_RDQS1 AK17 MA_RDQS1 MA_BA0 AP5 0 23 22 MB_RDQS1 AN28 MB_RDQS1 MB_BA0 AG30 0
    IN MA_DM1 IN MB_DM1
    21 20 AM17 MA_DM1 23 22 AK27 MB_DM1
    OUT MA_CKE OUT MB_CKE
    MA_CKE AN6 20 21 MB_CKE AG34 22 23
    MA_DQ7 MA_WE_N OUT MB_DQ7 MB_WE_N OUT
    21 20 AK15 MA_DQ7 MA_WE_N* AJ9 20 21 23 22 AK25 MB_DQ7 MB_WE_N* AF33 22 23
    BI OUT BI OUT
    21 20 BI MA_DQ6 AH11 MA_DQ6 MA_CAS_N* AK8 MA_CAS_N OUT 20 21 23 22 BI MB_DQ6 AH21 MB_DQ6 MB_CAS_N* AF32 MB_CAS_N OUT 22 23
    21 20 BI MA_DQ5 AH15 MA_DQ5 MA_RAS_N* AK7 MA_RAS_N OUT 20 21 23 22 BI MB_DQ5 AH25 MB_DQ5 MB_RAS_N* AF31 MB_RAS_N OUT 22 23
    21 20 MA_DQ4 AK11 MA_DQ4 MA_CS1_N* AK9 MA_CS1_N 21 23 22 MB_DQ4 AK21 MB_DQ4 MB_CS1_N* AH34 MB_CS1_N 23
    BI MA_DQ3 MA_CS0_N OUT BI MB_DQ3 MB_CS0_N OUT
    21 20 AH13 MA_DQ3 MA_CS0_N* AL10 20 23 22 AH23 MB_DQ3 MB_CS0_N* AF34 22
    BI MA_DQ2 OUT BI MB_DQ2 OUT
    21 20 AK12 MA_DQ2 23 22 AK22 MB_DQ2
    BI BI
    21 20 BI MA_DQ1 AJ13 MA_DQ1 23 22 BI MB_DQ1 AJ23 MB_DQ1
    21 20 BI MA_DQ0 AH12 MA_DQ0 23 22 BI MB_DQ0 AH22 MB_DQ0
    21 20 OUT MA_WDQS0 AM12 MA_WDQS0 23 22 OUT MB_WDQS0 AM22 MB_WDQS0
    21 20 MA_RDQS0 AJ14 MA_RDQS0 23 22 MB_RDQS0 AJ24 MB_RDQS0
    IN MA_DM0 IN MB_DM0
    21 20 AK14 MA_DM0 23 22 AK24 MB_DM0
    OUT OUT
    AK6 MA_VREF1 AG33 MB_VREF1
    V_MEM AP13 MA_VREF0 AP21 MB_VREF0
    V_MEM

    1
    X02056-010 1 X02056-010
    R4T4
    549 R5E2
    1% 549 V_MEM
    CH V_MEM 1% V_MEM
    402 CH MEMORY CONTROLLER B, DECOUPLING
    2 MA_VREF1 402
    1 2
    MB_VREF1
    1
    1 R4T7
    1 549 R4T8
    R4T3 549 C4T47 C4T31 C4T34 C5T2 C4T39
    C4T40 1% 1 10UF .22UF .22UF .22UF .22UF
    .1UF 1.27K 1% 10% 10% 10% 10% 10%
    10% 1% CH V_MEM 1
    402 C5E1 R5E1 CH 6.3V 6.3V 6.3V 6.3V 6.3V
    6.3V 402 X5R X5R X5R X5R X5R
    2 X5R CH 2 MEMORY CONTROLLER A, DECOUPLING .1UF 1.27K 1206 402 402 402 402
    402 402 10% 1% 2
    2 MA_VREF0 2 6.3V MB_VREF0
    X5R CH
    402 402
    1 2 1
    1 C4R3 C4T29 C4T32 C4T42 C4T44 1
    R4T6 C4T45 10UF .22UF .22UF .22UF .22UF R4T5 C4T46
    1.27K .1UF 10% 10% 10% 10% 10% 1.27K .1UF
    1% 10% 6.3V 6.3V 6.3V 6.3V 6.3V 1% 10%
    6.3V X5R X5R X5R X5R X5R 6.3V C4T33 C5T3 C5T4 C5T1
    CH 2 X5R 1206 402 402 402 402 CH 2 X5R .22UF .22UF .22UF .22UF
    402 402 402 402 10% 10% 10% 10%
    2 2 6.3V 6.3V 6.3V 6.3V
    X5R X5R X5R X5R
    402 402 402 402

    C4T35 C4T27 C4T41 C4T43


    .22UF .22UF .22UF .22UF
    10% 10% 10% 10%
    6.3V 6.3V 6.3V 6.3V
    X5R X5R X5R X5R
    402 402 402 402

    DRAWING
    PROJECT NAME PAGE REV
    XENON_FABK MICROSOFT
    [PAGE_TITLE=GPU, MEMORY CONTROLLER A + B] Wed Aug 24 09:27:08 2005 XENON_RETAIL 14/73 K7
    CONFIDENTIAL
    GPU, MEMORY CONTROLLER 1 PARTITION C & D
    U4D1 5 OF 8 IC U4D1 6 OF 8 IC
    GPU VERSION 57 GPU VERSION 57
    25 24 BI MC_DQ31 R1 MC_DQ31 27 26 BI MD_DQ31 AC3 MD_DQ31
    25 24 MC_DQ30 R3 MC_DQ30 27 26 MD_DQ30 AC4 MD_DQ30
    BI MC_DQ29 BI MD_DQ29
    25 24 R2 MC_DQ29 27 26 AC1 MD_DQ29
    BI MC_DQ28 BI MD_DQ28
    25 24 R4 MC_DQ28 27 26 AD1 MD_DQ28
    BI MC_DQ27 BI MD_DQ27
    25 24 N4 MC_DQ27 27 26 AB1 MD_DQ27
    BI BI
    25 24 BI MC_DQ26 T2 MC_DQ26 27 26 BI MD_DQ26 AE2 MD_DQ26
    25 24 BI MC_DQ25 N3 MC_DQ25 27 26 BI MD_DQ25 AA2 MD_DQ25
    25 24 MC_DQ24 U1 MC_DQ24 27 26 MD_DQ24 AE1 MD_DQ24
    BI MC_WDQS3 BI MD_WDQS3
    25 24 T1 MC_WDQS3 27 26 AD2 MD_WDQS3
    OUT MC_RDQS3 OUT MD_RDQS3
    25 24 P2 MC_RDQS3 27 26 AC2 MD_RDQS3
    IN MC_DM3 IN MD_DM3
    25 24 P1 MC_DM3 27 26 AB2 MD_DM3
    OUT OUT
    25 24 BI MC_DQ23 L1 MC_DQ23 MC_CLK1_DP J1 MC_CLK1_DP OUT 25 27 26 BI MD_DQ23 W2 MD_DQ23 MD_CLK1_DP AD6 MD_CLK1_DP OUT 27
    25 24 MC_DQ22 K4 MC_DQ22 MC_CLK1_DN H1 MC_CLK1_DN 25 27 26 MD_DQ22 W1 MD_DQ22 MD_CLK1_DN AD5 MD_CLK1_DN 27
    BI MC_DQ21 MC_CLK0_DP OUT BI MD_DQ21 MD_CLK0_DP OUT
    25 24 L2 MC_DQ21 MC_CLK0_DP F1 24 27 26 Y2 MD_DQ21 MD_CLK0_DP AE4 26
    BI MC_DQ20 MC_CLK0_DN OUT BI MD_DQ20 MD_CLK0_DN OUT
    25 24 K3 MC_DQ20 MC_CLK0_DN E1 24 27 26 V4 MD_DQ20 MD_CLK0_DN AE3 26
    BI MC_DQ19 OUT BI MD_DQ19 OUT
    25 24 N2 MC_DQ19 27 26 Y4 MD_DQ19
    BI MC_A<12..0> 24 25 BI MD_A<12..0> 26 27
    25 24 BI MC_DQ18 K2 MC_DQ18 MC_A12 A10 12 OUT 27 26 BI MD_DQ18 V1 MD_DQ18 MD_A12 AK5 12 OUT
    25 24 BI MC_DQ17 N1 MC_DQ17 MC_A11 A7 11 27 26 BI MD_DQ17 AA1 MD_DQ17 MD_A11 AL2 11
    25 24 MC_DQ16 J2 MC_DQ16 MC_A10 B10 10 27 26 MD_DQ16 V2 MD_DQ16 MD_A10 AM2 10
    BI MC_WDQS2 BI MD_WDQS2
    25 24 K1 MC_WDQS2 MC_A9 B6 9 27 26 V3 MD_WDQS2 MD_A9 AF5 9
    OUT MC_RDQS2 OUT MD_RDQS2
    25 24 M1 MC_RDQS2 MC_A8 D1 8 27 26 Y1 MD_RDQS2 MD_A8 AE5 8
    IN IN
    25 24 OUT MC_DM2 M2 MC_DM2 MC_A7 A5 7 27 26 OUT MD_DM2 Y3 MD_DM2 MD_A7 AF2 7
    MC_A6 A4 6 MD_A6 AF7 6
    25 24 BI MC_DQ15 J6 MC_DQ15 MC_A5 C1 5 27 26 BI MD_DQ15 W6 MD_DQ15 MD_A5 AE7 5
    25 24 MC_DQ14 N6 MC_DQ14 MC_A4 B5 4 27 26 MD_DQ14 AC7 MD_DQ14 MD_A4 AG2 4
    BI MC_DQ13 BI MD_DQ13
    25 24 J5 MC_DQ13 MC_A3 A6 3 27 26 W5 MD_DQ13 MD_A3 AM1 3
    BI MC_DQ12 BI MD_DQ12
    25 24 N7 MC_DQ12 MC_A2 B7 2 27 26 AC6 MD_DQ12 MD_A2 AJ2 2
    BI BI
    25 24 BI MC_DQ11 L5 MC_DQ11 MC_A1 A9 1 27 26 BI MD_DQ11 AA5 MD_DQ11 MD_A1 AM3 1
    25 24 BI MC_DQ10 M5 MC_DQ10 MC_A0 B8 0 27 26 BI MD_DQ10 AB5 MD_DQ10 MD_A0 AK2 0
    25 24 BI MC_DQ9 L7 MC_DQ9 MC_BA<2..0> 27 26 BI MD_DQ9 AA7 MD_DQ9 MD_BA<2..0>
    MC_DQ8 M3 B4 2 OUT 24 25 MD_DQ8 AB3 AG5 2 OUT 26 27
    25 24 BI MC_DQ8 MC_BA2 27 26 BI MD_DQ8 MD_BA2
    25 24 MC_WDQS1 M7 MC_WDQS1 MC_BA1 A3 1 27 26 MD_WDQS1 AB7 MD_WDQS1 MD_BA1 AH2 1
    OUT MC_RDQS1 OUT MD_RDQS1
    25 24 K5 MC_RDQS1 MC_BA0 B9 0 27 26 Y5 MD_RDQS1 MD_BA0 AJ5 0
    IN IN
    25 24 OUT MC_DM1 K7 MC_DM1 27 26 OUT MD_DM1 Y7 MD_DM1
    MC_CKE A8 MC_CKE OUT 24 25 MD_CKE AK1 MD_CKE OUT 26 27
    25 24 BI MC_DQ7 H2 MC_DQ7 MC_WE_N* E7 MC_WE_N OUT 24 25 27 26 BI MD_DQ7 V7 MD_DQ7 MD_WE_N* AH1 MD_WE_N OUT 26 27
    25 24 MC_DQ6 B2 MC_DQ6 MC_CAS_N* E8 MC_CAS_N 24 25 27 26 MD_DQ6 P6 MD_DQ6 MD_CAS_N* AJ1 MD_CAS_N 26 27
    BI MC_DQ5 MC_RAS_N OUT BI MD_DQ5 MD_RAS_N OUT
    25 24 H5 MC_DQ5 MC_RAS_N* E9 24 25 27 26 V6 MD_DQ5 MD_RAS_N* AL1 26 27
    BI MC_DQ4 MC_CS1_N OUT BI MD_DQ4 MD_CS1_N OUT
    25 24 C2 MC_DQ4 MC_CS1_N* E6 25 27 26 P5 MD_DQ4 MD_CS1_N* AH5 27
    BI OUT BI OUT
    25 24 BI MC_DQ3 F2 MC_DQ3 MC_CS0_N* B3 MC_CS0_N OUT 24 27 26 BI MD_DQ3 U3 MD_DQ3 MD_CS0_N* AG1 MD_CS0_N OUT 26
    25 24 BI MC_DQ2 E5 MC_DQ2 27 26 BI MD_DQ2 R5 MD_DQ2
    25 24 MC_DQ1 F5 MC_DQ1 27 26 MD_DQ1 T5 MD_DQ1
    BI MC_DQ0 BI MD_DQ0
    25 24 E2 MC_DQ0 27 26 T7 MD_DQ0
    BI MC_WDQS0 BI MD_WDQS0
    25 24 D2 MC_WDQS0 27 26 R7 MD_WDQS0
    OUT MC_RDQS0 OUT MD_RDQS0
    25 24 G5 MC_RDQS0 27 26 U5 MD_RDQS0
    IN IN
    25 24 OUT MC_DM0 G2 MC_DM0 27 26 OUT MD_DM0 U7 MD_DM0

    G1 MC_VREF1 AF1 MD_VREF1


    E10 MC_VREF0 V_MEM U2 MD_VREF0
    V_MEM

    2
    X02056-010 1 X02056-010
    R4R4
    549 R3T2
    1% V_MEM
    549 V_MEM
    1% V_MEM
    CH
    402 CH
    402 MEMORY CONTROLLER D, DECOUPLING
    1 2
    MC_VREF1
    2 MD_VREF1
    1
    R4R1 R4R6 1 1 1 1 1
    1 549 1 549 C4T28 C4R15 C4R61 C4T38 C4R50
    1% V_MEM 1 1% 10UF .22UF .22UF .22UF .22UF
    1 R4R5 C4T36 R4T2 10% 10% 10% 10% 10%
    C4R25 CH .1UF 1.27K CH 6.3V 6.3V 6.3V 6.3V 6.3V
    .1UF 1.27K 402 MEMORY CONTROLLER C, DECOUPLING 10% 1% 402 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R
    10% 1% 1 6.3V 2 1206 402 402 402 402
    6.3V 2 X5R CH
    2 X5R CH MC_VREF0 402 402
    402 402 2 MD_VREF0
    2 1 1 1 1 1 1
    1 C3R5 C4R38 C4R51 C4T14 C4R48
    R4R2 C4R10 10UF .22UF .22UF .22UF .22UF 1
    1.27K .1UF 10% 10% 10% 10% 10% 1
    10% 6.3V 6.3V 6.3V 6.3V 6.3V R4R7 C4R64
    1% 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 1 1 1 1
    6.3V 1.27K .1UF C4T7 C4R31 C4R12 C4R19
    CH 2 X5R 1206 402 402 402 402
    1% 10%
    402 402 6.3V .22UF .22UF .22UF .22UF
    2 CH 2 X5R 10% 10% 10% 10%
    402 6.3V 6.3V 6.3V 6.3V
    402 2 X5R 2 X5R 2 X5R 2 X5R
    2 402 402 402 402

    1 1 1 1
    C4R23 C4R66 C4T12 C4R32
    .22UF .22UF .22UF .22UF
    10% 10% 10% 10%
    6.3V 6.3V 6.3V 6.3V
    2 X5R 2 X5R 2 X5R 2 X5R
    402 402 402 402

    DRAWING
    PROJECT NAME PAGE REV
    XENON_FABK MICROSOFT
    PAGE_TITLE=[GPU, MEMORY CONTROLLER C + D] Wed Aug 24 09:27:10 2005
    CONFIDENTIAL
    XENON_RETAIL 15/73 K7
    GPU, PLL POWER + FSB POWER

    V_GPUCORE

    FB4D1
    1 2
    120 FB
    0.2A 603 1 1 1
    0.5 DCR C4D6 C4D5 C4D4
    2.2UF .1UF 0.01UF
    10% 10% 10%
    6.3V 6.3V 16V
    2 X5R 2 X5R 2 X7R
    603 402 402

    V_GPUCORE

    V_GPUPCIE U4D1 8 OF 12 IC
    GPU VERSION 57
    FB4T1 VDD_FSB24 AA27
    1 2 VDD_FSB23 AB28
    120 FB V_PVDDA A20 PVDDA VDD_FSB22 AB32
    0.2A 603 1 1 1 1 A21 PVSSA VDD_FSB21 AC27
    0.5 DCR C5R7 C4R8
    C4T48 C4T30 C4T37 .1UF .1UF VDD_FSB20 AD28
    2.2UF .1UF 0.01UF 10% 10% C27 VDD_BSB1 VDD_FSB19 AD31
    10% 10% 10% 6.3V 6.3V
    6.3V 6.3V 16V 2 X5R 2 X5R C26 VSS_BSB1 VDD_FSB18 K28
    2 X5R 2 X5R X7R 402 402 K31
    603 402 402 VDD_FSB17
    C25 VDD_BSB0 VDD_FSB16 L27
    C24 VSS_BSB0 VDD_FSB15 M28
    VDD_FSB14 M32
    V_PVDDA_MEM AG10 PVDDA_MEM VDD_FSB13 N27
    AG9 PVSSA_MEM VDD_FSB12 P28
    FB4R1 VDD_FSB11 P31
    1 2 V_PVDDA_ED A18 PVDDA_ED VDD_FSB10 R28
    120 FB A19 PVSSA_ED VDD_FSB9 R32
    0.2A 603 1 1 VDD_FSB8 T27
    0.5 DCR C4R68 C4R4 C4R6 B25 PVDDA_PEX VDD_FSB7 U28
    2.2UF .1UF 0.01UF B24 PVSSA_PEX VDD_FSB6 U31
    10% 10% 10%
    6.3V 6.3V 16V VDD_FSB5 V27
    2 X5R 2 X5R X7R V_PVDDA_FSB G34 V30
    603 402 402 PVDDA_FSB VDD_FSB4
    F34 PVSSA_FSB VDD_FSB3 W28
    VDD_FSB2 W32
    V_GPUPCIE VDD_FSB1 Y28
    VDD_FSB0 Y31

    X02056-010

    1
    C4R5 C4R7
    .1UF 0.01UF
    10% 10%
    2 6.3V 16V
    X5R X7R
    402 402

    FB5R1
    1 2
    120 FB
    0.2A 603 1 1
    0.5 DCR C5R19 C5R13 C5R15
    2.2UF .1UF 0.01UF
    10% 10% 10%
    6.3V 6.3V 16V
    2 X5R 2 X5R X7R
    603 402 402

    DRAWING
    PROJECT NAME PAGE REV
    XENON_FABK MICROSOFT
    [PAGE_TITLE=GPU, PLL POWER + FSB POWER] Wed Aug 24 09:27:10 2005 XENON_RETAIL 16/73 K7
    CONFIDENTIAL
    GPU, CORE POWER + MEM POWER

    V_GPUCORE V_GPUCORE
    U4D1 IC
    U4D1 IC 12 OF 12
    U4D1 9 OF 12 IC
    11 OF 12
    GPU VERSION 51
    GPU VERSION 57
    AA14 L11 GPU VERSION 51 F21 P18
    VDD_CORE139 VDD_CORE69 V_MEM V_MEM VSS130 VSS65
    AA15 VDD_CORE138 VDD_CORE68 L12 A1 VSS260 VSS195 AJ15 F24 VSS129 VSS64 P22
    AA16 VDD_CORE137 VDD_CORE67 L13 AA3 VSS259 VSS194 AJ17 F26 VSS128 VSS63 P23
    AA19 L17 U4D1 10 OF 12 IC AA8 AJ20 F28 P24
    VDD_CORE136 VDD_CORE66 VSS258 VSS193 VSS127 VSS62
    AA20 VDD_CORE135 VDD_CORE65 L18 GPU VERSION 57 AA11 VSS257 VSS192 AJ25 F31 VSS126 VSS61 P27
    AA21 VDD_CORE134 VDD_CORE64 L22 AA4 VDD_MEM111 VDD_MEM55 AL28 AA12 VSS256 VSS191 AJ27 G4 VSS125 VSS60 P32
    AB11 VDD_CORE133 VDD_CORE63 L23 AA6 VDD_MEM110 VDD_MEM54 AL30 AA13 VSS255 VSS190 AJ29 G7 VSS124 VSS59 R6
    AB12 VDD_CORE132 VDD_CORE62 L24 AB6 VDD_MEM109 VDD_MEM53 AL32 AA17 VSS254 VSS189 AJ31 G18 VSS123 VSS58 R11
    AB13 VDD_CORE131 VDD_CORE61 M11 AC5 VDD_MEM108 VDD_MEM52 AM5 AA18 VSS253 VSS188 AK4 G20 VSS122 VSS57 R12
    AB17 VDD_CORE130 VDD_CORE60 M12 AC8 VDD_MEM107 VDD_MEM51 AM7 AA22 VSS252 VSS187 AK18 G27 VSS121 VSS56 R13
    AB18 VDD_CORE129 VDD_CORE59 M13 AD4 VDD_MEM106 VDD_MEM50 AM9 AA23 VSS251 VSS186 AL3 G29 VSS120 VSS55 R17
    AB22 VDD_CORE128 VDD_CORE58 M17 AD7 VDD_MEM105 VDD_MEM49 AM16 AA24 VSS250 VSS185 AL5 G33 VSS119 VSS54 R18
    AB23 VDD_CORE127 VDD_CORE57 M18 AE8 VDD_MEM104 VDD_MEM48 AM19 AB4 VSS249 VSS184 AL7 H3 VSS118 VSS53 R22
    AB24 VDD_CORE126 VDD_CORE56 M22 AE28 VDD_MEM103 VDD_MEM47 AM26 AB8 VSS248 VSS183 AL9 H6 VSS117 VSS52 R23
    AC11 VDD_CORE125 VDD_CORE55 M23 AE31 VDD_MEM102 VDD_MEM46 AM27 AB14 VSS247 VSS182 AL12 H8 VSS116 VSS51 R24
    AC12 VDD_CORE124 VDD_CORE54 M24 AF3 VDD_MEM101 VDD_MEM45 AM29 AB15 VSS246 VSS181 AL16 H9 VSS115 VSS50 R27
    AC13 VDD_CORE123 VDD_CORE53 N11 AF6 VDD_MEM100 VDD_MEM44 AM31 AB16 VSS245 VSS180 AL19 H11 VSS114 VSS49 R31
    AC17 VDD_CORE122 VDD_CORE52 N12 AF27 VDD_MEM99 VDD_MEM43 AN2 AB19 VSS244 VSS179 AL22 H13 VSS113 VSS48 T4
    AC18 VDD_CORE121 VDD_CORE51 N13 AF30 VDD_MEM98 VDD_MEM42 AP3 AB20 VSS243 VSS178 AL26 H15 VSS112 VSS47 T8
    AC22 VDD_CORE120 VDD_CORE50 N17 AG4 VDD_MEM97 VDD_MEM41 C3 AB21 VSS242 VSS177 AL27 H17 VSS111 VSS46 T11
    AC23 VDD_CORE119 VDD_CORE49 N18 AG7 VDD_MEM96 VDD_MEM40 C5 AB27 VSS241 VSS176 AL29 H19 VSS110 VSS45 T12
    AC24 VDD_CORE118 VDD_CORE48 N22 AG13 VDD_MEM95 VDD_MEM39 C7 AB31 VSS240 VSS175 AL31 H21 VSS109 VSS44 T13
    AD11 VDD_CORE117 VDD_CORE47 N23 AG15 VDD_MEM94 VDD_MEM38 C9 AC14 VSS239 VSS174 AM4 H23 VSS108 VSS43 T17
    AD12 VDD_CORE116 VDD_CORE46 N24 AG17 VDD_MEM93 VDD_MEM37 C12 AC15 VSS238 VSS173 AM6 H25 VSS107 VSS42 T18
    AD13 VDD_CORE115 VDD_CORE45 P14 AG20 VDD_MEM92 VDD_MEM36 C14 AC16 VSS237 VSS172 AM8 H28 VSS106 VSS41 T22
    AD17 VDD_CORE114 VDD_CORE44 P15 AG23 VDD_MEM91 VDD_MEM35 C16 AC19 VSS236 VSS171 AM11 J4 VSS105 VSS40 T23
    AD18 VDD_CORE113 VDD_CORE43 P16 AG25 VDD_MEM90 VDD_MEM34 C18 AC20 VSS235 VSS170 AM14 J8 VSS104 VSS39 T24
    AD22 VDD_CORE112 VDD_CORE42 P19 AG28 VDD_MEM89 VDD_MEM33 D4 AC21 VSS234 VSS169 AM21 J28 VSS103 VSS38 U6
    AD23 VDD_CORE111 VDD_CORE41 P20 AG32 VDD_MEM88 VDD_MEM32 D6 AC30 VSS233 VSS168 AM24 K6 VSS102 VSS37 U14
    AD24 VDD_CORE110 VDD_CORE40 P21 AH3 VDD_MEM87 VDD_MEM31 D8 AD3 VSS232 VSS167 AM28 K27 VSS101 VSS36 U15
    B18 VDD_CORE109 VDD_CORE39 R14 AH6 VDD_MEM86 VDD_MEM30 E3 AD8 VSS231 VSS166 AM30 K32 VSS100 VSS35 U16
    B20 VDD_CORE108 VDD_CORE38 R15 AH8 VDD_MEM85 VDD_MEM29 F4 AD14 VSS230 VSS165 AN3 L3 VSS99 VSS34 U19
    C19 VDD_CORE107 VDD_CORE37 R16 AH9 VDD_MEM84 VDD_MEM28 F7 AD15 VSS229 VSS164 AN33 L8 VSS98 VSS33 U20
    C21 VDD_CORE106 VDD_CORE36 R19 AH14 VDD_MEM83 VDD_MEM27 F9 AD16 VSS228 VSS163 B19 L14 VSS97 VSS32 U21
    C29 VDD_CORE105 VDD_CORE35 R20 AH19 VDD_MEM82 VDD_MEM26 F11 AD19 VSS227 VSS162 B33 L15 VSS96 VSS31 U27
    C31 VDD_CORE104 VDD_CORE34 R21 AH24 VDD_MEM81 VDD_MEM25 F13 AD20 VSS226 VSS161 C4 L16 VSS95 VSS30 U32
    C33 VDD_CORE103 VDD_CORE33 T14 AH27 VDD_MEM80 VDD_MEM24 F15 AD21 VSS225 VSS160 C6 L19 VSS94 VSS29 V5
    C34 VDD_CORE102 VDD_CORE32 T15 AH29 VDD_MEM79 VDD_MEM23 G3 AD27 VSS224 VSS159 C8 L20 VSS93 VSS28 V14
    D17 VDD_CORE101 VDD_CORE31 T16 AH31 VDD_MEM78 VDD_MEM22 G6 AD32 VSS223 VSS158 C11 L21 VSS92 VSS27 V15
    D18 VDD_CORE100 VDD_CORE30 T19 AJ4 VDD_MEM77 VDD_MEM21 G8 AE6 VSS222 VSS157 C13 L28 VSS91 VSS26 V16
    D20 VDD_CORE99 VDD_CORE29 T20 AJ7 VDD_MEM76 VDD_MEM20 H4 AE27 VSS221 VSS156 C15 M4 VSS90 VSS25 V19
    D22 VDD_CORE98 VDD_CORE28 T21 AJ11 VDD_MEM75 VDD_MEM19 H7 AE32 VSS220 VSS155 C17 M8 VSS89 VSS24 V20
    D30 VDD_CORE97 VDD_CORE27 U11 AJ12 VDD_MEM74 VDD_MEM18 H10 AF4 VSS219 VSS154 C20 M14 VSS88 VSS23 V21
    D32 VDD_CORE96 VDD_CORE26 U12 AJ16 VDD_MEM73 VDD_MEM17 J3 AF8 VSS218 VSS153 C28 M15 VSS87 VSS22 W4
    D34 VDD_CORE95 VDD_CORE25 U13 AJ21 VDD_MEM72 VDD_MEM16 J7 AG3 VSS217 VSS152 C32 M16 VSS86 VSS20 W11
    E17 VDD_CORE94 VDD_CORE24 U17 AJ22 VDD_MEM71 VDD_MEM15 K8 AG6 VSS216 VSS151 D3 M19 VSS85 VSS21 W8
    E19 VDD_CORE93 VDD_CORE23 U18 AJ26 VDD_MEM70 VDD_MEM14 L4 AG8 VSS215 VSS150 D5 M20 VSS84 VSS19 W12
    E21 VDD_CORE92 VDD_CORE22 U22 AJ28 VDD_MEM69 VDD_MEM13 L6 AG12 VSS214 VSS149 D7 M21 VSS83 VSS18 W13
    E31 VDD_CORE91 VDD_CORE21 U23 AJ32 VDD_MEM68 VDD_MEM12 M6 AG14 VSS213 VSS148 D9 M27 VSS82 VSS17 W17
    F17 VDD_CORE90 VDD_CORE20 U24 AK3 VDD_MEM67 VDD_MEM11 N5 AG18 VSS212 VSS147 D19 M31 VSS81 VSS16 W18
    F18 VDD_CORE89 VDD_CORE19 V11 AK13 VDD_MEM66 VDD_MEM10 N8 AG19 VSS211 VSS146 D21 N14 VSS80 VSS15 W22
    F20 VDD_CORE88 VDD_CORE18 V12 AK23 VDD_MEM65 VDD_MEM9 P4 AG21 VSS210 VSS145 D31 N15 VSS79 VSS14 W23
    F23 VDD_CORE87 VDD_CORE17 V13 AK31 VDD_MEM64 VDD_MEM8 P7 AG22 VSS209 VSS144 E4 N16 VSS78 VSS13 W24
    F25 VDD_CORE86 VDD_CORE16 V17 AL4 VDD_MEM63 VDD_MEM7 R8 AG24 VSS208 VSS143 E18 N19 VSS77 VSS12 W27
    F27 VDD_CORE85 VDD_CORE15 V18 AL6 VDD_MEM62 VDD_MEM6 T3 AG26 VSS207 VSS142 E20 N20 VSS76 VSS11 W31
    F29 VDD_CORE84 VDD_CORE14 V22 AL8 VDD_MEM61 VDD_MEM5 T6 AG27 VSS206 VSS141 E22 N21 VSS75 VSS10 Y6
    F30 VDD_CORE83 VDD_CORE13 V23 AL11 VDD_MEM60 VDD_MEM4 U4 AG29 VSS205 VSS140 E30 N28 VSS74 VSS9 Y11
    G19 VDD_CORE82 VDD_CORE12 V24 AL14 VDD_MEM59 VDD_MEM3 U8 AG31 VSS204 VSS139 E32 N29 VSS73 VSS8 Y12
    G28 VDD_CORE81 VDD_CORE11 W14 AL17 VDD_MEM58 VDD_MEM2 W3 AH4 VSS203 VSS138 F3 N30 VSS72 VSS7 Y13
    G32 VDD_CORE80 VDD_CORE10 W15 AL21 VDD_MEM57 VDD_MEM1 W7 AH7 VSS202 VSS137 F6 P3 VSS71 VSS6 Y17
    H12 VDD_CORE79 VDD_CORE9 W16 AL24 VDD_MEM56 VDD_MEM0 Y8 AH28 VSS201 VSS136 F8 P8 VSS70 VSS5 Y18
    H14 VDD_CORE78 VDD_CORE8 W19 AH32 VSS200 VSS135 F10 P11 VSS69 VSS4 Y22
    H16 VDD_CORE77 VDD_CORE7 W20 AJ3 VSS199 VSS134 F12 P12 VSS68 VSS3 Y23
    H18 W21 X02056-010 BGA AJ6 F14 P13 Y24
    VDD_CORE76 VDD_CORE6 VSS198 VSS133 VSS67 VSS2
    H20 VDD_CORE75 VDD_CORE5 Y14 AJ8 VSS197 VSS132 F16 P17 VSS66 VSS1 Y27
    H22 VDD_CORE74 VDD_CORE4 Y15 AJ10 VSS196 VSS131 F19 VSS0 Y32
    H24 VDD_CORE73 VDD_CORE3 Y16
    H26 VDD_CORE72 VDD_CORE2 Y19
    H27 Y20 X02056-010 BGA X02056-010 BGA
    VDD_CORE71 VDD_CORE1
    J27 VDD_CORE70 VDD_CORE0 Y21

    X02056-010 BGA

    DRAWING
    PROJECT NAME PAGE REV
    XENON_FABK MICROSOFT
    [PAGE_TITLE=GPU, CORE POWER + MEM POWER] Wed Aug 24 09:27:11 2005 XENON_RETAIL 17/73 K7
    CONFIDENTIAL
    GPU, DECOUPLING
    V_GPUCORE V_GPUCORE

    C4R20 C4R11 C4R16 C4R28 C4R13 C5R9 C4R39 C5D2 C4R29


    1 2 1 2 1 2 1 2 1 2 1 2 1 2 2 1 2 1

    .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% 4.7UF 10% 4.7UF 10%
    6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
    X5R X5R X5R X5R X5R X5R X5R X5R X5R
    402 402 402 402 402 402 402 805 805

    C4R37 C4R17 C4R21 C4R22 C5R17 C5R16 C4R49 C4R30 C4T17


    1 2 1 2 1 2 1 2 1 2 1 2 1 2 2 1 2 1

    .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% 4.7UF 10% 4.7UF 10%
    6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
    X5R X5R X5R X5R X5R X5R X5R X5R X5R
    402 402 402 402 402 402 402 805 805

    C6E2
    C4R59 C4R55 C4T5 C4T23 C4R53 C5R10 C4R67 C5R5 2 1
    1 2 1 2 1 2 1 2 1 2 2 1 2 1 2 1
    4.7UF 10%
    .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% 4.7UF 10% 6.3V
    6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V X5R
    X5R X5R X5R X5R X5R X5R X5R X5R 805
    402 402 402 402 402 402 402 805

    C6E1
    C4T6 C4R47 C4T21 C4R44 C4R41 C5R12 C5R4 2 1
    1 2 1 2 1 2 1 2 1 2 1 2 2 1
    4.7UF 10%
    .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% 4.7UF 10% 6.3V
    6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V X5R
    X5R X5R X5R X5R X5R X5R X5R 805
    402 402 402 402 402 402 805

    C4T9 C4T20 C4R46 C4T24 C4T26 C4R24 C5R20 C6R47


    1 2 1 2 1 2 1 2 1 2 1 2 2 1 2 1

    .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% 4.7UF 10% 4.7UF 10%
    6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
    X5R X5R X5R X5R X5R X5R X5R X5R
    402 402 402 402 402 402 805 805

    C4R57 C4R36 C4T8 C4T19 C4T25 C4R40 C5R2 C4R69


    1 2 1 2 1 2 1 2 1 2 1 2 1 2 2 1

    .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% 4.7UF 10% 4.7UF 10%
    6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
    X5R X5R X5R X5R X5R X5R X5R X5R
    402 402 402 402 402 402 805 805

    C4T11 C4R34 C4R35 C4T18 C4T4 C5R8 C5R1 C5D3


    1 2 1 2 1 2 1 2 1 2 1 2 2 1 2 1

    .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% 4.7UF 10% 4.7UF 10%
    6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
    X5R X5R X5R X5R X5R X5R X5R X5R
    402 402 402 402 402 402 805 805

    C4T3 C4R42 C4R54 C4R62 C4R58 C4R9 C5R3 C5D4


    1 2 1 2 1 2 1 2 1 2 1 2 2 1 2 1

    .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% 4.7UF 10% 4.7UF 10%
    6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
    X5R X5R X5R X5R X5R X5R X5R X5R
    402 402 402 402 402 402 805 805

    C5R11 C5D6
    C4R52 C4T16 C4R63 C4R43 C4T10 C5R14 2 1 2 1
    1 2 1 2 1 2 1 2 1 2 1 2
    4.7UF 10% 4.7UF 10%
    .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% 6.3V 6.3V
    6.3V 6.3V 6.3V 6.3V 6.3V 6.3V X5R X5R
    X5R X5R X5R X5R X5R X5R 805 805
    402 402 402 402 402 402

    C4R18 C4T1 C4T2 C4R56 C4T15 C4R14 C5R6 C5D5


    1 2 1 2 1 2 1 2 1 2 1 2 2 1 2 1

    .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% 4.7UF 10% 4.7UF 10%
    6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
    X5R X5R X5R X5R X5R X5R X5R X5R
    402 402 402 402 402 402 805 805

    DRAWING
    PROJECT NAME PAGE REV
    XENON_FABK MICROSOFT
    [PAGE_TITLE=GPU, DECOUPLING] Wed Aug 24 09:27:12 2005 XENON_RETAIL 18/73 K7
    CONFIDENTIAL
    V_1P8

    FB1N1
    2 1 ENET_AVDD 19
    OUT
    60 EMPTY
    0.5A 603
    0.1DCR 1 1
    C1N7 C1N14
    1 10UF .1UF
    C1N8 20% 10%
    10UF 2 6.3V 2 6.3V
    10% EMPTY EMPTY
    6.3V 805 402
    2 EMPTY
    1206

    ENET_CLK U1B1 EMPTY


    39 46 IN
    BCM5241
    DB1N1 1 XTALI2
    TP 1 ENET_REF_CLK2_OUT 2 XTALO2
    44 19 39 IN V_ENET ENET_RST_N 10
    39 33 IN RESET_N

    1 36 39 MII_RX_CLK 20 RXC
    OUT
    R1B12 36 39 OUT MII_RXDV 19 RX_DV/TEST0
    4.7K 36 39 OUT MII_RXER 21 RX_ER/TEST1 OVDD2 22 V_ENET IN 39 19 44
    5% OVDD1 9
    EMPTY 36 39 MII_RXD3 15 RXD3/ISOLATE
    OUT 16 7 ENET_AVDD
    402 36 39 OUT MII_RXD2 RXD2/F100 AVDD IN 19
    2 36 39 MII_RXD1 17 RXD1/ANEN
    OUT
    36 39 OUT MII_RXD0 18 RXD0/PHYAD0 LINK# 12 ENET_LINK_N OUT 39 44
    ACT# 11 ENET_ACT_N OUT 39 44
    36 39 MII_TX_CLK 23 TXC
    OUT 24 3
    39 36 IN MII_TXEN TX_EN TDP ENET_RX_DP OUT 39 44
    TDN 4 ENET_RX_DN 39 44
    OUT
    39 36 IN MII_TXD3 28 TXD3
    39 36 IN MII_TXD2 27 TXD2 RDP 6 ENET_TX_DP OUT 39 44
    39 36 IN MII_TXD1 26 TXD1 RDN 5 ENET_TX_DN OUT 39 44
    39 36 MII_TXD0 25 TXD0
    IN 8
    RDAC
    39 36 MII_MDC_CLK_OUT 14 MDC_CLK_OUT
    IN
    MII_MDIO 13 33

    ENET_RDAC
    39 36 BI MDIO GND

    36 39 OUT MII_COL 29 COL/ENERGYDET


    36 39 MII_CRS 30 CRS/LOWPWR0
    OUT
    31 REGVDDIN 1
    19 IN ENET_AVDD 32 REGVDDOUT R1N8
    1.27K
    1 1%
    C1N6
    .1UF X801554-001 LCC32 EMPTY
    10% 402
    2 6.3V 2
    EMPTY
    402

    DRAWING
    PROJECT NAME PAGE REV
    XENON_FABK MICROSOFT
    [PAGE_TITLE=DUAL ETHERNET PHY] Wed Aug 24 09:27:13 2005 XENON_RETAIL 19/73 K7
    CONFIDENTIAL
    MEMORY PARTITION A, TOP
    V_MEM CHIP SELECT = 0, MIRROR FUNCTION = 0

    1 1
    R4F3 R4F4
    60.4 60.4
    1% 1%
    CH CH
    402 402 U4F1 IC V_MEM
    2 2
    GDDR136
    14 IN MA_CLK0_DP MF=0 DQ31 T3 MA_DQ31 BI 14 21 U4F1 IC
    DQ30 T2 MA_DQ30 BI 14 21
    R3 MA_DQ29 GDDR136
    DQ29 BI 14 21 V1
    R2 MA_DQ28 VDDQ<21> MF=0
    DQ28 BI 14 21 R12
    M3 MA_DQ27 VDDQ<20>
    DQ27 BI 14 21 R9 T12
    N2 MA_DQ26 VDDQ<19> VSSQ<19>
    DQ26 BI 14 21 R4 T9
    L3 MA_DQ25 VDDQ<18> VSSQ<18>
    DQ25 BI 14 21 R1 T4
    M2 MA_DQ24 VDDQ<17> VSSQ<17>
    DQ24 BI 14 21 N12 T1
    J11 P2 MA_WDQS3 VDDQ<16> VSSQ<16>
    CLK_DP WDQS3 IN 14 21 N9 P12
    MA_CLK0_DN J10 P3 MA_RDQS3 VDDQ<15> VSSQ<15>
    14 IN CLK_DN RDQS3 OUT 21 14 V12 P9
    N3 MA_DM3 VDDQ<14> VSSQ<14>
    DM3 IN 14 21 N4 P4
    MEM_RST V9 VDDQ<13> VSSQ<13>
    27 26 25 24 23 22 21 13 IN RESET N1 P1
    T10 MA_DQ23 VDDQ<12> VSSQ<12>
    MA_A<11..0> DQ23 BI 14 21 J9 L11
    21 14 IN 11 L4 T11 MA_DQ22 VDDQ<11> VSSQ<11>
    A11/A7 DQ22 BI 14 21 J4 L2
    10 K2 R10 MA_DQ21 VDDQ<10> VSSQ<10>
    A10/A8 DQ21 BI 14 21 E12 G11
    9 M9 R11 MA_DQ20 VDDQ<9> VSSQ<9>
    A9/A3 DQ20 BI 14 21 E9 G2
    8 K11 M10 MA_DQ19 VDDQ<8> VSSQ<8>
    A8/A10 DQ19 BI 14 21 E4 D12
    7 L9 N11 MA_DQ18 VDDQ<7> VSSQ<7>
    A7/A11 DQ18 BI 14 21 E1 D9
    6 K10 L10 MA_DQ17 VDDQ<6> VSSQ<6>
    A6/A2 DQ17 BI 14 21 C12 D4
    5 H11 M11 MA_DQ16 VDDQ<5> VSSQ<5>
    A5/A1 DQ16 BI 14 21 C9 D1
    4 K9 P11 MA_WDQS2 VDDQ<4> VSSQ<4>
    A4/A0 WDQS2 IN 14 21 C4 B12
    3 M4 P10 MA_RDQS2 VDDQ<3> VSSQ<3>
    A3/A9 RDQS2 OUT 21 14 C1 B9
    2 K3 N10 MA_DM2 VDDQ<2> VSSQ<2>
    A2/A6 DM2 IN 14 21 A12 B4
    1 H2 VDDQ<1> VSSQ<1>
    A1/A5 A1 B1
    0 K4 G10 MA_DQ15 VDDQ<0> VSSQ<0>
    A0/A4 DQ15 BI 14 21
    MA_BA<2..0> DQ14 F11 MA_DQ14 BI 14 21 V2 V3
    21 14 IN 2 H10 F10 MA_DQ13 VDD<7> VSS<7>
    BA2/RAS_N DQ13 BI 14 21 M12 L12
    1 G9 E11 MA_DQ12 VDD<6> VSS<6>
    BA1/BA0 DQ12 BI 14 21 M1 L1
    0 G4 C10 MA_DQ11 VDD<5> VSS<5>
    BA0/BA1 DQ11 BI 14 21 V11 G12
    C11 MA_DQ10 VDD<4> VSS<4>
    DQ10 BI 14 21 F12 G1
    MA_CKE H4 B10 MA_DQ9 VDD<3> VSS<3>
    21 14 IN CKE/WE_N DQ9 BI 14 21 F1 A10
    MA_WE_N H9 B11 MA_DQ8 VDD<2> VSS<2>
    21 14 IN WE_N/CKE DQ8 BI 14 21 A11 V10
    MA_CAS_N F4 D11 MA_WDQS1 VDD<1> VSS<1>
    21 14 IN CAS_N/CS_N WDQS1 IN 14 21 A2 A3
    MA_RAS_N H3 D10 MA_RDQS1 VDD<0> VSS<0>
    21 14 IN RAS_N/BA2 RDQS1 OUT 21 14
    14 MA_CS0_N F9 CS_N/CAS_N DM1 E10 MA_DM1 14 21
    IN IN K12 VDDA<1> NC<1> J3
    K1 VDDA<0> NC<0> J2
    26 24 22 12 IN MEM_SCAN_TOP_EN A9 MF DQ7 G3 MA_DQ7 BI 14 21
    DQ6 F2 MA_DQ6 14 21
    MEM_SCAN_EN V4 F3 MA_DQ5 BI J12 VSSA<1>
    27 26 25 24 23 22 21 12 IN SCAN_EN DQ5 BI 14 21 J1
    E2 MA_DQ4 VSSA<0>
    DQ4 BI 14 21
    21 20 MEM_A_VREF1 H1 VREF1 DQ3 C3 MA_DQ3 14 21
    IN BI
    21 IN MEM_A_VREF0 H12 VREF0 DQ2 C2 MA_DQ2 BI 14 21
    B3 MA_DQ1 X801995-006
    DQ1 BI 14 21
    DQ0 B2 MA_DQ0 14 21
    D2 MA_WDQS0 BI
    WDQS0 IN 14 21
    RDQS0 D3 MA_RDQS0 21 14
    OUT
    DM0 E3 MA_DM0 IN 14 21
    V_MEM
    ZQ A4 MA_ZQ_TOP

    1
    X801995-006 R3F1
    1 243
    R4U4 1%
    549 CH
    1% 402
    CH
    2 V_MEM
    402 PARTITION A DECOUPLING
    2 V_MEM MEMORY A, TOP, DECOUPLING
    MEM_A_VREF1 20 21
    OUT

    1 1 C3F3 C4F9 C4F11 C4F7 C3F1 C4F1 C4F6 C4F3


    C4F12 .22UF .22UF .22UF .22UF .22UF .22UF .22UF .22UF
    R4U5 C4U9 10UF 10% 10% 10% 10% 10% 10% 10% 10%
    1.27K .1UF 10% 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
    10% 6.3V X5R X5R X5R X5R X5R X5R X5R X5R
    1% 2 X5R 402 402 402 402 402 402 402 402
    6.3V 1206
    CH X5R
    402 402
    2

    DRAWING
    PROJECT NAME PAGE REV
    [PAGE_TITLE=MEMORY PARTITION A, TOP] XENON_FABK
    Wed Aug 24 09:27:13 2005
    MICROSOFT
    XENON_RETAIL 20/73 K7
    CONFIDENTIAL
    V_MEM
    MEMORY PARTITION A, BOTTOM
    CHIP SELECT = 1, MIRROR FUNCTION = 1

    1 1
    R4U2 R4U3
    60.4 60.4
    1% 1%
    CH CH
    402 402
    2 2
    U4U1 IC
    V_MEM
    GDDR136
    14 MA_CLK1_DP MF=1 DQ31 T3 MA_DQ23 14 20 U4U1 IC
    IN MA_DQ22 BI
    DQ30 T2 14 20
    MA_DQ21 BI GDDR136
    DQ29 R3 14 20
    BI V1 VDDQ<21> MF=1
    DQ28 R2 MA_DQ20 BI 14 20 R12 VDDQ<20>
    DQ27 M3 MA_DQ19 BI 14 20 R9 VDDQ<19> VSSQ<19> T12
    DQ26 N2 MA_DQ18 BI 14 20 R4 VDDQ<18> VSSQ<18> T9
    DQ25 L3 MA_DQ17 14 20
    MA_DQ16 BI R1 VDDQ<17> VSSQ<17> T4
    DQ24 M2 14 20
    MA_WDQS2 BI N12 VDDQ<16> VSSQ<16> T1
    J11 CLK_DP WDQS3 P2 14 20
    IN N9 VDDQ<15> VSSQ<15> P12
    14 IN MA_CLK1_DN J10 CLK_DN RDQS3 P3 MA_RDQS2 OUT 20 14 V12 VDDQ<14> VSSQ<14> P9
    DM3 N3 MA_DM2 IN 14 20 N4 VDDQ<13> VSSQ<13> P4
    24 23 22 20 13 MEM_RST V9 RESET
    IN MA_DQ31 N1 VDDQ<12> VSSQ<12> P1
    27 26 25 DQ23 T10 14 20
    20 14 IN MA_A<11..0> MA_DQ30 BI J9 VDDQ<11> VSSQ<11> L11
    11 L9 A7/A11 DQ22 T11 14 20
    MA_DQ29 BI J4 VDDQ<10> VSSQ<10> L2
    10 K11 A8/A10 DQ21 R10 14 20
    BI E12 VDDQ<9> VSSQ<9> G11
    9 M4 A3/A9 DQ20 R11 MA_DQ28 BI 14 20 E9 VDDQ<8> VSSQ<8> G2
    8 K2 A10/A8 DQ19 M10 MA_DQ27 BI 14 20 E4 VDDQ<7> VSSQ<7> D12
    7 L4 A11/A7 DQ18 N11 MA_DQ26 14 20
    MA_DQ25 BI E1 VDDQ<6> VSSQ<6> D9
    6 K3 A2/A6 DQ17 L10 14 20
    MA_DQ24 BI C12 VDDQ<5> VSSQ<5> D4
    5 H2 A1/A5 DQ16 M11 14 20
    MA_WDQS3 BI C9 VDDQ<4> VSSQ<4> D1
    4 K4 A0/A4 WDQS2 P11 14 20
    IN C4 VDDQ<3> VSSQ<3> B12
    3 M9 A9/A3 RDQS2 P10 MA_RDQS3 OUT 20 14 C1 VDDQ<2> VSSQ<2> B9
    2 K10 A6/A2 DM2 N10 MA_DM3 IN 14 20 A12 VDDQ<1> VSSQ<1> B4
    1 H11 A5/A1
    MA_DQ7 A1 VDDQ<0> VSSQ<0> B1
    0 K9 A4/A0 DQ15 G10 14 20
    MA_DQ6 BI
    DQ14 F11 14 20
    20 14 IN MA_BA<2..0> MA_DQ5 BI V2 VDD<7> VSS<7> V3
    2 H3 RAS_N/BA2 DQ13 F10 14 20
    BI M12 VDD<6> VSS<6> L12
    1 G4 BA0/BA1 DQ12 E11 MA_DQ4 BI 14 20 M1 VDD<5> VSS<5> L1
    0 G9 BA1/BA0 DQ11 C10 MA_DQ3 BI 14 20 V11 VDD<4> VSS<4> G12
    DQ10 C11 MA_DQ2 14 20
    MA_CKE MA_DQ1 BI F12 VDD<3> VSS<3> G1
    20 14 H9 WE_N/CKE DQ9 B10 14 20
    IN MA_WE_N MA_DQ0 BI F1 VDD<2> VSS<2> A10
    20 14 H4 CKE/WE_N DQ8 B11 14 20
    IN BI A11 VDD<1> VSS<1> V10
    20 14 IN MA_CAS_N F9 CS_N/CAS_N WDQS1 D11 MA_WDQS0 IN 14 20 A2 VDD<0> VSS<0> A3
    20 14 IN MA_RAS_N H10 BA2/RAS_N RDQS1 D10 MA_RDQS0 OUT 20 14
    14 IN MA_CS1_N F4 CAS_N/CS_N DM1 E10 MA_DM0 IN 14 20 K12 VDDA<1> NC<1> J3
    MEM_SCAN_BOT_EN MA_DQ15 K1 VDDA<0> NC<0> J2
    27 25 23 12 A9 MF DQ7 G3 14 20
    IN MA_DQ14 BI
    DQ6 F2 14 20
    BI J12 VSSA<1>
    26 25 24 23 22 20 12 IN MEM_SCAN_EN V4 SCAN_EN DQ5 F3 MA_DQ13 BI 14 20 J1 VSSA<0>
    27 DQ4 E2 MA_DQ12 BI 14 20
    20 21 IN MEM_A_VREF0 H1 VREF1 DQ3 C3 MA_DQ11 BI 14 20
    20 MEM_A_VREF1 H12 VREF0 DQ2 C2 MA_DQ10 14 20
    IN MA_DQ9 BI X801995-006
    DQ1 B3 14 20
    MA_DQ8 BI
    DQ0 B2 14 20
    BI
    WDQS0 D2 MA_WDQS1 IN 14 20
    RDQS0 D3 MA_RDQS1 OUT 20 14
    DM0 E3 MA_DM1 14 20
    IN
    ZQ A4 MA_ZQ_BOT
    V_MEM
    1
    X801995-006 R3U1
    243
    1 1%
    R4F1 CH
    549 402
    1% 2
    V_MEM
    CH
    402
    2 MEMORY A, BOTTOM, DECOUPLING
    MEM_A_VREF0 OUT 20 21

    1 C3U2 C4U8 C4U11 C4U6 C3U1 C4U1 C4U5 C4U2


    .22UF .22UF .22UF .22UF .22UF .22UF .22UF .22UF
    R4F2 C4F2 10% 10% 10% 10% 10% 10% 10% 10%
    1.27K .1UF 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
    1% 10% X5R X5R X5R X5R X5R X5R X5R X5R
    6.3V 402 402 402 402 402 402 402 402
    CH X5R
    402 402
    2

    DRAWING
    PROJECT NAME PAGE REV
    [PAGE_TITLE=MEMORY PARITION A, BOTTOM] XENON_FABK
    Wed Aug 24 09:27:14 2005
    MICROSOFT
    XENON_RETAIL 21/73 K7
    CONFIDENTIAL
    MEMORY PARTITION B, TOP
    V_MEM CHIP SELECT = 0, MIRROR FUNCTION = 0

    1 1
    R5F3 R5F4
    60.4 60.4
    1% 1%
    CH CH
    402 402
    2 2

    U5F1 IC V_MEM
    GDDR136
    14 MB_CLK0_DP MF=0 DQ31 T3 MB_DQ31 14 23 U5F1 IC
    IN MB_DQ30 BI
    DQ30 T2 BI 14 23
    R3 MB_DQ29 GDDR136
    DQ29 BI 14 23 V1
    R2 MB_DQ28 VDDQ<21> MF=1
    DQ28 BI 14 23 R12
    M3 MB_DQ27 VDDQ<20>
    DQ27 BI 14 23 R9 T12
    N2 MB_DQ26 VDDQ<19> VSSQ<19>
    DQ26 BI 14 23 R4 T9
    L3 MB_DQ25 VDDQ<18> VSSQ<18>
    DQ25 BI 14 23 R1 T4
    M2 MB_DQ24 VDDQ<17> VSSQ<17>
    DQ24 BI 14 23 N12 T1
    J11 P2 MB_WDQS3 VDDQ<16> VSSQ<16>
    CLK_DP WDQS3 IN 14 23 N9 P12
    MB_CLK0_DN J10 P3 MB_RDQS3 VDDQ<15> VSSQ<15>
    14 IN CLK_DN RDQS3 OUT 23 14 V12 P9
    N3 MB_DM3 VDDQ<14> VSSQ<14>
    DM3 IN 14 23 N4 P4
    MEM_RST V9 VDDQ<13> VSSQ<13>
    25 24 23 21 20 13 IN RESET N1 P1
    27 26 T10 MB_DQ23 VDDQ<12> VSSQ<12>
    MB_A<11..0> DQ23 BI 14 23 J9 L11
    23 14 IN 11 L4 T11 MB_DQ22 VDDQ<11> VSSQ<11>
    A11/A7 DQ22 BI 14 23 J4 L2
    10 K2 R10 MB_DQ21 VDDQ<10> VSSQ<10>
    A10/A8 DQ21 BI 14 23 E12 G11
    9 M9 R11 MB_DQ20 VDDQ<9> VSSQ<9>
    A9/A3 DQ20 BI 14 23 E9 G2
    8 K11 M10 MB_DQ19 VDDQ<8> VSSQ<8>
    A8/A10 DQ19 BI 14 23 E4 D12
    7 L9 N11 MB_DQ18 VDDQ<7> VSSQ<7>
    A7/A11 DQ18 BI 14 23 E1 D9
    6 K10 L10 MB_DQ17 VDDQ<6> VSSQ<6>
    A6/A2 DQ17 BI 14 23 C12 D4
    5 H11 M11 MB_DQ16 VDDQ<5> VSSQ<5>
    A5/A1 DQ16 BI 14 23 C9 D1
    4 K9 P11 MB_WDQS2 VDDQ<4> VSSQ<4>
    A4/A0 WDQS2 IN 14 23 C4 B12
    3 M4 P10 MB_RDQS2 VDDQ<3> VSSQ<3>
    A3/A9 RDQS2 OUT 23 14 C1 B9
    2 K3 N10 MB_DM2 VDDQ<2> VSSQ<2>
    A2/A6 DM2 IN 14 23 A12 B4
    1 H2 VDDQ<1> VSSQ<1>
    A1/A5 A1 B1
    0 K4 G10 MB_DQ15 VDDQ<0> VSSQ<0>
    A0/A4 DQ15 BI 14 23
    DQ14 F11 MB_DQ14 14 23
    23 14 MB_BA<2..0> BI V2 VDD<7> VSS<7> V3
    IN 2 H10 BA2/RAS_N DQ13 F10 MB_DQ13 BI 14 23
    MB_DQ12 M12 VDD<6> VSS<6> L12
    1 G9 BA1/BA0 DQ12 E11 BI 14 23 M1 L1
    0 G4 C10 MB_DQ11 VDD<5> VSS<5>
    BA0/BA1 DQ11 BI 14 23 V11 G12
    C11 MB_DQ10 VDD<4> VSS<4>
    DQ10 BI 14 23 F12 G1
    MB_CKE H4 B10 MB_DQ9 VDD<3> VSS<3>
    23 14 IN CKE/WE_N DQ9 BI 14 23 F1 A10
    MB_WE_N H9 B11 MB_DQ8 VDD<2> VSS<2>
    23 14 IN WE_N/CKE DQ8 BI 14 23 A11 V10
    MB_CAS_N F4 D11 MB_WDQS1 VDD<1> VSS<1>
    23 14 IN CAS_N/CS_N WDQS1 IN 14 23 A2 A3
    MB_RAS_N H3 D10 MB_RDQS1 VDD<0> VSS<0>
    23 14 IN RAS_N/BA2 RDQS1 OUT 23 14
    14 MB_CS0_N F9 CS_N/CAS_N DM1 E10 MB_DM1 14 23
    IN IN K12 VDDA<1> NC<1> J3
    MEM_SCAN_TOP_EN A9 G3 MB_DQ7 K1 VDDA<0> NC<0> J2
    26 24 20 12 IN MF DQ7 BI 14 23
    DQ6 F2 MB_DQ6 BI 14 23
    MEM_SCAN_EN MB_DQ5 J12 VSSA<1>
    26 25 24 23 21 20 12 IN V4 SCAN_EN DQ5 F3 BI 14 23 J1
    27 E2 MB_DQ4 VSSA<0>
    DQ4 BI 14 23
    23 22 MEM_B_VREF1 H1 VREF1 DQ3 C3 MB_DQ3 14 23
    IN MEM_B_VREF0 MB_DQ2 BI
    23 IN H12 VREF0 DQ2 C2 BI 14 23
    B3 MB_DQ1 X801995-006
    DQ1 BI 14 23
    DQ0 B2 MB_DQ0 BI 14 23
    WDQS0 D2 MB_WDQS0 IN 14 23
    RDQS0 D3 MB_RDQS0 23 14
    MB_DM0 OUT
    DM0 E3 IN 14 23
    V_MEM
    ZQ A4 MB_ZQ_TOP

    1
    1 R4F5
    X801995-006
    R5U4 243
    549 1% V_MEM
    1% CH
    402 MEMORY B, TOP, DECOUPLING
    CH PARTITION B DECOUPLING
    402 2
    2 V_MEM
    MEM_B_VREF1 OUT 22 23
    C4F10 C5F5 C4F8 C4F5 C4F4 C5F2 C5F3 C5F4
    .22UF .22UF .22UF .22UF .22UF .22UF .22UF .22UF
    10% 10% 10% 10% 10% 10% 10% 10%
    1 1 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
    C5F6 X5R X5R X5R X5R X5R X5R X5R X5R
    R5U3 C5U5 10UF 402 402 402 402 402 402 402 402
    1.27K .1UF 10%
    10% 6.3V
    1% 2 X5R
    6.3V 1206
    CH X5R
    402 402
    2

    DRAWING
    PROJECT NAME PAGE REV
    [PAGE_TITLE=MEMORY PARITION B, TOP] XENON_FABK
    Wed Aug 24 09:27:14 2005
    MICROSOFT
    XENON_RETAIL 22/73 K7
    CONFIDENTIAL
    MEMORY PARTITION B, BOTTOM
    CHIP SELECT = 1, MIRROR FUNCTION = 1

    V_MEM

    1 1
    R5U2 R5U1
    60.4 60.4
    1% 1%
    CH CH
    402 402 U5U1 IC
    2 2 V_MEM
    GDDR136
    14 IN MB_CLK1_DP MF=1 DQ31 T3 MB_DQ23 BI 14 22 U5U1 IC
    DQ30 T2 MB_DQ22 14 22
    MB_DQ21 BI GDDR136
    DQ29 R3 BI 14 22
    R2 MB_DQ20 V1 VDDQ<21> MF=1
    DQ28 BI 14 22 R12
    M3 MB_DQ19 VDDQ<20>
    DQ27 BI 14 22 R9 T12
    N2 MB_DQ18 VDDQ<19> VSSQ<19>
    DQ26 BI 14 22 R4 T9
    L3 MB_DQ17 VDDQ<18> VSSQ<18>
    DQ25 BI 14 22 R1 T4
    M2 MB_DQ16 VDDQ<17> VSSQ<17>
    DQ24 BI 14 22 N12 T1
    J11 P2 MB_WDQS2 VDDQ<16> VSSQ<16>
    CLK_DP WDQS3 IN 14 22 N9 P12
    MB_CLK1_DN J10 P3 MB_RDQS2 VDDQ<15> VSSQ<15>
    14 IN CLK_DN RDQS3 OUT 22 14 V12 P9
    N3 MB_DM2 VDDQ<14> VSSQ<14>
    DM3 IN 14 22 N4 P4
    MEM_RST V9 VDDQ<13> VSSQ<13>
    24 22 21 20 13 IN RESET N1 P1
    27 26 25 T10 MB_DQ31 VDDQ<12> VSSQ<12>
    MB_A<11..0> DQ23 BI 14 22 J9 L11
    22 14 IN 11 L9 T11 MB_DQ30 VDDQ<11> VSSQ<11>
    A7/A11 DQ22 BI 14 22 J4 L2
    10 K11 R10 MB_DQ29 VDDQ<10> VSSQ<10>
    A8/A10 DQ21 BI 14 22 E12 G11
    9 M4 R11 MB_DQ28 VDDQ<9> VSSQ<9>
    A3/A9 DQ20 BI 14 22 E9 G2
    8 K2 M10 MB_DQ27 VDDQ<8> VSSQ<8>
    A10/A8 DQ19 BI 14 22 E4 D12
    7 L4 N11 MB_DQ26 VDDQ<7> VSSQ<7>
    A11/A7 DQ18 BI 14 22 E1 D9
    6 K3 L10 MB_DQ25 VDDQ<6> VSSQ<6>
    A2/A6 DQ17 BI 14 22 C12 D4
    5 H2 M11 MB_DQ24 VDDQ<5> VSSQ<5>
    A1/A5 DQ16 BI 14 22 C9 D1
    4 K4 P11 MB_WDQS3 VDDQ<4> VSSQ<4>
    A0/A4 WDQS2 IN 14 22 C4 B12
    3 M9 P10 MB_RDQS3 VDDQ<3> VSSQ<3>
    A9/A3 RDQS2 OUT 22 14 C1 B9
    2 K10 N10 MB_DM3 VDDQ<2> VSSQ<2>
    A6/A2 DM2 IN 14 22 A12 B4
    1 H11 VDDQ<1> VSSQ<1>
    A5/A1 A1 B1
    0 K9 G10 MB_DQ7 VDDQ<0> VSSQ<0>
    A4/A0 DQ15 BI 14 22
    DQ14 F11 MB_DQ6 14 22
    22 14 IN MB_BA<2..0> MB_DQ5 BI V2 VDD<7> VSS<7> V3
    2 H3 RAS_N/BA2 DQ13 F10 BI 14 22
    G4 E11 MB_DQ4 M12 VDD<6> VSS<6> L12
    1 BA0/BA1 DQ12 BI 14 22
    MB_DQ3 M1 VDD<5> VSS<5> L1
    0 G9 BA1/BA0 DQ11 C10 BI 14 22 V11 G12
    C11 MB_DQ2 VDD<4> VSS<4>
    DQ10 BI 14 22 F12 G1
    MB_CKE H9 B10 MB_DQ1 VDD<3> VSS<3>
    22 14 IN WE_N/CKE DQ9 BI 14 22 F1 A10
    MB_WE_N H4 B11 MB_DQ0 VDD<2> VSS<2>
    22 14 IN CKE/WE_N DQ8 BI 14 22 A11 V10
    MB_CAS_N F9 D11 MB_WDQS0 VDD<1> VSS<1>
    22 14 IN CS_N/CAS_N WDQS1 IN 14 22 A2 A3
    MB_RAS_N H10 D10 MB_RDQS0 VDD<0> VSS<0>
    22 14 IN BA2/RAS_N RDQS1 OUT 22 14
    14 IN MB_CS1_N F4 CAS_N/CS_N DM1 E10 MB_DM0 IN 14 22 K12 VDDA<1> NC<1> J3
    MEM_SCAN_BOT_EN MB_DQ15 K1 VDDA<0> NC<0> J2
    27 25 21 12 IN A9 MF DQ7 G3 BI 14 22
    DQ6 F2 MB_DQ14 14 22
    MEM_SCAN_EN MB_DQ13 BI J12 VSSA<1>
    26 25 24 22 21 20 12 IN V4 SCAN_EN DQ5 F3 BI 14 22
    27 E2 MB_DQ12 J1 VSSA<0>
    DQ4 BI 14 22
    22 23 IN MEM_B_VREF0 H1 VREF1 DQ3 C3 MB_DQ11 BI 14 22
    22 IN MEM_B_VREF1 H12 VREF0 DQ2 C2 MB_DQ10 BI 14 22
    B3 MB_DQ9 X801995-006
    DQ1 BI 14 22
    DQ0 B2 MB_DQ8 14 22
    MB_WDQS1 BI
    WDQS0 D2 IN 14 22
    RDQS0 D3 MB_RDQS1 OUT 22 14
    V_MEM DM0 E3 MB_DM1 IN 14 22

    ZQ A4 MB_ZQ_BOT

    1
    1 R4U1
    X801995-006
    R5F1 243
    549 1%
    1% CH
    CH 402 V_MEM
    402 2
    2
    MEM_B_VREF0 MEMORY B, BOTTOM, DECOUPLING
    OUT 22 23

    1
    C4U10 C5U4 C4U7 C4U4 C4U3 C5U1 C5U2 C5U3
    R5F2 C5F1 .22UF .22UF .22UF .22UF .22UF .22UF .22UF .22UF
    1.27K .1UF 10% 10% 10% 10% 10% 10% 10% 10%
    1% 10% 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
    6.3V X5R X5R X5R X5R X5R X5R X5R X5R
    CH X5R 402 402 402 402 402 402 402 402
    402 402
    2

    DRAWING
    PROJECT NAME PAGE REV
    [PAGE_TITLE=MEMORY PARTITION B, BOTTOM] XENON_FABK
    Wed Aug 24 09:27:15 2005
    MICROSOFT
    XENON_RETAIL 23/73 K7
    CONFIDENTIAL
    MEMORY PARTITION C, TOP
    CHIP SELECT = 0, MIRROR FUNCTION = 0
    V_MEM

    1 1
    R3D5 R3D4
    60.4 60.4
    1% 1%
    CH CH
    402 402 U3D1 IC
    2 2 V_MEM
    GDDR136
    15 IN MC_CLK0_DP MF=0 DQ31 T3 MC_DQ31 BI 15 25 U3D1 IC
    DQ30 T2 MC_DQ30 15 25
    MC_DQ29 BI GDDR136
    DQ29 R3 BI 15 25
    R2 MC_DQ28 V1 VDDQ<21> MF=0
    DQ28 BI 15 25 R12
    M3 MC_DQ27 VDDQ<20>
    DQ27 BI 15 25 R9 T12
    N2 MC_DQ26 VDDQ<19> VSSQ<19>
    DQ26 BI 15 25 R4 T9
    L3 MC_DQ25 VDDQ<18> VSSQ<18>
    DQ25 BI 15 25 R1 T4
    M2 MC_DQ24 VDDQ<17> VSSQ<17>
    DQ24 BI 15 25 N12 T1
    J11 P2 MC_WDQS3 VDDQ<16> VSSQ<16>
    CLK_DP WDQS3 IN 15 25 N9 P12
    MC_CLK0_DN J10 P3 MC_RDQS3 VDDQ<15> VSSQ<15>
    15 IN CLK_DN RDQS3 OUT 25 15 V12 P9
    N3 MC_DM3 VDDQ<14> VSSQ<14>
    DM3 IN 15 25 N4 P4
    MEM_RST V9 VDDQ<13> VSSQ<13>
    27 26 25 23 22 21 20 13 IN RESET N1 P1
    T10 MC_DQ23 VDDQ<12> VSSQ<12>
    MC_A<11..0> DQ23 BI 15 25 J9 L11
    25 15 IN 11 L4 T11 MC_DQ22 VDDQ<11> VSSQ<11>
    A11/A7 DQ22 BI 15 25 J4 L2
    10 K2 R10 MC_DQ21 VDDQ<10> VSSQ<10>
    A10/A8 DQ21 BI 15 25 E12 G11
    9 M9 R11 MC_DQ20 VDDQ<9> VSSQ<9>
    A9/A3 DQ20 BI 15 25 E9 G2
    8 K11 M10 MC_DQ19 VDDQ<8> VSSQ<8>
    A8/A10 DQ19 BI 15 25 E4 D12
    7 L9 N11 MC_DQ18 VDDQ<7> VSSQ<7>
    A7/A11 DQ18 BI 15 25 E1 D9
    6 K10 L10 MC_DQ17 VDDQ<6> VSSQ<6>
    A6/A2 DQ17 BI 15 25 C12 D4
    5 H11 M11 MC_DQ16 VDDQ<5> VSSQ<5>
    A5/A1 DQ16 BI 15 25 C9 D1
    4 K9 P11 MC_WDQS2 VDDQ<4> VSSQ<4>
    A4/A0 WDQS2 IN 15 25 C4 B12
    3 M4 P10 MC_RDQS2 VDDQ<3> VSSQ<3>
    A3/A9 RDQS2 OUT 25 15 C1 B9
    2 K3 N10 MC_DM2 VDDQ<2> VSSQ<2>
    A2/A6 DM2 IN 15 25 A12 B4
    1 H2 VDDQ<1> VSSQ<1>
    A1/A5 A1 B1
    0 K4 G10 MC_DQ15 VDDQ<0> VSSQ<0>
    A0/A4 DQ15 BI 15 25
    DQ14 F11 MC_DQ14 15 25
    25 15 IN MC_BA<2..0> MC_DQ13 BI V2 VDD<7> VSS<7> V3
    2 H10 BA2/RAS_N DQ13 F10 BI 15 25
    G9 E11 MC_DQ12 M12 VDD<6> VSS<6> L12
    1 BA1/BA0 DQ12 BI 15 25
    MC_DQ11 M1 VDD<5> VSS<5> L1
    0 G4 BA0/BA1 DQ11 C10 BI 15 25 V11 G12
    C11 MC_DQ10 VDD<4> VSS<4>
    DQ10 BI 15 25 F12 G1
    MC_CKE H4 B10 MC_DQ9 VDD<3> VSS<3>
    25 15 IN CKE/WE_N DQ9 BI 15 25 F1 A10
    MC_WE_N H9 B11 MC_DQ8 VDD<2> VSS<2>
    25 15 IN WE_N/CKE DQ8 BI 15 25 A11 V10
    MC_CAS_N F4 D11 MC_WDQS1 VDD<1> VSS<1>
    25 15 IN CAS_N/CS_N WDQS1 IN 15 25 A2 A3
    MC_RAS_N H3 D10 MC_RDQS1 VDD<0> VSS<0>
    25 15 IN RAS_N/BA2 RDQS1 OUT 25 15
    15 IN MC_CS0_N F9 CS_N/CAS_N DM1 E10 MC_DM1 IN 15 25 K12 VDDA<1> NC<1> J3
    MEM_SCAN_TOP_EN MC_DQ7 K1 VDDA<0> NC<0> J2
    26 22 20 12 IN A9 MF DQ7 G3 BI 15 25
    DQ6 F2 MC_DQ6 15 25
    MEM_SCAN_EN MC_DQ5 BI J12 VSSA<1>
    27 26 25 23 22 21 20 12 IN V4 SCAN_EN DQ5 F3 BI 15 25
    MC_DQ4 J1 VSSA<0>
    DQ4 E2 BI 15 25
    25 24 IN MEM_C_VREF1 H1 VREF1 DQ3 C3 MC_DQ3 BI 15 25
    25 IN MEM_C_VREF0 H12 VREF0 DQ2 C2 MC_DQ2 BI 15 25
    B3 MC_DQ1 X801995-006
    DQ1 BI 15 25
    DQ0 B2 MC_DQ0 15 25
    MC_WDQS0 BI
    WDQS0 D2 IN 15 25
    RDQS0 D3 MC_RDQS0 OUT 25 15
    DM0 E3 MC_DM0 IN 15 25

    ZQ A4 MC_ZQ_TOP

    V_MEM 1
    X801995-006 R3D1
    243
    1 1% V_MEM
    CH
    R2R1 402 MEMORY C, TOP, DECOUPLING
    549 2
    1% PARTITION C DECOUPLING
    CH V_MEM
    402
    2 C2E1 C3E2 C3E1 C3E3 C3E5 C3E7 C3E6 C2E3
    MEM_C_VREF1 24 25
    .22UF .22UF .22UF .22UF .22UF .22UF .22UF .22UF
    OUT 10% 10% 10% 10% 10% 10% 10% 10%
    6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
    X5R X5R X5R X5R X5R X5R X5R X5R
    1 1 1 402 402 402 402 402 402 402 402
    1 C2D3 C3C5 C2E8
    10UF 10UF 10UF
    20% 20% 20%
    R2R2 C2R9 6.3V 6.3V 6.3V
    1.27K .1UF 2 X5R 2 X5R 2 X5R
    1% 10% 805 805 805
    6.3V
    CH X5R
    402 402
    2

    DRAWING
    [PAGE_TITLE=MEMORY PARITION C, TOP] XENON_FABK
    Wed Aug 24 09:27:15 2005
    MICROSOFT PROJECT NAME
    XENON_RETAIL
    PAGE
    24/73
    REV
    K7
    CONFIDENTIAL
    MEMORY PARTITION C, BOTTOM
    CHIP SELECT = 1, MIRROR FUNCTION = 1
    V_MEM

    1 1
    R2R4 R2R3
    60.4 60.4
    1% 1%
    CH CH V_MEM
    402 402 U3R1 IC
    2 2 V_MEM
    GDDR136
    MC_CLK1_DP T3 MC_DQ23 U3R1 IC
    15 IN MF=1 DQ31 BI 15 24
    DQ30 T2 MC_DQ22 BI 15 24 1 GDDR136
    DQ29 R3 MC_DQ21 BI 15 24 C3T4 V1 VDDQ<21> MF=1
    DQ28 R2 MC_DQ20 15 24
    .1UF R12 VDDQ<20>
    MC_DQ19 BI 10%
    DQ27 M3 BI 15 24 6.3V R9 VDDQ<19> VSSQ<19> T12
    N2 MC_DQ18 2 X5R R4 T9
    DQ26 BI 15 24
    402 VDDQ<18> VSSQ<18>
    DQ25 L3 MC_DQ17 15 24 R1 VDDQ<17> VSSQ<17> T4
    BI
    DQ24 M2 MC_DQ16 BI 15 24 N12 VDDQ<16> VSSQ<16> T1
    J11 CLK_DP WDQS3 P2 MC_WDQS2 IN 15 24 N9 VDDQ<15> VSSQ<15> P12
    15 MC_CLK1_DN J10 CLK_DN RDQS3 P3 MC_RDQS2 24 15 V12 VDDQ<14> VSSQ<14> P9
    IN MC_DM2 OUT
    DM3 N3 IN 15 24 N4 VDDQ<13> VSSQ<13> P4
    27 26 24 23 22 21 20 13 MEM_RST V9 RESET N1 VDDQ<12> VSSQ<12> P1
    IN
    MC_A<11..0> DQ23 T10 MC_DQ31 BI 15 24 J9 VDDQ<11> VSSQ<11> L11
    24 15 IN 11 L9 T11 MC_DQ30 J4 L2
    A7/A11 DQ22 BI 15 24 VDDQ<10> VSSQ<10>
    10 K11 A8/A10 DQ21 R10 MC_DQ29 BI 15 24 E12 VDDQ<9> VSSQ<9> G11
    9 M4 A3/A9 DQ20 R11 MC_DQ28 15 24 E9 VDDQ<8> VSSQ<8> G2
    MC_DQ27 BI
    8 K2 A10/A8 DQ19 M10 BI 15 24 E4 VDDQ<7> VSSQ<7> D12
    7 L4 A11/A7 DQ18 N11 MC_DQ26 15 24 E1 VDDQ<6> VSSQ<6> D9
    BI
    6 K3 A2/A6 DQ17 L10 MC_DQ25 BI 15 24 C12 VDDQ<5> VSSQ<5> D4
    5 H2 A1/A5 DQ16 M11 MC_DQ24 BI 15 24 C9 VDDQ<4> VSSQ<4> D1
    4 K4 A0/A4 WDQS2 P11 MC_WDQS3 IN 15 24 C4 VDDQ<3> VSSQ<3> B12
    3 M9 A9/A3 RDQS2 P10 MC_RDQS3 24 15 C1 VDDQ<2> VSSQ<2> B9
    MC_DM3 OUT
    2 K10 A6/A2 DM2 N10 IN 15 24 A12 VDDQ<1> VSSQ<1> B4
    1 H11 A5/A1 A1 VDDQ<0> VSSQ<0> B1
    0 K9 A4/A0 DQ15 G10 MC_DQ7 BI 15 24
    MC_BA<2..0> DQ14 F11 MC_DQ6 BI 15 24 V2 VDD<7> VSS<7> V3
    24 15 IN 2 H3 F10 MC_DQ5 M12 L12
    RAS_N/BA2 DQ13 BI 15 24 VDD<6> VSS<6>
    1 G4 BA0/BA1 DQ12 E11 MC_DQ4 15 24 M1 VDD<5> VSS<5> L1
    MC_DQ3 BI
    0 G9 BA1/BA0 DQ11 C10 BI 15 24 V11 VDD<4> VSS<4> G12
    DQ10 C11 MC_DQ2 15 24 F12 VDD<3> VSS<3> G1
    BI
    24 15 IN MC_CKE H9 WE_N/CKE DQ9 B10 MC_DQ1 BI 15 24 F1 VDD<2> VSS<2> A10
    24 15 IN MC_WE_N H4 CKE/WE_N DQ8 B11 MC_DQ0 BI 15 24 A11 VDD<1> VSS<1> V10
    24 15 MC_CAS_N F9 CS_N/CAS_N WDQS1 D11 MC_WDQS0 15 24 A2 VDD<0> VSS<0> A3
    IN MC_RAS_N MC_RDQS0 IN
    24 15 IN H10 BA2/RAS_N RDQS1 D10 OUT 24 15
    15 MC_CS1_N F4 CAS_N/CS_N DM1 E10 MC_DM0 15 24 K12 VDDA<1> NC<1> J3
    IN IN
    K1 VDDA<0> NC<0> J2
    27 23 21 12 IN MEM_SCAN_BOT_EN A9 MF DQ7 G3 MC_DQ15 BI 15 24
    DQ6 F2 MC_DQ14 BI 15 24 J12 VSSA<1>
    27 26 24 23 22 21 20 12 MEM_SCAN_EN V4 SCAN_EN DQ5 F3 MC_DQ13 15 24 J1 VSSA<0>
    IN MC_DQ12 BI
    DQ4 E2 BI 15 24
    24 25 MEM_C_VREF0 H1 VREF1 DQ3 C3 MC_DQ11 15 24
    IN MEM_C_VREF1 MC_DQ10 BI
    24 IN H12 VREF0 DQ2 C2 BI 15 24 X801995-006
    DQ1 B3 MC_DQ9 BI 15 24
    DQ0 B2 MC_DQ8 BI 15 24
    WDQS0 D2 MC_WDQS1 15 24
    MC_RDQS1 IN
    RDQS0 D3 OUT 24 15
    DM0 E3 MC_DM1 15 24
    IN
    V_MEM
    ZQ A4 MC_ZQ_BOT

    1
    1 X801995-006 R3R1
    243
    R3D3 1%
    549 CH
    1% V_MEM
    402
    CH 2 MEMORY C, BOTTOM, DECOUPLING
    402
    2
    MEM_C_VREF0 24 25
    OUT
    C2T1 C3T1 C3T2 C3T3 C3T5 C3T7 C3T6 C2T3
    .22UF .22UF .22UF .22UF .22UF .22UF .22UF .22UF
    1 10% 10% 10% 10% 10% 10% 10% 10%
    6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
    R3D2 C3D3 X5R X5R X5R X5R X5R X5R X5R X5R
    1.27K .1UF 402 402 402 402 402 402 402 402
    1% 10%
    6.3V
    CH X5R
    402 402
    2

    DRAWING
    PROJECT NAME PAGE REV
    [PAGE_TITLE=MEMORY PARTITION C, BOTTOM] XENON_FABK
    Wed Aug 24 09:27:16 2005
    MICROSOFT
    XENON_RETAIL 25/73 K7
    CONFIDENTIAL
    V_MEM MEMORY PARTITION D, TOP
    CHIP SELECT = 0, MIRROR FUNCTION = 0

    1 1
    R3E5 R3E4 MD_CLK0
    60.4 60.4
    1% 1% STITCHING CAP
    CH CH V_MEM
    402 402 V_MEM
    2 2 U3E1 IC U3E1 IC
    GDDR136 GDDR136
    15 IN MD_CLK0_DP MF=0 DQ31 T3 MD_DQ31 BI 15 27 1 V1 VDDQ<21> MF=0
    DQ30 T2 MD_DQ30 BI 15 27 C3R3 R12 VDDQ<20>
    DQ29 R3 MD_DQ29 15 27
    .1UF R9 VDDQ<19> VSSQ<19> T12
    BI 10%
    DQ28 R2 MD_DQ28 15 27 6.3V R4 VDDQ<18> VSSQ<18> T9
    MD_DQ27 BI 2 X5R
    DQ27 M3 15 27 R1 VDDQ<17> VSSQ<17> T4
    MD_DQ26 BI 402
    DQ26 N2 15 27 N12 VDDQ<16> VSSQ<16> T1
    BI
    DQ25 L3 MD_DQ25 BI 15 27 N9 VDDQ<15> VSSQ<15> P12
    DQ24 M2 MD_DQ24 BI 15 27 V12 VDDQ<14> VSSQ<14> P9
    J11 CLK_DP WDQS3 P2 MD_WDQS3 IN 15 27 N4 VDDQ<13> VSSQ<13> P4
    15 MD_CLK0_DN J10 CLK_DN RDQS3 P3 MD_RDQS3 27 15 N1 VDDQ<12> VSSQ<12> P1
    IN MD_DM3 OUT
    DM3 N3 15 27 J9 VDDQ<11> VSSQ<11> L11
    MEM_RST IN
    25 24 23 22 21 20 13 V9 RESET J4 VDDQ<10> VSSQ<10> L2
    IN
    27
    MD_A<11..0> DQ23 T10 MD_DQ23 BI 15 27 E12 VDDQ<9> VSSQ<9> G11
    27 15 IN 11 L4 T11 MD_DQ22 E9 G2
    A11/A7 DQ22 BI 15 27 VDDQ<8> VSSQ<8>
    10 K2 A10/A8 DQ21 R10 MD_DQ21 15 27 E4 VDDQ<7> VSSQ<7> D12
    MD_DQ20 BI
    9 M9 A9/A3 DQ20 R11 15 27 E1 VDDQ<6> VSSQ<6> D9
    MD_DQ19 BI
    8 K11 A8/A10 DQ19 M10 15 27 C12 VDDQ<5> VSSQ<5> D4
    MD_DQ18 BI
    7 L9 A7/A11 DQ18 N11 15 27 C9 VDDQ<4> VSSQ<4> D1
    BI
    6 K10 A6/A2 DQ17 L10 MD_DQ17 BI 15 27 C4 VDDQ<3> VSSQ<3> B12
    5 H11 A5/A1 DQ16 M11 MD_DQ16 BI 15 27 C1 VDDQ<2> VSSQ<2> B9
    4 K9 A4/A0 WDQS2 P11 MD_WDQS2 15 27 A12 VDDQ<1> VSSQ<1> B4
    MD_RDQS2 IN
    3 M4 A3/A9 RDQS2 P10 27 15 A1 VDDQ<0> VSSQ<0> B1
    MD_DM2 OUT
    2 K3 A2/A6 DM2 N10 15 27
    IN
    1 H2 A1/A5 V2 VDD<7> VSS<7> V3
    0 K4 A0/A4 DQ15 G10 MD_DQ15 BI 15 27 M12 VDD<6> VSS<6> L12
    MD_BA<2..0> DQ14 F11 MD_DQ14 BI 15 27 M1 VDD<5> VSS<5> L1
    27 15 IN 2 H10 F10 MD_DQ13 V11 G12
    BA2/RAS_N DQ13 BI 15 27 VDD<4> VSS<4>
    1 G9 BA1/BA0 DQ12 E11 MD_DQ12 15 27 F12 VDD<3> VSS<3> G1
    MD_DQ11 BI
    0 G4 BA0/BA1 DQ11 C10 15 27 F1 VDD<2> VSS<2> A10
    MD_DQ10 BI
    DQ10 C11 15 27 A11 VDD<1> VSS<1> V10
    BI
    27 15 IN MD_CKE H4 CKE/WE_N DQ9 B10 MD_DQ9 BI 15 27 A2 VDD<0> VSS<0> A3
    27 15 IN MD_WE_N H9 WE_N/CKE DQ8 B11 MD_DQ8 BI 15 27
    27 15 MD_CAS_N F4 CAS_N/CS_N WDQS1 D11 MD_WDQS1 15 27 K12 VDDA<1> NC<1> J3
    IN MD_RAS_N MD_RDQS1 IN
    27 15 H3 RAS_N/BA2 RDQS1 D10 27 15 K1 VDDA<0> NC<0> J2
    IN MD_CS0_N MD_DM1 OUT
    15 F9 CS_N/CAS_N DM1 E10 15 27
    IN IN
    J12 VSSA<1>
    24 22 20 12 IN MEM_SCAN_TOP_EN A9 MF DQ7 G3 MD_DQ7 BI 15 27 J1 VSSA<0>
    DQ6 F2 MD_DQ6 BI 15 27
    27 25 24 23 22 21 20 12 MEM_SCAN_EN V4 SCAN_EN DQ5 F3 MD_DQ5 15 27
    IN MD_DQ4 BI
    DQ4 E2 15 27 X801995-006
    MEM_D_VREF1 MD_DQ3 BI
    27 26 H1 VREF1 DQ3 C3 15 27
    IN BI
    27 IN MEM_D_VREF0 H12 VREF0 DQ2 C2 MD_DQ2 BI 15 27
    DQ1 B3 MD_DQ1 BI 15 27
    DQ0 B2 MD_DQ0 BI 15 27
    WDQS0 D2 MD_WDQS0 15 27
    MD_RDQS0 IN
    RDQS0 D3 27 15
    MD_DM0 OUT
    DM0 E3 15 27
    IN
    ZQ A4 MD_ZQ_TOP

    V_MEM 1
    X801995-006 R3E1
    243
    1% V_MEM
    1
    CH
    R2T4 402 MEMORY D, TOP, DECOUPLING
    549 2 PARTITION D DECOUPLING
    1% V_MEM
    CH
    402
    2 C2D2 C2D1 C3D1 C3D2 C3D4 C3D6 C3D5 C2D4
    .22UF .22UF .22UF .22UF .22UF .22UF .22UF .22UF
    MEM_D_VREF1 OUT 26 27 10% 10% 10% 10% 10% 10% 10% 10%
    1 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
    C2E2 X5R X5R X5R X5R X5R X5R X5R X5R
    10UF 402 402 402 402 402 402 402 402
    20%
    1 6.3V
    2 X5R
    R2T3 C2T2 805
    1.27K .1UF
    1% 10%
    6.3V
    CH X5R
    402 402
    2

    DRAWING
    PROJECT NAME PAGE REV
    [PAGE_TITLE=MEMORY PARTITION D, TOP] XENON_FABK
    Wed Aug 24 09:27:16 2005
    MICROSOFT
    XENON_RETAIL 26/73 K7
    CONFIDENTIAL
    MEMORY PARTITION D, BOTTOM
    V_MEM CHIP SELECT = 1, MIRROR FUNCTION = 1

    1 1
    R2T5 R2T6
    60.4 60.4
    1% 1%
    CH CH
    402 402
    2 2
    U3T1 IC
    GDDR136 V_MEM
    15 MD_CLK1_DP MF=1 DQ31 T3 MD_DQ23 15 26 U3T1 IC
    IN BI
    DQ30 T2 MD_DQ22 BI 15 26
    R3 MD_DQ21 GDDR136
    DQ29 BI 15 26 V1
    R2 MD_DQ20 VDDQ<21> MF=1
    DQ28 BI 15 26 R12
    M3 MD_DQ19 VDDQ<20>
    DQ27 BI 15 26 R9 T12
    N2 MD_DQ18 VDDQ<19> VSSQ<19>
    DQ26 BI 15 26 R4 T9
    L3 MD_DQ17 VDDQ<18> VSSQ<18>
    DQ25 BI 15 26 R1 T4
    M2 MD_DQ16 VDDQ<17> VSSQ<17>
    DQ24 BI 15 26 N12 T1
    J11 P2 MD_WDQS2 VDDQ<16> VSSQ<16>
    CLK_DP WDQS3 IN 15 26 N9 P12
    MD_CLK1_DN J10 P3 MD_RDQS2 VDDQ<15> VSSQ<15>
    15 IN CLK_DN RDQS3 OUT 26 15 V12 P9
    N3 MD_DM2 VDDQ<14> VSSQ<14>
    DM3 IN 15 26 N4 P4
    MEM_RST V9 VDDQ<13> VSSQ<13>
    23 22 21 20 13 IN RESET N1 P1
    26 25 24 T10 MD_DQ31 VDDQ<12> VSSQ<12>
    MD_A<11..0> DQ23 BI 15 26 J9 L11
    26 15 IN 11 L9 T11 MD_DQ30 VDDQ<11> VSSQ<11>
    A7/A11 DQ22 BI 15 26 J4 L2
    10 K11 R10 MD_DQ29 VDDQ<10> VSSQ<10>
    A8/A10 DQ21 BI 15 26 E12 G11
    9 M4 R11 MD_DQ28 VDDQ<9> VSSQ<9>
    A3/A9 DQ20 BI 15 26 E9 G2
    8 K2 M10 MD_DQ27 VDDQ<8> VSSQ<8>
    A10/A8 DQ19 BI 15 26 E4 D12
    7 L4 N11 MD_DQ26 VDDQ<7> VSSQ<7>
    A11/A7 DQ18 BI 15 26 E1 D9
    6 K3 L10 MD_DQ25 VDDQ<6> VSSQ<6>
    A2/A6 DQ17 BI 15 26 C12 D4
    5 H2 M11 MD_DQ24 VDDQ<5> VSSQ<5>
    A1/A5 DQ16 BI 15 26 C9 D1
    4 K4 P11 MD_WDQS3 VDDQ<4> VSSQ<4>
    A0/A4 WDQS2 IN 15 26 C4 B12
    3 M9 P10 MD_RDQS3 VDDQ<3> VSSQ<3>
    A9/A3 RDQS2 OUT 26 15 C1 B9
    2 K10 N10 MD_DM3 VDDQ<2> VSSQ<2>
    A6/A2 DM2 IN 15 26 A12 B4
    1 H11 VDDQ<1> VSSQ<1>
    A5/A1 A1 B1
    0 K9 G10 MD_DQ7 VDDQ<0> VSSQ<0>
    A4/A0 DQ15 BI 15 26
    MD_BA<2..0> DQ14 F11 MD_DQ6 BI 15 26
    26 15 IN MD_DQ5 V2 VDD<7> VSS<7> V3
    2 H3 RAS_N/BA2 DQ13 F10 BI 15 26 M12 L12
    1 G4 E11 MD_DQ4 VDD<6> VSS<6>
    BA0/BA1 DQ12 BI 15 26 M1 L1
    0 G9 C10 MD_DQ3 VDD<5> VSS<5>
    BA1/BA0 DQ11 BI 15 26 V11 G12
    C11 MD_DQ2 VDD<4> VSS<4>
    DQ10 BI 15 26 F12 G1
    MD_CKE H9 B10 MD_DQ1 VDD<3> VSS<3>
    26 15 IN WE_N/CKE DQ9 BI 15 26 F1 A10
    MD_WE_N H4 B11 MD_DQ0 VDD<2> VSS<2>
    26 15 IN CKE/WE_N DQ8 BI 15 26 A11 V10
    MD_CAS_N F9 D11 MD_WDQS0 VDD<1> VSS<1>
    26 15 IN CS_N/CAS_N WDQS1 IN 15 26 A2 A3
    MD_RAS_N H10 D10 MD_RDQS0 VDD<0> VSS<0>
    26 15 IN BA2/RAS_N RDQS1 OUT 26 15
    15 MD_CS1_N F4 CAS_N/CS_N DM1 E10 MD_DM0 15 26
    IN IN K12 VDDA<1> NC<1> J3
    V_MEM K1 VDDA<0> NC<0> J2
    25 23 21 12 IN MEM_SCAN_BOT_EN A9 MF DQ7 G3 MD_DQ15 BI 15 26
    DQ6 F2 MD_DQ14 BI 15 26
    MEM_SCAN_EN MD_DQ13 J12 VSSA<1>
    25 24 23 22 21 20 12 IN V4 SCAN_EN DQ5 F3 BI 15 26
    26 E2 MD_DQ12 J1 VSSA<0>
    DQ4 BI 15 26
    26 27 MEM_D_VREF0 H1 VREF1 DQ3 C3 MD_DQ11 15 26 1
    IN MEM_D_VREF1 MD_DQ10 BI C2T7
    26 IN H12 VREF0 DQ2 C2 BI 15 26 10UF
    B3 MD_DQ9 10% X801995-006
    DQ1 BI 15 26
    B2 MD_DQ8 6.3V
    DQ0 BI 15 26 2 X5R
    WDQS0 D2 MD_WDQS1 15 26 1206
    MD_RDQS1 IN
    RDQS0 D3 OUT 26 15
    DM0 E3 MD_DM1 15 26
    IN
    V_MEM
    ZQ A4 MD_ZQ_BOT

    1
    1 X801995-006 R3T1
    243
    R3E3 1% V_MEM
    549 CH
    1% 402 MEMORY D, BOTTOM, DECOUPLING
    CH 2
    402
    2
    MEM_D_VREF0 26 27
    OUT V_MEM C2R7 C3R1 C3R2 C3R4 C3R7 C3R6 C2R10 C2R8
    .22UF .22UF .22UF .22UF .22UF .22UF .22UF .22UF
    10% 10% 10% 10% 10% 10% 10% 10%
    MEMORY D, BOTTOM, DECOUPLING 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
    1 X5R X5R X5R X5R X5R X5R X5R X5R
    402 402 402 402 402 402 402 402
    R3E2 C3E4
    1.27K .1UF
    1% 10%
    6.3V C2R13 C2T6 C3E8 C3F5 C3U4 C4F14 C4F15 C4U12
    CH X5R .22UF .22UF .22UF .22UF .22UF .22UF .22UF .22UF
    402 402 10% 10% 10% 10% 10% 10% 10% 10%
    2 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
    X5R X5R X5R X5R X5R X5R X5R X5R
    402 402 402 402 402 402 402 402

    DRAWING
    PROJECT NAME PAGE REV
    XENON_FABK MICROSOFT
    [PAGE_TITLE=MEMORY PARITION D, BOTTOM] Wed Aug 24 09:27:17 2005 XENON_RETAIL 27/73 K7
    CONFIDENTIAL
    V_12P0
    ANA, CLOCKS + STRAPPING
    ANA_V_12P0_DET_R

    V_3P3STBY 1 R4B9 2 1 R4B8 2 1 R4B2 2


    1% 1K 1% 75 1% 68.1 ANA_VRST_OK 1
    FTP FT4N2
    CH 402 1 CH 402 CH 402 ANA_V12P0_PWRGD OUT 34 48
    1 C4N28 SMC_RST_N
    FT2P7 FTP 470PF OUT 34 46 56
    5%
    2 50V 1
    2 EMPTY 1
    R4B3 1 R3B1 2 402 R2P3 FTP FT2N3
    U4B1 1 of 3 IC
    1K 1K 1
    5% 5% 10K ANA VERSION 95 5% FTP FT3P4
    CH 402
    CH CH
    402 ANA_V_12P0_DET 112 V_12P0_DET V_RST_OK 120 402
    1 34 ANA_RST_N 138 CORE_RST_N*<DN> V_12P0_OK 122 2
    IN 2 R2P1 1
    1 ANA_POR_BYPASS 16 POR_BYPASS<DN> SMC_RST_N* 140 SMC_RST_N_R
    FT3N1 FTP
    10K 5%
    402 CH

    46 ANA_XTAL_IN 130 XTAL_IN CPU_CLK_DP 30 ANA_CPU_CLK_DP 1


    IN 1 TP DB3C3
    131 XTAL_OUT CPU_CLK_DN 29 ANA_CPU_CLK_DN
    TP DB3C4

    132 XTAL_VSS NB_CLK_DP 27 ANA_GPU_CLK_DP 1


    TP DB3C1
    NB_CLK_DN 26 ANA_GPU_CLK_DN 1
    1 TP DB3C2
    FTP FT2P4 ANA_XTAL_BYPASS 126 XTAL_BYPASS<DN>
    PCIEX_CLK_DP 22 ANA_PCIEX_CLK_DP 1
    ANA_CLK_OE 2 R4B17 1 ANA_CLK_OE_R 21 ANA_PCIEX_CLK_DN 1 TP DB3B4
    46 34 IN PCIEX_CLK_DN
    TP DB3B3
    1K 5%
    2 402 CH SATA_CLK_DP 19 ANA_SATA_CLK_DP 1
    139 ANA_CLK_OE<DN> TP DB3B2
    SATA_CLK_DN 18 ANA_SATA_CLK_DN 1
    R4B16 TP DB3B1
    10K ANA_PLL_BYP_VID_VREF 36 VREFGEN_18S1
    5% SATA_CLK_REF 13 ANA_SATA_CLK_REF 1 DB3N3
    TP
    CH ANA_CLK_DRV_RSET 24
    402 CLK_DRV_RSET 33 ANA_PIX_CLK_2X_DP_R
    PIX_CLK_OUT_DP
    1 32 ANA_PIX_CLK_2X_DN_R
    PIX_CLK_OUT_DN
    DB3N2
    1 ENET_CLK 11 ANA_ENET_CLK 1
    TP
    R4P1 1 DB4N4
    475 STBY_CLK 136 ANA_STBY_CLK
    TP
    1% 1 R3C14 2 1 R3C20 2
    V_1P8STBY CH AUD_CLK 14 AUD_CLK_R
    402 46 56 34 SMB_DATA 8 SMB_DATA 33 5% 49.9 1%
    2 BI SMB_CLK 402 CH 402 CH
    46 56 34 9 SMB_CLK PLL_BYP_VID 35 PLL_BYP_VID
    IN ANA_PIX_CLK_2X_DP
    1 OUT 13
    AV_CLK 127 AV_CLK 1 ANA_PIX_CLK_2X_DN OUT 13
    FTP FT4N5
    R4P4
    332 1 R3C13 2 1 R3C19 2
    1% 1
    ANA_TCLK 72 TCK 33 5% 49.9 1% FTP FT4P2
    CH 1
    ANA_TDO 69 TDO 1 402 CH 402 CH FTP FT4P3
    402
    2 ANA_TDI 71 TDI R4B7
    ANA_TMS 70 TMS 10K
    5%
    1 CH
    1 X02014-005 QFP144 402
    R4P3 C4P6 2 1
    332 .1UF FTP FT2P2
    1% 10%
    2 6.3V
    CH X5R
    402 402 1 R3B15 2 AUD_CLK OUT 36
    2
    33 5%
    402 CH
    1
    FT4P1 FTP
    1
    C3B12
    V_1P8STBY V_1P8STBY 10PF
    5%
    50V
    2 EMPTY
    1 402
    1 1
    R4P5
    R5C2 R5C1 10K
    1.5K 1.5K 5%
    1% 1%
    CH
    CH CH 402
    402 J5C1 402
    2 2X3HDR 2 2
    1 2 SATA_CLK_REF STITCH
    V_3P3
    3 4 V_3P3
    5 6 ENET_CLK STITCH
    1
    EMPTY
    R5C3
    1.5K 1 1 1
    C2B17
    1% C1B4 C2B14 .1UF
    CH .1UF .1UF 10%
    10% 10% 6.3V
    402 6.3V 6.3V 2 X5R
    2 2 X5R 2 X5R 402
    402 402

    DRAWING
    PROJECT NAME PAGE REV
    XENON_FABK MICROSOFT
    [PAGE_TITLE=ANA, CLOCKS + STRAPPING Wed Aug 24 09:27:18 2005
    CONFIDENTIAL
    XENON_RETAIL 28/73 K7
    ANA, VIDEO + FAN + JTAG
    U4B1 2 OF 3 IC
    ANA VERSION 95
    13 IN GPU_PIX_CLK_1X 55 PIX_CLK_IN VID_INT 128 ANA_VID_INT OUT 33
    V_1P8STBY 13 PIX_DATA<14..0>
    IN 14 67 PIX_DATA14 DAC_A_OUT_DP 92 VID_DACA_DP 43
    VID_DACA_DN OUT
    13 66 PIX_DATA13 DAC_A_OUT_DN 91
    1 12 64 PIX_DATA12
    R4P7 11 63 PIX_DATA11 DAC_B_OUT_DP 95 VID_DACB_DP OUT 43
    332 10 61 PIX_DATA10 DAC_B_OUT_DN 94 VID_DACB_DN
    1% 9 60 PIX_DATA9
    CH 8 58 PIX_DATA8 DAC_C_OUT_DP 99 VID_DACC_DP 43
    VID_DACC_DN OUT
    402 7 57 PIX_DATA7 DAC_C_OUT_DN 100
    2 6 53 PIX_DATA6
    5 52 PIX_DATA5 DAC_D_OUT_DP 102 VID_DACD_DP OUT 43
    4 49 PIX_DATA4 DAC_D_OUT_DN 103 VID_DACD_DN
    1
    3 48 PIX_DATA3
    R4P6 1
    C4P12 2 47 PIX_DATA2
    332 .1UF 1 46 PIX_DATA1
    1% 10%
    6.3V 0 44 PIX_DATA0
    CH 2 X5R 1 1 1 1
    402 402
    2 13 IN GPU_VSYNC_OUT 42 HSYNC_IN HSYNC_OUT 115 VID_HSYNC_OUT_R OUT 43 R4B10 R4B11 R4B13 R4B14
    13 GPU_HSYNC_OUT 41 VSYNC_IN VSYNC_OUT 116 VID_VSYNC_OUT_R 43
    37.4 37.4 37.4 37.4
    IN OUT 1% 1% 1% 1%
    ANA_VID_VREF 54 CH CH CH CH
    VREFGEN_18S0 402 402 402 402
    R4B12 2 2 2 2
    2 1 ANA_DAC_RSET 97 DAC_RSET
    806 1%
    402 CH

    DB4P1 DB5P1
    CUSTOM THERMAL
    CALIBRATION PADS
    SMC_PWM1 2 R4B15 1 FAN_OP2_DP 86 88 FAN2_OUT TP TP
    LOCATION MUST
    34 IN FAN_OP2_DP FAN_OUT2 OUT 42 1 1
    205K 1% 42 FAN2_FDBK 87 FAN_OP2_DN REMAIN LOCKED
    IN
    402 CH 1 DB4P2 DB5P2
    C4N24 82 FAN_OP1_DP FAN_OUT1 84 FAN1_OUT OUT 42
    .22UF 42 FAN1_FDBK 83 FAN_OP1_DN
    TP TP
    10% IN 1 1
    6.3V
    2 X5R
    402

    1 76 TEMP_N TEMP3_P 75 CAL_TEMP_P CAL_TEMP_N OUT 29


    FTP FT4N4
    SMC_PWM0 2 R4C1 1 FAN_OP1_DP TEMP2_P 77 CPU_TEMP_P OUT 4
    34 IN BND_GAP_CAP 111 79 GPU_TEMP_P
    BND_GAP_CAP TEMP1_P OUT 13
    205K 1% TEMP0_P 80 EDRAM_TEMP_P 13
    402 CH 1 BRD_TEMP_P OUT
    C4P2 TEMP_RSET 78 TEMP_RSET TEMPCAL_P 73
    OUT 29
    .22UF
    10%
    6.3V
    2 X5R X02014-005 QFP144
    402
    1 SATA_CLK_REF STITCH
    DB4P3 C5C6
    1000PF
    TP
    10% V_3P3
    1 50V
    ST4C1 2 2 EMPTY
    CPU_TEMP_N 2 1 C4B3
    4 IN 0.01UF 402
    10%
    SHORT 16V 1 1
    1 X7R C1P13
    ST4C2 402 R4C2 .1UF V_1P8
    13 GPU_TEMP_N 2 1 11K 10%
    IN 1% 6.3V
    1 2 X5R
    SHORT FT4N1 FTP CH 402
    402
    ST4C5 2
    13 IN EDRAM_TEMP_N 2 1
    SHORT
    STBY_CLK STITCH
    ST4C4
    29 BRD_TEMP_N 2 1 V_1P8STBY V_3P3STBY V_1P8STBY
    IN
    SHORT V_3P3STBY
    Q1G3
    ST4C3 MMBT3906
    2 XSTR 1 1 1
    29 CAL_TEMP_N 2 1 C2R2 C2R1 C3N10
    IN 1 .1UF .1UF .1UF
    10% 10% 10% 1
    SHORT 6.3V 6.3V 6.3V C2P50
    3 2 X5R 2 X5R 2 X5R .1UF
    402 402 402 10%
    2 6.3V
    X5R
    V_1P8STBY 402
    3
    29 BRD_TEMP_P 1 Q1G1
    IN MMBT2222
    EMPTY
    2
    29 OUT BRD_TEMP_N

    DRAWING
    PROJECT NAME PAGE REV
    XENON_FABK MICROSOFT
    [PAGE_TITLE=ANA, VIDEO + FAN + JTAG] Wed Aug 24 09:27:19 2005
    CONFIDENTIAL
    XENON_RETAIL 29/73 K7
    V_1P8STBY
    ANA, POWER + DECOUPLING FB3B2
    1 2
    120 FB
    V_1P8STBY 1 1 0.2A 603
    C4B4 C3B3 0.5 DCR
    .22UF 10UF
    FB4N2 10% 20%
    1 2
    ANA_VDD_DAC18S V_1P8STBY 6.3V 6.3V
    OUT 30 2 X5R 2 X5R
    120 FB 402 805
    0.2A 603
    0.5 DCR
    1 1 1 1
    C4N13 C4N26 C4B6 C4B7
    10UF 2.2UF .1UF .1UF
    10% 10% 10% 10% C4N10 1
    2 6.3V 2 6.3V 2 6.3V 2 6.3V .1UF C4B5
    X5R X5R X5R X5R 10% .22UF
    1206 603 402 402 6.3V 10%
    U4B1 3 of 3 IC X5R 6.3V
    402 2 X5R
    V_1P8STBY ANA VERSION 95 402
    VAA_POR18S 113
    104 VDD_DAC18S1 AVSS_POR18S 109
    90 VDD_DAC18S0
    105 VSS_DAC18S VAA_PLL18S6 142 ANA_VAA_PLL18S1
    FB4N4 AVSS_PLL18S6 141 1
    1 2 ANA_VDD_I18S 20
    C4B9
    VDD_I18S4 .22UF
    60 FB 31 VDD_I18S3 VAA_PLL18S5 144 10%
    0.5A 603 43 143 6.3V
    1 VDD_I18S2 AVSS_PLL18S5 2 X5R
    0.1DCR C4P4 C4N21 C4P7 C4P3 C4P11 C4P9 51 VDD_I18S1 402
    10UF .1UF .1UF .1UF .1UF .1UF 65 VDD_I18S0 VAA_PLL18S4 2
    20% 10% 10% 10% 10% 10%
    6.3V 6.3V 6.3V 6.3V 6.3V 6.3V AVSS_PLL18S4 1
    2 X5R X5R X5R X5R X5R X5R 17
    805 402 402 402 402 402 VSS_I18S4
    28 VSS_I18S3 VAA_PLL18S3 4
    34 VSS_I18S2 AVSS_PLL18S3 3
    56 VSS_I18S1 1
    62 6 C3B8
    VSS_I18S0 VAA_PLL18S2 .22UF
    AVSS_PLL18S2 5 10%
    V_1P8STBY 121 6.3V
    VDD_C18S5 2 X5R
    134 VDD_C18S4 VAA_PLL18S1 38 ANA_VAA_PLL18S0 402
    10 VDD_C18S3 AVSS_PLL18S1 37
    25 VDD_C18S2
    FB4N3 45 VDD_C18S1 VAA_PLL18S0 40
    ANA_VDD_C18S
    1 2 59 VDD_C18S0 AVSS_PLL18S0 39
    60 FB V_3P3STBY
    0.5A 603 119 VSS_C18S5 VAA_XTAL33S 129 1
    0.1DCR 1 133
    C3B9
    C4N14 C4N15 C4N19 C4P8 C4P10 C4P1 C4N11 C4N7 VSS_C18S4 R4N1 .22UF
    7 85 ANA_VAA_XTAL33S 1 2 10%
    10UF 10UF .1UF .1UF .1UF .1UF .1UF .1UF VSS_C18S3 VAA_FAN33S
    10% 20% 10% 10% 10% 10% 10% 10% 23 89 2 6.3V
    VSS_C18S2 AVSS_FAN33S 100 5% X5R
    6.3V 2 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 50 402 CH 402
    X5R X5R X5R X5R X5R X5R X5R X5R VSS_C18S1
    1206 805 402 402 402 402 402 402 68 VSS_C18S0 VAA_POR33S 114
    AVSS_POR33S 110
    1 1 1
    117 VDD_I33S3 C4N22 C4N9 C4N4 V_1P8STBY
    125 VDD_I33S2<2> VAA_RTS33S 74 .1UF .1UF .1UF
    10% 10% 10%
    123 VDD_I33S2<1> AVSS_RTS33S 81 6.3V 6.3V 6.3V FB4C2
    124 2 X5R 2 X5R 2 X5R
    VDD_I33S2<0> 402 402 402 1 2
    135 VDD_I33S1 VAA_DAC33M2 96
    12 101 120 FB
    VDD_I33S0 VAA_DAC33M1 1 1 0.2A 603
    V_3P3STBY VAA_DAC33M0 106 C4C4 C4C5 0.5 DCR
    118 VSS_I33S2 .22UF 10UF
    10% 20%
    137 VSS_I33S1 AVSS_DAC33M1 93 6.3V 6.3V
    15 98 2 X5R 2 X5R
    VSS_I33S0 AVSS_DAC33M0

    ANA_VAA_RTS33S
    402 805
    NC<1> 107
    C4N5 C4N6 C4N8 C4N17 108
    .1UF .1UF .1UF .1UF NC<0>
    10% 10% 10% 10% V_3P3STBY
    6.3V 6.3V 6.3V 6.3V
    X5R X5R X5R X5R X02014-005 QFP144
    402 402 402 402 FB4P1
    1 2
    1
    C4C3
    120 FB .22UF
    30 IN ANA_VDD_DAC18S 10%
    0.2A 603 6.3V
    0.5 DCR 2 X5R
    1 1 1 402
    C4P5 C4P13 C4N23
    .1UF 2.2UF 10UF
    10% 10% 10%

    ANA_VAA_DAC33M
    2 6.3V 2 6.3V 2 6.3V
    X5R X5R X5R
    402 603 1206

    V_3P3
    FB4N1
    1 2
    60 FB
    0.5A 603
    1 1 1 1 0.1DCR 1
    C4N18 C4N16 C4N12 C4N2 C4N3
    .1UF .1UF .1UF 10UF 10UF
    10% 10% 10% 20% 10%
    2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V
    X5R X5R X5R X5R X5R
    402 402 402 805 1206

    DRAWING
    PROJECT NAME PAGE REV
    XENON_FABK MICROSOFT
    [PAGE_TITLE=ANA, POWER + DECOUPLING] Wed Aug 24 09:27:20 2005
    CONFIDENTIAL
    XENON_RETAIL 30/73 K7
    DEBUG BOARD MAPPING XDK BOARD MAPPING

    57 CPU_DBGSEL_XDK<0..69>
    IN
    IN CPU_DBGSEL_DEBUG<0..69> CPU_DBG_TERM<0..69> OUT
    0 0
    1 1 N:CONNECT TO CPU
    N:CONNECT TO CPU 2 2 DEBUG OUT
    DEBUG OUT 3 3
    4 4
    5 5
    6 6
    7 7
    8 8
    9 9
    10 10
    11 11
    12 12
    13 13
    14 14
    15 15
    16 16
    17 17 1
    18 18 FTP FT6U11
    1
    19 19 FTP FT6U9
    1
    20 20 FTP FT6U10
    21 21
    22 22
    23 23
    24 24
    25 25
    26 26
    27 27
    28 28
    29 29
    30 30
    31 31
    32 32
    33 33
    34 34
    35 35
    36 36
    37 37
    38 38
    39 39
    40 40
    41 41
    42 42
    43 43
    44 44
    45 45
    46 46
    47 47
    52 1
    48 48 DB6E1
    53 1
    49 49 DB6E2
    54 1
    50 50 DB6E3
    51 51
    52 52
    53 53
    54 54
    55 55 56 DBG_WN_POST_OUT0 1
    FTP FT6U8
    56 56 57 DBG_WN_POST_OUT1 1
    FTP FT6U2
    57 57 58 DBG_WN_POST_OUT2 1
    DBG_WN_POST_OUT3 1 FTP FT6U3
    58 58 59
    DBG_WN_POST_OUT4 1 FTP FT6U4
    59 59 60
    DBG_WN_POST_OUT5 1 FTP FT6U5
    60 60 61
    FTP FT6U6
    61 61 62 DBG_WN_POST_OUT6 1
    FTP FT6U7
    62 62 63 DBG_WN_POST_OUT7 1
    FTP FT6U1
    63 63
    64 64
    65 65
    66 66
    67 67
    68 68
    69 69

    DRAWING
    PROJECT NAME PAGE REV
    XENON_FABK MICROSOFT
    [PAGE_TITLE=DEBUG MAPPING, WN DEBUG VS WN XDK] Wed Aug 24 09:27:21 2005 XENON_RETAIL 31/73 K7
    CONFIDENTIAL
    POWER TRACE DECOUPLING
    V_12P0 V_12P0 V_5P0STBY V_5P0 V_3P3STBY V_5P0DUAL V_1P8 54 V_VREG_V1P8V5P0
    IN

    C7G2 C3N2 C7B1 C5V1 C2F2 C1C8 C9N1 C4F13


    1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2

    0.01UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10%
    16V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
    X7R X5R X5R X5R X5R X5R X5R X5R
    402 402 402 402 402 402 402 402

    C4N27 C1N12 C6B1 C3U3 C2G1 C5G1


    1 2 1 2 1 2 1 2 1 2 C8G2 C5N2 1 2
    1 2 1 2
    0.01UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10%
    16V 6.3V 6.3V 6.3V 6.3V .1UF 10% .1UF 10% 6.3V
    X7R X5R X5R X5R X5R 6.3V 6.3V X5R
    402 402 402 402 402 X5R X5R 402
    402 402

    C9F2 C1C7 C4B8 C2T4 C3G3


    1 2 1 2 1 2 1 2 1 2 C1F1 C3N1
    1 2 1 2
    0.01UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10%
    16V 6.3V 6.3V 6.3V 6.3V .1UF 10% .1UF 10%
    X7R X5R X5R X5R X5R 6.3V 6.3V
    402 402 402 402 402 X5R X5R
    402 402

    C9E2 C1D8 C5G3 C7N2


    1 2 1 2 1 2 C5G5 1 2
    1 2
    0.01UF 10% .1UF 10% .1UF 10% .1UF 10%
    16V 6.3V 6.3V .1UF 10% 6.3V
    X7R X5R X5R 6.3V X5R
    402 402 402 X5R 402
    402

    C9C7 C1B2 C1C12


    1 2 1 2 1 2

    0.01UF 10% .1UF 10% .1UF 10%


    16V 6.3V 6.3V
    X7R X5R X5R
    402 402 402

    C1C15 C1C1 C1N13


    1 2 1 2 1 2

    0.01UF 10% .1UF 10% .1UF 10%


    16V 6.3V 6.3V
    X7R X5R X5R
    402 402 402

    C7N1 C1D10 C1G1


    1 2 1 2 1 2

    0.01UF 10% .1UF 10% .1UF 10%


    16V 6.3V 6.3V
    X7R X5R X5R
    402 402 402

    C6N1 C1B3 C1F2


    1 2 1 2 1 2

    0.01UF 10% .1UF 10% .1UF 10%


    16V 6.3V 6.3V
    X7R X5R X5R
    402 402 402

    C5N1
    1 2

    0.01UF 10%
    16V
    X7R
    402

    C4N1
    1 2

    0.01UF 10%
    16V
    X7R
    402

    DRAWING
    PROJECT NAME PAGE REV
    XENON_FABK MICROSOFT
    [PAGE_TITLE=POWER TRACE EMI CAPS] Wed Aug 24 09:27:22 2005 XENON_RETAIL 32/73 K7
    CONFIDENTIAL
    ADB:ADD CONFIG TABLE SB, PCIEX + SMM GPIO + JTAG]
    U2C1 1 of 6 EMPTY
    SB VERSION 106 C2C2
    2 R2P9 1 1 2 PEX_SB_GPU_L1_DP 13
    46 IN SATA_CLK_DP K1 SATA_CLK_DP OUT
    1K 5% 46 IN SATA_CLK_DN J1 SATA_CLK_DN .1UF 10%
    V_3P3 402 EMPTY 6.3V
    SATA_CLK_REF H3 X5R
    46 IN SATA_CLK_REF 402
    SATA_CLK_SEL H4 SATA_CLK_SEL<DN>
    DB1N5
    C2C1
    1 2 PEX_SB_GPU_L1_DN 13
    TP 1 ECB_CLK_BYP A6 ECB_CLK_BYP<DN> OUT
    V_1P8 2 R2P5 1 ECB_CLK_SEL B6 ECB_CLK_SEL<DN> .1UF 10%
    1K 5% DB2P15 6.3V
    1 HBEDB_CLK_BYP U20 X5R
    402 EMPTY TP HBEDB_CLK_BYP<DN> 402
    2 R2P16 1 HBEDB_CLK_SEL V20 HBEDB_CLK_SEL<DN>
    1K 5% DB2N8
    402 EMPTY 1 XUSB_CLK_BYP B15 XUSB_CLK_BYP<DN> C2C4
    2 R2P2 1
    TP 1 2 PEX_SB_GPU_L0_DP 13
    XUSB_CLK_SEL C15 XUSB_CLK_SEL<DN> OUT
    1K 5% .1UF 10%
    402 EMPTY 6.3V
    IN PCIEX_CLK_DP
    46 L22 PEX_CLK_DP X5R
    PCIEX_CLK_DN
    46 L21 PEX_CLK_DN 402
    IN
    13 PEX_GPU_SB_L1_DP P22 PEX_RX1_DP PEX_TX1_DP N20 PEX_SB_GPU_L1_DP_C C2C3
    IN 1 2 PEX_SB_GPU_L0_DN 13
    13 IN PEX_GPU_SB_L1_DN N22 PEX_RX1_DN PEX_TX1_DN M20 PEX_SB_GPU_L1_DN_C OUT
    .1UF 10%
    13 IN PEX_GPU_SB_L0_DP T21 PEX_RX0_DP PEX_TX0_DP R19 PEX_SB_GPU_L0_DP_C 6.3V
    PEX_GPU_SB_L0_DN R21 P19 PEX_SB_GPU_L0_DN_C
    X5R
    13 IN PEX_RX0_DN PEX_TX0_DN 402
    PEX_RBIAS1 K20 PEX_RBIAS1
    PEX_RBIAS0 K19 2 R2N8 1 KER_DBG_TXD
    PEX_RBIAS0 OUT 56
    1 47 5%
    1 56 IN KER_DBG_RXD D15 UART0_RXD<UP> UART0_TXD D14 KER_DBG_TXD_R 402 CH
    R2P11 1
    C2P25 1
    .1UF 124 C2P18 R2P8
    10% 1% .1UF 499 GPIO31 D10 SB_GPIO_RESERVED31 1
    6.3V DB2P1
    2 X5R CH 10% 1% GPIO30 D11 SB_GPIO_RESERVED30 1
    6.3V SB_GPIO_RESERVED29 1 DB2P2
    402 402 2 X5R CH GPIO29 D12
    2 SB_GPIO_RESERVED28 1 DB2P3
    402 402 GPIO28 D13
    2 SB_GPIO_RESERVED27 1 DB2P4
    GPIO27 C8
    V_3P3 DB2P5
    GPIO26 D9 SB_GPIO_RESERVED26 1
    DB2P6
    GPIO25 C9 SB_GPIO_RESERVED25 1
    DB2P7
    GPIO24 B9 SB_GPIO_RESERVED24 1
    SB_GPIO_RESERVED23 1 DB2N6
    GPIO23 A9
    SB_GPIO_RESERVED22 1 DB2N5
    GPIO22 C10
    DB2N4
    GPIO21 B10 SB_GPIO_RESERVED21 1
    1 1 1 1 1 1 1 1 SB_GPIO_RESERVED20 1 DB2N3
    GPIO20 A10 DB2N11
    R1P6 R1P2 R1P3 R1P5 R1P1 R2N6 R2N4 R2N5 GPIO19 C11 SB_GPIO_RESERVED19 1
    10K 10K 10K 10K 10K 10K 10K 10K DB2N12
    GPIO18 B11 SB_GPIO_RESERVED18 1
    5% 5% 5% 5% 5% 5% 5% 5% SB_GPIO_RESERVED17 1 DB2N10
    GPIO17 A11
    CH EMPTY EMPTY EMPTY EMPTY EMPTY EMPTY EMPTY SB_GPIO_RESERVED16 1 DB2N9
    GPIO16 C12 SB_GPIO<0..15>
    402 402 402 402 402 402 402 402 DB2N7 33
    2 2 2 2 2 2 2 2 GPIO15 B12 15 BI
    GPIO14 A12 14
    0 1 2 3 5 11 14 15 SB_GPIO<0..15> GPIO13 C13 SCART_RGB OUT 43
    BI 33 B13 AUD_RST_N
    GPIO12 OUT 40
    GPIO11 A13 11
    1 1 1 1 1 1 1 1 C14 ANA_VID_INT
    GPIO10 IN 29
    R1C7 R1C4 R1C5 R1C6 R1C2 R2B10 R2B8 R2B9 GPIO9 B14 WSS_CNTL0 OUT 43 DB1P1
    1K 1K 1K 1K 1K 1K 1K 1K GPIO8 A14 WSS_CNTL1 43
    5% 5% 5% 5% 5% 5% 5% 5% OUT TP DB1P2
    GPIO7 E3 PCIEX_INT 1 TP
    EMPTY CH CH CH CH CH CH CH F1 SB_GPIO_RESERVED6 1
    402 402 402 402 402 402 402 402 GPIO6
    2 2 2 2 2 2 2 2 GPIO5 F2 5
    GPIO4 F3 ENET_RST_N 19 39
    OUT
    GPIO3 G1 3
    GPIO2 G2 2
    GPIO1 G3 1
    GPIO0 G4 0

    SB_TCLK W20 TCK<DN> 1


    FTP FT1N1
    SB_TDO V22 TDO
    SB_TDI V21 TDI<UP> SATA_CLK V_3P3 STITCH
    SB_TMS W22 TMS<UP>
    SB_TRST W21 TRST<DN> V_3P3

    J2D1
    2X3HDR X02047-012
    1 2 2 2
    3 4
    C1C2 C2B16
    .1UF .1UF
    5 6 10% 10%
    6.3V 6.3V
    1 X5R 1 X5R
    EMPTY 402 402

    DRAWING
    PROJECT NAME PAGE REV
    XENON_FABK MICROSOFT
    [PAGE_TITLE=SB, PCIEX + SMM GPIO + JTAG] Wed Aug 24 09:27:23 2005
    CONFIDENTIAL
    XENON_RETAIL 33/73 K7
    SB, SMC
    V_12P0

    46 IN STBY_CLK 2
    56 46 28 SMC_RST_N R8N17
    IN 4.7K
    5%
    1 CH
    C2P51 402
    TRAY_OPEN 2 R2N15 1 1UF 1
    47 OUT 10%
    33 5% 2 50V VREG_GPU_PWRGD
    X7R IN 52
    402 CH
    603
    U2C1 2 of 6 EMPTY 1 R8N18 2
    EXT_PWR_ON_N 2 R2M1 1 SMC_DBG_TXD
    56 43 IN SB VERSION 106 OUT 56 1.82K 1%
    10K 5% 402 CH
    402 CH Y12 STBY_CLK
    V_3P3STBY 1 C17 SMC_RST_N*
    DDC_DATA_OUT FT2P10 FTP
    35 BI
    35 BI DDC_CLK_OUT SB_RST_N N: TIED TO V_MEMPORT
    34 G20 SB_RST_N* V_5P0
    IN FOR BETTER ROUTING
    34 IN SB_MAIN_PWRGD G19 MAIN_PWR_OK
    V_3P3STBY 1 R7V4 2
    D16 B16 SMC_DBG_TXD_R 1 R2N9 2
    SMC_UART1_RXD<UP> SMC_UART1_TXD 10K 5%
    47 5% 402 CH
    56 SMC_DBG_EN C16 SMC_DBG<DN> 402 CH
    IN VREG_CPU_PWRGD
    1 1 IN 50
    R2P6 R2P4
    2.2K 2.2K TRAY_OPEN_R A18 SMC_P4_GPIO7 SMC_P2_GPIO7 E22 PWRSW_N 48
    5% 5% TRAY_STATUS VREG_3P3_EN_N OUT
    47 B18 SMC_P4_GPIO6 SMC_P2_GPIO6 E21 55
    CH CH IN OUT
    1 EXT_PWR_ON_R C18 SMC_P4_GPIO5 SMC_P2_GPIO5 E20 ANA_V12P0_PWRGD IN 28 48
    402 402
    FT2P24 FTP 1 2 2 40 OUT AUD_CLAMP D18 SMC_P4_GPIO4 SMC_P2_GPIO4 E19
    FT2P15 FTP A19 SMC_P4_GPIO3 SMC_P2_GPIO3 F22 ANA_RST_N 28 2 R3P7 1
    VREG_GPU_EN_N OUT GPU_RST_DONE IN 13
    B19 SMC_P4_GPIO2 SMC_P2_GPIO2 F21 52
    SMB_DATA PSU_V12P0_EN OUT 1K 5%
    46 56 28 C19 SMC_P4_GPIO1 SMC_P2_GPIO1 F20 48
    BI SMB_CLK ANA_CLK_OE OUT 402 CH 2
    46 28 56 A20 SMC_P4_GPIO0 SMC_P2_GPIO0 F19 28 46
    BI OUT
    R3P6
    AV_MODE2_R B20 SMC_P3_GPIO7 SMC_P1_GPIO7 Y21 VREG_CPU_EN 50
    10K
    OUT 5%
    2 R2M3 1 AV_MODE1_R B21 SMC_P3_GPIO6 SMC_P1_GPIO6 Y22
    43 IN AV_MODE2 VREG_V5P0_EN_N CH
    AV_MODE0_R C20 SMC_P3_GPIO5 SMC_P1_GPIO5 AA20 54
    10K 5% VREG_V5P0_SEL OUT 402
    C22 SMC_P3_GPIO4 SMC_P1_GPIO4 AA21 46 1
    402 CH OUT
    C21 SMC_P3_GPIO3 SMC_P1_GPIO3 AB20 VREG_V1P8_EN_N OUT 54
    D22 SMC_P3_GPIO2 SMC_P1_GPIO2 Y20 BINDSW_N IN 42
    AV_MODE1 2 R2M5 1 D21 AA19 TILTSW_N
    43 IN SMC_P3_GPIO1 SMC_P1_GPIO1 IN 42
    10K 5% D20 SMC_P3_GPIO0 SMC_P1_GPIO0 AB19 EJECTSW_N 42 47
    IN
    402 CH 1
    SMC_P0_GPIO7 J20 GPU_RST_DONE_R FTP FT2P5
    AV_MODE0 2 R2A2 1 H21 CPU_RST_N
    43 IN SMC_P0_GPIO6 OUT 4
    H19 SB_MAIN_PWRGD_R 2 R2P15 1 SB_MAIN_PWRGD
    10K 5% SMC_P0_GPIO5 OUT 34
    402 CH SMC_P0_GPIO4 H20 SB_RST_N OUT 34 1K 5%
    43 35 DDC_CLK SMC_P0_GPIO3 J19 402 CH
    IN
    SMC_P0_GPIO2 J22 2
    SMC_P0_GPIO1 J21 GPU_RST_N 13
    OUT R2P10
    56 13 BI DBG_LED3 SMC_P0_GPIO0 H22 CPU_PWRGD OUT 4 10K
    56 BI DBG_LED2 5%
    56 DBG_LED1 42 IR_DATA A16 SMC_IR_IN SMC_PWM1 A17 SMC_PWM1 29 CH
    BI IN SMC_PWM0 OUT
    SMC_PWM0 B17 29 402
    OUT 1
    2 2 2
    TP
    DB2P8 1 EN_TEST1_N G22 ENTEST1_N*<UP>
    R2B16 R2B19 R2B18
    2K 2K 2K TP 1 EN_TEST0_N G21 ENTEST0_N*<UP>
    DB2P9
    1% 1% 1%
    EMPTY EMPTY EMPTY
    402 402 402 X02047-012 V_1P8STBY
    1 1 1
    56 DBG_LED0
    BI
    1
    FT3P3 FTP 1 N: DBG_LED0 STUFFED = ICS CLOCK
    FT2R1 FTP
    1 DBG_LED0 EMPTY = ANA CLOCK 1 1
    FT2P25 FTP
    1 R2P12 R2P13
    FT1U2 FTP 10K 10K
    5% 5%
    CH CH
    402 402
    2 2

    ARGON_DATA 48
    BI
    ARGON_CLK BI 48

    DRAWING
    PROJECT NAME PAGE REV
    XENON_FABK MICROSOFT
    [PAGE_TITLE=SB, SMC] Wed Aug 24 09:27:24 2005 XENON_RETAIL 34/73 K7
    CONFIDENTIAL
    SB, FLASH + USB + SPI

    U2C1 3 of 6 EMPTY
    SB VERSION 106
    SPI_CLK U3 AB5 SPI_MISO_R 2 R1R1 1 SPI_MISO
    56 IN SPI_CLK SPI_MISO OUT 56
    56 IN SPI_MOSI Y5 SPI_MOSI 33 5%
    56 IN SPI_SS_N AA5 SPI_SS_N*<UP> 402 CH

    41 BI FLSH_DATA<7..0> FLSH_CLE
    7 Y2 FLSH_DATA7 FLSH_CLE W1 OUT 41
    6 AA2 FLSH_DATA6
    41 FLSH_WP_N 5 Y3 FLSH_DATA5 FLSH_CE_N* V3 FLSH_CE_N 41
    OUT OUT
    4 AA3 FLSH_DATA4
    V_3P3STBY 3 AB3 FLSH_DATA3 FLSH_RE_N* V2 FLSH_RE_N OUT 41
    2 Y4 FLSH_DATA2
    1 AA4 FLSH_DATA1 FLSH_WE_N* W3 FLSH_WE_N 41
    2 R1P7 1 OUT
    0 AB4 FLSH_DATA0
    2.2K 5% FLSH_ALE W2 FLSH_ALE OUT 41
    402 CH Y1 FLSH_WP_N*<DN>
    41 IN FLSH_READY V1 FLSH_READY

    1 USBPORTA3_DP W18 USBA_D3_DP USBB_D4_DP Y10 USBPORTB4_DP 1


    FT2P22 FTP 1 USBPORTA3_DN USBPORTB4_DN 1 FTP FT2P8
    Y18 USBA_D3_DN USBB_D4_DN W10
    FT2P23 FTP FTP FT2P9
    1 USBPORTA2_DP AA17 USBA_D2_DP USBB_D3_DP Y8 MEMPORT1_DP BI 45
    FT2P20 FTP
    1 USBPORTA2_DN AB17 USBA_D2_DN USBB_D3_DN W8 MEMPORT1_DN 45
    FT2P21 FTP BI
    45 GAMEPORT2_DP W16 USBA_D1_DP USBB_D2_DP AB7 EXPPORT_DP 44
    BI GAMEPORT2_DN EXPPORT_DN BI
    45 BI Y16 USBA_D1_DN USBB_D2_DN AA7 BI 44

    45 BI GAMEPORT1_DP AA15 USBA_D0_DP USBB_D1_DP AB9 MEMPORT2_DP BI 45


    45 GAMEPORT1_DN AB15 USBA_D0_DN USBB_D1_DN AA9 MEMPORT2_DN 45
    BI BI
    V_5P0STBY
    USBB_D0_DP AB11 ARGONPORT_DP 48
    BI
    W12 USB_RBIAS USBB_D0_DN AA11 ARGONPORT_DN BI 48

    X02047-012
    1 1
    SB_USB_RBIAS

    R2M7 R2M8
    2.2K 2.2K
    5% 5%
    CH CH
    402 402
    2 2
    FB2N1
    DDC_DATA_OUT 2 R2N10 1 DDC_DATA_OUT_R 1 2 DDC_DATA
    1 34 BI BI 43
    1 49.9 1% 1K FB
    C2P40 R2P14 402 CH 0.2A 603

    DIO
    BAV99
    SOT23S
    .1UF 113 1 0.7DCR

    3
    10% 1% C2N2
    6.3V 62PF
    2 EMPTY CH 5%

    D2M2
    402 402 50V
    2 2 NPO
    402 V_5P0STBY

    1
    2 R3N1 1 DDC_CLK
    BI 43 34
    0 5%
    402 EMPTY DDC_CLK_OUT_B

    DIO
    BAV99
    SOT23S
    3
    DDC_CLK_OUT 2 R2N12 1 DDC_CLK_OUT_R 2 R3N3 1 1 Q2N2
    34 BI MMBT2222
    2.2K 5% 2.2K 5% XSTR

    D2M3
    402 CH 402 CH 2
    1 2
    C3N4
    470PF DDC_CLK_OUT_E R2N11

    1
    5% 49.9
    50V
    2 X7R 1%
    402 CH
    402
    1

    DRAWING
    PROJECT NAME PAGE REV
    XENON_FABK MICROSOFT
    [PAGE_TITLE=SB, FLASH + USB + SPI] Wed Aug 24 09:27:24 2005
    CONFIDENTIAL
    XENON_RETAIL 35/73 K7
    SB, ETHERNET + AUDIO + SATA

    MII_TX_CLK R1B9 MII_TX_CLK_R


    39 19 IN
    33 5%
    402 CH
    MII_MDC_CLK_OUT_R R1C3 MII_MDC_CLK_OUT
    OUT 19 39
    U2C1 4 of 6 EMPTY
    R1B10 33 5%
    39 19 IN MII_RX_CLK MII_RX_CLK_R SB VERSION 106 402 CH
    33 5% B3 MII_TX_CLK MII_MDC_CLK_OUT E2
    402 CH C3 MII_RX_CLK
    MII_TXD3 C5 MII_TXD3 19 39
    39 19 IN MII_RXD3 D1 MII_RXD3 MII_TXD2 OUT
    MII_TXD2 A4 19 39
    39 19 MII_RXD2 D2 MII_RXD2 OUT
    IN MII_RXD1 MII_TXD1 B4 MII_TXD1 OUT 19 39
    39 19 D3 MII_RXD1
    IN MII_RXD0 MII_TXD0 C4 MII_TXD0 OUT 19 39
    39 19 C1 MII_RXD0
    IN
    MII_TXEN A3 MII_TXEN 19 39
    39 19 IN MII_RXDV C2 MII_RXDV OUT
    39 19 MII_RXER B2 MII_RXER
    IN
    39 19 MII_COL B5 MII_COL
    IN MII_CRS R2B11 I2S_MCLK
    39 19 A5 MII_CRS 40
    IN OUT
    39 19 BI MII_MDIO E1 MII_MDIO 47 5%
    R2B14 402 CH I2S_BCLK
    OUT 40
    47 5%
    28 IN AUD_CLK A8 AUD_CLK I2S_MCLK_OUT C7 I2S_MCLK_R 402 CH R2B13 I2S_SD
    B8 I2S_BCLK_R OUT 40
    I2S_BCLK_OUT
    I2S_SD A7 I2S_SD_R 47 5%
    B7 I2S_WS_R
    R2B12 402 CH I2S_WS
    I2S_WS OUT 40
    SPDIF C6 SPDIF_R
    47 5%
    402 CH 1 R2A10 2 SPDIF
    OUT 43
    47 5%
    402 CH
    47 IN HDD_RX_DP N4 SATA1_RX_DP SATA1_TX_DP R2 HDD_TX_DP OUT 47
    47 IN HDD_RX_DN P4 SATA1_RX_DN SATA1_TX_DN P2 HDD_TX_DN OUT 47

    47 ODD_RX_DP L3 SATA0_RX_DP SATA0_TX_DP N1 ODD_TX_DP 47


    IN ODD_RX_DN ODD_TX_DN OUT
    47 M3 SATA0_RX_DN SATA0_TX_DN M1 47
    IN OUT
    SATA_RBIAS U2 SATA_RBIAS

    1
    1 X02047-012
    C1C9 R1C8
    .1UF 374
    10% 1%
    2 6.3V
    X5R CH
    402 402
    2

    DRAWING
    PROJECT NAME PAGE REV
    XENON_FABK MICROSOFT
    [PAGE_TITLE=SB, ETHERNET + AUDIO + SATA] Wed Aug 24 09:27:25 2005
    CONFIDENTIAL
    XENON_RETAIL 36/73 K7
    SB, STANDBY POWER + DECOUPLING

    U2C1 5 of 6 EMPTY V_1P8STBY


    SB VERSION 106

    VDD18_AUX<9> J18
    VDD18_AUX<8> H18
    VDD18_AUX<7> G18
    V_1P8STBY VDD18_AUX<6> J15
    VDD18_AUX<5> H15
    VDD18_AUX<4> R14
    VDD18_AUX<3> H14 SB BALLS V18 AND V19 ARE IN THE
    VDD18_AUX<2> R12 LOWER RIGHT HAND OF THE CHIP
    VDD18_AUX<1> P12 THEY HAVE BEEN ISOLATED
    VDD18_AUX<0> R9 FOR BETTER POWER ROUTING

    VDD33_AUX<14> V19 V_CMPAVDD33_USB IN 37


    FB2P4 VDD33_AUX<13> D19
    1 2 V_AVDD_USB AB13 AVDD_USB VDD33_AUX<12> V18
    120 FB V_AVSS_USB AA13 AVSS_USB VDD33_AUX<11> F18 V_3P3STBY
    0.2A 603 VDD33_AUX<10> E18
    0.5 DCR 1 1
    C2R5 C2P47 C2P43 V_CMPAVDD18_USB Y13 CMPAVDD18_USB VDD33_AUX<9> E17
    10UF 2.2UF .1UF V_CMPAVSS18_USB W13 CMPAVSS18_USB VDD33_AUX<8> D17
    10% 10% 10%
    6.3V 6.3V 6.3V VDD33_AUX<7> E16
    X5R 2 X5R 2 X5R V_VDD18_USB V13 E15
    1206 603 402 VDD18_USB<9> VDD33_AUX<6>
    ST2P3 V12 W5
    1 2 VDD18_USB<8> VDD33_AUX<5>
    V11 VDD18_USB<7> VDD33_AUX<4> V5
    V10 VDD18_USB<6> VDD33_AUX<3> U5
    SHORT
    V9 VDD18_USB<5> VDD33_AUX<2> W4
    V8 VDD18_USB<4> VDD33_AUX<1> V4
    FB2P3 V7 VDD18_USB<3> VDD33_AUX<0> U4
    1 2 Y6 VDD18_USB<2>
    W6 VDD18_USB<1> VSS_USB<25> Y19
    120 FB V6 W19
    0.2A 603 VDD18_USB<0> VSS_USB<24>
    0.5 DCR 1 1 VSS_USB<23> AB18
    C2P46 C2P42 Y14 AA18
    2.2UF .1UF CMPAVDD33_USB VSS_USB<22>
    10% 10% V_CMPAVSS33_USB W14 CMPAVSS33_USB VSS_USB<21> Y17
    2 6.3V 2 6.3V W17
    X5R X5R VSS_USB<20>
    ST2P2 603 402 V_VDD33_USB V17 VDD33_USB<3> VSS_USB<19> AB16
    1 2 V16 VDD33_USB<2> VSS_USB<18> AA16
    V15 VDD33_USB<1> VSS_USB<17> Y15
    SHORT V14 VDD33_USB<0> VSS_USB<16> W15
    VSS_USB<15> AB14 V_1P8STBY
    FB2R1 VSS_USB<14> AA14
    1 2 VSS_USB<13> AB12
    120 FB VSS_USB<12> AA12
    1 0.5A 603 1 1 1 1 VSS_USB<11> Y11
    C2R3 0.2DCR C2P45 C2P41 C2P2 C2P3 VSS_USB<10> W11
    10UF 10UF .1UF .1UF .1UF 1
    10% 20% 10% 10% 10% VSS_USB<9> AB10 C2P38 C2P37 C2P23 C2P24
    6.3V 6.3V 6.3V 6.3V 6.3V VSS_USB<8> AA10 .1UF .1UF .1UF .1UF
    2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 10% 10% 10% 10%
    VSS_USB<7> Y9 6.3V 6.3V 6.3V 6.3V
    1206 805 402 402 402 W9 2 X5R X5R X5R X5R
    VSS_USB<6> 402 402 402 402
    VSS_USB<5> AB8
    VSS_USB<4> AA8
    VSS_USB<3> Y7
    VSS_USB<2> W7
    VSS_USB<1> AB6
    VSS_USB<0> AA6

    V_3P3STBY X02047-012
    37 V_CMPAVDD33_USB V_3P3STBY
    FB2P5 OUT
    1 2
    120 FB
    0.2A 603 1 1 1
    C2R6 0.5 DCR C2P48 C2P44 C2P6 C2N1 C2P5
    10UF 2.2UF .1UF .1UF .1UF .1UF
    10% 10% 10% 10% 10% 10%
    6.3V 2 6.3V 2 6.3V 2 6.3V 6.3V 6.3V
    X5R X5R X5R X5R X5R X5R
    1206 ST2P4 603 402 402 402 402
    1 2
    SHORT

    FB2P1
    1 2
    120 FB
    0.2A 603
    0.5 DCR 1 1
    C2P8 C2P34 C2P35
    10UF 2.2UF .1UF
    10% 10% 10%
    6.3V 2 6.3V 2 6.3V
    X5R X5R X5R
    1206 603 402

    DRAWING
    PROJECT NAME PAGE REV
    XENON_FABK MICROSOFT
    [PAGE_TITLE=SB, STANDBY POWER + DECOUPLING] Wed Aug 24 09:27:26 2005 XENON_RETAIL 37/73 K7
    CONFIDENTIAL
    V_1P8
    U2C1 6 of 6 EMPTY
    SB VERSION 106
    VDD18<17> U19 V_1P8
    VDD18<16> U18
    VDD18<15> R15
    VDD18<14> P15
    VDD18<13> M15
    V_SBPCIE VDD18<12> M14 1 1 1 1 1 1 1 1 1
    J12
    C2P22 C2P21 C2P16 C2P28 C2P30 C2P17 C2P15 C2P33 C2P29
    VDD18<11> .1UF .1UF .1UF .1UF .1UF .1UF .1UF .1UF .1UF
    FB2P2 VDD18<10> H12 10% 10% 10% 10% 10% 10% 10% 10% 10%
    1 2 V_AVDD_PEX L19 R11 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V
    AVDD_PEX VDD18<9> X5R X5R X5R X5R X5R X5R X5R X5R X5R
    120 FB V_AVSS_PEX L20 AVSS_PEX VDD18<8> J11 402 402 402 402 402 402 402 402 402
    1 0.2A 603 1 1 VDD18<7> H11
    C2P19 0.5 DCR C2P27 C2P26 V_VDD_PEX_FB T18 VDD_PEX<4> VDD18<6> M9
    10UF 2.2UF 0.01UF R18 VDD_PEX<3> VDD18<5> H9
    10% 10% 10%
    6.3V 6.3V 16V P18 VDD_PEX<2> VDD18<4> R8
    2 X5R 2 X5R 2 X7R N18 P8
    1206 603 402 VDD_PEX<1> VDD18<3>
    ST2P1 M18 M8
    1 2 VDD_PEX<0> VDD18<2> V_3P3
    VDD18<1> J8
    U22 VSS_PEX<15> VDD18<0> H8 V_1P8
    SHORT
    T22 VSS_PEX<14>
    R22 VSS_PEX<13> VDD33<13> E14
    R2P17 M22 E13
    VSS_PEX<12> VDD33<12>
    0 5% K22 VSS_PEX<11> VDD33<11> E12
    603 CH 1 1 1 U21 VSS_PEX<10> VDD33<10> E11 1 1 1
    C2P10 C2P32 C2P31 P21 VSS_PEX<9> VDD33<9> E10 C2P39 C2P20 C1D2
    4.7UF .1UF 0.01UF N21 VSS_PEX<8> VDD33<8> E9 1UF 1UF 10UF
    10% 10% 10% 10% 10% 10%
    6.3V 6.3V 16V M21 VSS_PEX<7> VDD33<7> D8 50V 50V 6.3V
    2 X5R 2 X5R 2 X7R K21 D7 2 X7R 2 X7R 2 X5R
    805 402 402 VSS_PEX<6> VDD33<6> 603 603 1206
    T20 VSS_PEX<5> VDD33<5> D6
    R20 VSS_PEX<4> VDD33<4> G5
    P20 VSS_PEX<3> VDD33<3> D5
    T19 VSS_PEX<2> VDD33<2> F4
    V_1P8 N19 VSS_PEX<1> VDD33<1> E4
    M19 VSS_PEX<0> VDD33<0> D4
    FB1P2
    1 2 V_AVDD1_SATA J3 AVDD1_SATA VSS<41> N15
    120 FB V_AVSS1_SATA J2 AVSS1_SATA VSS<40> L15
    0.2A 603 VSS<39> K15 V_3P3
    1 1 0.5 DCR 1 1
    C1P2 C1P7 C1P5 C1P6 V_AVDD0_SATA H1 AVDD0_SATA VSS<38> P14
    10UF 10UF 2.2UF .1UF V_AVSS0_SATA H2 AVSS0_SATA VSS<37> N14
    10% 10% 10% 10%
    6.3V 6.3V 6.3V 6.3V VSS<36> L14
    2 X5R 2 X5R 2 X5R 2 X5R V_CMPAVDD_SATA U1 K14
    1206 1206 603 402 CMPAVDD_SATA VSS<35>
    ST1P2 V_CMPAVSS_SATA T1 J14 1 1 1 1 1
    1 2 CMPAVSS_SATA VSS<34> C2P13 C2P12 C2P14 C2P11 C2P9
    VSS<33> R13 .1UF .1UF .1UF .1UF .1UF
    V_VDD_SATA T5 VDD_SATA<5> VSS<32> P13 10% 10% 10% 10% 10%
    SHORT 6.3V 6.3V 6.3V 6.3V 6.3V
    R5 VDD_SATA<4> VSS<31> N13 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R
    P5 VDD_SATA<3> VSS<30> M13 402 402 402 402 402
    FB1P1 N5 VDD_SATA<2> VSS<29> L13
    1 2 M5 VDD_SATA<1> VSS<28> K13
    L5 VDD_SATA<0> VSS<27> J13
    120 FB H13
    0.2A 603 VSS<26>
    0.5 DCR 1 1 T4 VSS_SATA<18> VSS<25> N12
    C1P3 C1P4 R4 M12
    2.2UF .1UF VSS_SATA<17> VSS<24>
    10% 10% M4 VSS_SATA<16> VSS<23> L12
    6.3V 6.3V L4 K12
    2 X5R 2 X5R VSS_SATA<15> VSS<22>
    ST1P1 603 402 K4 VSS_SATA<14> VSS<21> P11
    1 2 J4 VSS_SATA<13> VSS<20> N11 V_3P3
    T3 VSS_SATA<12> VSS<19> M11
    SHORT R3 VSS_SATA<11> VSS<18> L11
    P3 VSS_SATA<10> VSS<17> K11
    FB1P4 N3 VSS_SATA<9> VSS<16> R10
    1 2 K3 VSS_SATA<8> VSS<15> P10
    1 1
    120 FB T2 VSS_SATA<7> VSS<14> N10 C2P4 C2P1
    0.2A 603 N2 VSS_SATA<6> VSS<13> M10 1UF 10UF
    0.5 DCR 1 1 10% 10%
    C1P10 C1P11 M2 VSS_SATA<5> VSS<12> L10 50V 6.3V
    2.2UF .1UF L2 K10 2 X7R 2 X5R
    10% 10% VSS_SATA<4> VSS<11> 603 1206
    6.3V 6.3V K2 VSS_SATA<3> VSS<10> J10
    2 X5R 2 X5R R1 H10
    603 402 VSS_SATA<2> VSS<9>
    ST1P3 P1 P9
    1 2 VSS_SATA<1> VSS<8>
    L1 VSS_SATA<0> VSS<7> N9
    VSS<6> L9
    SHORT
    VSS<5> K9
    VSS<4> J9
    FB1P3 VSS<3> N8
    1 2 VSS<2> L8
    VSS<1> K8
    120 FB A15
    0.5A 603 VSS<0>
    0.2DCR 1 1 1
    C1P8 C2P52 C1P1
    10UF .1UF .1UF
    20% 10% 10%
    2 6.3V 2 6.3V 2 6.3V
    X5R X5R X5R X02047-012
    805 402 402

    DRAWING
    PROJECT NAME PAGE REV
    XENON_FABK MICROSOFT
    [PAGE_TITLE=SB, MAIN POWER + DECOUPLING] Wed Aug 24 09:27:27 2005 XENON_RETAIL 38/73 K7
    CONFIDENTIAL
    N: 123.8 OHM TERMINATION REQUIRED FOR ICS
    N: 100 OHM TERMINATION REQUIRED FOR BROADCOM

    ENET_RX_DP BI 19 44

    1
    R1A4
    44 19 39 IN V_ENET 61.9
    1%
    1 CH
    402
    R1B7 2
    1K
    5% ENET_RX_DP_R

    CH 1
    402 R1M1
    ENET_CLK 2
    19 46 IN ENET_POAC_R 0
    OUT 44
    STUFF FOR BROADCOM 5%
    U1B2 IC 1 1 EMPTY FOR ICS CH
    ICS1893BF 603
    R1B6 R1B13 2
    DB1N4 10K 330
    TP 47 REF_IN VDD<7> 48 5% 1% ENET_RX_DN_R
    1 ENET_REF_CLK_OUT 46 REF_OUT VDD<6> 45 CH EMPTY
    VDD<5> 33 402 402
    ENET_RST_N 23 14 2 2 1
    19 33 IN RESET_N* VDD<4>
    VDD<3> 7 R1A3
    36 19 MII_RX_CLK 34 RXCLK VDD<2> 24 61.9
    2 OUT ENET_ACT_N 19 44 1%
    36 19 OUT MII_RXDV 32 RXDV VDD<1> 22 OUT
    R1C1 MII_RXER 35 18 CH
    36 19 OUT RXER VDD<0> 402
    10K 2
    5% MII_RXD3 28 12
    36 19 OUT RXD<3> TP_AP
    CH MII_RXD2 29 13 ENET_RX_DN
    402 36 19 OUT RXD<2> TP_AN BI 19 44
    1 36 19 OUT MII_RXD1 30 RXD<1>
    36 19 OUT MII_RXD0 31 RXD<0> TP_BP 16 ENET_TX_DP BI 19 44
    TP_BN 15
    36 19 OUT MII_TX_CLK 37 TXCLK
    19 36 IN MII_TXEN 38 TXEN P4RD 8
    1
    P3TD 6
    19 36 IN MII_MDC_CLK_OUT R1A1
    19 36 IN MII_TXD3 42 TXD<3> P2LI 4
    19 36 MII_TXD2 41 TXD<2> P1CL 3 61.9
    IN 1%
    2 R1B11 1 19 36 IN MII_TXD1 40 TXD<1> P0AC 1 ENET_P2LI_R
    OUT 44
    44 19 39 IN V_ENET MII_TXD0 39 CH
    19 36 IN TXD<0> 402
    1.5K 1% 10/100 9 1 2
    402 CH 27

    ENET_P4RD
    ENET_P3TD
    MDC

    ENET_P1CL
    R1B4
    36 19 BI MII_MDIO 26 MDIO VSS<6> 36 10K ENET_TX_DP_R
    VSS<5> 25 5%
    36 19 OUT MII_COL 43 COL VSS<4> 21 CH
    MII_CRS 44 17 1 402
    1
    36 19 OUT CRS VSS<3>
    VSS<2> 11 2 R1M2
    R1N6 0
    ENET_AMDIX_EN 10 AMDIX_EN VSS<1> 5 10K ENET_LINK_N OUT 19 44 5%
    2 R1N4 1 VSS<0> 2 5%
    20 1 1 1 CH
    100TCSR CH 603
    100 5% 19 10TCSR 402 2
    402 EMPTY R1N7 2 R1N5 R1B5
    10K 10K 1K ENET_TX_DN_R
    5% 5% 5%
    V_ENET 2 R1N1 1 ENET_100BIAS 1
    44 19 39 IN X800188-002 CH CH CH
    9.53K 1% ENET_10BIAS DB1N3 402 402 402 R1A2
    402 CH 2 2 2
    TP
    EMPTY FOR BROADCOM 61.9
    1 ENET_10_100_OUT 1%
    2 2 STUFF FOR ICS
    CH
    R1N2 R1N3 AMDIX_EN HAS INTERNAL PULLUP 402
    1.58K 2K AUTO MDIX IS ON BY DEFAULT 2
    1% 1%
    CH CH
    402 402 10/100 PIN IS FOR OUTPUT
    1 1 INDICATION OF CONNECTION SPEED ENET_TX_DN BI 19 44

    ETHERNET ADDRESS="00001"

    V_3P3

    FB1B1
    1 2 V_ENET 19 39 44
    OUT
    60 0.1DCR
    0.5A 603
    2
    1 C1A5 C1B1 C1N1 C1N4 C1N5 C1N3 C1N9 C1N11 C1N2 C1N10
    100UF 10UF .1UF .1UF .1UF .1UF .1UF .1UF .1UF .1UF
    20% 20% 10% 10% 10% 10% 10% 10% 10% 10%
    6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
    16V 1 X5R X5R X5R X5R X5R X5R X5R X5R X5R
    2 ELEC
    RDL 805 402 402 402 402 402 402 402 402

    DRAWING
    PROJECT NAME PAGE REV
    XENON_FABK MICROSOFT
    [PAGE_TITLE=SB OUT, ETHERNET] Wed Aug 24 09:27:28 2005
    CONFIDENTIAL
    XENON_RETAIL 39/73 K7
    V_12P0
    FB2A2
    2 R2B3 1 AUD_CLAMP_R 1 2
    1 C2B10 1K 5% 1K 0.7DCR
    V_3P3 FTP FT2M1 1 2 AUD_AC_R 402 CH 0.2A 603

    R2B1 10UF 20%


    1 2 AUD_VAA 16V
    X5R
    1 0 5% 1206
    FTP FT2N1 603 CH
    2 2
    C2A7 C2B7
    1 R2B6 2 AUD_VDD 4.7UF 0.1UF R2B5
    10% 10% 10K
    0 5% 16V 25V
    603 CH X5R 1 X7R 5%
    1 1206 603 CH
    C2B11 C2B5 402
    2
    4.7UF .1UF EG2B2 1 C2B3

    1
    10% 10% PGB0010603 470PF
    6.3V 6.3V 5%
    2 X5R X5R X801161-001
    805 402 603 1 50V
    X7R
    U2B1 IC EMPTY 402
    XDAC

    2
    14 DVDD AUDIO
    36 I2S_MCLK 13 MCLK AVDD 9 AUD_R_OUT 43
    IN I2S_BCLK OUT
    36 4 BCLK
    IN I2S_SD
    36 3 SD VOUTR 6 AUD_VOUTR
    IN
    1 36 IN I2S_WS 2 WS VOUTL 10 AUD_VOUTL AUD_L_OUT OUT 43
    FT2N2 FTP
    5 NC AVREF 8 AUD_ACAP

    33 AUD_RST_N 12 PDN
    IN AUD_DCAP 11 DVREF AGND 7
    1 C2B4 C2B8

    1
    1 DGND .1UF 10UF EG2B1
    R2N3 C2B1 C2B6 10% 10%
    2
    10UF .1UF 6.3V 6.3V PGB0010603
    1K 10% 10% X5R X5R X801161-001
    5% 6.3V 6.3V 402 1206 R2B4
    X5R X5R X02238-002 603 10K
    CH 1206 402 5%
    402 EMPTY
    2 CH 2
    C2B2

    2
    402 470PF
    1 5%
    50V
    1 X7R
    402

    C2B9
    1 2 AUD_AC_L

    10UF 20% FB2A1


    16V 2 R2B2 1 AUD_CLAMP_L 1 2
    X5R
    1206 1K 5% 1K 0.7DCR
    402 CH 0.2A 603

    1
    FT2P1 FTP CR2N1
    MBT3904 3 6

    AUD_CLAMP 2 3 AUD_CLAMP_C 2 R2N2 1 AUD_CLAMP_B2


    5 2 AUD_CLAMP_B3 2 R2N1 1
    34 IN
    Q2N1 1K 5% 1K 5%
    MMBT3906 402 CH 402 CH
    XSTR 4 1 XSTR
    1
    V_3P3STBY

    1 R2M12 2 AUD_CLAMP_B1

    4.7K 5%
    402 CH 1
    R2M13
    1K
    5%
    CH
    402
    2

    DRAWING
    PROJECT NAME PAGE REV
    XENON_FABK MICROSOFT
    [PAGE_TITLE=SB OUT, AUDIO] Wed Aug 24 09:27:29 2005
    CONFIDENTIAL
    XENON_RETAIL 40/73 K7
    N: RETAIL=16MB
    FLSH_DATA0 N: XDK=64MB
    0 1
    FLSH_DATA1

    0 8MB 16MB

    1 32MB 64MB

    V_3P3STBY

    N: STUFFED AT CONFIG LEVEL


    1 1 1
    1 1 1 N: UPDATE TO RECENT PART NO#
    R2D7 R2D6 R1E2 C2E6 C2E5 C2R11
    10K 10K 10K 10UF .1UF .1UF
    1 5% 5% 5% 10% 10% 10%
    FT1R3 FTP 6.3V 6.3V 6.3V
    1 CH EMPTY CH 2 X5R 2 X5R 2 X5R
    FT1R4 FTP 1 402 402 402 1206 402 402 U2E1 IC
    FT1R5 FTP 1 2 2 2
    FT2R3 FTP 1 NAND FLASH
    FT2R4 FTP RDY 7 FLSH_READY 35
    1 OUT
    FT2R5 FTP
    1 2 R2D2 1
    FT2R6 FTP NC<27> 38 FLSH_NC38
    1
    FT2R7 FTP 37 VCC1 NC<26> 48 0 5%
    1 12 VCC0 NC<25> 47 402 EMPTY
    FTP FT1T1
    FLSH_DATA<7..0> NC<24> 46
    35 IN 7 44 45
    DATA<7> NC<23>
    6 43 DATA<6> NC<22> 40
    5 42 DATA<5> NC<21> 39
    4 41 DATA<4> NC<20> 35
    3 32 DATA<3> NC<19> 34
    2 31 DATA<2> NC<18> 33
    1 30 DATA<1> NC<17> 28
    0 29 DATA<0> NC<16> 27
    NC<15> 26
    35 IN FLSH_CE_N 9 CE_N* NC<14> 25
    35 IN FLSH_RE_N 8 RE_N* NC<13> 24
    1 1 1 1 1 1 1 1 35 FLSH_WE_N 18 WE_N* NC<12> 23
    IN FLSH_WP_N
    35 19 WP_N* NC<11> 22
    R2D8 R2D5 R2D4 R2D3 R2D1 R1D4 R1D3 R1D2 IN FLSH_ALE
    10K 10K 10K 10K 10K 10K 10K 10K 35 17 ALE NC<10> 21
    IN FLSH_CLE
    5% 5% 5% 5% 5% 5% 5% 5% 35 16 CLE NC<9> 20
    IN
    EMPTY CH CH CH CH CH CH CH NC<8> 15
    402 402 402 402 402 402 402 402 6 VSS/NC NC<7> 14
    2 2 2 2 2 2 2 2 36 11
    VSS1 NC<6>
    13 VSS0 NC<5> 10
    NC<4> 5
    NC<3> 4
    NC<2> 3
    NC<1> 2
    NC<0> 1

    X803471-003 TSOP

    DRAWING
    PROJECT NAME PAGE REV
    XENON_FABK MICROSOFT
    [PAGE_TITLE=SB OUT, FLASH] Wed Aug 24 09:27:30 2005
    CONFIDENTIAL
    XENON_RETAIL 41/73 K7
    V_3P3STBY
    V_12P0
    BINDING BUTTON

    1 FAN CONTROL 1 2 R3A8 1


    R5V3 5.11K 1%
    SWITCH 10K 402 CH
    TH 5% 3
    CH FAN1_Q1_C 1 Q3M1
    SW5G1 402 BCP51
    2 XSTR
    THR 3
    2 4
    2 R5V2 1 29 FAN1_OUT 1 Q3A1 3
    4 1 BINDSW_N_R BINDSW_N 34 IN MMBT2222
    OUT XSTR D3A1
    3 2 10K 5% 2 1N4148
    402 CH SOT23
    X02246-002 1 DIO

    FAN1_Q1_E
    2
    C4N25
    V_3P3STBY 2700PF
    10%
    50V
    1 X7R
    402 2 V_FAN1
    ODD EJECT BUTTON 1 R3A1
    R1G4 249 1
    SWITCH 10K 1% C3M1
    TH 5% CH 1UF
    10%
    CH 402 50V
    1 2

    FAN1_FDBK_R
    402 1 X7R
    SW1G1 603
    THR
    2 R3A7
    30K
    4 1 EJECTSW_N_R 2 R1G3 1 EJECTSW_N 1%
    OUT 34 47
    3 2 CH
    10K 5% 402
    402 CH 2
    2 R4P2 1
    X02246-002
    5.11K 1% FAN1_FDBK 29
    V_3P3STBY OUT
    402 CH J3A1
    1 2X2HDR
    R3A2 2 1
    1 11K 4 3
    TILT SWITCH 1%
    R2G2 CH
    SM 10K 402 HDR
    5% 2
    SW2G1 CH
    SM 402
    2
    V_12P0
    4 1
    3 2 TILTSW_N_R 2 R2G3 1 TILTSW_N
    OUT 34
    FAN CONTROL 2
    10K 5%
    X800550-001 402 CH 2 R3B16 1
    5.11K 1%
    402 CH 3
    FAN2_Q1_C 1 Q3A2 3
    BCP51
    3 XSTR D3B1
    2 4 1N4148
    TILT SWITCH FAN2_OUT 1 Q3M4 SOT23
    29 IN MMBT2222 1 DIO
    SM XSTR
    2
    SW2G2

    FAN2_Q1_E
    SM
    V_FAN2
    4 1
    3 2 2 1
    C3A7
    C4N20 2 1UF
    X800550-001 2700PF 10%
    10% R3M4 50V
    50V 1 2 X7R
    1 X7R 249 603
    402 1% R3A5
    V_3P3STBY CH 30K
    402 1%
    1 CH
    402

    FAN2_FDBK_R
    V_IR 1 R2V1 2 2
    FAN2_FDBK 29
    49.9 1% OUT
    402 CH 2
    1
    C2V1 C2V2 R2N7
    .1UF
    4.7UF 10% 10K 2 R4N8 1
    10% 6.3V 5%
    6.3V 2 X5R
    X5R 402 CH 5.11K 1%
    U1G1 IC 805 402 402 CH
    1
    IR 1
    VCC 3 R3M5
    DATA 1 IR_DATA 34
    11K
    2 OUT 1%
    GND
    5 CH
    ME2 402
    ME1 4 2

    X803473-002

    DRAWING
    PROJECT NAME PAGE REV
    XENON_FABK MICROSOFT
    [PAGE_TITLE=CONN, FAN + INFRARED + SWITCHES] Wed Aug 24 09:27:30 2005
    CONFIDENTIAL
    XENON_RETAIL 42/73 K7
    AARON: THIS PAGE HAS TOO MUCH ON IT.
    L3A3
    1 2 V_5P0
    29 VID_DACA_DP VID_DACA_OUT 43 DAC STANDARD ADVANCED SDTV HDTV SCART VGA
    IN OUT
    .27UH IND RT2M1
    1 2 V_AVIP
    SOT23S

    1 0.45A 1210
    BAV99

    NA
    3

    R3A4 A N/A Y(LUMA) Y Y G G


    DIO

    1 1 1.1A THRMSTR
    75 C3A6 C3A3 0.21DCR 1206
    1% 62PF 75PF 1
    C2M5 C2A1
    D3A4

    V_3P3 CH 5% 5% SPDIF 4.7UF 470PF B N/A C(CHROMA) PR PR R R


    402 50V 50V 36 IN 10% 5%
    2 NPO 2 NPO
    2 402 402 2 6.3V 50V
    X5R X7R
    2

    1 805 402
    C2A6 C N/A N/A PB PB B B

    SOT23S
    22PF

    BAV99

    3
    5%

    DIO
    2 50V D CVBS(COMP) CVBS(COMP) CVBS N/A CVBS CVBS
    NPO
    402

    D2A1
    L3A2
    29 VID_DACB_DP 1 2 VID_DACB_OUT 43
    IN OUT
    .27UH IND

    1
    SOT23S

    1 0.45A 1210 V_3P3


    BAV99

    NA
    3

    R3A3
    DIO

    75 1 1
    C3A5 C3A2
    1% 62PF 75PF
    D3A3

    V_3P3 CH 5% 5%
    402 50V 50V
    2 NPO 2 NPO
    2 402 402 J2A1 CONN
    2

    XENON AVIP CONNECTOR


    29 V_AVIP
    27 V_AVIP_RET

    43 IN VID_DACA_OUT 4 VID_DACA_OUT
    L3A1 2 VID_DACA_RET
    29 VID_DACC_DP 1 2 VID_DACC_OUT 43
    IN OUT V_12P0 43 VID_DACB_OUT 3 VID_DACB_OUT
    IN 1
    .27UH IND VID_DACB_RET
    SOT23S

    0.45A 1210 EXT_PWR_ON 30 EXT_PWR_ON_N 56 34 43


    OUT
    BAV99

    1 NA VID_DACC_OUT 8
    3

    43 IN VID_DACC_OUT
    DIO

    R3A6 6 VID_DACC_RET DDC_CLK 21 DDC_CLK 35 34


    75 1 1 23 DDC_DATA BI
    C3A4 C3A1 DDC_DATA BI 35
    D3A2

    1% 62PF 75PF VID_DACD_OUT 7

    R2A8 1
    5% 5% 43 IN VID_DACD_OUT

    1%
    CH
    V_3P3 CH 5 28 AV_MODE2
    402 50V 50V VID_DACD_RET AV_MODE2 OUT 34 43
    2 NPO 2 NPO 24 AV_MODE1
    2 402 402 AV_MODE1 OUT 34 43
    2

    43 IN VID_HSYNC_OUT 11 VID_HSYNC_OUT AV_MODE0 20 AV_MODE0 OUT 34 43


    9 VID_HSYNC_RET

    1.82K
    402
    GND<2> 26

    2
    43 VID_VSYNC_OUT 12 VID_VSYNC_OUT GND<1> 22
    IN
    WSS_CNTL1 1 R2A6 2 WSS_CNTL_B
    10 VID_VSYNC_RET GND<0> 18
    33 IN
    5.36K 1% CR2A1 25 SPDIF SHIELD<3> 34
    402 CH 33
    MBT3904 3 6 SHIELD<2>
    40 AUD_R_OUT 15 AUD_R_OUT SHIELD<1> 32
    IN 13 31
    5 2 AUD_R_RET SHIELD<0>
    WSS_CNTL0 1 R2A7 2
    33 IN AUD_L_OUT 16
    40 IN AUD_L_OUT MTGB<8-1>
    4.75K 1% XSTR 14 AUD_L_RET MTGA<8-1>
    402 CH 4 1
    L2A1 2 R2A5 1
    1 2 WSS_CNTL_OUT_R WSS_CNTL_OUT 17 WSS_CNTL
    29 IN VID_DACD_DP VID_DACD_OUT OUT 43 WSS_CNTL_E
    19
    1K 5% SCART_RGB
    .27UH IND 402 CH
    1
    R2A9 2

    R2A4 2
    SOT23S

    0.45A 1210

    5%
    1%
    CH

    CH
    2
    BAV99

    R2A3 NA
    3

    C2A8 X800055-001 TH

    SCART_RGB_OUT
    2
    DIO

    75 C2A5 2 75PF
    1% 62PF C2A2 5% V_3P3STBY
    75PF 50V
    D2A2

    V_3P3 CH 5% 1 NPO
    5%
    402

    402
    50V 10K
    301

    402 1 NPO 50V 402


    2 1
    1

    402 NPO
    402 1 1 1 1
    2

    R2A1 R2M6 R2M4 R2M2


    V_3P3 10K 10K 10K 10K
    5% 5% 5% 5%
    CH CH CH CH
    402 402 402 402
    2 2 2 2
    2 34 56 43 EXT_PWR_ON_N
    SCART_RGB 2 R2M11 1 Q2M1 IN AV_MODE2
    1 R3M3 2 33 SCART_RGB_R 1 34 43
    29 IN VID_VSYNC_OUT_R VID_VSYNC_OUT OUT 43 IN MMBT3906 IN AV_MODE1
    10K 5% XSTR 34 43 IN
    49.9 1% 402 CH 3 34 43 AV_MODE0
    402 CH IN
    DIO

    1 1 1 1
    BAV99
    SOT23S

    1 R2M9 2
    3

    SCART_RGB_OUT_R C2A3 C2M3 C2M2 C2M1


    470PF 470PF 470PF 470PF
    33 5% 5% 5% 5% 5%
    V_3P3STBY R3M2
    R2M10 1

    VID_HSYNC_OUT_R 1 2 VID_HSYNC_OUT 402 CH 50V 50V 50V 50V


    D3M3

    2 2 2 2
    5%
    CH

    29 IN OUT 43 1 X7R X7R X7R X7R


    49.9 1% C2M4 402 402 402 402
    402 CH 0.01UF
    10%
    2

    16V
    1

    2
    DIO
    BAV99

    X7R
    SOT23S

    10K
    402
    3

    402
    2

    LAYOUT:PLACE CLOSE TO CONNECTOR


    V_3P3STBY
    D3M2

    EMI CAPS
    2

    DRAWING PROJECT NAME PAGE REV


    MICROSOFT
    [PAGE_TITLE=[CONN, AVIP] XENON_FABK XENON_RETAIL 43/73 K7
    Wed Aug 24 09:27:31 2005 CONFIDENTIAL
    V_5P0DUAL

    RT1B1
    V_EXPPORT
    2 1 V_EXPPORT 1
    44 FTP FT1N2
    IN
    1.1A THRMSTR
    0.21DCR 1206 1 C2A4 2 2
    D1A2 C1A3 C1M2
    220UF 470PF 4.7UF
    2 20% 5% 10%
    10V 50V 6.3V
    R1B2 2 ELEC 1 X7R 1 X5R
    3 RDL 402 805
    0 5%
    603 CH 1
    NA
    SM
    BAV99
    L1B1 EMPTY SOT23S
    CMCHOKE DIO
    35 BI EXPPORT_DN 1 2 EXPPORT_DN_CM

    35 BI EXPPORT_DP 4 3 EXPPORT_DP_CM

    D1A1
    X801560-001 EG1A2
    2 EG1A1
    PGB0010603

    1
    PGB0010603
    X801161-001
    3 X801161-001
    EMPTY
    EMPTY
    R1B1 603
    1 603
    0 5%
    603 CH BAV99

    2
    SOT23S J1A1 CONN
    DIO
    XENON RJ45/USB COMBO
    12 VBUS
    13 D-
    48 IN ARGON_NTX 14 D+
    D1B1 2 15 GND
    V_EXPPORT 2 C1A4
    44 IN 470PF 16
    5% OMNI
    3 50V
    1 X7R ENET_P2LI_R 1
    402 39 IN LED_LEFT_A
    39 19 IN ENET_LINK_N 2 LED_LEFT_C
    1

    39 IN ENET_POAC_R 3 LED_RIGHT_A
    BAV99 ENET_ACT_N 4
    SOT23S 39 19 IN LED_RIGHT_C
    DIO
    39 19 IN ENET_TX_DP 11 XFMER2_P
    V_ENET 1 R1M3 2 ENET_TX_CT 10
    19 39 IN XFMER2_C
    0 5% 39 19 IN ENET_TX_DN 7 XFMER2_N
    402 EMPTY
    39 19 IN ENET_RX_DP 9 XFMER1_P
    1 R1A5 2 ENET_RX_CT 6 XFMER1_C
    0 5% 39 19 IN ENET_RX_DN 5 XFMER1_N
    402 EMPTY
    8 CAP
    C1M1 C1A2
    .1UF .1UF 20 EMI4
    10% 10%
    6.3V 6.3V 19 EMI3
    X5R X5R 18 EMI2
    402 402 17 EMI1

    21 ME1

    X806148-001

    DRAWING
    PROJECT NAME PAGE REV
    XENON_FABK MICROSOFT
    [PAGE_TITLE=CONN, ETHERNET] Wed Aug 24 09:27:32 2005
    CONFIDENTIAL
    XENON_RETAIL 44/73 K7
    V_MEMPORT1
    OUT
    V_MPORT
    V_5P0DUAL
    RT2G1 FB5G1
    RT8G1 2 1 2 1 V_MEMPORT2
    2 1 V_GAMEPORT2 120 FB
    1.1A THRMSTR 0.5A 603
    1.1A THRMSTR 0.21DCR 1206 0.2DCR 1 C5G4 1 2
    2 2 C4V6 C5G6
    0.21DCR 1206 1 C9G2 220UF 470PF 4.7UF
    C8V14 C9G1 20% 5% 10%
    4.7UF 220UF 470PF 10V
    10% 20% 5% 2 50V 1 6.3V
    10V 2 ELEC X7R X5R
    1 6.3V 1 50V RDL 402 805
    X5R 2 ELEC X7R
    805 RDL 402

    1
    EG9G2 R4G5
    PGB0010603
    X801161-001 0 5%
    603 CH
    603
    V_5P0DUAL NA
    EMPTY
    SM
    L4G1 EMPTY

    2
    D9G2
    2 MEMPORT2_DN 1 CMCHOKE 2 MEMPORT2_DN_CM
    35 BI
    1 R9G2 2
    0 5% 3
    603 CH MEMPORT2_DP 4 3 MEMPORT2_DP_CM
    1 35 BI
    NA
    SM X801560-001

    1
    BAV99 EG4G2 EG4G1
    L9G1 EMPTY SOT23S PGB0010603 PGB0010603 J3G1 CONN
    DIO

    1
    GAMEPORT2_DN 4 CMCHOKE 3 EG9G1 X801161-001 X801161-001
    35 BI XENON MU
    PGB0010603 603 603
    X801161-001 DIO DIO 1 GND
    R4G4 2
    603 VBUS
    GAMEPORT2_DP 1 2 3

    2
    35 BI EMPTY 0 5% D-
    TH 603 CH 4 D+
    5

    2
    X801560-001 D9G1 J9G1 CONN GND
    2 XENON GAME 6 GND
    CONN 7
    3 VBUS
    1 VBUS 8 D-
    1 R9G1 2 GAMEPORT2_DN_CM 2 D- 2 2 9 D+
    1 1 C2G2
    GAMEPORT2_DP_CM 3 D+ C3V5 C2G3 10 GND
    0 5% 4 220UF 470PF 4.7UF
    603 CH GND 20% 5% 10%
    BAV99 10V 14
    50V 6.3V EMI4
    SOT23S
    5 2 ELEC 1 X7R 1 X5R 13
    DIO VBUS RDL 402 805 EMI3
    GAMEPORT1_DN_CM 6 D- R3G4 12 EMI2
    GAMEPORT1_DP_CM 7 D+ 11 EMI1
    V_5P0DUAL 8 GND 0 5%
    603 CH 15 ME4
    RT8G2 9 NA 16 ME3
    EMI1
    2 1 V_GAMEPORT1 10 SM 17 ME2
    EMI2
    L2G1 EMPTY 18 ME1
    1.1A THRMSTR 11
    0.21DCR 1206 2 ME1 MEMPORT1_DN 1 CMCHOKE 2 MEMPORT1_DN_CM
    2 1 C9G3 C9G4 12 ME2
    35 BI MTGA<8-1>
    C9V3 220UF 470PF
    4.7UF 20% 5% MTGB<8-1>
    10% 10V 50V MTGC<8-1>
    1 6.3V 2 ELEC 1 X7R MEMPORT1_DP 4 3 MEMPORT1_DP_CM
    X5R RDL 402 X800245-003 35 BI
    805
    X800059-001 TH
    X801560-001

    1
    EG3G1 EG2G1
    V_5P0DUAL PGB0010603 PGB0010603
    R2G5 X801161-001 X801161-001
    D9V2 603 603
    2 0 5% DIO DIO
    R9V2 603 CH
    1

    EG9V2

    2
    0 5% 3 PGB0010603
    603 CH X801161-001
    1 603
    NA
    EMPTY
    SM
    BAV99 V_MPORT
    L9V1 EMPTY V_5P0
    2

    SOT23S
    DIO U1F2 IC
    GAMEPORT1_DN 4 CMCHOKE 3
    35 BI NCP1117
    1

    EG9V1 3 2 1
    IN OUT FTP FT1V1
    PGB0010603
    GAMEPORT1_DP 1 2 X801161-001 1
    35 BI ADJUST/GND
    603 1
    D9V1 EMPTY 1 C1F6 1 C1F4
    X801560-001 C1U2 0.1UF 100UF
    2 1.0UF X800499-001 10% 20%
    2

    10% 25V 16V


    16V 2
    3 2 X7R
    X7R
    603 2 ELEC
    RDL
    805
    1
    R9V1
    0 5% BAV99
    603 CH SOT23S
    DIO

    DRAWING
    PROJECT NAME PAGE REV
    XENON_FABK MICROSOFT
    [PAGE_TITLE=CONN, MEMORY PORTS + GAME PORTS] Wed Aug 24 09:27:33 2005
    CONFIDENTIAL
    XENON_RETAIL 45/73 K7
    V_5P0DUAL V_3P3STBY
    FB3P2
    1 2
    60 0.1DCR
    V_3P3STBY V_3P3 0.5A 603
    1 1 1 EMPTY N: ONE CAP PER POWER PIN
    R1G2 R1G1 R1V2 FB3P1 STBY_CLK STITCH
    1K 20 20 1 2 V_CLKGEN
    5% 1% 1% ANA_XTAL_BACKUP 2 R3B5 1 ANA_XTAL_IN
    60 0.1DCR OUT 28
    CH CH CH 0.5A 603
    402 1206 1206 33 5%
    2 2 2 2 2 2 2 2 2 1 402 CH
    2 2 C3P6 C3P4 C3P8 C3P2 C3P1 C3P7 C3P5
    C3N9 C3N8 4.7UF .1UF .1UF .1UF .1UF .1UF .1UF
    .1UF .1UF 10% 10% 10% 10% 10% 10% 10%
    10% 10% 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
    6.3V 6.3V 1 X5R 1 X5R 1 X5R 1 X5R 1 X5R 1 X5R 2 X5R

    BLEEDER_C1

    BLEEDER_C2
    1 X5R 1 X5R 805 402 402 402 402 402 402
    R3C12 1 R3C18 2
    402 402
    33 5% 49.9 1%
    402 CH 402 CH
    CPU_CLK_DP 4
    3 V_1P8STBY CPU_CLK_DN OUT
    OUT 4
    1 Q1G2
    MMBT2222 V_3P3STBY R3C11 1 R3C17 2
    XSTR
    2 ANA_BCKUP_X1
    33 5% 49.9 1%
    ANA_BCKUP_X2
    402 CH 402 CH
    3 1 R3B4 2
    56
    SMC_RST_N 2 R1V1 1 BLEEDER_B 1 Q1V1
    28 IN MMBT2222 1M 5%
    34 402 CH R3C8 1 R3C16 2
    10K 5% XSTR
    402 CH 2
    NOTE: SWAP POLARITY 33 5% 49.9 1%
    Y3B1 FOR ROUTING 402 CH 402 CH
    27MHZ
    1 2 GPU_CLK_DP OUT 13
    U3B4 IC GPU_CLK_DN OUT 13
    SM BACKUP CLK GEN
    XTAL R3C7 1 R3C15 2
    V_1P8STBY
    2 2 22 VCC3_5 X1_BCKUP 28 33 5% 49.9 1%
    C3B13 C3B14 23
    22PF 22PF VCC3_4 402 CH 402 CH
    5% 5% 17 VCC3_3 CPU_CLK_DP_R 15 CPU_CLK_DP_R
    50V 50V 5 16
    1 NPO 1 NPO VCC3_2 CPU_CLK_DN_R CPU_CLK_DN_R

    2 402 402 1 VCC3_1


    C3N3 18 R3C10 1 R3C9 2
    .1UF GPU_CLK_DP_R GPU_CLK_DP_R

    10% V_3P3STBY 2 BCKUP_X1 GPU_CLK_DN_R 19 GPU_CLK_DN_R


    33 5% 49.9 1%
    1 6.3V 3 402 CH 402 CH
    X5R BCKUP_X2
    402 PCIEX_CLK_DP_R 14 PCIEX_CLK_DP_R
    PCIEX_CLK_DP
    ANA_CLK_OE 2 R3P3 1 ANA_BCKUP_OE 8 13 OUT 33
    28 34 IN BCKUP_OE PCIEX_CLK_DN_R PCIEX_CLK_DN_R
    PCIEX_CLK_DN
    OUT 33
    1K 5%
    402 CH 28 56 34 SMB_CLK 27 SMB_CLK SATA_CLK_DP_R 11 SATA_CLK_DP_R
    1 R3C6 2 1 R3C5 2
    IN SMB_DATA 26 10 1
    56 34 28 SMB_DATA SATA_CLK_DN_R SATA_CLK_DN_R FTP FT3P2
    IN 33 5% 49.9 1% 1
    FTP FT3P1
    ANA_BCKUP_RSET 20 6 402 CH 402 CH
    BCKUP_RSET BCKUP_F25MA
    BCKUP_F25MB 7
    21 GND_5
    25 GND_4 BCKUP_F48M 24 1 R3C4 2 1 R3C3 2
    12 GND_3
    9 GND_2 33 5% 49.9 1%
    2 4 402 CH 402 CH
    GND_1
    R3P2 SATA_CLK_DP 33
    475 SATA_CLK_DN OUT
    OUT 33
    1% X803897-001 TSSOP28
    CH 1 R3C2 2 1 R3C1 2
    402 1
    1 33 5% 49.9 1% 1 FTP FT1P2
    402 CH 402 CH FTP FT1P1
    V_5P0STBY

    ANA_BCKUP_F25MA 1 R3B8 2 ENET_CLK OUT 19 39


    V_5P0STBY V_12P0 33 5%
    1 C1D11 402 CH 1
    220UF V_5P0DUAL C3B4
    20% 10PF
    10V 5%
    1 1 ELEC 50V
    2 RDL 2 EMPTY
    R1R2 R1R3 402
    10K 10K
    5% 5%
    U1R1 IC
    CH CH
    402 402 ANA_BCKUP_F25MB 1 R3C27 2 SATA_CLK_REF
    SI4501DY OUT 33
    2 2 3
    R1R5 S2 33 5%
    2 1 VREG_V5P0_SEL_PGATE 4 402 CH 1
    G2 1 FTP FT2N4
    10K 5% VREG_V5P0_SEL_NGATE
    5 1 C3C3
    402 CH D<3> FTP FT1R2 10PF
    VREG_V5P0_SEL_C
    V_5P0 D<2> 8 5%
    7 50V
    CR1D1 2 D<1> 2 EMPTY
    MBT3904 C1R3 D<0> 6 402
    .1UF
    10% 2 G1
    VREG_V5P0_SEL 1 R1D6 2 6.3V 1
    34 IN
    VREG_V5P0_SEL_B1 VREG_V5P0_SEL_B2 1 X5R S1
    402 ANA_BCKUP_F48M 1 R3B7 2 STBY_CLK
    4.7K 5% OUT 34
    1 402 CH 2 33 5%
    FT1R1 FTP XSTR X801132-001
    R1D5 402 CH 1 1
    C3C4 FTP FT2R2
    4.7K 10PF
    5% 5%
    50V
    CH VREG_5P0_SEL 2 EMPTY
    402 VREG_5P0_SEL NGATE/PGATE V_5P0DUAL 402
    1
    HIGH LOW V_5P0STBY
    LOW HIGH V_5P0 DRAWING
    PROJECT NAME PAGE REV
    XENON_FABK MICROSOFT
    [PAGE_TITLE=[BACKUP CLOCK + V_5P0 DUAL] Wed Aug 24 09:27:34 2005
    CONFIDENTIAL
    XENON_RETAIL 46/73 K7
    V_5P0
    D1E4
    2

    3
    C1E4
    36 IN HDD_TX_DP 1 2
    1
    0.01UF 10%
    16V BAV99
    X7R SOT23S
    402
    DIO
    HDD_TX_DP_C HDD SATA AND POWER
    HDD_TX_DN_C

    D1E3
    C1E3 J1E1 CONN
    36 IN HDD_TX_DN 1 2 2
    XENON HDD
    0.01UF 10% 3 1 CONN
    16V GND
    X7R 2 D+
    402 1 3 D-
    4 GND
    BAV99 5 D-
    SOT23S 6 D+
    DIO 7 GND

    V_5P0 8 GND
    9 GND
    D1E2 10 GND
    11 V_HDD
    2 12

    1
    V_HDD
    EG1E4 EG1E3 EG1E2 EG1E1 13
    3 V_HDD
    X801161-001 PGB0010603 PGB0010603 PGB0010603 14
    C1E2 V_XPOD
    HDD_RX_DN 1 2 PGB0010603 X801161-001 X801161-001 X801161-001
    36 OUT 1 603 603 603 603 15 EMI1
    0.01UF 10% EMPTY EMPTY EMPTY EMPTY 16
    16V EMI2
    BAV99

    2
    X7R
    402 SOT23S 17
    DIO ME1
    HDD_RX_DN_C 18 ME2

    HDD_RX_DP_C MTGA<8-1>
    MTGB<8-1>
    D1E1 V_5P0
    C1E1 RT1U1
    36 HDD_RX_DP 1 2 2 X800351-002 TH
    OUT 2 1 V_HDD
    0.01UF 10% 3
    16V 1.5A THRMSTR
    X7R 1 C1E5 1 1
    402 1 0.11DCR 1812 C1T5 C1T4 C1T3
    100UF 1UF 1UF 470PF
    20% 10% 10% 5%
    16V 50V 50V 50V
    BAV99
    2 ELEC 2 X7R 2 X7R X7R
    SOT23S RDL 603 603 402
    DIO

    V_5P0DUAL
    RT1R1
    ODD SATA 2 1 V_XPOD
    V_3P3
    V_3P3
    ODD_TX_DP 1
    C1C6
    2 ODD_TX_DP_C
    ODD POWER DECOUPLING 1.1A
    0.21DCR
    THRMSTR
    1206
    1
    C1T1 C1T2
    36 IN 1UF 470PF
    0.01UF 10%
    10%
    50V
    5%
    50V
    ODD POWER AND CONTROL
    16V V_12P0 V_3P3 2 X7R X7R
    X7R 603 402
    402 CR1D2
    CR1D3
    2
    C1C5 J1C1 2
    36 IN ODD_TX_DN 1 2 ODD_TX_DN_C SATA 1 C1C10 1 1 C1C11 1
    C1C14 C1C13 C1D6 C1R1 3
    3
    9 100UF 1UF 0.1UF 100UF 1UF .1UF
    0.01UF 10% 20% 10% 10% 20% 10% 10%
    16V 16V 50V 25V 16V 50V 6.3V 1
    X7R 1 ELEC 2 X7R X7R ELEC 2 X7R X5R 1
    402 2 2 RDL 603 603
    2 RDL 603 402 TRAY_STATUS_R BAV99
    3 BAV99
    SOT23S
    C1C4 4 EMPTY SOT23S
    36 OUT ODD_RX_DN 1 2 ODD_RX_DN_C 5 EMPTY
    6 V_5P0
    0.01UF 10% 7 TRAY_STATUS 1 R1R4 2 V_3P3
    16V 34 OUT J1D1
    X7R 8 100 5% V_5P0 1 EJECTSW_N
    402 402 CH IN 42 34
    4 3 TRAY_OPEN 34
    1 1 V_12P0 IN
    C1C3 CONN 1 C1D9 6 5
    ODD_RX_DP 1 2 ODD_RX_DP_C
    C1D4 C1D1 C1D3 8 7
    36 OUT 100UF 1UF 1UF .1UF
    20% 10% 10% 10% 10 9 1
    0.01UF 10% 16V 50V 50V 6.3V 12 11 C1R4
    16V 2 ELEC 2 X7R 2 X7R X5R 75PF
    X7R RDL 603 603 402 5%
    402 50V
    CONN 2 NPO
    402

    DRAWING
    PROJECT NAME PAGE REV
    XENON_FABK MICROSOFT
    [PAGE_TITLE=CONN, ODD + HDD] Wed Aug 24 09:27:35 2005
    CONFIDENTIAL
    XENON_RETAIL 47/73 K7
    DB8M1
    TP
    1

    DB8M2
    TP
    V_12P0 1
    V_3P3STBY FTP FT9N1 1

    DB8M3
    TP
    1

    1 C9B1 1 1 1 1
    2 C9A1 C9A5 C9A6 C9A2
    1 C6G5 C6G2 1500UF 0.1UF 0.1UF 0.1UF 0.1UF
    100UF 20% 10% 10% 10% 10% J9A1 CONN
    470PF 16V 25V 25V 25V 25V
    20% 5% ALUM 2 2 2 2
    16V 50V 2 RDL X7R X7R X7R X7R XENON PWR
    ELEC 1 X7R 603 603 603 603
    2 RDL 402 1 GND
    2 GND
    3 GND

    4 V12P0
    5 V12P0
    6 V12P0

    PSU_V12P0_EN 2 R8A2 1 PSU_V12P0_EN_R 7


    34 IN PSU_EN
    1 100 5%
    1 R6G7 2 402 CH 1 1 8 VSB5P0
    R8A1 C8A1 C8A2
    .1UF 470PF
    0 5% 10K 10% 5% 9 EMI1
    603 CH 5% 6.3V 50V 10
    NA 2 X5R 2 EMPTY EMI2
    CH 402 402 13
    SM 402 EMI3
    2 14 EMI4
    L6G1 EMPTY
    11 ME1
    ARGONPORT_DN 4 CMCHOKE 3 12
    35 BI ME2

    TH MTGA<8-1>
    ARGONPORT_DP 1 2 J6G1 CONN V_5P0STBY MTGB<8-1>
    35 BI
    1
    XENON RF FTP FT8N1
    X801560-001 1 1 X02285-004 TH
    C6G3 C6G4 1 CONN
    VCC
    470PF 470PF ARGON_DN_CM 2 D-
    5% 5%
    50V 50V ARGON_DP_CM 3 D+
    2 EMPTY 2 EMPTY 4
    R6G8 402 402 GND
    1 2 1
    1 C5B7 1 C8B1 C9A4
    0 5% 5 SPARE 100UF 100UF 470PF
    603 CH 6 C_DATA 20% 20% 5%
    7 16V 16V 50V
    C_CLK ELEC ELEC 2 X7R
    8 2 RDL 2 RDL 402
    GND
    USE LC NETWORK FOR USB 1.1 9 NTX
    USE USB CHOKE FOR USB 2.0
    V_3P3STBY 10 EMI1
    11 EMI2

    1 12 ME1
    13 ME2 V_5P0STBY V_12P0 V_12P0
    R3N7
    10K
    5%
    CH X800095-001
    402
    2 1 1
    PWRSW_N 2 R3N6 1 PWRSW_N_R R8B5 R7B2
    34 IN 2.2K 2.2K
    10K 5% 5% 5%
    402 CH 2
    C6V15 CH CH
    470PF 402 402
    5% 2 2 3
    1 50V 2 R8N1 1 BLEEDER_V12P0_B2 1 Q8N1
    X7R BCP51
    402 549 1%

    BLEEDER_V12P0_C2
    XSTR
    402 CH 2 4

    BLEEDER_V12P0_C1
    34 BI ARGON_DATA
    34 ARGON_CLK BLEEDER_V12P0_LOAD
    BI
    2 2
    C6V11 C6V10 1 1 1 1
    470PF 470PF
    5% 5% 3
    50V 50V R7N3 R7N1 R7N4 R7N2
    1 X7R 1 X7R 1 Q8B4 10 10 10 10
    402 402 MMBT2222 1% 1% 1% 1%
    XSTR CH CH CH CH
    2 805 805 805 805
    3
    R8A4 2 2 2 2
    2 1 BLEEDER_V12P0_B1 1 Q8B5
    MMBT2222
    2.2K 5% XSTR
    ARGON_NTX 402 CH 2
    44 OUT
    2
    C6V12
    470PF
    5% 2 R8A3 1
    50V 34 28 IN ANA_V12P0_PWRGD
    1 X7R
    402 2.2K 5%
    402 CH

    DRAWING
    PROJECT NAME PAGE REV
    XENON_FABK MICROSOFT
    [PAGE_TITLE=CONN, ARGON + POWER] Wed Aug 24 09:27:35 2005
    CONFIDENTIAL
    XENON_RETAIL 48/73 K7
    CPU_VREG_APS5 R7E3 5
    4 IN
    0 5% V_GPUCORE
    CPU_VREG_APS4 402 CH R7E1 4
    4 IN
    0 5%
    CPU_VREG_APS3 R7E5 402 CH 3
    4 IN N: WATERNOSE=011100=1.1625V
    0 5% 1 1 1 1 1 1 N: DD1.0 REQUIRES VID0 RC
    CPU_VREG_APS2 402 CH R7E4 2 N: DD2.0 NO STUFF RC
    4 IN R7T6 R7T4 R7T8 R7T7 R7T5 R7T9
    0 5% 10K 10K 10K 10K 10K 10K
    CPU_VREG_APS1 R7E2 402 CH 1 5% 5% 5% 5% 5% 5%
    4 IN EMPTY CH CH CH EMPTY EMPTY
    0 5% 402 402 402 402 402 402
    CPU_VREG_APS0 402 CH R7E6 0 2 2 2 2 2 2
    4 IN
    1K 5%
    402 CH 5 4 3 2 1 0 VREG_CPU_VID<5..0>
    OUT 50

    1 1 1 1 1 1
    1
    R7T13 R7T11 R7T15 R7T14 R7T12 R7T16 C7E13
    10K 10K 10K 10K 10K 10K 220PF
    5% 5% 5% 5% 5% 5% 5%
    50V
    CH EMPTY EMPTY EMPTY CH CH 2 NPO
    402 402 402 402 402 402 402
    2 2 2 2 2 2

    V_12P0 N:GPU INPUT FILTER

    V_12P0 N:CPU INPUT FILTER L8B1


    1 2 V_VREG_GPU 52 53
    OUT
    L9B1 1.6UH IND
    1 2 V_VREG_CPU 10A TH 1 1 1 1 1
    OUT 50 51 1 NA 1 C6B3 1 C7B3 C8B4 C6B5 C6N2 C7B4 C7N3
    1.6UH IND
    C8B2 1500UF 1500UF 10UF 10UF 10UF 10UF 10UF
    4.7UF 20% 20% 20% 20% 20% 20% 20%
    1 10A TH 1 1 10% 16V 16V 16V 16V 16V 16V 16V
    C9B2 NA C9C4 C9C1 C9E3 C9D2 C9B4 C9C3 16V 2 2 2 2 2
    4.7UF 1500UF 1500UF 1500UF 1500UF 10UF 10UF 2 X5R 2 ALUM
    RDL 2 ALUM
    RDL
    X5R
    1206
    X5R
    1206
    X5R
    1206
    X5R
    1206
    X5R
    1206
    10% 20% 20% 20% 20% 20% 20% 1206
    16V 16V 16V 16V 16V 16V 16V
    2 X5R ALUM ALUM ALUM ALUM 2 EMPTY 2 EMPTY
    1206 RDL RDL RDL RDL 1206 1206

    1
    DB8P1
    1
    DB8P2 V_GPUCORE
    V_CPUCORE
    1 1
    N:CPU OUTPUT FILTER FTP FT7U1 N:GPU OUTPUT FILTER FTP FT5R2

    1 C8F3 C8F1 C8E3 C8F2 C8E8 C8D1 C8C1 C8D4 1 C7C2 1 C7C1 1 C6C3 1 C6C2 1 C6C1 1 C5C4
    2200UF 2200UF 2200UF 2200UF 2200UF 2200UF 2200UF 2200UF 2200UF 2200UF 2200UF 2200UF 820UF 820UF
    20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
    6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 4V 4V
    2 ALUM
    RDL
    ALUM
    RDL
    ALUM
    RDL
    ALUM
    RDL
    ALUM
    RDL
    ALUM
    RDL
    ALUM
    RDL
    ALUM
    RDL 2 ALUM
    RDL 2 ALUM
    RDL
    ALUM
    2 RDL 2 ALUM
    RDL 2 POLY
    RDL 2 POLY
    RDL

    DRAWING
    PROJECT NAME PAGE REV
    XENON_FABK MICROSOFT
    [PAGE_TITLE=VREGS, INPUT + OUTPUT FILTERS] Wed Aug 24 09:27:36 2005
    CONFIDENTIAL
    XENON_RETAIL 49/73 K7
    V_VREG_CPU 2 R7V5 1 VREG_CPU_VCC
    51 49 IN
    10 1%
    VREG_CPU_EN 805 CH 1
    34 IN 1
    C7V1 1 C7G1 R8U3
    1 1UF 100UF 294K
    10% 20% 1%
    1 50V 16V
    FT2P17 FTP R7F5 2 X7R ELEC CH
    10K 603
    2 RDL 402
    5% 2 1
    CH FTP FT2P16
    402
    2
    VREG_CPU_PWRGD 34
    OUT
    U7U1 IC
    VREG_CPU_PHASE3 R7V1
    51 IN ADP3188
    0 5% 28 VCC
    603 CH PWRGD 10
    VREG_CPU_RAMPADJ 14 RAMPADJ
    VREG_CPU_PHASE2 R7V2 VREG_CPU_VID<5..0> IN 49
    51 VID5 6 5
    IN
    0 5% 11 EN VID4 1 4
    603 CH VID3 2 3
    DB7U3
    1 VREG_CPU_SW4 20 SW4 VID2 3 2
    VREG_CPU_PHASE1 R7V3 TP
    VREG_CPU_PHASE3_R 21 4 1
    51 IN SW3 VID1
    0 5% VREG_CPU_PHASE2_R 22 SW2 VID0 5 0
    603 CH VREG_CPU_PHASE1_R 23 SW1
    PWM4 24
    RT8F1 VREG_CPU_CSCOMP 18 CSCOMP PWM3 25 VREG_CPU_PWM3 OUT 51
    1 2 TEMP SENSOR 26 VREG_CPU_PWM2
    PWM2 OUT 51
    17 27 VREG_CPU_PWM1
    VREG_CPU_CSCOMP_R

    CSSUM PWM1 OUT 51


    NA THRMSTR
    100K 603 16 15 VREG_CPU_DRV_EN
    CSREF ILIMIT OUT 51

    8 FB DELAY 12 VREG_CPU_DELAY
    2 2 2
    R8V1 R8V2 R8V4 1 R8V3 2 9 COMP RT 13 VREG_CPU_RT 2 2
    47.5K 47.5K 47.5K 1 2
    1% 1% 1% 35.7K 1% C8U1 R8U1 R8U4 C8U2
    7 FBRTN GND 19 .047UF 324K 205K 1000PF
    CH CH CH 603 CH 2 10% 10%
    603 603 603 2 1% 1%
    R8U2 2 16V 1 50V
    1 1 1 1 1 X7R CH CH EMPTY
    R8V5 C8V1 C8U3 X803045-001 294K 603 603 402 402
    76.8K 360PF 8200PF 1% 1 1
    1% 10% 10% CH
    50V 16V ST7T1
    CH 2 NPO 2 CH 2 1 402
    603 603 603
    VREG_CPU_FBRTN 1
    1
    SHORT

    VREG_CPU_CSSUM 2
    C7U4
    1000PF N: TARGET FSW=233KHZ
    10%
    V_CPUCORE 1 50V
    X7R
    402
    LAYOUT:ATTACH TO
    CLOSEST INDUCTOR
    ST8F1
    1 2 VREG_CPU_CSREF 1 R8G3 2 VREG_CPU_CSREF_R

    10 1%
    SHORT 402 CH 2
    C8G1
    1000PF
    10%
    50V
    1 X7R
    402

    C7U2
    2 1 VREG_CPU_FB

    0.1UF 10% 2
    25V C7U3
    EMPTY 360PF
    603 10%
    50V
    1 NPO
    603
    1 R7U1 2 C7U1 1 R7U2 2
    1 2 VREG_CPU_COMP_R VREG_CPU_COMP

    1.33K 1% 3000PF 10% 4.02K 1%


    603 CH 50V 402 CH
    X7R
    603

    DRAWING
    PROJECT NAME PAGE REV
    XENON_FABK MICROSOFT
    [PAGE_TITLE=VREGS, CPU CONTROLLER] Wed Aug 24 09:27:36 2005
    CONFIDENTIAL
    XENON_RETAIL 50/73 K7
    51 50 49 IN V_VREG_CPU
    D9C1 3
    1N4148 C9P3
    V_VREG_CPU 1 R9P2 2 1 3
    VREG_CPU_BST3
    1 2 D Q9D1
    51 50 49 IN VREG_CPU3_VCC D Q9D2 1 1
    2.2 1% C9D3 C9D1
    805 CH SOT23 0.01UF 10% NTD60N02R 10UF 4.7UF
    DIO 50V NTD60N02R DPAK 20% 10%
    1 X7R DPAK 1 16V 16V
    C9P4 805 2 X5R 2 X5R
    1.0UF G S
    10% R9P1 C9P2 G S FET 1206 1206
    16V
    1 2 VREG_CPU_BST3_R 1 2 FET 2 VREG_CPU_PHASE3 50
    2 X7R
    OUT
    805 2.2 1% 0.015UF 5%
    U9P1 IC 805 CH 16V V_CPUCORE
    X7R
    MOS DRIVER 805
    4 VCC BST 1 L8D1
    50 VREG_CPU_PWM3 2 IN DRVH 8 VREG_CPU_DRVH3 1 2
    IN
    50 IN VREG_CPU_DRV_EN 3 OD_N* SW 7
    0.6UH IND
    6 PGND DRVL 5 30A TH
    1
    NA

    VREG_CPU_BG3
    R9C1
    X801233-001 3 2.2
    D Q9C1 D Q8C1 1%
    EMPTY
    NTD85N02R NTD85N02R 805
    2
    DPAK DPAK
    1
    G S G S
    FET FET VREG_CPU_SW3_R
    2
    1
    C9C5
    4700PF
    10%
    50V
    D9E1 2 EMPTY
    1N4148 C9T2 603
    1 R9T2 2 VREG_CPU2_VCC 1 3
    VREG_CPU_BST2
    1 2 3 3
    2.2 1% D Q9E1 D Q9D4 1 1
    805 CH SOT23 0.01UF 10% C9D4 C9E1
    DIO 50V 10UF 4.7UF
    1 X7R
    C9T3 805 NTD60N02R NTD60N02R 20% 10%
    1.0UF DPAK DPAK 2 16V 2 16V
    10% 1 R9T1 2 1
    C9T1
    2
    1 1 X5R X5R
    16V VREG_CPU_BST2_R
    G S G S 1206 1206 VREG_CPU_PHASE2
    2 X7R FET FET OUT 50
    805 2.2 1% 0.015UF 5% 2 2
    U9T1 IC 805 CH 16V
    X7R
    MOS DRIVER 805
    4 VCC BST 1 L8E1
    50 VREG_CPU_PWM2 2 IN DRVH 8 VREG_CPU_DRVH2 1 2
    IN
    3 OD_N* SW 7
    0.6UH IND
    6 PGND DRVL 5 1 30A TH
    R9E1 NA
    VREG_CPU_BG2
    X801233-001 2.2
    1%
    D Q9E3 D Q9D3
    EMPTY
    805
    NTD85N02R NTD85N02R 2
    DPAK DPAK
    G S FET G S FET VREG_CPU_SW2_R

    1
    C9E4
    4700PF
    10%
    D9F1 50V
    1N4148 2 EMPTY
    1 R9U2 2 VREG_CPU_BST1 C9U2 603
    VREG_CPU1_VCC 1 3 1 2
    3
    2.2 1% 0.01UF 10% D Q9F1 D Q9F4
    805 CH 1 SOT23 50V 1 1
    DIO C9F4 C9F1
    C9U3 X7R 10UF 4.7UF
    1.0UF 805 NTD60N02R NTD60N02R 20% 10%
    10% 1 R9U1 2 C9U1 16V 16V
    16V VREG_CPU_BST1_R 1 2 DPAK DPAK 2 2
    2 1 X5R X5R
    X7R 2.2 1% S S 1206 1206 VREG_CPU_PHASE1 50
    805 0.015UF 5% G FET G FET OUT
    805 CH 16V 2
    U9U1 IC X7R
    MOS DRIVER 805
    4 VCC BST 1 L8F1
    50 VREG_CPU_PWM1 2 IN DRVH 8 VREG_CPU_DRVH1 1 2
    IN
    3 OD_N* SW 7
    0.6UH IND
    6 PGND DRVL 5 30A TH
    1
    NA
    VREG_CPU_BG1

    R9F1
    X801233-001 2.2
    D Q9F2 D Q8F1 1%
    EMPTY
    NTD85N02R NTD85N02R 805
    2
    DPAK DPAK
    VREG_CPU_SW1_R
    G S FET G S FET
    1
    C9F3
    4700PF
    10%
    2 50V
    EMPTY
    603

    DRAWING
    PROJECT NAME PAGE REV
    XENON_FABK MICROSOFT
    [PAGE_TITLE=VREGS, CPU OUTPUT PHASE 1,2,3] Wed Aug 24 09:27:37 2005
    CONFIDENTIAL
    XENON_RETAIL 51/73 K7
    53 52 49 IN V_VREG_GPU 53 52 49 IN V_VREG_GPU
    V_GPUCORE
    1
    R8N7 VREG_GPU_VID4 1 R8N8 2
    2.2 D8B3
    1% 0 5% VREG_GPU_PHASE1_C
    402 EMPTY 1 1
    ST5R2 CH
    1 2 805 D8B2 C8B3
    1 R8N9 2 1N4148 3 2 1 VREG_GPU_PHASE1
    2 10000=1.150V
    VREG_GPU_VID3
    OUT 53 52
    SOT23
    SHORT 0 5% 3 DIO 0.1UF 10%
    402 CH 2 25V
    BAV99 X7R
    VREG_GPU_VID2 1 R8N10 2 SOT23S 603
    1 1 0 5% DIO
    C8N3 C8N2
    RT7C1 1.0UF 1.0UF 402 CH
    2 1 2 R8P9 1 10% 10% U8N1 IC
    VREG_GPU_VFB_R
    2 16V 2 16V VREG_GPU_VID1 1 R8N11 2 VREG_GPU_NPNC
    1.21K 1% X7R X7R NCP5331
    NA THRMSTR 2 R8P4 1 805 805 16 0 5% 1 2
    402 CH VCCL2
    10K 603 25 15 402 CH R8N2 C9B3
    5.11K 1% VCCL1 VID4 0.1UF
    402 CH VID3 14 1 R8N12 2 330 10%
    VREG_GPU_VID0 5% 25V
    VREG_GPU_VCCL 26 VCCL VID2 13 1 X7R
    2 R8P7 1 C8P2 12 0 5% CH 603
    2 1 VID1 402 CH 805
    1.1K 1% 52 VREG_GPU_5VREF 30 5VSB VID0 11 2
    IN
    402 CH 1000PF 10%
    50V VREG_GPU_VFFB 7 VFFB VCCH 20 VREG_GPU_VCCH
    EMPTY
    402
    VREG_GPU_VFB 1 VFB ILIM 31 VREG_GPU_ILIM 1 1
    C8N1 D8B1
    C8P1 VREG_GPU_COMP_R 2 R8P3 1 0.1UF MMSZ18
    1 2 VREG_GPU_VDRP 2 VDRP 5VREF 8 VREG_GPU_5VREF 52 10%
    OUT 25V SOD123
    4.02K 1% 2 X7R 2 DIO
    6800PF 10% 402 CH VREG_GPU_COMP 32 21 603
    50V COMP CBOUT
    X7R
    603 VREG_GPU_SEN 10 NSEN PGD 29
    VREG_GPU_COMP_C 1 R8P1 2 VREG_GPU_CS2 6 19
    CS2 GH2
    7.5K 1% VREG_GPU_CS1 4 CS1 GL2 17
    2 603 CH
    C9P1 C8N5 VREG_GPU_CSREF 5 22 1 R8B4 2
    2 1 CSREF GH1
    .047UF GL1 24
    10% 7.5K 1%
    16V 6800PF 10% VREG_GPU_ROSC 9 ROSC 603 CH
    1 X7R 50V 2 3
    LGND 3
    603 X7R 2 R8C1 Q8B3
    603 2 VREG_GPU_CPGD 28 CPGD C9C2 FET
    GND2 18 0.1UF 6.19K 1 2N7002
    ST5R1 R8P2 10% 1% V_5P0STBY
    1 2 42.2K 27 COVC GND1 23 25V 2 SOT23
    1%
    1 X7R CH
    603 402

    VREG_GPU_EN_N_R
    SHORT CH 1 1
    603 C8N4 X800631-001 1
    1 0.01UF
    10% R5N1
    16V
    R8P5 2 X7R 10K
    VREG_GPU_PHASE2 2 1 402 5%
    53 IN
    7.5K 1% CH
    603 CH 1 402
    V_GPUCORE C8P3 2
    0.1UF
    10% 1 R9B1 2
    25V 34 VREG_GPU_EN_N
    2 X7R IN
    603 1 10K 5%
    FT2P6 FTP 402 CH

    VREG_GPU_PHASE1 2 R8P6 1
    53 52 IN
    7.5K 1%
    603 CH
    V_GPUCORE 1 VREG_GPU_PWRGD 34
    C8P4 OUT
    0.1UF 1
    10% FTP FT2P3
    25V
    2 X7R
    603 VREG_GPU_GH2_R 1 R8N5 2 VREG_GPU_GH2
    OUT 53
    0 1A
    805 CH
    VREG_GPU_GL2_R 1 R8N6 2 VREG_GPU_GL2
    OUT 53
    ST5D1 0 1A
    1 2
    VREG_GPU_CSREF_R 2 R8B2 1 805 CH
    2K 1% VREG_GPU_GH1_R 1 R8N3 2 VREG_GPU_GH1
    SHORT OUT 53
    402 CH 2 0 1A
    2 805 CH
    C8B8 R8B3 1 R8N4 2
    0.1UF 750K VREG_GPU_GL1_R VREG_GPU_GL1 OUT 53
    10% C8B7 1% 0 1A
    25V 1 2
    1 X7R CH 805 CH
    603 603
    470PF 5% 1
    50V
    NPO
    603

    DRAWING
    PROJECT NAME PAGE REV
    XENON_FABK MICROSOFT
    [PAGE_TITLE=VREGS, GPU CONTROLLER] Wed Aug 24 09:27:38 2005
    CONFIDENTIAL
    XENON_RETAIL 52/73 K7
    52 49 IN V_VREG_GPU

    3 C6B2
    D Q6B1 4.7UF
    10%
    16V
    X5R
    NTD60N02R 1206
    1
    DPAK V_GPUCORE
    52 IN VREG_GPU_GH2
    G S VREG_GPU_PHASE2
    FET OUT 52
    2
    L6C1
    1 2
    0.6UH IND
    1 30A TH
    3 3 NA
    D Q6B2 D Q6C1 R6B3
    2.2
    1%
    NTD85N02R NTD85N02R CH
    DPAK DPAK 805
    52 VREG_GPU_GL2 1 1 2
    IN G S G S
    FET FET
    2 2

    VREG_GPU_PH2_R
    2
    C6B4
    3 C7B2 4700PF
    4.7UF 10%
    D Q7B1 10% 50V
    1 X7R
    16V 603
    X5R
    NTD60N02R 1206
    DPAK
    52 VREG_GPU_GH1 1
    IN G S
    FET
    2
    L7C1
    1 2
    0.6UH IND
    1 30A TH
    3 3 NA
    D Q7B2 D Q7C1 R7B6
    2.2 VREG_GPU_PHASE1 OUT 52
    1%
    NTD85N02R NTD85N02R CH
    DPAK DPAK 805
    52 VREG_GPU_GL1 1 1 2
    IN G S G S
    FET FET
    2 2

    VREG_GPU_PH1_R
    2
    C8B6
    4700PF
    10%
    1 50V
    X7R
    603

    V_5P0 V_1P8
    U1E1 IC U2T1 IC V_1P8 V_MEM
    NCP1117 NCP1117
    3 IN OUT 2 V_V3P3TOV1P8 3 IN OUT 2 1
    FTP FT2R8 1 R2T8 2
    1 ADJUST/GND 1 ADJUST/GND 0 1A
    1 1 1 C2E7 1 1 C2D6 805 EMPTY
    C2T5 C2R4
    C1T6 0.1UF 100UF 0.1UF 100UF
    1.0UF X800499-001 10% 20% X800500-001 10% 20%
    10% 16V 16V 1 R2T7 2
    DPAK 25V DPAK 25V
    16V 2 2
    2 X7R 3.3V X7R
    603 2 ELEC
    RDL 1.8V X7R
    603 2 ELEC
    RDL 0 1A
    805 805 EMPTY

    DRAWING
    PROJECT NAME PAGE REV
    XENON_FABK MICROSOFT
    [PAGE_TITLE=VREGS, GPU OUTPUT PHASE 1,2] Wed Aug 24 09:27:39 2005
    CONFIDENTIAL
    XENON_RETAIL 53/73 K7
    32 54 V_VREG_V1P8V5P0
    1 R3V1 2 V_12P0 IN
    32 54 IN V_VREG_V1P8V5P0
    2.2 1% 1 1
    C3U5 C3F6
    805 CH 4.7UF 4.7UF
    1 10% 10%
    VREG_V1P8_EN C3V1 16V 16V
    54 IN 1.0UF L7F1 2 X5R 2 X5R
    C3V4 10% 1 2 1206 1206 VREG_1P8_IS2P 54
    1 R3V7 2 1 2 16V V_VREG_V1P8V5P0 OUT 32 54 OUT
    VREG_V1P8_EN_R 2 X7R
    805 1.6UH NA
    32 54 V_VREG_V1P8V5P0 10 1% 470NF 10% 10A TH 3
    IN 603 CH 10V C3V2 1
    X7R D Q3F1 1 R3V4 2 2 1 FTP FT2U1
    603 C6F3 1 C7F2
    VREG_5P0_PHASE 1500UF 1500UF 13.3K 1%
    54 IN 20% 20% NTD60N02R 402 CH 0.1UF 10%
    16V 16V 25V
    54 54 VREG_1P8_IS2P ALUM ALUM 1
    DPAK X7R
    IN RDL 2 RDL
    VREG_1P8_GATEH2_R
    603 V_MEM

    V_VREG_V1P8V5P0_R
    G S R3V6
    FET 1 2
    2
    2 15.4K 1% DB3F1
    C4V4 L2F1
    0.1UF 402 CH TP
    10% V_MEM VREG_1P8_OUT 1 2 1
    25V 2
    1 X7R D4V2 4.0UH NA
    603 1 R2U1 2 R3U2 2 12A TH 1
    1 2.2 C3U6 1 C3F2 1 C2F3 1 C5F8
    402 1% 1% R2V2 10UF 820UF 820UF 220UF
    VREG_5P0_PHASE_C 402 CH 2 CH 3 2.2 10% 20% 20% 20%
    3 V_MEM 1% 6.3V 4V 4V 10V
    805 D Q2G1 2 POLY
    VREG_1P8_VFB2_C R3V3 1 CH X5R
    1206
    2 RDL 2 POLY
    RDL 2 ELEC
    RDL
    2 18.7K 805
    2 R3V8 1 C3V6 1% 1
    BAV99 1 2 NTD60N02R
    SOT23S EMPTY DPAK
    10 1% 1

    VREG_1P8_OUT_R
    4700PF 10% 402 VREG_1P8_GATEL2_R
    DIO 402 CH 1 S
    50V G FET
    X7R 2
    603
    U4V1 IC 2
    VREG_5P0_BST_R 2 R3G6 1
    NCP5425 R3V9
    1.47K 1% 2 18 VCC
    402 CH 0
    R3G7 1A 2
    1.07K 11 COMP2 CH C3V7
    2 1% 805 4700PF
    1 10%
    CH VREG_1P8_IS2P 14 IS+2 50V
    1 R4V1 1 X7R
    330 402 VREG_1P8_IS2M 15 IS-2
    C4V2 1 603
    0.1UF 5%
    10% CH VREG_1P8_VFB2 12 VFB2
    25V 805 20
    2 X7R R3V2 GATEH2 VREG_1P8_GATEH2
    603 1 2 1 VREG_1P8_ROSC 17 19 VREG_1P8_GATEL2
    ROSC GATEL2
    22.1K 1%
    402 CH VREG_5P0_BST 4 BST GATEH1 1 VREG_5P0_GATEH1
    54 V_VREG_V1P8V5P0
    GATEL1 2 VREG_5P0_GATEL1
    32
    IN
    54 IN VREG_V5P0_EN 10 COMP1 1 1
    NC<1> 5 C6U1 C6F7
    1 R4V3 2 VREG_5P0_IS1P 7 6 4.7UF 4.7UF
    54 IN IS+1 NC<0> 10% 10%
    43.2 1% VREG_5P0_IS1M 8 IS-1 16V 16V VREG_5P0_PHASE 54
    2 2 2 X5R 2 X5R VREG_5P0_IS1P OUT
    402 CH OUT 54
    1 C4V5 VREG_5P0_VFB1 9 R5F5 1206 1206
    C4V3 1 VREG_V5P0_EN_R 220NF VFB1
    10% 2.2
    0.1UF D4V1 10V 1% 1 R4G1 2 C4G1
    10% MMSZ18 V_5P0 1 X7R
    VREG_5P0_VREF2 13 VREF2 3 2 1
    25V SOD123 CH
    2 X7R 603 805 D Q6F1 12.1K 1% 1
    603 2 DIO 16 402 CH 0.1UF 10% FTP FT6V1
    MODE 1 25V
    NTD60N02R X7R
    2 R6U1 1 3 603
    GND DPAK
    402 1% VREG_5P0_GATEH1_R 1 1 R4G2 2
    2 G S V_5P0
    402 CH
    X800762-001
    FET
    R4V2 2 16.9K 1%
    51.1K 402 CH DB6G1
    1% L6F1
    V_5P0 1 2
    TP
    EMPTY VREG_V5P0_EN 2 1
    402 OUT 54
    1 R5F6 4.0UH NA
    2 R6V3 1 C6V1 2 12A TH
    VREG_5P0_VFB1_C 1 2 VREG_V1P8_EN 54
    0
    OUT 1A R6G1 1 1 C7F1
    5.36K 1% 4700PF 10% CH C7V2 C6G1 2200UF
    402 CH 3 2.2
    50V 805 1% 10UF 10UF 20%
    X7R 1 D Q6F2 10% 10% 6.3V
    R6V1 603 V_3P3STBY V_3P3STBY CH 2 6.3V 6.3V ALUM
    2 RDL
    2 1 805 EMPTY X5R
    NTD60N02R 1 1206 1206
    10.7K 1%
    402 CH DPAK
    2 2 1

    VREG_5P0_OUT_R
    VREG_5P0_GATEL1_R
    2 2 G S
    R6V2 R3V5 FET
    2K 10K R4G3 R3G1 2
    1% 5% 10K 10K
    5% VREG_V5P0_EN_N_R VREG_V1P8_EN_N_R
    5%
    CH CH
    402 402 CH 3 3 CH
    1 1 402 402
    1 R4G6 R3G5 1
    34 VREG_V5P0_EN_N 1 2 1 1 1 2 VREG_V1P8_EN_N 34
    IN IN 2
    1 10K 5% 2 2 10K 5% 1 C5G2
    1 FT2P18 FTP 402 CH Q4G1 Q3G1 402 CH FTP FT2P19 4700PF
    C3V3 FET FET 10%
    0.1UF SOT23 1 50V
    10% 2N7002 X7R
    SOT23 2N7002 603
    25V
    2 X7R
    603

    DRAWING
    PROJECT NAME PAGE REV
    XENON_FABK MICROSOFT
    [PAGE_TITLE=VREGS, V1P8 AND V5P0] Wed Aug 24 09:27:39 2005
    CONFIDENTIAL
    XENON_RETAIL 54/73 K7
    U6T2 EMPTY
    V_5P0
    V_5P0 V_5P0 LP2980
    1 R2F2 2 1 VIN VOUT 5
    V_5P0 0 1A 3 ENABLE GND 2
    805 EMPTY 1 1
    2 SOT23 4
    1 R7T10 R6T3 NC
    1 NTR2101P
    FET V_3P3 10K 10K
    R1F7 Q2F2 5% 5% C7T100
    1K 3 U1F1 IC 1UF X803461-001
    5% CH CH 10%
    402 402 SOT23_5
    NCP1086 50V
    CH VREG_V3P3_IN 3 IN TAB 4 1 2 2 X7R 3.5V
    402 FTP FT1U1 603 V_EFUSE
    2

    VREG_EFUSE_EN_C1
    1 U6T1 IC
    1 R1F8 2 C1U1 1 GND OUT 2
    34 VREG_3P3_EN_N VREG_3P3_EN_N_R
    1.0UF 1 1 C1F3 NCP502D
    IN C1F5
    1K 5% 10% 0.1UF 100UF
    16V 20% 1 VIN VOUT 5 1
    402 CH 2 X7R X800498-001 10% FTP FT7T6
    25V 16V
    805 3.3V 2 X7R
    603
    2 ELEC
    RDL
    VREG_EFUSE_EN_C2 3 ENABLE GND 2

    4 C7T98 C7T99
    NC 1UF 1UF
    CR6T1 10% 10%
    50V 50V
    MBT3904 3 6 X7R EMPTY
    X800489-002 603 603
    SC70
    VREG_EFUSE_EN 2 R6T4 1 VREG_EFUSE_EN_R
    5 2
    4 IN 3.5V
    1K 5%
    1 402 CH
    FT7T8 FTP XSTR
    2 4 1
    R6T1
    V_5P0STBY V_3P3STBY 10K
    U5B1 IC 5%
    CH
    NCP1117 402
    3 IN OUT 2 1 1
    FTP FT5N1
    V_3P3 V_GPUPCIE
    1 ADJUST/GND V_3P3STBY
    1 1 1 C5B2
    C5B1 U5C1 IC
    C5B3 0.1UF 100UF CR4N1
    1.0UF X800499-001 10% 20%
    10% 16V 1 NCP1117 N: TARGET IS 1.25V
    DPAK 25V 3 2 1
    16V 2 X7R ELEC IN OUT FTP FT5R1
    2 X7R 3.3V 603 2 RDL
    805 3
    1 ADJUST/GND OUT/TAB 4 1 1
    2 1 R5P2 R5C9
    C4C6 1K 1
    BAV99 1.0UF X800501-001
    SOT23S 10% 1% 1%

    V3P3STBY_V1P8STBY_D
    SOT223
    EMPTY 16V CH CH
    2 X7R 1.2V 402 0402
    V_1P8STBY 805 2 2
    V_5P0STBY
    U5B2 IC VREG_PCIEX_ADJUST

    VREG_PCIEX_R
    NCP1117 1
    3 IN OUT 2 1 CR4P2
    FTP FT5N2
    1 R5P1
    1
    1 C5P1 0
    1 ADJUST/GND .1UF 5%
    C5B5 1 1 C5B4 V_1P8STBY 10%
    1.0UF C5B6 3 6.3V CH
    10% 0.1UF 100UF 2 X5R 402
    X800500-001 10% 20% 402
    2 16V 16V 2 2 1
    X7R DPAK 25V C5C5
    805 2 X7R 2 ELEC BAV99
    1.8V 603 RDL 4.7UF
    SOT23S 10%
    EMPTY 2 6.3V
    X5R
    V_3P3 805
    1 R6C1 2
    1 R5C6 2 0 1A
    805 CH
    V_3P3 0 1A V_CPUPLL
    V_SBPCIE 805 EMPTY
    U3P1 IC V_1P8
    N: TARGET IS 1.87V U6R1 EMPTY
    NCP1117 N: TARGET IS 2.20V
    3 2 1 NCP1117
    IN OUT FTP FT2P26 1 R5C4 2 VREG_CPUPLL_IN
    3 2 1
    IN OUT FTP FT7R3
    1 ADJUST/GND OUT/TAB 4 1 1 0 1A
    805 CH 1 ADJUST/GND OUT/TAB 4 1 1
    1 R3C22 R3C21
    C2C5 499 1 1 R6R3 R6R1
    1.0UF X800501-001 C6P1 499 1
    10% 1% 1% 1.0UF X800501-001
    SOT223 10% 1% 1%
    16V CH CH SOT223
    2 X7R 1.2V 402 0402 2 16V EMPTY CH
    805 X7R 1.8V 402 0402
    2 2 805 2 2
    VREG_VDD_PEX_R

    VREG_VDD_PEX_ADJ

    VREG_CPUPLL_R
    VREG_CPUPLL_ADJUST
    1
    1 R2C3
    C2C6 243 1
    .1UF 1%
    10% 1
    6.3V CH C6R1 R6R2
    2 X5R 402 .1UF 374
    402 2 1 10% 1%
    C3C1 6.3V 1
    2 EMPTY EMPTY C7P1
    4.7UF 402 402
    10% 2 4.7UF
    6.3V 10%
    2 X5R 6.3V
    805
    2 X5R
    805

    DRAWING
    PROJECT NAME PAGE REV
    XENON_FABK MICROSOFT
    [PAGE_TITLE=[VREGS, LINEAR VREGS] Wed Aug 24 09:27:40 2005
    CONFIDENTIAL
    XENON_RETAIL 55/73 K7
    XDK, DEBUG CONNECTORS

    V_5P0DUAL
    J1D2 KER_DBG_RXD 33
    OUT
    2X5HDR_10
    V_5P0STBY
    35 OUT SPI_SS_N 2 1 SPI_MOSI OUT 35
    SPI_MISO 4 3 SPI_CLK J1F1
    35 IN OUT 35
    6 5 1X6HDR
    8 7 1
    9 2
    1 R2P18 2 SMC_RST_N DBG_LED0 3
    IN 28 34 46 34 IN
    EMPTY C1D7 100 5% 34 IN DBG_LED1 4
    .1UF 402 CH 34 DBG_LED2 5
    10% IN DBG_LED3 6
    6.3V V_3P3STBY 13 34 IN
    X5R
    402
    EMPTY
    TH

    SMC_RST_XDK_N
    C3B5 C2B15
    .1UF 1UF
    10% 10%
    6.3V 50V
    X5R X7R
    402 603
    J2B1
    V_3P3 2X7HDR_14
    33 KER_DBG_TXD 2 1
    IN
    34 IN SMC_DBG_TXD 4 3
    34 OUT SMC_DBG_EN 6 5
    8 7
    SMB_CLK_R 10 9 SMB_DATA_R 1 R2N14 2 SMB_DATA
    BI 28 34 46
    12 11 100 5% V_12P0
    1 13 402 CH
    C1R2
    .1UF
    10% EMPTY EXT_PWR_ON_DBG 1 R2B7 2 EXT_PWR_ON_N
    6.3V OUT 43 56 34
    2 X5R SMB_CLK 1 R2N13 2
    46 28 34 BI 1K 5%
    402
    100 5% 402 CH
    402 CH V_5P0STBY 1
    D8B4
    GREEN
    SM
    2 EMPTY

    1 1
    C2B13 C2B12 R8B6
    .1UF 1UF
    10% 10% 2K
    6.3V 50V 1%
    2 X5R X7R
    402 603 EMPTY
    V_12P0 402
    2

    V_5P0STBY 3
    1 R7V7 2 1 R8A5 2 1 Q8B6
    J9A2 MMBT2222
    V_5P0 0 1A 1X2HDR 1K 5% EMPTY
    805 EMPTY 1 402 EMPTY 2
    2
    V_GPUFAN

    1 R7V6 2 SM
    EMPTY C9A3 V_1P8
    0 1A
    .1UF V_1P8
    10%
    805 EMPTY 6.3V
    X5R
    402
    2 2 2 2
    J7G1 2
    1X3HDR R8C3 R8C4 R8C5 R8C6 1
    10K 10K 10K 10K C8P5 R8P8
    1 .1UF 10K
    2 5% 5% 5% 5% 10% 5%
    3 EMPTY EMPTY EMPTY EMPTY 2 6.3V
    402 402 402 402 X5R CH
    1 1 1 1 1 1 402 402
    C7G3 C7G4 EMPTY 1
    4.7UF 0.01UF
    10% 10% J8C1
    16V 16V
    2 EMPTY 2 EMPTY 2X5HDR
    805 402 CPU_RST_V1P1_N 2 R8C2 1 CPU_RST_N_2_R 2 1 CPU_CHECKSTOP_N
    4 IN IN 57
    1K 5% 4 3
    402 CH 6 5
    57 CPU_TMS 8 7 CPU_TCLK 57
    OUT CPU_TRST_N EXT_PWR_ON_N OUT
    57 10 9 43 56 34
    OUT CPU_TDO OUT
    57 IN
    57 OUT CPU_TDI EMPTY
    1
    1 C7D23
    FT7R7 FTP .1UF
    10%
    6.3V
    2 EMPTY
    402

    DRAWING
    PROJECT NAME PAGE REV
    XENON_FABK MICROSOFT
    [PAGE_TITLE=XDK. DEBUG CONN] Wed Aug 24 09:26:59 2005
    CONFIDENTIAL
    XENON_RETAIL 56/73 K7
    V_GPUCORE
    DEBUG BOARD, CPU + GPU DEBUG BREAKOUT]
    U4D1 7 OF 8 IC U7D1 3 OF 10 IC
    GPU VERSION 57 CPU VERSION 20
    TBCLK3 E25 56 CPU_TCLK AH7 TCLK TDO AJ7 CPU_TDO 56
    IN CPU_TDI CPU_CHECKSTOP_N OUT
    TBCLK2 D29 56 IN AK8 TDI CHECKSTOP_B AK2 OUT 56
    TBCLK1 G30 56 CPU_TMS AK4 TMS
    IN
    TBCLK0 F32 56 IN CPU_TRST_N AK7 TRST_B DEBUG_CLKOUT_DP E25 CPU_DBG_CLK_DP OUT
    DEBUG_CLKOUT_DN F25 CPU_DBG_CLK_DN OUT
    TB31 G21 CPU_DBGSEL_XDK<0..69>
    G22 C7 0 OUT 31
    TB30 DEBUG_OUT0
    TB29 F22 DEBUG_OUT1 F13 1
    G23 B7 2 N:CPU_DBGSEL_DEBUG<0..69>
    TB28 DEBUG_OUT2
    D23 A7 3 N:CPU_DBGSEL_XDK<0..69>
    TB27 DEBUG_OUT3
    TB26 G24 V_GPUCORE DEBUG_OUT4 A8 4
    TB25 E23 DEBUG_OUT5 A9 5
    TB24 E24 DEBUG_OUT6 C10 6
    TB23 D24 DEBUG_OUT7 B10 7
    TB22 G25 DEBUG_OUT8 A10 8
    TB21 G26 DEBUG_OUT9 E11 9
    TB20 E26 1 1 1 1 DEBUG_OUT10 E12 10
    TB19 D26 C6T35 C7T90 C6T36 C7T91 DEBUG_OUT11 E13 11
    TB18 E27 .1UF .1UF .1UF .1UF DEBUG_OUT12 A11 12
    10% 10% 10% 10%
    TB17 D27 6.3V 6.3V 6.3V 6.3V DEBUG_OUT13 F15 13
    E28 2 X5R 2 X5R 2 X5R 2 X5R E14 14
    TB16 402 402 402 402 DEBUG_OUT14
    TB15 D28 DEBUG_OUT15 D12 15
    TB14 H29 DEBUG_OUT16 A12 16
    TB13 E29 DEBUG_OUT17 D14 17
    TB12 H30 DEBUG_OUT18 E15 18
    TB11 C30 DEBUG_OUT19 C13 19
    TB10 B30 DEBUG_OUT20 B13 20
    TB9 A30 V_GPUCORE DEBUG_OUT21 E16 21
    TB8 G31 DEBUG_OUT22 A13 22
    TB7 B31 DEBUG_OUT23 A14 23
    TB6 A31 DEBUG_OUT24 A15 24
    TB5 B32 DEBUG_OUT25 D16 25
    TB4 A32 DEBUG_OUT26 C16 26
    TB3 F33 1 1 1 1 DEBUG_OUT27 B16 27
    E33
    C7T89 C6T34 C7T92 C6T31 E17
    TB2 .1UF .1UF .1UF .1UF DEBUG_OUT28 28
    TB1 D33 10% 10% 10% 10% DEBUG_OUT29 F17 29
    E34 6.3V 6.3V 6.3V 6.3V A17
    TB0 2 X5R 2 X5R 2 X5R 2 X5R DEBUG_OUT30 30
    402 402 402 402 DEBUG_OUT31 A16 31
    DEBUG_OUT32 A18 32
    X02056-010 DEBUG_OUT33 E18 33
    DEBUG_OUT34 A19 34
    DEBUG_OUT35 D18 35
    DEBUG_OUT36 B19 36
    DEBUG_OUT37 A20 37
    DEBUG_OUT38 C19 38
    DEBUG_OUT39 A21 39
    TP7A1 EMPTY DEBUG_OUT40 E19 40
    TP7M2 EMPTY D20
    TDRX2 TDRX4 DEBUG_OUT41 41
    DEBUG_OUT42 F19 42
    TDR_DIFF_XDK2_DP 1 DP DEBUG_OUT43 A22 43
    TDR_SINGLE_XDK2 1 SIG
    2 2 GND DEBUG_OUT44 B22 44
    GND TDR_DIFF_XDK2_DN 3 E20 45
    DN DEBUG_OUT45
    4 GND DEBUG_OUT46 A23 46
    DEBUG_OUT47 C22 47
    DEBUG_OUT48 A24 48
    DEBUG_OUT49 A25 49
    DEBUG_OUT50 E21 50
    DEBUG_OUT51 D22 51
    TP7A2 EMPTY A26 52
    TP7M1 EMPTY TDRX4 DEBUG_OUT52
    DEBUG_OUT53 B25 53
    TDRX2 F21 54
    1 DEBUG_OUT54
    DP E22 55
    1 2 DEBUG_OUT55
    SIG GND A27 56
    2 3 DEBUG_OUT56
    GND DN A28 57
    4 DEBUG_OUT57
    GND C25 58
    DEBUG_OUT58
    DEBUG_OUT59 D24 59
    DEBUG_OUT60 A29 60
    TP8A2 EMPTY TP8M1 EMPTY E23 61
    DEBUG_OUT61
    TDRX2 TDRX4 A30 62
    DEBUG_OUT62
    TDR_SINGLE_XDK1 1 DEBUG_OUT63 B28 63
    SIG TDR_DIFF_XDK1_DP 1 C29 64
    2 DP DEBUG_OUT64
    GND 2 F23 65
    GND DEBUG_OUT65
    TDR_DIFF_XDK1_DN 3 DN DEBUG_OUT66 B30 66
    4 GND DEBUG_OUT67 E24 67
    DEBUG_OUT68 C28 68
    DEBUG_OUT69 C30 69

    X02046-002
    TP8A1 EMPTY TP8M2 EMPTY
    TDRX2 TDRX4
    1 SIG 1 DP
    2 GND 2 GND
    3 DN
    4 GND

    DRAWING
    PROJECT NAME PAGE REV
    XENON_FABK MICROSOFT
    [PAGE_TITLE=DEBUG BOARD, CPU + GPU DEBUG BREAKOUT] Wed Aug 24 09:27:41 2005
    CONFIDENTIAL
    XENON_RETAIL 57/73 K7
    INTELLIGENT SERIAL NUMBER TARGET.
    LB7G1
    LABEL

    1
    1375X250_TARGET
    X801181-001

    WEST PCB MOUNTING HOLES MIDDLE PCB MOUNTING HOLES EAST PCB MOUNTING HOLES
    EDGE CTR EDGE
    MTG1B1 MTG5G1 MTG9G1
    MTG_HOLE MTG_HOLE MTG_HOLE
    NC9 9 NC9 9 NC9 9

    EMPTY EMPTY EMPTY


    GND=1,2,3,4,5,6,7,8 GND=1,2,3,4,5,6,7,8 GND=1,2,3,4,5,6,7,8
    EDGE CTR EDGE
    MTG1G1 MTG5B1 MTG9B1
    MTG_HOLE MTG_HOLE MTG_HOLE
    NC9 9 NC9 9 NC9 9

    EMPTY EMPTY EMPTY


    GND=1,2,3,4,5,6,7,8 GND=1,2,3,4,5,6,7,8 GND=1,2,3,4,5,6,7,8

    HEAT SINK MOUNTING HOLES


    STD STD
    MTG8C1 MTG6E1
    MTG_HOLE MTG_HOLE
    NC9 9 NC9 9

    EMPTY EMPTY
    GND=1,2,3,4,5,6,7,8 GND=1,2,3,4,5,6,7,8

    STD STD
    MTG3C1 MTG3E1
    MTG_HOLE MTG_HOLE
    NC9 9 NC9 9

    EMPTY EMPTY
    GND=1,2,3,4,5,6,7,8 GND=1,2,3,4,5,6,7,8

    STD STD
    MTG6C1 MTG8E1
    MTG_HOLE MTG_HOLE
    NC9 9 NC9 9

    EMPTY EMPTY
    GND=1,2,3,4,5,6,7,8 GND=1,2,3,4,5,6,7,8

    STD STD
    MTG5C1 MTG5E1
    MTG_HOLE MTG_HOLE
    NC9 9 NC9 9

    EMPTY EMPTY
    GND=1,2,3,4,5,6,7,8 GND=1,2,3,4,5,6,7,8

    DRAWING
    PROJECT NAME PAGE REV
    XENON_FABK MICROSOFT
    [PAGE_TITLE=LABELS AND MOUNTING] Wed Aug 24 09:27:41 2005
    CONFIDENTIAL
    XENON_RETAIL 64/73 K7
    *** Signal Cross-Reference for the entire design *** ENET_RX_DP 19B3> 39D1<> 44B5< FSB_GP_CP0_FLAG_DP 12C4> 5C7< MA_DQ11 14C8<> 20B5<> 21B5<>
    ENET_TX_DN 19B3> 39A1<> 44B5< FSB_GP_CP1_CLK_DN 12C4> 5C7< MA_DQ12 14C8<> 20B5<> 21B5<>
    ANA_CLK_OE 34B3> 28C8< 46B7< ENET_TX_DP 19B3> 39C1<> 44B5< FSB_GP_CP1_CLK_DP 12C4> 5C7< MA_DQ13 14C8<> 20B5<> 21B5<>
    ANA_PIX_CLK_2X_DN 28B1> 13C8< EXPPORT_DN 35B4<> 44C8<> FSB_GP_CP1_DATA0_DN 12B4> 5B7< MA_DQ14 14C8<> 20B5<> 21B5<>
    ANA_PIX_CLK_2X_DP 28B1> 13C8< EXPPORT_DP 35B4<> 44C8<> FSB_GP_CP1_DATA0_DP 12B4> 5B7< MA_DQ15 14C8<> 20C5<> 21B5<>
    ANA_RST_N 34C3> 28D7< EXT_PWR_ON_N 43C1> 56A1> 56C3> 34C8< 43A3< FSB_GP_CP1_DATA1_DN 12B4> 5B7< MA_DQ16 14C8<> 20C5<> 21C5<>
    ANA_V12P0_PWRGD 28D3> 34C3< 48A5< FAN1_FDBK 42C2> 29C6< FSB_GP_CP1_DATA1_DP 12B4> 5B7< MA_DQ17 14C8<> 20C5<> 21C5<>
    ANA_VDD_DAC18S 30D5> 30A5< FAN1_OUT 29C3> 42D5< FSB_GP_CP1_DATA2_DN 12B4> 5B7< MA_DQ18 14C8<> 20C5<> 21C5<>
    ANA_VID_INT 29D3> 33B2< FAN2_FDBK 42A2> 29C6< FSB_GP_CP1_DATA2_DP 12B4> 5B7< MA_DQ19 14C8<> 20C5<> 21C5<>
    ANA_XTAL_IN 46D2> 28C7< FAN2_OUT 29C3> 42B4< FSB_GP_CP1_DATA3_DN 12B4> 5B7< MA_DQ20 14C8<> 20C5<> 21C5<>
    ARGONPORT_DN 35B4<> 48C8<> FLSH_ALE 35C4> 41B5< FSB_GP_CP1_DATA3_DP 12B4> 5B7< MA_DQ21 14C8<> 20C5<> 21C5<>
    ARGONPORT_DP 35B4<> 48C8<> FLSH_CE_N 35C4> 41B5< FSB_GP_CP1_DATA4_DN 12B4> 5B7< MA_DQ22 14C8<> 20C5<> 21D5<>
    ARGON_CLK 34A1<> 48A7<> FLSH_CLE 35C4> 41B5< FSB_GP_CP1_DATA4_DP 12B4> 5B7< MA_DQ23 14C8<> 20C5<> 21D5<>
    ARGON_DATA 34A1<> 48A7<> FLSH_DATA<7..0> 35C8<> 41C8< FSB_GP_CP1_DATA5_DN 12B4> 5B7< MA_DQ24 14D8<> 20C5<> 21C5<>
    ARGON_NTX 48A6> 44B7< FLSH_READY 41C1> 35C8< FSB_GP_CP1_DATA5_DP 12B4> 5B7< MA_DQ25 14D8<> 20C5<> 21C5<>
    AUD_CLAMP 34C6> 40A6< FLSH_RE_N 35C4> 41B5< FSB_GP_CP1_DATA6_DN 12B4> 5B7< MA_DQ26 14D8<> 20C5<> 21C5<>
    AUD_CLK 28B1> 36C6< FLSH_WE_N 35C4> 41B5< FSB_GP_CP1_DATA6_DP 12B4> 5B7< MA_DQ27 14D8<> 20C5<> 21C5<>
    AUD_L_OUT 40C1> 43B4< FLSH_WP_N 35C8> 41B5< FSB_GP_CP1_DATA7_DN 12B4> 5B7< MA_DQ28 14D8<> 20C5<> 21C5<>
    AUD_RST_N 33B2> 40C8< FSB_CP_GP0_CLK_DN 5D3> 12D8< FSB_GP_CP1_DATA7_DP 12B4> 5B7< MA_DQ29 14D8<> 20C5<> 21C5<>
    AUD_R_OUT 40C1> 43B4< FSB_CP_GP0_CLK_DP 5D3> 12D8< FSB_GP_CP1_FLAG_DN 12B4> 5B7< MA_DQ30 14D8<> 20D5<> 21C5<>
    AV_MODE0 43B1> 34B8< 43A3< FSB_CP_GP0_DATA0_DN 5C3> 12C8< FSB_GP_CP1_FLAG_DP 12C4> 5B7< MA_DQ31 14D8<> 20D5<> 21C5<>
    AV_MODE1 43B1> 34B8< 43A3< FSB_CP_GP0_DATA0_DP 5C3> 12C8< GAMEPORT1_DN 35B7<> 45A8<> MA_RAS_N 14B5> 20B8< 21B8<
    AV_MODE2 43B1> 34B8< 43A3< FSB_CP_GP0_DATA1_DN 5C3> 12C8< GAMEPORT1_DP 35B7<> 45A8<> MA_RDQS0 20B5> 21B5> 14B8<
    BINDSW_N 42D6> 34B3< FSB_CP_GP0_DATA1_DP 5C3> 12C8< GAMEPORT2_DN 35B7<> 45C8<> MA_RDQS1 20B5> 21B5> 14C8<
    BRD_TEMP_N 29A7> 29A8< FSB_CP_GP0_DATA2_DN 5C3> 12C8< GAMEPORT2_DP 35B7<> 45C8<> MA_RDQS2 20C5> 21C5> 14C8<
    BRD_TEMP_P 29B1> 29A7< FSB_CP_GP0_DATA2_DP 5C3> 12C8< GPU_CLK_DN 46C1> 13D7< MA_RDQS3 20C5> 21C5> 14D8<
    CAL_TEMP_N 29B1> 29A8< FSB_CP_GP0_DATA3_DN 5C3> 12C8< GPU_CLK_DP 46C1> 13D7< MA_WDQS0 14B8> 20B5< 21B5<
    CPU_ANL_1 4C5> FSB_CP_GP0_DATA3_DP 5C3> 12C8< GPU_HSYNC_OUT 13C4> 29C6< MA_WDQS1 14C8> 20B5< 21B5<
    CPU_CHECKSTOP_N 57D1> 56A1< FSB_CP_GP0_DATA4_DN 5C3> 12C8< GPU_PIX_CLK_1X 13C3> 29D6< MA_WDQS2 14C8> 20C5< 21C5<
    CPU_CLK_DN 46D1> 4D6< FSB_CP_GP0_DATA4_DP 5C3> 12C8< GPU_RST_DONE 13D3> 34C1< MA_WDQS3 14D8> 20C5< 21C5<
    CPU_CLK_DP 46D1> 4D6< FSB_CP_GP0_DATA5_DN 5C3> 12C8< GPU_RST_N 34B3> 13D8< MA_WE_N 14B5> 20B8< 21B8<
    CPU_DBGSEL_DEBUG<0..69> 31D8< FSB_CP_GP0_DATA5_DP 5C3> 12C8< GPU_SCAN_BUFF_EN_N 13A7> 12A3< MB_A<11..0> 22C8< 23C8<
    CPU_DBGSEL_XDK<0..69> 57D1> 31D4< FSB_CP_GP0_DATA6_DN 5C3> 12C8< GPU_SPI_CLK 13B3> 13A7< MB_A<12..0> 14C1>
    CPU_DBG_CLK_DN 57D1> FSB_CP_GP0_DATA6_DP 5C3> 12C8< GPU_SPI_CS_N 13B3> 13A7< MB_BA<2..0> 14C1> 22B8< 23B8<
    CPU_DBG_CLK_DP 57D1> FSB_CP_GP0_DATA7_DN 5C3> 12C8< GPU_SPI_SI 13A2> 13B4> 13C7< MB_CAS_N 14B1> 22B8< 23B8<
    CPU_FSB_HF_CLKOUT_DN 4C2> FSB_CP_GP0_DATA7_DP 5C3> 12C8< GPU_SPI_SO 13C3> 13A7< MB_CKE 14B1> 22B8< 23B8<
    CPU_FSB_HF_CLKOUT_DP 4C2> FSB_CP_GP0_FLAG_DN 5C3> 12C8< GPU_SPI_WP_N 13B4> 13A4< MB_CLK0_DN 14C1> 22C8<
    CPU_PWRGD 34B3> 4D8< FSB_CP_GP0_FLAG_DP 5C3> 12C8< GPU_TEMP_N 13C8> 29B8< MB_CLK0_DP 14C1> 22D8<
    CPU_RST_N 34B3> 4D8< FSB_CP_GP1_CLK_DN 5C3> 12C8< GPU_TEMP_P 29B1> 13C8< MB_CLK1_DN 14C1> 23C8<
    CPU_RST_V1P1_N 4D7> 56A5< FSB_CP_GP1_CLK_DP 5C3> 12C8< GPU_VSYNC_OUT 13C4> 29C6< MB_CLK1_DP 14C1> 23D8<
    CPU_SPI_CLK 4B1> 4A5< FSB_CP_GP1_DATA0_DN 5B3> 12B8< HDD_RX_DN 47C8> 36B6< MB_CS0_N 14B1> 22B8<
    CPU_SPI_EN 4B2> 4A6< FSB_CP_GP1_DATA0_DP 5B3> 12B8< HDD_RX_DP 47B8> 36B6< MB_CS1_N 14B1> 23B8<
    CPU_SPI_SI 4A1> 4B3> 4B6< FSB_CP_GP1_DATA1_DN 5B3> 12B8< HDD_TX_DN 36B3> 47D8< MB_DM0 14B4> 22B5< 23B5<
    CPU_SPI_SO 4B2> 4A5< FSB_CP_GP1_DATA1_DP 5B3> 12B8< HDD_TX_DP 36B3> 47D8< MB_DM1 14C4> 22B5< 23B5<
    CPU_SPI_WP_N 4A3> 4A2< FSB_CP_GP1_DATA2_DN 5B3> 12B8< I2S_BCLK 36C1> 40C7< MB_DM2 14C4> 22C5< 23C5<
    CPU_TCLK 56A1> 57D5< FSB_CP_GP1_DATA2_DP 5B3> 12B8< I2S_MCLK 36C1> 40C7< MB_DM3 14D4> 22C5< 23C5<
    CPU_TDI 56A5> 57D5< FSB_CP_GP1_DATA3_DN 5B3> 12B8< I2S_SD 36C1> 40C7< MB_DQ0 14B4<> 22B5<> 23B5<>
    CPU_TDO 57D1> 56A5< FSB_CP_GP1_DATA3_DP 5B3> 12B8< I2S_WS 36C1> 40C7< MB_DQ1 14B4<> 22B5<> 23B5<>
    CPU_TEMP_N 4B2> 29B8< FSB_CP_GP1_DATA4_DN 5B3> 12B8< IR_DATA 42A5> 34B6< MB_DQ2 14B4<> 22B5<> 23B5<>
    CPU_TEMP_P 29B1> 4B2< FSB_CP_GP1_DATA4_DP 5B3> 12B8< KER_DBG_RXD 56D4> 33C6< MB_DQ3 14B4<> 22B5<> 23B5<>
    CPU_TMS 56A5> 57D5< FSB_CP_GP1_DATA5_DN 5B3> 12B8< KER_DBG_TXD 33C1> 56C6< MB_DQ4 14B4<> 22B5<> 23B5<>
    CPU_TRST_N 56A5> 57D5< FSB_CP_GP1_DATA5_DP 5B3> 12B8< MA_A<11..0> 20C8< 21C8< MB_DQ5 14B4<> 22B5<> 23B5<>
    CPU_VREG_APS0 4B2> 49C7< FSB_CP_GP1_DATA6_DN 5B3> 12B8< MA_A<12..0> 14C5> MB_DQ6 14B4<> 22B5<> 23B5<>
    CPU_VREG_APS1 4B2> 49D7< FSB_CP_GP1_DATA6_DP 5B3> 12B8< MA_BA<2..0> 14C5> 20B8< 21B8< MB_DQ7 14B4<> 22B5<> 23B5<>
    CPU_VREG_APS2 4B2> 49D7< FSB_CP_GP1_DATA7_DN 5B3> 12B8< MA_CAS_N 14B5> 20B8< 21B8< MB_DQ8 14C4<> 22B5<> 23B5<>
    CPU_VREG_APS3 4B2> 49D7< FSB_CP_GP1_DATA7_DP 5B3> 12B8< MA_CKE 14B5> 20B8< 21B8< MB_DQ9 14C4<> 22B5<> 23B5<>
    CPU_VREG_APS4 4B2> 49D7< FSB_CP_GP1_FLAG_DN 5B3> 12B8< MA_CLK0_DN 14C5> 20C8< MB_DQ10 14C4<> 22B5<> 23B5<>
    CPU_VREG_APS5 4B2> 49D7< FSB_CP_GP1_FLAG_DP 5B3> 12C8< MA_CLK0_DP 14C5> 20D8< MB_DQ11 14C4<> 22B5<> 23B5<>
    DBG_LED0 34A8<> 56D3< FSB_GP_CP0_CLK_DN 12D4> 5D7< MA_CLK1_DN 14C5> 21C8< MB_DQ12 14C4<> 22B5<> 23B5<>
    DBG_LED1 34B8<> 56D3< FSB_GP_CP0_CLK_DP 12D4> 5D7< MA_CLK1_DP 14C5> 21D8< MB_DQ13 14C4<> 22B5<> 23B5<>
    DBG_LED2 34B8<> 56D3< FSB_GP_CP0_DATA0_DN 12C4> 5C7< MA_CS0_N 14B5> 20B8< MB_DQ14 14C4<> 22B5<> 23B5<>
    DBG_LED3 34B8<> 13C7< 56D3< FSB_GP_CP0_DATA0_DP 12C4> 5C7< MA_CS1_N 14B5> 21B8< MB_DQ15 14C4<> 22B5<> 23B5<>
    DDC_CLK 35A1<> 43C1<> 34B8< FSB_GP_CP0_DATA1_DN 12C4> 5C7< MA_DM0 14B8> 20B5< 21B5< MB_DQ16 14C4<> 22C5<> 23C5<>
    DDC_CLK_OUT 34C8<> 35A5<> FSB_GP_CP0_DATA1_DP 12C4> 5C7< MA_DM1 14C8> 20B5< 21B5< MB_DQ17 14C4<> 22C5<> 23C5<>
    DDC_DATA 35B1<> 43C1<> FSB_GP_CP0_DATA2_DN 12C4> 5C7< MA_DM2 14C8> 20C5< 21C5< MB_DQ18 14C4<> 22C5<> 23C5<>
    DDC_DATA_OUT 34C8<> 35B5<> FSB_GP_CP0_DATA2_DP 12C4> 5C7< MA_DM3 14D8> 20C5< 21C5< MB_DQ19 14C4<> 22C5<> 23C5<>
    EDRAM_TEMP_N 13C8> 29A8< FSB_GP_CP0_DATA3_DN 12C4> 5C7< MA_DQ0 14B8<> 20B5<> 21B5<> MB_DQ20 14C4<> 22C5<> 23C5<>
    EDRAM_TEMP_P 29B1> 13C8< FSB_GP_CP0_DATA3_DP 12C4> 5C7< MA_DQ1 14B8<> 20B5<> 21B5<> MB_DQ21 14C4<> 22C5<> 23C5<>
    EJECTSW_N 42C6> 34B3< 47A1< FSB_GP_CP0_DATA4_DN 12C4> 5C7< MA_DQ2 14B8<> 20B5<> 21B5<> MB_DQ22 14C4<> 22C5<> 23C5<>
    ENET_ACT_N 19B3> 39C3> 44B5< FSB_GP_CP0_DATA4_DP 12C4> 5C7< MA_DQ3 14B8<> 20B5<> 21B5<> MB_DQ23 14C4<> 22C5<> 23D5<>
    ENET_AVDD 19D4> 19B3< 19B6< FSB_GP_CP0_DATA5_DN 12C4> 5C7< MA_DQ4 14B8<> 20B5<> 21B5<> MB_DQ24 14D4<> 22C5<> 23C5<>
    ENET_CLK 46B1> 19C6< 39C7< FSB_GP_CP0_DATA5_DP 12C4> 5C7< MA_DQ5 14B8<> 20B5<> 21B5<> MB_DQ25 14D4<> 22C5<> 23C5<>
    ENET_LINK_N 19B3> 39B2> 44B5< FSB_GP_CP0_DATA6_DN 12C4> 5C7< MA_DQ6 14B8<> 20B5<> 21B5<> MB_DQ26 14D4<> 22C5<> 23C5<>
    ENET_P2LI_R 39B2> 44B5< FSB_GP_CP0_DATA6_DP 12C4> 5C7< MA_DQ7 14B8<> 20B5<> 21C5<> MB_DQ27 14D4<> 22C5<> 23C5<>
    ENET_POAC_R 39C3> 44B5< FSB_GP_CP0_DATA7_DN 12C4> 5C7< MA_DQ8 14C8<> 20B5<> 21B5<> MB_DQ28 14D4<> 22C5<> 23C5<>
    ENET_RST_N 33A2> 19C6< 39C8< FSB_GP_CP0_DATA7_DP 12C4> 5C7< MA_DQ9 14C8<> 20B5<> 21B5<> MB_DQ29 14D4<> 22C5<> 23C5<>
    ENET_RX_DN 19B3> 39C1<> 44B5< FSB_GP_CP0_FLAG_DN 12C4> 5C7< MA_DQ10 14C8<> 20B5<> 21B5<> MB_DQ30 14D4<> 22C5<> 23C5<>

    PROJECT NAME PAGE REV


    MICROSOFT
    XENON_RETAIL 65/73 K7
    CONFIDENTIAL
    MB_DQ31 14D4<> 22D5<> 23C5<> MD_CS0_N 15B1> 26B8< MII_RXDV 19C6> 39C7> 36C6< VREG_GPU_EN_N 34C3> 52B3<
    MB_RAS_N 14B1> 22B8< 23B8< MD_CS1_N 15B1> 27B8< MII_RXER 19C6> 39C7> 36C6< VREG_GPU_GH1 52A1> 53C7<
    MB_RDQS0 22B5> 23B5> 14B4< MD_DM0 15B4> 26B5< 27B5< MII_RX_CLK 19C6> 39C7> 36D7< VREG_GPU_GH2 52A1> 53D7<
    MB_RDQS1 22B5> 23B5> 14C4< MD_DM1 15C4> 26B5< 27B5< MII_TXD0 36C3> 19B6< 39B7< VREG_GPU_GL1 52A1> 53B7<
    MB_RDQS2 22C5> 23C5> 14C4< MD_DM2 15C4> 26C5< 27C5< MII_TXD1 36C3> 19B6< 39B7< VREG_GPU_GL2 52A1> 53C7<
    MB_RDQS3 22C5> 23C5> 14D4< MD_DM3 15D4> 26C5< 27C5< MII_TXD2 36C3> 19B6< 39B7< VREG_GPU_PHASE1 52D1> 53B2> 52B8<
    MB_WDQS0 14B4> 22B5< 23B5< MD_DQ0 15B4<> 26B5<> 27B5<> MII_TXD3 36C3> 19B6< 39C7< VREG_GPU_PHASE2 53D2> 52B8<
    MB_WDQS1 14C4> 22B5< 23B5< MD_DQ1 15B4<> 26B5<> 27B5<> MII_TXEN 36C3> 19B6< 39C7< VREG_GPU_PWRGD 52A1> 34D1<
    MB_WDQS2 14C4> 22C5< 23C5< MD_DQ2 15B4<> 26B5<> 27B5<> MII_TX_CLK 19B6> 39C7> 36D7< VREG_V1P8_EN 54A4> 54D8<
    MB_WDQS3 14D4> 22C5< 23C5< MD_DQ3 15B4<> 26B5<> 27B5<> ODD_RX_DN 47A8> 36B6< VREG_V1P8_EN_N 34B3> 54A3<
    MB_WE_N 14B1> 22B8< 23B8< MD_DQ4 15B4<> 26B5<> 27B5<> ODD_RX_DP 47A8> 36B6< VREG_V5P0_EN 54A4> 54B7<
    MC_A<11..0> 24C8< 25C8< MD_DQ5 15B4<> 26B5<> 27B5<> ODD_TX_DN 36B3> 47A8< VREG_V5P0_EN_N 34B3> 54A7<
    MC_A<12..0> 15C5> MD_DQ6 15B4<> 26B5<> 27C5<> ODD_TX_DP 36B3> 47B8< VREG_V5P0_SEL 34B3> 46A8<
    MC_BA<2..0> 15C5> 24C8< 25B8< MD_DQ7 15B4<> 26B5<> 27C5<> PCIEX_CLK_DN 46B1> 33C6< V_CMPAVDD33_USB 37A7> 37C2<
    MC_CAS_N 15B5> 24B8< 25B8< MD_DQ8 15C4<> 26B5<> 27B5<> PCIEX_CLK_DP 46B1> 33C6< V_ENET 39A3> 19C3< 19C7< 39B8< 39B8<
    MC_CKE 15C5> 24B8< 25B8< MD_DQ9 15C4<> 26B5<> 27B5<> PEX_GPU_SB_L0_DN 13C1> 33C7< 39D5< 44B6<
    MC_CLK0_DN 15C5> 24C8< MD_DQ10 15C4<> 26B5<> 27B5<> PEX_GPU_SB_L0_DP 13D1> 33C7< V_EXPPORT 44B7< 44D4 44D7<
    MC_CLK0_DP 15C5> 24D8< MD_DQ11 15C4<> 26B5<> 27B5<> PEX_GPU_SB_L1_DN 13D1> 33C7< V_MEMPORT1 45D1>
    MC_CLK1_DN 15C5> 25C8< MD_DQ12 15C4<> 26C5<> 27B5<> PEX_GPU_SB_L1_DP 13D1> 33C7< V_VREG_CPU 49B4> 50D7< 51D5< 51D8<
    MC_CLK1_DP 15D5> 25D8< MD_DQ13 15C4<> 26C5<> 27B5<> PEX_SB_GPU_L0_DN 33C1> 13D8< V_VREG_GPU 49B1> 52D4< 52D7< 53D7<
    MC_CS0_N 15B5> 24B8< MD_DQ14 15C4<> 26C5<> 27B5<> PEX_SB_GPU_L0_DP 33C1> 13D8< V_VREG_V1P8V5P0 54D4> 32D4< 54B4< 54D4< 54D7<
    MC_CS1_N 15B5> 25B8< MD_DQ15 15C4<> 26C5<> 27B5<> PEX_SB_GPU_L1_DN 33D1> 13D8< 54D8<
    MC_DM0 15B8> 24B4< 25B4< MD_DQ16 15C4<> 26C5<> 27C5<> PEX_SB_GPU_L1_DP 33D1> 13D8< WSS_CNTL0 33B2> 43B6<
    MC_DM1 15C8> 24B4< 25B4< MD_DQ17 15C4<> 26C5<> 27C5<> PIX_DATA<14..0> 13C3> 29D6< WSS_CNTL1 33B2> 43B6<
    MC_DM2 15C8> 24C4< 25C4< MD_DQ18 15C4<> 26C5<> 27C5<> PSU_V12P0_EN 34B3> 48C5<
    MC_DM3 15D8> 24C4< 25C4< MD_DQ19 15C4<> 26C5<> 27C5<> PWRSW_N 34C3> 48B8<
    MC_DQ0 15B8<> 24B5<> 25B4<> MD_DQ20 15C4<> 26C5<> 27C5<> SATA_CLK_DN 46B1> 33D6<
    MC_DQ1 15B8<> 24B5<> 25B4<> MD_DQ21 15C4<> 26C5<> 27D5<> SATA_CLK_DP 46B1> 33D6<
    MC_DQ2 15B8<> 24B5<> 25B4<> MD_DQ22 15C4<> 26C5<> 27D5<> SATA_CLK_REF 46A1> 33D6<
    MC_DQ3 15B8<> 24B5<> 25B4<> MD_DQ23 15D4<> 26C5<> 27D5<> SB_GPIO<0..15> 33B1<> 33B5<>
    MC_DQ4 15B8<> 24B5<> 25B4<> MD_DQ24 15D4<> 26C5<> 27C5<> SB_MAIN_PWRGD 34B1> 34C6<
    MC_DQ5 15B8<> 24B5<> 25B4<> MD_DQ25 15D4<> 26C5<> 27C5<> SB_RST_N 34B3> 34C6<
    MC_DQ6 15B8<> 24B5<> 25C4<> MD_DQ26 15D4<> 26C5<> 27C5<> SCART_RGB 33B2> 43A6<
    MC_DQ7 15B8<> 24B5<> 25C4<> MD_DQ27 15D4<> 26D5<> 27C5<> SMB_CLK 34B8<> 56C7<> 28B6< 46B6<
    MC_DQ8 15C8<> 24B5<> 25B4<> MD_DQ28 15D4<> 26D5<> 27C5<> SMB_DATA 28B7<> 34B8<> 56C3<> 46B6<
    MC_DQ9 15C8<> 24B5<> 25B4<> MD_DQ29 15D4<> 26D5<> 27C5<> SMC_DBG_EN 56C6> 34C6<
    MC_DQ10 15C8<> 24B5<> 25B4<> MD_DQ30 15D4<> 26D5<> 27C5<> SMC_DBG_TXD 34C3> 56C6<
    MC_DQ11 15C8<> 24B5<> 25B4<> MD_DQ31 15D4<> 26D5<> 27C5<> SMC_PWM0 34B3> 29B8<
    MC_DQ12 15C8<> 24B5<> 25B4<> MD_RAS_N 15B1> 26B8< 27B8< SMC_PWM1 34B3> 29C8<
    MC_DQ13 15C8<> 24B5<> 25B4<> MD_RDQS0 26B5> 27B5> 15B4< SMC_RST_N 28D3> 34D6< 46C8< 56D3<
    MC_DQ14 15C8<> 24C5<> 25B4<> MD_RDQS1 26B5> 27B5> 15C4< SPDIF 36C1> 43D6<
    MC_DQ15 15C8<> 24C5<> 25B4<> MD_RDQS2 26C5> 27C5> 15C4< SPI_CLK 56D6> 35D7<
    MC_DQ16 15C8<> 24C5<> 25C4<> MD_RDQS3 26C5> 27C5> 15D4< SPI_MISO 35D3> 56D8<
    MC_DQ17 15C8<> 24C5<> 25C4<> MD_WDQS0 15B4> 26B5< 27B5< SPI_MOSI 56D6> 35D7<
    MC_DQ18 15C8<> 24C5<> 25C4<> MD_WDQS1 15C4> 26B5< 27B5< SPI_SS_N 56D8> 35D7<
    MC_DQ19 15C8<> 24C5<> 25C4<> MD_WDQS2 15C4> 26C5< 27C5< STBY_CLK 46A1> 34D6<
    MC_DQ20 15C8<> 24C5<> 25C4<> MD_WDQS3 15D4> 26C5< 27C5< TILTSW_N 42B6> 34B3<
    MC_DQ21 15C8<> 24C5<> 25D4<> MD_WE_N 15B1> 26B8< 27B8< TRAY_OPEN 34D8> 47A1<
    MC_DQ22 15C8<> 24C5<> 25D4<> MEMPORT1_DN 35C4<> 45B4<> TRAY_STATUS 47A4> 34C6<
    MC_DQ23 15D8<> 24C5<> 25D4<> MEMPORT1_DP 35C4<> 45B4<> VID_DACA_DP 29D3> 43D8<
    MC_DQ24 15D8<> 24C5<> 25C4<> MEMPORT2_DN 35B4<> 45C4<> VID_DACA_OUT 43D5> 43C4<
    MC_DQ25 15D8<> 24C5<> 25C4<> MEMPORT2_DP 35B4<> 45C4<> VID_DACB_DP 29D3> 43C8<
    MC_DQ26 15D8<> 24C5<> 25C4<> MEM_A_VREF0 21A6> 20B8< 21B8< VID_DACB_OUT 43C6> 43C4<
    MC_DQ27 15D8<> 24C5<> 25C4<> MEM_A_VREF1 20A6> 20B8< 21B8< VID_DACC_DP 29D3> 43C8<
    MC_DQ28 15D8<> 24C5<> 25C4<> MEM_B_VREF0 23A6> 22B8< 23B8< VID_DACC_OUT 43C6> 43C4<
    MC_DQ29 15D8<> 24D5<> 25C4<> MEM_B_VREF1 22A6> 22B8< 23B8< VID_DACD_DP 29D3> 43B8<
    MC_DQ30 15D8<> 24D5<> 25C4<> MEM_C_VREF0 25A6> 24B8< 25B8< VID_DACD_OUT 43B6> 43B4<
    MC_DQ31 15D8<> 24D5<> 25C4<> MEM_C_VREF1 24A6> 24B8< 25B8< VID_HSYNC_OUT 43A4> 43B4<
    MC_RAS_N 15B5> 24B8< 25B8< MEM_D_VREF0 27A7> 26B8< 27B8< VID_HSYNC_OUT_R 29C3> 43A7<
    MC_RDQS0 24B4> 25B4> 15B8< MEM_D_VREF1 26A7> 26B8< 27B8< VID_VSYNC_OUT 43A6> 43B4<
    MC_RDQS1 24B4> 25B4> 15C8< MEM_RST 13B3> 20C8< 21C8< 22C8< 23C8< VID_VSYNC_OUT_R 29C3> 43A8<
    MC_RDQS2 24C4> 25C4> 15C8< 24C8< 25C8< 26C8< 27C8< VREG_1P8_IS2P 54D1> 54D7< 54D7<
    MC_RDQS3 24C4> 25C4> 15D8< MEM_SCAN_BOT_EN 12A1> 21B8< 23B8< 25B8< 27B8< VREG_3P3_EN_N 34C3> 55D8<
    MC_WDQS0 15B8> 24B4< 25B4< MEM_SCAN_BOT_EN_BUFF 13B3> 12A4< VREG_5P0_IS1P 54B1> 54B6<
    MC_WDQS1 15C8> 24B4< 25B4< MEM_SCAN_EN 12D1> 20B8< 21B8< 22B8< 23B8< VREG_5P0_PHASE 54B1> 54D8<
    MC_WDQS2 15C8> 24C4< 25C4< 24B8< 25B8< 26B8< 27B8< VREG_CPU_DRV_EN 50C1> 51D8<
    MC_WDQS3 15D8> 24C4< 25C4< MEM_SCAN_EN_BUFF 13B3> 12D4< VREG_CPU_EN 34B3> 50D7<
    MC_WE_N 15B5> 24B8< 25B8< MEM_SCAN_TOP_EN 12B1> 20B8< 22B8< 24B8< 26B8< VREG_CPU_PHASE1 51A1> 50C8<
    MD_A<11..0> 26C8< 27C8< MEM_SCAN_TOP_EN_BUFF 13B3> 12B4< VREG_CPU_PHASE2 51C1> 50C8<
    MD_A<12..0> 15C1> MII_COL 19B6> 39B7> 36C6< VREG_CPU_PHASE3 51D1> 50C8<
    MD_BA<2..0> 15C1> 26C8< 27B8< MII_CRS 19B6> 39B7> 36C6< VREG_CPU_PWM1 50C2> 51A7<
    MD_CAS_N 15B1> 26B8< 27B8< MII_MDC_CLK_OUT 36D2> 19B6< 39C8< VREG_CPU_PWM2 50C2> 51B7<
    MD_CKE 15C1> 26B8< 27B8< MII_MDIO 19B6<> 36C6<> 39B8<> VREG_CPU_PWM3 50C2> 51D7<
    MD_CLK0_DN 15C1> 26C8< MII_RXD0 19B7> 39C7> 36C6< VREG_CPU_PWRGD 50C2> 34C1<
    MD_CLK0_DP 15C1> 26D8< MII_RXD1 19B6> 39C7> 36C6< VREG_CPU_VID<5..0> 49C2> 50C2<
    MD_CLK1_DN 15C1> 27C8< MII_RXD2 19B6> 39C7> 36C6< VREG_EFUSE_EN 4D2> 55C6<
    MD_CLK1_DP 15D1> 27D8< MII_RXD3 19C6> 39C7> 36C6< VREG_GPU_5VREF 52C3> 52C6<

    PROJECT NAME PAGE REV


    MICROSOFT
    XENON_RETAIL 66/73 K7
    CONFIDENTIAL
    *** Part Cross-Reference for the entire design *** C1R4 CAPN 47 C2P13 CAPN 38 C3C3 CAPN 46
    C1T1 CAPN 47 C2P14 CAPN 38 C3C4 CAPN 46
    C1A2 CAPN 44 C1T2 CAPN 47 C2P15 CAPN 38 C3C5 CAPN 24
    C1A3 CAPN 44 C1T3 CAPN 47 C2P16 CAPN 38 C3D1 CAPN 26
    C1A4 CAPN 44 C1T4 CAPN 47 C2P17 CAPN 38 C3D2 CAPN 26
    C1A5 CAP_P 39 C1T5 CAPN 47 C2P18 CAPN 33 C3D3 CAPN 25
    C1B1 CAPN 39 C1T6 CAPN 53 C2P19 CAPN 38 C3D4 CAPN 26
    C1B2 CAPN 32 C1U1 CAPN 55 C2P20 CAPN 38 C3D5 CAPN 26
    C1B3 CAPN 32 C1U2 CAPN 45 C2P21 CAPN 38 C3D6 CAPN 26
    C1B4 CAPN 28 C2A1 CAPN 43 C2P22 CAPN 38 C3E1 CAPN 24
    C1C1 CAPN 32 C2A2 CAPN 43 C2P23 CAPN 37 C3E2 CAPN 24
    C1C2 CAPN 33 C2A3 CAPN 43 C2P24 CAPN 37 C3E3 CAPN 24
    C1C3 CAPN 47 C2A4 CAP_P 44 C2P25 CAPN 33 C3E4 CAPN 27
    C1C4 CAPN 47 C2A5 CAPN 43 C2P26 CAPN 38 C3E5 CAPN 24
    C1C5 CAPN 47 C2A6 CAPN 43 C2P27 CAPN 38 C3E6 CAPN 24
    C1C6 CAPN 47 C2A7 CAPN 40 C2P28 CAPN 38 C3E7 CAPN 24
    C1C7 CAPN 32 C2A8 CAPN 43 C2P29 CAPN 38 C3E8 CAPN 27
    C1C8 CAPN 32 C2B1 CAPN 40 C2P30 CAPN 38 C3F1 CAPN 20
    C1C9 CAPN 36 C2B2 CAPN 40 C2P31 CAPN 38 C3F2 CAP_P 54
    C1C10 CAP_P 47 C2B3 CAPN 40 C2P32 CAPN 38 C3F3 CAPN 20
    C1C11 CAP_P 47 C2B4 CAPN 40 C2P33 CAPN 38 C3F5 CAPN 27
    C1C12 CAPN 32 C2B5 CAPN 40 C2P34 CAPN 37 C3F6 CAPN 54
    C1C13 CAPN 47 C2B6 CAPN 40 C2P35 CAPN 37 C3G3 CAPN 32
    C1C14 CAPN 47 C2B7 CAPN 40 C2P37 CAPN 37 C3M1 CAPN 42
    C1C15 CAPN 32 C2B8 CAPN 40 C2P38 CAPN 37 C3N1 CAPN 32
    C1D1 CAPN 47 C2B9 CAPN 40 C2P39 CAPN 38 C3N2 CAPN 32
    C1D2 CAPN 38 C2B10 CAPN 40 C2P40 CAPN 35 C3N3 CAPN 46
    C1D3 CAPN 47 C2B11 CAPN 40 C2P41 CAPN 37 C3N4 CAPN 35
    C1D4 CAPN 47 C2B12 CAPN 56 C2P42 CAPN 37 C3N8 CAPN 46
    C1D6 CAPN 47 C2B13 CAPN 56 C2P43 CAPN 37 C3N9 CAPN 46
    C1D7 CAPN 56 C2B14 CAPN 28 C2P44 CAPN 37 C3N10 CAPN 29
    C1D8 CAPN 32 C2B15 CAPN 56 C2P45 CAPN 37 C3P1 CAPN 46
    C1D9 CAP_P 47 C2B16 CAPN 33 C2P46 CAPN 37 C3P2 CAPN 46
    C1D10 CAPN 32 C2B17 CAPN 28 C2P47 CAPN 37 C3P4 CAPN 46
    C1D11 CAP_P 46 C2C1 CAPN 33 C2P48 CAPN 37 C3P5 CAPN 46
    C1E1 CAPN 47 C2C2 CAPN 33 C2P50 CAPN 29 C3P6 CAPN 46
    C1E2 CAPN 47 C2C3 CAPN 33 C2P51 CAPN 34 C3P7 CAPN 46
    C1E3 CAPN 47 C2C4 CAPN 33 C2P52 CAPN 38 C3P8 CAPN 46
    C1E4 CAPN 47 C2C5 CAPN 55 C2R1 CAPN 29 C3R1 CAPN 27
    C1E5 CAP_P 47 C2C6 CAPN 55 C2R2 CAPN 29 C3R2 CAPN 27
    C1F1 CAPN 32 C2D1 CAPN 26 C2R3 CAPN 37 C3R3 CAPN 26
    C1F2 CAPN 32 C2D2 CAPN 26 C2R4 CAPN 53 C3R4 CAPN 27
    C1F3 CAP_P 55 C2D3 CAPN 24 C2R5 CAPN 37 C3R5 CAPN 15
    C1F4 CAP_P 45 C2D4 CAPN 26 C2R6 CAPN 37 C3R6 CAPN 27
    C1F5 CAPN 55 C2D5 CAPN 12 C2R7 CAPN 27 C3R7 CAPN 27
    C1F6 CAPN 45 C2D6 CAP_P 53 C2R8 CAPN 27 C3T1 CAPN 25
    C1G1 CAPN 32 C2E1 CAPN 24 C2R9 CAPN 24 C3T2 CAPN 25
    C1M1 CAPN 44 C2E2 CAPN 26 C2R10 CAPN 27 C3T3 CAPN 25
    C1M2 CAPN 44 C2E3 CAPN 24 C2R11 CAPN 41 C3T4 CAPN 25
    C1N1 CAPN 39 C2E4 CAPN 12 C2R12 CAPN 12 C3T5 CAPN 25
    C1N2 CAPN 39 C2E5 CAPN 41 C2R13 CAPN 27 C3T6 CAPN 25
    C1N3 CAPN 39 C2E6 CAPN 41 C2T1 CAPN 25 C3T7 CAPN 25
    C1N4 CAPN 39 C2E7 CAP_P 53 C2T2 CAPN 26 C3U1 CAPN 21
    C1N5 CAPN 39 C2E8 CAPN 24 C2T3 CAPN 25 C3U2 CAPN 21
    C1N6 CAPN 19 C2F2 CAPN 32 C2T4 CAPN 32 C3U3 CAPN 32
    C1N7 CAPN 19 C2F3 CAP_P 54 C2T5 CAPN 53 C3U4 CAPN 27
    C1N8 CAPN 19 C2G1 CAPN 32 C2T6 CAPN 27 C3U5 CAPN 54
    C1N9 CAPN 39 C2G2 CAP_P 45 C2T7 CAPN 27 C3U6 CAPN 54
    C1N10 CAPN 39 C2G3 CAPN 45 C2V1 CAPN 42 C3V1 CAPN 54
    C1N11 CAPN 39 C2M1 CAPN 43 C2V2 CAPN 42 C3V2 CAPN 54
    C1N12 CAPN 32 C2M2 CAPN 43 C3A1 CAPN 43 C3V3 CAPN 54
    C1N13 CAPN 32 C2M3 CAPN 43 C3A2 CAPN 43 C3V4 CAPN 54
    C1N14 CAPN 19 C2M4 CAPN 43 C3A3 CAPN 43 C3V5 CAPN 45
    C1P1 CAPN 38 C2M5 CAPN 43 C3A4 CAPN 43 C3V6 CAPN 54
    C1P2 CAPN 38 C2N1 CAPN 37 C3A5 CAPN 43 C3V7 CAPN 54
    C1P3 CAPN 38 C2N2 CAPN 35 C3A6 CAPN 43 C4B3 CAPN 29
    C1P4 CAPN 38 C2P1 CAPN 38 C3A7 CAPN 42 C4B4 CAPN 30
    C1P5 CAPN 38 C2P2 CAPN 37 C3B3 CAPN 30 C4B5 CAPN 30
    C1P6 CAPN 38 C2P3 CAPN 37 C3B4 CAPN 46 C4B6 CAPN 30
    C1P7 CAPN 38 C2P4 CAPN 38 C3B5 CAPN 56 C4B7 CAPN 30
    C1P8 CAPN 38 C2P5 CAPN 37 C3B8 CAPN 30 C4B8 CAPN 32
    C1P10 CAPN 38 C2P6 CAPN 37 C3B9 CAPN 30 C4B9 CAPN 30
    C1P11 CAPN 38 C2P8 CAPN 37 C3B12 CAPN 28 C4C3 CAPN 30
    C1P13 CAPN 29 C2P9 CAPN 38 C3B13 CAPN 46 C4C4 CAPN 30
    C1R1 CAPN 47 C2P10 CAPN 38 C3B14 CAPN 46 C4C5 CAPN 30
    C1R2 CAPN 56 C2P11 CAPN 38 C3C1 CAPN 55 C4C6 CAPN 55
    C1R3 CAPN 46 C2P12 CAPN 38 C3C2 CAPN 13 C4D1 CAPN 13

    PROJECT NAME PAGE REV


    MICROSOFT
    XENON_RETAIL 67/73 K7
    CONFIDENTIAL
    C4D2 CAPN 13 C4R16 CAPN 18 C4T24 CAPN 18 C5R2 CAPN 18
    C4D3 CAPN 13 C4R17 CAPN 18 C4T25 CAPN 18 C5R3 CAPN 18
    C4D4 CAPN 16 C4R18 CAPN 18 C4T26 CAPN 18 C5R4 CAPN 18
    C4D5 CAPN 16 C4R19 CAPN 15 C4T27 CAPN 14 C5R5 CAPN 18
    C4D6 CAPN 16 C4R20 CAPN 18 C4T28 CAPN 15 C5R6 CAPN 18
    C4F1 CAPN 20 C4R21 CAPN 18 C4T29 CAPN 14 C5R7 CAPN 16
    C4F2 CAPN 21 C4R22 CAPN 18 C4T30 CAPN 16 C5R8 CAPN 18
    C4F3 CAPN 20 C4R23 CAPN 15 C4T31 CAPN 14 C5R9 CAPN 18
    C4F4 CAPN 22 C4R24 CAPN 18 C4T32 CAPN 14 C5R10 CAPN 18
    C4F5 CAPN 22 C4R25 CAPN 15 C4T33 CAPN 14 C5R11 CAPN 18
    C4F6 CAPN 20 C4R26 CAPN 13 C4T34 CAPN 14 C5R12 CAPN 18
    C4F7 CAPN 20 C4R27 CAPN 12 C4T35 CAPN 14 C5R13 CAPN 16
    C4F8 CAPN 22 C4R28 CAPN 18 C4T36 CAPN 15 C5R14 CAPN 18
    C4F9 CAPN 20 C4R29 CAPN 18 C4T37 CAPN 16 C5R15 CAPN 16
    C4F10 CAPN 22 C4R30 CAPN 18 C4T38 CAPN 15 C5R16 CAPN 18
    C4F11 CAPN 20 C4R31 CAPN 15 C4T39 CAPN 14 C5R17 CAPN 18
    C4F12 CAPN 20 C4R32 CAPN 15 C4T40 CAPN 14 C5R18 CAPN 12
    C4F13 CAPN 32 C4R33 CAPN 12 C4T41 CAPN 14 C5R19 CAPN 16
    C4F14 CAPN 27 C4R34 CAPN 18 C4T42 CAPN 14 C5R20 CAPN 18
    C4F15 CAPN 27 C4R35 CAPN 18 C4T43 CAPN 14 C5T1 CAPN 14
    C4G1 CAPN 54 C4R36 CAPN 18 C4T44 CAPN 14 C5T2 CAPN 14
    C4N1 CAPN 32 C4R37 CAPN 18 C4T45 CAPN 14 C5T3 CAPN 14
    C4N2 CAPN 30 C4R38 CAPN 15 C4T46 CAPN 14 C5T4 CAPN 14
    C4N3 CAPN 30 C4R39 CAPN 18 C4T47 CAPN 14 C5U1 CAPN 23
    C4N4 CAPN 30 C4R40 CAPN 18 C4T48 CAPN 16 C5U2 CAPN 23
    C4N5 CAPN 30 C4R41 CAPN 18 C4U1 CAPN 21 C5U3 CAPN 23
    C4N6 CAPN 30 C4R42 CAPN 18 C4U2 CAPN 21 C5U4 CAPN 23
    C4N7 CAPN 30 C4R43 CAPN 18 C4U3 CAPN 23 C5U5 CAPN 22
    C4N8 CAPN 30 C4R44 CAPN 18 C4U4 CAPN 23 C5V1 CAPN 32
    C4N9 CAPN 30 C4R45 CAPN 12 C4U5 CAPN 21 C6B1 CAPN 32
    C4N10 CAPN 30 C4R46 CAPN 18 C4U6 CAPN 21 C6B2 CAPN 53
    C4N11 CAPN 30 C4R47 CAPN 18 C4U7 CAPN 23 C6B3 CAP_P 49
    C4N12 CAPN 30 C4R48 CAPN 15 C4U8 CAPN 21 C6B4 CAPN 53
    C4N13 CAPN 30 C4R49 CAPN 18 C4U9 CAPN 20 C6B5 CAPN 49
    C4N14 CAPN 30 C4R50 CAPN 15 C4U10 CAPN 23 C6C1 CAP_P 49
    C4N15 CAPN 30 C4R51 CAPN 15 C4U11 CAPN 21 C6C2 CAP_P 49
    C4N16 CAPN 30 C4R52 CAPN 18 C4U12 CAPN 27 C6C3 CAP_P 49
    C4N17 CAPN 30 C4R53 CAPN 18 C4V2 CAPN 54 C6D1 CAPN 6
    C4N18 CAPN 30 C4R54 CAPN 18 C4V3 CAPN 54 C6D4 CAPN 6
    C4N19 CAPN 30 C4R55 CAPN 18 C4V4 CAPN 54 C6E1 CAPN 18
    C4N20 CAPN 42 C4R56 CAPN 18 C4V5 CAPN 54 C6E2 CAPN 18
    C4N21 CAPN 30 C4R57 CAPN 18 C4V6 CAPN 45 C6F1 CAPN 4
    C4N22 CAPN 30 C4R58 CAPN 18 C5B1 CAPN 55 C6F3 CAP_P 54
    C4N23 CAPN 30 C4R59 CAPN 18 C5B2 CAP_P 55 C6F7 CAPN 54
    C4N24 CAPN 29 C4R60 CAPN 12 C5B3 CAPN 55 C6G1 CAPN 54
    C4N25 CAPN 42 C4R61 CAPN 15 C5B4 CAP_P 55 C6G2 CAPN 48
    C4N26 CAPN 30 C4R62 CAPN 18 C5B5 CAPN 55 C6G3 CAPN 48
    C4N27 CAPN 32 C4R63 CAPN 18 C5B6 CAPN 55 C6G4 CAPN 48
    C4N28 CAPN 28 C4R64 CAPN 15 C5B7 CAP_P 48 C6G5 CAP_P 48
    C4P1 CAPN 30 C4R65 CAPN 12 C5C3 CAPN 13 C6N1 CAPN 32
    C4P2 CAPN 29 C4R66 CAPN 15 C5C4 CAP_P 49 C6N2 CAPN 49
    C4P3 CAPN 30 C4R67 CAPN 18 C5C5 CAPN 55 C6P1 CAPN 55
    C4P4 CAPN 30 C4R68 CAPN 16 C5C6 CAPN 29 C6R1 CAPN 55
    C4P5 CAPN 30 C4R69 CAPN 18 C5D1 CAPN 13 C6R2 CAPN 6
    C4P6 CAPN 28 C4T1 CAPN 18 C5D2 CAPN 18 C6R3 CAPN 6
    C4P7 CAPN 30 C4T2 CAPN 18 C5D3 CAPN 18 C6R4 CAPN 6
    C4P8 CAPN 30 C4T3 CAPN 18 C5D4 CAPN 18 C6R5 CAPN 6
    C4P9 CAPN 30 C4T4 CAPN 18 C5D5 CAPN 18 C6R6 CAPN 5
    C4P10 CAPN 30 C4T5 CAPN 18 C5D6 CAPN 18 C6R7 CAPN 11
    C4P11 CAPN 30 C4T6 CAPN 18 C5E1 CAPN 14 C6R8 CAPN 11
    C4P12 CAPN 29 C4T7 CAPN 15 C5F1 CAPN 23 C6R9 CAPN 11
    C4P13 CAPN 30 C4T8 CAPN 18 C5F2 CAPN 22 C6R10 CAPN 11
    C4R1 CAPN 13 C4T9 CAPN 18 C5F3 CAPN 22 C6R11 CAPN 10
    C4R2 CAPN 13 C4T10 CAPN 18 C5F4 CAPN 22 C6R12 CAPN 11
    C4R3 CAPN 14 C4T11 CAPN 18 C5F5 CAPN 22 C6R13 CAPN 11
    C4R4 CAPN 16 C4T12 CAPN 15 C5F6 CAPN 22 C6R14 CAPN 5
    C4R5 CAPN 16 C4T13 CAPN 12 C5F8 CAP_P 54 C6R15 CAPN 11
    C4R6 CAPN 16 C4T14 CAPN 15 C5G1 CAPN 32 C6R16 CAPN 10
    C4R7 CAPN 16 C4T15 CAPN 18 C5G2 CAPN 54 C6R17 CAPN 10
    C4R8 CAPN 16 C4T16 CAPN 18 C5G3 CAPN 32 C6R18 CAPN 10
    C4R9 CAPN 18 C4T17 CAPN 18 C5G4 CAP_P 45 C6R19 CAPN 10
    C4R10 CAPN 15 C4T18 CAPN 18 C5G5 CAPN 32 C6R20 CAPN 10
    C4R11 CAPN 18 C4T19 CAPN 18 C5G6 CAPN 45 C6R21 CAPN 10
    C4R12 CAPN 15 C4T20 CAPN 18 C5N1 CAPN 32 C6R22 CAPN 10
    C4R13 CAPN 18 C4T21 CAPN 18 C5N2 CAPN 32 C6R23 CAPN 10
    C4R14 CAPN 18 C4T22 CAPN 12 C5P1 CAPN 55 C6R24 CAPN 11
    C4R15 CAPN 15 C4T23 CAPN 18 C5R1 CAPN 18 C6R25 CAPN 5

    PROJECT NAME PAGE REV


    MICROSOFT
    XENON_RETAIL 68/73 K7
    CONFIDENTIAL
    C6R26 CAPN 11 C7D8 CAPN 9 C7R36 CAPN 10 C7R114 CAPN 6
    C6R27 CAPN 10 C7D9 CAPN 9 C7R37 CAPN 10 C7R115 CAPN 6
    C6R28 CAPN 10 C7D10 CAPN 9 C7R38 CAPN 10 C7R116 CAPN 6
    C6R29 CAPN 10 C7D11 CAPN 9 C7R39 CAPN 11 C7R117 CAPN 9
    C6R30 CAPN 10 C7D12 CAPN 9 C7R40 CAPN 11 C7R118 CAPN 9
    C6R31 CAPN 10 C7D13 CAPN 9 C7R41 CAPN 11 C7R119 CAPN 9
    C6R32 CAPN 10 C7D14 CAPN 9 C7R42 CAPN 11 C7R120 CAPN 9
    C6R33 CAPN 10 C7D15 CAPN 9 C7R43 CAPN 10 C7R121 CAPN 9
    C6R34 CAPN 10 C7D16 CAPN 9 C7R44 CAPN 10 C7R122 CAPN 9
    C6R35 CAPN 10 C7D17 CAPN 9 C7R45 CAPN 10 C7T1 CAPN 9
    C6R36 CAPN 10 C7D18 CAPN 9 C7R46 CAPN 10 C7T2 CAPN 10
    C6R37 CAPN 5 C7D19 CAPN 9 C7R47 CAPN 10 C7T3 CAPN 10
    C6R38 CAPN 10 C7D20 CAPN 9 C7R48 CAPN 10 C7T4 CAPN 11
    C6R39 CAPN 10 C7D21 CAPN 9 C7R49 CAPN 10 C7T5 CAPN 10
    C6R40 CAPN 10 C7D22 CAPN 9 C7R50 CAPN 10 C7T8 CAPN 10
    C6R41 CAPN 11 C7D23 CAPN 56 C7R51 CAPN 10 C7T9 CAPN 10
    C6R42 CAPN 10 C7E1 CAPN 9 C7R52 CAPN 10 C7T10 CAPN 10
    C6R43 CAPN 10 C7E2 CAPN 9 C7R53 CAPN 10 C7T11 CAPN 11
    C6R44 CAPN 10 C7E3 CAPN 9 C7R54 CAPN 10 C7T12 CAPN 11
    C6R45 CAPN 10 C7E4 CAPN 9 C7R55 CAPN 10 C7T13 CAPN 11
    C6R46 CAPN 4 C7E5 CAPN 9 C7R56 CAPN 11 C7T14 CAPN 11
    C6R47 CAPN 18 C7E6 CAPN 9 C7R57 CAPN 10 C7T15 CAPN 10
    C6T1 CAPN 10 C7E7 CAPN 9 C7R58 CAPN 10 C7T16 CAPN 11
    C6T2 CAPN 10 C7E8 CAPN 9 C7R59 CAPN 10 C7T17 CAPN 11
    C6T3 CAPN 11 C7E9 CAPN 9 C7R60 CAPN 10 C7T18 CAPN 11
    C6T4 CAPN 10 C7E10 CAPN 9 C7R61 CAPN 10 C7T19 CAPN 10
    C6T5 CAPN 10 C7E11 CAPN 9 C7R62 CAPN 10 C7T20 CAPN 10
    C6T6 CAPN 10 C7E12 CAPN 9 C7R63 CAPN 10 C7T21 CAPN 10
    C6T7 CAPN 5 C7E13 CAPN 49 C7R64 CAPN 10 C7T22 CAPN 10
    C6T8 CAPN 11 C7E14 CAPN 9 C7R65 CAPN 11 C7T23 CAPN 11
    C6T9 CAPN 11 C7E15 CAPN 9 C7R66 CAPN 10 C7T24 CAPN 11
    C6T10 CAPN 10 C7E16 CAPN 9 C7R67 CAPN 10 C7T25 CAPN 11
    C6T11 CAPN 11 C7F1 CAP_P 54 C7R68 CAPN 10 C7T26 CAPN 11
    C6T12 CAPN 11 C7F2 CAP_P 54 C7R69 CAPN 10 C7T27 CAPN 10
    C6T13 CAPN 11 C7G1 CAP_P 50 C7R70 CAPN 10 C7T28 CAPN 11
    C6T14 CAPN 11 C7G2 CAPN 32 C7R71 CAPN 10 C7T29 CAPN 11
    C6T15 CAPN 11 C7G3 CAPN 56 C7R72 CAPN 10 C7T30 CAPN 11
    C6T16 CAPN 11 C7G4 CAPN 56 C7R73 CAPN 11 C7T31 CAPN 11
    C6T17 CAPN 11 C7N1 CAPN 32 C7R74 CAPN 10 C7T32 CAPN 9
    C6T18 CAPN 11 C7N2 CAPN 32 C7R75 CAPN 11 C7T33 CAPN 9
    C6T19 CAPN 5 C7N3 CAPN 49 C7R76 CAPN 10 C7T34 CAPN 9
    C6T20 CAPN 11 C7P1 CAPN 55 C7R77 CAPN 10 C7T35 CAPN 9
    C6T21 CAPN 11 C7R1 CAPN 6 C7R78 CAPN 10 C7T36 CAPN 9
    C6T22 CAPN 11 C7R2 CAPN 9 C7R79 CAPN 10 C7T37 CAPN 10
    C6T23 CAPN 10 C7R3 CAPN 9 C7R80 CAPN 10 C7T38 CAPN 11
    C6T24 CAPN 11 C7R4 CAPN 9 C7R81 CAPN 10 C7T39 CAPN 11
    C6T25 CAPN 10 C7R5 CAPN 9 C7R82 CAPN 11 C7T40 CAPN 11
    C6T26 CAPN 10 C7R6 CAPN 9 C7R83 CAPN 11 C7T41 CAPN 11
    C6T27 CAPN 5 C7R7 CAPN 6 C7R84 CAPN 10 C7T42 CAPN 11
    C6T28 CAPN 11 C7R8 CAPN 11 C7R85 CAPN 11 C7T43 CAPN 11
    C6T29 CAPN 11 C7R9 CAPN 11 C7R86 CAPN 11 C7T44 CAPN 11
    C6T30 CAPN 11 C7R10 CAPN 9 C7R88 CAPN 10 C7T45 CAPN 9
    C6T31 CAPN 57 C7R11 CAPN 9 C7R89 CAPN 10 C7T46 CAPN 11
    C6T32 CAPN 5 C7R12 CAPN 9 C7R90 CAPN 9 C7T47 CAPN 11
    C6T33 CAPN 5 C7R13 CAPN 9 C7R91 CAPN 9 C7T48 CAPN 11
    C6T34 CAPN 57 C7R14 CAPN 11 C7R92 CAPN 9 C7T49 CAPN 11
    C6T35 CAPN 57 C7R15 CAPN 11 C7R93 CAPN 9 C7T50 CAPN 11
    C6T36 CAPN 57 C7R16 CAPN 9 C7R94 CAPN 9 C7T51 CAPN 11
    C6U1 CAPN 54 C7R17 CAPN 11 C7R95 CAPN 11 C7T52 CAPN 11
    C6V1 CAPN 54 C7R18 CAPN 11 C7R96 CAPN 11 C7T53 CAPN 11
    C6V10 CAPN 48 C7R19 CAPN 10 C7R97 CAPN 11 C7T54 CAPN 11
    C6V11 CAPN 48 C7R20 CAPN 11 C7R98 CAPN 11 C7T55 CAPN 11
    C6V12 CAPN 48 C7R21 CAPN 11 C7R99 CAPN 10 C7T56 CAPN 11
    C6V15 CAPN 48 C7R22 CAPN 10 C7R100 CAPN 10 C7T57 CAPN 11
    C7B1 CAPN 32 C7R23 CAPN 10 C7R101 CAPN 11 C7T58 CAPN 11
    C7B2 CAPN 53 C7R24 CAPN 10 C7R102 CAPN 10 C7T59 CAPN 11
    C7B3 CAP_P 49 C7R25 CAPN 10 C7R103 CAPN 11 C7T60 CAPN 11
    C7B4 CAPN 49 C7R26 CAPN 9 C7R104 CAPN 11 C7T61 CAPN 11
    C7C1 CAP_P 49 C7R27 CAPN 9 C7R105 CAPN 11 C7T62 CAPN 11
    C7C2 CAP_P 49 C7R28 CAPN 9 C7R106 CAPN 11 C7T63 CAPN 11
    C7D1 CAPN 6 C7R29 CAPN 9 C7R107 CAPN 11 C7T64 CAPN 11
    C7D2 CAPN 6 C7R30 CAPN 9 C7R108 CAPN 11 C7T65 CAPN 11
    C7D3 CAPN 9 C7R31 CAPN 11 C7R109 CAPN 11 C7T66 CAPN 11
    C7D4 CAPN 9 C7R32 CAPN 11 C7R110 CAPN 10 C7T67 CAPN 11
    C7D5 CAPN 9 C7R33 CAPN 11 C7R111 CAPN 10 C7T68 CAPN 11
    C7D6 CAPN 9 C7R34 CAPN 10 C7R112 CAPN 4 C7T69 CAPN 10
    C7D7 CAPN 9 C7R35 CAPN 10 C7R113 CAPN 4 C7T70 CAPN 10

    PROJECT NAME PAGE REV


    MICROSOFT
    XENON_RETAIL 69/73 K7
    CONFIDENTIAL
    C7T71 CAPN 10 C9B1 CAP_P 48 DB1N1 DBPAD 19 FB2A1 FERRITE 40
    C7T72 CAPN 10 C9B2 CAPN 49 DB1N3 DBPAD 39 FB2A2 FERRITE 40
    C7T73 CAPN 10 C9B3 CAPN 52 DB1N4 DBPAD 39 FB2N1 FERRITE 35
    C7T74 CAPN 10 C9B4 CAPN 49 DB1N5 DBPAD 33 FB2P1 FERRITE 37
    C7T75 CAPN 10 C9C1 CAP_P 49 DB1P1 DBPAD 33 FB2P2 FERRITE 38
    C7T76 CAPN 9 C9C2 CAPN 52 DB1P2 DBPAD 33 FB2P3 FERRITE 37
    C7T77 CAPN 9 C9C3 CAPN 49 DB2N3 DBPAD 33 FB2P4 FERRITE 37
    C7T78 CAPN 9 C9C4 CAP_P 49 DB2N4 DBPAD 33 FB2P5 FERRITE 37
    C7T79 CAPN 9 C9C5 CAPN 51 DB2N5 DBPAD 33 FB2R1 FERRITE 37
    C7T80 CAPN 11 C9C7 CAPN 32 DB2N6 DBPAD 33 FB3B2 FERRITE 30
    C7T81 CAPN 10 C9D1 CAPN 51 DB2N7 DBPAD 33 FB3P1 FERRITE 46
    C7T82 CAPN 10 C9D2 CAP_P 49 DB2N8 DBPAD 33 FB3P2 FERRITE 46
    C7T83 CAPN 9 C9D3 CAPN 51 DB2N9 DBPAD 33 FB4C2 FERRITE 30
    C7T84 CAPN 9 C9D4 CAPN 51 DB2N10 DBPAD 33 FB4D1 FERRITE 16
    C7T85 CAPN 9 C9E1 CAPN 51 DB2N11 DBPAD 33 FB4N1 FERRITE 30
    C7T86 CAPN 9 C9E2 CAPN 32 DB2N12 DBPAD 33 FB4N2 FERRITE 30
    C7T87 CAPN 9 C9E3 CAP_P 49 DB2P1 DBPAD 33 FB4N3 FERRITE 30
    C7T88 CAPN 9 C9E4 CAPN 51 DB2P2 DBPAD 33 FB4N4 FERRITE 30
    C7T89 CAPN 57 C9F1 CAPN 51 DB2P3 DBPAD 33 FB4P1 FERRITE 30
    C7T90 CAPN 57 C9F2 CAPN 32 DB2P4 DBPAD 33 FB4R1 FERRITE 16
    C7T91 CAPN 57 C9F3 CAPN 51 DB2P5 DBPAD 33 FB4T1 FERRITE 16
    C7T92 CAPN 57 C9F4 CAPN 51 DB2P6 DBPAD 33 FB5G1 FERRITE 45
    C7T93 CAPN 9 C9G1 CAPN 45 DB2P7 DBPAD 33 FB5R1 FERRITE 16
    C7T94 CAPN 9 C9G2 CAP_P 45 DB2P8 DBPAD 34 FB6D1 FERRITE 6
    C7T95 CAPN 9 C9G3 CAP_P 45 DB2P9 DBPAD 34 FB6R1 FERRITE 6
    C7T96 CAPN 9 C9G4 CAPN 45 DB2P15 DBPAD 33 FB6R2 FERRITE 6
    C7T97 CAPN 9 C9N1 CAPN 32 DB3B1 DBPAD 28 FB7D1 FERRITE 6
    C7T98 CAPN 55 C9P1 CAPN 52 DB3B2 DBPAD 28 FB7R1 FERRITE 6
    C7T99 CAPN 55 C9P2 CAPN 51 DB3B3 DBPAD 28 FT1N1 FTPAD 33
    C7T100 CAPN 55 C9P3 CAPN 51 DB3B4 DBPAD 28 FT1N2 FTPAD 44
    C7T101 CAPN 9 C9P4 CAPN 51 DB3C1 DBPAD 28 FT1P1 FTPAD 46
    C7U1 CAPN 50 C9T1 CAPN 51 DB3C2 DBPAD 28 FT1P2 FTPAD 46
    C7U2 CAPN 50 C9T2 CAPN 51 DB3C3 DBPAD 28 FT1R1 FTPAD 46
    C7U3 CAPN 50 C9T3 CAPN 51 DB3C4 DBPAD 28 FT1R2 FTPAD 46
    C7U4 CAPN 50 C9U1 CAPN 51 DB3F1 DBPAD 54 FT1R3 FTPAD 41
    C7V1 CAPN 50 C9U2 CAPN 51 DB3N2 DBPAD 28 FT1R4 FTPAD 41
    C7V2 CAPN 54 C9U3 CAPN 51 DB3N3 DBPAD 28 FT1R5 FTPAD 41
    C8A1 CAPN 48 C9V3 CAPN 45 DB4D1 DBPAD 13 FT1T1 FTPAD 41
    C8A2 CAPN 48 CR1D1 MBT3904DUAL 46 DB4N4 DBPAD 28 FT1U1 FTPAD 55
    C8B1 CAP_P 48 CR1D2 DIOSOT23S 47 DB4P1 DBPAD 29 FT1U2 FTPAD 34
    C8B2 CAPN 49 CR1D3 DIOSOT23S 47 DB4P2 DBPAD 29 FT1V1 FTPAD 45
    C8B3 CAPN 52 CR2A1 MBT3904DUAL 43 DB4P3 DBPAD 29 FT2M1 FTPAD 40
    C8B4 CAPN 49 CR2N1 MBT3904DUAL 40 DB5P1 DBPAD 29 FT2N1 FTPAD 40
    C8B6 CAPN 53 CR4N1 DIOSOT23S 55 DB5P2 DBPAD 29 FT2N2 FTPAD 40
    C8B7 CAPN 52 CR4P2 DIOSOT23S 55 DB6E1 DBPAD 31 FT2N3 FTPAD 28
    C8B8 CAPN 52 CR6T1 MBT3904DUAL 55 DB6E2 DBPAD 31 FT2N4 FTPAD 46
    C8C1 CAP_P 49 D1A1 DIOSOT23S 44 DB6E3 DBPAD 31 FT2P1 FTPAD 40
    C8D1 CAP_P 49 D1A2 DIOSOT23S 44 DB6G1 DBPAD 54 FT2P2 FTPAD 28
    C8D4 CAP_P 49 D1B1 DIOSOT23S 44 DB7R1 DBPAD 4 FT2P3 FTPAD 52
    C8E3 CAP_P 49 D1E1 DIOSOT23S 47 DB7U3 DBPAD 50 FT2P4 FTPAD 28
    C8E8 CAP_P 49 D1E2 DIOSOT23S 47 DB8M1 DBPAD 48 FT2P5 FTPAD 34
    C8F1 CAP_P 49 D1E3 DIOSOT23S 47 DB8M2 DBPAD 48 FT2P6 FTPAD 52
    C8F2 CAP_P 49 D1E4 DIOSOT23S 47 DB8M3 DBPAD 48 FT2P7 FTPAD 28
    C8F3 CAP_P 49 D2A1 DIOSOT23S 43 DB8P1 DBPAD 49 FT2P8 FTPAD 35
    C8G1 CAPN 50 D2A2 DIOSOT23S 43 DB8P2 DBPAD 49 FT2P9 FTPAD 35
    C8G2 CAPN 32 D2M2 DIOSOT23S 35 EG1A1 ESDGUARD 44 FT2P10 FTPAD 34
    C8N1 CAPN 52 D2M3 DIOSOT23S 35 EG1A2 ESDGUARD 44 FT2P11 FTPAD 4
    C8N2 CAPN 52 D3A1 DIODE 42 EG1E1 ESDGUARD 47 FT2P12 FTPAD 4
    C8N3 CAPN 52 D3A2 DIOSOT23S 43 EG1E2 ESDGUARD 47 FT2P13 FTPAD 13
    C8N4 CAPN 52 D3A3 DIOSOT23S 43 EG1E3 ESDGUARD 47 FT2P14 FTPAD 13
    C8N5 CAPN 52 D3A4 DIOSOT23S 43 EG1E4 ESDGUARD 47 FT2P15 FTPAD 34
    C8P1 CAPN 52 D3B1 DIODE 42 EG2B1 ESDGUARD 40 FT2P16 FTPAD 50
    C8P2 CAPN 52 D3M2 DIOSOT23S 43 EG2B2 ESDGUARD 40 FT2P17 FTPAD 50
    C8P3 CAPN 52 D3M3 DIOSOT23S 43 EG2G1 ESDGUARD 45 FT2P18 FTPAD 54
    C8P4 CAPN 52 D4V1 ZENER 54 EG3G1 ESDGUARD 45 FT2P19 FTPAD 54
    C8P5 CAPN 56 D4V2 DIOSOT23S 54 EG4G1 ESDGUARD 45 FT2P20 FTPAD 35
    C8U1 CAPN 50 D8B1 ZENER 52 EG4G2 ESDGUARD 45 FT2P21 FTPAD 35
    C8U2 CAPN 50 D8B2 DIODE 52 EG9G1 ESDGUARD 45 FT2P22 FTPAD 35
    C8U3 CAPN 50 D8B3 DIOSOT23S 52 EG9G2 ESDGUARD 45 FT2P23 FTPAD 35
    C8V1 CAPN 50 D8B4 LED 56 EG9V1 ESDGUARD 45 FT2P24 FTPAD 34
    C8V14 CAPN 45 D9C1 DIODE 51 EG9V2 ESDGUARD 45 FT2P25 FTPAD 34
    C9A1 CAPN 48 D9E1 DIODE 51 FB1B1 FERRITE 39 FT2P26 FTPAD 55
    C9A2 CAPN 48 D9F1 DIODE 51 FB1N1 FERRITE 19 FT2R1 FTPAD 34
    C9A3 CAPN 56 D9G1 DIOSOT23S 45 FB1P1 FERRITE 38 FT2R2 FTPAD 46
    C9A4 CAPN 48 D9G2 DIOSOT23S 45 FB1P2 FERRITE 38 FT2R3 FTPAD 41
    C9A5 CAPN 48 D9V1 DIOSOT23S 45 FB1P3 FERRITE 38 FT2R4 FTPAD 41
    C9A6 CAPN 48 D9V2 DIOSOT23S 45 FB1P4 FERRITE 38 FT2R5 FTPAD 41

    PROJECT NAME PAGE REV


    MICROSOFT
    XENON_RETAIL 70/73 K7
    CONFIDENTIAL
    FT2R6 FTPAD 41 L3A3 INDUCTOR 43 R1B4 RESN 39 R2B16 RESN 34
    FT2R7 FTPAD 41 L4G1 CMCHOKE 45 R1B5 RESN 39 R2B18 RESN 34
    FT2R8 FTPAD 53 L6C1 INDUCTOR 53 R1B6 RESN 39 R2B19 RESN 34
    FT2U1 FTPAD 54 L6F1 INDUCTOR 54 R1B7 RESN 39 R2C3 RESN 55
    FT3N1 FTPAD 28 L6G1 CMCHOKE 48 R1B9 RESN 36 R2D1 RESN 41
    FT3P1 FTPAD 46 L7C1 INDUCTOR 53 R1B10 RESN 36 R2D2 RESN 41
    FT3P2 FTPAD 46 L7F1 INDUCTOR 54 R1B11 RESN 39 R2D3 RESN 41
    FT3P3 FTPAD 34 L8B1 INDUCTOR 49 R1B12 RESN 19 R2D4 RESN 41
    FT3P4 FTPAD 28 L8D1 INDUCTOR 51 R1B13 RESN 39 R2D5 RESN 41
    FT4N1 FTPAD 29 L8E1 INDUCTOR 51 R1C1 RESN 39 R2D6 RESN 41
    FT4N2 FTPAD 28 L8F1 INDUCTOR 51 R1C2 RESN 33 R2D7 RESN 41
    FT4N4 FTPAD 29 L9B1 INDUCTOR 49 R1C3 RESN 36 R2D8 RESN 41
    FT4N5 FTPAD 28 L9G1 CMCHOKE 45 R1C4 RESN 33 R2D9 RESN 13
    FT4P1 FTPAD 28 L9V1 CMCHOKE 45 R1C5 RESN 33 R2D10 RESN 13
    FT4P2 FTPAD 28 LB7G1 LABEL 58 R1C6 RESN 33 R2D11 RESN 12
    FT4P3 FTPAD 28 MTG1B1 STD_MTG_HOLE 58 R1C7 RESN 33 R2D12 RESN 12
    FT5N1 FTPAD 55 MTG1G1 STD_MTG_HOLE 58 R1C8 RESN 36 R2E1 RESN 13
    FT5N2 FTPAD 55 MTG3C1 STD_MTG_HOLE 58 R1D2 RESN 41 R2E2 RESN 13
    FT5R1 FTPAD 55 MTG3E1 STD_MTG_HOLE 58 R1D3 RESN 41 R2E3 RESN 13
    FT5R2 FTPAD 49 MTG5B1 STD_MTG_HOLE 58 R1D4 RESN 41 R2E4 RESN 13
    FT6U1 FTPAD 31 MTG5C1 STD_MTG_HOLE 58 R1D5 RESN 46 R2E5 RESN 12
    FT6U2 FTPAD 31 MTG5E1 STD_MTG_HOLE 58 R1D6 RESN 46 R2F2 RESN 55
    FT6U3 FTPAD 31 MTG5G1 STD_MTG_HOLE 58 R1E2 RESN 41 R2G2 RESN 42
    FT6U4 FTPAD 31 MTG6C1 STD_MTG_HOLE 58 R1F7 RESN 55 R2G3 RESN 42
    FT6U5 FTPAD 31 MTG6E1 STD_MTG_HOLE 58 R1F8 RESN 55 R2G5 RESN 45
    FT6U6 FTPAD 31 MTG8C1 STD_MTG_HOLE 58 R1G1 RESN 46 R2M1 RESN 34
    FT6U7 FTPAD 31 MTG8E1 STD_MTG_HOLE 58 R1G2 RESN 46 R2M2 RESN 43
    FT6U8 FTPAD 31 MTG9B1 STD_MTG_HOLE 58 R1G3 RESN 42 R2M3 RESN 34
    FT6U9 FTPAD 31 MTG9G1 STD_MTG_HOLE 58 R1G4 RESN 42 R2M4 RESN 43
    FT6U10 FTPAD 31 Q1G1 NPN 29 R1M1 RESN 39 R2M5 RESN 34
    FT6U11 FTPAD 31 Q1G2 NPN 46 R1M2 RESN 39 R2M6 RESN 43
    FT6V1 FTPAD 54 Q1G3 PNP 29 R1M3 RESN 44 R2M7 RESN 35
    FT7R1 FTPAD 4 Q1V1 NPN 46 R1N1 RESN 39 R2M8 RESN 35
    FT7R2 FTPAD 4 Q2F2 FET_P 55 R1N2 RESN 39 R2M9 RESN 43
    FT7R3 FTPAD 55 Q2G1 FET_VREG 54 R1N3 RESN 39 R2M10 RESN 43
    FT7R4 FTPAD 4 Q2M1 PNP 43 R1N4 RESN 39 R2M11 RESN 43
    FT7R5 FTPAD 4 Q2N1 PNP 40 R1N5 RESN 39 R2M12 RESN 40
    FT7R6 FTPAD 4 Q2N2 NPN 35 R1N6 RESN 39 R2M13 RESN 40
    FT7R7 FTPAD 56 Q3A1 NPN 42 R1N7 RESN 39 R2N1 RESN 40
    FT7T1 FTPAD 4 Q3A2 PNP_2C 42 R1N8 RESN 19 R2N2 RESN 40
    FT7T2 FTPAD 4 Q3F1 FET_VREG 54 R1P1 RESN 33 R2N3 RESN 40
    FT7T3 FTPAD 4 Q3G1 FET 54 R1P2 RESN 33 R2N4 RESN 33
    FT7T4 FTPAD 4 Q3M1 PNP_2C 42 R1P3 RESN 33 R2N5 RESN 33
    FT7T5 FTPAD 4 Q3M4 NPN 42 R1P5 RESN 33 R2N6 RESN 33
    FT7T6 FTPAD 55 Q4G1 FET 54 R1P6 RESN 33 R2N7 RESN 42
    FT7T7 FTPAD 4 Q6B1 FET_VREG 53 R1P7 RESN 35 R2N8 RESN 33
    FT7T8 FTPAD 55 Q6B2 FET_VREG 53 R1R1 RESN 35 R2N9 RESN 34
    FT7U1 FTPAD 49 Q6C1 FET_VREG 53 R1R2 RESN 46 R2N10 RESN 35
    FT8N1 FTPAD 48 Q6F1 FET_VREG 54 R1R3 RESN 46 R2N11 RESN 35
    FT9N1 FTPAD 48 Q6F2 FET_VREG 54 R1R4 RESN 47 R2N12 RESN 35
    J1A1 XENONRJ45USB 44 Q7B1 FET_VREG 53 R1R5 RESN 46 R2N13 RESN 56
    J1C1 1X7SATA 47 Q7B2 FET_VREG 53 R1V1 RESN 46 R2N14 RESN 56
    J1D1 2X6HDR2 47 Q7C1 FET_VREG 53 R1V2 RESN 46 R2N15 RESN 34
    J1D2 2X5HDR10 56 Q8B3 FET 52 R2A1 RESN 43 R2P1 RESN 28
    J1E1 XENONHDD 47 Q8B4 NPN 48 R2A2 RESN 34 R2P2 RESN 33
    J1F1 1X6HDR 56 Q8B5 NPN 48 R2A3 RESN 43 R2P3 RESN 28
    J2A1 XENONAVIP 43 Q8B6 NPN 56 R2A4 RESN 43 R2P4 RESN 34
    J2B1 2X7HDR14 56 Q8C1 FET_VREG 51 R2A5 RESN 43 R2P5 RESN 33
    J2D1 2X3HDR 33 Q8F1 FET_VREG 51 R2A6 RESN 43 R2P6 RESN 34
    J2D2 2X4HDR 13 Q8N1 PNP_2C 48 R2A7 RESN 43 R2P8 RESN 33
    J3A1 2X2HDR 42 Q9C1 FET_VREG 51 R2A8 RESN 43 R2P9 RESN 33
    J3G1 XENONMU 45 Q9D1 FET_VREG 51 R2A9 RESN 43 R2P10 RESN 34
    J5C1 2X3HDR 28 Q9D2 FET_VREG 51 R2A10 RESN 36 R2P11 RESN 33
    J5C2 2X3HDR 13 Q9D3 FET_VREG 51 R2B1 RESN 40 R2P12 RESN 34
    J6G1 XENONRF 48 Q9D4 FET_VREG 51 R2B2 RESN 40 R2P13 RESN 34
    J7F1 2X3HDR 4 Q9E1 FET_VREG 51 R2B3 RESN 40 R2P14 RESN 35
    J7G1 1X3HDR 56 Q9E3 FET_VREG 51 R2B4 RESN 40 R2P15 RESN 34
    J8C1 2X5HDR 56 Q9F1 FET_VREG 51 R2B5 RESN 40 R2P16 RESN 33
    J9A1 XENONPWR 48 Q9F2 FET_VREG 51 R2B6 RESN 40 R2P17 RESN 38
    J9A2 1X2HDR 56 Q9F4 FET_VREG 51 R2B7 RESN 56 R2P18 RESN 56
    J9G1 XENONGAME 45 R1A1 RESN 39 R2B8 RESN 33 R2R1 RESN 24
    L1B1 CMCHOKE 44 R1A2 RESN 39 R2B9 RESN 33 R2R2 RESN 24
    L2A1 INDUCTOR 43 R1A3 RESN 39 R2B10 RESN 33 R2R3 RESN 25
    L2F1 INDUCTOR 54 R1A4 RESN 39 R2B11 RESN 36 R2R4 RESN 25
    L2G1 CMCHOKE 45 R1A5 RESN 44 R2B12 RESN 36 R2R5 RESN 12
    L3A1 INDUCTOR 43 R1B1 RESN 44 R2B13 RESN 36 R2R6 RESN 12
    L3A2 INDUCTOR 43 R1B2 RESN 44 R2B14 RESN 36 R2T1 RESN 12

    PROJECT NAME PAGE REV


    MICROSOFT
    XENON_RETAIL 71/73 K7
    CONFIDENTIAL
    R2T2 RESN 12 R3R1 RESN 25 R4U1 RESN 23 R7E6 RESN 49
    R2T3 RESN 26 R3T1 RESN 27 R4U2 RESN 21 R7E7 RESN 4
    R2T4 RESN 26 R3T2 RESN 15 R4U3 RESN 21 R7E8 RESN 4
    R2T5 RESN 27 R3U1 RESN 21 R4U4 RESN 20 R7F1 RESN 4
    R2T6 RESN 27 R3U2 RESN 54 R4U5 RESN 20 R7F2 RESN 4
    R2T7 RESN 53 R3V1 RESN 54 R4U6 RESN 12 R7F3 RESN 4
    R2T8 RESN 53 R3V2 RESN 54 R4V1 RESN 54 R7F4 RESN 4
    R2U1 RESN 54 R3V3 RESN 54 R4V2 RESN 54 R7F5 RESN 50
    R2V1 RESN 42 R3V4 RESN 54 R4V3 RESN 54 R7F7 RESN 4
    R2V2 RESN 54 R3V5 RESN 54 R5C1 RESN 28 R7N1 RESN 48
    R3A1 RESN 42 R3V6 RESN 54 R5C2 RESN 28 R7N2 RESN 48
    R3A2 RESN 42 R3V7 RESN 54 R5C3 RESN 28 R7N3 RESN 48
    R3A3 RESN 43 R3V8 RESN 54 R5C4 RESN 55 R7N4 RESN 48
    R3A4 RESN 43 R3V9 RESN 54 R5C5 RESN 13 R7R1 RESN 4
    R3A5 RESN 42 R4B2 RESN 28 R5C6 RESN 55 R7R2 RESN 4
    R3A6 RESN 43 R4B3 RESN 28 R5C8 RESN 13 R7R3 RESN 4
    R3A7 RESN 42 R4B7 RESN 28 R5C9 RESN 55 R7R4 RESN 4
    R3A8 RESN 42 R4B8 RESN 28 R5C10 RESN 13 R7R5 RESN 4
    R3B1 RESN 28 R4B9 RESN 28 R5C11 RESN 12 R7R6 RESN 4
    R3B4 RESN 46 R4B10 RESN 29 R5C12 RESN 12 R7R7 RESN 4
    R3B5 RESN 46 R4B11 RESN 29 R5D1 RESN 13 R7R8 RESN 4
    R3B7 RESN 46 R4B12 RESN 29 R5D2 RESN 13 R7R9 RESN 4
    R3B8 RESN 46 R4B13 RESN 29 R5E1 RESN 14 R7R10 RESN 4
    R3B15 RESN 28 R4B14 RESN 29 R5E2 RESN 14 R7R11 RESN 4
    R3B16 RESN 42 R4B15 RESN 29 R5F1 RESN 23 R7R12 RESN 4
    R3C1 RESN 46 R4B16 RESN 28 R5F2 RESN 23 R7R13 RESN 4
    R3C2 RESN 46 R4B17 RESN 28 R5F3 RESN 22 R7R14 RESN 4
    R3C3 RESN 46 R4C1 RESN 29 R5F4 RESN 22 R7R15 RESN 4
    R3C4 RESN 46 R4C2 RESN 29 R5F5 RESN 54 R7R16 RESN 4
    R3C5 RESN 46 R4C3 RESN 13 R5F6 RESN 54 R7R17 RESN 4
    R3C6 RESN 46 R4C4 RESN 13 R5N1 RESN 52 R7R18 RESN 4
    R3C7 RESN 46 R4C5 RESN 13 R5P1 RESN 55 R7R19 RESN 4
    R3C8 RESN 46 R4C6 RESN 13 R5P2 RESN 55 R7R20 RESN 4
    R3C9 RESN 46 R4C7 RESN 13 R5P3 RESN 13 R7R21 RESN 4
    R3C10 RESN 46 R4D1 RESN 13 R5R1 RESN 12 R7R22 RESN 4
    R3C11 RESN 46 R4D2 RESN 13 R5R2 RESN 12 R7R23 RESN 4
    R3C12 RESN 46 R4D3 RESN 13 R5R3 RESN 12 R7R24 RESN 4
    R3C13 RESN 28 R4D4 RESN 13 R5U1 RESN 23 R7T2 RESN 6
    R3C14 RESN 28 R4F1 RESN 21 R5U2 RESN 23 R7T4 RESN 49
    R3C15 RESN 46 R4F2 RESN 21 R5U3 RESN 22 R7T5 RESN 49
    R3C16 RESN 46 R4F3 RESN 20 R5U4 RESN 22 R7T6 RESN 49
    R3C17 RESN 46 R4F4 RESN 20 R5V2 RESN 42 R7T7 RESN 49
    R3C18 RESN 46 R4F5 RESN 22 R5V3 RESN 42 R7T8 RESN 49
    R3C19 RESN 28 R4F6 RESN 13 R6B3 RESN 53 R7T9 RESN 49
    R3C20 RESN 28 R4F7 RESN 12 R6C1 RESN 55 R7T10 RESN 55
    R3C21 RESN 55 R4F8 RESN 12 R6D1 RESN 4 R7T11 RESN 49
    R3C22 RESN 55 R4G1 RESN 54 R6D2 RESN 4 R7T12 RESN 49
    R3C27 RESN 46 R4G2 RESN 54 R6E1 RESN 4 R7T13 RESN 49
    R3C28 RESN 13 R4G3 RESN 54 R6E2 RESN 4 R7T14 RESN 49
    R3D1 RESN 24 R4G4 RESN 45 R6G1 RESN 54 R7T15 RESN 49
    R3D2 RESN 25 R4G5 RESN 45 R6G7 RESN 48 R7T16 RESN 49
    R3D3 RESN 25 R4G6 RESN 54 R6G8 RESN 48 R7U1 RESN 50
    R3D4 RESN 24 R4N1 RESN 30 R6R1 RESN 55 R7U2 RESN 50
    R3D5 RESN 24 R4N8 RESN 42 R6R2 RESN 55 R7U3 RESN 4
    R3E1 RESN 26 R4P1 RESN 28 R6R3 RESN 55 R7V1 RESN 50
    R3E2 RESN 27 R4P2 RESN 42 R6R4 RESN 4 R7V2 RESN 50
    R3E3 RESN 27 R4P3 RESN 28 R6R5 RESN 4 R7V3 RESN 50
    R3E4 RESN 26 R4P4 RESN 28 R6R6 RESN 4 R7V4 RESN 34
    R3E5 RESN 26 R4P5 RESN 28 R6R7 RESN 4 R7V5 RESN 50
    R3F1 RESN 20 R4P6 RESN 29 R6R8 RESN 4 R7V6 RESN 56
    R3G1 RESN 54 R4P7 RESN 29 R6R9 RESN 4 R7V7 RESN 56
    R3G4 RESN 45 R4R1 RESN 15 R6R10 RESN 4 R8A1 RESN 48
    R3G5 RESN 54 R4R2 RESN 15 R6T1 RESN 55 R8A2 RESN 48
    R3G6 RESN 54 R4R3 RESN 13 R6T3 RESN 55 R8A3 RESN 48
    R3G7 RESN 54 R4R4 RESN 15 R6T4 RESN 55 R8A4 RESN 48
    R3M2 RESN 43 R4R5 RESN 15 R6U1 RESN 54 R8A5 RESN 56
    R3M3 RESN 43 R4R6 RESN 15 R6V1 RESN 54 R8B2 RESN 52
    R3M4 RESN 42 R4R7 RESN 15 R6V2 RESN 54 R8B3 RESN 52
    R3M5 RESN 42 R4R8 RESN 13 R6V3 RESN 54 R8B4 RESN 52
    R3N1 RESN 35 R4T1 RESN 13 R7B2 RESN 48 R8B5 RESN 48
    R3N3 RESN 35 R4T2 RESN 15 R7B6 RESN 53 R8B6 RESN 56
    R3N6 RESN 48 R4T3 RESN 14 R7D1 RESN 4 R8C1 RESN 52
    R3N7 RESN 48 R4T4 RESN 14 R7E1 RESN 49 R8C2 RESN 56
    R3P2 RESN 46 R4T5 RESN 14 R7E2 RESN 49 R8C3 RESN 56
    R3P3 RESN 46 R4T6 RESN 14 R7E3 RESN 49 R8C4 RESN 56
    R3P6 RESN 34 R4T7 RESN 14 R7E4 RESN 49 R8C5 RESN 56
    R3P7 RESN 34 R4T8 RESN 14 R7E5 RESN 49 R8C6 RESN 56

    PROJECT NAME PAGE REV


    MICROSOFT
    XENON_RETAIL 72/73 K7
    CONFIDENTIAL
    R8G3 RESN 50 ST8F1 SHORT 50
    R8N1 RESN 48 SW1G1 SWITCH 42
    R8N2 RESN 52 SW2G1 SWITCH 42
    R8N3 RESN 52 SW2G2 SWITCH 42
    R8N4 RESN 52 SW5G1 SWITCH 42
    R8N5 RESN 52 TP6D1 PROBE 4
    R8N6 RESN 52 TP6R1 PROBE 4
    R8N7 RESN 52 TP6R2 PROBE 4
    R8N8 RESN 52 TP7A1 TDRX4 57
    R8N9 RESN 52 TP7A2 TDRX4 57
    R8N10 RESN 52 TP7M1 TDRX2 57
    R8N11 RESN 52 TP7M2 TDRX2 57
    R8N12 RESN 52 TP7R1 PROBE 4
    R8N17 RESN 34 TP7R2 PROBE 4
    R8N18 RESN 34 TP7R3 PROBE 4
    R8P1 RESN 52 TP7R4 PROBE 4
    R8P2 RESN 52 TP8A1 TDRX2 57
    R8P3 RESN 52 TP8A2 TDRX2 57
    R8P4 RESN 52 TP8M1 TDRX4 57
    R8P5 RESN 52 TP8M2 TDRX4 57
    R8P6 RESN 52 U1B1 BCM5241 19
    R8P7 RESN 52 U1B2 ICS1893BF 39
    R8P8 RESN 56 U1E1 NCP1117 53
    R8P9 RESN 52 U1F1 NCP1086 55
    R8U1 RESN 50 U1F2 NCP1117 45
    R8U2 RESN 50 U1G1 IR_WHOLDER 42
    R8U3 RESN 50 U1R1 SI4501DY 46
    R8U4 RESN 50 U2B1 XDAC 40
    R8V1 RESN 50 U2C1 SB 33 34 35 36 37 38
    R8V2 RESN 50 U2D1 SN74LVC1G125 12
    R8V3 RESN 50 U2E1 NAND 41
    R8V4 RESN 50 U2E2 SN74LVC1G125 12
    R8V5 RESN 50 U2R1 SN74LVC1G125 12
    R9B1 RESN 52 U2T1 NCP1117 53
    R9C1 RESN 51 U3B4 MK1493REV13 46
    R9E1 RESN 51 U3D1 GDDR136 24
    R9F1 RESN 51 U3E1 GDDR136 26
    R9G1 RESN 45 U3P1 NCP1117 55
    R9G2 RESN 45 U3R1 GDDR136 25
    R9P1 RESN 51 U3T1 GDDR136 27
    R9P2 RESN 51 U4B1 ANA 28 29 30
    R9T1 RESN 51 U4C1 AT25020A 13
    R9T2 RESN 51 U4D1 NB 12 13 14 15 16 17 57
    R9U1 RESN 51 U4F1 GDDR136 20
    R9U2 RESN 51 U4U1 GDDR136 21
    R9V1 RESN 45 U4V1 NCP5425 54
    R9V2 RESN 45 U5B1 NCP1117 55
    RT1B1 THERMISTOR 44 U5B2 NCP1117 55
    RT1R1 THERMISTOR 47 U5C1 NCP1117 55
    RT1U1 THERMISTOR 47 U5F1 GDDR136 22
    RT2G1 THERMISTOR 45 U5U1 GDDR136 23
    RT2M1 THERMISTOR 43 U6R1 NCP1117 55
    RT7C1 THERMISTOR 52 U6T1 NCP502D 55
    RT8F1 THERMISTOR 50 U6T2 LP2980 55
    RT8G1 THERMISTOR 45 U7D1 WATERNOOSE 4 5 6 7 8 57
    RT8G2 THERMISTOR 45 U7E1 AT25020A 4
    ST1P1 SHORT 38 U7U1 ADP3188 50
    ST1P2 SHORT 38 U8N1 NCP5331 52
    ST1P3 SHORT 38 U9P1 MOSDRIVER 51
    ST2P1 SHORT 38 U9T1 MOSDRIVER 51
    ST2P2 SHORT 37 U9U1 MOSDRIVER 51
    ST2P3 SHORT 37 Y3B1 CRYSTAL 46
    ST2P4 SHORT 37
    ST4C1 SHORT 29
    ST4C2 SHORT 29
    ST4C3 SHORT 29
    ST4C4 SHORT 29
    ST4C5 SHORT 29
    ST5D1 SHORT 52
    ST5R1 SHORT 52
    ST5R2 SHORT 52
    ST6D1 SHORT 6
    ST6R1 SHORT 6
    ST6R2 SHORT 6
    ST7D1 SHORT 6
    ST7R1 SHORT 6
    ST7T1 SHORT 50

    PROJECT NAME PAGE REV


    MICROSOFT
    XENON_RETAIL 73/73 K7
    CONFIDENTIAL

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