Xbox One Fat Schematic

8 7 6 5 4 3 2 1
PAGE CONTENTS
[1]
[2]
COVER PAGE
SOC, PCIEX + CLOCKS + VIDEO
[38]
[39]
[40]
CONN, HDMI OUT
CONN, ODD + HDD
CONN, LITHIUM + FAN
GREYBULL
D [3]
[4]
SOC POWER, MEM+CPUCORE+MEMCORE+NBCORE+MISC
SOC POWER, V_GFXCORE + VSS
[41]
[42]
CONN, PWR
VREGS, BLEEDERS REV 1.0 D
[5]
[6]
SOC, MEMOERY PARTITION C + D
SOC, MEMORY PARTITION A + B
[43]
[44]
[45]
VREGS, INPUT + OUTPUT FILTERS
VREGS, CPUCORE
VREGS, GFXCORE
FAB M
[7]
[8]
[9]
SOC, VSS + SPARE
SOC, DEBUG + SB SIGNALS
SOC, DECOUPLING
[46]
[47]
VREGS, GFXCORE OUTPUT PHASE 1 & 2
RETAIL
[48] VREGS, CPUCORE OUTPUT PHASE
[10] SOC, DECOUPLING
[49] VREGS, VTT TERMINATION
[11] SOC, DECOUPLING
[50] VREGS, NBCORE
[12] MEMORY CHANNEL D
[51] VREGS, MEMCORE
[13] MEMORY CHANNEL D
[52] VREGS, MEMIOCD
[14] MEMORY CHANNEL D, DECOUPLING
[53] VREGS, MEMIOAB
C [15] MEMORY CHANNEL C C
[54] VREGS, V5P0
[16] MEMORY CHANNEL C
[55] VREGS, V5P0 DUAL
[17] MEMORY CHANNEL C, DECOUPLING
[56] VREGS, V3P3
[18] MEMORY CHANNEL B
[57] VREGS, VSOCPHY
[19] MEMORY CHANNEL B
[58] VREGS, VSOCPLL + VBURN + VFUSE + VBAT
[20] MEMORY CHANNEL B, DECOUPLING
[59] VREGS, VSB2P5
[21] MEMORY CHANNEL A
[60] VREGS, VSB1P8PLL + VSB1P8IO + VSBCORE + VSB1P1PLL
[22] MEMORY CHANNEL A
[61] VREGS, STANDBY SWITCHERS 3P3
[23] MEMORY CHANNEL A, DECOUPLING
[62] VREGS, STANDBY SWITCHERS 1P1 + 1P8
[24] KIC, USB
[63] IR BLASTER
[25] KIC, PCIEX + SATA + VIDEO
[64] I2C
B [26] KIC, SMC
[65] FACET, FTDI B
[27] KIC, FACET
[66] FACET, FTDI + MISC
[28] KIC, POWER
[67] CONN, SWITCHES
[29] KIC, CLOCKS + STRAPPING + POR
[68] CONN, HDT
[30] KIC, POWER
[69] DEBUG, VR HEADERS AND TEST POINTS
[31] KIC, DECOUPLING
[70] DEBUG, CONNECTORS
[32] CONTROLLER, ETHERNET
[71] DEBUG, ENET EEPROM + MISC
[33] EMMC
[72] LABELS AND MOUNTING
[34] CONN, RJ45 + TOSLINK
[35] CONN, USB
[36] CONN, USB
[37] CONN, HDMI IN
RULES: (APPLIED WHEN POSSIBLE)
1.) MSB TO LSB IS TOP TO BOTTOM
2.) WHEN POSSIBLE: INPUTS ON LEFT, OUTPUTS ON RIGHT
3.) ORDER OF PAGES=CHIP INTERFACES, TERMINATION, POWER, DECOUPLING
4.) AVOID USING OFF PAGE CONNECTORS FOR ON PAGE CONNECTIONS
A 5.) LANED SIGNALS ARE GROUPED ON SYMBOLS A
6.) TRANSIMITTER NAME USED AS PREFIX WITH RX AND TX CONNECTIONS
7.) SUFFIX V_ IS USED FOR VOLTAGE RAIL SIGNAL NAMES
8.) SUFFIX _DP AND _DN ARE USED FOR DIFFERIENTAL PAIRS
9.) UNNAMED NETS ARE NAMED WITH /2 TEXT SIZE
10.) SUFFIX _N FOR ACTIVE LOW OR N JUNCTION
12.) SUFFIX _P FOR P JUNCTION
13.) SUFFIX _EN FOR ENABLE
14.) 'CLK' FOR CLOCKS, 'RST' FOR RESETS
15.) PWRGD FOR POWER GOOD
16.) REV AND FAB ARE SET USING CUSTOM VARIABLES
TOOLS>OPTIONS>VARIABLES
MICROSOFT PROJECT NAME PAGE CSA FAB REV
[PAGE_TITLE=COVER PAGE] DRAWING
CONFIDENTIAL
Fri May 10 13:22:55 2013 GREYBULL_RETAIL 1/72
PAGE
1/72 M 1.0
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
SOC,PCIEX + CLOCKS + VIDEO R4R19
1 2
0 OHM 5%
402 EMPTY
D R4R20 D
1 2
U7E1 IC 0 OHM 5%
402 EMPTY
R5U6
1 2 PCIE C7E6
0 OHM 5% 1 of 17 1 2 PEX_SOC_ENET_TP_C 32
402 EMPTY OUT
0.1 UF
6.3 V 10%
X5R C7E8
P_UMI_TX3_P AP20 PEX_SOC_SPARE_TP 402 1 2 PEX_SOC_ENET_TN_C 32
R5U7 AP21 PEX_SOC_SPARE_TN
OUT
1 2 P_UMI_TX3_N
0.1 UF 10%
0 OHM 5% 6.3 V
EMPTY X5R
402 PEX_SPARE_SOC_TP_C AR19 AP23 PEX_SOC_ENET_TP 402
P_UMI_RX3_P P_UMI_TX2_P
PEX_SPARE_SOC_TN_C AR20 P_UMI_RX3_N P_UMI_TX2_N AP24 PEX_SOC_ENET_TN
32 PEX_ENET_SOC_TP_C AN21 P_UMI_RX2_P P_UMI_TX1_P AU23 PEX_L1_SOC_SB_TP

IN PEX_ENET_SOC_TN_C AN22 AU24 PEX_L1_SOC_SB_TN
32 IN P_UMI_RX2_N P_UMI_TX1_N
C7E1 U7E1 IC
25 PEX_L1_SB_SOC_TP_C AV22 P_UMI_RX1_P P_UMI_TX0_P AV25 PEX_L0_SOC_SB_TP 1 2 PEX_L1_SOC_SB_TP_C 25
IN OUT
C 25 IN PEX_L1_SB_SOC_TN_C AV23 P_UMI_RX1_N P_UMI_TX0_N AV26 PEX_L0_SOC_SB_TN
0.1 UF 10% VIDEO C
6.3 V
C7E3
X5R
402
3 of 17
25 PEX_L0_SB_SOC_TP_C AT24 P_UMI_RX0_P P_RX_ZVDD_095 AN19 1 2
IN PEX_L0_SB_SOC_TN_C AT25 AN18
PEX_L1_SOC_SB_TN_C
OUT 25
25 IN P_UMI_RX0_N P_TX_ZVDD_095
RX_ZVDD_095
0.1 UF 10%
6.3 V
TX_ZVDD_095
X5R
X862035-001 BGA1443 C7E5 402
1 2 PEX_L0_SOC_SB_TP_C 25
OUT
0.1 UF10%
6.3 V
1 R3T6 C7E7 X5R
1 2 402 PEX_L0_SOC_SB_TN_C 25
1 KOHM OUT
V_SOCPHY 1%
EMPTY 0.1 UF 10%
1 R3T5 2 CH 6.3 V
1.69 KOHM 402 X5R
1% 402 DP_CR_CLK AP14 DP_CR_CLK
BI
2 CH
402
25 IN DP_L0_SB_SOC_TP_C AU18 DP1_RX0_P
25 IN DP_L0_SB_SOC_TN_C AU17 DP1_RX0_N
IC 38 OUT TMDS_TX_DP0 AU15 DP0_TX2_P
U7E1 TMDS_TX_DN0 AU14
B 38
38
OUT
OUT TMDS_TX_DP2 AV17
DP0_TX2_N
DP0_TX0_P B
CLOCKS 38 TMDS_TX_DN2 AV16 DP0_TX0_N
OUT DP_L1_SB_SOC_TP_C AT19
2 of 17 25 IN DP1_RX1_P
29 IN SOC_NB_PEX_SS_100M_CLKP AU26 CLKIN_NB_P 25 IN DP_L1_SB_SOC_TN_C AT18 DP1_RX1_N
29 IN SOC_NB_PEX_SS_100M_CLKN AU27 CLKIN_NB_N 38 OUT TMDS_TX_DP1 AT16 DP0_TX1_P
C3R26 38 TMDS_TX_DN1 AT15 DP0_TX1_N
25 DP_AUX_SB_SOC_TP_C 1 2 OUT
29 IN SOC_REF_NS_100M_CLKP AT21 DISP_CLKIN_P IN
29 IN SOC_REF_NS_100M_CLKN AT22 DISP_CLKIN_N 0.1 UF 10% X5R DP_AUX_SOC_SB_TP AT13 DP1_AUX_P
29 SOC_AV_NS_100M_CLKP AV19 AV_CLKIN_P 6.3 V 402 DP_AUX_SOC_SB_TN AT12 DP1_AUX_N
IN SOC_AV_NS_100M_CLKN AV20 C3R25
29 IN AV_CLKIN_N DP_AUX_SB_SOC_TN_C 1 2
SOC_PEX_SS_100M_CLKP AU20 25 IN
29 IN CLKIN_P
29 IN SOC_PEX_SS_100M_CLKN AU21 CLKIN_N 0.1 UF 10% X5R 38 OUT HDMI_OUT_DDC_CLK AR14 DP0_AUX_P
AR23 TEST25_P 6.3 V 402 38 HDMI_OUT_DDC_DATA AR13 DP0_AUX_N
AR22
BI TMDS_TX_CLKP AV14
TEST25_N 38 OUT DP0_TX3_P
38 OUT TMDS_TX_CLKN AV13 DP0_TX3_N
25 OUT DP1_HPD AP15 DP1_HPD
X862035-001 BGA1443 SPDIF_OUT AP12
34 OUT SPDIF_OUT
38 IN DP0_HPD AU12 DP0_HPD
DP_TX_CALR AM12 DP_TX_ZVSS

1 R3R11 DP_AUX_CALR AR12
100 KOHM DP_AUX_ZVSS
DVI PCB DP PCB 1 R7D10 1% DP_RX_CALR AN13 DP_RX_ZVSS
ROUTING ROUTING 100 KOHM 2 CH
1% 402
ORDERING ORDERING PIN NAME
2 CH
TMDS CLOCK - DP LANE 3 - DP0_TX3_N 402 1 R3R10 1 R3R7 1 R3R9 X862035-001 BGA1443
150 OHMS 150 OHMS
A TMDS CLOCK + DP LANE 3 + DP0_TX3_P 1% 1% 2 KOHM
1% A
2 CH 2 CH
TMDS DATA0 - DP LANE 2 - DP0_TX2_N 402 402 2 CH
402
TMDS DATA0 + DP LANE 2 + DP0_TX2_P
70 OUT TEST25_P TMDS DATA1 - DP LANE 1 - DP0_TX1_N
70 OUT TEST25_N
TMDS DATA2 - DP LANE 0 - DP0_TX0_N

MS_PART# MATL REF_DES TRUEDESCR. BOM PROPERTY
[PAGE_TITLE=SOC PAGE 1] U7E1 EMPTY EMPTY SOC DUMMY_BOM DRAWING
CONFIDENTIAL
Tue Jun 18 16:42:23 2013 GREYBULL_RETAIL 2/72
PAGE
2/72 M 1.0
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
SOC POWER, MEM + CPUCORE + MEMCORE + NBCORE + MISC

D D
V_NBCORE
EMPTY
V_MEMIOCD V_CPUCORE U7E1 IC

V_MEMIOAB EMPTY
EMPTY
EMPTY U7E1 POWER IC
VDD_CORE VDD_NB[14] AJ23
VDD_NB[13] AF24
U7E1 10 of 17 VDD_NB[12] AJ25
IC A31 VDD_CORE[54] V_SOCPHY 11 of 17 AD28
A30 VDD_NB[11]
VDD_CORE[53] EMPTY AD26
VDD MEM A29 VDD_CORE[52]
VDD_NB[10] V_FUSE
VDD_NB[9] AH24 EMPTY
9 of 17 A27 VDD_CORE[51]
VDD_NB[8] AE27
A25 VDD_CORE[50] AJ18 VDD_095[4] VDD_NB[7] AE25
AU31 VDD_MEM1[47] VDD_MEM0[47] AU4 B31 VDD_CORE[49] AH18 VDD_095[3] VDD_NB[6] AF28
AU35 VDD_MEM1[46] VDD_MEM0[46] AU8 B30 VDD_CORE[48] AH17 VDD_095[2] VDD_NB[5] AF26
AT30 VDD_MEM1[45] VDD_MEM0[45] AT5 B29 VDD_CORE[47] AG19 VDD_095[1] VDD_NB[4] AG27 1
AT34 VDD_MEM1[44] VDD_MEM0[44] AT9 B27 VDD_CORE[46] AF18 VDD_095[0] VDD_NB[3] AG25 C3R22
AP29 VDD_MEM1[43] VDD_MEM0[43] AP6 B25 VDD_CORE[45] 1 UF
VDD_NB[2] AH28 10%
AP33 VDD_MEM1[42] VDD_MEM0[42] AP10 C30 VDD_CORE[44] 6.3 V
VDD_NB[1] AH26 2 X5R
AN28 VDD_MEM1[41] VDD_MEM0[41] AN2 C28 VDD_CORE[43]
VDD_NB[0] AJ27 402
AN32 VDD_MEM1[40] VDD_MEM0[40] AN7 C26 VDD_CORE[42]
C AN37
AM36
VDD_MEM1[39] VDD_MEM0[39] AN11
AM3
D28
D26
VDD_CORE[41]
C
VDD_MEM1[38] VDD_MEM0[38] VDD_CORE[40] AJ13
AK33 AK6 E29 VDD_085
VDD_MEM1[37] VDD_MEM0[37] VDD_CORE[39] V_3P3
AJ34 VDD_MEM1[36] VDD_MEM0[36] AJ2 E27 VDD_CORE[38] EMPTY V_MEMCORE
AJ37 AJ5 E25 EMPTY
VDD_MEM1[35] VDD_MEM0[35] VDD_CORE[37]
AH29 VDD_MEM1[34] VDD_MEM0[34] AH3 F29 VDD_CORE[36] AE21
AG16 VDD_33[1] VDDCR_MEM[9]
AH36 VDD_MEM1[33] VDD_MEM0[33] AH10 F27 VDD_CORE[35] AJ19
AJ16 VDD_33[0] VDDCR_MEM[8]
AF29 VDD_MEM1[32] VDD_MEM0[32] AF6 F25 VDD_CORE[34] AF22
AF33 AF10 G28 VDDCR_MEM[7] V_BAT
VDD_MEM1[31] VDD_MEM0[31] VDD_CORE[33] AF20
AE34 AE2 G26 VDDCR_MEM[6] EMPTY
VDD_MEM1[30] VDD_MEM0[30] VDD_CORE[32] AG23
AE37 AE5 H28 1 1 VDDCR_MEM[5]
VDD_MEM1[29] VDD_MEM0[29] VDD_CORE[31] C3T2 C3T7 AG21
AD29 AD3 H26 VDDCR_MEM[4]
VDD_MEM1[28] VDD_MEM0[28] VDD_CORE[30] 1 UF 1 UF AD24
AD36 AD10 J27 10% 10% VDDCR_MEM[3]
VDD_MEM1[27] VDD_MEM0[27] VDD_CORE[29] AH22
AB29 AB6 J25 6.3 V 6.3 V VDDCR_MEM[2] 1
VDD_MEM1[26] VDD_MEM0[26] VDD_CORE[28] 2 X5R 2 X5R AH20 C3T37
AB33 AB10 K27 402 402 VDDCR_MEM[1]
VDD_MEM1[25] VDD_MEM0[25] VDD_CORE[27] AE23 1 UF
AA34 AA2 K25 VDDCR_MEM[0] 10%
VDD_MEM1[24] VDD_MEM0[24] VDD_CORE[26]
AA37 AA5 L28 6.3 V
VDD_MEM1[23] VDD_MEM0[23] VDD_CORE[25] 2 X5R
Y29 VDD_MEM1[22] VDD_MEM0[22] Y3 L26 VDD_CORE[24] AM25 402
AG15 VDD_18[3] VDDBT_RTC_G
Y36 VDD_MEM1[21] VDD_MEM0[21] Y10 M28 VDD_CORE[23] AH15 VDD_18[2]
V29 VDD_MEM1[20] VDD_MEM0[20] V6 M26 VDD_CORE[22] AH14 VDD_18[1] VBURN[1] AH12
V33 VDD_MEM1[19] VDD_MEM0[19] V10 N27 VDD_CORE[21] V_BURN
AJ14 VDD_18[0] VBURN[0] AJ12
U34 VDD_MEM1[18] VDD_MEM0[18] U2 N25 VDD_CORE[20] EMPTY
U37 U5 P27
B T29
VDD_MEM1[17]
VDD_MEM1[16]
VDD_MEM0[17]
VDD_MEM0[16] T3 P25
VDD_CORE[19]
VDD_CORE[18] B
T36 VDD_MEM1[15] VDD_MEM0[15] T10 R28 VDD_CORE[17] X862035-001 BGA1443
P29 VDD_MEM1[14] VDD_MEM0[14] P6 R26 VDD_CORE[16] 1
P33 VDD_MEM1[13] VDD_MEM0[13] P10 T28 VDD_CORE[15] V_SOC1P8VDD V_SOC1P8 C3R21
N34 VDD_MEM1[12] VDD_MEM0[12] N2 T26 VDD_CORE[14] EMPTY EMPTY 1 UF
10%
N37 VDD_MEM1[11] VDD_MEM0[11] N5 U27 VDD_CORE[13] 6.3 V
M29 M3 U25 2 X5R
VDD_MEM1[10] VDD_MEM0[10] VDD_CORE[12] FB6D1 402
M36 VDD_MEM1[9] VDD_MEM0[9] M10 V27 VDD_CORE[11] 1 2
K29 VDD_MEM1[8] VDD_MEM0[8] K6 V25 VDD_CORE[10]
K33 K10 W28 120 OHM FB
VDD_MEM1[7] VDD_MEM0[7] VDD_CORE[9] 1.3 A 402
J34 VDD_MEM1[6] VDD_MEM0[6] J2 W26 VDD_CORE[8] 0.09DCR
J37 VDD_MEM1[5] VDD_MEM0[5] J5 Y28 VDD_CORE[7] 1 1
H29 VDD_MEM1[4] VDD_MEM0[4] H3 Y26 VDD_CORE[6] C7D3 C6D10
H36 VDD_MEM1[3] VDD_MEM0[3] H10 AA27 VDD_CORE[5] 4.7 UF 4.7 UF
10% 10%
F33 VDD_MEM1[2] VDD_MEM0[2] F6 AA25 VDD_CORE[4] 6.3 V 6.3 V
E32 E5 AB27 2 X5R 2 X5R
VDD_MEM1[1] VDD_MEM0[1] VDD_CORE[3] C3R24 603 603
E34 VDD_MEM1[0] VDD_MEM0[0] E7 AB25 VDD_CORE[2] 1 2
AC28 VDD_CORE[1]
AC26 1 UF 10%
VDD_CORE[0] 6.3 V
X5R
BGA1443 402
X862035-001
X862035-001 BGA1443
A A

PAGE
[PAGE_TITLE=SOC PAGE 2] DRAWING
CONFIDENTIAL
Tue Jun 18 16:42:23 2013 GREYBULL_RETAIL 3/72 3/72 M 1.0
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
SOC POWER, V_GFXCORE + VSS

D D
V_GFXCORE
EMPTY
V_GFXCORE
EMPTY V_GFXCORE
EMPTY IC
U7E1 IC
U7E1 IC U7E1 IC U7E1
VDD_GFX VSS
VDD_GFX 14 of 17 VSS
U15 VDD_GFX[60] 12 of 17
U13 J23 A23 VDD_GFX[181] 13 of 17 15 of 17
VDD_GFX[59] VDD_GFX[120] A21 AB31 VSS[180] VSS[240] U22
U11 J21 VDD_GFX[180] AN30 VSS[60] AB28 U20
VDD_GFX[58] VDD_GFX[119] A19 AN26 AF8 VSS[179] VSS[239]
V23 J19 VDD_GFX[179] VSS[59] VSS[120] AB26 U18
VDD_GFX[57] VDD_GFX[118] A17 AN23 AF3 VSS[178] VSS[238]
V21 J17 VDD_GFX[178] VSS[58] VSS[119] AB24 U16
VDD_GFX[56] VDD_GFX[117] A15 AN20 VSS[57] AG37 VSS[177] VSS[237]
V19 J15 VDD_GFX[177] VSS[118] AB22 U14
V17 J13 VDD_GFX[176] VSS[117] AB20 U12
V15 J11 VDD_GFX[175] VSS[116] AB18 U9
V13 K23 VDD_GFX[174] VSS[115] AB16 V36
V11 K21 VDD_GFX[173] VSS[114] AB14 V31
VDD_GFX[51] VDD_GFX[112] B23 AN5 VSS[52] AG24 VSS[172] VSS[232]
W24 K19 VDD_GFX[172] VSS[113] AB12 V28
VDD_GFX[50] VDD_GFX[111] B21 AP36 VSS[51] AG22 VSS[171] VSS[231]
W22 K17 VDD_GFX[171] VSS[112] AB8 V26
W20 K15 VDD_GFX[170] VSS[111] AB3 V24
W18 K13 VDD_GFX[169] VSS[110] AC37 V22
C W16
VDD_GFX[47]
VDD_GFX[46]
VDD_GFX[108]
VDD_GFX[107] K11 B15
B13
VDD_GFX[168] AP25
AP22
VSS[48] VSS[109] AG9
AG5
AC34
VSS[168]
VSS[167]
VSS[228]
VSS[227] V20 C
W14 L24 VDD_GFX[167] VSS[47] VSS[108] AC30 V18
W12 L22 VDD_GFX[166] VSS[107] AC27 V16
VDD_GFX[44] VDD_GFX[105] B10 AP16 VSS[45] AH33 VSS[165] VSS[225]
Y24 L20 VDD_GFX[165] VSS[106] AC23 V14
VDD_GFX[43] VDD_GFX[104] C24 AP13 AH31 VSS[164] VSS[224]
Y22 L18 VDD_GFX[164] VSS[44] VSS[105] AC21 V12
VDD_GFX[42] VDD_GFX[103] C22 AP8 VSS[43] AH27 VSS[163] VSS[223]
Y20 L16 VDD_GFX[163] VSS[104] AC19 V8
Y18 L14 VDD_GFX[162] VSS[103] AC17 V3
Y16 L12 VDD_GFX[161] VSS[102] AC15 W37
VDD_GFX[39] VDD_GFX[100] C16 AR37 VSS[40] AH21 VSS[160] VSS[220]
Y14 M24 VDD_GFX[160] VSS[101] AC13 W34
VDD_GFX[38] VDD_GFX[99] C14 AR27 VSS[39] AH19 VSS[159] VSS[219]
Y12 M22 VDD_GFX[159] VSS[100] AC11 W30
VDD_GFX[37] VDD_GFX[98] C12 AR24 VSS[38] VSS[99] AH16 VSS[158] VSS[218]
AA23 M20 VDD_GFX[158] AC9 W27
VDD_GFX[36] VDD_GFX[97] C10 AR21 VSS[37] VSS[98] AH13 VSS[157] VSS[217]
AA21 M18 VDD_GFX[157] AC5 W25
VDD_GFX[35] VDD_GFX[96] D24 VDD_GFX[156] AR18 VSS[36] VSS[97] AH8 VSS[156] VSS[216]
AA19 VDD_GFX[34] VDD_GFX[95] M16 AC2 VSS[155] VSS[215] W23
AA17 M14 D22 VDD_GFX[155] AR15 VSS[35] VSS[96] AH6
VDD_GFX[33] VDD_GFX[94] D20 AD33 VSS[154] VSS[214] W21
AA15 M12 VDD_GFX[154] AR2 VSS[34] VSS[95] AJ30 AD31 W19
VDD_GFX[32] VDD_GFX[93] D18 VDD_GFX[153] AT36 VSS[33] VSS[94] AJ26 VSS[153] VSS[213]
AA13 VDD_GFX[31] VDD_GFX[92] N23 AD27 VSS[152] VSS[212] W17
AA11 N21 D16 VDD_GFX[152] AT32 VSS[32] VSS[93] AJ24
VDD_GFX[30] VDD_GFX[91] D14 AD25 VSS[151] VSS[211] W15
AB23 N19 VDD_GFX[151] AT28 VSS[31] VSS[92] AJ20 AD23 W13
VDD_GFX[29] VDD_GFX[90] D12 VDD_GFX[150] AT26 VSS[30] VSS[91] AJ17 VSS[150] VSS[210]
AB21 VDD_GFX[28] VDD_GFX[89] N17 AD21 VSS[149] VSS[209] W11
AB19 N15 D10 VDD_GFX[149] AT23 VSS[29] VSS[90] AJ15
VDD_GFX[27] VDD_GFX[88] E23 AD19 VSS[148] VSS[208] W9
AB17 N13 VDD_GFX[148] AT20 VSS[28] VSS[89] AJ9 AD17 W5
VDD_GFX[26] VDD_GFX[87] E21 VDD_GFX[147] AT17 VSS[27] VSS[88] AK36 VSS[147] VSS[207]
AB15 VDD_GFX[25] VDD_GFX[86] N11 AD15 VSS[146] VSS[206] W2
E19 AT14 AK31
B AB13
AB11
VDD_GFX[24] VDD_GFX[85] P23
P21 E17
VDD_GFX[146]
VDD_GFX[145] AT11
VSS[26]
VSS[25]
VSS[87]
VSS[86] AK29
AD13
AD11
VSS[145] VSS[205] Y33
Y31 B
VDD_GFX[23] VDD_GFX[84] E15 VDD_GFX[144] AT7 VSS[24] VSS[85] AK23 VSS[144] VSS[204]
AC24 VDD_GFX[22] VDD_GFX[83] P19 AD8 VSS[143] VSS[203] Y27
AC22 P17 E13 VDD_GFX[143] AT3 VSS[23] VSS[84] AK10
VDD_GFX[21] VDD_GFX[82] E11 AU38 AD6 VSS[142] VSS[202] Y25
AC20 P15 VDD_GFX[142] VSS[22] VSS[83] AK8 AE30 Y23
VDD_GFX[20] VDD_GFX[81] F23 VDD_GFX[141] AU37 VSS[21] VSS[82] AK3 VSS[141] VSS[201]
AC18 VDD_GFX[19] VDD_GFX[80] P13 AE28 VSS[140] VSS[200] Y21
F21 VDD_GFX[140] AU33 VSS[20] VSS[81] AL37
AC16 VDD_GFX[18] VDD_GFX[79] P11 AE26 VSS[139] VSS[199] Y19
AC14 VDD_GFX[17] VDD_GFX[78] R24 AE24 VSS[138] VSS[198] Y17
AC12 VDD_GFX[16] VDD_GFX[77] R22 AE22 VSS[137] VSS[197] Y15
AD22 VDD_GFX[15] VDD_GFX[76] R20 AE20 VSS[136] VSS[196] Y13
G24 VDD_GFX[134] AU13 VSS[14] VSS[75] AL19
AD14 VDD_GFX[11] VDD_GFX[72] R12 AE12 VSS[132] VSS[192] AA30
AD12 VDD_GFX[10] VDD_GFX[71] T24 AE9 VSS[131] VSS[191] AA28
AE17 VDD_GFX[9] VDD_GFX[70] T22 AF36 VSS[130] VSS[190] AA26
G14 VDD_GFX[129] AV38 VSS[9] VSS[70] AL2
G12 VDD_GFX[128] AV37 VSS[8] VSS[69] AM33
H24 VDD_GFX[127] AV27 VSS[7] VSS[68] AM27
AF17 VDD_GFX[5] VDD_GFX[66] T14 AF23 VSS[126] VSS[186] AA18
AF15 VDD_GFX[4] VDD_GFX[65] T12 AF21 VSS[125] VSS[185] AA16
AF13 VDD_GFX[3] VDD_GFX[64] U23 AF19 VSS[124] VSS[184] AA14
AF11 VDD_GFX[2] VDD_GFX[63] U21 AF16 VSS[123] VSS[183] AA12
AG14 VDD_GFX[1] VDD_GFX[62] U19 AF14 VSS[122] VSS[182] AA9
AG12 VDD_GFX[0] VDD_GFX[61] U17 AF12 VSS[121] VSS[181] AB36
AV1 VSS[0] VSS[61] AN34
X862035-001 BGA1443 X862035-001 BGA1443 X862035-001 BGA1443
A X862035-001 BGA1443 A

DRAWING PAGE
[PAGE_TITLE=SOC PAGE 3] CONFIDENTIAL
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
SOC, MEMORY PARTITION C + D U7E1 IC
U7E1 IC
16 MC_DQ63 AN8 MC_DQ63
MEM CHANNEL C
BI MC_DQ62 AM11
13 MD_DQ63 P2 MD_DQ63
MEM CHANNEL D 16 BI MC_DQ62 5 of 17
BI MD_DQ62 W1 16 BI MC_DQ61 AM8 MC_DQ61
13 BI MD_DQ62 6 of 17 16 MC_DQ60 AN10 MC_DQ60
MD_DQ61 N4 BI
D 13
13
BI
BI MD_DQ60 V2
MD_DQ61
MD_DQ60
16 BI MC_DQ59
MC_DQ58
AR7
AP11
MC_DQ59 D
MD_DQ59 N1 16 BI MC_DQ58
13 BI MD_DQ59 MC_DQ57 AP9
MD_DQ58 W3 16 BI MC_DQ57
13 BI MD_DQ58 MC_DQ56 AR11
MD_DQ57 P1 16 BI MC_DQ56
13 BI MD_DQ57 MC_DQ55 AV11
MD_DQ56 W4 16 BI MC_DQ55
MD_DQ55 Y2 16 BI MC_DQ54
13 BI MD_DQ55 MC_DQ53 AU11
MD_DQ54 M2 16 BI MC_DQ53
MD_DQ53 Y1 16 BI MC_DQ52
13 BI MD_DQ52 MC_DQ50 AT8
MD_DQ51 T1 16 BI MC_DQ50
MD_DQ49 U3 16 BI MC_DQ48
MD_DQ48 R4 16 BI MC_DQ47
13 BI MD_DQ48 MC_DQ46 AN6
MD_DQ44 P7 16 BI MC_DQ43
13 BI MD_DQ44 MC_DQ42 AM7
MD_DQ40 T4 16 BI MC_DQ39
MD_DQ39 L4 16 BI MC_DQ38
MD_DQ38 H1 16 BI MC_DQ37
C 13 BI MD_DQ37
MD_DQ36
L3
G4
MD_DQ37
16
16
BI
BI MC_DQ35 AT6
MC_DQ36
MC_DQ35 C
MD_DQ33 K1 16 BI MC_DQ32
13 BI MD_DQ33 MC_DQ31 AJ8
MD_DQ32 J1 15 BI MC_DQ31
13 BI MD_DQ32 MC_DQ30 AL6
12 BI MD_DQ31 MC_DQ29 AH4
12 BI MD_DQ30 MC_DQ28 AL8
12 BI MD_DQ29 MC_DQ27 AH5
MD_DQ27 G8 15 BI MC_DQ26
12 BI MD_DQ27 MC_DQ25 AJ6
MD_DQ24 L8 15 BI MC_DQ23 V_MEMIOCD
12 BI MD_DQ24 MC_DQ22 AK1
MD_DQ23 G3 15 BI MC_DQ22 EMPTY
12 BI MD_DQ23 V_MEMIOCD MC_DQ21 AP1
MD_DQ22 C1 15 BI MC_DQ21
12 BI MD_DQ22 EMPTY MC_DQ20 AJ4
MD_DQ21 G1 15 BI MC_DQ20
12 BI MD_DQ21 MC_DQ19 AN1 1 R3R16
MD_DQ20 C3 15 BI MC_DQ19
12 BI MD_DQ20 MC_DQ18 AK2 40.2 OHM
MD_DQ19 F1 1 R3R14 15 BI MC_DQ18 1%
MD_DQ18 D2 40.2 OHM 15 BI MC_DQ17
12 BI MD_DQ18 1% MC_DQ16 AL1 2 EMPTY
MD_DQ17 E1 15 BI MC_DQ16 402
12 BI MD_DQ17 2 EMPTY MC_DQ15 AC1 AJ11 MC_TEST
MD_DQ16 D1 15 BI MC_DQ15 MC_TEST
12 BI MD_DQ16 402 MC_DQ14 AG4
MD_DQ15 C8 AG11 MD_TEST 15 BI MC_DQ14
B 12
12
BI
BI MD_DQ14 D5
MD_DQ15
MD_DQ14
MD_TEST
15 BI MC_DQ13
MC_DQ12
AB2
AG3
MC_DQ13
AK9 MC_CLK0_DP
1 R3R15
40.2 OHM B
MD_DQ13 E8 1 R3R13 15 BI MC_DQ12 MC_CLK0_DP OUT 15 16 1%
12 BI MD_DQ13 MC_DQ11 AB1 MC_CLK0_DN AJ10 MC_CLK0_DN
MD_DQ12 G6 K9 MD_CLK0_DP 40.2 OHM 15 BI MC_DQ11 OUT 15 16
2 EMPTY
12 BI MD_DQ12 MD_CLK0_DP OUT 12 13 1% MC_DQ10 AH1
MD_DQ11 D9 J10 MD_CLK0_DN 15 BI MC_DQ10 402
12 BI MD_DQ11 MD_CLK0_DN OUT 12 13
2 EMPTY MC_DQ9 AC3 MC_A15 AC8 MC_A<15>
MD_DQ10 F5 15 BI MC_DQ9 BI 15 16 17
12 BI MD_DQ10 402 MC_DQ8 AH2 MC_A14 AA7 MC_A<14>
MD_DQ9 B7 V7 MD_A<15> 15 BI MC_DQ8 BI 15 16 17
12 BI MD_DQ9 MD_A15 BI 12 13 14 MC_DQ7 AJ3 MC_A13 AA10 MC_A<13>
MD_DQ8 F4 W10 MD_A<14> 15 BI MC_DQ7 BI 15 16 17
12 BI MD_DQ8 MD_A14 BI 12 13 14 MC_DQ6 AA3 AC6 MC_A<12>
MD_DQ7 A3 U10 MD_A<13> 15 BI MC_DQ6 MC_A12 BI 15 16 17
12 BI MD_DQ7 MD_A13 BI 12 13 14 MC_DQ5 AJ1 AB4 MC_A<11>
MD_DQ6 D6 W6 MD_A<12> 15 BI MC_DQ5 MC_A11 BI 15 16 17
12 BI MD_DQ6 MD_A12 BI 12 13 14 MC_DQ4 AA1 MC_DQ4 AE10 MC_A<10>
MD_DQ5 B3 Y5 MD_A<11> 15 BI MC_A10 BI 15 16 17
12 BI MD_DQ5 MD_A11 BI 12 13 14 MC_DQ3 AE3 AC7 MC_A<9>
MD_DQ4 A7 N10 MD_A<10> 15 BI MC_DQ3 MC_A9 BI 15 16 17
12 BI MD_DQ4 MD_A10 BI 12 13 14 MC_DQ2 AA4 AB9 MC_A<8>
MD_DQ3 D4 V9 MD_A<9> 15 BI MC_DQ2 MC_A8 BI 15 16 17
12 BI MD_DQ3 MD_A9 BI 12 13 14 MC_DQ1 AE4 AD9 MC_A<7>
MD_DQ2 C6 W7 MD_A<8> 15 BI MC_DQ1 MC_A7 BI 15 16 17
12 BI MD_DQ2 MD_A8 BI 12 13 14 MC_DQ0 AD1 MC_DQ0 AA8 MC_A<6>
MD_DQ1 C4 MD_DQ1 MD_A7 U7 MD_A<7> 15 BI MC_A6 BI 15 16 17
12 BI BI 12 13 14 MC_DQSL_0_P AD2 AD5 MC_A<5>
MD_DQ0 A6 Y7 MD_A<6> 15 BI MC_DQSL_0_P MC_A5 BI 15 16 17
12 BI MD_DQ0 MD_A6 BI 12 13 14 MC_DQSL_0_N AE1 AC10 MC_A<4>
MD_DQSL_0_P B5 V4 MD_A<5> 15 BI MC_DQSL_0_N MC_A4 BI 15 16 17
12 BI MD_DQSL_0_P MD_A5 BI 12 13 14 MC_DQSL_1_P AL3 AD7 MC_A<3>
MD_DQSL_0_N A5 R10 MD_A<4> 15 BI MC_DQSL_1_P MC_A3 BI 15 16 17
12 BI MD_DQSL_0_N MD_A4 BI 12 13 14 MC_DQSL_1_N AL4 AB5 MC_A<2>
MD_DQSL_1_P E3 U8 MD_A<3> 15 BI MC_DQSL_1_N MC_A2 BI 15 16 17
12 BI MD_DQSL_1_P MD_A3 BI 12 13 14 MC_DQSL_2_P AV4 AB7 MC_A<1>
MD_DQSL_1_N E4 Y4 MD_A<2> 16 BI MC_DQSL_2_P MC_A1 BI 15 16 17
12 BI MD_DQSL_1_N MD_A2 BI 12 13 14 MC_DQSL_2_N AU5 AE7 MC_A<0>
MD_DQSL_2_P J3 W8 MD_A<1> 16 BI MC_DQSL_2_N MC_A0 BI 15 16 17
13 BI MD_DQSL_2_P MD_A1 BI 12 13 14 MC_DQSL_3_P AU9
MD_DQSL_2_N J4 T9 MD_A<0> 16 BI MC_DQSL_3_P
13 BI MD_DQSL_2_N MD_A0 BI 12 13 14 MC_DQSL_3_N AV9 AE8 MC_BA<0>
MD_DQSL_3_P R1 16 BI MC_DQSL_3_N MC_BA0 BI 15 16 17
13 BI MD_DQSL_3_P MC_DQSU_0_P AF2 AD4 MC_BA<1>
MD_DQSL_3_N T2 T7 MD_BA<0> 15 BI MC_DQSU_0_P MC_BA1 BI 15 16 17
13 BI MD_DQSL_3_N MD_BA0 BI 12 13 14 MC_DQSU_0_N AG1 AE6 MC_BA<2>
MD_DQSU_0_P E6 V5 MD_BA<1> 15 BI MC_DQSU_0_N MC_BA2 BI 15 16 17
12 BI MD_DQSU_0_P MD_BA1 BI 12 13 14 MC_DQSU_1_P AK4
MD_DQSU_0_N F7 U6 MD_BA<2> 15 BI MC_DQSU_1_P
12 BI MD_DQSU_0_N MD_BA2 BI 12 13 14 MC_DQSU_1_N AK5
MD_DQSU_1_P J8 15 BI MC_DQSU_1_N
12 BI MD_DQSU_1_P MC_DQSU_2_P AP5 AH9 MC_CKE0 V_MEMIOCD
MD_DQSU_1_N K7 16 BI MC_DQSU_2_P MC_CKE0 OUT
12 BI MD_DQSU_1_N MC_DQSU_2_N AR5 AG10 MC_CAS_N EMPTY
MD_DQSU_2_P P4 N7 MD_CKE0 16 BI MC_DQSU_2_N MC_CAS_N OUT 15 16 17
13 BI MD_DQSU_2_P MD_CKE0 OUT 12 13 14 MC_DQSU_3_P AM9 AJ7 MC_RAS_N
A 13 BI MD_DQSU_2_N
MD_DQSU_3_P
P5
U1
MD_DQSU_2_N MD_CAS_N L10
M9
MD_CAS_N
MD_RAS_N OUT V_MEMIOCD
12 13 14
16
16
BI
BI MC_DQSU_3_N AM10
MC_DQSU_3_P
MC_DQSU_3_N
MC_RAS_N
MC_CS0_N AF9 MC_CS0_N OUT
OUT
15
15
16
16
17
17
A
13 BI MD_DQSU_3_P MD_RAS_N OUT MC_DML_0 AF1 AF4 MC_ODT0 1 R3R5
MD_DQSU_3_N V1 R7 MD_CS0_N EMPTY 15 BI MC_DML_0 MC_ODT0 OUT 15 16 17
13 BI MD_DQSU_3_N MD_CS0_N OUT 12 13 14 MC_DMU_0 AC4 AG7 MC_WE_N 40.2 OHM
MD_DML_0 A4 T5 MD_ODT0 15 BI MC_DMU_0 MC_WE_N OUT 15 16 17 1%
12 BI MD_DML_0 MD_ODT0 OUT 12 13 14 MC_DML_1 AM2 AA6 MC_RESET_N
MD_DMU_0 D7 P9 MD_WE_N 15 BI MC_DML_1 MC_RESET OUT 15 16
12 BI MD_DMU_0 MD_WE_N OUT 12 13 14 MC_DMU_1 AK7 AH7 2 CH
MD_DML_1 F2 Y9 MD_RESET_N 15 BI MC_DMU_1 MC_CKE1 402
12 BI MD_DML_1 MD_RESET OUT 12 13
MD_DMU_1 J6 H9 16 1 R2R6 BI MC_DML_2 AR6 MC_DML_2 MC_CS1_N AF7
12 BI MD_DMU_1 MD_CKE1 40.2 OHM MC_DMU_2 AR3 AG8
MD_DML_2 K2 F9 16 1% BI MC_DMU_2 MC_ODT1
13 BI MD_DML_2 MD_CS1_N MC_DML_3 AT10
13 MD_DMU_2 N8 MD_DMU_2 MD_ODT1 G10 2 CH
16 BI MC_DML_3 R3R4
BI MD_DML_3 U4 402 16 BI MC_DMU_3 AR9 MC_DMU_3 MC_VREFDQ AL7 MC_VREFDQ 1 2 MC_VREFDQ_MM
OUT
13 BI MD_DML_3 R2R5 MC_ZVDDIO AL10 0 OHM 5% MC_ZVDDIO
13 BI MD_DMU_3 R3 MD_DMU_3 MD_VREFDQ G7 MD_VREFDQ 1 2 MD_VREFDQ_MM
OUT 402 EMPTY
MD_ZVDDIO J7 0 OHM 5% MD_ZVDDIO
402 EMPTY X862035-001 BGA1443
X862035-001 BGA1443 DRAWING PAGE
[PAGE_TITLE=SOC MEMORY PARTITION A & B] Tue Jun 18 16:42:18 2013
CONFIDENTIAL GREYBULL_RETAIL 5/72 5/72 M 1.0
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
U7E1 IC
SOC, MEMORY PARTITION A + B U7E1 IC
22 MA_DQ63 AM28 MA_DQ63

MEM CHANNEL A
MB_DQ63 V37 MEM CHANNEL B BI MA_DQ62 AN31 8 of 17
19 BI MB_DQ63 22 BI MA_DQ62
19 MB_DQ62 N38 MB_DQ62
7 of 17 22 MA_DQ61 AP28 MA_DQ61
BI MB_DQ61 W38
BI MA_DQ60 AM30
19 BI MB_DQ60 P37 MB_DQ60 22 BI MA_DQ59 AR28 MA_DQ59
D 19 BI MB_DQ59
MB_DQ58
W36
N35
MB_DQ59 22 BI MA_DQ58
MA_DQ57
AM31
AN29
MA_DQ58 D
19 BI MB_DQ57 V38 MB_DQ57 22 BI MA_DQ56 AR32 MA_DQ56
19 BI MB_DQ56 N36 MB_DQ56 22 BI MA_DQ55 AV32 MA_DQ55
19 BI MB_DQ55 M37 MB_DQ55 22 BI MA_DQ54 AU28 MA_DQ54
19 BI MB_DQ54 Y38 MB_DQ54 22 BI MA_DQ53 AR31 MA_DQ53
19 BI MB_DQ53 M38 MB_DQ53 22 BI MA_DQ52 AV28 MA_DQ52
19 BI MB_DQ52 Y37 MB_DQ52 22 BI MA_DQ51 AT31 MA_DQ51
19 BI MB_DQ51 T38 MB_DQ51 22 BI MA_DQ50 AV29 MA_DQ50
19 BI MB_DQ50 W35 MB_DQ50 22 BI MA_DQ49 AR29 MA_DQ49
19 BI MB_DQ49 R35 MB_DQ49 22 BI MA_DQ48 AT29 MA_DQ48
19 BI MB_DQ48 U36 MB_DQ48 22 BI MA_DQ47 AN33 MA_DQ47
19 BI MB_DQ47 R33 MB_DQ47 22 BI MA_DQ46 AT37 MA_DQ46
19 BI MB_DQ46 M32 MB_DQ46 22 BI MA_DQ45 AM32 MA_DQ45
19 BI MB_DQ45 R31 MB_DQ45 22 BI MA_DQ44 AR36 MA_DQ44
19 BI MB_DQ44 N33 MB_DQ44 22 BI MA_DQ43 AP32 MA_DQ43
19 BI MB_DQ43 T35 MB_DQ43 22 BI MA_DQ42 AP37 MA_DQ42
19 BI MB_DQ42 M34 MB_DQ42 22 BI MA_DQ41 AR34 MA_DQ41
19 BI MB_DQ41 P32 MB_DQ41 22 BI MA_DQ40 AT38 MA_DQ40
19 BI MB_DQ40 M35 MB_DQ40 22 BI MA_DQ39 AU36 MA_DQ39
19 BI MB_DQ39 G35 MB_DQ39 22 BI MA_DQ38 AV33 MA_DQ38
19 BI MB_DQ38 L38 MB_DQ38 22 BI MA_DQ37 AV36 MA_DQ37
19 BI MB_DQ37 H37 MB_DQ37 22 BI MA_DQ36 AU32 MA_DQ36
MB_DQ36 L35 MA_DQ35 AR35
C 19
19
BI
BI MB_DQ35 H38
MB_DQ36
MB_DQ35
22
22
BI
BI MA_DQ34 AT33
MA_DQ35
MA_DQ34 C
19 BI MB_DQ34 L36 MB_DQ34 22 BI MA_DQ33 AV35 MA_DQ33
19 BI MB_DQ33 J35 MB_DQ33 22 BI MA_DQ32 AR33 MA_DQ32
19 BI MB_DQ32 K37 MB_DQ32 21 BI MA_DQ31 AL33 MA_DQ31
18 BI MB_DQ31 K34 MB_DQ31 21 BI MA_DQ30 AJ31 MA_DQ30
18 BI MB_DQ30 H34 MB_DQ30 21 BI MA_DQ29 AM34 MA_DQ29
18 BI MB_DQ29 L33 MB_DQ29 21 BI MA_DQ28 AJ33 MA_DQ28
18 BI MB_DQ28 H32 MB_DQ28 21 BI MA_DQ27 AM35 MA_DQ27
18 BI MB_DQ27 L31 MB_DQ27 21 BI MA_DQ26 AH35 MA_DQ26
18 BI MB_DQ26 H35 MB_DQ26 21 BI MA_DQ25 AL31 MA_DQ25
18 BI MB_DQ25 K35 MB_DQ25 21 BI MA_DQ24 AH34 MA_DQ24
18 BI MB_DQ24 G31 MB_DQ24 21 BI MA_DQ23 AJ35 MA_DQ23 V_MEMIOAB
18 BI MB_DQ23 C36 MB_DQ23 V_MEMIOAB 21 BI MA_DQ22 AP38 MA_DQ22 EMPTY
18 BI MB_DQ22 G36 MB_DQ22 EMPTY 21 BI MA_DQ21 AK38 MA_DQ21
18 BI MB_DQ21 C38 MB_DQ21 21 BI MA_DQ20 AR38 MA_DQ20
18 BI MB_DQ20 G38 MB_DQ20 21 BI MA_DQ19 AK37 MA_DQ19 1 R3T12
18 MB_DQ19 E35 MB_DQ19 1 R3T10 21 MA_DQ18 AM37 MA_DQ18 40.2 OHM
BI MB_DQ18 F38 40.2 OHM BI MA_DQ17 AM38 1%
18 BI MB_DQ18 1% 21 BI MA_DQ17
MB_DQ17 D38 MA_DQ16 AN38 2 EMPTY
18 BI MB_DQ17 21 BI MA_DQ16 402
MB_DQ16 E38 2 EMPTY MA_DQ15 AG36 AK28 MA_TEST
18 BI MB_DQ16 402 21 BI MA_DQ15 MA_TEST
18 BI MB_DQ15 D34 MB_DQ15 MB_TEST AJ28 MB_TEST 21 BI MA_DQ14 AB37 MA_DQ14
18 BI MB_DQ14 C31 MB_DQ14 21 BI MA_DQ13 AG35 MA_DQ13 1 R3T14
B 18 BI MB_DQ13
MB_DQ12
F34
B32
MB_DQ13
K30 MB_CLK0_DP
1 R3T13
40.2 OHM
21 BI MA_DQ12
MA_DQ11
AC38
AH38
MA_DQ12 MA_CLK0_DP AK30
AJ29
MA_CLK0_DP
MA_CLK0_DN OUT 21 22 40.2 OHM
1% B
18 BI MB_DQ12 MB_CLK0_DP OUT 18 19 1% 21 BI MA_DQ11 MA_CLK0_DN OUT 21 22
2 EMPTY
18 BI MB_DQ11 F35 MB_DQ11 MB_CLK0_DN J29 MB_CLK0_DN OUT 18 19 21 BI MA_DQ10 AB38 MA_DQ10 402
MB_DQ10 E31 2 EMPTY MA_DQ9 AG38 AC31 MA_A<15>
18 BI MB_DQ10 402 21 BI MA_DQ9 MA_A15 BI 21 22 23
18 BI MB_DQ9 G33 MB_DQ9 MB_A15 V32 MB_A<15> BI 18 19 20 21 BI MA_DQ8 AA35 MA_DQ8 MA_A14 AA32 MA_A<14> BI 21 22 23
18 BI MB_DQ8 D30 MB_DQ8 MB_A14 W29 MB_A<14> BI 18 19 20 21 BI MA_DQ7 AA38 MA_DQ7 MA_A13 AA29 MA_A<13> BI 21 22 23
18 BI MB_DQ7 A32 MB_DQ7 MB_A13 U29 MB_A<13> BI 18 19 20 21 BI MA_DQ6 AJ38 MA_DQ6 MA_A12 AC33 MA_A<12> BI 21 22 23
18 BI MB_DQ6 B36 MB_DQ6 MB_A12 W33 MB_A<12> BI 18 19 20 21 BI MA_DQ5 AA36 MA_DQ5 MA_A11 AB35 MA_A<11> BI 21 22 23
18 BI MB_DQ5 D33 MB_DQ5 MB_A11 Y34 MB_A<11> BI 18 19 20 21 BI MA_DQ4 AJ36 MA_DQ4 MA_A10 AE29 MA_A<10> BI 21 22 23
18 BI MB_DQ4 A36 MB_DQ4 MB_A10 N29 MB_A<10> BI 18 19 20 21 BI MA_DQ3 AE38 MA_DQ3 MA_A9 AC32 MA_A<9> BI 21 22 23
18 BI MB_DQ3 D35 MB_DQ3 MB_A9 V30 MB_A<9> BI 18 19 20 21 BI MA_DQ2 AH37 MA_DQ2 MA_A8 AB30 MA_A<8> BI 21 22 23
18 BI MB_DQ2 A35 MB_DQ2 MB_A8 W32 MB_A<8> BI 18 19 20 21 BI MA_DQ1 AD37 MA_DQ1 MA_A7 AD30 MA_A<7> BI 21 22 23
18 BI MB_DQ1 A33 MB_DQ1 MB_A7 U32 MB_A<7> BI 18 19 20 21 BI MA_DQ0 AF38 MA_DQ0 MA_A6 AA31 MA_A<6> BI 21 22 23
18 BI MB_DQ0 C35 MB_DQ0 MB_A6 Y32 MB_A<6> BI 18 19 20 21 BI MA_DQSL_0_P AE35 MA_DQSL_0_P MA_A5 AD34 MA_A<5> BI 21 22 23
18 BI MB_DQSL_0_P A34 MB_DQSL_0_P MB_A5 V35 MB_A<5> BI 18 19 20 21 BI MA_DQSL_0_N AE36 MA_DQSL_0_N MA_A4 AC29 MA_A<4> BI 21 22 23
18 BI MB_DQSL_0_N B34 MB_DQSL_0_N MB_A4 R29 MB_A<4> BI 18 19 20 21 BI MA_DQSL_1_P AL35 MA_DQSL_1_P MA_A3 AD32 MA_A<3> BI 21 22 23
18 BI MB_DQSL_1_P F37 MB_DQSL_1_P MB_A3 U31 MB_A<3> BI 18 19 20 21 BI MA_DQSL_1_N AL36 MA_DQSL_1_N MA_A2 AB34 MA_A<2> BI 21 22 23
18 BI MB_DQSL_1_N E36 MB_DQSL_1_N MB_A2 Y35 MB_A<2> BI 18 19 20 22 BI MA_DQSL_2_P AV34 MA_DQSL_2_P MA_A1 AB32 MA_A<1> BI 21 22 23
19 BI MB_DQSL_2_P K38 MB_DQSL_2_P MB_A1 W31 MB_A<1> BI 18 19 20 22 BI MA_DQSL_2_N AU34 MA_DQSL_2_N MA_A0 AE32 MA_A<0> BI 21 22 23
19 BI MB_DQSL_2_N J38 MB_DQSL_2_N MB_A0 T30 MB_A<0> BI 18 19 20 22 BI MA_DQSL_3_P AU30 MA_DQSL_3_P
19 BI MB_DQSL_3_P U38 MB_DQSL_3_P 22 BI MA_DQSL_3_N AV30 MA_DQSL_3_N MA_BA0 AE31 MA_BA<0> BI 21 22 23
19 BI MB_DQSL_3_N T37 MB_DQSL_3_N MB_BA0 T32 MB_BA<0> BI 18 19 20 21 BI MA_DQSU_0_P AC35 MA_DQSU_0_P MA_BA1 AD35 MA_BA<1> BI 21 22 23
18 BI MB_DQSU_0_P E33 MB_DQSU_0_P MB_BA1 V34 MB_BA<1> BI 18 19 20 21 BI MA_DQSU_0_N AC36 MA_DQSU_0_N MA_BA2 AE33 MA_BA<2> BI 21 22 23
18 BI MB_DQSU_0_N D32 MB_DQSU_0_N MB_BA2 U33 MB_BA<2> BI 18 19 20 21 BI MA_DQSU_1_P AK34 MA_DQSU_1_P
18 BI MB_DQSU_1_P J31 MB_DQSU_1_P 21 BI MA_DQSU_1_N AK35 MA_DQSU_1_N
MB_DQSU_1_N J33 MA_DQSU_2_P AN35 AH30 MA_CKE0 23 23
18 BI MB_DQSU_1_N 22 BI MA_DQSU_2_P MA_CKE0 OUT 22 21
19 BI MB_DQSU_2_P P35 MB_DQSU_2_P MB_CKE0 N32 MB_CKE0 OUT
20
19 22 BI MA_DQSU_2_N AN36 MA_DQSU_2_N MA_CAS_N AG29 MA_CAS_N OUT 21 22 V_MEMIOAB
MB_DQSU_2_N P34 L29 MB_CAS_N V_MEMIOAB MA_DQSU_3_P AR30 AJ32 MA_RAS_N EMPTY
19 BI MB_DQSU_2_N MB_CAS_N OUT 18 22 BI MA_DQSU_3_P MA_RAS_N OUT 21 22 23
MB_DQSU_3_P R38 M30 MB_RAS_N EMPTY MA_DQSU_3_N AP30 AF30 MA_CS0_N
A
19
19
BI
BI MB_DQSU_3_N P38
MB_DQSU_3_P
MB_DQSU_3_N
MB_RAS_N
MB_CS0_N R32 MB_CS0_N OUT
OUT
18
18
19
19
20
20
22
21
BI
BI MA_DML_0 AD38
MA_DQSU_3_N
MA_DML_0
MA_CS0_N
MA_ODT0 AF35 MA_ODT0 OUT
OUT
21 22
21 22
23
23
A
18 BI MB_DML_0 C33 MB_DML_0 MB_ODT0 T34 MB_ODT0 OUT 18 19 20 21 BI MA_DMU_0 AF37 MA_DMU_0 MA_WE_N AG32 MA_WE_N OUT 21 22 23 1 R3T17
18 MB_DMU_0 F32 MB_DMU_0 MB_WE_N P30 MB_WE_N 18 19 20 21 MA_DML_1 AL38 MA_DML_1 MA_RESET AA33 MA_RESET_N 21 22 40.2 OHM
BI MB_DML_1 D37 Y30 MB_RESET_N OUT 1 R2T1 BI MA_DMU_1 AK32 AH32
OUT 1%
18 BI MB_DML_1 MB_RESET OUT 18 19 40.2 OHM 21 BI MA_DMU_1 MA_CKE1
MB_DMU_1 K32 H30 1% MA_DML_2 AT35 AF32 2 CH
18 BI MB_DMU_1 MB_CKE1 22 BI MA_DML_2 MA_CS1_N 402
19 BI MB_DML_2 J36 MB_DML_2 MB_CS1_N F30 2 CH 22 BI MA_DMU_2 AP34 MA_DMU_2 MA_ODT1 AG31
19 BI MB_DMU_2 N31 MB_DMU_2 MB_ODT1 G29 402 22 BI MA_DML_3 AV31 MA_DML_3 R3T18 MA_VREFDQ_MM
19 BI MB_DML_3 R36 MB_DML_3 R2T2 22 BI MA_DMU_3 AM29 MA_DMU_3 MA_VREFDQ AL32 MA_VREFDQ 1 2 OUT
19 BI MB_DMU_3 U35 MB_DMU_3 MB_VREFDQ G32 MB_VREFDQ 1 2 MB_VREFDQ_MM
OUT MA_ZVDDIO AL29 0 OHM 5% MA_ZVDDIO
MB_ZVDDIO J32 0 OHM 5% MB_ZVDDIO 402 EMPTY
402 EMPTY X862035-001 BGA1443
X862035-001 BGA1443 PROJECT NAME PAGE CSA FAB REV
MICROSOFT PAGE
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
SOC VSS + SPARE
D IC
D
U7E1
VSS/SPARE U7E1 IC
16 of 17 VSS[360] H31
VSS[359] H27 VSS VSS[461] A38
VSS[358] H25 17 of 17 VSS[460] A37
VSS[357] H23 VSS[459] A28
M13 VSS[300] VSS[356] H21 VSS[458] A26
M11 VSS[299] VSS[355] H19 VSS[457] A24
M8 VSS[298] VSS[354] H17 VSS[456] A22
M6 VSS[297] VSS[353] H15 VSS[455] A20
N30 VSS[296] VSS[352] H13 VSS[454] A18
N28 VSS[295] VSS[351] H11 VSS[453] A16
N26 VSS[294] VSS[350] H8 VSS[452] A14
N24 VSS[293] VSS[349] H6 VSS[451] A12
N22 VSS[292] VSS[348] J30 VSS[450] A2
N20 VSS[291] VSS[347] J28 VSS[449] B38
N18 VSS[290] VSS[346] J26 VSS[448] B37
N16 VSS[289] VSS[345] J24 VSS[447] B35
N14 VSS[288] VSS[344] J22 VSS[446] B33
N12 J20 B28
C N9
VSS[287]
VSS[286]
VSS[343]
VSS[342] J18
VSS[445]
VSS[444] B26 C
P36 VSS[285] VSS[341] J16 VSS[443] B24
P31 VSS[284] VSS[340] J14 VSS[442] B22
P28 VSS[283] VSS[339] J12 VSS[441] B20
P26 VSS[282] VSS[338] J9 VSS[440] B18
P24 VSS[281] VSS[337] K36 VSS[439] B16
P22 VSS[280] VSS[336] K31 E26 VSS[399] VSS[438] B14
P8 VSS[274] VSS[330] K18 E14 VSS[393] VSS[432] C37
P3 VSS[273] VSS[329] K16 E12 VSS[392] VSS[431] C34
R37 VSS[272] VSS[328] K14 E9 VSS[391] VSS[430] C32
R34 VSS[271] VSS[327] K12 E2 VSS[390] VSS[429] C29
R30 VSS[270] VSS[326] K8 F36 VSS[389] VSS[428] C27
R27 VSS[269] VSS[325] K3 F31 VSS[388] VSS[427] C25
R25 VSS[268] VSS[324] L37 F28 VSS[387] VSS[426] C23
B R17
R15
VSS[264] VSS[320] L25
L23
F20
F18
VSS[383] VSS[422] C15
C13 B
VSS[263] VSS[319] VSS[382] VSS[421]
R2 VSS[258] VSS[314] L13 F3 VSS[377] VSS[416] D36
T33 VSS[257] VSS[313] L11 G37 VSS[376] VSS[415] D31
T23 VSS[253] VSS[309] M33 G25 VSS[372] VSS[411] D23
T6 M15 EMPTY G9 D3
VSS[245] VSS[301] VSS[364] VSS[403]
U30 L7 SOC_SPARE4 EMPTY
1 G5 E37
VSS[244] SPARE4 DB2R1 VSS[363] VSS[402]
U28 VSS[243] SPARE3 L32 SOC_SPARE3 1 G2 VSS[362] VSS[401] E30
DB2T1
U26 VSS[242] SPARE2 AG33 SOC_SPARE2 H33 VSS[361] VSS[400] E28
U24 AG6 SOC_SPARE1
BI
VSS[241] SPARE1 BI
X862035-001 BGA1443
X862035-001 BGA1443
A A

CONFIDENTIAL
PAGE
7/72 M 1.0
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
SOC DEBUG + SB SIGNALS

V_SOC1P8
1 R4R22
D 10 KOHM
5% IC
D
2 CH
U7E1
402 JTAG/DEBUG
4 of 17
1 R3R18
10 KOHM ATE_TSTCLK_EN AK11 ATE_TSTCLK_EN
5% BI AL24 DLY_PSP_RESET
2 EMPTY AM22 TMON_CAL1
402 TMON_CAL1 BI
A0_BYPASS AK16 A0_BYPASS TMON_CAL0 AM20 TMON_CAL0
BI
26 SOC_THERMTRIP AN15 THERMTRIP*
OUT
R3T7
1 2 X32K_X2 AM23 X32K_X2
0 OHM 5% X32K_X1_R AN24 X32K_X1
402 EMPTY 1 R3T8
0 OHM DB651 GPIO_3P3_3 AK19 NEW_GPIO13
BI GPIO_3P3_2 AN25
1
5% BI NEW_GPIO12
2 CH GPIO_3P3_1 AK21 NEW_GPIO11 PSEN AG13
402
BI VREG_BURN_EN AK20
58 BI NEW_GPIO10
R3T951 VREG_MEMCORE_VID1 AL21 NEW_GPIO9
X32K_X1 1 2
OUT VREG_MEMCORE_VID0 AL20
29 IN 51 OUT NEW_GPIO8
0 OHM 5% GPIO_1P8_1 AM19 NEW_GPIO7
402 EMPTY GPIO_1P8_0 AM17
C BI
BI GPIO_POSTOUT_5 AM26
NEW_GPIO6
NEW_GPIO5 C
GPIO_POSTOUT_4 AR25 NEW_GPIO4
BI GPIO_POSTOUT_3 AP27
BI NEW_GPIO3
GPIO_POSTOUT_2 AP26 NEW_GPIO2
BI GPIO_POSTOUT_1 AR26
V_SOC1P8
BI NEW_GPIO1
GPIO_POSTOUT_0 AT27 NEW_GPIO0
BI
DBREQ_L AK26
1 R5T13
68 IN DBREQ_N 10 KOHM
68 DBRDY AL26 DBRDY 5%
OUT TRST_L AN27
68 IN TRST_N 2 CH
68 TMS AK24 TMS 402
IN TDO AK25
68 OUT TDO
68 TDI AK22 TDI
IN TCK AL23 AN16 SP_SMC_INT_N
68 IN TCK ALERT_N OUT 26
68 26 SOC_RST_N AR17 RESET_N SVT E10 SVT 44 R3T4

V_SOC1P8 IN SOC_PWR_OK AR16 C9 SVD
IN 2 1 SB_SOC_DATA
26 IN PWROK SVD BI 44 BI 26
SVC F10 SVC 44 1% 243 OHM
SOC_TEST32_P AL18 AP18 SID
OUT CH 402
BI TEST32_P SID
1 R3T21 BI SOC_TEST32_N AK18 TEST32_N SIC AP17 SIC
10 KOHM SOC_TEST30_P AK17 TEST30_P RTCCLK AK27 RTCCLK R3T2
5% BI AL17
BI 2 1 SB_SOC_CLK
DB3T4 BI SOC_TEST30_N TEST30_N IN 26
B 2 EMPTY AL15 AH11 M_VREF
1
BI
402 BI
BI
SOC_TEST28_P
SOC_TEST28_N AK15
TEST28_P
TEST28_N
M_VREF IN 8 1% 243 OHM
CH 402 B
70 68 TEST19 AJ21 TEST19 VDDCR_MEM_SENSE AE19 SOC_MEMCORE_S
1 R3T22 IN TEST18 AL27 AF5 SOC_MEMIOAB_S
BI
10 KOHM 70 68 IN TEST18 VDD_MEM0_SENSE BI
5% TEST17 AL11 TEST17 VDD_MEM1_SENSE AF34 SOC_MEMIOCD_S
OUT TEST16 AK13 B8 SOC_GFXCPU_S_RTN
BI
2 CH OUT TEST16 VSS_GFX_SENSE OUT 8 44
402 TEST15 AL14 TEST15 VDD_GFX_SENSE B9 SOC_GFXCORE_S 8 45 V_SOCPHY
OUT TEST14 AM16
OUT
OUT TEST14
TEST10 AK12 TEST10 VDD_NB_SENSE AC25 SOC_NBCORE_S
IN TEST9 AM14
BI
IN TEST9
SOC_TEST6 AJ22 TEST6 VDD_CORE_SENSE A8 SOC_CPUCORE_S 8 44
BI SOC_TEST5 AK14 AG17
OUT
BI TEST5 VDD_095_SENSE
SOC_TEST4 AL13 TEST4
BI
X862035-001 BGA1443
V_MEMIOCD
EMPTY
V_CPUCORE
1 R3R3 EMPTYV_GFXCORE
1 KOHM EMPTY EMPTY
EMPTY
1%
2 CH 8 SOC_CPUCORE_S EMPTY
1 EMPTY
1
402 M_VREF
IN SOC_GFXCORE_S EMPTY
1
DB2R6 DB1T2 EMPTY
1
A 1 R3R2
OUT 8 8
8
IN
IN SOC_GFXCPU_S_RTN 1
DB2R2
DB2R3
DB2R4
DB2R5
1 A
1 KOHM 1 C3R20
1% 1 UF
2 CH 10%
402 6.3 V
2 X5R
402

CONFIDENTIAL
PAGE
8/72 M 1.0
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
SOC, DECOUPLING
V_GFXCORE 42 0805 22UF
EMPTY
D V_GFXCORE
EMPTY
44 0805 10UF D
C2T17 C8E3 C2T36 C2R20
1 2 1 2 1 2 1 2
22 UF 20% 22 UF 20% 22 UF 20% 22 UF 20% C3R19 C3R16 C2R28 C2T21 C2T26
6.3 V 6.3 V 6.3 V 6.3 V 1 2 1 2 1 2 1 2 1 2
X7R X7R X7R X7R
805 805 805 805 10 UF 10% 10 UF 10% 10 UF 10% 10 UF 10% 10 UF 10%
6.3 V 6.3 V 6.3 V 6.3 V 6.3 V
X5R X5R X5R X5R X5R
805 805 805 805 805
C2T39 C2R34 C2R10 C2R21
1 2 1 2 1 2 1 2
22 UF 20% 22 UF 20% 22 UF 20% 22 UF 20% C2T4 C2T9 C2R27 C2T20 C2T25
6.3 V 6.3 V 6.3 V 6.3 V 1 2 1 2 1 2 1 2 1 2
X7R X7R X7R X7R
805 805 805 805 10 UF 10% 10 UF 10% 10 UF 10% 10 UF 10% 10 UF 10%
6.3 V 6.3 V 6.3 V 6.3 V 6.3 V
X5R X5R X5R X5R X5R
C2T14 805 805 805 805 805
C2T32 C2R38 1 2 C2R39
1 2 1 2 1 2
22 UF 20% 22 UF 20% C2R26
22 UF 20% 6.3 V 22 UF 20% C2T3 C2T8 1 2 C2T19
6.3 V 6.3 V X7R 6.3 V 1 2 1 2 1 2 C2T44
X7R X7R 805 X7R 1 2
805 805 805 10 UF 10%
C 10 UF 10%
6.3 V
X5R
10 UF 10%
6.3 V
X5R
6.3 V
X5R
10 UF 10%
6.3 V
X5R
10 UF 10%
6.3 V C
805 X5R
C2T33 805 805 805 805
C2R33 C2T11 C2T34 1 2
1 2 1 2 1 2
22 UF 20% C2T42
22 UF 20% 22 UF 20% 22 UF 20% C2T18 1 2
6.3 V C2T2 C2T40 C2R25 1 2
6.3 V 6.3 V 6.3 V X7R 1 2 1 2 1 2
X7R X7R X7R 805 10 UF 10%
805 805 805 10 UF 10% 6.3 V
10 UF 10% 10 UF 10% 10 UF 10% 6.3 V X5R
6.3 V 6.3 V 6.3 V X5R 805
X5R X5R X5R 805
C2R35 805 805 805
C2R16 1 2 C2T15
C2T10 1 2 1 2
1 2
22 UF 20% C2T27
22 UF 20% 22 UF 20% C2R24 1 2
22 UF 20% 6.3 V C2T24 1 2 C2T45
6.3 V X7R 6.3 V C2T1 1 2 1 2
6.3 V X7R 805 X7R 1 2 10 UF 10%
X7R 805 805 10 UF 10% 6.3 V
805 10 UF 10% 6.3 V 10 UF 10% X5R
10 UF 10% 6.3 V X5R 6.3 V
6.3 V X5R X5R 805
X5R 805
805 805
C2R23 C8D5 C2T12 C2R37 805
1 2 1 2 1 2 1 2
22 UF 20% 22 UF 20% 22 UF 20% 22 UF 20% C3T3 C3T4 C2T5 C2T43
6.3 V 6.3 V 6.3 V 6.3 V 1 2 1 2 1 2 1 2
X7R X7R X7R X7R
805 805 805 805
B 10 UF 10%
6.3 V
X5R
10 UF 10%
6.3 V
X5R
10 UF 10%
6.3 V
X5R
10 UF 10%
6.3 V
X5R B
805 805 805 805
C2R9 C2T13 C2T37 C2R36
1 2 1 2 1 2 1 2
22 UF 20% 22 UF 20% 22 UF 20% 22 UF 20% C3R18 C2R32 C2T6 C2T31
6.3 V 6.3 V 6.3 V 6.3 V 1 2 1 2 1 2 1 2
X7R X7R X7R X7R
805 805 805 805 10 UF 10% 10 UF 10% 10 UF 10% 10 UF 10%
6.3 V 6.3 V 6.3 V 6.3 V
X5R X5R X5R X5R
805 805 805 805
C2R13 C2T38 C2R22 C2T35
1 2 1 2 1 2 1 2
22 UF 20% 22 UF 20% 22 UF 20% 22 UF 20% C3R17 C2R31 C2T7 C2T30
6.3 V 6.3 V 6.3 V 6.3 V 1 2 1 2 1 2 1 2
X7R X7R X7R X7R
805 805 805 805 10 UF 10% 10 UF 10% 10 UF 10% 10 UF 10%
6.3 V 6.3 V 6.3 V 6.3 V
X5R X5R X5R X5R
805 805 805 805
C8D3 C2R18 C8D6 C2R11
1 2 1 2 1 2 1 2
22 UF 20% 22 UF 20% 22 UF 20% 22 UF 20% C2T41 C2R30 C2T23 C2T29
6.3 V 6.3 V 6.3 V 6.3 V 1 2 1 2 1 2 1 2
X7R X7R X7R X7R
805 805 805 805 10 UF 10% 10 UF 10% 10 UF 10% 10 UF 10%
6.3 V 6.3 V 6.3 V 6.3 V
X5R X5R X5R X5R
C8E2 805 805 805 805
C2R12 C2R19 1 2 C2R17
1 2 1 2 1 2
22 UF 20% C2T22
22 UF 20% 22 UF 20% 6.3 V 22 UF 20% C2R29 1 2 C2T28
6.3 V 6.3 V X7R 6.3 V 1 2 1 2
A X7R
805
X7R
805
805 X7R
805 10 UF 10%
A
10 UF 10% 6.3 V 10 UF 10%
6.3 V X5R 6.3 V
X5R 805 X5R
805 805
C2R40 C2T16
1 2 1 2
22 UF 20% 22 UF 20%
6.3 V 6.3 V
X7R X7R
805 805

PAGE
[PAGE_TITLE=GCPU, DECOUPLING] DRAWING
CONFIDENTIAL
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
SOC, DECOUPLING
V_CPUCORE 10 0805 22UF
EMPTY V_NBCORE
13 0805 10UF V_SOCPHY EMPTY
EMPTY V_MEMCORE
D EMPTY D
C2T61 C2T66 C8E7
1 2 1 2
C3T27
C3T8 1 2 C5U8
10 UF 10% 22 UF 20% 22 UF 20% 1 2 1 2
C3T21 C5T3
6.3 V 6.3 V 6.3 V 1 UF 10% 1 2 1 2
C3T33 X5R X7R X7R 1 UF 10% 22 UF 20%
2 1 6.3 V
805 805 805 6.3 V X5R 6.3 V 4.7 UF 20% 22 UF 20%
X5R 402 X7R 6.3 V 6.3 V
10% 10 UF 402 805 X5R X7R
6.3 V C3T29 402 805
X5R C2T60 C2T67 C8E9 C3T15 1 2 C4U6
805 1 2 1 2 1 2 1 2
1 UF 10%
10 UF 10% 22 UF 20% 22 UF 20% 1 UF 10% 6.3 V 22 UF 20% C3T19 C5T2
6.3 V 6.3 V 6.3 V 6.3 V X5R 6.3 V 1 2 1 2
C2T68 X5R X7R X7R X5R 402 X7R
2 1 805 805 805 402 805 4.7 UF 20% 22 UF 20%
C3T30 6.3 V 6.3 V
10% 10 UF C3T16 1 2 C4U7 X5R X7R
1 2 1 2
6.3 V C2T80 402 805
X5R C2T59 C2T51 1 2 1 UF 10%
1 2 1 2 1 UF 10% 22 UF 20%
805 6.3 V C3T53 C5T1
22 UF 20% 6.3 V X5R 6.3 V 1 2 1 2
10 UF 10% 22 UF 20% 6.3 V X5R 402 X7R
6.3 V 6.3 V X7R 402 805 4.7 UF 20% 22 UF 20%
X5R X7R 805 6.3 V 6.3 V
805 805 C3T28 X5R X7R
C 1
C3T12
2
1 2
1
C5U7
2 402 805 C
C8E4 1 UF 10%
C2T58 C2T62 1 2 1 UF 10% 6.3 V 22 UF 20% C3T23 C4T20
1 2 1 2 6.3 V X5R 6.3 V 1 2 1 2
X5R 402 X7R
22 UF 20% 402 805
10 UF 10% 22 UF 20% 6.3 V 4.7 UF 20% 22 UF 20%
6.3 V 6.3 V X7R C3T25 6.3 V 6.3 V
X5R X7R C3T11 1 2 C4U8 X5R X7R
805 1 2 1 2
805 805 402 805
1 UF 10%
1 UF 10% 6.3 V 22 UF 20% C3T20 C4T19
6.3 V X5R 6.3 V 1 2 1 2
C8E6 X5R X7R
C2T57 C2T49 1 2 402
1 2 1 2 402 805 4.7 UF 20% 22 UF 20%
22 UF 20% C3T26 6.3 V 6.3 V
10 UF 10% 22 UF 20% 1 2 C5F14 X5R X7R
6.3 V 1 2
6.3 V 6.3 V X7R 402 805
X5R X7R 805 1 UF 10%
805 805 6.3 V 22 UF 20% C3T22
X5R 6.3 V 1 2
402 EMPTY
805 4.7 UF 20%
C2T47
C2T56 C2T63 1 2 C3T36 6.3 V
1 2 1 2 1 2 C5F13 X5R
1 2
22 UF 20% 402
10 UF 10% 22 UF 20% 6.3 V 1 UF 10%
6.3 V 6.3 V X7R 6.3 V 22 UF 20% C3T5
X5R X7R X5R 6.3 V 1 2
805 EMPTY
805 805 402
B C3T24
805 22 UF 20%
4 V B
1 2 C6F10 X5R
C2T71 1 2
C2T55 C2T64 1 2 603
1 2 1 2 1 UF 10%
6.3 V 22 UF 20% C3T1
22 UF 20% X5R 6.3 V 1 2
10 UF 10% 22 UF 20% 6.3 V EMPTY
6.3 V 6.3 V X7R 402
X5R X7R 805 22 UF 20%
805
805 805 4 V
C3T35 X5R
1 2 C6F8
1 2 603
C2T46 1 UF 10%
C2T54 C2T65 1 2 22 UF 20% C3T56
1 2 1 2 6.3 V 1 2
X5R 6.3 V
22 UF 20% 402 EMPTY
10 UF 10% 22 UF 20% 6.3 V 805 22 UF 20%
6.3 V 6.3 V X7R C3T31 4 V
X5R X7R 805 1 2 C6F7 X5R
805 805 1 2 603
1 UF 10% C3T57
6.3 V 22 UF 20% 1 2
C2T72 X5R 6.3 V
C2T53 C2T52 1 2 EMPTY
1 2 1 2 402 22 UF 20%
805
22 UF 20% 4 V
10 UF 10% 22 UF 20% 6.3 V X5R
6.3 V 6.3 V X7R C3T32 603
X5R X7R 1 2
805
805 805 C3T6
10 UF 10% 1 2
6.3 V
C2T48 X5R 22 UF 20%
C3T34 C2T50 1 2 805 4 V
1 2 1 2 X5R
22 UF 20% 603
10 UF 10% 22 UF 20% 6.3 V
6.3 V 6.3 V X7R
A X5R
805
X7R
805
805 A
I75 I73
C2T70
1 2
22 UF 20%
6.3 V
X7R
805
C2T73
1 2
22 UF 20%
6.3 V
X7R
805 MICROSOFT PROJECT NAME PAGE CSA FAB REV
PAGE
[PAGE_TITLE=GCPU, DECOUPLING] CONFIDENTIAL GREYBULL_RETAIL 10/72 10/72 M 1.0
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
SOC, DECOUPLING
D D
V_MEMIOCD V_MEMIOAB
EMPTY
EMPTY
V_MEMIOCD V_MEMIOAB
EMPTY EMPTY
C3R7 C2R7 C3T38 C2T74

1 2 1 2 C3R3 1 2 1 2
1 2 C2T81
1 2
0.22 UF 10% 0.22 UF 10% 0.22 UF 10% 0.22 UF 10%
6.3 V 6.3 V 10 UF 20% 6.3 V 6.3 V
X5R X5R 6.3 V X5R X5R 10 UF 20%
402 402 X5R 402 402 6.3 V
805 X5R
805
C2R4 C3R5 C3T40 C2T77
1 2 1 2 1 2 1 2
0.22 UF 10% 0.22 UF 10% C3R2 0.22 UF 10% 0.22 UF 10%
1 2 C2T82
6.3 V 6.3 V 6.3 V 6.3 V 1 2
X5R X5R X5R X5R
402 402 10 UF 20% 402 402
6.3 V 10 UF 20%
C3R10 C3R14 X5R C3T49 C3T46 6.3 V
1 2 1 2 805 1 2 1 2 X5R
C 805
C
0.22 UF 10% 0.22 UF 10% 0.22 UF 10% 0.22 UF 10%
6.3 V 6.3 V C2R1 6.3 V 6.3 V
X5R X5R 1 2 X5R X5R C3T52
402 402 402 402 1 2
C3R9 C3R6 10 UF 20% C3T50 C3T45
1 2 1 2 6.3 V 1 2 1 2 10 UF 20%
X5R 6.3 V
805 X5R
0.22 UF 10% 0.22 UF 10% 0.22 UF 10% 0.22 UF 10% 805
6.3 V 6.3 V 6.3 V 6.3 V
X5R X5R X5R X5R
402 402 402 402
C2R2
1 2 C3T51
C3R8 C2R8 C3T42 C2T78 1 2
1 2 1 2 1 2 1 2
10 UF 20%
6.3 V 10 UF 20%
0.22 UF 10% 0.22 UF 10% X5R 0.22 UF 10% 0.22 UF 10% 6.3 V
6.3 V 6.3 V 805 6.3 V 6.3 V X5R
X5R X5R X5R X5R 805
402 402 402 402
C3R11 C3R4 C3T41 C3T48
1 2 1 2 1 2 1 2
0.22 UF 10% 0.22 UF 10% 0.22 UF 10% 0.22 UF 10%
6.3 V 6.3 V 6.3 V 6.3 V
X5R X5R X5R X5R
402 402 402 402
B 1
C3R12
2 1
C3R15
2 1
C2T69
2 1
C3T44
2 V_MEMIOAB B
V_MEMIOCD EMPTY
0.22 UF 10% 0.22 UF 10% EMPTY 0.22 UF 10% 0.22 UF 10%
6.3 V 6.3 V 6.3 V 6.3 V
X5R X5R X5R X5R
402 402 402 402
C2R3 C2R15 C3T39 C2T75
1 2 1 2 1 2 1 2
C3T54
0.22 UF 10% 0.22 UF 10% 0.22 UF 10% 0.22 UF 10% 1 2
C2R42
6.3 V 6.3 V 1 2 6.3 V 6.3 V
X5R X5R X5R X5R 1 UF 10%
402 402 1 UF 10% 402 402 6.3 V
6.3 V X5R
C2R5 C2R14 X5R C2T79 C3T47 402
1 2 1 2 1 2 1 2
402
C2T83
0.22 UF 10% 0.22 UF 10% 0.22 UF 10% 0.22 UF 10% 1 2
C2R41
6.3 V 6.3 V 1 2 6.3 V 6.3 V
X5R X5R X5R X5R 1 UF 10%
402 402 1 UF 10% 402 402 6.3 V
6.3 V X5R
C2R6 C3R13 X5R C2T76 C3T43 402
1 2 1 2 1 2 1 2
402
0.22 UF 10% 0.22 UF 10% 0.22 UF 10% 0.22 UF 10% C2T84
1 2
6.3 V 6.3 V C3R28 6.3 V 6.3 V
X5R X5R 1 2 X5R X5R
402 402 402 402 1 UF 10%
1 UF 10% 6.3 V
6.3 V X5R
X5R 402
402
C3T55
1 2
C3R27
1 2
A 1 UF 10%
6.3 V
A
1 UF 10% X5R
6.3 V 402
X5R
402

PAGE
[PAGE_TITLE=GCPU, DECOUPLING] CONFIDENTIAL GREYBULL_RETAIL 11/72 11/72 M 1.0
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
V_MEMIOCD
EMPTY
MEMORY CHANNEL D V_MEMIOCD
EMPTY
U9C1 MEM U8C5 MEM
DDR3_4GBIT_X16 BYTE LANE 0 V_MEMIOCD
BYTE LANE 2 V_MEMIOCD DDR3_4GBIT_X16
D BYTE LANE 1 EMPTY
BYTE LANE 3 EMPTY D
1 R8C23 1 R8C20
R9 VDD9 NC4 L9 1 KOHM 1 KOHM R9 VDD9 NC4 L9
R1 VDD8 NC3 L1 1% 1% R1 VDD8 NC3 L1
N9 J9 2 CH 2 CH N9 J9
VDD7 NC2 402 MD_VREFCAA 402MD_VREFCAB VDD7 NC2
N1 J1 OUT 12 OUT 12 N1 J1
VDD6 NC1 VDD6 NC1
K8 VDD5 1 R8C24 1 R8C19 1 K8 VDD5
K2 VDD4 VSS12 T9 1 KOHM 1 C8C12 1 KOHM C8C11 K2 VDD4 VSS12 T9
1% 1% 1 UF
G7 VDD3 VSS11 T1 1 UF 10% G7 VDD3 VSS11 T1
2 CH 10% 2 CH 6.3 V
D9 VDD2 VSS10 P9 6.3 V 2 X5R D9 VDD2 VSS10 P9
B2 P1
402 2 X5R 402 402 B2 P1
VDD1 VSS9 402 VDD1 VSS9
VSS8 M9 VSS8 M9
VSS7 M1 VSS7 M1
VSS6 J8 VSS6 J8
VSS5 J2 VSS5 J2
H9 VDDQ9 VSS4 G8 H9 VDDQ9 VSS4 G8
H2 VDDQ8 VSS3 E1 H2 VDDQ8 VSS3 E1
F1 VDDQ7 VSS2 B3 V_MEMIOCD V_MEMIOCD F1 VDDQ7 VSS2 B3
E9 VDDQ6 VSS1 A9 EMPTY EMPTY E9 VDDQ6 VSS1 A9
D2 VDDQ5 D2 VDDQ5
C9 VDDQ4 VSSQ9 G9 1 R9C47 1 R8C38 C9 VDDQ4 VSSQ9 G9
C1 VDDQ3 VSSQ8 G1 1 KOHM 1 KOHM C1 VDDQ3 VSSQ8 G1
A8 F9 1% 1% A8 F9
C A1
VDDQ2
VDDQ1
VSSQ7
VSSQ6 E8 2 CH
402 MD_VREFDQA
2 CH
402 MD_VREFDQB
A1
VDDQ2
VDDQ1
VSSQ7
VSSQ6 E8 C
E2 OUT 12 OUT 12 E2
VSSQ5 VSSQ5
VSSQ4 D8 1 R9C46 1 R8C37 1 VSSQ4 D8
VSSQ3 D1 1 KOHM 1 C1P14 1 KOHM C2P16 VSSQ3 D1
1% 1% 1 UF
VSSQ2 B9 1 UF 10% VSSQ2 B9
2 CH 10% 2 CH 6.3 V
VSSQ1 B1 6.3 V 2 VSSQ1 B1
402 2 X5R 402 X5R
402
402
X866978-001 BGA96 X866978-001 BGA96
U9C1,U8C5 EMPTY EMPTY MEMORY DUMMY_BOM
MD_CLK_TERM_RC
R1P22 1 1
36.5 OHM C1P19
1% 0.1 UF
CH 2 10%
U9C1 MEM 402 6.3 V U8C5 MEM
R1P23 1 2 X5R
DDR3_4GBIT_X16 36.5 OHM 402 DDR3_4GBIT_X16
1%
5 BI MD_DQSU_0_P C7 DQSU_P CH 2 5 BI MD_DQSU_1_P C7 DQSU_P
5 BI MD_DQSU_0_N B7 DQSU_N 402 5 BI MD_DQSU_1_N B7 DQSU_N
MD_DQSL_0_P F3 J7 MD_CLK0_DP MD_DQSL_1_P F3 J7 MD_CLK0_DP
B 5
5
BI
BI MD_DQSL_0_N G3
DQSL_P
DQSL_N
CK_P
CK_N K7 MD_CLK0_DN IN
IN
5
5
5
5
BI
BI MD_DQSL_1_N G3
DQSL_P
DQSL_N
CK_P
IN
5
5 B
5 IN MD_RESET_N T2 RESET_N 5 IN MD_RESET_N T2 RESET_N
5 IN MD_A<15..0> 5 IN MD_A<15..0>
15 M7 A15 15 M7 A15
14 T7 A14 14 T7 A14
13 T3 A13 13 T3 A13
12 N7 A12 DQU7 A3 MD_DQ15 BI 5 12 N7 A12 DQU7 A3 MD_DQ31 BI 5
11 R7 A11 DQU6 B8 MD_DQ14 BI 5 11 R7 A11 DQU6 B8 MD_DQ30 BI 5
10 L7 A10 DQU5 A2 MD_DQ13 BI 5 10 L7 A10 DQU5 A2 MD_DQ29 BI 5
9 R3 A9 DQU4 A7 MD_DQ12 BI 5 9 R3 A9 DQU4 A7 MD_DQ28 BI 5
8 T8 A8 DQU3 C2 MD_DQ11 BI 5 8 T8 A8 DQU3 C2 MD_DQ27 BI 5
7 R2 A7 DQU2 C8 MD_DQ10 BI 5 7 R2 A7 DQU2 C8 MD_DQ26 BI 5
5 P2 A5 DQU0 D7 MD_DQ8 BI 5 5 P2 A5 DQU0 D7 MD_DQ24 BI 5
4 P8 A4 4 P8 A4
3 N2 A3 3 N2 A3
2 P3 A2 DQL7 H7 MD_DQ7 BI 5 2 P3 A2 DQL7 H7 MD_DQ23 BI 5
1 P7 A1 DQL6 G2 MD_DQ6 BI 5 1 P7 A1 DQL6 G2 MD_DQ22 BI 5
0 N3 A0 DQL5 H8 MD_DQ5 BI 5 0 N3 A0 DQL5 H8 MD_DQ21 BI 5
MD_BA<2..0> DQL4 H3 MD_DQ4 BI 5 MD_BA<2..0> DQL4 H3 MD_DQ20 BI 5
5 IN 2 M3 F8 MD_DQ3 5 IN 2 M3 F8 MD_DQ19
BA2 DQL3 BI 5 BA2 DQL3 BI 5
1 N8 BA1 DQL2 F2 MD_DQ2 BI 5 1 N8 BA1 DQL2 F2 MD_DQ18 BI 5
0 M2 BA0 DQL1 F7 MD_DQ1 BI 5 0 M2 BA0 DQL1 F7 MD_DQ17 BI 5
DQL0 E3 MD_DQ0 BI 5 DQL0 E3 MD_DQ16 BI 5
5 IN MD_WE_N L3 WE_N 5 IN MD_WE_N L3 WE_N
5 IN MD_CAS_N K3 CAS_N 5 IN MD_CAS_N K3 CAS_N
5 IN MD_RAS_N J3 RAS_N CKE K9 MD_CKE0 IN 5 5 IN MD_RAS_N J3 RAS_N CKE K9 MD_CKE0 IN 5
5 IN MD_DMU_0 D3 DMU CS_N L2 MD_CS0_N IN 5 5 IN MD_DMU_1 D3 DMU CS_N L2 MD_CS0_N IN 5
A 5 IN MD_DML_0 E7 DML
K1 MD_ODT0
5 IN MD_DML_1 E7 DML
K1 MD_ODT0
A
ODT IN 5 ODT IN 5
12 IN MD_VREFCAA M8 VREFCA ZQ L8 MD_ZQ0 12 IN MD_VREFCAB M8 VREFCA ZQ L8 MD_ZQ1
12 IN MD_VREFDQA H1 VREFDQ 1 R8C29 12 IN MD_VREFDQB H1 VREFDQ 1 R8C28
243 OHM
243 OHM 1%
X866978-001 BGA96 1% X866978-001 BGA96 2 CH
2 CH 402
402

DRAWING PAGE
[PAGE_TITLE=MEMORY PARTITION A, LOW] CONFIDENTIAL
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
V_MEMIOCD
MEMORY CHANNEL D
EMPTY
BYTE LANE 4 BYTE LANE 6
U8C4 MEM BYTE LANE 5 V_MEMIOCD BYTE LANE 7 V_MEMIOCD V_MEMIOCD
D DDR3_4GBIT_X16 EMPTY EMPTY EMPTY
U8C3 MEM D
DDR3_4GBIT_X16
1 R8C17 1 R7C5
1 KOHM 1 KOHM
R9 VDD9 NC4 L9
1% 1%
R1 VDD8 NC3 L1 2 CH
2 CH R9 VDD9 NC4 L9
N9 VDD7 NC2 J9
402 402 R1 L1
N1 J1 MD_VREFCAD VDD8 NC3
VDD6 NC1 MD_VREFCAC OUT 13 N9 J9
K8 OUT 13 VDD7 NC2
VDD5 N1 J1
K2 T9 1 R7C4 VDD6 NC1
VDD4 VSS12 1 R8C16 1 K8
G7 VDD3 VSS11 T1 1 KOHM 1 1 KOHM C7C6 VDD5
D9 VDD2 VSS10 P9 1% C8C10 1% 1 UF K2 VDD4 VSS12 T9
1 UF 2 CH 10% G7 VDD3 VSS11 T1
B2 VDD1 VSS9 P1 2 CH 10% 6.3 V
M9 402 6.3 V 402 2 X5R D9 VDD2 VSS10 P9
VSS8 2 X5R 402 B2 P1
M1 402 VDD1 VSS9
VSS7 M9
J8 VSS8
VSS6 M1
J2 VSS7
VSS5 J8
H9 G8 VSS6
VDDQ9 VSS4 J2
H2 E1 VSS5
VDDQ8 VSS3 H9 G8
F1 B3 V_MEMIOCD VDDQ9 VSS4
VDDQ7 VSS2 H2 E1
E9 A9 EMPTY VDDQ8 VSS3
VDDQ6 VSS1 F1 B3
D2 V_MEMIOCD VDDQ7 VSS2
VDDQ5 E9 A9
C9 G9 EMPTY VDDQ6 VSS1
VDDQ4 VSSQ9 1 R8C34 D2
C1 G1 VDDQ5
C A8
VDDQ3
VDDQ2
VSSQ8
VSSQ7 F9
1 R8C36
1 KOHM
1 KOHM
1% C9
C1
VDDQ4 VSSQ9 G9
G1 C
A1 E8 1% VDDQ3 VSSQ8
VDDQ1 VSSQ6 2 CH A8 F9
E2 402 MD_VREFDQD VDDQ2 VSSQ7
VSSQ5 2 CH OUT 13 A1 E8
D8 402 MD_VREFDQC VDDQ1 VSSQ6
VSSQ4 OUT 13 1 R8C33 1 E2
D1 C2P14 VSSQ5
VSSQ3 1 R8C35 1 KOHM 1 UF VSSQ4 D8
VSSQ2 B9 1 KOHM 1 C2P15 1% 10% VSSQ3 D1
VSSQ1 B1 1% 1 UF 2 CH
2
6.3 V
VSSQ2 B9
2 CH 10% 402 X5R
402 B1
402 6.3 V VSSQ1
X866978-001 BGA96 2 X5R
402
X866978-001 BGA96
U8C4 MEM U8C3 MEM

DDR3_4GBIT_X16 DDR3_4GBIT_X16
5 BI MD_DQSU_2_P C7 DQSU_P 5 BI MD_DQSU_3_P C7 DQSU_P
5 BI MD_DQSU_2_N B7 DQSU_N 5 BI MD_DQSU_3_N B7 DQSU_N
MD_DQSL_2_P F3 J7 MD_CLK0_DP MD_DQSL_3_P F3 J7 MD_CLK0_DP
B 5
5
BI
BI MD_DQSL_2_N G3
DQSL_P
DQSL_N
CK_P
IN
5
5
5
5
BI
BI MD_DQSL_3_N G3
DQSL_P
DQSL_N
CK_P
IN
5
5 B
5 IN MD_RESET_N T2 RESET_N 5 IN MD_RESET_N T2 RESET_N
5 IN MD_A<15..0> 5 IN MD_A<15..0>
15 M7 A15 15 M7 A15
14 T7 A14 14 T7 A14
13 T3 A13 13 T3 A13
12 N7 A12 DQU7 A3 MD_DQ47 BI 5 12 N7 A12 DQU7 A3 MD_DQ63 BI 5
11 R7 A11 DQU6 B8 MD_DQ46 BI 5 11 R7 A11 DQU6 B8 MD_DQ62 BI 5
10 L7 A10 DQU5 A2 MD_DQ45 BI 5 10 L7 A10 DQU5 A2 MD_DQ61 BI 5
9 R3 A9 DQU4 A7 MD_DQ44 BI 5 9 R3 A9 DQU4 A7 MD_DQ60 BI 5
8 T8 A8 DQU3 C2 MD_DQ43 BI 5 8 T8 A8 DQU3 C2 MD_DQ59 BI 5
5 P2 A5 DQU0 D7 MD_DQ40 BI 5 5 P2 A5 DQU0 D7 MD_DQ56 BI 5
4 P8 A4 4 P8 A4
3 N2 A3 3 N2 A3
2 P3 A2 DQL7 H7 MD_DQ39 BI 5 2 P3 A2 DQL7 H7 MD_DQ55 BI 5
1 P7 A1 DQL6 G2 MD_DQ38 BI 5 1 P7 A1 DQL6 G2 MD_DQ54 BI 5
0 N3 A0 DQL5 H8 MD_DQ37 BI 5 0 N3 A0 DQL5 H8 MD_DQ53 BI 5
5 IN MD_BA<2..0> DQL4 H3 MD_DQ36 BI 5 5 IN MD_BA<2..0> DQL4 H3 MD_DQ52 BI 5
1 N8 BA1 DQL2 F2 MD_DQ34 BI 5 1 N8 BA1 DQL2 F2 MD_DQ50 BI 5
DQL0 E3 MD_DQ32 BI 5 DQL0 E3 MD_DQ48 BI 5
5 IN MD_WE_N L3 WE_N 5 IN MD_WE_N L3 WE_N
5 IN MD_CAS_N K3 CAS_N 5 IN MD_CAS_N K3 CAS_N
5 IN MD_RAS_N J3 RAS_N CKE K9 MD_CKE0 IN 5 5 IN MD_RAS_N J3 RAS_N CKE K9 MD_CKE0 IN 5
5 IN MD_DMU_2 D3 DMU CS_N L2 MD_CS0_N IN 5 5 IN MD_DMU_3 D3 DMU CS_N L2 MD_CS0_N IN 5
A 5 IN MD_DML_2 E7 DML
K1 MD_ODT0
5 IN MD_DML_3 E7 DML
K1 MD_ODT0
A
ODT IN 5 ODT IN 5
13 IN MD_VREFCAC M8 VREFCA ZQ L8 MD_ZQ2 13 IN MD_VREFCAD M8 VREFCA ZQ L8 MD_ZQ3
13 IN MD_VREFDQC H1 VREFDQ 1 R8C27 13 IN MD_VREFDQD H1 VREFDQ 1 R7C7
243 OHM 243 OHM
X866978-001 BGA96 1% X866978-001 BGA96 1%
2 CH 2 CH
402 402

DRAWING PAGE
[PAGE_TITLE=MEMORY PARTITION A, HIGH] Tue Jun 18 16:42:22 2013
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
MEMORY CHANNEL D, DECOUPLING + TERMINATION

PARTITION D DECOUPLING
D V_MEMIOCD D
V_VTTD
1 1 1 1
V_VTTD C7C4 C9C22 C8C8 C8C9
22 UF 22 UF 22 UF 22 UF
R1P14 20% 20% 20% 20%
5 IN MD_A<15..0> MD_WE_N 1 2 6.3 V 6.3 V 6.3 V 6.3 V
5 IN 2 X7R 2 X7R 2 X7R 2 X7R
36.5 OHM1% 805 805 805 805
402 CH
R9C31
5 IN MD_CAS_N 1 2
36.5 OHM 1%
402 CH
R9C7 R1P16
15 1 2 5 IN MD_RAS_N 1 2
36.5 OHM1% 36.5 OHM1%
402 CH 402 CH V_MEMIOCD
R1P4 R9C34 MEMORY D, CHIP 0, DECOUPLING
14 1 2 5 IN MD_ODT0 1 2
36.5 OHM1% 36.5 OHM 1%
402 CH 402 CH 1
R1P5 R1P15 C1P13 1 C1P18 1 C1P5 1
C2P3 1
C1P11 1 C1P17 1 C1P12 1 C1P16
C 13 1 2 5 IN MD_CKE0 1 2 1 UF
10%
1 UF
10%
1 UF
10%
1 UF
10%
1 UF
10%
1 UF
10%
1 UF
10%
1 UF
10% C
36.5 OHM1% 36.5 OHM 1% 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V
402 CH 402 CH 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R
402 402 402 402 402 402 402 402
R9C6 R1P12
12 1 2 5 IN MD_CS0_N 1 2
36.5 OHM1% 36.5 OHM 1%
402 CH 402 CH
R9C11
11 1 2
36.5 OHM1% V_MEMIOCD
402 CH
R9C15 MEMORY D, CHIP 1 DECOUPLING
10 1 2
36.5 OHM1%
402 CH V_VTTD 1 1
R1P6 C2P8 C2P22 1 C2P11 1 C2P26 1 C2P4 1
C2P18 1 C2P9 1 C2P20
9 1 2 1 UF 1 UF 1 UF 1 UF 1 UF 1 UF 1 UF 1 UF
10% 10% 10% 10% 10% 10% 10% 10%
36.5 OHM1% 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V
402 CH 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R
MD_BA<2..0> 402 402 402 402 402 402 402 402
R9C9 5 IN R1P13
8 1 2 2 1 2
36.5 OHM1% 36.5 OHM 1%
I499
402 CH 402 CH
B R9C16 R8C25 B
7 1 2 1 1 2
36.5 OHM1% 36.5 OHM 1%
402 CH 402 CH
R8C26 R9C27 V_MEMIOCD
6 1 2 0 1 2 MEMORY D, CHIP 2, DECOUPLING
36.5 OHM1% 36.5 OHM 1%
402 CH 402 CH
R1P7
5 1 2 1
C2P24 1 C2P25 1 C2P7 1
C2P5 1
C2P10 1 C2P19 1 C2P13 1 C2P17
36.5 OHM1% 1 UF 1 UF 1 UF 1 UF 1 UF 1 UF 1 UF 1 UF
402 CH 10% 10% 10% 10% 10% 10% 10% 10%
6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V
R9C10 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R
4 1 2 402 402 402 402 402 402 402 402
36.5 OHM1%
402 CH
R9C25
3 1 2
36.5 OHM1%
402 CH
R9C8
2 1 2 V_MEMIOCD
36.5 OHM1% MEMORY D, CHIP 3, DECOUPLING
402 CH
R9C5
1 1 2 1
C3P6 1
C2P12 1 C2P23 1 C2P21 1 C3P13 1 C3P15 1 C2P6 1
C3P1
36.5 OHM1% 1 UF 1 UF 1 UF 1 UF 1 UF 1 UF 1 UF 1 UF
402 CH 10% 10% 10% 10% 10% 10% 10% 10%
A 0
R9C12
1 2
2
6.3 V
X5R
402
2
6.3 V
X5R
402
2
6.3 V
X5R
402
2
6.3 V
X5R
402
2
6.3 V
X5R
402
2
6.3 V
X5R
402
2
6.3 V
X5R
402
2
6.3 V
X5R
402
A
36.5 OHM1%
402 CH

PAGE
[PAGE_TITLE=MEMORY PARTITION A, DECOUPLING, TERMINATION] DRAWING
CONFIDENTIAL
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
MEMORY CHANNEL C
V_MEMIOCD
U7C2 MEM
BYTE LANE 0 V_MEMIOCD
BYTE LANE 2 V_MEMIOCD
V_MEMIOCD U7C1 MEM
D DDR3_4GBIT_X16 BYTE LANE 1 BYTE LANE 3 DDR3_4GBIT_X16 D
1 R7C2 1 R6C6
1 KOHM 1 KOHM
1% 1%
R9 VDD9 NC4 L9 2 CH
2 CH R9 VDD9 NC4 L9
R1 VDD8 NC3 L1 402 402 R1 L1
N9 J9 MC_VREFCAA VDD8 NC3
VDD7 NC2 OUT 15 MC_VREFCAB N9 J9
N1 J1 OUT 15 VDD7 NC2
VDD6 NC1 N1 J1
K8 1 R7C1 1 R6C5 VDD6 NC1
VDD5 1 K8
K2 VDD4 VSS12 T9 1 KOHM C7C5 1 KOHM 1 C6C3 VDD5
G7 VDD3 VSS11 T1 1% 1 UF 1% 1 UF K2 VDD4 VSS12 T9
2 CH 10% 2 CH 10% G7 VDD3 VSS11 T1
D9 VDD2 VSS10 P9 6.3 V 6.3 V
B2 P1
402 2 X5R 402 2 X5R D9 VDD2 VSS10 P9
VDD1 VSS9 402 402 B2 P1
M9 VDD1 VSS9
VSS8 M9
M1 VSS8
VSS7 M1
J8 VSS7
VSS6 J8
J2 VSS6
VSS5 J2
H9 G8 VSS5
VDDQ9 VSS4 H9 G8
H2 E1 V_MEMIOCD VDDQ9 VSS4
VDDQ8 VSS3 V_MEMIOCD H2 E1
F1 B3 VDDQ8 VSS3
VDDQ7 VSS2 F1 B3
E9 A9 VDDQ7 VSS2
VDDQ6 VSS1 E9 A9
D2 1 R7C14 VDDQ6 VSS1
VDDQ5 1 R7C11 D2
C9 VDDQ4 VSSQ9 G9 1 KOHM 1 KOHM VDDQ5
C1 G1 1% 1% C9 VDDQ4 VSSQ9 G9
C A8
VDDQ3
VDDQ2
VSSQ8
VSSQ7 F9 2 CH
402 2 CH
C1
A8
VDDQ3 VSSQ8 G1
F9 C
A1 E8 402 VDDQ2 VSSQ7
VDDQ1 VSSQ6 A1 E8
E2 MC_VREFDQA VDDQ1 VSSQ6
VSSQ5 OUT 15 MC_VREFDQB E2
D8 OUT 15 VSSQ5
VSSQ4 1 R7C13 D8
1 R7C10 VSSQ4
VSSQ3 D1 1 KOHM 1 C3P10 1 KOHM
1
C3P9 VSSQ3 D1
VSSQ2 B9 1% 1 UF 1% 1 UF VSSQ2 B9
VSSQ1 B1 2 CH 10% 10%
6.3 V 2 CH 6.3 V VSSQ1 B1
402 2 X5R 402 2 X5R
X866978-001 BGA96 402 402
X866978-001 BGA96
MC_CLK_TERM_RC
R4R6 1
36.5 OHM 1
1% C4R21
CH 2 R4R7 1 0.1 UF
U7C2 MEM 402 36.5 OHM 10% U7C1 MEM
6.3 V
DDR3_4GBIT_X16 1% 2 X5R DDR3_4GBIT_X16
CH 2 402
5 BI MC_DQSU_0_P C7 DQSU_P 402 5 BI MC_DQSU_1_P C7 DQSU_P
5 BI MC_DQSU_0_N B7 DQSU_N 5 BI MC_DQSU_1_N B7 DQSU_N
MC_DQSL_0_P F3 J7 MC_CLK0_DP MC_DQSL_1_P F3 J7 MC_CLK0_DP
B 5
5
BI
BI MC_DQSL_0_N G3
DQSL_P
DQSL_N
CK_P
CK_N K7 MC_CLK0_DN IN
IN
5
5
5
5
BI
BI MC_DQSL_1_N G3
DQSL_P
DQSL_N
CK_P
CK_N K7 MC_CLK0_DN IN
IN
5
5 B
5 IN MC_RESET_N T2 RESET_N 5 IN MC_RESET_N T2 RESET_N
5 IN MC_A<15..0> 5 IN MC_A<15..0>
15 M7 A15 15 M7 A15
14 T7 A14 14 T7 A14
13 T3 A13 13 T3 A13
12 N7 A12 DQU7 A3 MC_DQ15 BI 5 12 N7 A12 DQU7 A3 MC_DQ31 BI 5
11 R7 A11 DQU6 B8 MC_DQ14 BI 5 11 R7 A11 DQU6 B8 MC_DQ30 BI 5
10 L7 A10 DQU5 A2 MC_DQ13 BI 5 10 L7 A10 DQU5 A2 MC_DQ29 BI 5
9 R3 A9 DQU4 A7 MC_DQ12 BI 5 9 R3 A9 DQU4 A7 MC_DQ28 BI 5
8 T8 A8 DQU3 C2 MC_DQ11 BI 5 8 T8 A8 DQU3 C2 MC_DQ27 BI 5
7 R2 A7 DQU2 C8 MC_DQ10 BI 5 7 R2 A7 DQU2 C8 MC_DQ26 BI 5
5 P2 A5 DQU0 D7 MC_DQ8 BI 5 5 P2 A5 DQU0 D7 MC_DQ24 BI 5
4 P8 A4 4 P8 A4
3 N2 A3 3 N2 A3
2 P3 A2 DQL7 H7 MC_DQ7 BI 5 2 P3 A2 DQL7 H7 MC_DQ23 BI 5
1 P7 A1 DQL6 G2 MC_DQ6 BI 5 1 P7 A1 DQL6 G2 MC_DQ22 BI 5
0 N3 A0 DQL5 H8 MC_DQ5 BI 5 0 N3 A0 DQL5 H8 MC_DQ21 BI 5
5 IN MC_BA<2..0> DQL4 H3 MC_DQ4 BI 5 5 IN MC_BA<2..0> DQL4 H3 MC_DQ20 BI 5
2 M3 BA2 DQL3 F8 MC_DQ3 BI 5 2 M3 BA2 DQL3 F8 MC_DQ19 BI 5
1 N8 BA1 DQL2 F2 MC_DQ2 BI 5 1 N8 BA1 DQL2 F2 MC_DQ18 BI 5
DQL0 E3 MC_DQ0 BI 5 DQL0 E3 MC_DQ16 BI 5
5 IN MC_WE_N L3 WE_N 5 IN MC_WE_N L3 WE_N
5 IN MC_CAS_N K3 CAS_N 5 IN MC_CAS_N K3 CAS_N
5 IN MC_RAS_N J3 RAS_N CKE K9 MC_CKE0 IN 5 5 IN MC_RAS_N J3 RAS_N CKE K9 MC_CKE0 IN 5
5 IN MC_DMU_0 D3 DMU CS_N L2 MC_CS0_N IN 5 5 IN MC_DMU_1 D3 DMU CS_N L2 MC_CS0_N IN 5
A 5 IN MC_DML_0 E7 DML
K1 MC_ODT0
5 IN MC_DML_1 E7 DML
K1 MC_ODT0
A
ODT IN 5 ODT IN 5
15 IN MC_VREFCAA M8 VREFCA ZQ L8 MC_ZQ0 15 IN MC_VREFCAB M8 VREFCA ZQ L8 MC_ZQ1
15 IN MC_VREFDQA H1 VREFDQ 15 IN MC_VREFDQB H1 VREFDQ 1 R6C12
1 R7C8 243 OHM
X866978-001 BGA96 243 OHM X866978-001 BGA96 1%
1%
2 CH
2 CH 402
402

DRAWING PAGE
[PAGE_TITLE=MEMORY PARTITION B, LOW] CONFIDENTIAL
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
MEMORY CHANNEL C
V_MEMIOCD
BYTE LANE 4 BYTE LANE 6 V_MEMIOCD
V_MEMIOCD
D U6D2 MEM BYTE LANE 5 BYTE LANE 7 V_MEMIOCD U6D3 MEM
D
DDR3_4GBIT_X16
1 R6D35 DDR3_4GBIT_X16
1 R6D13 1 KOHM
1 KOHM 1%
R9 L9 1%
VDD9 NC4 2 CH
R1 VDD8 NC3 L1 2 CH 402 MC_VREFCAD R9 VDD9 NC4 L9
N9 J9
402 MC_VREFCAC OUT 16 R1 L1
VDD7 NC2 OUT 16 VDD8 NC3
N1 VDD6 NC1 J1 N9 VDD7 NC2 J9
K8
1 R6D36 1 N1 J1
VDD5 1 R6D14 1 KOHM C4R29 VDD6 NC1
K2 VDD4 VSS12 T9 1 KOHM 1
C6D8 1% 1 UF K8 VDD5
G7 VDD3 VSS11 T1 1% 1 UF 2 CH 10%
6.3 V
K2 VDD4 VSS12 T9
D9 VDD2 VSS10 P9 2 CH 10% 402 2 X5R G7 VDD3 VSS11 T1
B2 P1 402 6.3 V 402 D9 P9
VDD1 VSS9 2 X5R VDD2 VSS10
VSS8 M9 402 B2 VDD1 VSS9 P1
VSS7 M1 VSS8 M9
VSS6 J8 VSS7 M1
VSS5 J2 VSS6 J8
H9 VDDQ9 VSS4 G8 VSS5 J2
H2 VDDQ8 VSS3 E1 H9 VDDQ9 VSS4 G8
F1 VDDQ7 VSS2 B3 H2 VDDQ8 VSS3 E1
E9 VDDQ6 VSS1 A9 F1 VDDQ7 VSS2 B3
D2 VDDQ5 V_MEMIOCD E9 VDDQ6 VSS1 A9
C9 G9 V_MEMIOCD D2
C C1
VDDQ4
VDDQ3
VSSQ9
VSSQ8 G1 C9
VDDQ5
VDDQ4 VSSQ9 G9 C
A8 VDDQ2 VSSQ7 F9
1 R6D5 1 R6D20 C1 VDDQ3 VSSQ8 G1
A1 VDDQ1 VSSQ6 E8 1 KOHM 1 KOHM A8 VDDQ2 VSSQ7 F9
VSSQ5 E2 1% 1% A1 VDDQ1 VSSQ6 E8
D8 2 CH E2
VSSQ4 2 CH 402 MC_VREFDQD VSSQ5
D1 402 MC_VREFDQC OUT 16 D8
VSSQ3 OUT 16 VSSQ4
VSSQ2 B9 1 R6D22 1 VSSQ3 D1
1 R6D6 1 KOHM C4R14
VSSQ1 B1 1 KOHM 1 C4R1 1% 1 UF VSSQ2 B9
1% 1 UF 2 CH
10%
6.3 V
VSSQ1 B1
X866978-001 BGA96 2 CH 10% 2 X5R
402 6.3 V 402
2 X5R 402 X866978-001 BGA96
402
U6D2,U6D3 EMPTY EMPTY MEMORY DUMMY_BOM
U6D2 MEM U6D3 MEM

5 BI MC_DQSU_2_P C7 DQSU_P 5 BI MC_DQSU_3_P C7 DQSU_P
MC_DQSU_2_N B7 MC_DQSU_3_N B7
B 5
5
BI
BI MC_DQSL_2_P F3
DQSU_N
DQSL_P CK_P J7 MC_CLK0_DP IN 5
5
5
BI
BI MC_DQSL_3_P F3
DQSU_N
DQSL_P CK_P J7 MC_CLK0_DP IN 5 B
5 BI MC_DQSL_2_N G3 DQSL_N CK_N K7 MC_CLK0_DN IN 5 5 BI MC_DQSL_3_N G3 DQSL_N CK_N K7 MC_CLK0_DN IN 5
5 IN MC_RESET_N T2 RESET_N 5 IN MC_RESET_N T2 RESET_N
5 IN MC_A<15..0> 5 IN MC_A<15..0>
15 M7 A15 15 M7 A15
14 T7 A14 14 T7 A14
13 T3 A13 13 T3 A13
12 N7 A12 DQU7 A3 MC_DQ47 BI 5 12 N7 A12 DQU7 A3 MC_DQ63 BI 5
11 R7 A11 DQU6 B8 MC_DQ46 BI 5 11 R7 A11 DQU6 B8 MC_DQ62 BI 5
10 L7 A10 DQU5 A2 MC_DQ45 BI 5 10 L7 A10 DQU5 A2 MC_DQ61 BI 5
9 R3 A9 DQU4 A7 MC_DQ44 BI 5 9 R3 A9 DQU4 A7 MC_DQ60 BI 5
8 T8 A8 DQU3 C2 MC_DQ43 BI 5 8 T8 A8 DQU3 C2 MC_DQ59 BI 5
5 P2 A5 DQU0 D7 MC_DQ40 BI 5 5 P2 A5 DQU0 D7 MC_DQ56 BI 5
4 P8 A4 4 P8 A4
3 N2 A3 3 N2 A3
2 P3 A2 DQL7 H7 MC_DQ39 BI 5 2 P3 A2 DQL7 H7 MC_DQ55 BI 5
1 P7 A1 DQL6 G2 MC_DQ38 BI 5 1 P7 A1 DQL6 G2 MC_DQ54 BI 5
0 N3 A0 DQL5 H8 MC_DQ37 BI 5 0 N3 A0 DQL5 H8 MC_DQ53 BI 5
MC_BA<2..0> DQL4 H3 MC_DQ36 BI 5 5 IN MC_BA<2..0> DQL4 H3 MC_DQ52 BI 5
5 IN 2 M3 F8 MC_DQ35 2 M3 F8 MC_DQ51
1 N8 BA1 DQL2 F2 MC_DQ34 BI 5 1 N8 BA1 DQL2 F2 MC_DQ50 BI 5
DQL0 E3 MC_DQ32 BI 5 DQL0 E3 MC_DQ48 BI 5
5 IN MC_WE_N L3 WE_N 5 IN MC_WE_N L3 WE_N
5 IN MC_CAS_N K3 CAS_N 5 IN MC_CAS_N K3 CAS_N
5 IN MC_RAS_N J3 RAS_N CKE K9 MC_CKE0 IN 5 5 IN MC_RAS_N J3 RAS_N CKE K9 MC_CKE0 IN 5
A 5 IN MC_DMU_2
MC_DML_2
D3
E7
DMU CS_N L2 MC_CS0_N IN 5 5 IN MC_DMU_3
MC_DML_3
D3
E7
DMU CS_N L2 MC_CS0_N IN 5 A
5 IN DML 5 IN DML
ODT K1 MC_ODT0 IN 5 ODT K1 MC_ODT0 IN 5
16 IN MC_VREFCAC M8 VREFCA ZQ L8 MC_ZQ2 16 IN MC_VREFCAD M8 VREFCA ZQ L8 MC_ZQ3
16 IN MC_VREFDQC H1 VREFDQ 1 R6D17 16 IN MC_VREFDQD H1 VREFDQ 1 R6D37
243 OHM 243 OHM
X866978-001 BGA96 1% X866978-001 BGA96 1%
2 CH 2 CH
402 402

PAGE
CONFIDENTIAL GREYBULL_RETAIL
[PAGE_TITLE=MEMORY PARTITION B, HIGH] DRAWING
Tue Jun 18 16:42:23 2013
16/72 16/72 M 1.0
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
MEMORY CHANNEL C, DECOUPLING + TERMINATION

V_VTTC PARTITION C DECOUPLING
D V_MEMIOCD D
V_VTTC R4R15
5 IN MC_WE_N 1 2 1
C7C3 1
C6D7 1
1
C4R30
36.5 OHM 1% 22 UF 22 UF C7C2 22 UF
5 MC_A<15..0> 402 CH 20% 20% 22 UF 20%
IN 6.3 V 6.3 V 20% 6.3 V
R4R13 R4R17 2 X7R 2 X7R 2
6.3 V 2 X7R
15 1 2 5 IN MC_CAS_N 1 2 805 805 X7R
805
805
36.5 OHM1% 36.5 OHM1%
402 CH 402 CH
R4R8 R4R18
14 1 2 5 IN MC_RAS_N 1 2
36.5 OHM1% 36.5 OHM 1%
402 CH 402 CH
R4R9 R6D16
13 1 2 5 IN MC_ODT0 1 2
36.5 OHM1% 36.5 OHM1% V_MEMIOCD
402 CH 402 CH
R6D28 R4R16 MEMORY C, CHIP 0 DECOUPLING
12 1 2 5 IN MC_CKE0 1 2
36.5 OHM1% 36.5 OHM1%
402 CH 402 CH 1 1 1 1 1 1 1 1
C 11
R4R10
1 2 MC_CS0_N
R4R12
1 2
C3P8
1 UF
C3P12
1 UF
C3P2
1 UF
C3P17
1 UF
C3P14
1 UF
C3P5
1 UF
C3P19
1 UF
C3P4
1 UF C
5 IN 10% 10% 10% 10% 10% 10% 10% 10%
36.5 OHM1% 36.5 OHM1% 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V
2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R
R6D27
402 CH 402 CH
402 402 402 402 402 402 402 402
10 1 2
36.5 OHM1%
402 CH
V_VTTC
R6D24
9 1 2
36.5 OHM1%
402 CH 5 IN MC_BA<2..0> V_MEMIOCD
R6D31 R4R14 MEMORY C, CHIP 1, DECOUPLING
8 1 2 2 1 2
36.5 OHM1% 36.5 OHM 1%
402 CH 402 CH 1 1
R6D23 R6D33 C4P2 C3P3 1
C4P5 1
C3P7 1
C3P11 1
C4P4 1
C3P18 1 C3P16
7 1 2 1 1 2 1 UF 1 UF
10% 10% 1 UF 1 UF 1 UF 1 UF 1 UF 1 UF
36.5 OHM1% 36.5 OHM1% 6.3 V 6.3 V 10% 10% 10% 10% 10% 10%
402 CH 402 CH 2 X5R 2 X5R 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V
402 402 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R
R6D32 R6D19 402 402 402 402 402 402
6 1 2 0 1 2
B 36.5 OHM1%
402 CH
36.5 OHM 1%
402 CH B
R6D21
5 1 2
36.5 OHM1%
402 CH V_MEMIOCD
R6D30 MEMORY C, CHIP 2, DECOUPLING
4 1 2
36.5 OHM1%
402 CH 1 1
R4R11 C4R8 C4R10 1 C4R7 1
C4R3 1
C4R11 1 C4R5 1
C4R4 1
C4R2
10% 10% 10% 10% 10% 10% 10% 10%
36.5 OHM1% 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V
402 402 402 402 402 402 402 402
R6D25
2 1 2
36.5 OHM1%
402 CH
R6D29
1 1 2
36.5 OHM1%
402 CH
R6D26 V_MEMIOCD
0 1 2
36.5 OHM1%
MEMORY C, CHIP 3, DECOUPLING
402 CH
1 1 1
C4R23 C4R17 C4R16 1 C4R27 1
C4R25 1
C4R18 1
C4R19 1
C4R24
A 1 UF
10%
1 UF
10%
1 UF
10%
1 UF
10%
1 UF
10%
1 UF
10%
1 UF
10%
1 UF
10% A
6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V
402 402 402 402 402 402 402 402

PAGE
[PAGE_TITLE=MEMORY PARTITION B, DECOUPLING, TERMINATION] DRAWING
CONFIDENTIAL
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
V_MEMIOAB
U9F5 MEM
I37
MEMORY CHANNEL B V_MEMIOAB
DDR3_4GBIT_X16 V_MEMIOAB V_MEMIOAB I111
BYTE LANE 0 BYTE LANE 2 U8F3 MEM
D R9 L9
BYTE LANE 1 1 R9F21 BYTE LANE 3 1 R8F20
1 KOHM DDR3_4GBIT_X16 D
VDD9 NC4 1 KOHM 1%
R1 VDD8 NC3 L1 1% 2 CH
N9 VDD7 NC2 J9 2 CH
N1 J1 402 MB_VREFCAA 402 R9 L9
VDD6 NC1 VDD9 NC4
K8 OUT 18 MB_VREFCAB R1 L1
VDD5 OUT 18 VDD8 NC3
K2 VDD4 VSS12 T9 N9 VDD7 NC2 J9
G7 T1
1 R9F20 1 N1 J1
VDD3 VSS11 1 KOHM C9F15 1 R8F21 1 VDD6 NC1
D9 VDD2 VSS10 P9 1% 1 UF 1 KOHM C8F4 K8 VDD5
B2 VDD1 VSS9 P1 2 CH 10% 1% 1 UF K2 VDD4 VSS12 T9
6.3 V 10%
VSS8 M9 402 2 X5R 2 CH 6.3 V G7 VDD3 VSS11 T1
VSS7 M1 402 402 2 X5R D9 VSS10 P9
402 VDD2
VSS6 J8 B2 VDD1 VSS9 P1
VSS5 J2 VSS8 M9
H9 VDDQ9 VSS4 G8 VSS7 M1
H2 VDDQ8 VSS3 E1 VSS6 J8
F1 VDDQ7 VSS2 B3 VSS5 J2
E9 VDDQ6 VSS1 A9 H9 VDDQ9 VSS4 G8
D2 VDDQ5 V_MEMIOAB H2 VDDQ8 VSS3 E1
C9 VDDQ4 VSSQ9 G9 V_MEMIOAB F1 VDDQ7 VSS2 B3
C1 VDDQ3 VSSQ8 G1 E9 VDDQ6 VSS1 A9
A8 VDDQ2 VSSQ7 F9 1 R8F6 1 R8F3 D2 VDDQ5
A1 VDDQ1 VSSQ6 E8 1 KOHM 1 KOHM C9 VDDQ4 VSSQ9 G9
VSSQ5 E2 1% 1% C1 VDDQ3 VSSQ8 G1
2 CH
C VSSQ4 D8
D1
402 MB_VREFDQA OUT 18
2 CH
402MB_VREFDQB
A8
A1
VDDQ2 VSSQ7 F9
E8 C
VSSQ3 OUT 18 VDDQ1 VSSQ6
VSSQ2 B9 1 R8F7 VSSQ5 E2
1 KOHM 1 C2U13 1 R8F4 1
VSSQ1 B1
1% 1 KOHM C2U12 VSSQ4 D8
1 UF 1% 1 UF VSSQ3 D1
2 CH 10% 10%
X866978-001 BGA96 6.3 V 2 CH 6.3 V VSSQ2 B9
402 2 X5R 402 2 X5R B1
402 402 VSSQ1
X866978-001 BGA96
U9F5,U8F3 EMPTY EMPTY MEMORY DUMMY_BOM MB_CLK_TERM_RC
R1U8 1
36.5 OHM
1% 1
I11 R1U9 1 C1U4 I82
CH 2
402 36.5 OHM 0.1 UF
U9F5 MEM 1% 10% U8F3 MEM
6.3 V
DDR3_4GBIT_X16 CH 2 2 X5R DDR3_4GBIT_X16
402 402
6 BI MB_DQSU_0_P C7 DQSU_P 6 BI MB_DQSU_1_P C7 DQSU_P
6 BI MB_DQSU_0_N B7 DQSU_N 6 BI MB_DQSU_1_N B7 DQSU_N
6 BI MB_DQSL_0_P F3 DQSL_P CK_P J7 MB_CLK0_DP IN 6 6 BI MB_DQSL_1_P F3 DQSL_P CK_P J7 MB_CLK0_DP IN 6
6 BI MB_DQSL_0_N G3 DQSL_N CK_N K7 MB_CLK0_DN IN 6 6 BI MB_DQSL_1_N G3 DQSL_N CK_N K7 MB_CLK0_DN IN 6
B 6 IN MB_RESET_N
MB_A<15..0>
T2 RESET_N 6 IN MB_RESET_N
MB_A<15..0>
T2 RESET_N
B
6 IN 6 IN
15 M7 A15 15 M7 A15
14 T7 A14 14 T7 A14
13 T3 A13 13 T3 A13
12 N7 A12 DQU7 A3 MB_DQ15 BI 6 12 N7 A12 DQU7 A3 MB_DQ31 BI 6
11 R7 A11 DQU6 B8 MB_DQ14 BI 6 11 R7 A11 DQU6 B8 MB_DQ30 BI 6
10 L7 A10 DQU5 A2 MB_DQ13 BI 6 10 L7 A10 DQU5 A2 MB_DQ29 BI 6
9 R3 A9 DQU4 A7 MB_DQ12 BI 6 9 R3 A9 DQU4 A7 MB_DQ28 BI 6
8 T8 A8 DQU3 C2 MB_DQ11 BI 6 8 T8 A8 DQU3 C2 MB_DQ27 BI 6
7 R2 A7 DQU2 C8 MB_DQ10 BI 6 7 R2 A7 DQU2 C8 MB_DQ26 BI 6
5 P2 A5 DQU0 D7 MB_DQ8 BI 6 5 P2 A5 DQU0 D7 MB_DQ24 BI 6
4 P8 A4 4 P8 A4
3 N2 A3 3 N2 A3
2 P3 A2 DQL7 H7 MB_DQ7 BI 6 2 P3 A2 DQL7 H7 MB_DQ23 BI 6
1 P7 A1 DQL6 G2 MB_DQ6 BI 6 1 P7 A1 DQL6 G2 MB_DQ22 BI 6
0 N3 A0 DQL5 H8 MB_DQ5 BI 6 0 N3 A0 DQL5 H8 MB_DQ21 BI 6
MB_BA<2..0> DQL4 H3 MB_DQ4 BI 6 MB_BA<2..0> DQL4 H3 MB_DQ20 BI 6
6 IN 2 M3 F8 MB_DQ3 6 IN 2 M3 F8 MB_DQ19
1 N8 BA1 DQL2 F2 MB_DQ2 BI 6 1 N8 BA1 DQL2 F2 MB_DQ18 BI 6
0 M2 BA0 DQL1 F7 MB_DQ1 BI 6 0 M2 BA0 DQL1 F7 MB_DQ17 BI 6
DQL0 E3 MB_DQ0 BI 6 DQL0 E3 MB_DQ16 BI 6
6 IN MB_WE_N L3 WE_N 6 IN MB_WE_N L3 WE_N
6 IN MB_CAS_N K3 CAS_N 6 IN MB_CAS_N K3 CAS_N
6 IN MB_RAS_N J3 RAS_N CKE K9 MB_CKE0 IN 6 6 IN MB_RAS_N J3 RAS_N CKE K9 MB_CKE0 IN 6
6 IN MB_DMU_0 D3 DMU CS_N L2 MB_CS0_N IN 6 6 IN MB_DMU_1 D3 DMU CS_N L2 MB_CS0_N IN 6
6 IN MB_DML_0 E7 DML 6 IN MB_DML_1 E7 DML
K1 MB_ODT0 K1 MB_ODT0
A 18 IN MB_VREFCAA M8 VREFCA
ODT
ZQ L8 MB_ZQ0 IN 6
18 IN MB_VREFCAB M8 VREFCA
ODT
ZQ L8 MB_ZQ1 IN 6
A
18 IN MB_VREFDQA H1 VREFDQ 1 R9F19 18 IN MB_VREFDQB H1 VREFDQ 1 R8F12
243 OHM
243 OHM 1%
X866978-001 BGA96 1% X866978-001 BGA96 2 CH
2 CH 402
402
[PAGE_TITLE=MEMORY PARTITION C, LOW]

PAGE
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
MEMORY CHANNEL B V_MEMIOAB

V_MEMIOAB
I37
BYTE LANE 4 V_MEMIOAB BYTE LANE 6
D U8F2 MEM BYTE LANE 5 BYTE LANE 7 1 R8F14 V_MEMIOAB I109
D
DDR3_4GBIT_X16 1 KOHM U8F1 MEM
1 R8F17 1%
1 KOHM 2 CH
DDR3_4GBIT_X16
1% 402
2 CH MB_VREFCAD
R9 L9 402 MB_VREFCAC OUT 19
VDD9 NC4
R1 L1 OUT 19 R9 L9
VDD8 NC3 1 R8F15 VDD9 NC4
N9 VDD7 NC2 J9 1 KOHM 1 R1 VDD8 NC3 L1
N1 VDD6 NC1 J1 1 R8F18 1% C8F2 N9 VDD7 NC2 J9
1 1 UF
K8 VDD5 1 KOHM C8F3 2 CH 10% N1 VDD6 NC1 J1
K2 VDD4 VSS12 T9 1% 1 UF 402 6.3 V K8 VDD5
10% 2 X5R
G7 VSS11 T1 2 CH 402 K2 VSS12 T9
VDD3 402 6.3 V VDD4
D9 VSS10 P9 2 X5R G7 VSS11 T1
VDD2 402 VDD3
B2 VDD1 VSS9 P1 D9 VDD2 VSS10 P9
VSS8 M9 B2 VDD1 VSS9 P1
VSS7 M1 VSS8 M9
VSS6 J8 VSS7 M1
VSS5 J2 VSS6 J8
F1 VDDQ7 VSS2 B3 H2 VDDQ8 VSS3 E1
E9 VDDQ6 VSS1 A9 V_MEMIOAB F1 VDDQ7 VSS2 B3
D2 VDDQ5 E9 VDDQ6 VSS1 A9
C9 G9 V_MEMIOAB D2
C C1
VDDQ4
VDDQ3
VSSQ9
VSSQ8 G1 1 R7F7 C9
VDDQ5
VDDQ4 VSSQ9 G9 C
A8 VDDQ2 VSSQ7 F9 1 KOHM C1 VDDQ3 VSSQ8 G1
A1 E8
1 R8F1 1% A8 F9
VDDQ1 VSSQ6 1 KOHM 2 CH
VDDQ2 VSSQ7
VSSQ5 E2 1% 402MB_VREFDQD 19
A1 VDDQ1 VSSQ6 E8
VSSQ4 D8 2 CH OUT VSSQ5 E2
VSSQ3 D1 402 MB_VREFDQC OUT 19 1 R7F8 1
C3U11 VSSQ4 D8
VSSQ2 B9 1 KOHM 1 UF VSSQ3 D1
1 R8F2 1%
VSSQ1 B1 1 KOHM 1 C2U11 10% VSSQ2 B9
1% 2 CH 6.3 V B1
1 UF 402 2 X5R VSSQ1
X866978-001 BGA96 2 CH 10% 402
402 6.3 V
2 X5R X866978-001 BGA96
402

I11 U8F2,U8F1 EMPTY EMPTY DUMMY_BOM
MEMORY
I166
U8F2 MEM U8F1 MEM
6 BI MB_DQSU_2_P C7 DQSU_P 6 BI MB_DQSU_3_P C7 DQSU_P
6 BI MB_DQSU_2_N B7 DQSU_N 6 BI MB_DQSU_3_N B7 DQSU_N
6 BI MB_DQSL_2_P F3 DQSL_P CK_P J7 MB_CLK0_DP IN 6 6 BI MB_DQSL_3_P F3 DQSL_P CK_P J7 MB_CLK0_DP IN 6
B 6 BI MB_DQSL_2_N
MB_RESET_N
G3
T2
DQSL_N CK_N K7 MB_CLK0_DN IN 6 6 BI MB_DQSL_3_N
MB_RESET_N
G3
T2
DQSL_N CK_N K7 MB_CLK0_DN IN 6
B
6 IN RESET_N 6 IN RESET_N
6 IN MB_A<15..0> 6 IN MB_A<15..0>
15 M7 A15 15 M7 A15
14 T7 A14 14 T7 A14
13 T3 A13 13 T3 A13
12 N7 A12 DQU7 A3 MB_DQ47 BI 6 12 N7 A12 DQU7 A3 MB_DQ63 BI 6
11 R7 A11 DQU6 B8 MB_DQ46 BI 6 11 R7 A11 DQU6 B8 MB_DQ62 BI 6
10 L7 A10 DQU5 A2 MB_DQ45 BI 6 10 L7 A10 DQU5 A2 MB_DQ61 BI 6
9 R3 A9 DQU4 A7 MB_DQ44 BI 6 9 R3 A9 DQU4 A7 MB_DQ60 BI 6
8 T8 A8 DQU3 C2 MB_DQ43 BI 6 8 T8 A8 DQU3 C2 MB_DQ59 BI 6
5 P2 A5 DQU0 D7 MB_DQ40 BI 6 5 P2 A5 DQU0 D7 MB_DQ56 BI 6
4 P8 A4 4 P8 A4
3 N2 A3 3 N2 A3
2 P3 A2 DQL7 H7 MB_DQ39 BI 6 2 P3 A2 DQL7 H7 MB_DQ55 BI 6
1 P7 A1 DQL6 G2 MB_DQ38 BI 6 1 P7 A1 DQL6 G2 MB_DQ54 BI 6
0 N3 A0 DQL5 H8 MB_DQ37 BI 6 0 N3 A0 DQL5 H8 MB_DQ53 BI 6
6 IN MB_BA<2..0> DQL4 H3 MB_DQ36 BI 6 6 IN MB_BA<2..0> DQL4 H3 MB_DQ52 BI 6
1 N8 BA1 DQL2 F2 MB_DQ34 BI 6 1 N8 BA1 DQL2 F2 MB_DQ50 BI 6
DQL0 E3 MB_DQ32 BI 6 DQL0 E3 MB_DQ48 BI 6
6 IN MB_WE_N L3 WE_N 6 IN MB_WE_N L3 WE_N
6 IN MB_CAS_N K3 CAS_N 6 IN MB_CAS_N K3 CAS_N
6 IN MB_RAS_N J3 RAS_N CKE K9 MB_CKE0 IN 6 6 IN MB_RAS_N J3 RAS_N CKE K9 MB_CKE0 IN 6
6 IN MB_DMU_2 D3 DMU CS_N L2 MB_CS0_N IN 6 6 IN MB_DMU_3 D3 DMU CS_N L2 MB_CS0_N IN 6
MB_DML_2 E7 MB_DML_3 E7
A
6 IN DML
ODT K1 MB_ODT0 IN 6
6 IN DML
ODT K1 MB_ODT0 IN 6
A
19 IN MB_VREFCAC M8 VREFCA ZQ L8 MB_ZQ2 19 IN MB_VREFCAD M8 VREFCA ZQ L8 MB_ZQ3
19 IN MB_VREFDQC H1 VREFDQ 1 R8F11 19 IN MB_VREFDQD H1 VREFDQ 1 R8F10
243 OHM 243 OHM
X866978-001 BGA96 1% X866978-001 BGA96 1%
2 CH 2 CH
402 402
[PAGE_TITLE=MEMORY PARTITION C, HIGH]

PAGE
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
MEMORY CHANNEL B, DECOUPLING + TERMINATION

D PARTITION B DECOUPLING D
V_MEMIOAB
V_VTTB V_VTTB
1 1
C8F6 C9F9 1
C7F5 1
C8F5
22 UF 22 UF
20% 20% 22 UF 22 UF
R1U13 6.3 V 6.3 V 20% 20%
MB_A<15..0> MB_WE_N 1 2 2 X7R 2 X7R 6.3 V 6.3 V
6 IN 6 IN 805 805 2 X7R 2 X7R
36.5 OHM1% 805 805
402 CH
R1U11
6 IN MB_CAS_N 1 2
36.5 OHM1%
402 CH
R1U14 R1U10
15 1 2 6 IN MB_RAS_N 1 2 V_MEMIOAB
36.5 OHM 1% 36.5 OHM1% MEMORY B, CHIP 0 DECOUPLING
402 CH 402 CH
R1U18 R8F22
14 1 2 6 IN MB_ODT0 1 2
36.5 OHM1% 36.5 OHM1% 1 I140 I137 I138 I139
C 402 CH 402 CH C2U16 1 C3U5 1
C3U2 1
C3U13 1 C3U17 1 C2U8 1
C2U5 1
C2U23
13
R1U21
1 2 MB_CKE0
R1U12
1 2
1 UF
10%
1 UF
10%
1 UF
10%
1 UF
10%
1 UF
10%
1 UF
10%
1 UF
10%
1 UF
10% C
6 IN 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V
36.5 OHM1% 36.5 OHM1% 402 402 402 402 402 402 402 402
402 CH 402 CH
R9F29 R8F23
12 1 2 6 IN MB_CS0_N 1 2
36.5 OHM 1% 36.5 OHM1%
402 CH 402 CH
R9F31
11 1 2
36.5 OHM1%
402 CH V_MEMIOAB
R9F28 MEMORY B, CHIP 1, DECOUPLING
10 1 2
36.5 OHM 1% I136 I141 I142 I143
1 1 1
402
R9F25
CH V_VTTB C2U2 C2U3 C2U14 1 C2U9 1
C2U6 1
C2U17 1 C2U19 1 C2U21
1 UF 1 UF 1 UF 1 UF 1 UF 1 UF 1 UF 1 UF
9 1 2 10% 10% 10% 10% 10% 10% 10% 10%
6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V
36.5 OHM 1% 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R
402 CH 402 402 402 402 402 402 402 402
R1U19 6 IN MB_BA<2..0> R1U15
8 1 2 2 1 2
B 36.5 OHM 1%
402 CH
36.5 OHM1%
402 CH B
R9F24 R9F23
7 1 2 1 1 2
36.5 OHM1% 36.5 OHM 1%
402 CH 402 CH V_MEMIOAB
R1U20 R8F24 MEMORY B, CHIP 2, DECOUPLING
6 1 2 0 1 2
36.5 OHM 1% 36.5 OHM1%
402 CH 402 CH 1 I144 1 1 I145 I146 I147
R1U17 C2U1 C2U4 C2U15 1 C2U10 1 C2U7 1
C2U18 1 C2U20 1 C2U22
10% 10% 10% 10% 10% 10% 10% 10%
36.5 OHM 1% 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V
402 402 402 402 402 402 402 402
R1U16
4 1 2
36.5 OHM 1%
402 CH
R8F25
3 1 2
36.5 OHM 1%
402 CH
R9F26 V_MEMIOAB
2 1 2
36.5 OHM 1% MEMORY B, CHIP 3, DECOUPLING
402 CH
R9F30
1 1 2
1 I148 1 I149 1 1 1 I150 1
A 36.5 OHM 1%
402 CH C1U5 C1U8 C1U9 C1U6 C1U7 C1U10 1 C1U11 1 C1U12 A
R9F27 10% 10% 10% 10% 10% 10% 10% 10%
0 1 2 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V
36.5 OHM 1% 402 402 402 402 402 402 402 402
402 CH
[PAGE_TITLE=MEMORY PARTITION C, DECOUPLING, TERMINATION]

PAGE
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
MEMORY CHANNEL A
V_MEMIOAB
I58 BYTE LANE 0 V_MEMIOAB BYTE LANE 2 V_MEMIOAB V_MEMIOAB
I111
D U7F2 MEM BYTE LANE 1 BYTE LANE 3 U7F1 MEM
D
DDR3_4GBIT_X16 1 R7F16 1 R7F13
1 KOHM 1 KOHM DDR3_4GBIT_X16
1% 1%
2 CH 2 CH
R9 VDD9 NC4 L9 402 MA_VREFCAA 402
R1 L1 OUT 21 R9 L9
VDD8 NC3 VDD9 NC4
N9 VDD7 NC2 J9
1 R7F17 MA_VREFCAB OUT 21 R1 VDD8 NC3 L1
N1 VDD6 NC1 J1 1 KOHM 1 N9 VDD7 NC2 J9
K8 VDD5 1% C7F2 1 R7F14 N1 VDD6 NC1 J1
1 UF 1
K2 VDD4 VSS12 T9 2 CH 10% 1 KOHM C7F1 K8 VDD5
G7 VDD3 VSS11 T1 402 6.3 V 1% 1 UF K2 VDD4 VSS12 T9
2 X5R 10%
D9 VSS10 P9 402 2 CH G7 VSS11 T1
VDD2 402 6.3 V VDD3
B2 VSS9 P1 2 X5R D9 VSS10 P9
VDD1 402 VDD2
VSS7 M1 VSS8 M9
VSS6 J8 VSS7 M1
VSS5 J2 VSS6 J8
H9 VDDQ9 VSS4 G8 V_MEMIOAB VSS5 J2
F1 VDDQ7 VSS2 B3 V_MEMIOAB H2 VDDQ8 VSS3 E1
E9 VDDQ6 VSS1 A9 F1 VDDQ7 VSS2 B3
D2
1 R7F5 E9 A9
VDDQ5 1 KOHM VDDQ6 VSS1
C9 G9 1% 1 R6F7 D2
C C1
VDDQ4
VDDQ3
VSSQ9
VSSQ8 G1 2 CH 1 KOHM
1% C9
VDDQ5
VDDQ4 VSSQ9 G9 C
A8 VDDQ2 VSSQ7 F9 402 MA_VREFDQA C1 VDDQ3 VSSQ8 G1
A1 E8 OUT 21 2 CH A8 F9
VDDQ1 VSSQ6 402 MA_VREFDQB VDDQ2 VSSQ7
VSSQ5 E2 1 R7F6 21 A1 VDDQ1 VSSQ6 E8
D8 1 KOHM 1 C3U10 OUT E2
VSSQ4 1% 1 R6F8 1 VSSQ5
D1 1 UF C4U10 D8
VSSQ3
2 CH 10% 1 KOHM 1 UF
VSSQ4
VSSQ2 B9 402 6.3 V
2 X5R
1% 10% VSSQ3 D1
VSSQ1 B1 2 CH 6.3 V VSSQ2 B9
402 402 2 X5R B1
402 VSSQ1
X866978-001 BGA96
X866978-001 BGA96
MA_CLK_TERM_RC
R4T12 1
36.5 OHM
I36 1% 1 I82
CH 2
C4T6
0.1 UF
U7F2 MEM 402 R4T10 1 10% U7F1 MEM
36.5 OHM 6.3 V
DDR3_4GBIT_X16 1% 2 X5R DDR3_4GBIT_X16
402
MA_DQSU_0_P C7 CH 2 MA_DQSU_1_P C7
6 BI DQSU_P 402 6 BI DQSU_P
6 BI MA_DQSU_0_N B7 DQSU_N 6 BI MA_DQSU_1_N B7 DQSU_N
6 BI MA_DQSL_0_P F3 DQSL_P CK_P J7 MA_CLK0_DP IN 6 6 BI MA_DQSL_1_P F3 DQSL_P CK_P J7 MA_CLK0_DP IN 6
B 6 BI MA_DQSL_0_N
MA_RESET_N
G3
T2
DQSL_N CK_N K7 MA_CLK0_DN IN 6 6 BI MA_DQSL_1_N
MA_RESET_N
G3
T2
DQSL_N CK_N K7 MA_CLK0_DN IN 6
B
6 IN MA_A<15..0> 6 IN MA_A<15..0>
15 M7 A15 15 M7 A15
14 T7 A14 14 T7 A14
13 T3 A13 13 T3 A13
12 N7 A12 DQU7 A3 MA_DQ15 BI 6 12 N7 A12 DQU7 A3 MA_DQ31 BI 6
11 R7 A11 DQU6 B8 MA_DQ14 BI 6 11 R7 A11 DQU6 B8 MA_DQ30 BI 6
10 L7 A10 DQU5 A2 MA_DQ13 BI 6 10 L7 A10 DQU5 A2 MA_DQ29 BI 6
9 R3 A9 DQU4 A7 MA_DQ12 BI 6 9 R3 A9 DQU4 A7 MA_DQ28 BI 6
8 T8 A8 DQU3 C2 MA_DQ11 BI 6 8 T8 A8 DQU3 C2 MA_DQ27 BI 6
7 R2 A7 DQU2 C8 MA_DQ10 BI 6 7 R2 A7 DQU2 C8 MA_DQ26 BI 6
5 P2 A5 DQU0 D7 MA_DQ8 BI 6 5 P2 A5 DQU0 D7 MA_DQ24 BI 6
4 P8 A4 4 P8 A4
3 N2 A3 3 N2 A3
2 P3 A2 DQL7 H7 MA_DQ7 BI 6 2 P3 A2 DQL7 H7 MA_DQ23 BI 6
1 P7 A1 DQL6 G2 MA_DQ6 BI 6 1 P7 A1 DQL6 G2 MA_DQ22 BI 6
0 N3 A0 DQL5 H8 MA_DQ5 BI 6 0 N3 A0 DQL5 H8 MA_DQ21 BI 6
MA_BA<2..0> DQL4 H3 MA_DQ4 BI 6 MA_BA<2..0> DQL4 H3 MA_DQ20 BI 6
6 IN 2 M3 F8 MA_DQ3 6 IN 2 M3 F8 MA_DQ19
1 N8 BA1 DQL2 F2 MA_DQ2 BI 6 1 N8 BA1 DQL2 F2 MA_DQ18 BI 6
0 M2 BA0 DQL1 F7 MA_DQ1 BI 6 0 M2 BA0 DQL1 F7 MA_DQ17 BI 6
DQL0 E3 MA_DQ0 BI 6 DQL0 E3 MA_DQ16 BI 6
6 IN MA_WE_N L3 WE_N 6 IN MA_WE_N L3 WE_N
6 IN MA_CAS_N K3 CAS_N 6 IN MA_CAS_N K3 CAS_N
6 IN MA_RAS_N J3 RAS_N CKE K9 MA_CKE0 IN 6 6 IN MA_RAS_N J3 RAS_N CKE K9 MA_CKE0 IN 6
6 IN MA_DMU_0 D3 DMU CS_N L2 MA_CS0_N IN 6 6 IN MA_DMU_1 D3 DMU CS_N L2 MA_CS0_N IN 6
MA_DML_0 E7 MA_DML_1 E7
A
6 IN DML
ODT K1 MA_ODT0 IN 6
6 IN DML
ODT K1 MA_ODT0 IN 6
A
21 IN MA_VREFCAA M8 VREFCA ZQ L8 MA_ZQ0 21 IN MA_VREFCAB M8 VREFCA ZQ L8 MA_ZQ1
21 IN MA_VREFDQA H1 VREFDQ 1 R7F11 21 IN MA_VREFDQB H1 VREFDQ 1 R7F10
243 OHM
243 OHM 1%
X866978-001 BGA96 1% X866978-001 BGA96 2 CH
2 CH 402
402 MS_PART# MATL REF_DES TRUEDESCR. BOM PROPERTY
U7F2,U7F1 EMPTY EMPTY MEMORY DUMMY_BOM
[PAGE_TITLE=MEMORY PARTITION D, LOW]

PAGE
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
MEMORY CHANNEL A
V_MEMIOAB BYTE LANE 4 V_MEMIOAB BYTE LANE 6 V_MEMIOAB
I37
BYTE LANE 5 BYTE LANE 7
D U6E5 MEM V_MEMIOAB I109 D
DDR3_4GBIT_X16 1 R6F1 1 R6E27
1 KOHM 1 KOHM U6E3 MEM
1% 1% DDR3_4GBIT_X16
2 CH 2 CH
R9 VDD9 NC4 L9 402 402
R1 VDD8 NC3 L1 MA_VREFCAC OUT 22 MA_VREFCAD OUT 22
N9 VDD7 NC2 J9 R9 VDD9 NC4 L9
N1 VDD6 NC1 J1 1 R6F2 1
1 R6E24 1
R1 VDD8 NC3 L1
K8 VDD5 1 KOHM C6F3 1 KOHM C6E14 N9 VDD7 NC2 J9
K2 VDD4 VSS12 T9 1% 1 UF 1% 1 UF N1 VDD6 NC1 J1
2 CH 10% 2 CH 10%
G7 VDD3 VSS11 T1 6.3 V 6.3 V K8 VDD5
D9 P9
402 2 X5R 402 2 X5R K2 T9
VDD2 VSS10 402 402 VDD4 VSS12
B2 VDD1 VSS9 P1 G7 VDD3 VSS11 T1
VSS8 M9 D9 VDD2 VSS10 P9
VSS6 J8 VSS8 M9
VSS5 J2 VSS7 M1
H2 VDDQ8 VSS3 E1 VSS5 J2
F1 VDDQ7 VSS2 B3 H9 VDDQ9 VSS4 G8
E9 VDDQ6 VSS1 A9 V_MEMIOAB V_MEMIOAB H2 VDDQ8 VSS3 E1
D2 VDDQ5 F1 VDDQ7 VSS2 B3
C9 G9 E9 A9
C C1
VDDQ4
VDDQ3
VSSQ9
VSSQ8 G1 1 R6E25 1 R6E9 D2
VDDQ6
VDDQ5
VSS1
C
A8 VDDQ2 VSSQ7 F9 1 KOHM 1 KOHM C9 VDDQ4 VSSQ9 G9
A1 VDDQ1 VSSQ6 E8 1% 1% C1 VDDQ3 VSSQ8 G1
E2 2 CH 2 CH A8 F9
VSSQ5 402 MA_VREFDQC 402 MA_VREFDQD VDDQ2 VSSQ7
D8 OUT 22 OUT 22 A1 E8
VSSQ4 VDDQ1 VSSQ6
VSSQ3 D1 1 R6E26 1 R6E8 1 VSSQ5 E2
VSSQ2 B9 1 KOHM 1 C4T11 1 KOHM C4T1 VSSQ4 D8
1% 1% 1 UF
VSSQ1 B1 1 UF 10% VSSQ3 D1
2 CH 10% 2 CH 6.3 V
6.3 V 2 VSSQ2 B9
402 2 X5R 402 X5R
B1
X866978-001 BGA96 402
402 VSSQ1
X866978-001 BGA96
I11 U6E5,U6E3 EMPTY EMPTY MEMORY DUMMY_BOM I78
U6E5 MEM U6E3 MEM
6 BI MA_DQSU_2_P C7 DQSU_P 6 BI MA_DQSU_3_P C7 DQSU_P
6 BI MA_DQSU_2_N B7 DQSU_N 6 BI MA_DQSU_3_N B7 DQSU_N
6 BI MA_DQSL_2_P F3 DQSL_P CK_P J7 MA_CLK0_DP IN 6 6 BI MA_DQSL_3_P F3 DQSL_P CK_P J7 MA_CLK0_DP IN 6
B 6 BI MA_DQSL_2_N
MA_RESET_N
G3
T2
DQSL_N CK_N K7 MA_CLK0_DN IN 6 6 BI MA_DQSL_3_N
MA_RESET_N
G3
T2
DQSL_N CK_N K7 MA_CLK0_DN IN 6
B
6 IN MA_A<15..0> 6 IN MA_A<15..0>
15 M7 A15 15 M7 A15
14 T7 A14 14 T7 A14
13 T3 A13 13 T3 A13
12 N7 A12 DQU7 A3 MA_DQ47 BI 6 12 N7 A12 DQU7 A3 MA_DQ63 BI 6
11 R7 A11 DQU6 B8 MA_DQ46 BI 6 11 R7 A11 DQU6 B8 MA_DQ62 BI 6
10 L7 A10 DQU5 A2 MA_DQ45 BI 6 10 L7 A10 DQU5 A2 MA_DQ61 BI 6
9 R3 A9 DQU4 A7 MA_DQ44 BI 6 9 R3 A9 DQU4 A7 MA_DQ60 BI 6
8 T8 A8 DQU3 C2 MA_DQ43 BI 6 8 T8 A8 DQU3 C2 MA_DQ59 BI 6
5 P2 A5 DQU0 D7 MA_DQ40 BI 6 5 P2 A5 DQU0 D7 MA_DQ56 BI 6
4 P8 A4 4 P8 A4
3 N2 A3 3 N2 A3
2 P3 A2 DQL7 H7 MA_DQ39 BI 6 2 P3 A2 DQL7 H7 MA_DQ55 BI 6
1 P7 A1 DQL6 G2 MA_DQ38 BI 6 1 P7 A1 DQL6 G2 MA_DQ54 BI 6
0 N3 A0 DQL5 H8 MA_DQ37 BI 6 0 N3 A0 DQL5 H8 MA_DQ53 BI 6
6 IN MA_BA<2..0> DQL4 H3 MA_DQ36 BI 6 6 IN MA_BA<2..0> DQL4 H3 MA_DQ52 BI 6
1 N8 BA1 DQL2 F2 MA_DQ34 BI 6 1 N8 BA1 DQL2 F2 MA_DQ50 BI 6
DQL0 E3 MA_DQ32 BI 6 DQL0 E3 MA_DQ48 BI 6
6 IN MA_WE_N L3 WE_N 6 IN MA_WE_N L3 WE_N
6 IN MA_CAS_N K3 CAS_N 6 IN MA_CAS_N K3 CAS_N
6 IN MA_RAS_N J3 RAS_N CKE K9 MA_CKE0 IN 6 6 IN MA_RAS_N J3 RAS_N CKE K9 MA_CKE0 IN 6
6 IN MA_DMU_2 D3 DMU CS_N L2 MA_CS0_N IN 6 6 IN MA_DMU_3 D3 DMU CS_N L2 MA_CS0_N IN 6
MA_DML_2 E7 MA_DML_3 E7
A
6 IN DML
ODT K1 MA_ODT0 IN 6
6 IN DML
ODT K1 MA_ODT0 IN 6
A
22 IN MA_VREFCAC M8 VREFCA ZQ L8 MA_ZQ2 22 IN MA_VREFCAD M8 VREFCA ZQ L8 MA_ZQ3
22 IN MA_VREFDQC H1 VREFDQ 1 R6F3 22 IN MA_VREFDQD H1 VREFDQ 1 R6E22
243 OHM 243 OHM
X866978-001 BGA96 1% X866978-001 BGA96 1%
2 CH 2 CH
402 402
[PAGE_TITLE=MEMORY PARTITION D, HIGH]

PAGE
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
MEMORY CHANNEL A, DECOUPLING + TERMINATION

D D
PARTITION A DECOUPLING
V_MEMIOAB
V_VTTA V_VTTA
1 1 1 1
C6E3 C6E18 C7F4 C7F3
22 UF 22 UF 22 UF 22 UF
20% 20% 20% 20%
R4T6 2
6.3 V
2
6.3 V
2
6.3 V
2
6.3 V
6 IN MA_A<15..0> 6 IN MA_WE_N 1 2 X7R
805
X7R
805
X7R
805
X7R
805
36.5 OHM 1%
402 CH
R6E5
6 IN MA_CAS_N 1 2
36.5 OHM1%
402 CH
R6E12 R4T7
15 1 2 6 IN MA_RAS_N 1 2 V_MEMIOAB
36.5 OHM1% 36.5 OHM 1% MEMORY A, CHIP 0 DECOUPLING
402 CH 402 CH
C R4T11 R6E6 C
14 1 2 6 IN MA_ODT0 1 2
1 I136 1 I137 1 I138 1 1 1 1 1
36.5 OHM1% 36.5 OHM1% C3U7 C3U9 C3U15 C3U4 C3U1 C3U12 C3U16 C3U19
402 CH 402 CH 1 UF 1 UF 1 UF 1 UF 1 UF 1 UF 1 UF 1 UF
R4T9 R4T8 10% 10% 10% 10% 10% 10% 10% 10%
13 1 2 MA_CKE0 1 2 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V
6 IN 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R
36.5 OHM1% 36.5 OHM 1% 402 402 402 402 402 402 402 402
402 CH 402 CH
R6E14 R4T4
12 1 2 6 IN MA_CS0_N 1 2
36.5 OHM1% 36.5 OHM 1%
402 CH 402 CH
R6E16
11 1 2
36.5 OHM1% V_MEMIOAB
402 CH
R6E13 MEMORY A, CHIP 1, DECOUPLING
10 1 2
36.5 OHM1% 1 1 I139 1 I140 1 1 1 I141 1 1
402 CH V_VTTA C4U9 C3U3 C4U11 C3U8 C3U6 C3U14 C3U18 C4U12
R4T2 1 UF 1 UF 1 UF 1 UF 1 UF 1 UF 1 UF 1 UF
10% 10% 10% 10% 10% 10% 10% 10%
9 1 2 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V
B 36.5 OHM1%
402 CH
2 X5R
402
2 X5R
402
2 X5R
402
2 X5R
402
2 X5R
402
2 X5R
402
2 X5R
402
2 X5R
402 B
R6E18 6 IN MA_BA<2..0> R4T5
8 1 2 2 1 2
36.5 OHM1% 36.5 OHM1%
402 CH 402 CH
R6E2 R6E21
7 1 2 1 1 2
36.5 OHM1% 36.5 OHM 1% V_MEMIOAB
402 CH 402 CH MEMORY A, CHIP 2, DECOUPLING
R6E20 R6E4
6 1 2 0 1 2
1 1 I142 I143 I144
36.5 OHM1%
402 CH
36.5 OHM1%
402 CH C4U3 C4T12 1 C4T18 1 C4T17 1 C4T16 1 C4T15 1 C4T14 1 C4T13
R4T3 10% 10% 10% 10% 10% 10% 10% 10%
5 1 2 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V
36.5 OHM1% 402 402 402 402 402 402 402 402
402 CH
R6E17
4 1 2
36.5 OHM1%
402 CH
R6E3
3 1 2
36.5 OHM1% V_MEMIOAB
402 CH
R6E1 MEMORY A, CHIP 3, DECOUPLING
2 1 2
A 36.5 OHM1%
402 CH 1 1
A
1 I145 C4T2 C4T9 1 I146 1 1 I147 1 I148 1
R6E15 C4T10 1 UF 1 UF C4T8 C4T7 C4T5 C4T4 C4T3
1 1 2 1 UF 10% 10% 1 UF 1 UF 1 UF 1 UF 1 UF
36.5 OHM1% 10% 6.3 V 6.3 V 10% 10% 10% 10% 10%
402 CH 6.3 V 2 X5R 2 X5R 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V
2 X5R 402 402 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R
R6E10 402 402 402 402 402 402
0 1 2
36.5 OHM1%
402 CH
[PAGE_TITLE=MEMORY PARTITION D, DECOUPLING, TERMINATION] MICROSOFT PROJECT NAME PAGE CSA

PAGE
FAB REV
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
U4D2 KIC IC
KIC, USB 6 of 11 I84

USBD_D0_DP AF8 USB2_WIFI_DP
BI 36
USBD_D0_DN AE8 USB2_WIFI_DN 36

BI
D D
USBC_D0_DP AC4 USB2_AUX_DP 36
BI
USBC_D0_DN AC3 USB2_AUX_DN 36
BI
C6B9
1 2 USB3_AUX_TP 36
OUT
36 USB3_AUX_RP Y1 USBC_D1_RXP USBC_D1_TXP W3 USB3_AUX_TP_C 0.1 UF 10% X5R
IN 6.3 V 402
36 USB3_AUX_RN Y2 USBC_D1_RXN USBC_D1_TXN W4 USB3_AUX_TN_C C6B8
IN 1 2 USB3_AUX_TN
OUT 36
0.1 UF 10% X5R
6.3 V 402
C7B10
1 2 USB3_BP_P1_TP 35
USB3_BP_P1_RP V1 U3 USB3_BP_P1_TP_C
OUT
35 IN USBB_D2_RXP USBB_D2_TXP
0.1 UF 10% X5R
6.3 V 402
35 USB3_BP_P1_RN V2 USBB_D2_RXN USBB_D2_TXN U4 USB3_BP_P1_TN_C C7B9
IN 1 2 USB3_BP_P1_TN
OUT 35
0.1 UF 10% X5R
6.3 V 402
C USBB_D0_DP AE4 USB2_BP_P1_DP
BI 35
C
USBB_D0_DN AE3 USB2_BP_P1_DN 35
BI
USBB_D1_DP AD2 USB2_BP_P0_DP 35

BI
USBB_D1_DN AD1 USB2_BP_P0_DN 35
BI
C7B12
1 2 USB3_BP_P0_TP 35
OUT
35 USB3_BP_P0_RP T1 USBB_D3_RXP USBB_D3_TXP R3 USB3_BP_P0_TP_C 0.1 UF 10% X5R
IN 6.3 V 402
35 USB3_BP_P0_RN T2 USBB_D3_RXN USBB_D3_TXN R4 USB3_BP_P0_TN_C
IN C7B11
1 2 USB3_BP_P0_TN 35
OUT
0.1 UF 10% X5R
6.3 V 402
B 1
C3F4
2 USB3_FP_P0_TP
OUT 35 B
35 USB3_FP_P0_RP AA8 USBA_D2_RXP USBA_D2_TXP AB10 USB3_FP_P0_TP_C
IN 0.1 UF 10% X5R
6.3 V 402
35 USB3_FP_P0_RN AA7 USBA_D2_RXN USBA_D2_TXN AB9 USB3_FP_P0_TN_C
IN C3F5
1 2 USB3_FP_P0_TN 35
OUT
0.1 UF 10% 402
USBA_D0_DP AC7 6.3 V X5R USB2_FP_P0_DP 35
BI
USBA_D0_DN AC8 USB2_FP_P0_DN 35
BI
USBA_D1_DP AF6 USB2_ACC_DP 36

BI
USBA_D1_DN AF5 USB2_ACC_DN 36
BI
C4B8
1 2 USB3_TP_P1_TP 1
DB4B5
1 USB3_TP_P1_RP AB1 USBA_D3_RXP USBA_D3_TXP AA3 USB3_TP_P1_TP_C
DB4B3 0.1 UF 10% X5R
6.3 V 402
1 USB3_TP_P1_RN AB2 USBA_D3_RXN USBA_D3_TXN AA4 USB3_TP_P1_TN_C
DB4B2 C4B7
1 2 USB3_TP_P1_TN 1
DB4B4
A AA5 USBA_D2_AMOUNT 1
0.1 UF 10% 402
6.3 V X5R
A
USBA_D2_AMOUT DB6P4
USBA_D1_AMOUT AE6 USBA_D1_AMOUNT 1
DB4C2
USBA_D0_AMOUT AC11 USBA_D0_AMOUNT 1
DB4D4
USBB_D2_AMOUT R5 USBB_D2_AMOUNT 1
DB6P7
USBB_D1_AMOUT AD5 USBB_D1_AMOUNT 1
DB4C3
USBB_D0_AMOUT AF4 USBB_D0_AMOUNT 1
DB4D1
USBA_D1_TXRTUNE AB11 USBA_D1_TXRTUNE USBC_D1_AMOUT W5 USBC_D1_AMOUNT 1
DB6P5
USBC_D0_AMOUT AC5 USBC_D0_AMOUNT 1
1 R6R19 DB6P6
174 OHM
1% USBD_D0_AMOUT AE9 USBD_D0_AMOUNT 1
DB3D8 PROJECT NAME PAGE CSA FAB REV
2 CH MICROSOFT PAGE
402
X861949-001 BGA515 GREYBULL_RETAIL
CONFIDENTIAL 24/72 24/72 M 1.0
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D
KIC, PCIEX + SATA + VIDEO D
C4D2
1 2 PEX_L0_SB_SOC_TP_C 2
OUT
I5
0.1 UF 10% X5R
U4D2 KIC IC 6.3 V 402
1
C4D1
2 PEX_L0_SB_SOC_TN_C 2
OUT
3 of 11 0.1 UF 10% X5R
C5D9 6.3 V 402
1 2 PEX_L1_SB_SOC_TP_C 2
2 IN PEX_L0_SOC_SB_TP_C D26 PEX_RX0_DP PEX_TX0_DP C24 PEX_L0_SB_SOC_TP OUT
2 IN PEX_L0_SOC_SB_TN_C E26 PEX_RX0_DN PEX_TX0_DN D24 PEX_L0_SB_SOC_TN 0.1 UF 10% X5R
2 PEX_L1_SOC_SB_TP_C A23 PEX_RX1_DP PEX_TX1_DP C22 PEX_L1_SB_SOC_TP 6.3 V 402
IN C5D12
2 PEX_L1_SOC_SB_TN_C B23 PEX_RX1_DN PEX_TX1_DN D22 PEX_L1_SB_SOC_TN 1 2 PEX_L1_SB_SOC_TN_C 2
IN OUT
0.1 UF 10% X5R
6.3 V 402
39 IN SATA1_HDD_RP B6 SATA1_RX_DP SATA1_TX_DP D5 SATA1_HDD_TP OUT 39
39 IN SATA1_HDD_RN A6 SATA1_RX_DN SATA1_TX_DN C5 SATA1_HDD_TN OUT 39
39 IN SATA0_ODD_RP B4 SATA0_RX_DP SATA0_TX_DP D3 SATA0_ODD_TP OUT 39
39 IN SATA0_ODD_RN A4 SATA0_RX_DN SATA0_TX_DN C3 SATA0_ODD_TN OUT 39
SATA_AMOUT C1 SATA_AMOUT 1
DB5C1
PEX_AMOUT B25 PEX_AMOUT 1
DB6R1
C C
X861949-001 BGA515
C5D6
V_3P3 1 2 DP_L1_SB_SOC_TP_C 2
OUT
0.1 UF 10% X5R
6.3 V 402
1 R6P8 I24
U4D2 IC C5D5
2 KOHM KIC 1 2 DP_L1_SB_SOC_TN_C 2
V_3P3STBY 1% OUT
2 CH 7 of 11 0.1 UF 10% X5R
402
402 6.3 V
1
2
BAS40LT
SOT23-3
C5D4
1 HDMI_RX_REXT N3 1 2 DP_L0_SB_SOC_TP_C
NC
TMDS_RX_REXT OUT 2
D4C2
DB6P3
TMDS_RX_DP2 M1 0.1 UF 10% X5R
37 IN TMDS_RX_DP2 6.3 V 402
37 IN TMDS_RX_DN2 M2 TMDS_RX_DN2 C5D3
B10 DP_L1_SB_SOC_TP 1 2 DP_L0_SB_SOC_TN_C
3
DP_TX_LANE1_P OUT 2
37 IN TMDS_RX_DP1 L2 TMDS_RX_DP1 DP_TX_LANE1_N C10 DP_L1_SB_SOC_TN
0.1 UF 10% X5R
HDMI_RX_CEC_3P3
37 IN TMDS_RX_DN1 L3 TMDS_RX_DN1 6.3 V 402

B V_SB1P1 37 IN TMDS_RX_DP0 K1 TMDS_RX_DP0 DP_TX_LANE0_P A9 DP_L0_SB_SOC_TP B
37 TMDS_RX_DN0 K2 TMDS_RX_DN0 DP_TX_LANE0_N B9 DP_L0_SB_SOC_TN C5D8
IN 1 2 DP_AUX_SB_SOC_TP_C 2
OUT
TMDS_RX_CLKP J3 0.1 UF
37 IN TMDS_RX_CLK_P 10% X5R
R5R15 402
1 37 IN TMDS_RX_CLKN J2 TMDS_RX_CLK_N DP_TX_AUX_P A11 DP_AUX_SB_SOC_TP C5D7 6.3 V
300 OHM DP_TX_AUX_N B11 DP_AUX_SB_SOC_TN 1 2 DP_AUX_SB_SOC_TN_C 2
1% 1 R4C3 1 HMDI_RX_TESTP K4
OUT
27 KOHM DB6P1 TMDS_RX_TESTP
2 CH 5% 1 HDMI_RX_TESTN J4 0.1 UF 10% X5R
402 DB6P2 TMDS_RX_TESTN 6.3 V 402
2 CH
402
R4C5 1 R5R2 1 R5R1 V_3P3
38 37 HDMI_RX_CEC 1 2 HDMI_RX_CEC_R P2 HDMI_RX_CEC HDMI_RX_HPD P1 HDMI_RX_HPD 37 100 KOHM
IN OUT 1% 100 KOHM
330 OHM 1% 1%
SP1_TM1 402 CH D12 2 CH
DP_TM1 402 2 CH
402
2 DP1_HPD B8 DP_TX_HPD
IN
DDA_LFCSENSE F11 DDA_LFCSENSE
DDA_LFC F10 DDA_LFC DP_ATB C12 DP_ATB 1
1 R3T20 DB5R1
100 KOHM
1%
2 CH X861949-001 BGA515
402 1
C6R35
0.1 UF PLACE AS CLOSE AS POSSIBLE
10%
6.3 V TO U4D2 PINS F10-F11
2 X5R
402
A A

U4D2 EMPTY EMPTY KIC DUMMY_BOM

PAGE
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
KIC, SMC
V_3P3STBY
R4D28
D 4.7 KOHM
5% U4D2
D
KIC IC
1 EMPTY
FT6R21 FTP 1
402 FTP FT6R14
4 of 11
SMC_UART1_TXD T24 SMC_TXD OUT 70
65 29 SMC_RST_N AF23 SMC_RST_N_IN
IN 1
FTP FT6R13
67 40 PWRSW_N V23 SMC_P4_GPIO7 SMC_UART1_RTS V24 SMC_RTS 70

IN OUT
V_3P3STBY
67 40 IN EJECTSW_N V22 SMC_P4_GPIO6 V_5P0
40 BINDSW_N T23 SMC_P4_GPIO5 I181
IN 1 R4F19
INT_N U23 10 KOHM 1 R9C64
40 IN SMC_P4_GPIO4 5% 10 KOHM
5%
VREG_V5P0_DUAL_SEL0 U22 2 CH
55 OUT SMC_P4_GPIO3 402 2 CH
402
R5E10 61 VREG_3P3STBY_IN_SEL U21 SMC_P4_GPIO2
63 OUT IR_BLAST_SMC_OUT 1 2 OUT G2 VREG_CPUGFX_PWRGD
SMC_P2_GPIO7 IN 44 45
0 OHM 5% 32 ENET_RST_N T21 SMC_P4_GPIO1
402 CH 1
OUT F2 COLD_RESET_N
FT5N1 FTP SMC_P2_GPIO6 IN 68
C 32 IN ENET_WAKE_N R23 SMC_P4_GPIO0
G1 HDD_PWR_EN
V_SOC1P8 C
1 SMC_P2_GPIO5 OUT 39
FT5N2 FTP I21
SMC_P2_GPIO4 F1 ODD_3P3V_STBY_EN 39
SMC_P3_GPIO7 L21
OUT
V_5P0 V_5P0 SMC_P3_GPIO7
SMC_P2_GPIO3 G3 ODD_PWR_EN 39
USB_AUX_OCP_FLT_N M22
OUT R5R8 1 1 R5T10
36 IN SMC_P3_GPIO6 4.7 KOHM 4.7 KOHM
SMC_P2_GPIO2 H5 ODD_OPEN 39 5% 5%
1 R6R22 1 R6R23 VREG_V5P0_PWRGD N22
OUT 1
FTP FT5R1
54 IN SMC_P3_GPIO5 CH 2 2 CH
10 KOHM 10 KOHM SMC_P2_GPIO1 J5 ODD_STATUS 39 402 402
5% 5% VREG_V5P0_EN N21
IN 1
FTP FT5R2
54 69 OUT SMC_P3_GPIO4
2 CH 2 CH SMC_P2_GPIO0 J6 ODD_WAKE_N 39
402 402
VREG_PWRGPB_PWRGD P21
IN
57 51 50 IN SMC_P3_GPIO3
58 57 51 50 69 VREG_PWRGPB_EN R21 SMC_P3_GPIO2 R5R7

OUT J21 SOC_THERMTRIP_R 1 2 SOC_THERMTRIP
SMC_P1_GPIO7 IN 8
56 53 52 VREG_PWRGPA_PWRGD R22 SMC_P3_GPIO1 0 OHM 5% R5R5
IN H21 SOC_PWR_OK_R 402 CH 1 2 SOC_PWR_OK
SMC_P1_GPIO6 OUT 8 44 68
56 53 52 69 VREG_PWRGPA_EN P23 SMC_P3_GPIO0 R5R9 0 OHM 5%
OUT J22 SOC_RESET_N_R 1 2 402 CH SOC_RST_N
SMC_P1_GPIO5 OUT 68 8
1 R6R6 1 R6R7 0 OHM 5% R5R12
V_3P3STBY 10 KOHM 10 KOHM K22 SP_SMC_INT_N_R 402 CH 1 2 SP_SMC_INT_N
5% 5%
SMC_P1_GPIO4 IN 8
V_SOC1P8 1
B 2 CH
402
2 CH
402
FT6R11 FTP
SMC_P1_GPIO3 J23 FAN_PWM
OUT 40
0 OHM 5%
402 CH B
R5R6 1
1 R4D26 70 SMC_RXD V25 SMC_UART1_RXD SMC_P1_GPIO2 H25 SMC_P1_GPIO2 4.7 KOHM 1
1.27 KOHM 1 R4D27 IN 5% FTP FT5R3
1% 1.27 KOHM 1 R5T11 1 R5T9 FT6R12 FTP
1
J25 SMC_P1_GPIO1 CH 2
1% 2 KOHM 2 KOHM SMC_P1_GPIO1 402 1
2 CH 1% 1% FTP FT4T1
402 2 CH
402 2 CH 2 CH 70 IN SMC_CTS V26 SMC_UART1_CTS SMC_P1_GPIO0 H26 LED_NEXUS_R
OUT 40
402 402 R4D31
8 BI SB_SOC_DATA 1 2 SB_SOC_DATA_R 1
FTP FT6R19
243 OHM 1%
402 CH R4D33 AE21 SMBUS3_SDA SMC_P0_GPIO7 M23 HDMI_V_5P0_EN 38 R5R33
SB_SOC_CLK 1 2 SB_SOC_CLK_R AD21
OUT 1 2 USB_AUX_EN
8 OUT SMBUS3_SCK OUT 36
243 OHM 1% 1 SMC_P0_GPIO6 M24 PSU_V12P0_EN 41 42 0 OHM 5%
FT6R6 FTP
1
1
FTP FT6R20 OUT
FTP FT6R7 R4D38 402 CH 402 CH
53 52 50 44 40 BI SMBUS_DATA 1 2 SMBUS_DATA_R AE20 SMBUS2_SDA SMC_P0_GPIO5 L23 DP0_HPD
IN 38
66 65 64 54 0 OHM 5% SMBUS_CLK_R AF20 SMBUS2_SCK
402 CH SMC_P0_GPIO4 K24 WIFI_RESET_N 36 R5R34
OUT 1 2 IR_BLAST_EN
R4D39 OUT 63
52 50 40 65 44 OUT SMBUS_CLK 1 2 HDMI_TX_DDC_DATA_SB H6 SMBUS1_SDA SMC_P0_GPIO3 L25 ENET_V_3P3STBY_EN
OUT 32 0 OHM 5%
66 64 54 53 0 OHM 5% HDMI_TX_DDC_CLK_SB G6 SMBUS1_SCK R6R24 402 CH
402 CH SMC_P0_GPIO2 M25 HDMI_RX_DDC_5V_E_R 1 2 HDMI_RX_DDC_5V_E 37
IN
R5D2 0 OHM 5%
HDMI_TX_DDC_DATA 1 2
HDMI_RX_DDC_DATA_SB G5 SMBUS0_SDA SMC_P0_GPIO1 L26 SMC_DBG_LED0_SWO
OUT 65 402 CH
38 BI HDMI_RX_DDC_CLK_SB F5 SMBUS0_SCK
49.9 OHM1% SMC_P0_GPIO0 K26 VREG_SB1P8_EN 60
402 CH AC14
OUT
SECURITY_BYPASS
R5D1 N26 SMC_IR_IN
38 OUT HDMI_TX_DDC_CLK 1 2
V_5P0STBY
A 49.9 OHM1%
402 CH
BGA515
A
R5C28 D5C1 X861949-001
37 BI HDMI_RX_DDC_DATA 1 2 2
49.9 OHM1%
402 CH 6 V_5P0STBY
R5C27 D5C1
37 OUT HDMI_RX_DDC_CLK 1 2 1
10 OHM 1% 5
402 CH
DIO 3
40 IR_DATA
IN 4
PAGE
THESE SIGNALS ARE NOT COMPLETE- ENDING IS CLK OR P AND N DIO GREYBULL_RETAIL
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
KIC, FACET
D D
1
FT6R15 FTP
1
FT6R18 FTP 1
FTP FT6R16
1
FTP FT6R17
I38
U4D2 KIC IC
2 of 11
65 IN KER_DBG_CTS R26 UART0_CTS UART0_TXD U25 KER_DBG_TXD OUT 65
C 1
IN KER_DBG_RXD U26 UART0_RXD UART0_RTS T25 KER_DBG_RTS OUT 65
C
FT6T1 FTP
65 IN SPI_SS_N AF13 SPI_SS_N 1
1 R4D3 FTP FT6T4
FTCT3 FTP
65 IN SPI_MOSI AF11 SPI_MOSI SPI_MISO AE12 SPI_MISO_R 1 2 SPI_MISO
OUT 65
1 36.5 OHM1%
FT6T2 FTP SMM_GPIO3 (N24)
65 IN SPI_CLK AE11 SPI_CLK_IN 402 CH
N24 SMM_GPIO3 OVERLOADED ON SLT
GPIO3 BI
P24 SMM_GPIO2 SYSTEMS
GPIO2 BI
GPIO1 P25 SMM_GPIO1
SB_TDI AA13 P26 SMM_GPIO0
BI
65 IN TDI GPIO0 BI
65 SB_TMS AB14 TMS
IN SB_TRST AB12
IN TRST
65 SB_TCK AB13 TCK TDO AA12 SB_TDO 65
IN H22 POR_ATB 1
OUT
POR_ATB
DB6R2
1 TP
FT6R1 FTP
1 X861949-001 BGA515
FT6R3 FTP
1 1
FT6R5 FTP FTP FT6R2
1
FT6R4 FTP R6R16
40 FAN_TACH_IN 1 2
IN
100 OHM 5%
B 402 CH
B
R5R21
38 HDMI_DP_OUT_SEL 1 2
OUT
100 OHM 5%
402 CH
A A

PAGE
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
U4D2 KIC I4
9 of 11 IC
I3 AF1 VSS[0] VSS[68] L22
AF2 VSS[1] VSS[69] L24
D U4D2 KIC IC AF3 VSS[2] VSS[70] K6 D
8 of 11 AF7 VSS[3] VSS[71] K21
AF9 VSS[4] VSS[72] K23
AF10 VSS[5] VSS[73] K25
PEX_VSS[0] A26 AF12 VSS[6] VSS[74] J24
PEX_VSS[1] A25 AF15 VSS[7] VSS[75] J26
PEX_VSS[2] A24 AF17 VSS[8] VSS[76] H1
PEX_VSS[3] A22 AF19 VSS[9] VSS[77] AB21
PEX_VSS[4] B26 AF21 VSS[10] VSS[78] G4
PEX_VSS[5] B24 AF24 VSS[11] VSS[79] G25
PEX_VSS[6] B22 AF25 VSS[12] VSS[80] F3
PEX_VSS[7] C26 AF26 VSS[13] VSS[81] F7
E9 DP_VSS[0] PEX_VSS[8] C25 AE1 VSS[14] VSS[82] F8
A8 DP_VSS[1] PEX_VSS[9] C23 AE2 VSS[15] VSS[83] F18
D10 DP_VSS[2] PEX_VSS[10] D25 AE5 VSS[16] VSS[84] F23
D8 DP_VSS[3] PEX_VSS[11] D23 AE7 VSS[17] VSS[85] E1
A10 DP_VSS[4] PEX_VSS[12] E25 AE16 VSS[18] VSS[86] E21
C8 DP_VSS[5] PEX_VSS[13] E24 AE22 VSS[19] VSS[87] AB22
C9 DP_VSS[6] PEX_VSS[14] E22 AE23 VSS[20] VSS[88] AB23
C11 DP_VSS[7] PEX_VSS[15] F25 AE24 VSS[21] VSS[89] AB24
E11 DP_VSS[8] AE25 VSS[22] VSS[90] D18
AE26 VSS[23] VSS[91] D19
F4 SATA_VSS[0] USB3_VSS[0] AC1 AD3 VSS[24] VSS[92] AB25
E3 AC2 AD4 C16
C E5
SATA_VSS[1]
SATA_VSS[2]
USB3_VSS[1]
USB3_VSS[2] AC9 AD6
VSS[25]
VSS[26]
VSS[93]
VSS[94] C17 C
D1 SATA_VSS[3] USB3_VSS[3] AC10 AD8 VSS[27] VSS[95] C21
D2 SATA_VSS[4] USB3_VSS[4] AB3 AD9 VSS[28] VSS[96] B12
D4 SATA_VSS[5] USB3_VSS[5] AB4 AD18 VSS[29] VSS[97] AB26
C2 SATA_VSS[6] USB3_VSS[6] AB5 AC12 VSS[30] VSS[98] AA19
C6 SATA_VSS[7] USB3_VSS[7] AB6 AC13 VSS[31] VSS[99] AA20
C4 SATA_VSS[8] USB3_VSS[8] AB7 AC15 VSS[32] VSS[100] B18
B3 SATA_VSS[9] USB3_VSS[9] AB8 AC17 VSS[33] VSS[101] B19
B2 SATA_VSS[10] USB3_VSS[10] AA1 AC19 VSS[34] VSS[102] A12
B5 SATA_VSS[11] USB3_VSS[11] AA2 AC20 VSS[35] VSS[103] A17
B7 SATA_VSS[12] USB3_VSS[12] AA9 AC21 VSS[36] VSS[104] H23
A2 SATA_VSS[13] USB3_VSS[13] AA10 AB16 VSS[37] VSS[105] AB19
A3 SATA_VSS[14] USB3_VSS[14] AA11 AA14 VSS[38] VSS[106] AB20
A5 SATA_VSS[15] USB3_VSS[15] Y3 AA18 VSS[39] VSS[107] AC18
A7 SATA_VSS[16] USB3_VSS[16] Y4 V21 VSS[40] VSS[108] AC22
B1 SATA_VSS[17] USB3_VSS[17] Y5 U24 VSS[41] VSS[109] AC23
D6 SATA_VSS[18] USB3_VSS[18] W1 T11 VSS[42] VSS[110] AC26
USB3_VSS[19] W2 T12 VSS[43] VSS[111] AD23
USB3_VSS[20] V3 T13 VSS[44] VSS[112] AD25
R6 HDMI_VSS[0] USB3_VSS[21] V4 T15 VSS[45] VSS[113] AB18
N1 HDMI_VSS[1] USB3_VSS[22] V5 T16 VSS[46] VSS[114] AD20
N2 HDMI_VSS[2] USB3_VSS[23] U1 T22 VSS[47] VSS[115] AD19
B N4
N6
HDMI_VSS[3] USB3_VSS[24] U2
T3
T26
R11
VSS[48] VSS[116] AE19
AA21 B
HDMI_VSS[4] USB3_VSS[25] VSS[49] VSS[117]
M3 HDMI_VSS[5] USB3_VSS[26] T4 R24 VSS[50] VSS[118] AA22
M4 HDMI_VSS[6] USB3_VSS[27] T5 R25 VSS[51] VSS[119] AA23
L1 HDMI_VSS[7] USB3_VSS[28] R1 P12 VSS[52] VSS[120] AA24
L4 HDMI_VSS[8] USB3_VSS[29] R2 P14 VSS[53] VSS[121] AA25
K3 HDMI_VSS[9] USB3_VSS[30] P3 P22 VSS[54] VSS[122] AA26
J1 HDMI_VSS[10] USB3_VSS[31] P4 N15 VSS[55] VSS[123] Y21
H2 HDMI_VSS[11] N23 VSS[56] VSS[124] Y22
H3 HDMI_VSS[12] N25 VSS[57] VSS[125] Y23
H4 HDMI_VSS[13] M11 VSS[58] VSS[126] Y24
M14 VSS[59] VSS[127] Y25
M16 VSS[60] VSS[128] Y26
F14 PLL_VSS[0] M21 VSS[61] VSS[129] D13
E16 PLL_VSS[1] M26 VSS[62] VSS[130] D14
E13 PLL_VSS[2] L5 VSS[63] VSS[131] D15
L11 VSS[64] VSS[132] C13
L12 VSS[65] VSS[133] B13
L15 VSS[66] VSS[134] B14
X861949-001 BGA515 L16 B15
VSS[67] VSS[135]
VSS[136] A20
X861949-001 BGA515
A A

PAGE
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
V_12P0
KIC, CLOCKS + STRAPPING + POR R5R20

11.3 KOHM 1
1% C5R15
1 UF
CH 10%
CONNECT BYPASS PIN TO BACKUP CLOCK U4D2 KIC IC 402 16 V
D V_3P3
V_1P8STBY R5R19
2 X5R
603 D
1 of 11 1.13 KOHM
V_EXT_DET G21 V_EXT_DET 1% R4D29
G22 V_VDD18_DET CH
1 R5R16 F22 V12P0_PWRGD 402 1 2 SMC_RST_N
OUT 65 26
100 KOHM V_EXT_OK OUT 42 42
5% 1 KOHM 1% 1
2 CH 32 PEX_REF_CLK1_REQN C18 PEX_REF_CLK1_REQN SMC_RST_N_OUT AF22SMC_RST_N_OUT_R 402 CH C4D3
IN 270 PF
402 PEX_REF_CLK2_REQN C19 PEX_REF_CLK2_REQN 1 1 10%
I27 DB5D7 DB5D4 50 V
1 R5R17 2 X7R
100 KOHM AD22 VPGM CLK_MONITOR E17 SB_CLK_MONITOR 402
5%
BI
2 EMPTY BKUP_SB_SYNC_CLKP E18 100M_SYNC_CLK_BYPASS_DP R5D12
402
IN BKUP_SB_SYNC_CLKN E19 A21 RTC_CLK_OUT 1 2 X32K_X1
R5D5 IN 100M_SYNC_CLK_BYPASS_DP RTC_CLK_OUT OUT 8
0 OHM 5%
249 KOHM
1% R5D11 402 CH 1 R5D13
402 CH SMC_XTAL_OUT 1 2 SMC_XTAL_OUT_R A18 XTAL_CLK_OUT EMMC_CLK AC16 MMC_CLK 33 69.8 KOHM
SMC_XTAL_IN 0 OHM 5% 402 CH A19 C20 ENET_REF_CLK
OUT 1%
XTAL_CLK_IN ENET_REF_CLK
Y5D1 2 EMPTY
25 MHZ 2 R5D4 402
49.9 OHM R5B17
1% AD24 TEST SOC_NS_SYNC_CLK_DP B16 SOC_REF_NS_100M_CLKP 2 PEX_XTAL2 32
1 3 B17 SOC_REF_NS_100M_CLKN
OUT OUT
1 EMPTY SOC_NS_SYNC_CLK_DN OUT 2 100 OHM 1%
402 R5R18 402 EMPTY
1 GND1 2 1 1 2 SMC_BYPASS_CLK_IN D21 SMC_BYPASS_CLK_IN
C5D11 C5D10
C 22 PF
5%
GND2 4 22 PF
5%
10 KOHM 5%
402 CH
SOC_NS_AV_CLK_DP A13 SOC_AV_NS_100M_CLKP
A14 SOC_AV_NS_100M_CLKN
OUT 2
C
SOC_NS_AV_CLK_DN OUT 2
2
50 V SM 2
50 V
NPO NPO
402 XTAL 402
BKUP_SB_PEX_REF_CLKP E20 PCIE_BYPASS_CLK_DP PEX_REF_CLK2_DP B20 SOC_NB_PEX_SS_100M_CLKP 2
IN BKUP_SB_PEX_REF_CLKN D20 B21 SOC_NB_PEX_SS_100M_CLKN
OUT
IN PCIE_BYPASS_CLK_DN PEX_REF_CLK2_DN OUT 2
1 250M_CLK_BYPASS_DP F20 250M_CLK_BYPASS_DP PEX_REF_CLK1_DP C14 ENET_PEX_SS_100M_CLKP 32

DB5R2
1 250M_CLK_BYPASS_DN F21 C15 ENET_PEX_SS_100M_CLKN
OUT
DB5R3 250M_CLK_BYPASS_DN PEX_REF_CLK1_DN OUT 32
BKUP_SB_AV_CLKP D16 AV_CLK_BYPASS_DP PEX_REF_CLK0_DP A15 SOC_PEX_SS_100M_CLKP 2

IN BKUP_SB_AV_CLKN D17 A16 SOC_PEX_SS_100M_CLKN
OUT
IN AV_CLK_BYPASS_DN PEX_REF_CLK0_DN OUT 2
X861949-001 BGA515
B B
A A

PAGE
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
R6P11 V_5P0 V_3P3
43 V_VREG_12P0_TO_5P0_3P3 1 2 KIC3P3HDMI_C
IN
10 KOHM 1%
V_KIC1P8AUX 402 EMPTY 1 R6P4
V_SB1P8 10 KOHM 2 SOT23
3
R6P7 1% 1 AO3414L
FB5R7 Q6P1 1 KIC3P3HDMI_B 1 2 2 CH FET
1 2 EMPTY 10 KOHM 1% 402
3
Q6P2
60 OHM FB 2 402 EMPTY KIC3P3HDMI_G 1 R6P12
D 0.5 A
0.1DCR
603 V_KIC3P3HDMI
0 OHM
5% D
1 U4D2 IC FB6R7 2 EMPTY
1
C5R7 C5R14 KIC 1 2 KIC3P3HDMI_FB 402
4.7 UF
4.7 UF 10% 60 OHM FB
I3
10%
6.3 V 2
6.3 V 11 of 11 0.5 A 603
2 X5R 0.1DCR
X5R 603 E10 AUX_VDD18[0] HDMI_VDD33[0] M5
603 1
D9 AUX_VDD18[1] HDMI_VDD33[1] M6 C6R93 1
C6P11
D11 AUX_VDD18[2] 4.7 UF
10% 4.7 UF
U4D2 IC 6.3 V 10%
KIC 2 X5R 2
6.3 V
603 X5R
V_KIC1P8CK 603
10 of 11 V_SB1P8
V_3P3STBY V_SB1P1
FB6R3 I4 V_KIC1P1PLL0
V_KIC1P1SPLL2 1 2 F12 CK_VDD18[0] HDMI_VDD11[0] P5
V_1P1STBY V_SB1P1
VDD33S_1[0] AB15 60 OHM FB F13 CK_VDD18[1] HDMI_VDD11[1] P6 FB5R2
VDD33S_1[1] AB17 0.5 A 603 E12 CK_VDD18[2] HDMI_VDD11[2] N5 1 2
FB6R5 VDD33S_1[2] AA15
1
0.1DCR
1 2 AA16 C6R66 1 120 OHM FB
VDD33S_1[3] V_KIC3P3USB C6R47 0.2A A 603
120 OHM FB VDD33S_1[4] AA17 4.7 UF
10% 4.7 UF 0.5DCR 1
0.2A A 603 VDD33S_1[5] W21 V_3P3STBY 6.3 V 10% C5R5
0.5DCR 2 X5R 6.3 V 1 4.7 UF
1 1 VDD33S_1[6] W22
603 2 X5R C5R3 10%
C6R74 C6R75 H24 PLL2_VDD11S[0] VDD33S_1[7] W23 FB6R1 603 E14 PLL1_VDD18 PLL1_VDD11 F15 4.7 UF
10% 6.3 V
C 4.7 UF
10%
4.7 UF
10%
G23
G24
PLL2_VDD11S[1] VDD33S_2[0] L6
K5
1 2 E15 PLL0_VDD18 PLL0_VDD11 F16
2
6.3 V
X5R
2 X5R
603 C
6.3 V 6.3 V PLL2_VDD11S[2] VDD33S_2[1] 60 OHM FB V_KIC1P8PLL1 603
2 X5R 2 X5R 0.5 A 603 V_SB1P8
603 603 0.1DCR
1 FB5R3
1
C6R38 C6R15 V_KIC1P1PLL1
4.7 UF 1 2
4.7 UF 10% V_SB1P1
10% 6.3 V 60 OHM FB F24 PEX_VDD18[0] PEX_VDD11[0] G26 FB5R4
6.3 V 2 X5R 0.5 A 603 E23 F26
2 X5R 603 PEX_VDD18[1] PEX_VDD11[1] 1 2
USB2_VDD33S[0] AE10 603 0.1DCR 1
USB2_VDD33S[1] AD10 1
C5R9 C5R8 120 OHM FB
4.7 UF 0.2A A 603
USB2_VDD33S[2] AD11 4.7 UF 10%
10% 6.3 V 0.5DCR 1
V_1P1STBY 2
6.3 V 2 X5R 1 C5R11
X5R 603 C5R10 4.7 UF
603 4.7 UF 10%
V_KIC3P3XTAL 10% 6.3 V
T14 AD7 2 X5R
VDD11S[0] USB3_VDD18<0> 6.3 V 603
R12 V_KIC1P8PLL0 AC6 V6 2 X5R
VDD11S[1] V_3P3STBY V_SB1P8 USB3_VDD18<1> USB3_VDD11<0> 603
R13 VDD11S[2] VDD33S_XTAL[0] F19 AA6 USB3_VDD18<2> USB3_VDD11<1> U5
R14 VDD11S[3] VDD33S_XTAL[1] F17 FB5R1 Y6 USB3_VDD18<3> USB3_VDD11<2> U6
R15 VDD11S[4] V_1P8STBY FB6R4 1 2 W6 USB3_VDD18<4> USB3_VDD11<3> T6
R16 VDD11S[5] 1 2 V_SB1P1
P11 AD26 60 OHM FB
VDD11S[6] VDD18S[0] 60 OHM FB 0.5 A 603
P13 VDD11S[7] VDD18S[1] AC24 0.5 A 603 0.1DCR
0.1DCR 1
B P15 VDD11S[8] VDD18S[2] AC25
1 1
1
C5R4 C5R2
P16
N11
VDD11S[9] VDD18S[3] W24
W25
C6R69
4.7 UF
C6R73
4.7 UF
4.7 UF
10%
4.7 UF
10% B
VDD11S[10] VDD18S[4] 10% 10% 6.3 V
N12 W26 6.3 V 2 X5R 1
VDD11S[11] VDD18S[5] 6.3 V 6.3 V 2 X5R 603 1 C6R90
N13 2 X5R 2 X5R 603 C6R89
VDD11S[12] 603 603 4.7 UF
N14 VDD11S[13] E2 SATA_VDD18[0] SATA_VDD11[0] F6 10 UF 10%
N16 20% 6.3 V
VDD11S[14] E4 SATA_VDD18[1] SATA_VDD11[1] E6 6.3 V 2 X5R
M12 AD14 2 X5R 603
VDD11S[15] FLSH_VDD18S[0] 603
M13 VDD11S[16] FLSH_VDD18S[1] AD13 V_SB1P8
M15 VDD11S[17] FLSH_VDD18S[2] AD12 V_1P8STBY
L13 VDD11S[18] FLSH_VDD18S[3] AE13
L14 VDD11S[19] V_SB1P1
V_SB1P8 V_SB1P1
1 1
X861949-001 BGA515 C5R12 C5R13 E7
1 UF 10 UF DP_VDD11[0]
10% 20% C7 DP_VDD18[0] DP_VDD11[1] E8
6.3 V 6.3 V D7 F9
2 X5R 2 X5R DP_VDD18[1] DP_VDD11[2] 1
402 603 1
C6R92 C6P9
4.7 UF
10 UF 10%
20% 6.3 V
X861949-001 BGA515 6.3 V 2 X5R
2 X5R 603
603
V_KIC1P8USB
V_SB1P8
FB6R2 V_SB1P1
1 2
60 OHM FB
0.5 A 603
A 1
0.1DCR
1
A
C6R55 C6R33
4.7 UF 4.7 UF 1
10%
6.3 V
10%
6.3 V
1
C6P18 C6P17
2 2 4.7 UF
X5R X5R 10 UF 10%
603 603 20% 6.3 V
6.3 V 2 X5R
2 X5R 603
603

PAGE
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
KIC, DECOUPLING
D D
V_1P1STBY V_KIC1P8AUX V_SB1P1 V_3P3STBY V_1P8STBY V_KIC1P8USB V_KIC3P3XTAL V_SB1P1

V_KIC1P1SPLL2
C6R4 C6R60
C5R6 1 2 1 2 C6R43 C6R12
C6R70 C6R59 1 2 1 2 1 2 C6R63 C6R16
1 2 1 2 1 2 1 2 C6R77
1 UF 10% 1 UF 10% 1 2
4.7 UF 10% 6.3 V 6.3 V 1 UF 10% 1 UF 10%
4.7 UF 10% 1 UF 10% 6.3 V X5R X5R 6.3 V 6.3 V 1 UF 10% 1 UF 10%
6.3 V 6.3 V X5R X5R X5R 6.3 V 6.3 V 1 UF 10%
X5R X5R 402 402 X5R X5R 6.3 V
603 402 402 X5R
603 402 402 402
C6R13 C6R76 402
C6R1 1 2 1 2 C6R82 C6R22 C6R72
C6R24 C6R51 1 2 1 2 1 2 1 2 C6R18
C 1 2 1 2
1 UF 10% 1 UF 10%
1 2
1
C6R79
2 C
1 UF 10% 6.3 V 6.3 V 1 UF 10% 1 UF 10% 1 UF 10%
4.7 UF 10% 1 UF 10% 6.3 V X5R X5R 6.3 V 6.3 V 6.3 V 1 UF 10%
6.3 V 6.3 V X5R X5R X5R X5R 6.3 V 1 UF 10%
X5R X5R 402 402 X5R 6.3 V
402 402 402 402 X5R
603 402 C6R25 C6R57 402
C6R2 1 2 1 2 C6R44 C6R23 402
C6R53 C6R40 1 2 1 2 1 2 C6R17
1 2 1 2 1 2 C6R80
1 UF 10% 1 UF 10% 1 2
1 UF 10% 6.3 V 6.3 V 1 UF 10% 1 UF 10%
1 UF 10% 1 UF 10% 6.3 V X5R X5R 6.3 V 6.3 V 1 UF 10%
6.3 V 6.3 V X5R X5R X5R 6.3 V 1 UF 10%
X5R X5R 402 402 X5R 6.3 V
402 402 402 X5R
402 402 C6R26 C6R78 402
C6R29 1 2 1 2 C6R85 C6R6 402
1
C6R42
2 C6R68
1 2 1 2 1 2 V_KIC3P3USB 1
C6R7
2
1 2 1 UF 10% 1 UF 10%
1 UF 10% 6.3 V 6.3 V 1 UF 10% 1 UF 10%
1 UF 10% 6.3 V X5R X5R 6.3 V 6.3 V 1 UF 10%
6.3 V 1 UF 10% X5R X5R X5R 6.3 V
X5R 6.3 V 402 402 X5R
X5R 402 402 402 C6R34
402 1 2 402
402 C6R8 C6R21
C6R36 1 2 1 2 C6R83 C6R27
C6R61 1 2 1 2 1 2 1 UF 10%
1 2
1
C6R67
2 6.3 V V_SB1P8
1 UF 10% 1 UF 10% X5R
1 UF 10% 6.3 V 6.3 V 1 UF 10% 1 UF 10%
1 UF 10% 6.3 V X5R X5R 6.3 V 6.3 V 402
6.3 V 1 UF 10% X5R X5R X5R
X5R 6.3 V 402 402 C6R28
X5R 402 402 402 1 2
402 C5R1
402 C6R19 C6R11 1 2
C6R37 1 2 1 2 C6R86
B 1
C6R31
2
1
C6R30
2
1 2 1 2 1 UF 10%
6.3 V
X5R 1 UF 10% B
1 UF 10% 1 UF 10% 6.3 V
1 UF 10% 6.3 V 6.3 V 1 UF 10% 402 X5R
1 UF 10% 6.3 V X5R X5R 6.3 V
6.3 V 1 UF 10% X5R X5R V_SB1P8 402
X5R 6.3 V 402 402 C6R39
X5R 402 402 1 2
402 C6R20
402 C6R41 C6R64 1 2
1 2 1 2 C6R48 1 UF 10%
C6R32 1 2
1 2 6.3 V V_KIC3P3HDMI 1 UF 10%
1 UF 10% 1 UF 10% X5R 6.3 V
6.3 V 6.3 V 1 UF 10% C6R84 402 X5R
1 UF 10% X5R X5R 6.3 V 1 2
6.3 V X5R 402
X5R 402 402
402 1 UF 10%
402 C6R5
6.3 V 1 2
C6R71 X5R
1 2
402 1 UF 10%
1 UF 10% C6R81 6.3 V
6.3 V V_KIC1P8CK 1 2 X5R
X5R 402
402 1 UF 10% C6R9
6.3 V 1 2
V_SB1P1 X5R
C6R52 V_SB1P1 402
1 2 1 UF 10%
6.3 V
X5R
1 UF 10% 402
6.3 V C6R14
X5R C6R87 1 2
V_KIC1P8PLL0 V_KIC1P8PLL1 402
1 2
C6R46 1 UF 10% V_KIC1P1PLL1
1 2 1 UF 10% 6.3 V V_KIC1P1PLL0
6.3 V X5R
X5R 402
1 UF 10% 402
C6R54 C6R49 6.3 V
1 2 1 2 X5R C6R10
C6R88 1 2
A 1 UF 10% 1 UF 10%
402
C6R45
1 2
1
C6R62
2
1
C6R65
2 A
6.3 V 6.3 V 1 2 1 UF 10%
X5R X5R 1 UF 10% 6.3 V
6.3 V X5R 1 UF 10%
402 402 X5R 1 UF 10% 6.3 V
1 UF 10% 402 6.3 V X5R
6.3 V 402 X5R
X5R 402
402
402

PAGE
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
RT4B1
V_3P3STBY 1 2
V_3P3STBY_ENET
CONTROLLER, ETHERNET 01.10 A EMPTY
1206 V_3P3STBY_ENET
V_3P3STBY_ENET V_3P3 1
C6N2 U4B5 IC
0.1 UF TPS2065
1 R5B2 R5B15 10% 5 1
D 10 KOHM 26 1 2 1 R5P1 6.3 V
2 X5R
IN OUT
D
5%
OUT 1 KOHM 402 1 1
29 10 KOHM 5% 5% OC_N 3 V_3P3STBY_ENET_FLT_N C4B6 C4B5 1
2 CH IN 402 CH 10 UF 10 UF C6N1
402 29 IN 2 CH 20% 20% 0.1 UF
C5B6 402 26 IN ENET_V_3P3STBY_EN 4 EN GND 2 6.3 V 6.3 V 10%
2 PEX_ENET_SOC_TP_C 1 2 1 R5N3
2 X5R
603
2 X5R
603 2 6.3
X5R
V
OUT FT5N9 FTP
1 15 KOHM 1 R6N2 X862402-001 402
29 OUT C5B8 1 10 KOHM
1 2 6.3 V 10% 1% FT6N2 FTP 5% SOT23-5
2 OUT PEX_ENET_SOC_TN_C 402 X5R 2 EMPTY
402 2 CH 1
DB4B8
0.1 UF 402
V_3P3STBY_ENET 6.3 V 10%
402 X5R
0.1 UF V_3P3STBY_ENET
U5B2 IC
1 R5B13 RTL8151GNM
10 KOHM ENET_WAKE_N 28 LANWAKEB DVDD33_1 27
5% ENET_ISOLATE_N 26 39
ISOLATEB DVDD33_2
2 EMPTY
26 IN 402 1 1
ENET_PEX_SS_100M_CLKP 19 REFCLK_P DVDD10_1 13 C5N9 C5N16 1 C5N1 1
C5N6 1 C5N2 1
C5N10
ENET_PEX_SS_100M_CLKN 20 REFCLK_N DVDD10_2 29 0.1 UF 0.1 UF 0.1 UF 0.1 UF 0.1 UF 0.1 UF
10% 10% 10% 10% 10% 10%
1 R5B16 PEX_ENET_SOC_TP 22 HSOP DVDD10_3 41 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V
10 KOHM PEX_ENET_SOC_TN 23 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R
5% HSON 402 402 402 402 402 402
2 IN PEX_SOC_ENET_TP_C 17 HSIP AVDD10_1 3
2 CH PEX_SOC_ENET_TN_C 18 6
402 2 IN HSIN AVDD10_2
ENET_RST_N 25 9 V_1P0STBY
C PEX_REF_CLK1_REQN 16
PERSTB
CLKREQB
AVDD10_3
AVDD10_4 45 C
1
FTP FT5N8
PEX_XTAL1 43 CKXTAL1 EVDD10 21
29 PEX_XTAL2 44 CKXTAL2
IN
V_1P0STBY 1L5B12 ENET_REGOUT 36 REGOUT AVDD33_1 12
1
C5N11 1 C5N7 1
C5N14 1 C5N5 C5N8 1
C5N12 1 C5N13 1 C5N4 1
C5N3
33 ENSWREG AVDD33_2 42 0.1 UF 0.1 UF 0.1 UF 0.1 UF 1 UF 0.1 UF 0.1 UF 0.1 UF 0.1 UF
4.7 UH IND 10% 10% 10% 10% 10% 10% 10% 10% 10%
0.9 A SM 34 VDDREG1 AVDD33_3 47 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V
R5B7 0.2 OHM 35 48 2 X5R 2 X5R 2 X5R 2 X5R X5R 2 X5R 2 X5R 2 X5R 2 X5R
1 C5B9 1 VDDREG2 AVDD33_4 402 402 402 402 402 402 402 402 402
49.9 OHM C5B7 ENET_RSET 46 RSET
1% 0.1 UF 4.7 UF 1 MDIP0
10% 10% MDIP0 BI 34
R5B8 CH 32 2 MDIN0
402 10 V 6.3 V EEDI/SDA MDIN0 BI 34
0 OHM 2 X5R 2 X5R 30 EECS/SCL MDIP1 4 MDIP1 34
5% 402 805 1 R5B6 5 MDIN1
BI
MDIN1 BI 34
Y5B1
PEX_XTAL_2_R
CH 2.49 KOHM 40 7 MDIP2

402 V_3P3STBY_ENET 1% LED0 MDIP2 BI 34
25 MHZ 37 LED1/EESK MDIN2 8 MDIN2
BI 34
2 CH 31 10 MDIP3
402 LED2/EEDO MDIP3 BI 34
1 3 MDIN3 11 MDIN3 34
BI
PEX_XTAL_1_R
14 NC
GND1 2 15 SMBDATA GND1 24
GND2 4 71 ENET_EEDI 38 GPO GND2 49
OUT
B SM
1
C5N17 1 C5N15 1 X862048-001 QFN49
ENET_SMBDATA
B
ENET_SMBCLK
4.7 UF 0.1 UF
ENET_SMBALERT_N
C5B4 10% 10%
FT5N3 FTP
XTAL 18 PF 6.3 V 10 V
C5B5 5%
50 V
2 X5R 2 X5R 71 OUT ENET_EECS
18 PF 805 402
5% NPO
50 V 402 1 V_3P3STBY_ENET
NPO FT5N4 FTP
402
71 ENET_EESK
OUT
1 R5B9
FT5N5 FTP 1 2
71 ENET_EEDO 1 KOHM 5%
IN 402 EMPTY
1
FT5N6 FTP
1 R5N1
1 R5N2 10 KOHM V_3P3STBY V_3P3STBY_ENET
10 KOHM 5%
5%
ENET_LED0_R
2 EMPTY
2 EMPTY 402 R5B3
402 1 2
V_3P3STBY_ENET 1 KOHM 5%
402 EMPTY
1 R4B16
FT5N7 FTP 1 2
D5B1 R5B11 0 OHM 5%
DB5B1
1 1 2 EMPTY
1210
511 OHM 1%
2 4 ENET_LED0 402 EMPTY
R5B5
1 2
1 3 ENET_LED1
R5B12 1 KOHM 5%
402 EMPTY
A EMPTY
YELLOW-GREEN DB5B2
1 1 2 A
SM 511 OHM 1%
402 EMPTY 1 R5B4
10 KOHM
5%
D5B2 2 EMPTY R5B5
R5B14 402 EEPROM CONFIG (93C66) CHIPSET U5B1 C5B3 R5B3 R5B4 R5N2 R5B9 R5N1
1 2 ENET_LED3 1 2
511 OHM 1% GREYBULL WITH EEPROM RTL8151GNM STUFF STUFF STUFF EMPTY STUFF EMPTY EMPTY
GREEN 1 402 EMPTY
SM EMPTY DB5B3 GREYBULL W/O EEPROM RTL8151GNM EMPTY EMPTY EMPTY EMPTY EMPTY EMPTY EMPTY

PAGE
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
V_1P8STBY
EMMC MS_PART#
U3D1
U3D1
U3D1
MATL REF_DES
X866677-001
X875870-001
X867925-001
IC
IC
IC
MEM,SM,8GB,FLASH,EMMC
TRUEDESCR.
EMMC_TOSH
TRUE
EMMC_SEC
TRUE
EMMC_HX
BOM PROPERTY
R4D4 1 2 10 KOHM I477

402 CH 1%
R4D9 1 2 10 KOHM
402 CH 1% V_1P8STBY
D R4D13 1 2 10 KOHM
D
402 CH 1% V_1P8STBY
R4D11 1 2 10 KOHM
402 CH 1%
R4D17 1 2 10 KOHM
402 CH 1%
1
R4D15 1 2 10 KOHM
1
C7R4
1
C3D8
1
C7R5 C7R9 1 C6R50 1 C6R58 1
C6R56
402 CH 1% 0.1 UF 0.1 UF 2.2 UF 1 UF 0.1 UF 0.1 UF 2.2 UF
10% 10% 20% 10% 10% 10% 20%
R4D21 1 2 10 KOHM 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V
402 CH 1% 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R
402 402 402 402 402 402 402
R4D19 1 2 10 KOHM U3D1 IC
402 CH 1%
R4D23 1 2 10 KOHM emmc_169pin

402 CH 1%
R4D10 1 R4D7 1 of 3 VCCQ4 AA5 V_3P3STBY
10 KOHM AA3
33 MMC_DATA<7> 1 2 VCCQ3
BI 1%
402 Y4
0 OHM 5% R4D14 2
CH
1/16W
VCCQ2
33 MMC_DATA<6> 402 CH 1 2 VCCQ1 W4
BI X806693-001
K6
R4D12 0 OHM 5% VCCQ0
33 MMC_DATA<5> 1 2 402 CH 1 1 1
BI MMC_DATA_R<7> J6 U9 C7R6 C7R7 C7R8
R4D18 0 OHM 5% DATA7 VCC3 0.1 UF 0.1 UF 2.2 UF
33 MMC_DATA<4> 1 2 402 CH MMC_DATA_R<6> J5 DATA6 VCC2 T10 10% 10% 20%
BI MMC_DATA_R<5> J4 N5 6.3 V 6.3 V 6.3 V
R4D16 0 OHM 5% DATA5 VCC1 2 X5R 2 X5R 2 X5R
MMC_DATA<3> 1 2 402 CH MMC_DATA_R<4> J3 M6
C 33 BI
0 OHM 5% R4D22 MMC_DATA_R<3> J2
DATA4
DATA3
VCC0 402 402 402
C
33 MMC_DATA<2> 402 CH 1 2 MMC_DATA_R<2> H5 DATA2 VDDI K2 VDDI_ROUTE
BI MMC_DATA_R<1> H4
0 OHM 5% R4D20 DATA1
33 MMC_DATA<1> 402 CH 1 2 MMC_DATA_R<0> H3 DATA0 VSSQ4 AA6 1
BI AA4 C3D9
0 OHM 5% R4D24 VSSQ3 1 UF
33 MMC_DATA<0> 402 CH 1 2 VSSQ2 Y5 10%
BI Y2 6.3 V
R4D8 0 OHM 5% VSSQ1 2 X5R
33 MMC_CMD 1 2 402 CH MMC_CMD_R W5 CMD VSSQ0 K4 402
BI U8
0 OHM 5% R4D2 VSS3
29 MMC_CLK 402 CH 1 2 MMC_CLK_R W6 CLK VSS2 R10
BI P5
MMC_RST_N
0 OHM 5% R4D6 MMC_RST_N_R U5
VSS1
M7 MMC_X NETS ARE DUMMY NETS
33 BI 402 CH 2 1 RSTN VSS0
1 TO IMPROVE PAD ADHESION
1 KOHM
DB3D3
1 R4D36 5%
402
FT7R1 FTP
1 BGA169B
10 KOHM CH X866676-001
1%
2 EMPTY U3D1 IC U3D1 IC
402
eMMC_169PIN eMMC_169PIN
1 2 of 3 3 of 3
FT7R2 FTP A4 K14
U4D2 KIC IC NC0 NC35 AA7 RFU0 NC87 W7
MMC_DATA<7..0> BI 33 A6 NC1 NC36 L1 AA10 RFU1 NC88 W8
5 of 12 I446 A9 NC2 NC37 L2 H6 RFU2 NC89 W9
B MMC_DATA7 AE18 7 A11
B2
NC3 NC38 L3 D5
L4
H7 RFU3 NC90 W10
W11 B
AD15 6 NC4 NC39 D6 K5 RFU4 NC91
MMC_DATA6 B13 NC5 L12 M5 W12
AE15 5 NC40 RFU5 NC92
MMC_DATA5 D1 NC6 L13 M8 W13
AD16 4 NC41 RFU6 NC93
MMC_DATA4 D14 L14 M9 W14
MMC_DATA3 AF16 3 NC7 NC42 DB633 RFU7 NC94
MMC_X7 H1 M1 M10 Y1 MMC_X11
1
AF18 2 NC8 NC43 RFU8 NC95
MMC_DATA2 H2 NC9 M2 N10 Y3
AD17 1 D4 NC44 RFU9 NC96
MMC_DATA1 H8 NC10 M3 P3 Y6
AE17 0 NC45 RFU10 NC97
MMC_DATA0 H9 NC11 M12 P10 Y7
NC46 RFU11 NC98
H10 NC12 NC47 M13 R5 RFU12 NC99 Y8
MMC_CMD AF14 MMC_CMD 33
OUT H11 NC13 NC48 M14 DB634 T5 RFU13 NC100 Y9
H12 N1 U6 Y10
1
AE14 MMC_RST_N NC14 NC49 RFU14 NC101
MMC_RESET_N OUT 33 MMC_X6 H13 NC15 N2 U7 Y11
NC50 RFU15 NC102
MMC_X4 H14 NC16 NC51 N3 U10 RFU16 NC103 Y12
MMC_X8 J1 NC17 NC52 N12 NC104 Y13
X861949-001 BGA515 J7 NC18 NC53 N13 T13 NC70 NC105 Y14 MMC_X3
J8 NC19 NC54 N14 DB637 DB638T14 NC71 NC106 AA1 MMC_X10
J9 P1 U1 AA2 MMC_X12
1
NC20 NC55 NC72 NC107
J10 NC21 NC56 P2 U2 NC73 NC108 AA8
J11 NC22 NC57 P12 U3 NC74 NC109 AA9
J12 NC23 NC58 P13 U12 NC75 NC110 AA11
J13 NC24 NC59 P14 DB635 U13 NC76 NC111 AA12
MMC_X5 J14 R1 U14 AA13 MMC_X2
1
NC25 NC60 NC77 NC112
D3 K1 NC26 NC61 R2 V1 NC78 NC113 AA14 MMC_X1
SIGNALS ROUTED TO NC PINS FOR ESCAPE D5 K3 NC27 NC62 R3 V2 NC79 NC114 AE1
D7 K7 NC28 NC63 R12 V3 NC80 NC115 AE14
D7 PIN J6 ROUTED TO PIN K7, K8 K8 NC29 NC64 R13 V12 NC81 NC116 AG2
D6 PIN J5 ROUTED TO PIN K5 K9 NC30 NC65 R14 DB636 V13 NC82 NC117 AG13
K10 T1 V14 AH4
1
A
D5
D4
PIN
PIN
J4
J3
ROUTED
ROUTED
TO
TO
PIN
PIN
K3, L3
H2 K11
NC31
NC32
NC66
NC67 T2 W1
NC83
NC84
NC118
NC119 AH6 A
D3 PIN J2 ROUTED TO PIN K1 K12 NC33 NC68 T3 W2 NC85 NC120 AH9
K13 NC34 NC69 T12 W3 NC86 NC121 AH11
VDDI PIN K2 ROUTED TO PIN L1 X866676-001 BGA169B X866676-001 BGA169B
GND PIN Y2 ROUTED TO PIN W1

[PAGE_TITLE=EMMC] DRAWING
CONFIDENTIAL
PAGE
33/72 M 1.0
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
CONN, RJ45 + TOSLINK

V_5P0
D D
1
C8A4
1 UF
10%
6.3 V
2 X5R
402 J8A2 CONN
TOSLINK
2 VCC
2 SPDIF_OUT 3 VIN
IN 1 GND
1
1
C8A1 EG8A1
22 PF
5%
X882235-001 45 EMI1
EMI2
50 V 6
J5A1 CONN 2 NPO EMPTY EMI3
402 7 EMI4
RJ45 10P 402
2
34 32 MDIP0 1 TRD1_P
BI MDIN0 2 X866874-003 TH
34 32 BI TRD1_N
BI MDIN1 4
34 32 BI TRD2_N
BI MDIN2 8
C 34 32 BI TRD3_N
C
BI MDIN3 10
34 32 BI TRD4_N
RJ45_CT1 5 CT1 SHLD1 11
6 CT2 SHLD2 12
1
C5B2 X866473-004
0.01 UF
10% TH
16 V
2 X7R
402
EG5B4 EG5B5
EMPTY EMPTY
SP3010 SP3010
B 34 32 BI MDIN3 1 D1A 34 32 BI MDIN1

MDIN1
1
10
D1A
D1B B
MDIN3 10 D1B 34 32 BI
34 32 BI
34 32 MDIP1 2 D2A
34 32 BI MDIP3 2 D2A BI MDIP1 9 D2B
MDIP3 9 D2B 34 32 BI
34 32 BI
34 32 MDIN0 4 D3A
34 32 BI MDIN2 4 D3A BI MDIN0 7 D3B
MDIN2 7 D3B 34 32 BI
34 32 BI
34 32 MDIP0 5 D4A GNDA 3
34 32 BI MDIP2 5 D4A GNDA 3 BI MDIP0 6 D4B GNDB 8
MDIP2 6 D4B GNDB 8 34 32 BI
34 32 BI
CONNECT As TO Bs
CONNECT As TO Bs
X863136-001 X863136-001
DFN10 DFN10
A A

PAGE
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
CONN, USB
EG7B1 V_5P0DUAL
ESD ARRAY
D SP3011 D
RT7A1
USB3_BP_P0_RN 8 D1A 1 2
24 35 BI USB3_BP_P0_RN 7 D1B
V_5P0_USB3_P0
24 35 BI
01.50 A THRMSTR 1 C7B1 2 C7A2 2 C7A1
USB3_BP_P0_RP 9 220 UF 470 PF 4.7 UF
24 35 BI D2A 1812 20% 5% 10% BOTTOM SLOT
24 35 USB3_BP_P0_RP 6 D2B 10 V 50 V 6.3 V
BI ELEC X7R X5R
2 RDL 1 402 1 603
35 24 USB2_BP_P0_DN 11 D3A
BI USB2_BP_P0_DN 4 D3B USB2_BP_P0_DN J7A2 CONN
35 24 BI 35 24 BI
35 24 BI USB2_BP_P0_DP USB3 DUAL
35 24 USB2_BP_P0_DP 12 D4A 1 VBUS
BI USB2_BP_P0_DP 3 D4B 2
35 24 BI USB3_BP_P0_RN D-
24 35 OUT 3 D+
24 35 USB3_BP_P1_RN 13 D5A 4 GND
BI USB3_BP_P1_RN 2 D5B 5
24 35 BI STDA_SSRX_N
6 STDA_SSRX_P
USB3_BP_P1_RP 14 10 24 35 OUT USB3_BP_P0_RP 7
24 35 BI D6A GNDA GND_DRAIN
24 35 USB3_BP_P1_RP 1 D6B GNDB 5 USB3_BP_P0_TN_CMC 8 STDA_SSTX_N MTH1 19
BI USB3_BP_P0_TP_CMC 9 20
STDA_SSTX_P MTH2
CM7B4
CONNECT As TO Bs 24 USB3_BP_P0_TN 4 3 X865822-004
IN TH
C X863137-001 C
DFN14 CHK
EG7B2 24 IN USB3_BP_P0_TP 1 2
ESD ARRAY 80 OHM
SM
SP3011 X869713-001
V_5P0DUAL
35 USB3_BP_P1_TN_CMC 8 D1A
BI USB3_BP_P1_TN_CMC 7 D1B RT7B2
35 BI 1 2 V_5P0_USB3_P1
35 USB3_BP_P1_TP_CMC 9 D2A 1 C7B4
BI USB3_BP_P1_TP_CMC 6 D2B 01.50 A THRMSTR 2 C7B3 2 C7B2
35 BI 220 UF 470 PF 4.7 UF
1812 20% 5% 10% TOP SLOT
USB2_BP_P1_DN 11 10 V 50 V 6.3 V
35 24 BI D3A ELEC X7R X5R
35 24 USB2_BP_P1_DN 4 D3B 2 RDL 1 402 1 603
BI USB2_BP_P1_DN J7A2 CONN
35 24 BI
35 24 BI USB2_BP_P1_DP 12 D4A 35 24 BI USB2_BP_P1_DP USB3 DUAL
35 24 USB2_BP_P1_DP 3 D4B 10 VBUS
BI 11
USB3_BP_P1_RN D-
USB3_BP_P0_TN_CMC 13 D5A 24 35 OUT 12
35 BI D+
35 USB3_BP_P0_TN_CMC 2 D5B 13 GND
BI
B USB3_BP_P0_TP_CMC 14 D6A GNDA 10
14
15
STDA_SSRX_N
B
35 BI USB3_BP_P1_RP STDA_SSRX_P
USB3_BP_P0_TP_CMC 1 D6B GNDB 5 24 35 OUT 16
35 BI GND_DRAIN
USB3_BP_P1_TN_CMC 17 STDA_SSTX_N MTH1 21
USB3_BP_P1_TP_CMC 18 STDA_SSTX_P MTH2 22
CONNECT As TO Bs CM7B3
24 USB3_BP_P1_TN 4 3 X865822-004
X863137-001 IN TH
DFN14
CHK
24
V_5P0DUAL IN USB3_BP_P1_TP 1 2
EG3F1 80 OHM
ESD ARRAY SM
SP3011 RT3F1 X869713-001
1 2 V_5P0_USB3_FP
24 35 BI USB3_FP_P0_RN 8 D1A 01.50 A THRMSTR 1 C3F1 2 C3F2 2 C3F3
USB3_FP_P0_RN 7 220 UF 470 PF 4.7 UF
24 35 BI D1B 1812 20% 5% 10%
10 V 50 V 6.3 V
24 35 USB3_FP_P0_RP 9 D2A 2 ELEC 1 X7R 1 X5R
BI USB3_FP_P0_RP 6 D2B
RDL 402 603
24 35 BI 35 24 BI USB2_FP_P0_DN J3F2 CONN
USB2_FP_P0_DP 11 35 24 BI USB2_FP_P0_DP USB3_9P_2MH
35 24 BI D3A 1
USB2_FP_P0_DP 4 D3B VBUS
35 24 BI 2
USB3_FP_P0_RN D-
24 35 OUT 3
USB2_FP_P0_DN 12 D4A D+
35 24 BI 4
USB2_FP_P0_DN 3 D4B GND
35 24 BI 5 STDA_SSRX_N
6
A 35 BI USB3_FP_P0_TN_CMC
USB3_FP_P0_TN_CMC
13
2
D5A
D5B
24 35 OUT USB3_FP_P0_RP 7
STDA_SSRX_P
GND_DRAIN
A
35 BI USB3_FP_P0_TN_CMC 8 10
STDA_SSTX_N MTH1
USB3_FP_P0_TP_CMC 9 STDA_SSTX_P MTH2 11
35 USB3_FP_P0_TP_CMC 14 D6A GNDA 10
BI USB3_FP_P0_TP_CMC 1 D6B GNDB 5 CM3F1
35 BI
24 USB3_FP_P0_TN 4 3 X866825-003
IN TH
CONNECT As TO Bs CHK
X863137-001 24 IN USB3_FP_P0_TP 1 2
DFN14 80 OHM
SM
X869713-001
PAGE
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
EG6B1
CONN, USB
ESD ARRAY
SP3011
D USB3_AUX_RN 8 D1A
V_3P3STBY D
24 36 BI
24 36 USB3_AUX_RN 7 D1B
BI R4B12
V_3P3STBY_BAJA 1 2
24 36 USB3_AUX_RP 9 D2A
BI USB3_AUX_RP 6 D2B 0 OHM 5%
24 36 BI 603 CH
1
USB2_AUX_DP 11 D3A
C4B10 C4B9
36 24 BI USB2_AUX_DP 4
402 402 1 UF
10%
22 UF
20%
2
36 24 BI D3B DIO DIO 6.3 V 6.3 V
2 X5R X7R
36 24 USB2_AUX_DN 12 D4A X882235-001 402 805
BI USB2_AUX_DN 3 D4B X882235-001
36 24 BI EG3B3 EG3B4 J3B1
USB3_AUX_TN_CMC 13
1
36 BI D5A WIFI_HDR
36 USB3_AUX_TN_CMC 2 D5B
BI 11 3P3V2
36 USB3_AUX_TP_CMC 14 D6A GNDA 10 1 3P3V1
BI USB3_AUX_TP_CMC 1 D6B GNDB 5 USB2_WIFI_DP 7
36 BI 24 BI NETW_DP
24 USB2_WIFI_DN 8 NETW_DN
BI USB2_ACC_DP 3
24 BI ACC_DP
24 USB2_ACC_DN 4 ACC_DN
CONNECT As TO Bs BI WIFI_RESET_N 9
26 IN RESETN
X863137-001
DFN14 6
C GND
SHLD2 10 C
V_5P0DUAL RT6B1 SHLD1 2
1 2 SHLD_ALL 5
1
EG3B1 EG3B2
01.50 A EMPTY X882235-001 X882235-001 1 R3B5 TH
1 1812 10 KOHM
C6B6 U6B2 IC DIO DIO 5%
1 UF TPS2065 2 EMPTY
10%
5 1
402 402 402
2
6.3 V IN OUT
2 X5R
402 3 1
OC_N V_5P0_USB3_AUX_FLT
DB6B3
26 USB_AUX_EN 4 EN GND 2
IN
1 R6B3
100 KOHM X862402-001
1 5% SOT23-5
FT4N3 FTP
2 CH
402
V_5P0_USB3_AUX
1 C6B5 2 C6B1 2 C6B4
220 UF 470 PF 4.7 UF
20% 5% 10%
B 10 V
ELEC
50 V
X7R
6.3 V
X5R B
2 RDL 1 402 1 603
I90
1
EG6B2 IC U6B1 V_12P0

X882235-001 J6A1 CONN TPS2590
DIO USB_13P_4MH
VIN4 4
402 1 5 V12P0_AUX 12 3
2
VBUS VCC VOUT3 VIN3

11 VOUT2 VIN2 2
63 IR_BLAST_SENSOR_SIG 8 IR_I/O 1 10 VOUT1 VIN1 1
IN 11
1
C6B3 C6B2
GND_DRAIN 1 UF
36 24 USB2_AUX_DP 2 D+ GND 6 4.7 UF 10% ILIM 7 USB_AUX_OCP_ILIM
BI USB2_AUX_DN 3 7
10% 16 V 15 R4N2 ON ILIM SETS
36 24 BI D- GND 16 V 2 X5R FLT_N
4 2 X5R 603 8 LIMIT CURRENT: 3.1 A
GND 805 IFLT USB_AUX_OCP_IFLT
12 STDA_SSRX_P
13 STDA_SSRX_N MTH4 17 CT 9 USB_AUX_OCP_CT R4N1 ON IFLT SETS
24 36 OUT USB3_AUX_RP 16 5
MTH3 GND1 FAULT CURRENT: 3.1 A
36 USB3_AUX_TP_CMC 9 STDA_SSTX_P MTH2 15 13 GND2 RTRY_N 6 USB_AUX_OCP_RTRY_N
36 USB3_AUX_TN_CMC 10 STDA_SSTX_N MTH1 14 14 GND3 EN_N 16 USB_AUX_OCP_EN_N
17 C4N1 ON CT SETS
USB3_AUX_RN MPAD
24 36 OUT V_SOC1P8 FAULT TIME: 22 MS
X862297-003 V_SOC1P8 QFN16 X866681-001
TH
CM6B2 R6B8 1 R6B1 R6B2 R6B9 1
C4N1 1 R4N1
24 USB3_AUX_TP 1 2
1 10 KOHM 1 1 64.9 KOHM 1 R4N2
IN 10 KOHM 5% 0 OHM 0 OHM .68 UF 1% 64.9 KOHM
5% 5% 5% 10% 1%
2 CH 6.3 V 2 CH
2 CH 402 2 CH 2 EMPTY 2 X5R 603 2 CH
402 402 402 402 402
A 24 IN USB3_AUX_TN 4 3
USB_AUX_OCP_FLT_N
USB_AUX_EN_D A
80 OHM 26 OUT 3
SM Q6B2
X869713-001 FET
26 USB_AUX_EN 1 AO3414L
IN
2 SOT23

PAGE
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
EG7B3
CONN, HDMI IN ESD ARRAY

SP3010
25 OUT TMDS_RX_DP2 1 D1A

10 D1B
D 25 OUT TMDS_RX_DN2
2 D2A
D
9 D2B
25 OUT TMDS_RX_DP1 4 D3A

7 D3B
25 OUT TMDS_RX_DN1
5 D4A GNDA 3
6 D4B GNDB 8
25 OUT TMDS_RX_DP0
CONNECT As TO Bs
25 OUT TMDS_RX_DN0 X863136-001
DFN10
25 OUT TMDS_RX_CLKP
25 OUT TMDS_RX_CLKN
C C
J7A1 CONN
HDMI
1 TMDS_DATA2_DP
2 TMDS_DATA2_SHD
3 TMDS_DATA2_DN
4 TMDS_DATA1_DP
10
5
2
9
4
7
5
6
TMDS_DATA1_SHD
V_3P3STBY 6 TMDS_DATA1_DN
EG7B4
ESD ARRAY
X863136-001
DFN10
7
D1A
D1B
D2A
D2B
D3A
D3B
D4A
D4B
TMDS_DATA0_DP
CONNECT As TO Bs
8 TMDS_DATA0_SHD
9 TMDS_DATA0_DN
1 R8B19 SP3010
10
10 KOHM TMDS_CLK_DP
1% 11 TMDS_CLK_SHD
2 CH 12 TMDS_CLK_DN
402 25 38 HDMI_RX_CEC 13 CEC
BI 14 RESERVED
15 SCL
GNDA
GNDB
16 SDA MT1 20
17 DDC_CEC_GND MT2 21
B 18
19
5VCC MT3 22
23 B
3
8
HOT_PLUG_DET MT4
26 HDMI_RX_DDC_5V_E
OUT
X864613-003 SM
2
1 R8B20
SOT-523
EMPTY
D8B3
0 OHM
1
5% EG7A9
2 CH X882235-001
402
HDMI_RX_DDC_5V_D
3
DIO
1 R8B21 3 402
2
2 KOHM U8B2
1% FET R8B9
2 EMPTY 1HDMI_RX_DDC_5V_G 1 2 HDMI_RX_DDC_5V
402 SOT23 2 10 KOHM 1%
603 CH
R8A3
1
1 R8A2 1
C8B1 EG7A7 HDMI_HPD_PIN 1 2 HDMI_RX_HPD IN 25
100 KOHM 0.1 UF X882235-001 1 KOHM 5%
1% 10% 402 CH
6.3 V DIO 1 R3M2
1
2 CH 2 EMPTY EG8A7
402 402 402 47 KOHM 1 R3M1 X882235-001
2
1% 47 KOHM
2 CH 1%
402 2 CH EMPTY
402 402
2
A A
26 BI HDMI_RX_DDC_CLK
26 BI HDMI_RX_DDC_DATA
1
EG7A4
1
EG7A3 X882235-001
X882235-001
DIO DIO
402 402
2
2

PAGE
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
C8B2
402
X5R
6.3 V
0.1 UF 10%
CONN, HDMI OUT
2 IN TMDS_TX_DP2 1 2
TMDS_TX_DP2_C
TMDS_TX_DN2 1 2 TMDS_TX_DN2_C ESD DIODE ARRAYS
2 IN EG8B1 ARE INCLUDED FOR
0.1 UF 10% ESD ARRAY EVALUATION. TO BE
D 6.3 V
X5R SP3010 CLEANED UP LATER. D
402 C8B4
C8B3 402
X5R 1 D1A
6.3 V 10 D1B
0.1 UF 10%
2 IN TMDS_TX_DP1 1 2 TMDS_TX_DP1_C 2 D2A
9 D2B
2 IN TMDS_TX_DN1 1 2
TMDS_TX_DN1_C
0.1 UF 10% 4 D3A
3
8
6.3 V 7 D3B
X5R
GNDA
GNDB
402 5 3
D4A GNDA
CONNECT As TO Bs
C8B5 6 8
D4B GNDB
X863136-001
SP3010
ESD ARRAY
CONNECT As TO Bs
X863136-001
EG8B2
DFN10
DFN10
D1A
D1B
D2A
D2B
D3A
D3B
D4A
D4B
C8B6
402
X5R
C 6.3 V
1
10
2
9
4
7
5
6
0.1 UF 10% J8A1 CONN C
2 TMDS_TX_DP0 TMDS_TX_DP0_C HDMI
IN 1 2 1 TMDS_DATA2_DP
2 IN TMDS_TX_DN0 1 2 TMDS_TX_DN0_C 2 TMDS_DATA2_SHD
3 TMDS_DATA2_DN
0.1 UF 10% 4
6.3 V TMDS_DATA1_DP
X5R C8B8 5 TMDS_DATA1_SHD
402 6 TMDS_DATA1_DN
402
C8B7 X5R 7 TMDS_DATA0_DP
6.3 V 8 TMDS_DATA0_SHD
0.1 UF 10% 9 TMDS_DATA0_DN
2 IN TMDS_TX_CLKP 1 2 TMDS_TX_CLKP_C 10 TMDS_CLK_DP
11 TMDS_CLK_SHD
2 IN TMDS_TX_CLKN 1 2
TMDS_TX_CLKN_C 12 TMDS_CLK_DN
25 37 HDMI_RX_CEC 1 2 HDMI_TX_CEC 13 CEC
0.1 UF 10% BI 14
6.3 V 0 OHM 5% RESERVED
X5R 402 CH 15 SCL
402 R8A1 16 SDA MT1 20
C8B9 R1N2 17 DDC_CEC_GND MT2 21
499 OHM
1 R8B1 1 R8B3 1 R8B5 1 R8B7 38 V_5P0_HDMI_OUT 1 2 HDMI_OUT_DDC_BUFF_EN 38 V_5P0_HDMI_OUT 18 5VCC MT3 22
499 OHM
499 OHM
499 OHM
IN IN 19 23
1% 1% 1% 1% 10 KOHM 5% HOT_PLUG_DET MT4
402 EMPTY
B 2 CH 2 CH 2 CH 2 CH X864613-003 SM
V_5P0DUAL 402 402 402 402 B
1
IC U1N1 EG9A2 EG8A8
1 R8B2 1 R8B4 1 R8B6 1 R8B8 1 PCA9507 X882235-001 X882235-001
499 OHM
499 OHM
499 OHM
499 OHM
C1N1
HDMI_TX_HPD_PIN
0.1 UF 8 VCCB VCCA 1 1
R2N3 1 1% 1% 1% 1% 1 R1N4 10% 1 R1M4 C9B3 DIO DIO
2 CH 2 CH 2 CH 2 CH 0.1 UF
47.5 KOHM 2 KOHM 2
25 V
X5R 7 SCLB SCLA 2 2 KOHM 10% 402 402
1% 402 402 402 402
2
1% 6 3 1% 25 V V_3P3STBY
402 SDAB SDAA 2 X5R
EMPTY 2 2 CH 2 CH 402
402 402
4 5
402
GND EN 2 3 DP0_HPD
OUT 2 26
1
1 R1N3 1 R1M3 1 R9B1 U9B2
1
FT2N1 FTP 2 KOHM X871021-001 2 KOHM EG9A1 FET
TO SB GPIO
TMDS_COMMON_FET 1% MSOP8 1% X882235-001
10 KOHM
1% 1
3 2 CH 2 CH
U2N1 C8B19 402 402 2 CH SOT23
FET R9B4 DIO 402 X857156-001
HDMI_DP_OUT_SEL
HDMI_TX_HPD_D
27 1 0.1 UF
IN 10% 26 IN HDMI_TX_DDC_CLK 1 2 R9A7 402
2 SOT23
2
1 R2N2 X801032-001 25 V HDMI_OUT_DDC_BUFF_CLK 1 2
EMPTY 0 OHM 5%
PLACEHOLDER, ACTUAL 47.5 KOHM 402 402 CH 22 OHM 5%
1% R9B5 402 CH
FET REQURIEMENTS 2 CH 26 HDMI_TX_DDC_DATA 1 2 R9A8
402 BI 1
HDMI_OUT_DDC_BUFF_DATA2
3
U9B1
NEED TO BE ASSESSED. 0 OHM 5%
402 CH 22 OHM 5%
R9B16 FET
1 2 HDMI_TX_HPD_G 1
C9B13 402 CH
HDMI_OUT_DDC_CLK 1 2 HDMI_OUT_DDC_CLK_R 10 KOHM 1% 2 SOT23
2 IN 402 CH
V_3P3
1 R1N1 1
1
0.1 UF 10% 1 R9A5 EG9B1 C9B1
V_5P0DUAL RT8A1 6.3 V 100 KOHM
100 KOHM
0.1 UF
1 2 EMPTY 1 R9A6 5%
X882235-001 1% 10%
402 2 CH 6.3 V
100 KOHM 2 EMPTY 2
5% DIO 402 EMPTY
A HDMI_OUT_DDC_DATA 1
01.10 A EMPTY
1206 2 EMPTY
402
402 402 A
2
2 BI C2N1 U8B1 IC C9B15 402
1 UF TPS2051C 1 2 HDMI_OUT_DDC_DATA_R
10%
6.3 V 5 IN OUT 1
2 X5R 0.1 UF 10%
AUX VS DDX STUFFING 402 6.3 V
FLT* 3 V_5P0_HDMI_FLT_N EMPTY
402 38
HDMI_V_5P0_EN 4 2 V_5P0_HDMI_OUT
OUT
26 IN EN GND
MODE R9B8/R9B9 R9A5/R9A6 R9A3/R9A4
R2N4 1 1
1 X867973-001 C8A2 C8A3
AUX 0.1 UF CAP STUFF EMPTY 1 10 KOHM SOT23-5 4.7 UF 0.1 UF
FT2N2 FTP 5% 1
10% 10%
DDC 0 OHM RES EMPTY STUFF 2 CH DB8B1 2
16 V
X5R 2 6.3
X5R
V
PROJECT NAME PAGE CSA FAB REV
402 805 MICROSOFT
402 PAGE
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
CONN, ODD + HDD

25 SATA1_HDD_TP 1 C5C6 2
IN
0.01 UF 10%
16 V V_3P3STBY
X7R
402
D SATA1_HDD_TP_C
D
SATA1_HDD_TN_C J4B2 1 R5C8
1X5HDR2
HDD SATA 39 IN V_5P0_HDD 1
0 OHM
5%
2
1 C5C7 2
2 CH
25 IN SATA1_HDD_TN J5C1 3 402
1X7SATA 4
0.01 UF 10% 9 2 C5C13 1
16 V C5P4
ODD_3P3V_STBY_S
X7R 4.7 UF 2 R5C7
10% 1 UF 10 KOHM
402 1 6.3 V 10% TH 5%
2 X5R 6.3 V
1 603 2 X5R 1 CH
3 402 402
4
5
6
25 SATA1_HDD_RN 1 C5C8 2 7
OUT ODD_3P3V_STBY_EN 1 2 U5C2
26 IN
0.01 UF 10% 8 FET
16 V V_5P0
X7R
402 TH 3
SOT23
SATA1_HDD_RN_C V_12P0 X857156-001
C SATA1_HDD_RP_C
1
C4C4 ODD_3P3V_STBY_PULSE
OUT 39
C
U4C2 IC 1 UF
10%
6.3 V
1 C5C9 2 1 NCP45521 2 X5R
25 OUT SATA1_HDD_RP C4C3 VCC 3 402
1 UF
0.01 UF 10% 10%
16 V 16 V
X7R 2 X7R
402 603 1 VIN1 VOUT1 7 V_12P0_ODD 39
9 8
OUT
VIN2 VOUT2
BLEED 5
1
C4C9 1 C6P4 1 C6P5 1
C4C10
SR 6 ODD_PWR_SR 10 UF 10 UF 10 UF 10 UF
10% 10% 10% 10%
16 V 16 V 16 V 16 V
2 2 2 2
ODD SATA 26 IN ODD_PWR_EN 2 EN GND 4
1
X5R
805
X5R
805
EMPTY
805
EMPTY
805
X866665-001 C4C7 V_5P0
25 SATA0_ODD_TP 1C4C172 SATA0_ODD_TP_C 1 R6P3 DFN8 0.015 UF
10%
IN 10 KOHM 50 V
2 X7R
0.01 UF 10% 5%
603
16 V 2 EMPTY
X7R 402 1 C5C1
402 220 UF
J4C1 20%
B SATA0_ODD_TN 1C4C182 SATA0_ODD_TN_C 1X7SATA U5C4 IC 10 V
B
2 ELEC
25 IN 9 MP5010B RDL
0.01 UF 10% HDD_PWR_DVDT VCC 11
16 V
X7R 1
1 1 V_5P0_HDD
402 2 C5C25 SOURCE1 OUT 39
270 PF SOURCE2 2
3
4
10% SOURCE3 3 1 R5C6 1
C5C12
1C4C192
50 V 4 22 OHM
25 OUT SATA0_ODD_RN SATA0_ODD_RN_C 5 2 X7R
402
SOURCE4
SOURCE5 5 5% 10 UF
20%
6 2 CH 6.3 V
0.01 UF 10% 7 402 2 X5R
16 V 9 DV/DT ILIMIT 7 HDD_PWR_ILIMIT 805
X7R R5C5 6
402 8 NC
26 HDD_PWR_EN 1 2 HDD_PWR_EN_R 8 EN/FLT GND 10
IN
TH 1 1 R5C2 1 KOHM 1%
25 SATA0_ODD_RP 1C4C202 SATA0_ODD_RP_C
FT5P1 FTP 10 KOHM 402 CH X878106-001
OUT 5% DFN11
0.01 UF 10% 2 CH
16 V 402 V_5P0
V_3P3STBY X7R
402
1
1 R5C14 C5C2
100 KOHM R5C13 1 UF
5% ODD_STATUS_R 1 2 ODD_STATUS
U5C1 IC 10%
OUT 26 6.3 V
2 CH
100 OHM 1%
MP5010B 2 X5R
402 ODD_PWR_DVDT VCC 11 402
402 CH 1 R5C12
100 KOHM
26 5% 1 SOURCE1 1 V_5P0_ODD 39
OUT C5C16 OUT
A 2 CH
402
270 PF
10%
SOURCE2 2
3 1 R5C4 1
A
J5C3 SOURCE3 C5C11
50 V 4 22 OHM
2X6HDR2 2 X7R SOURCE4 5% 10 UF
402 SOURCE5 5 20%
ODD_WAKE_N 1 2 CH 6.3 V
ODD_OPEN 3 4 402 2 X5R
26 IN 9 7 ODD_PWR_ILIMIT 805
5 6 ODD_3P3V_STBY_PULSE DV/DT ILIMIT
IN 39 6
7 8 V_5P0_ODD 39
R5C1 NC
1 9 10 V_12P0_ODD
IN 26 IN ODD_PWR_EN 1 2 ODD_PWR_EN_R 8 EN/FLT GND 10
C5C17 IN 39
11 12 1 1 R5C3 1 KOHM 1%
75 PF 1 1 FT5P2 FTP 402 CH X878106-001
5% C5C3 1 2 C5C14 1 C5P3 C5C24 10 KOHM
2
50 V
TH 4.7 UF C4C11 4.7 UF 1 UF 5% DFN11
NPO 10% 1 UF 10% 1 UF 10% 2 CH
402 16 V 10% 6.3 V 10% 6.3 V
2 X5R 16 V X5R 6.3 V 2 X5R 402
805 2 X5R 1 603 2 X5R 402 MICROSOFT PROJECT NAME PAGE CSA FAB REV
603 402 PAGE
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
CONN, LITHIUM + FAN
D D
V_3P3STBY
J5F1 CONN
LITHIUM CONN
12 V_3P3STBY
C5F10 1 R5F22 1 R5F23 1 R5F25 1 R5F21 1 R5F20
1 100 UF 100 KOHM 100 KOHM 100 KOHM 100 KOHM 249 KOHM
C5F15 20% 5% 5% 5% 5% 1%
470 PF 16 V 2 CH 2 CH 2 CH 2 CH 2 CH
5% ELEC
50 V RDL 402 402 402 402 402
2 NPO SMBUS_CLK 5
402 65 44 26 IN I2C_CLK
66 65 64 54 53 52 50 44 26 SMBUS_DATA 6 I2C_DATA
V_5P0DUAL BI
C R5F19 4 V5P0_DUAL C
26 BINDSW_N 1 2 BINDSW_N_R 13 BINDSW_N
1
OUT
C5F12 C5F11 IR_DATA
0 OHM 5%
7
470 PF 100 UF 26 OUT 402 CH IR_DATA
5% 20%
50 V 16 V LED_NEXUS_R 1
2 NPO ELEC 26 IN LED_NEXUS
402 RDL
R5F26
26 67 PWRSW_N 1 2 PWRSW_N_R 8 PWRSW_N
OUT
10 KOHM 1%
402 CH
R5F24
26 67 EJECTSW_N 1 2 EJECTSW_N_R 10 EJECTSW_N
OUT
10 KOHM 1%
402 CH 2 LED_HALO
3 LED_ZONE
9 GND1
B INT_N
14
11
GND2
17 B
26 OUT INT_N SPARE3
18 MTH1 SPARE2 16
19 MTH2 SPARE1 15
1 R5F32
100 KOHM
5% X866836-003 TH
2 CH
402
V_12P0 V_3P3
1 R7B2
4.7 KOHM
5%
2 CH
1 C7C1 402
C7B14 100 UF
1 UF
10% 20%
16 V 16 V
2 X5R ELEC FAN_TACH_IN_R R7B3 FAN_TACH_IN A
A 603 RDL 1 2
OUT 27
0 OHM 5%
J7C1 402 CH
1X4HDR
1
1
2 C7B13
R5R11 3 4700 PF
10%
26 FAN_PWM 1 2 FAN_PWM_R 4 16 V
IN 2 EMPTY
33 OHMS 1% 603
402 CH TH

PAGE
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D CONN, PWR D
C C
V_12P0 J9A1 CONN

12P_PWR_RCPT
1 GND
2 GND
3 GND
1 C9B6 1 C1N4 1 C1N3 1 C1N5 1 C1N2 4 GND
1 C9B11 470 UF 0.1 UF 0.1 UF 0.1 UF 0.1 UF
470 UF 20% 10% 10% 10% 10% 5 +12V MAIN
20% 16 V 25 V 25 V 25 V 25 V 6 +12V MAIN
16 V POLY X7R X7R X7R X7R 7
2 POLY 2 TH 2 603 2 603 2 603 2 603 +12V MAIN
TH 8 +12V MAIN
9 POWER ENABLE
1 10 +5V STANDBY
R9A2 DB9A1
26 IN PSU_V12P0_EN 1 2 PSU_V12P0_EN_R
11 MH1
100 OHM 1% 1 1 12 MH2
1 R9B2 402 CH C9A2 C9A1
10 KOHM 0.1 UF 470 PF
5% 10% 5% X863226-003
V_5P0STBY 2 CH 2
6.3 V 2 50 V TH
X5R EMPTY
B 402 402 402 B
1 C9B5 1
220 UF C9B2
20% 470 PF
10 V 5%
2 ELEC 2
50 V
RDL X7R
402
A A

DRAWING PAGE
CONFIDENTIAL
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
VREGS, BLEEDERS
D D
V_5P0STBY V_12P0
C V_5P0DUAL C
1 R2N9 1 R2N7 1
DB4B1
2.2 KOHM 2.2 KOHM V_12P0
5% 5%
2 CH 2 CH 1 R4B6 1 R4B3 1 R4B4 1 R4B2 1 R4B5
402 402 10 KOHM 20 OHM 20 OHM 20 OHM 20 OHM
R2N8 3 5% 5% 5% 5% 5%
1 2 BLEEDER_V12P0_B2 1 U8B3 2 CH 2 CH 2 CH 2 CH 2 CH
BLEEDER_V12P0_C2
BLEEDER_V12P0_C1
549 OHM 1% XSTR 402 1206 1206 1206 1206
402 CH 24
BLEEDER_C2
BLEEDER_V12P0_LOAD
BLEEDER_C1
1 R2N11 1 R2N12 1 R2N13 1 R2N10
10 OHMS 10 OHMS 10 OHMS 10 OHMS
1% 1% 1% 1%
3 2 CH 2 CH 2 CH 2 CH
1
U2N3 1206 1206 1206 1206
DB8C2 FET 3
1 U4B1
1
2 SOT23
3 XSTR
B R8C2
26 IN PSU_V12P0_EN 1 2 BLEEDER_V12P0_B1 1 U2N4
SMC_RST_N
R4B1
1 2 BLEEDER_B 1
3
U4B2
2
B
2.2 KOHM 5% XSTR 65 29 IN
402 CH 2 10 KOHM 5% XSTR
402 CH 2
R8C1
29 V12P0_PWRGD 1 2
IN
2.2 KOHM 5%
402 CH
1
DB8C1
V_5P0DUAL BLEEDER
V_12P0 BLEEDER
A A

PAGE
[PAGE_TITLE=VREGS, INPUT + OUTPUT FILTERS] DRAWING
CONFIDENTIAL
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
VREGS, INPUT + OUTPUT FILTERS

D D
IO/NBCORE/MEMCORE INPUT FILTER

V_12P0 V_12P0
L9B1
GFX/CPU INPUT FILTER
L9B2 1 2 V_VREG_12P0_GFXCPU OUT 44 46 47 48
1 2 V_VREG_12P0_MEM_NBCORE OUT 50 51 52 53 0.68 UH IND
0.68 UH IND 15.5 A SM
15.5 A SM 1 0.005 OHM 1 C9B12 1 C9B8 1 C9B4 1 1
0.005 OHM 1 C9B7 1 C9B14 C8B11 470 UF 470 UF 470 UF C9B9 C9B10
470 UF 10 UF
10 UF 20% 20% 20% 10 UF 10 UF
20% 10%
10% 16 V 16 V 16 V 10% 10%
16 V 16 V 2
16 V 2 POLY 2 POLY 2 POLY 2
16 V 2
16 V
2 X5R TH TH TH X5R X5R
C 2 POLY
TH
X5R
805
805 805 805 C
V_GFXCORE
V_GFXCORE OUTPUT FILTER V_CPUCORE
V_CPUCORE OUTPUT FILTER
1 1
FTP FT2R1 FTP FT1T1
1 C8E1 1 C8D4 1 C8D2 1 C8D1 1 C8E5

1 C8E8
1 C8E10
820 UF 820 UF 820 UF 820 UF 820 UF 820 UF 820 UF
B 20%
2.5 V
20%
2.5 V
20%
2.5 V
20%
2.5 V
20%
2.5 V 20%
2.5 V
20%
2.5 V B
2 POLY 2 POLY 2 POLY 2 POLY 2 POLY POLY 2 POLY
RDL RDL RDL RDL RDL 2 RDL RDL
5P0/3P3 INPUT FILTER

V_12P0
L8B1
1 2 V_VREG_12P0_TO_5P0_3P3
OUT 30 54 56
0.68 UH IND 1 C8B18
15.5 A SM 470 UF 1 C8B17
0.005 OHM 20%
16 V 4.7 UF
10%
A 2 POLY
TH 2 16 V
X5R
A
1206

PAGE
[PAGE_TITLE=VREGS, INPUT + OUTPUT FILTERS] DRAWING
CONFIDENTIAL
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
V_5P0
VREGS, CPUCORE 8 SOC_CPUCORE_S
IN
D D
1
R1P8 C1P7
1 UF
VREG_CPUGFX_PWRGD OUT 45 26 69
43 IN V_VREG_12P0_GFXCPU 1 2 10% 1
V_SOC1P8 1 KOHM 1% 16 V FTP FT1P5
402 CH 1 1 R1P9 2 X5R
C9C8 0 OHM 603
1 UF
10% 5% U9C2 IC
2
16 V 2 EMPTY NCP4204
X5R 402
1
2
603 11 7
C9C9 VCC VDD_PWRGD
ST1T1
SHORT
2.2 UF R2R1
10%
6.3 V VREG_GFXCPU_RAMP 12 VRMP 1 2
2 X5R 0 OHM 5%
1
603 4 VDDIO 805 EMPTY
VDD 15 VREG_CPUCORE_S VENABLE
DIFF 17 VREG_CPUCORE_DIFFOUT OUT 44
26 IN SOC_PWR_OK 52 PWROK VSS 14 VREG_GFXCPU_S_RTN
FT1P7 FTP
1
IN VREG_CPUCORE_EN 9 EN CSP1 25 VREG_CPUCORE_CSP IN 48
2
ST2R1
SHORT
1 5 SCL
FT1P4 FTP
6 SDA
1 R1P10
C 10 KOHM SVD_R_CPUCORE 1
1
5% SVC_R 3
SVD
SVC DB2P1
1 C
2 CH SVT_R 2 SVT
402
1 1 1
DB9C3 DB9C7 DB9C8 8 SOC_GFXCPU_S_RTN
VREG_CPUCORE_FB 16 FB IN
VREG_CPUCORE_COMP 19 COMP
R9C1 VREG_CPUCORE_TRBST 18 TRBST
52 50 40 65 26 OUT SMBUS_CLK 1 2 SMBUS_CLK_CPUCORE
66 64 54 53 0 OHM 5%
402 CH
R9C54 V_SOC1P8
48 IN VREG_CPUCORE_CSN1 2 VREG_CPUCORE_CSN_R 26 CSN1
10 OHM 1% VREG_CPUCORE_DROOP 21 DROOP
66 65 64 R9C2 402 CH VREG_CPUCORE_ILIM 20 ILIM
50 40 26 BI SMBUS_DATA 1 2 SMBUS_DATA_CPUCORE
R1P19 1 C9C20 1 R9C40
54 53 52 36.5 OHM1% 2.8 KOHM 2200 PF 28.7 KOHM
402 CH 1% 10%
50 V
1%
CH 2 X7R 2 CH 1 R9C17
R9C39 402 402 402 10 KOHM
1 2 VREG_CPUCORE_CSCOMP 22 CSCOMP 5%
73.2 KOHM1% 24 CSSUM 2 CH
BI 402 CH 402
VREG_CPUCORE_CSCOMP_R
B IN
RT9E1
1 2
PWM1/SR 27 VREG_CPUCORE_PWM OUT 48 B
1 603 1
THRMSTR
FT1P1 FTP C9C18 C1P9 1
X863133-001 1500 PF 1500 PF DB1P2
R2R2 R9C4 10% 10%
SVD 1 2 SVD_R 1 2
R9C43 1 50 V 50 V
8 BI 165 KOHM X7R 2 X7R
18.2 OHM1% 10 OHM 1% 1% 402 402 OCP_L 13 VREG_OCP_L
402 CH FT1P3 FTP
1
402 CH 32 VREG_GFXCPU_DRV_EN
OUT
CH 2 DRON OUT 46 47 48
R2R3 402 IOUT 23 VREG_CPUCORE_IOUT
SVC 1 2 48 IN VREG_CPUCORE_CSSUM
8 IN
1 18.2 OHM 1% R9C55 1
FT1P2 FTP 402 CH 53 AGND 10 KOHM
R9C45 1%
R9C21 28.7 KOHM CH 2
8 OUT SVT 1 2 X861898-002 QFN53 1% 402
18.2 OHM1% CH
1
DB9C1 402 CH 402
VREG_CPUCORE_DIFFOUT IN 44 TO INCREASE CURRENT LIMIT FREQUENCY = 400KHZ, CHANGED OVER I2C
INCREASE ILIM RES ON PIN 20 SEE DATASHEET FOR REGISTER TABLE SLEW RATE SET BY SR RES
R9C32 1
C9C12
2
RES OF 30KOHM EFFECTIVELY ON PIN 27
VREG_CPUCORE_FB REMOVES CURRENT LIMIT NCP4204 I2C ADDRESS
150 OHMS1%VREG_CPUCORE_FB_C
1500 PF 10%
0000 000 R/W HEX SLEW RATE RESISTANCE
402 CH 50 V WRITE 0100 000 0 0X40
X7R
C9C16 READ 0100 000 1 0X41 10MV/US 10 KOHM
68 PF
402 5%
R9C23 R9C36 50 V 20MV/US 25 KOHM
C9C11 NPO
1 2 1 2 VREG_CPUCORE_COMP_R 402 30MV/US 45 KOHM
1 KOHM 1% 5.9 KOHM 1%
A 402 CH 1500 PF 10%
50 V 402 CH A
X7R
402
C9C15
1
R9C35
2VREG_VDD_TRBST_C1 2 SVC SVD BOOT VOLTAGE
470 PF 5% 0 OHM 5% 0 0 1.1V
50 V 402 EMPTY
R9C29 EMPTY R9C38 0 1 1.0V
1 2 VREG_CPUCORE_TRBST_R 402 1 2
1 0 0.9V
43.2 KOHM1% 1 10 KOHM 1%
402 CH C9C13 402 CH 1 1 0.8V
470 PF
5%
50 V
2 X7R
402
PAGE
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
VREGS, GFXCORE 8 IN SOC_GFXCORE_S
D D
VREG_CPUGFX_PWRGD OUT 44 26 69
2
1
ST2R2
SHORT
U9C2 IC DB1P3
NCP4204
R2P5
1 2
1
IN VREG_GFXCORE_EN 10 EN_NB VDDNB_PWRGD 8 0 OHM 5%
805 EMPTY
FT1P6 FTP
1 VDDNB 51 VREG_GFXCORE_S
DIFFNB 50 VREG_GFXCORE_DIFFOUT OUT 45 VENABLE
1 R9C18
10 KOHM
1 5%
DB9C2 2 CH
402
VREG_GFXCORE_DIFFOUT DB9C4
1 CSP1NB 33 VREG_GFXCORE_CSP1 IN 46
IN 45 37 VREG_GFXCORE_CSP2
CSP2NB IN 46
DB9C6
C R9C24
1 2 1
C1P3
2 VREG_GFXCORE_FB
DB9C5
VREG_GFXCORE_FB 48 C
FBNB
VREG_GFXCORE_FB_C
49.9 OHM 1% VREG_GFXCORE_COMP 47 COMPNB
402 CH 2200 PF 10% VREG_GFXCORE_TRBST 49
50 V TRBSTNB
X7R C1P8
402 100 PF R1P20
5%
50 V CSN1NB 34 1 2 VREG_GFXCORE_CSREF OUT 45
R9C26 C9C14 R9C37 NPO 10 OHM 1% R1P24
1 2 1 2 VREG_GFXCORE_COMP_R 1 2 402 38 CH 1 2 1
CSN2NB 402
C1P15
1 KOHM 1% 1000 PF 10% 7.32 KOHM
1% R1P21 10 OHM 1% 0.01 UF
402 CH 50 V 402 CH CSN3NB 36 1 2 402 CH 10%
16 V
X7R
402 1
C1P6
2 VREG_GFXCORE_TRBST_C
R9C33 10 OHM 1% R1P25 2 X7R
1 2 CSN4NB 39 402 CH 1 2 402
470 PF 5% 200 OHM 1% 10 OHM 1%
50 V 402 EMPTY 402 CH
R9C28 EMPTY R9C30 VREG_GFXCORE_CSREF 41 CSREFNB VREG_GFXCORE_CSN1 IN 46
1 2 VREG_GFXCORE_TRBST_R 402 1 2 VREG_GFXCORE_DROOP 45 DROOPNB VREG_GFXCORE_CSN2 46
VREG_GFXCORE_ILIM 46 VREG_GFXCORE_CSN3 IN
43.2 KOHM
1% 10 KOHM 1% ILMNB IN 47
402 CH 402 CH R1P17 VREG_GFXCORE_CSN4 IN 47
1 C1P4 44.2 KOHM
1%
470 PF CH
5%
50 V 45 402
2 IN 44
B R1P18
X7R
402 43
CSCOMPNB
CSSUMNB B
1 2 PWM1NB/SRNB 31 VREG_GFXCORE_PWM1 OUT 46
73.2 KOHM1% 1 R9C41 PWM2NB/ICCMAX 29 VREG_GFXCORE_PWM2 OUT 46
402 CH 2.1 KOHM PWM3NB/ICCMAXNB 30 VREG_GFXCORE_PWM3 OUT 47
TO INCREASE CURRENT LIMIT
VREG_GFXCORE_CSCOMP_R
1% PWM4NB 28 VREG_GFXCORE_PWM4 OUT 47

INCREASE ILIM RES ON PIN 20
2 CH
402 RES OF 30KOHM EFFECTIVELY R1R6 1
REMOVES CURRENT LIMIT 10 KOHM
RT9D1
1 2 VREG_GFXCORE_CSCOMP C9C17 1%
2200 PF CH 2
10% IOUTNB 42 VREG_GFXCORE_IOUT
50 V 402
603
C1P10 1 C9C19 X7R
THRMSTR
2200 PF 1500 PF 402
R9C44 1 X863133-001 10% 10% R9C48 R1R9 1
165 KOHM 50 V 50 V 23.7 KOHM 30.1 KOHM
1% X7R 2 X7R X861898-002 QFN53 1% 1%
402 402
CH 2 CH CH 2
402 402 402
47 46 IN VREG_GFXCORE_CSSUM
R1R12 1
130 KOHM
1%
CH 2
402
R1T3 1
10 KOHM
1%
PWM4NB RES ON PIN 28
CH 2
402 SETS I2C ADDRESS
A SEE DATASHEET FOR ADDRESS TABLE A
SLEW RATE SET BY SRNB RES
ON PIN 31
SLEW RATE RESISTANCE
10MV/US 10 KOHM
20MV/US 25 KOHM
30MV/US 45 KOHM

PAGE
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

43 IN V_VREG_12P0_GFXCPU
V_5P0
5
D 1
C9D2
1
C9D3
1 C1R1 1 C1R2 D
10 UF 10 UF 10 UF 10 UF
Q9D1 10% 10% 10% 10%
1 R1R4 NTTFS4928N 2
16 V 2
16 V 2 16 V 2 16 V
2.2 OHM X5R X5R EMPTY EMPTY
1% R9D5 C9D5 X862002-001 805 805 805 805 V_GFXCORE
VREG_GFXCORE_BST1 1 2 VREG_GFXCORE_BST1_R 1 2 4 DFN5
2 EMPTY FET V_GFXCORE NOM.VOLTAGE: 0.9-1.1V
402 U9D2 IC 2.2 OHM1% 0.1 UF 10%
R9D4 805 CH 25 V
1 2 X7R
1
2
3
VREG_GFXCORE1_VCC NCP5901B 603
2.2 OHM 1% 4 VCC BST 1
402 CH 2 PWM DRVH 8 VREG_GFXCORE_DRVH1 L9D1
1 C9D4 3 EN SW 7 VREG_GFXCORE_SW1 1 2
6 5
1
1 UF GND DRVL 230 NH IND
ST9D1
SHORT
10% 9 MPAD 1 R9D2 61 A SM
16 V 1 OHM
5
2 X7R 1% 0.00029 OHM
2
805 X863210-001
ST9D2
SHORT
DFN9 2 CH VREG_GFXCORE_CSN1
2
805 OUT 45
Q9D2
VREG_GFXCORE_SW1_R
45 IN VREG_GFXCORE_PWM1 NTMFS4985NF 1 R1P26 1 C9C24
1
R1R5 VREG_GFXCORE_DRVL1 X866717-001 1 KOHM 0.15 UF
44 IN VREG_GFXCPU_DRV_EN 1 2VREG_GFXCORE_PH1_EN 4 DFN5 5% 10%
2 16 V
VREG_GFXCORE_SW1_S
49.9 OHM 1% FET 2 EMPTY X7R
402 CH R9C59 402 603
C 1 2 VREG_GFXCORE_CSP1
1
2
3
1 C9D1 5.9 KOHM 1%
OUT 45
C
1000 PF 603 CH
10%
50 V
2 X7R R1P29
603 VREG_GFXCORE_CSSUM OUT 46 47 45
20 KOHM 1%
402 CH
V_5P0
1 R1R7
B 2.2 OHM
1% B
2 EMPTY
402
R9D7
1 2
5
VREG_GFXCORE2_VCC
2.2 OHM 1% 1
C9D8
1
C9D7
1 C1R3 1 C1R4
402 CH 10 UF 10 UF 10 UF 10 UF
1 C9D9 Q9D3 10% 10% 10% 10%
NTTFS4928N 2
16 V 2
16 V 2 16 V 2 16 V
1 UF R9D8 X5R X5R EMPTY EMPTY
10%
16 V C9D10 X862002-001 805 805 805 805
2 VREG_GFXCORE_BST2 1 2 VREG_GFXCORE_BST2_R 1 2 4 DFN5
X7R V_GFXCORE
805 2.2 OHM1% 0.1 UF 10% FET
U9D3 IC 805 CH 25 V
X7R
1
2
3
NCP5901B 603
4 VCC BST 1
45 VREG_GFXCORE_PWM2 R1R8 2 PWM DRVH 8 VREG_GFXCORE_DRVH2 L9D2
IN 1 2 VREG_GFXCORE_PH2_EN 3 7 VREG_GFXCORE_SW2 1 2
EN SW
6 5
1
49.9 OHM1% GND DRVL 230 NH IND
ST9D3
SHORT
402 CH 9 MPAD 61 A SM
1 R9D6
5
1 OHM 0.00029 OHM
X863210-001 1%
DFN9 VREG_GFXCORE_CSN2
2
1
2 CH OUT 45
805
ST9D4
SHORT
Q9D4
NTMFS4985NF
VREG_GFXCORE_SW2_R
X866717-001 1 R1P28 1 C9C26
4
2
VREG_GFXCORE_DRVL2 DFN5 1 KOHM
0.15 UF
FET 5% 10%
A MS_PART# MATL REF_DES TRUEDESCR. BOM PROPERTY
2 EMPTY
402 2 16 V
X7R
A
1
2
3
Q9D1,Q9D3 X875319-001 FET TRA-N-CNL,SM,WDFN8,8.9 MOHM,30 V,24 A FET_CPUGFX_IRF
TRUE 603
I69
Q9D1,Q9D3 X875313-001 FET TRA-N-CNL,SM,WDFN8,10 MOHM,30 V,27 A FET_CPUGFX_TOS

TRUE
R9C57
I70
Q9D1,Q9D3 X876425-001 FET FET_CPUGFX_STM VREG_GFXCORE_SW2_S 1 2 VREG_GFXCORE_CSP2 OUT 45

I71
TRA-N-CNL,SM,WDFN8,9 MOHM,30 V,12 A
TRUE 1 C9D6
ZZ400
I75
Q9D1,Q9D3 X875316-001 FET TRA-N-CNL,SM,WDFN8,8.8 MOHM,30 V,24 A FET_CPUGFX_AOS
TRUE 5.9 KOHM 1%
Q9D2,Q9D4 X875320-001 FET TRA-N-CNL,SM,SO-8FL,3.1 MOHM,30 V,50 A FET_CPUGFX_IRF
TRUE 1000 PF 603 CH
I72
Q9D2,Q9D4 X875312-001 FET FET_CPUGFX_TOS 10%

TRUE
2 50 V
TRA-N-CNL,SM,SO-8FL,3.5 MOHM,30 V,35 A
I73
Q9D2,Q9D4 X878211-001 FET TRA-N-CNL,SM,SO-8FL,4.5 MOHM,30 V,24 A FET_CPUGFX_STM

TRUE X7R R9C58
I74
Q9D2,Q9D4 X875317-001 FET TRA-N-CNL,SM,SO-8FL,3.6 MOHM,30 V,32 A FET_CPUGFX_AOS 603 VREG_GFXCORE_CSSUM OUT 46 47
ZZ401
I76
20 KOHM 1% 45
402 CH

DRAWING PAGE
CONFIDENTIAL
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

5
V_5P0
D 1 1 1 C1R5 1 C1R6
D
C9D13 C9D12
Q9D5 10 UF 10 UF 10 UF 10 UF V_GFXCORE
1 R1R10 NTTFS4928N 10% 10% 10% 10%
X862002-001 2
16 V 2
16 V 2 16 V 2 16 V NOM.VOLTAGE: 0.9-1.1V
2.2 OHM X5R X5R EMPTY EMPTY
1% R9D11 C9D15 4 DFN5 805 805 805 805
2 EMPTY VREG_GFXCORE_BST3 1 2 VREG_GFXCORE_BST3_R1 2 FET V_GFXCORE
402 2.2 OHM1%
U9D4 IC 805 CH 0.1 UF 10%
1
2
3
25 V
R9D10 NCP5901B X7R
1 2 VREG_GFXCORE3_VCC 4 VCC BST 1 603
2.2 OHM 1% 2 PWM DRVH 8 VREG_GFXCORE_DRVH3 L9D3
402 CH 3 EN SW 7 VREG_GFXCORE_SW3 1 2
1 C9D14 6 GND DRVL 5
230 NH IND
1 UF 9 MPAD 61 A SM
1 R9D9
10%
5
1 OHM 0.00029 OHM
1
2 16 V X863210-001 1%
X7R
ST9D5
SHORT
DFN9
2
805 2 CH
ST9D6
SHORT
Q9D6 805
NTMFS4985NF
VREG_GFXCORE_SW3_R
2
45 IN VREG_GFXCORE_PWM3 VREG_GFXCORE_DRVL3 X866717-001
4 VREG_GFXCORE_CSN3
1
R1R11 DFN5 OUT 45
44 IN VREG_GFXCPU_DRV_EN 1 2VREG_GFXCORE_PH3_EN FET
VREG_GFXCORE_SW3_S
C 49.9 OHM 1%
1 R1P27 C
1
2
3
402 CH 1 C9C25
1 KOHM
1 C9D11 5% 0.15 UF
1000 PF 2 EMPTY 10%
10% 402 16 V
50 V
2 X7R
2 X7R R9C60 603
603 1 2 VREG_GFXCORE_CSP3 OUT 45
5.9 KOHM 1%
603 CH
R1P30
VREG_GFXCORE_CSSUM OUT 46 47
20 KOHM 1% 45
402 CH
V_5P0
B 1 R9E2
2.2 OHM B
1%
2 EMPTY
402
R1T1
1 2
5
VREG_GFXCORE4_VCC
2.2 OHM 1% 1
C9E2
1
C9E3
1 C1T1 1 C1T2
402 CH 10 UF 10 UF 10 UF 10 UF
1 C9E4 Q9E1 10% 10% 10% 10%
NTTFS4928N 2
16 V 2
16 V 2 16 V 2 16 V
1 UF X5R X5R EMPTY EMPTY V_GFXCORE
10%
16 V
R9E3 C9E5 X862002-001 805 805 805 805
2 VREG_GFXCORE_BST4 1 2 VREG_GFXCORE_BST4_R 1 2 4 DFN5
X7R
805 2.2 OHM 1% 0.1 UF 10% FET
U9E1 IC 805 CH 25 V
X7R
1
2
3
NCP5901B 603
4 VCC BST 1
45 VREG_GFXCORE_PWM4 R1T2 2 PWM DRVH 8 VREG_GFXCORE_DRVH4 L9E1
IN 1 2 VREG_GFXCORE_PH4_EN 3 7 VREG_GFXCORE_SW4 1 2
EN SW
1
6 5
1
49.9 OHM1% GND DRVL
ST9E1
SHORT
1 R9E1 230 NH IND
ST9E2
SHORT
402 CH 9 MPAD 1 OHM 61 A SM
1%
5
0.00029 OHM
X863210-001 2 CH
2
DFN9 805 VREG_GFXCORE_CSN4
2
OUT 45
Q9E2
VREG_GFXCORE_SW4_R
NTMFS4985NF 1 R9C51 1 C9C21
VREG_GFXCORE_DRVL4 X866717-001 1 KOHM 0.15 UF
4 DFN5 5% 10%
16 V
FET 2 EMPTY 2 X7R A
A 402 603
1
2
3
R9C52
1 C9E1 VREG_GFXCORE_SW4_S 1 2 VREG_GFXCORE_CSP4 OUT 45
MS_PART# MATL REF_DES TRUEDESCR. BOM PROPERTY 1000 PF
10% 5.9 KOHM 1%
Q9D5,Q9E1 X875319-001 FET TRA-N-CNL,SM,WDFN8,8.9 MOHM,30 V,24 A FET_CPUGFX_IRF
TRUE 50 V 603 CH
I73
Q9D5,Q9E1 X875313-001 FET TRA-N-CNL,SM,WDFN8,10 MOHM,30 V,27 A FET_CPUGFX_TOS

TRUE
2 X7R
I74
Q9D5,Q9E1 X876425-001 FET TRA-N-CNL,SM,WDFN8,9 MOHM,30 V,12 A FET_CPUGFX_STM

TRUE
603 R9C56
I72
Q9D5,Q9E1 X875316-001 FET FET_CPUGFX_AOS VREG_GFXCORE_CSSUM OUT 46 47 45

ZZ402
I76
TRA-N-CNL,SM,WDFN8,8.8 MOHM,30 V,24 A
TRUE
Q9D6,Q9E2 X875320-001 FET TRA-N-CNL,SM,SO-8FL,3.1 MOHM,30 V,50 A FET_CPUGFX_IRF
TRUE 20 KOHM 1%
I71
Q9D6,Q9E2 X875312-001 FET FET_CPUGFX_TOS 402 CH

I70
TRA-N-CNL,SM,SO-8FL,3.5 MOHM,30 V,35 A
TRUE
I69
Q9D6,Q9E2 X878211-001 FET TRA-N-CNL,SM,SO-8FL,4.5 MOHM,30 V,24 A FET_CPUGFX_STM
TRUE
Q9D6,Q9E2 X875317-001 FET TRA-N-CNL,SM,SO-8FL,3.6 MOHM,30 V,32 A FET_CPUGFX_AOS
ZZ403
I75

DRAWING PAGE
CONFIDENTIAL
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
VREGS, CPUCORE OUTPUT PHASE

D D
V_5P0 1 1 1 C1T3 1 C1T4
5
C9E8 C9E7
10 UF 10 UF 10 UF 10 UF
10% 10% 10% 10%
Q9E3 2
16 V 2
16 V 2 16 V 2 16 V V_CPUCORE
1 R1T4
X5R X5R EMPTY EMPTY
NTTFS4928N 805 805 805 805 NOM.VOLTAGE: 0.8-1.2V
2.2 OHM X862002-001
1% R9E6 C9E10 4
2 EMPTY
VREG_CPUCORE_BST
1 2 VREG_CPUCORE_BST_R 1 2 DFN5
402 2.2 OHM1% FET V_CPUCORE
805 CH 0.1 UF 10%
U9E2 IC 25 V
1
2
3
R9E5 X7R
1 2 VREG_CPUCORE_VCC NCP5901B 603
2.2 OHM 1% 4 VCC BST 1
402 CH 2 PWM DRVH 8 VREG_CPUCORE_DRVH L9E2
1 C9E9 3 EN SW 7 VREG_CPUCORE_SW 1 2
1 UF 6 GND DRVL 5
300 NH IND
10% 9
5
MPAD 42 A SM
16 V
2 X7R X863210-001 0.00047 OHM
1 R9E4
2
805
C
1
DFN9 1 OHM C
ST9E4
SHORT
Q9E4
ST9E3
SHORT
NTMFS4985NF 1%
44 VREG_CPUCORE_PWM X866717-001 2 CH
IN 4
805
1
R1T5 VREG_CPUCORE_DRVL DFN5
2
VREG_GFXCPU_DRV_EN VREG_CPUCORE_PH_EN
VREG_CPUCORE_SW_R
44 IN 1 2 FET
49.9 OHM 1% VREG_CPUCORE_CSN OUT 44
VREG_CPUCORE_SW_S
1
2
3
402 CH
1 R9C53 1 C9C23
1 KOHM
5% 0.15 UF
10%
1 C9E6 2 EMPTY 2 16 V
402 X7R
1000 PF 603
10% R9C50
50 V 1 2 VREG_CPUCORE_CSP OUT 44
2 X7R 7.15 KOHM1%
603 CH
402
R9C49
1 2 VREG_CPUCORE_CSSUM OUT 44
19.6 KOHM
1%
402 CH
B MS_PART#
Q9E3
MATL REF_DES
X875319-001 FET
TRUEDESCR. BOM PROPERTY
FET_CPUGFX_IRF B
I39
TRUE
I38
Q9E3 X875313-001 FET TRA-N-CNL,SM,WDFN8,10 MOHM,30 V,27 A FET_CPUGFX_TOS
TRUE
I37
Q9E3 X876425-001 FET TRA-N-CNL,SM,WDFN8,9 MOHM,30 V,12 A FET_CPUGFX_STM
TRUE
ZZ410
I43
Q9E3 X875316-001 FET TRA-N-CNL,SM,WDFN8,8.8 MOHM,30 V,24 A FET_CPUGFX_AOS
TRUE
I36
Q9E4 X875320-001 FET TRA-N-CNL,SM,SO-8FL,3.1 MOHM,30 V,50 A FET_CPUGFX_IRF
TRUE
I41
Q9E4 X875312-001 FET TRA-N-CNL,SM,SO-8FL,3.5 MOHM,30 V,35 A FET_CPUGFX_TOS
TRUE
I40
Q9E4 X878211-001 FET TRA-N-CNL,SM,SO-8FL,4.5 MOHM,30 V,24 A FET_CPUGFX_STM
TRUE
ZZ411
I42
Q9E4 X875317-001 FET TRA-N-CNL,SM,SO-8FL,3.6 MOHM,30 V,32 A FET_CPUGFX_AOS
A A

PAGE
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
VREGS, VTT TERMINATION POWERED BY V3P3 DUE TO

PHYSICAL LAYOUT CONSTRAINTS
V_5P0 EXHIBITS CORRECT FUNCTIONALITY
V_3P3
D D
1
1 R8C9 C8C7 U8C2 IC V_VTTD 1 U4R1 IC
1 UF 1 R4R4 C4R9
10 KOHM 10% TPS51206 TPS51206 V_VTTC
5% 10 KOHM 1 UF
6.3 V 10 10% 10
2 X5R VDD 1 5% VDD
2 CH FTP FT1P8 6.3 V 1
402
402 2 CH 2 X5R FTP FT4R3
2 VLDOIN VTT 3 402 402 2 VLDOIN VTT 3
1
R9C3 ST9C1 DB9C10 R4R5 ST4R1 1
DB6D5
1 VDDQSNS VTTSNS 5 VREG_VTTA_VO 1 2 1 2 1 VDDQSNS VTTSNS 5 VREG_VTTB_VO 1 2 1 2
0 OHM 5% 0 OHM 5% C4R22
VTTREF 6 VREG_VTTA_REFOUT 402 CH SHORT C9C10 VTTREF 6 VREG_VTTB_REFOUT 402 CH SHORT
1 2 1 2
PGND 4 1 UF 10% PGND 4 1 UF 10%
VREG_VTTA_EN 7 S3 GND 8 6.3 V VREG_VTTB_EN 7 S3 GND 8 6.3 V
9 11 1 X5R 9 11 X5R
S5 MPAD 402 S5 MPAD 402
VREG_VTTB_SNS
V_MEMIOCD 1 1 1 C9C1 1 1 1
C8C5 C9C5 C9C3 10 UF C9C7 V_MEMIOCD 1
C4R12 C4R13 1
C4R20
C4R31 1
1 UF 1 UF 10 UF 22 UF 1 UF 10 UF
VREG_VTTA_SNS
X864012-001 10% 10% 20%

20%
6.3 V 20% 1
C9C4
2
X864012-001 1 UF 10% 10 UF 20%
C4R26
10 UF 1
C4R15
2
SON11 6.3 V 6.3 V 6.3 V 2 X5R 6.3 V SON11 10% 6.3 V 20% 6.3 V
2 X5R 2 2 2 6.3 V 2 6.3 V 2 20%
X5R X5R 805 X7R 2 X5R 2 X5R 6.3 V
402 402 805 805 1 UF 10% X5R 402 X5R 805 2 1 UF 10%
402 805 X5R
6.3 V 805 6.3 V
X5R V_MEMIOCD X5R
402 1 R4R1 402
C V_MEMIOCD 1 R8C15
0 OHM C9C6
0 OHM
5% C4R28 C
5% 1 2 1 2
1 R4R2 2 CH
2 CH 1 1 KOHM 402 1
1 R8C13 402 FT1P9 FTP 1 UF 10% 1% FT4R2 FTP 1 UF 10%
1 KOHM 6.3 V 6.3 V
1 X5R 2 EMPTY 1 X5R
1% DB9C9 402 402 DB6D4 402
2 EMPTY C9C2 C4R32
402 1 2 1 R4R3 1 2
1 KOHM
1 R8C14 1 UF 10% 1% 1 UF 10%
1 KOHM 6.3 V 2 EMPTY 1 6.3 V
1% 1 X5R C4R6 X5R
C8C6 402 402 10 UF 402
2 EMPTY 10 UF 20%
402 20% 6.3 V
6.3 V 2 X5R
2 X5R 805
805
V_5P0
V_5P0
B B
1 R9F17 1 U9F4 IC V_VTTB
10 KOHM C9F11 1
1 UF
5%
10% TPS51206 1 R6E29 C6E16
1 UF
U6E4 IC
2 CH 6.3 V VDD 10 10 KOHM V_VTTA
2 1 10% TPS51206
402 X5R FTP FT1U6 5% 6.3 V
402 2 VDD 10
2 VLDOIN VTT 3 2 CH X5R
1 402 1
R9F18 ST9F1 DB9F5 402 FTP FT4T3
2 VLDOIN VTT 3
1 VDDQSNS VTTSNS 5 VREG_VTTC_VO 1 2 1 2 C9F14
1 2 R6E19 ST6E2 1
0 OHM 5% DB6E1
1 VDDQSNS VTTSNS 5 VREG_VTTD_VO 1 2 1 2
VTTREF 6 VREG_VTTC_REFOUT 402 CH SHORT C6E11
1 UF 10% 0 OHM 5% 1 2
6.3 V VTTREF 6 VREG_VTTD_REFOUT 402 CH SHORT
VREG_VTTC_SNS
PGND 4 X5R
VREG_VTTC_EN 7 8 402 1 UF 10%
S3 GND 4 6.3 V
9 11 1 1 PGND X5R
S5 MPAD 1 1 1 C9F19 C9F16 VREG_VTTD_EN 7 8
V_MEMIOAB C9F12 C9F13 C9F20 C9F17 S3 GND 402
10 UF 10 UF 1 2
VREG_VTTD_SNS
1 UF 1 UF 10 UF 9 S5 MPAD 11
1
X864012-001
SON11
10%
6.3 V
10%
6.3 V
20%
2
20%
6.3 V
2
20%
6.3 V
1 UF 10%
V_MEMIOAB C6E13 1 C6E12 1
C6E5
1
C6E8
1
C6E10 C6E4
2 2 2
6.3 V X5R X5R X864012-001 1 UF 1 UF 1 2
X5R X5R X5R 805 805 6.3 V 10% 10% 10 UF 10 UF 10 UF
V_MEMIOAB 402 402 805 X5R
402
SON11 2
6.3 V
2
6.3 V 20%
6.3 V
20%
6.3 V
20%
6.3 V 1 UF 10%
X5R X5R 2 2 2
1 R9F14 402 402 X5R
805
X5R
805
X5R
805
6.3 V
X5R
0 OHM C8F7
5% 1 2 402
1 R9F15 V_MEMIOAB 1 R6E31
2 CH 0 OHM C6E9
1 KOHM 402 1 UF 10% 5% 1 2
1% 6.3 V
1 X5R 2 CH
2 EMPTY FT7P11 FTP 402 1 UF 10%
402
1 R6E32 402 6.3 V
1 C9F18 1 KOHM 1 X5R
A 1 R9F16 DB9F6 1 2 1% FT4T4 FTP 402 A
1 KOHM 2 EMPTY 1 C6E7
1% 1 1 UF 10% 402 DB6E2 1 2
C9F10 6.3 V
2 EMPTY 10 UF X5R 1 R6E30
402 20% 402 1 UF 10%
6.3 V
1 KOHM 6.3 V
2 X5R 1% X5R
805 2 EMPTY 1 402
402 C6E17
10 UF
NOTE: VOSNS SHOULD BE CONNECTED AS A 20%
6.3 V
2 X5R
SEPARATE TRACE FROM VO PATH 805

PAGE
[PAGE_TITLE=VTT TERMINATION] DRAWING CONFIDENTIAL GREYBULL_RETAIL 49/72 49/72 M 1.0
Tue Jun 18 16:42:25 2013
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D
VREGS, NBCORE D
43 V_VREG_12P0_MEM_NBCORE MS_PART# MATL REF_DES TRUEDESCR. BOM PROPERTY

IN Q5F1 X875319-001 FET FET_MEMNB_IRF
I295
TRUE
I296
Q5F1 X875313-001 FET TRA-N-CNL,SM,WDFN8,10 MOHM,30 V,27 A FET_MEMNB_TOS
TRUE
1 C5F7 1 C5F8 1 C5U4 1 C5U3 I294
Q5F1 X876425-001 FET TRA-N-CNL,SM,WDFN8,9 MOHM,30 V,12 A FET_MEMNB_STM
TRUE
10 UF 10 UF 10 UF 10 UF ZZ412
I301
Q5F1 X875316-001 FET TRA-N-CNL,SM,WDFN8,8.8 MOHM,30 V,24 A FET_MEMNB_AOS
TRUE
10% 10% 10% 10% Q5F2 X875320-001 FET TRA-N-CNL,SM,SO-8FL,3.1 MOHM,30 V,50 A FET_MEMNB_IRF
TRUE
16 V 16 V 16 V 16 V
I291
R5F13 2 2 2 2 Q5F2 X875312-001 FET TRA-N-CNL,SM,SO-8FL,3.5 MOHM,30 V,35 A FET_MEMNB_TOS

TRUE
X5R X5R EMPTY EMPTY I293
1 2 805 805 805 805 I292

Q5F2 X878211-001 FET TRA-N-CNL,SM,SO-8FL,4.5 MOHM,30 V,24 A FET_MEMNB_STM
TRUE
2.2 OHM 1% ZZ413
I300
Q5F2 X875317-001 FET TRA-N-CNL,SM,SO-8FL,3.6 MOHM,30 V,32 A FET_MEMNB_AOS
402 CH 1 C5F4
1 UF
10%
C 2 16
X7R
V C
805 U5F3 IC
TPS53819A
5
VREG_NBCORE_VCC 8 VDD
VREG_NBCORE_LDO5 9 VREG
1
Q5F1
C5F6 FET
1 UF NTTFS4928N
10%
6.3 V DRVH 11VREG_NBCORE_DH 4 X862002-001
1 R5F15 2 X5R 69 26 57 51 VREG_PWRGPB_PWRGD 15 FT4U2 FTP
1
249 KOHM 402 OUT PGOOD DFN5 V_NBCORE
1% C5F5 1
13VREG_NBCORE_BST 1 2 DB6F2 NOM.VOLTAGE: 1.25V
1
2
3
2 CH 1 VBST
FT5U1 FTP
402 VREG_NBCORE_ADDR 16 ADDR
1 1VREG_NBCORE_ALERT_N 3 0.1 UF 10%
FT5U2 FTP DB5U1 ALERT_N 25 V V_NBCORE
1 R5F12 X7R
603
47.5 KOHM
1% 69 26 VREG_PWRGPB_EN 14 EN
IN L5F1
2 CH
402 65 44 26 SMBUS_CLK 1 SCL SW 12 VREG_NBCORE_SW 1 2 1
IN SMBUS_DATA 2
FTP FT4U1
66 65 64 54 53 52 44 40 26 BI SDA 400 NH IND
DRVL 10 VREG_NBCORE_DL
R5F18 1 42 A SM
B VREG_NBCORE_OCP 4 1 C6F9 1
5
0.00047 OHM
1 R5F10
TRIP
VO 5 VREG_NBCORE_VO
1 OHM
1% 820 UF
20%
1 C6F12
820 UF
DB6F1 B
130 KOHM 7 GND EMPTY 2 2.5 V 20%
2.5 V
1% 17 6 VREG_NBCORE_FB Q5F2 805 2 POLY 2 POLY
VREG_NBCORE_SW_R
MPAD FB RDL
2 CH NTMFS4985NF RDL
402 X869867-001 X866717-001
QFN17 4 DFN5
FET 1
FTP FT4U3
TO INCREASE CURRENT LIMIT
C5F9 1
1
2
3
FREQUENCY = 400KHZ, SET OVER I2C
INCREASE TRIP RESISTOR VALUE
SEE DATASHEET FOR REGISTER TABLE 1000 PF 1
10% DB6F3
50 V
1 EMPTY 2
TPS53819 I2C ADDRESS DB3T2 603
0010 101 R/W HEX
WRITE 0010 101 0 0X2A
READ 0010 101 1 0X2B R5F9 R5F7 ST3T3
1 2 1 2
10 KOHM 1% 0 OHM 5%
1 402 CH 805 EMPTY SHORT
DB5F1
1 R5F8 VENABLE
13.3 KOHM
1%
2 CH
402
2 VREG_NPCORE_FB_R_GND
A A
ST3T4
SHORT
1

PAGE
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
VREGS, MEMCORE
D D
43 IN V_VREG_12P0_MEM_NBCORE
1
C5T10
1
C5E21
1 C5E22 1 C5T9
V_5P0 10 UF 10 UF 10 UF 10 UF
10% 10% 10% 10%
VREG_MEMCORE_VID1 16 V 16 V 16 V 16 V
8 IN 2 X5R 2 X5R 2 EMPTY 2 EMPTY
805 805 805 805
8 VREG_MEMCORE_VID0 R5E30
IN 1 2 VREG_VDDR_VCC5
2.2 OHM 1%
V_SOC1P8 V_SOC1P8 402 CH 1
C5E14
V_MEMCORE
4.7 UF DUAL SETPOINT VR
10%
2
6.3 V
X5R
V_HI = 1.25V V_LO = 0.95V
603
1 R5E12 1 R5E25 1 R5E26 1 R5T15 OUT 50 57 26 69
10 KOHM 0 OHM 0 OHM 10 KOHM 1
1 U5E2 IC C5E23
5% 5% 5% 5%
C FTP FT5T4 4.7 UF
10% 1 C
5
2 EMPTY 2 CH 2 EMPTY 2 EMPTY NCP5269 6.3 V FT5T5 FTP
402 402 402 402 2 X5R
69 26 IN VREG_PWRGPB_EN 1 EN VCC 2 603 Q5E1 1
FET FT5T7 FTP
OUT VREG_MEMCORE_VID1_R 3 VID1 NTTFS4928N
VREG_MEMCORE_VID0_R 4 VID0 VCCP 12 X862002-001 1
4 DFN5 DB5E1
1 R5E22 1 R5E27 9 VREG_PWRGPB_PWRGD
10 KOHM 10 KOHM PG
5% 5% VREG_MEMCORE_SS 8 VREF V_MEMCORE
1
1
2
3
2 CH 2 CH VR_MM FTP FT4T5
402 402 RSET1 GH 14 VREG_MEMCORE_DH
VREG_MEMCORE_SET0 7 V1 1
1 R5E38 DB6E3
76.8 KOHM
1% R5T7 C5T12 L5E1
2 CH VREG_MEMCORE_SET1 6 V2 BST 15 VREG_MEMCORE_BST 1 2 VREG_MEMCORE_BST_R 1 2 1 2
402
2
2.2 OHM 1% 0.1 UF 10% 0.68 UH IND
ST5E3
SHORT
ST5E4
SHORT
5
805 CH 25 V 15.5 A SM
VREG_MEMCORE_SET2 5 V3 X7R 0.005 OHM
SW 13 VREG_MEMCORE_SW 603 R5E43 C5E20 1 C6E15 1 1 1
VREG_MEMCORE_SW_S 1 2 1 2 820 UF C5U5 C6F2 C5F1 C5U6 C6F1
1
Q5E2 20% 22 UF 22 UF 22 UF 22 UF 22 UF
VREG_MEMCORE_RTN 18 FBRTN NTTFS4939N 10 KOHM 1% 2.5 V 20% 20% 20% 20% 20%
0.1 UF 10% POLY 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V
X863539-001 402 CH 25 V 2 RDL 2 X7R X7R 2 X7R 2 X7R X7R
B 11 VREG_MEMCORE_DL 4
2
1 GL_FSET DFN5 1 R5E44 X5R 805 805 805 805 805

B
ST3T1
SHORT
C5E19 FET 402

1 OHM
0.1 UF CSP 16 VREG_MEMCORE_CSP 1%
10%
1
2
3
2
6.3 V 2 EMPTY R5E40
X5R 805
1
CSN 17 VREG_MEMCORE_CSN
VREG_MEMCORE_SW_R
402 1
4.99 KOHM1% FTP FT5U3
RSET2 FB 19 VREG_MEMCORE_FB 402 CH
10
1 R5E42 1
1 R5E35 PGND 15 KOHM DB5E2
15.8 KOHM 21 MPAD COMP 20 VREG_MEMCORE_COMP 1% 1
1% 2 CH 1 C5E25 DB3T3
2 CH X862818-001 402 1000 PF
402 QFN20 10%
50 V
2 EMPTY
603
1
ST5E2 IS OUTPUT VOLTAGE DB3T1
SENSE RETURN 1
DB5E3
PLACE NEAR ST1002 AND
RSET3 CONNECT TO GND PLANE
R5E39 R5E32 ST3T2
1 2 VREG_MEMCORE_S 1 2 1 2
1 R5E34 10 KOHM 1% 0 OHM 5%
18.7 KOHM 402 CH 805 EMPTY SHORT
1%
2 CH 1
C5E15
2 VREG_MEMCORE_RNT_R
R5E36 R5E37 1
C5E17
2
402
1 2 1 2 VREG_MEMCORE_FB_R VENABLE
3300 PF 10% 35.7 KOHM1% 562 OHM 1% 1500 PF 10%
50 V 402 CH 402 CH 50 V
X7R X7R
402 402
C5E18
1 2
RSET4 A
A 1 R5E29 68 PF 5%
50 V
130 KOHM NPO
1% 402
2 CH
402
NOTE: FSEL RES (R1127) FSW
2K 300KHZ
MS_PART# MATL REF_DES TRUEDESCR. BOM PROPERTY 6K 400KHZ
I306
Q5E1 X875319-001 FET TRA-N-CNL,SM,WDFN8,8.9 MOHM,30 V,24 A FET_MEMNB_IRF
TRUE 15K 600KHZ
I307
Q5E1 X875313-001 FET TRA-N-CNL,SM,WDFN8,10 MOHM,30 V,27 A FET_MEMNB_TOS
TRUE
I305
Q5E1 X876425-001 FET TRA-N-CNL,SM,WDFN8,9 MOHM,30 V,12 A FET_MEMNB_STM
TRUE
ZZ408
I312
Q5E1 X875316-001 FET TRA-N-CNL,SM,WDFN8,8.8 MOHM,30 V,24 A FET_MEMNB_AOS
TRUE
Q5E2 X875318-001 FET TRA-N-CNL,SM,WDFN8,6.3 MOHM,30 V,24 A FET_MEMNB_IRF
TRUE
I302
Q5E2 X875314-001 FET TRA-N-CNL,SM,WDFN8,5.4 MOHM,30 V,27 A FET_MEMNB_TOS

TRUE MICROSOFT PROJECT NAME PAGE CSA FAB REV
I308
Q5E2 X876423-001 FET TRA-N-CNL,SM,WDFN8,4.5 MOHM,30 V,17 A FET_MEMNB_STM

TRUE
PAGE
I309
ZZ409
I313
Q5E2 X875315-001 FET TRA-N-CNL,SM,WDFN8,5 MOHM,30 V,30 A FET_MEMNB_AOS CONFIDENTIAL GREYBULL_RETAIL 51/72 51/72 M 1.0
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
VREG, MEMIOCD
1 C5P2 1 C5P1 1 C5C5 1 C5C4

10 UF 10 UF 10 UF 10 UF
10% 10% 10% 10%
16 V 16 V 16 V 16 V
R6C4 2 X5R 2 X5R 2 EMPTY 2 EMPTY
1 2 805 805 805 805
2.2 OHM 1%
402 CH 1 C6C4
1 UF
C 10%
C
2 16
X7R
V
805 U6C1 IC
TPS53819A
5
VREG_MEMIOCD_VCC 8 VDD
VREG_MEMIOCD_LDO5 9 VREG
1 C6C13 Q5C1
FET
1 UF NTTFS4928N
10% 11 VREG_MEMIOCD_DH 4 1
1 R5C10
249 KOHM
2 16 V
X5R 69 26 56 53 VREG_PWRGPA_PWRGD 15 PGOOD
DRVH X862002-001
DFN5
FT4N2 FTP V_MEMIOCD
1%
603 OUT NOM.VOLTAGE: 1.5V
C5C10
13 VREG_MEMIOCD_BST 1 2 1
1
2
3
2 CH 1 VBST
FT5P4 FTP DB6B1 V_MEMIOCD
402 VREG_MEMIOCD_ADDR 16 ADDR
1 1 VREG_MEMIOCD_ALERT_N 3 0.1 UF 10%
FT5P3 FTP DB6C2 ALERT_N 25 V
1 R5C11 X7R
603
105 KOHM
1% 69 26 IN VREG_PWRGPA_EN 14 EN
2 CH L5C1
402 65 44 26 IN SMBUS_CLK 1 SCL SW 12 VREG_MEMIOCD_SW 1 2 1
FTP FT4N4
66 65 64 54 53 50 44 40 26 BI SMBUS_DATA 2 SDA 1 UH IND
10 VREG_MEMIOCD_DL
B 4
DRVL R6C2 1 13.9 A SM
1 C6C14 1
C6B10 1 B
5
VREG_MEMIOCD_OCP TRIP 1 OHM 0.003 OHM
5 VREG_MEMIOCD_VO 1% 820 UF 22 UF DB6C4
1 R6C11 VO 20% 20%
100 KOHM 7 GND EMPTY 2 2.5 V 6.3 V 1
DB3P1
1% 17 MPAD FB 6 VREG_MEMIOCD_FB Q5C2 805 2 POLY 2 EMPTY
VREG_MEMIOCD_SW_R
RDL 805
2 CH NTTFS4939N
402 X869867-001 X863539-001
QFN17 4 DFN5
FET
1
FTP FT4N1
C6C2 1
1
2
3
TO INCREASE CURRENT LIMIT 1000 PF 1
FREQUENCY = 400KHZ, SET OVER I2C 10% DB6B2
INCREASE TRIP RESISTOR VALUE
SEE DATASHEET FOR REGISTER TABLE 50 V
EMPTY 2
TPS53819 I2C ADDRESS 603 1
DB3P2
0011 001 R/W HEX
WRITE 0011 001 0 0X32 DUPLICATE TEST POINTS FOR
READ 0011 001 1 0X33 R6C8 R6C10 ST7C1 PROBING AT VR SOURCE+SINK
1 2 1 2 1 2
10 KOHM 1% 0 OHM 5%
DB6C1
1 R6C9 VENABLE
6.65 KOHM
1%
2 CH
402
2VREG_MEMIOCD_FB_R_GND
Q5C1 X875319-001 FET FET_MEMNB_IRF
A
I297
I295
Q5C1 X875313-001 FET

TRUE
FET_MEMNB_TOS
TRUE
A
I296
Q5C1 X876425-001 FET TRA-N-CNL,SM,WDFN8,9 MOHM,30 V,12 A FET_MEMNB_STM
TRUE
ZZ404
I303
Q5C1 X875316-001 FET TRA-N-CNL,SM,WDFN8,8.8 MOHM,30 V,24 A FET_MEMNB_AOS
TRUE
I294
Q5C2 X875318-001 FET TRA-N-CNL,SM,WDFN8,6.3 MOHM,30 V,24 A FET_MEMNB_IRF
TRUE
I298
Q5C2 X875314-001 FET TRA-N-CNL,SM,WDFN8,5.4 MOHM,30 V,27 A FET_MEMNB_TOS
TRUE
I293
Q5C2 X876423-001 FET TRA-N-CNL,SM,WDFN8,4.5 MOHM,30 V,17 A FET_MEMNB_STM
TRUE
ZZ405
I302
Q5C2 X875315-001 FET TRA-N-CNL,SM,WDFN8,5 MOHM,30 V,30 A FET_MEMNB_AOS
ST7C2
SHORT
1

PAGE
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
VREG, MEMIOAB
1 C9F4 1 C1U2 1 C1U3 1 C9F3

10 UF 10 UF 10 UF 10 UF
10% 10% 10% 10%
16 V 16 V 16 V 16 V
R1U3 2 X5R 2 X5R 2 EMPTY 2 EMPTY
1 2 805 805 805 805
2.2 OHM 1%
402 CH 1 C9F8
C 1 UF C
10%
2 16
X7R
V
805 U9F2 IC
TPS53819A
5
VREG_MEMIOAB_VCC 8 VDD
VREG_MEMIOAB_LDO5 9 VREG
Q9F2
1 C9F6 FET
1 UF NTTFS4928N
R9F6 10% DRVH 11 VREG_MEMIOAB_DH 4 X862002-001
1
249 KOHM 2 16
X5R
V 56 52 VREG_PWRGPA_PWRGD 15 PGOOD DFN5 FT1U3 FTP
1 V_MEMIOAB
1% 603 69 26 OUT NOM.VOLTAGE: 1.5V
C9F7
13 VREG_MEMIOAB_BST 1 2
1
2
3
2 CH 1 VBST
FT1U1 FTP 1 V_MEMIOAB
402 VREG_MEMIOAB_ADDR 16 ADDR DB9F7
1 1 VREG_MEMIOAB_ALERT_N 3 0.1 UF 10%
FT1U2 FTP DB9F2 ALERT_N 25 V
1 R9F11 X7R
603
90.9 KOHM
1% 69 26 VREG_PWRGPA_EN 14 EN
IN L9E3
2 CH
402 65 44 26 IN SMBUS_CLK 1 SCL SW 12 VREG_MEMIOAB_SW 1 2 1
FTP FT1U4
B 66 65 64 54 52 50 44 40 26 BI SMBUS_DATA 2 SDA
10 VREG_MEMIOAB_DL
R9F1 1 1 UH IND B
DRVL 1 OHM 13.9 A SM 1
VREG_MEMIOAB_OCP 4 1 C9E11 C9F21 1
5
TRIP 1% 0.003 OHM
5 VREG_MEMIOAB_VO EMPTY 2
820 UF 22 UF DB9F3
VO 20% 20%
1 R9F12 7 GND 805 2.5 V 6.3 V
2 POLY 2
VREG_VDDIOCD_SW_R
100 KOHM 17 MPAD FB 6 VREG_MEMIOAB_FB Q9F1 EMPTY 1
1% RDL 805 DB3U1
2 CH
NTTFS4939N
402 X869867-001 X863539-001
QFN17 4 DFN5
FET 1
FTP FT1U5
C9F2 1
1
2
3
TO INCREASE CURRENT LIMIT 1
FREQUENCY = 400KHZ, SET OVER I2C 1000 PF DB9F4
INCREASE TRIP RESISTOR VALUE 10%
SEE DATASHEET FOR REGISTER TABLE
50 V
EMPTY 2 1
TPS53819 I2C ADDRESS 603 DB3U2
0011 000 R/W HEX
WRITE 0011 000 0 0X30 DUPLICATE TEST POINTS FOR
READ 0011 000 1 0X31 R9F10 R9F13 ST7F1 PROBING AT VR SOURCE+SINK
1 2 1 2 1 2
10 KOHM 1% 0 OHM 5%
DB9F1
1 R1U5 VENABLE
6.65 KOHM
1%
2 CH
402
A
VREG_MEMIOAB_FB_R_GND
A I296
Q9F2
Q9F2
X875319-001
X875313-001
FET
FET
TRA-N-CNL,SM,WDFN8,8.9 MOHM,30 V,24 A FET_MEMNB_IRF
TRUE
FET_MEMNB_TOS
I294
TRUE
I295
Q9F2 X876425-001 FET TRA-N-CNL,SM,WDFN8,9 MOHM,30 V,12 A FET_MEMNB_STM
TRUE
ZZ406
I302
Q9F2 X875316-001 FET TRA-N-CNL,SM,WDFN8,8.8 MOHM,30 V,24 A FET_MEMNB_AOS
TRUE
I293
Q9F1 X875318-001 FET TRA-N-CNL,SM,WDFN8,6.3 MOHM,30 V,24 A FET_MEMNB_IRF
TRUE
I297
Q9F1 X875314-001 FET TRA-N-CNL,SM,WDFN8,5.4 MOHM,30 V,27 A FET_MEMNB_TOS
TRUE
I292
Q9F1 X876423-001 FET TRA-N-CNL,SM,WDFN8,4.5 MOHM,30 V,17 A FET_MEMNB_STM
TRUE
Q9F1 X875315-001 FET TRA-N-CNL,SM,WDFN8,5 MOHM,30 V,30 A FET_MEMNB_AOS
2
ZZ407
I301
ST7F2
SHORT
1

PAGE
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
VREGS, V5P0
D D
43 V_VREG_12P0_TO_5P0_3P3
IN
1 1 1 1
C6T17 C3E12 C4E4 C7T2
10 UF 10 UF 10 UF 10 UF
10% 10% 10% 10%
16 V 16 V 16 V 16 V
2 X5R 2 X5R 2 X5R 2 X5R
805 805 805 805
R3E23
1 2 VREG_5P0_VDD
2.2 OHM 1%
402 CH 1
C3E13
1 UF
10% U3E2 IC
16 V
C 2 X7R TPS53819A
C
5
603
8 VDD
VREG_5P0_LDO5 9 VREG
1 R7T4 Q3E2
1 10 KOHM NTTFS4939N
1 R3E20 C3E16 FT7T3 FTP 1 5%
X863539-001
1 UF 2 CH
249 KOHM 10% DRVH 11 VREG_5P0_DH 4 DFN5
1% 16 V 402
2 69 26 VREG_V5P0_PWRGD 15 PGOOD FET
2 CH X7R
603
OUT
402 C3E14
13 VREG_5P0_BST 1 2
1
2
3
VBST
VREG_5P0_ADDR 16 ADDR V_5P0
1 VREG_5P0_ALERT_N 3 0.1 UF 10%
DB3E4 ALERT_N 25 V 1 V_5P0
1 R3E18 1 X7R DB3F5 VOLTAGE: 5.09V
61.9 KOHM FT7T4 FTP 603 1
1% FT7U1 FTP
69 26 IN VREG_V5P0_EN 14 EN
2 CH L3E1
402 1 R3E22 65
10 KOHM 44 26 66 SMBUS_CLK 1 SCL SW 12 VREG_5P0_SW 1
IN SMBUS_DATA 2
FTP FT7T5
5% 50 44 40 26
BI SDA 1.5 UH
5
IND
2 CH 65 64 53 52 DRVL 10 VREG_5P0_DL 11.1 A SM
402 VREG_5P0_OCP 4 TRIP 0.00475 OHM 1 C3E15 C3E8 C3E9 C3E10
820 UF 22 UF 22 UF 22 UF 1
VO 5 VREG_5P0_VO 1 R3E25 20% DB3F7
Q3E1 1 OHM 20% 20% 20%
7 GND 6.3 V 6.3 V 6.3 V 6.3 V
1 R3E17 NTTFS4939N 1%
B 90.9 KOHM
1%
17 MPAD FB 6 VREG_5P0_FB
X863539-001 2 EMPTY 2 POLY
TH
X7R
805
X7R
805
X7R
805 B
4 DFN5 402 1
2 CH X869867-001 FTP FT7U2
FET VREG_5P0_SW_R
402 QFN17 1
1 DB3F6
C3E17
1
2
3
0.01 UF
10%
16 V
2 EMPTY
402
R3E19 R3E16 ST4B1

1 2 1 2 1 2
1 7.5 KOHM 1% 0 OHM 5%
DB3E3
402 CH 805 EMPTY SHORT
1 R3E21 C3E2
1 2 VENABLE
1 KOHM
TPS53819 I2C ADDRESS 1%
5.6 PF 0.5PF
0010 110 R/W HEX 2 CH 50 V
WRITE 0010 110 0 0X2C 402 NPO
2VREG_5P0_FB_R_GND
READ 0010 110 1 0X2D 402

ST3E1
SHORT

Q3E2 X875318-001 FET FET_5P0_IRF
A
I110
Q3E2 X875314-001 FET


TRUE
FET_5P0_TOS
TRUE
A
1
I114
I109
Q3E2 X876423-001 FET TRA-N-CNL,SM,WDFN8,4.5 MOHM,30 V,17 A FET_5P0_STM
TRUE
I115
ZZ414
I122
Q3E2 X875315-001 FET TRA-N-CNL,SM,WDFN8,5 MOHM,30 V,30 A FET_5P0_AOS
I117
TRUE
Q3E1 X875318-001 FET TRA-N-CNL,SM,WDFN8,6.3 MOHM,30 V,24 A FET_5P0_IRF
I116
Q3E1 X875314-001 FET TRA-N-CNL,SM,WDFN8,5.4 MOHM,30 V,27 A FET_5P0_TOS
Q3E1 X876423-001 FET TRA-N-CNL,SM,WDFN8,4.5 MOHM,30 V,17 A FET_5P0_STM
TRUE
ZZ451
I121
Q3E1 X875315-001 FET TRA-N-CNL,SM,WDFN8,5 MOHM,30 V,30 A FET_5P0_AOS

[PAGE_TITLE=VREGS, V5P0] GREYBULL_RETAIL
PAGE
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
VREGS, V5P0 DUAL
D D
R4B13
VREG_V5P0DUAL_CDG 1 2
100 OHM1%
V_5P0STBY 402 CH
1 1 C4B4
C4B2 220 UF
V_5P0STBY V_12P0 1 UF 20%
10% 10 V
1 10 V ELEC
C4B11 2 X5R 2 RDL
0.22 UF 402
10%
1 R6N1 1 R4B11 10 V
2 X7R
10 KOHM 10 KOHM 603
5% 5%
2 CH 2 CH U4B4 IC
C 402 402
SI4501DY V_5P0DUAL C
R4B9 R4B14 3 S2
1 2 VREG_V5P0_SEL_PGATE 1 2 VREG_V5P0_SEL_PGATE_R 4 G2
10 KOHM 1% VREG_V5P0_SEL_NGATE 0 OHM 5% D<3> 5 V_5P0DUAL
VREG_V5P0_SEL_C
402 CH 402 CH D<2> 8 NOM.VOLTAGE: 5.00V
2 1
U4B3 C4B1 C4B3 D<1> 7
0.22 UF 4.7 UF 6 1
3 6 10% 10% V_5P0 D<0> FTP FT6N1
6.3 V 16 V 2
R4B10 1 EMPTY 2 X5R G1
VREG_V5P0_DUAL_SEL0 1 2 VREG_V5P0_SEL_B1 5 2 VREG_V5P0_SEL_B2 1
26 IN 402 1206 S1 1
4.75 KOHM 1% DB4B6
1 402 CH
1 R4B8 FT6N3 FTP XSTR 1 R4B7 X801132-002 1
10 KOHM 4 1 DB4B7
5% 4.75 KOHM
1%
2 CH
402 2 CH
5
402
Q6N1
NTTFS4939N
X863539-001
4 DFN5
B FET B
1
2
3
VREG_5P0_SEL
VREG_V5P0_DUAL_SEL0 NGATE/PGATE V_5P0DUAL
HIGH LOW V_5P0STBY
LOW HIGH V_5P0
A A

DRAWING PAGE
[PAGE_TITLE=VREGS, V5P0 DUAL] Tue Jun 18 16:42:27 2013 CONFIDENTIAL GREYBULL_RETAIL 55/72 55/72 M 1.0
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
VREGS, V3P3
D D
43 V_VREG_12P0_TO_5P0_3P3
IN
1 1 1 1
C4F2 C6T20 C6U2 C4E10 C4E11
10 UF 10 UF 10 UF 10 UF 10 UF
20% 20% 20% 20% 20%
16 V 16 V 16 V 16 V 16 V
2 X5R 2 X5R 2 X5R X5R 2 X5R
1206 1206 1206 1206 1206
C C
1 V_3P3
1 R4F6 DB4F5
0 OHM
FT6U4 FTP
1 V_3P3
5% U4F1 IC VOLTAGE: 3.3V
2 CH L4F1
402 TPS54526
13 VIN1 SW1 10 VREG_V3P3_VSW 1 2
VREG_3P3_VIN2 14 VIN2 SW2 11
1.5 UH IND
C4F5 4.95 A SM 1
1 2 DB3R1
VBST 12 VREG_V3P3_BST 0.0156 OHM
1
C4F3
1 UF VO 1 0.1 UF 10% VREG_V3P3_VO
10% 25 V 1 R4F25 1
2
16 V
X5R
X7R
603
100 OHM FTP FT6U1
603 VFB 2 VREG_V3P3_FB 5% 1
2 CH DB4F1
PG 6 VREG_PWRGPA_PWRGD
OUT 52 53 1206 C4F21
VREG5 3 VREG_V3P3_VREG 26 69 C4E14 C4E13 C6U3 C4F7 C4F8 C6U4 470 UF
22 UF 22 UF 22 UF 22 UF 22 UF 22 UF 20%
R4F4 R4F5 ST4F3 20% 20% 20% 20% 20% 20% 6.3 V
69 26 VREG_PWRGPA_EN 7 EN PGND1 8 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V POLY
IN 9
1 2 1 2 1 2 EMPTY EMPTY X7R X7R X7R X7R TH
PGND2 805 805 805 805 805 805
GND 5 102 K 1% 0 OHM 5%
VREG_V3P3_SS 4 15
B SS MPAD 1
FTP FT5U4 B
VENABLE 1
X865085-001 1 R4F8 DB5F2
TSSOP15 30.1 KOHM
1 1%
C4F6 2 CH
0.022 UF
10% 402
16 V
2 X7R
402
1
C4F4
1 UF
10%
16 V
2 X7R
603
A A
PROJECT NAME PAGE CSA FAB REV

[PAGE_TITLE=VREGS, V3P3] MICROSOFT PAGE
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
VREGS, VSOCPHY
D D
C V_SOCPHY
NOM.VOLTAGE: 0.95V C
1
FT6U5 FTP
1
DB4F7
V_3P3
U4F3 IC V_SOCPHY
RT8071A
2 VCC
L4F2
3 VIN SW1 6VREG_SOCPHY_SW 1 2 1
1 1 FTP FT6U2
1
C4F14 C4F15 C4F16 SW2 7
1.5 UH IND 0.04 OHM
10 UF 10 UF
1 UF 20% 20% 2.6 A SM
10% 6.3 V 6.3 V FB 1 VREG_SOCPHY_FB
6.3 V 2 X5R 2 EMPTY VREG_PWRGPB_PWRGD 9 1 R4F16
2 X5R 805 805 51 50 OUT PGOOD
402 69 26 4.7 KOHM
8 5%
C4F12 C4F13 1
C4F17 1 R4F24
NC 182 OHMS
B GND1 4
5
2 EMPTY
402
22 UF
20%
22 UF
20%
10 UF
20% 1% B
2 EMPTY
VREG_SOCPHY_COMP_C
GND2 6.3 V 6.3 V 6.3 V
VREG_PWRGPB_EN 10 11 X7R X7R 2 X5R 603
69 26 IN EN MPAD 805 805 805
X865086-001
DFN11
1
C4F11
2200 PF
10%
50 V
2 EMPTY
402 1
DB4F2
C4F10
1 2 1
FTP FT6U3
220 PF 5% 1
50 V DB4F6
NPO
R4F14 402 R4F10 ST4F4
1 2 1 2 VREG_SOCPHY_FB_TOP 2 1
47.5 KOHM 1% 0 OHM 5%
1 R4F18 VENABLE
82.5 KOHM
1%
2 CH
402
A A

PAGE
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
VREGS, VSOCPLL + VBURN + VFUSE + VBAT V_BURN

V_BURN
NOM.VOLTAGE: 1.9V
D 2 3 1
DB6C3 D
V_3P3 1 1 U6C6
C6C7 C6C8 1 FET
1 UF 1 UF C6C101 1 1
10% 10% 1 UF C6D11 C6C9 1 R3R1
6.3 V 6.3 V 10% SOT23 0.047 UF 10 UF 1 KOHM
2 EMPTY 2 EMPTY 10% 10% 1%
402 402 6.3 V X857156-001
1 R6C14 2 X5R 10 V 6.3 V
I170 402 2 X7R 2 X5R 2 CH
4.7 KOHM 402 805 402
V_1P8STBY 5% U6C3 IC
2 EMPTY
V_BAT 402 CAT6219 R6D39
1 VIN VOUT 5 VREG_BURN_OUT
NOM.VOLTAGE: 1.8V VREG_BURN_OUT_G 1 2 VREG_BURN_OUT_CGD
1 R6C22 100 OHM 1%
1 R6R21 ADJ 4 1 OHM 1 R6D38 402 CH
I169 1% 5.49 KOHM
0 OHM 1%
5% V_BAT VREG_BURN_EN_R 3 EN GND 2 2 CH 1 R6C19
2 CH 402 887 OHM 2 CH
402 1 X865083-001 1% 402
C6C5 1 R6C15 2 CH
VREG_BURN_COUT
1 UF 10 KOHM SOT23-5 402
5%
CH
R6C13
10% 5%
2
6.3 V
1 R6R20 2 X5R 2 CH
402
0 OHM
402
402
4.99 KOHM
1
1%
2 EMPTY
402
C VREG_BURN_ADJUST C
I171 VREG_BURN_EN
8 IN
1
1 C6D1
C6C6 4.7 UF
0.1 UF 10%
10% 6.3 V
6.3 V 2 X5R 1 R6C16
2 EMPTY 603
402 1.65 KOHM
1%
2 CH
402
1 NOTE: BOTTOM ADJUST RESISTOR

FT5P6 FTP LEFT IN TO REDUCE EFFECT OF ADJUST
1 PIN CURRENT WHEN USED WITH 1K DIGIPOT
DB5C2
V_SOC1P8
V_SOC1P8
NOM.VOLTAGE: 1.83V
1
B 1
C5C19 1
C5C20
DB5D3
B
1 UF 1 UF 1 1
10% 10% FTP FT5R4 FTP FT5R5
6.3 V 6.3 V V_3P3
2 EMPTY 2 EMPTY 1
402 402 DB5D2
NOTE: THIS WAS SET TO 1.83V TO ACCOMODATE DROP IN FERRITES
V_3P3 1 V_FUSE
U5C3 IC 1 C6D5 NOM.VOLTAGE: 0.95V
DB5D1 1 UF
10% V_FUSE
NCP1117 2
6.3 V
3 IN OUT 2 1 X5R
FTP FT5P5 402 U6D1 IC
1 ADJUST/GND CAT6241
1 VIN1 VOUT1 7 1
1
C5C23 1 R5C20 1 R5C19 2 8
FTP FT4R1
1 UF X819037-001 1 OHM 200 OHM VIN2 VOUT2
10% 1% 1% 1 R6D8
6.3 V 2 CH 2 CH 69 26 VREG_PWRGPB_EN 4 EN ADJ 6 1 OHM 1
2 X5R 1.8V 402 603 IN 1%
C6D3 C6D4 DB6D2
402 3 2 CH 1 UF 1 UF
1 GND 402 10% 10%
DB6D3 5 CBYP MPAD 9 6.3 V 6.3 V 1
VREG_SOC1P8_COUT
X5R X5R DB3R2

402 402
X865082-001
VREG_FUSE_COUT
VREG_FUSE_CBYP
DFN9
1 R6D10
2.74 KOHM
VREG_SOC1P8_ADJUST 1%
A
I178
2 CH
402
A
1 VREG_FUSE_ADJ
C5C18 1
C5C21 R5C15
0.1 UF 1
10% 4.7 UF 100 OHM C6D6 1 R6D11
2
6.3 V 10%
6.3 V
1% 0.01 UF 1
C6D2 3 KOHM
EMPTY 2 CH 10% 4.7 UF 1%
402 X5R 16 V
603 402 2 EMPTY 10% 2 CH
402 6.3 V 402
2 X5R
603 I176
NOTE: BOTTOM ADJUST RESISTOR

LEFT IN TO REDUCE EFFECT OF ADJUST MICROSOFT PROJECT NAME PAGE CSA FAB REV
PIN CURRENT WHEN USED WITH 1K DIGIPOT
PAGE
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
VREGS, VSB2P5
D D
C V_SB2P5
NOM.VOLTAGE: 2.5V C
V_5P0
U3D5 IC V_SB2P5
RT8071A
2 VCC
L3D1
1 R3D3 3 6 VREG_SB2P5_SW 1 2 1
1 1 100 KOHM VIN SW1 FTP FT7R10
1
C3E4 C4B13 C4B12 1% SW2 7
1.5 UH IND 0.04 OHM
10 UF 10 UF 2 CH
1 UF 20% 20% 2.6 A SM
10% 6.3 V 6.3 V 402 FB 1 VREG_SB2P5_FB
6.3 V 2 X5R 2 X5R 1 R3D4 VREG_VSB2P5_PWRGD 9 1 R3E4
2 X5R 805 805 PGOOD
402 10 KOHM 4.7 KOHM
5% 8 5%
C3D1 C3D2 1
C3D3 1 R3D1
NC 182 OHMS
B 2 CH
402 GND1 4
5
2 EMPTY
402
22 UF
20%
22 UF
20%
10 UF
20% 1% B
GND2 6.3 V 6.3 V 6.3 V 2 EMPTY
VREG_SB2P5_COMP_C
VREG_VSB2P5_EN 10 11 X7R X7R 2 X5R 603
EN MPAD 805 805 805
1 X865086-001
C3D4 DFN11
4.7 UF
10%
6.3 V 1
2 EMPTY C3E3
603 2200 PF
10%
50 V
2 EMPTY
402 1
DB3D2
C3E1
1 2 1
FTP FT7R9
220 PF 5% 1
50 V DB3D1
NPO
402 R3D5 R3D2 ST3D1
1 2 1 2 VREG_SB2P5_TOP 2 1
47.5 KOHM 1% 0 OHM 5%
1 R3E2 VENABLE
15 KOHM
1%
2 CH
402
A A

PAGE
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
VREGS, VSB1P8PLL + VSB1P8IO + VSBCORE + VSB1P1PLL

D D
V_SB1P8
1 1
C7T8 C7T7 NOM.VOLTAGE: 1.83V
1 UF 1 UF
10% 10%
6.3 V 6.3 V V_SB1P8 1
2 EMPTY 2 EMPTY DB3E2
402 402
1
FT7T6 FTP 1 1
FTP FT7T2 FTP FT1U7
NOTE: THIS WAS SET TO 1.83V TO ACCOMODATE DROP IN FERRITES 1
V_SB2P5 DB3E5 1
DB3D10
U3E1 IC 1
FTP FT7T1
CAT6243DC
1 R7T7 4 VIN VOUT 2
1 R7T8
1
DB3E1
10 KOHM
5% 1 OHM
1
C7T4 ADJ 1 1% R3E10
1 UF
2 EMPTY
GND1 3 2 CH 1.47 KOHM
10% 26
402
VREG_SB1P8_EN 5 EN GND2 6 402 1%
6.3 V IN CH
2 X5R 402
C 402 X854310-001 C
VREG_SB1P8_COUT
DPAK-6
C7T6 1 R7T2
0.1 UF 10 KOHM
10% 5%
16 V
EMPTY 2 CH
603 402
VREG_SB1P8_ADJUST
1
R3E11
C7T5 1.15 KOHM
4.7 UF 1%
10% CH
6.3 V 402
2 X5R
603 V_SB1P1 1
DB3D4
1 1
C7R13 C7R12 1
FTP FT7R4
1 UF 1 UF
B NOTE: BOTTOM ADJUST RESISTOR 10%
6.3 V
10%
6.3 V V_SB1P1 B
LEFT IN TO REDUCE EFFECT OF ADJUST 2 EMPTY 2 EMPTY
PIN CURRENT WHEN USED WITH 1K DIGIPOT 402 402 NOM.VOLTAGE: 1.1V
1
FT7R7 FTP
V_SB2P5 1
DB3D9 1
DB3D5
1
FTP FT7R8
U3D3 IC 1
1 DB3D11
FTP FT7R3
CAT6243DC
1 R7R3 4 VIN VOUT 2
10 KOHM 1 R7R5
1 5% 1 1 OHM
C7R14 ADJ 1% R3D19
2 CH 3
1 UF 402 GND1
2 CH 825 OHMS
10%
6.3 V
VREG_SB1P1_EN 5 EN GND2 6
402 1%
2 X5R CH
402 X854310-001 402
VREG_SB1P1_COUT
1 DPAK-6
C7R15
0.1 UF
10%
16 V
2 EMPTY
603
VREG_SB1P1_ADJUST
A A
1 1
C3D17 C7R11 R7R4
0.1 UF 4.7 UF 2 KOHM
10%
6.3 V
10%
6.3 V
1%
2 EMPTY 2 X5R CH
402 603 402
NOTE: BOTTOM ADJUST RESISTOR

LEFT IN TO REDUCE EFFECT OF ADJUST
PIN CURRENT WHEN USED WITH 1K DIGIPOT PAGE
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
VREGS,STANDBY SWITCHERS 3P3 VREG_3P3STBY_IN_SEL

VREG_3P3STBY_IN_SEL
NGATE/PGATE VREG_3P3STBY_VCC
HIGH LOW V_5P0STBY
D LOW HIGH V_5P0

D
V_12P0
61 V_VREG_STBY_VIN
V_VREG_STBY_VIN
IN
61 IN
2 1 C3B1
C7N1 220 UF
1 R7N1 1 R3B1 0.22 UF 20%
10 KOHM 10 KOHM 10% 10 V
5% 5% 6.3 V ELEC
1 X5R 2 RDL
2 CH 2 CH 402
U3C1 IC
402 402
SI4501DY
R7P1 3 S2
1 2 VREG_3P3STBY_IN_SEL_PGATE 4 G2
61 V_VREG_STBY_VIN VREG_3P3STBY_IN_SEL_NGATE
IN 10 KOHM
402
1%
CH D<3> 5 V_VREG_3P3STBY_IN
VREG_3P3STBY_IN_SEL_C D<2> 8 NOM.VOLTAGE: 5.00V
2 1
1 R7N2 C3B2 C3C1 D<1> 7
4.7 KOHM 0.22 UF 22 UF
D<0> 6 1
5% 10% 20% V_5P0 FTP FT7P1
U7P1 6.3 V 10 V 2
2 CH 1 EMPTY 2 EMPTY G1
402 3 6 1
402 1206 S1
1 I288
R7P2 DB3C7
VREG_3P3STBY_IN_SEL 1 2 VREG_3P3STBY_IN_SEL_B1 5 2 VREG_3P3STBY_IN_SEL_B2
26 IN
C 1
4.75 KOHM 1%
402 CH 1 R7P3
X801132-002
1 C
FT7P2 FTP XSTR 4.75 KOHM DB3C8
4 1 1%
2 CH
402
V_5P0STBY
L4C1 V_VREG_3P3STBY_IN
1 2 OUT 61 62
2.2 UH IND V_3P3STBY
V_VREG_STBY_VIN
1.6 A 1210 NOM.VOLTAGE: 3.315V

0.08DCR MAX RECOMMENDED CURRENT: 1A
CR4C1
1
FT7P4 FTP 1
1 2 FT6P2 FTP
2 SMA 1
DB4C5
D4C1
B DIO
V_3P3STBY B
SMA U3C2 IC
1 EMPTY L4C2
R3C1 TPS54218
V_VREG_STBY_VIN_CR 1 VIN1 PH1 10 VREG_3P3STBY_SW 1 2 1
DB4C1
0 OHM 5% 2 VIN2 PH2 11 C3C2 1.5 UH IND
1210 1 R3C3 16 VIN3 PH3 12 2.6 A SM 1 C4C5 C6P2 1
EMPTY C3C3 1 R3C2 10 KOHM 0.04 OHM C4C6 C6P3 C4C8 FTP FT6P1
1 2 1% 0.1 UF 10%
0.05 OHM 10 UF 10 UF
100 KOHM 15 EN BOOST 13 VREG_3P3STBY_BT 22 UF 20% 20% 10 UF 10 UF
1% 2 CH 402 16 V 20% 6.3 V 6.3 V 20% 20%
10 UF 20% X7R 6.3 V X5R X5R 6.3 V 6.3 V
6.3 V 2 EMPTY VREG_3P3STBY_PWRGD 14 6 VREG_3P3STBY_FB 603 2 X7R 805 805 X5R X5R
402 PWRGD VSENSE
X5R
805 COMP 7 VREG_3P3STBY_COMP R3C6 805 805 805
1 2
GND1 3
GND2 4 93.1 KOHM1%
C7P3 1 1 402 CH
1 2 FTP FT7P10 8 RT/CLK AGND 5 C3C6 1
0.012 UF FTP FT6P3
9 SS MPAD 17
10 UF 20% 10% 1
6.3 V VREG_3P3STBY_EN 16 V
2 X7R
C3C8 C3C7 R3C9 1
DB4C4
EMPTY X865747-001 100 PF 1 2 1 2
VREG_3P3STBY_RT
805 402 5%
QFN17 50 V 0 OHM 5%
VREG_3P3STBY_COMP_C
1
VREG_3P3STBY_SS
C3C11 1 R7P5 C7P1

2 NPO 470 PF 5% 402 EMPTY
1 2 402 50 V ST4C3
0 OHM 4.7 UF NPO VREG_3P3STBY_FB_TOP 2 1
5% 10%
1 R3C7 402
10 UF 20% 6.3 V VENABLE
6.3 V 2 CH 2 X5R 30.1 KOHM SHORT
X5R 402 603 1%
805 2 CH
C3C4 402
1 2 1 R7P4 1 R3C10
20 KOHM 1 21.5 KOHM
1% FT7P5 FTP 1%
1 UF 10%
6.3 V 2 CH 2 CH
X5R 402 402
A 402
1 R3C8 VREG_3P3STBY_AGND
A
90.9 KOHM 1
C3C5
2
1% 1500 PF
ST3C1
SHORT
2 CH 10%
V_1P8STBY 402 50 V
2 X7R
402
1
[PAGE_TITLE=VREGS, STANDBY SWITCHERS] MICROSOFT PROJECT NAME PAGE CSA FAB REV
R5A5 SHOULD BE 182KOHM 0402, WAITING ON COMPONENT TB ADDED IN TC PAGE
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
VREGS,STANDBY SWITCHERS 1P1 + 1P8
D D
V_1P1STBY
NOM.VOLTAGE: 1.13V
MAX RECOMMENDED CURRENT: 1.25A
1
FT7P12 FTP
1
DB3C9
1
FT7P9 FTP
U3C4 IC V_1P1STBY
NCP3170 L3C2
61 V_VREG_STBY_VIN 2 VIN VSW 8 VREG_1P1STBY_SW 1 2 1
IN 1 R7P10 DB3C6
20 KOHM 4 VREG_1P1STBY_FB 0.04 OHM 1.5 UH IND
1 1% FB 2.6 A SM
1
C7P9
1
C7P8
1
C3C15 1 C3C16 C7P10 2 CH 402
1
C3C21 C7P12 C3C22 C7P13 C3C23 1
FTP FT7P14
1 UF 7 5 VREG_1P1STBY_COMP
C 10 UF
20%
10 UF
20%
10 UF
20%
10 UF
20%
10%
6.3 V
62 OUT VREG_1P1STBY_PWRGD
PG COMP
1
22 UF
20%
10 UF
20%
10 UF
20%
10 UF
20%
10 UF
20% C
6.3 V 6.3 V 6.3 V 6.3 V 2 X5R 1 R7P11 1 3 C3C17 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V
2 X5R 2 X5R 2 EMPTY 2 EMPTY 402 FTP FT7R5 AGND 2 X7R X5R X5R X5R X5R
805 805 805 805 10 KOHM 6 EN PGND 1 0.012 UF R3C27 805 805 805 805 805
1% 10%
16 V 1 2
2 CH 2 1
X865081-001 X7R 1 36.5 KOHM1% DB3C4
402 402 C7P11
VREG_1P1STBY_COMP_C
VREG_1P1STBY_EN SO8 100 PF 402 CH
5%
50 V C3C19 R3C28 1
2 1 2 FTP FT7P13
EMPTY 1 2
402
1 DB3C5 0 OHM 5%
C3C18 1 470 PF 5%
V_VREG_STBY_VIN 4.7 UF 50 V 402 EMPTY ST3C6
61 IN 10% 1 R3C24 1 R3C23 NPO VREG_1P1STBY_FB_TOP 2 1
2
6.3 V 21.5 KOHM 90.9 KOHM 402 VENABLE
1 R3C29 X5R
603
1% 1% SHORT
2 10 KOHM 2 CH 2 CH
CR7P2 5% 402 VREG_1P1STBY_AGND 402
2
2 EMPTY
SMA
ST3C3
SHORT
402
1 DIO
1
2
CR3C1
B SMA B
1 DIO
2
CR7P1 1 1
C3D6 C3D5
SMA 1 UF 1 UF
10% 10%
1 DIO 6.3 V 6.3 V
2 EMPTY 2 EMPTY
402 402 1 V_1P8STBY
FT7P15 FTP NOM.VOLTAGE: 1.8V
2 MAX RECOMMENDED CURRENT: 300MA
CR3C2 1
DB3C10
1 NOTE: THIS WAS SET TO 1.83V TO ACCOMODATE DROP IN FERRITES
SMA FT7N1 FTP V_1P8STBY
1 DIO
VREG_1P8STBY_IN U3C3 IC 1
DB3D7
1 R7P9 CAT6243DC
100 KOHM 4 VIN VOUT 2
1 R3D6
1% 1 OHM
1 1 2 EMPTY ADJ 1 1% 1 R7R1 C3D22 C3D21 C3D23 1
FTP FT7R6
C7P6 C7P5 10 UF 10 UF 10 UF
V_3P3STBY 402 GND1 3 2 CH 1.47 KOHM 20% 20% 20%
10 UF 1 UF 1% 6.3 V 6.3 V 6.3 V
CR3C3 20% 10% VREG_1P8STBY_EN 5 EN GND2 6 402
6.3 V 6.3 V 2 CH X5R X5R EMPTY
2 EMPTY 2 X5R 402 805 805 805
VREG_1P8STBY_COMP_C
2 1 805 402 X854310-001
1 R3D31 1
0 OHM DPAK-6 DB3C1
SMA 5% 1
DIO C3D20 1
A
2 CH
402
4.7 UF
20%
FTP FT7P16 A
6.3 V
2 X5R
1 DB3C2
402
VREG_1P8STBY_FB
1 R3D30 1 R7R2
20 KOHM 1
1% C3C9 1.15 KOHM
VREG_1P1STBY_PWRGD 4.7 UF 1%
62 IN 2 CH 10%
402 2 CH
6.3 V 402
2 X5R
603
[PAGE_TITLE=VREGS, STANDBY SWITCHERS] MICROSOFT PROJECT NAME PAGE CSA FAB REV
PAGE
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
V_3P3STBY R3B2
1 2
0 OHM 5% V_3P3STBY_IR
1
C7N2
0.1 UF
1210 EMPTY
U3B3 IC
TPS2065 V_3P3STBY_IR
IR BLASTER
10%
6.3 V 5 IN OUT 1
D 2 X5R
402 3 1
D
OC_N V_3P3STBY_IR_FLT_N
C7N3
0.1 UF
26 IN IR_BLAST_EN 4 EN GND 2 10% 1 R5B30
1
6.3 V 4.7 KOHM EG5A1
2 X5R C5B1 1%
1 R7N3 X862402-001 402 1 2 V_5P0DUAL 1 1 X882235-001
1 100 KOHM SOT23-5 2 C5A1 C5A3
FT7N2 FTP 5% 10 PF 5% 402 10 PF 10 PF
1 50 V
RT5B12
1 5% 5% DIO
2 CH DB3B1 EMPTY 50 V 50 V 402
402 2 EMPTY 2 EMPTY
2
402 PTC 402 402
1206 1
3 X882908-001 C5B11
R5B29 V_3P3STBY_IR J5A2 CONN
26 IR_BLAST_SMC_OUT 1 2 1 Q5B1 10 UF
IN 20% 3 3 5
1 KOHM 1% XSTR 10 V MH2
2
IR_BLAST_SMC_OUT_C
402 CH 2 X5R MH1 4
1 R5B1 603
10 KOHM
R5A1 R5A2
IR_BLAST_SNUB 1 2 IR_BLAST_TIP 1 2 IR_BLAST_TIP_R 2 2
5% V_3P3STBY_IR 1
2 CH
C5B13 10 OHM 1% 0 OHM 5%
0.1 UF 1 805 CH 603 CH R5A3
402 10%
6.3 V
C5A2 1 2 IR_BLAST_SLEEVE_R 1 1
2 0.01 UF
X5R 10% 0 OHM 5% IR_JACK_3P
402 50 V CH
1 R5B19 U5B4 IC 2 X7R 603
10 KOHM 74LVC1G00 805 IR_BLAST_SLEEVE X852978-004
1% 2 5 R5B25 TH
C R5B28 2
402
A VCC
Y 4IR_BLAST_OR_OUT 1 2 C
1
1 2 IR_BLAST_P3_1_R 1 B GND 3 0 OHM 5% 1
C6A1 1
C6A2 EG6A1
0 OHM 5% 402 CH
4 10 PF 10 PF X882235-001
402 CH X853473-001 SC70 R5B26 5% 5%
IR_BLAST_P3_1_OUT 1 2 IR_BLAST_G1 Q6B1 2
50 V
EMPTY 2
50 V
EMPTY DIO
1.47 KOHM1% NPN 402 402 402
2
402 CH
Q5B2
IR_BLAST_E1
R5B27 R5B21
1 2 IR_BLAST_SENSOR_SIG 1 2 3 XSTR R6B11
0 OHM 5% J6B2 24.9 OHM1% 1 R5B22 1 IR_BLAST_G2 1 2
402 EMPTY 1X2HDR 402 CH 10 KOHM
1% 221 OHM 1%
1
OUT 36 2 402 CH 1 R6B10
2 2 CH 15.8 OHMS
IR_BLAST_P3_1_IN
402 1%
2 CH
SM 805
EMPTY
IR_BLAST_XIN
U3C6 IC V_3P3STBY_IR
V_3P3STBY_IR IC U3B1 V_3P3STBY_IR S3F80P5
B 74LVC1G07 2 22 B
5 TEST VDD
VCC
1 R3C39 24 XIN XOUT 1
1
C7N5 4 Y A 2 475 OHM
1%
1
C3C25 1
C3C26 1 R3C13
10 KOHM
1 UF 20 P3_1/REM/T0CK 0.1 UF 1 UF 1%
10% 3 GND NC 1 2 EMPTY 10% 10%
6.3 V 19 P3_0/T0PWM/T0CAP/T1CAP/T2CAP 6.3 V 6.3 V 2 CH
2 402 2 2
X5R 1 R7N5 X5R X5R 402
402 SC70 X801758-001 10 KOHM IR_BLAST_LED 21 P2_0/INT5
402 402
5%
2 EMPTY 18 P1_7
R7P13
402 1 2
17 P1_6
IR_BLAST_P1_5 16 P1_5 1 MOHM 5%
R3B3 1 V_3P3STBY_IR 15 P1_4
402 EMPTY
70 IR_BLAST_TXD 1 2 D3C2 8 MHZ
OUT 14 P1_3
0 OHM 5% GREEN 13 XTAL
402 EMPTY 1 R3C38 P1_2
V_3P3STBY_IR SM 12 Y3C1
2 EMPTY 10 KOHM P1_1
U3B2 IC 1% 11 P1_0 XTAL
74AUP1G125 2 EMPTY IR_BLAST_XOUT
VCC 5 402 10 P0_7/INT4 1 3
IR_BLAST_P0_6 9 P0_6/INT4
2 A Y 4 1 IR_BLAST_P0_5 8 P0_5/INT4 2
C7N4 7 P0_4/INT4
1 3
1 UF
10%
V_3P3STBY_IR 6
OE_N GND
6.3 V
P0_3/INT3 X854881-001
2 5 NRESET/P0_2_INT2 VSS 23 SM
1 R7N4 X5R
4
10 KOHM X867692-001 402 R3C12 SCLK/P0_1/INT1 CH
5% SC70-5 1 KOHM 3 SDAT/P0_0/INT0 MPAD 25
2 CH 1%
402 X855475-001
A R3C37
EMPTY
402
IR_BLAST_P0_7 QFN25 A
70 IR_BLAST_RXD 1 2
IN R3B4
0 OHM 5%
402 EMPTY 1 KOHM
1%
CH
402

PAGE
CONFIDENTIAL GREYBULL_RETAIL 63/72 CH
63/72 M 1.0
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
I2C
65 44 26 SMBUS_CLK 1
IN FTP FT4P1
D V_5P0STBY D
66 65 54 53 52 50 44 40 26 SMBUS_DATA 1
BI FTP FT4P3 R3E7
0 OHM
5%
EMPTY
402
I2C_2X2_HDR_VDD
J3E2
2X2HDR
1 2
3 4
TH
EMPTY
C C
B B
A A

PAGE
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
FACET, FTDI
D D
V_3P3STBY
R4E2
C 42 26 29 OUT SMC_RST_N 1 2
C
100 OHM 1%
402 CH
1
R4E3 C4E1 1 C4E2
27 SPI_MISO 1 2 1 UF 1 UF
IN 10% 10%
0 OHM 5% 6.3 V 6.3 V
402 CH 2 X5R 2 X5R
27 OUT 402 402
OUT 27
27 OUT
27 J4E1 R4D1
OUT 2X13HDR 1 2 SB_TDO
IN 27
27 OUT SMC_RST_N_FACET 1 2 33 OHMS 1%
SPI_MISO_FACET 3 4 SPI_MOSI 402 CH
27 KER_DBG_CTS 27
OUT SPI_SS_N 5 6 OUT
SPI_CLK 7 8
SB_TDI 9 10 SB_TDO_FACET
R4E4 SB_TMS 11 12
26 SMC_DBG_LED0_SWO 1 2
IN SB_TCK 13 14
33 OHMS 1% SMC_DBG_LED0_SWO_FACET 15 16
402 CH KER_DBG_TXD_FACET 17 18 KER_DBG_RTS_FACET
KER_DBG_RXD 19 20 FTDI_SMC_CTS_FACET
R4E5 FTDI_SMC_TXD_FACET 21 22 FTDI_SMC_RTS_FACET R4E1
B 27 IN KER_DBG_TXD 1 2 FTDI_SMC_RXD_FACET 23 24 1 2 KER_DBG_RTS
IN 27 B
33 OHMS 1% SMBUS_CLK_FACET 25 26 SMBUS_DATA_FACET 33 OHMS 1%
402 CH 402 CH 1
IN SM DB4E1
EMPTY 1
1 DB4E2
DB4E3
1 R5T1
DB4E4 1 2 SMBUS_DATA 26 40 44 50 52 53 54 64 66
BI
R5T2 0 OHM 5%
66 64 54 53 52 50 40 44 26 SMBUS_CLK 1 2 402 CH
BI
0 OHM 5%
402 CH
A A

PAGE
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
FACET, FTDI+MISC
D D
V_3P3STBY
C C
1
C5U10 1
C5U9
0.1 UF
DEBUG 10% 1 UF
1 R5U4 1 R5U5 6.3 V 10%
0 OHM 0 OHM EMPTY 2 6.3 V
2 EMPTY
5% 5% U5F4 EMPTY 402
402
2 EMPTY 2 EMPTY
402 402 CAT24M01
EEPROM_A2 3 A2 VCC 8
EEPROM_A1 2 A1
SDA 5 SMBUS_DATA 26 40 44 50 52 53 54 64 65
SMBUS_CLK 6
BI
65 44 26 IN SCL
7 WP NC 1
VSS 4
MPAD 9
CAT24M01 I2C ADDRESSES
1010 110 R/W HEX X868479-001
WRITE 1010 110 0 0XAC DFN9
READ 1010 110 1 0XAD
B B
1010 111 R/W HEX
WRITE 1010 111 0 0XAE
READ 1010 111 1 0XAF
A A

PAGE
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
CONN, SWITCHES
D D
V_12P0
V_5P0STBY
1 R8B17
1 R8B18 6.04 KOHM
R4F21 2 KOHM 1%
EJECTSW_N_SW EJECTSW_N 40 26 1% 2 EMPTY
OUT 402
2.49 KOHM 1% 2 EMPTY
402 CH 402
J4F4
V_12P0_LED_R
1X2HDR
V_5P0STBY_LED_R
1
2
C TH C
EMPTY
1
1 D8B1
D8B2 GREEN
GREEN SM
SM 2 EMPTY
2 EMPTY
R4F20
PWRSW_N_SW PWRSW_N 40 26
OUT
2.49 KOHM 1%
402 CH
J4F5
1X2HDR
1
2
TH
EMPTY
B B
A A

PAGE
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
CONN, HDT
D D
V_SOC1P8
1 R5E19
1 KOHM
1%
R5E14 1 2 EMPTY
1 KOHM 402
V_SOC1P8 1% 1 R5E18
EMPTY 2 1 KOHM
402 1%
2 EMPTY
402
C 1 R5E17
1 KOHM
1
FTP FT4T2 C
V_SOC1P8 1 1%
FT5T1 FTP 2 EMPTY 1
402 FTP FT5T3
1 1 1
C5E1 C5T6 C5T4 DEBUG
1 UF 0.1 UF 0.1 UF 1
10% 10% 10% FT5T2 FTP 1
6.3 V 6.3 V 6.3 V J5E1 FTP FT5T6
1 R5E4 2 EMPTY 2 EMPTY 2 EMPTY
1 KOHM 402 402 402 2x10HDR_HDT
5% 1 2 TCK
OUT 8
2 CH 3 4 TMS
402 OUT 8
5 6 TDI 8
7 8 TDO
OUT
R5E3 IN 8
1 2 9 10
8 OUT TRST_L HDT_TRST
HDT_PIN11 11 12
PWROK_BUF
RESET_L_BUF
0 OHM 5%
402 EMPTY HDT_PIN13 13 14 DBRDY 8
HDT_PIN15 15 16 DBREQ_L
IN
OUT 8
17 18 TEST19 70 8
19 20 TEST18
OUT
OUT 70 8
SM V_SOC1P8
EMPTY
1 R5D8 1 R5E2
B 10 KOHM
5%
10 KOHM
5%
1 R5E1
10 KOHM 1 B
2 EMPTY 2 EMPTY
5% C6E1 1 R5E16 1 R5E15
2 EMPTY 0.22 UF
402 402 10% 1 KOHM 1 KOHM
402 6.3 V 5% 5%
U6E1 EMPTY 2 EMPTY
402 2 EMPTY 2 EMPTY
X802100-002 402 402
SN74AUP2G07
SW4F2 EMPTY VCC 5
3 4 COLD_RESET_N 26
OUT 1 1A 1Y 6
1 2 J4F2 3 2A 2Y 4
1X2HDR 1
SM 1 C4F18 GND 2
0.22 UF
2 10%
6.3 V
2 EMPTY V_SOC1P8 X865298-001
TH 402 SC70-6
EMPTY
26 SOC_PWR_OK
V_SOC1P8 1
IN
C6E2
0.22 UF
10% V_SOC1P8
1 R3F2 6.3 V
2 EMPTY
47 KOHM 402
1%
2 EMPTY U4F4 EMPTY U6E2 EMPTY
402
SN74AUP1G17 74LVC1G07
A
X802100-002
SW4F1 EMPTY VCC 5 VCC 5 A
3 4 WARM_RESET_N 2 A Y 4 WARM_RESET_N_DEBOUNCE 2 A Y 4 SOC_RST_N 26 8
OUT
1
1 2 C4F19 1 NC GND 3 1 NC GND 3
J4F1 0.22 UF
10%
SM 1X2HDR 6.3 V
X862374-001 X801758-001 SC70
1 2 EMPTY SC70-5
2 402
TH
EMPTY
PAGE
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
DEBUG, VR HEADERS AND TEST POINTS

D D
V_CPUCORE V_GFXCORE V_NBCORE V_MEMCORE V_SOCPHY V_BURN V_SB1P8 V_1P1STBY

EMPTY EMPTY EMPTY EMPTY EMPTY EMPTY EMPTY EMPTY
TP9F1 TP9C2 TP6F1 TP5E2 TP4F4 TP6D4 TP5C2 TP3C1
1 1 1 1 1 1 1 1
C EMPTY EMPTY EMPTY EMPTY EMPTY EMPTY EMPTY EMPTY C

V_VTTD V_VTTB V_3P3 V_5P0 V_5P0DUAL V_SOC1P8 V_FUSE V_SB1P8 V_1P8STBY
EMPTY EMPTY EMPTY EMPTY EMPTY EMPTY EMPTY EMPTY EMPTY
TP9C1 TP9F3 TP5F1 TP3E3 TP4B1 TP5D2 TP6D1 TP5D1 TP4D2
1 1 1 1 1 1 1 1 1

V_VTTC V_VTTA V_3P3STBY V_5P0STBY V_12P0 V_SOC1P8 V_BAT V_SB1P1 V_SB1P1
TP6D2 TP6E1 TP4C1 TP4B3 TP8B1 TP3F1 TP4D3 TP3D3 TP3D2
1 1 1 1 1 1 1 1 1
V_MEMIOCD TP4B2 TP9F4

EMPTY TP5B1 TP5C1 TP4E1
TP6C1 1 1
1 1 1
1 EMPTY EMPTY
EMPTY EMPTY EMPTY
EMPTY EMPTY EMPTY EMPTY EMPTY
B EMPTY B
EMPTY TP3E2 V_MEMIOAB TP4C2 TP5E1
VREG_V5P0_PWRGD 1 EMPTY TP4D1 TP6F2 TP8B2
54 IN 1 1
TP9F2 1 1 1
1 EMPTY EMPTY
EMPTY EMPTY EMPTY EMPTY EMPTY EMPTY
EMPTY EMPTY EMPTY
EMPTY TP3E1 EMPTY
54 26 VREG_V5P0_EN 1
OUT
EMPTY
EMPTY TP4F5
57 51 50 VREG_PWRGPB_PWRGD 1
IN
EMPTY
EMPTY TP4F3
58 57 51 50 26 VREG_PWRGPB_EN 1
OUT
EMPTY
EMPTY TP4F1
56 53 52 VREG_PWRGPA_PWRGD 1
IN
EMPTY
EMPTY TP4F2
56 53 52 26 VREG_PWRGPA_EN 1
OUT
A A
EMPTY
EMPTY TP7C1
45 44 VREG_CPUGFX_PWRGD 1
IN
EMPTY

PAGE
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
DEBUG, CONNECTORS
D
D
TITAN POWER CONNECTOR

V_3P3STBY
DEBUG
J3C2
1X2HDR
1
2
TH
EMPTY
C C
V_SOCPHY
1 R5F31
1
FTDI_SMC_CTS IR_BLAST_RXD 63 510 OHM
DB4D2 OUT 5%
R6R11 1 2 CH
63 IR_BLAST_TXD 100 OHM FTDI_SMC_RTS 1 402
IN 5% DB4D3
CH 2 1 R6R10
R6R8 1 1 R6R9 402 100 OHM
100 OHM 100 OHM 5%
5% 5%
2 EMPTY
CH 2 2 EMPTY 402
402 402
2 TEST25_N
IN
B 2 IN TEST25_P B
TEST19 68 8
OUT
TEST18 68 8
1 R5E7 OUT
1 KOHM
5%
1 R5F27 2 EMPTY
510 OHM 402
26 BI SMC_TXD
5%
1 R5E8
26 SMC_RTS 1 KOHM
BI SMC_CTS 2 CH 5%
26 BI 402
SMC_RXD 2 EMPTY
26 BI 402
A
A
MICROSOFT PROJECT NAME PAGE CSA REV

PAGE
CONFIDENTIAL GREYBULL_RETAIL 70/72 70/72 1.0
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
DEBUG, ENET EEPROM + MISC

D D
C C
V_3P3STBY_ENET
1
C5B3
0.1 UF
10%
6.3 V
2 EMPTY
402
U5B1 EMPTY
93LC66B
VCC 8
ENET_EEDI 3 4 ENET_EEDO
B 32 IN DI DO OUT 32
B
32 ENET_EESK 2 CLK NC1 6
IN 7
NC2
32 ENET_EECS 1 CS GND 5
IN
X867158-001
TSSOP8
A A

PAGE
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D LABELS AND MOUNTING D
HEAT SINK MOUNTING HOLES
STD STD
MTG8D1 MTG7E1
MTG_HOLE MTG_HOLE
NC9 9 NC9 9
EMPTY EMPTY
GND=1,2,3,4,5,6,7,8 GND=1,2,3,4,5,6,7,8
C STD STD C
MTG8E1 MTG7D1
MTG_HOLE MTG_HOLE
NC9 9 NC9 9
EMPTY EMPTY
GND=1,2,3,4,5,6,7,8 GND=1,2,3,4,5,6,7,8
B INTELLIGENT SERIAL NUMBER TARGET B

X801181-001
LB3F1
LABEL
1
1375X250_TARGET
A A

PAGE
8 7 6 5 4 3 2 1

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8 7 6 5 4 3 2 1

32 PEX_ENET_SOC_TP_C AN21 P_UMI_RX2_P P_UMI_TX1_P AU23 PEX_L1_SOC_SB_TP

DP_TX_CALR AM12 DP_TX_ZVSS

MICROSOFT PROJECT NAME PAGE CSA FAB REV

SOC POWER, MEM + CPUCORE + MEMCORE + NBCORE + MISC

V_MEMIOCD V_CPUCORE U7E1 IC

MICROSOFT PROJECT NAME PAGE CSA FAB REV

SOC POWER, V_GFXCORE + VSS

MICROSOFT PROJECT NAME PAGE CSA FAB REV

22 MA_DQ63 AM28 MA_DQ63

SOC VSS + SPARE

MICROSOFT PROJECT NAME PAGE CSA FAB REV

SOC DEBUG + SB SIGNALS

68 26 SOC_RST_N AR17 RESET_N SVT E10 SVT 44 R3T4

MICROSOFT PROJECT NAME PAGE CSA FAB REV

MICROSOFT PROJECT NAME PAGE CSA FAB REV

C3R7 C2R7 C3T38 C2T74

MICROSOFT PROJECT NAME PAGE CSA FAB REV

MICROSOFT PROJECT NAME PAGE CSA FAB REV

U8C4 MEM U8C3 MEM

MICROSOFT PROJECT NAME PAGE CSA FAB REV

MEMORY CHANNEL D, DECOUPLING + TERMINATION

MICROSOFT PROJECT NAME PAGE CSA FAB REV

MICROSOFT PROJECT NAME PAGE CSA FAB REV

U6D2 MEM U6D3 MEM

MICROSOFT PROJECT NAME PAGE CSA FAB REV

MEMORY CHANNEL C, DECOUPLING + TERMINATION

MICROSOFT PROJECT NAME PAGE CSA FAB REV

MICROSOFT PROJECT NAME PAGE CSA FAB REV

MEMORY CHANNEL B V_MEMIOAB

MS_PART# MATL REF_DES TRUEDESCR. BOM PROPERTY

MICROSOFT PROJECT NAME PAGE CSA FAB REV

MEMORY CHANNEL B, DECOUPLING + TERMINATION

[PAGE_TITLE=MEMORY PARTITION C, DECOUPLING, TERMINATION]

MICROSOFT PROJECT NAME PAGE CSA FAB REV

[PAGE_TITLE=MEMORY PARTITION D, HIGH]

MICROSOFT PROJECT NAME PAGE CSA FAB REV

MEMORY CHANNEL A, DECOUPLING + TERMINATION

[PAGE_TITLE=MEMORY PARTITION D, DECOUPLING, TERMINATION] MICROSOFT PROJECT NAME PAGE CSA

CONFIDENTIAL GREYBULL_RETAIL 23/72 23/72 M 1.0

KIC, USB 6 of 11 I84

USBD_D0_DN AE8 USB2_WIFI_DN 36

USBB_D1_DP AD2 USB2_BP_P0_DP 35

USBA_D1_DP AF6 USB2_ACC_DP 36

37 IN TMDS_RX_DN1 L3 TMDS_RX_DN1 6.3 V 402

MS_PART# MATL REF_DES TRUEDESCR. BOM PROPERTY

MICROSOFT PROJECT NAME PAGE CSA FAB REV

67 40 PWRSW_N V23 SMC_P4_GPIO7 SMC_UART1_RTS V24 SMC_RTS 70

58 57 51 50 69 VREG_PWRGPB_EN R21 SMC_P3_GPIO2 R5R7

MICROSOFT PROJECT NAME PAGE CSA FAB REV

MICROSOFT PROJECT NAME PAGE CSA FAB REV

KIC, CLOCKS + STRAPPING + POR R5R20

1 250M_CLK_BYPASS_DP F20 250M_CLK_BYPASS_DP PEX_REF_CLK1_DP C14 ENET_PEX_SS_100M_CLKP 32

BKUP_SB_AV_CLKP D16 AV_CLK_BYPASS_DP PEX_REF_CLK0_DP A15 SOC_PEX_SS_100M_CLKP 2

MICROSOFT PROJECT NAME PAGE CSA FAB REV

MICROSOFT PROJECT NAME PAGE CSA FAB REV

V_1P1STBY V_KIC1P8AUX V_SB1P1 V_3P3STBY V_1P8STBY V_KIC1P8USB V_KIC3P3XTAL V_SB1P1

MICROSOFT PROJECT NAME PAGE CSA FAB REV

CH 2.49 KOHM 40 7 MDIP2

MICROSOFT PROJECT NAME PAGE CSA FAB REV