BASIC VLSI DESIGN

Principles and Applications

Douglas A. Pucknell
Kamran Eshraghian
Department of Electrical and Electronic Engineering
The University of Adelaide
and Directors of Integrated Silicon Design Pty Ltd
Adelaide, South Australia
lechnische Hochschule Darmstadt
FACHBEREICH INFORMATfK
B I 8 L I O T H E K
Inviantnr.Mr . Z?.7 / T~~ ,
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Sachgebiete
Standorh :
Prentice-Hall of Australia Pty Ltd
Contents
Figures
Tables
Preface
Acknowledgments
VIII
xiii
xiv
xvii
Chapter 1
Chapter 2
Chapter 3
A Review of Microelectronics and an Introduction to nMOS
Technology
1.1 Introduction to Integrated Circuit Technology
1.2 The Integrated Circuit (IC) Era
1.3 Metal-Oxide-Semiconductor (MOS) Technology and VLSI
1.4 Basic nMOS Transistors
1.5 Enhancement Mode Transistor Action
1.6 Depletion Mode Transistor Action
1'7 nMOS Fabrication
1.8 Summary of an nMOS Process ,
Basic Electrical Properties of nMOS Circuits
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.9
2.10
Drain to Source Current 1^ versus Voltage V^ Relationships
2.1.1 The nonsaturated region
2.1.2 The saturated region
Aspects of Threshold Voltage V
t
Transistor Transconductance g
m
~
Figure of Merit (0
o
The Pass Transistor
The nMOS Inverter
Determination of Pull-up to Pull-down Ratio (
z
p.u./
z
p.d.) for an
Inverter Driven by another Inverter
Pull-up to Pull-down Ratio for an Inverter Driven through One or
More Pass Transistors
Alternative Forms of Pull-up
nMOS Circuit Model
Exercise 1
nMOS Circuit Design Processes
3.1 nMOS Layers
3.2 Stick Diagrams
3.3 nMOS Design Rules and Layout
3.4 Contact Cuts
3.4.1 Double metal nMOS process rules
3.5 General Observations on Design Rules
3.6 Layout Diagrams
1
1
4
4
7
8
9
13
14
15
16
17
19
20
21
21
23
25
28
31
31
32
32
33
35
39
42
42
in
iv Contents
Exercise 2 43
Tutorial 1 45
Chapter 4 Basic Circuit Concepts
4.1 Sheet Resistance R
s
46
4.2 Sheet Resistance Concept Applied to nMOS Transistors and
Inverters 47
4.3 Layer Capacitances * 49
4.4 Standard Unit of Capacitance nC
g
50
4.5 Some Capacitance Calculations 51
4.6 The Delay Unit x 53
4.7 Inverter Delays 54
4.8 Super Buffers 55
4.9 Driving Large Capacitive Loads 56
4.10 Propagation Delays in Cascaded Pass Transistors 58
4.11 Wiring Capacitances 59
4.12 Choice of Layers ' 60
Exercise 3 62
Chapter 5 Subsystem Design and Layout
5.1 Some Architectural Issues 64
5.2 Switch Logic 66
5.3 Gate Logic 68
5.3.1 The inverter 68
5.3.2 Two input Nand gate 69
5.3.3 Two input Nor gate 73
5.4 Examples of Structured Design (Combinational Logic) 73
5.4.1 A parity generator 73
5.4.2 Bus arbitration logic for n line bus 76
5.4.3 Multiplexers (data selectors) 80
5.4.4 The red-green (polysilicon-diffusion) function block 83
5.4.5 A general logic function block 86
5.5 Some Clocked Sequential Circuits - 86
5.5.1 Two-phase clocking 86
5.5.2 Charge storage 87
. 5.5.3 A dynamic register element 89
5.5.4 A dynamic shift register 89
5.5.5 A ratioless dynamic shift register 90
5.6 Other System Considerations 93
5.6.1 The precharged bus concept 93
5.6.2 Current limitations for V
DD
and GND(V
5
s) rails 95
, Tutorial 2 96
e
Chapter 6 Scaling of nMOS Circuits
6.1 Scaling Factor a 99
6.2 Some Functional Limitations to Scaling 100
I 6.3 Scaling of Wires and Interconnections 105
6.4 Some Aspects of Fabrication 106
Chapter 7 PLAs and Finite State Machines
7.1 Some Thoughts on Combinational Logic 108
:
Contents v
7.2 Some Alternatives to Simple Combinational Logic 108
7.2.1 Read only memory (ROM) or programmable read only
memory (PROM) realizations of combinational logic 110
7.2.2 Multiplexer-based realization of combinational logic 110
7.3 The Programmable Logic Array (PLA) . 110
7.4 Finite State Machines 116
7.4.1 A PLA-based finite state machine design example 118
Specification __ 118
Procedure . 118
Some cautionary remarks 121
PLA realization of the example 123
Exercise 4 123
Tutorial 3 125
Chapter 8 Aspects of System Design .
8.1 Some General Considerations 127
8.1.1 Some problems 128
8.2 An Illustration of Design Processes 128
8.2.1 The general arrangement of a 4-bit arithmetic processor 128
8.2.2 The design of a 4-bit shifter 130
8.3 Summary of Design Processes 134
Chapter 9 Further Consideration and Illustration of the Design Process
9.1 Some Observations on the Design Process 138
9:2 Regularity 138
9.3 Design of an ALU Subsystem , 139
9.3.1 Design of a 4-bit adder 140
Adder element requirements 141
v A standard adder element ' 142
Standard cells required for adder element 143
Adder element bounding box 145
9.3.2 Implementing ALU functions with an adder 148
Exercise 5 154
Tutorial 4 154
Chapter 10 Memory and Registers and Aspects of System Timing
10.1 System Timing Considerations 155
10.2 Some Commonly Used Storage/Memory Elements 156
10.2.1. The dynamic shift register stage 156
10.2.2 A modified lower power dynamic register element 157
10.2.3 A three-transistor dynamic RAM cell 159
10.2.4 A one-transistor dynamic memory cell 160
'
p
10.2.5 A pseudo-static RAM/register cell 162.
10.2.6 A JK Flip-Flop circuit 168
Logic gate implementations 171
Switch logic and inverter implementation 171
Comparison of implementations 171
10.2.7 A D Flip-Flop circuit 173
10.3 Forming Arrays of Memory Cells 173
10.3.1 Selection of cells or groups of cells 174
10.3.2 Building up the floorplan for a 4 X 4-bit register array 174
10.3.3 Selection and control of the 4 X 4-bit register array 176
10.3.4 Random access memory (RAM) arrays 184
vi Contents
I
Appendixes
Exercise 6 188
Tutorial5 188
Chapter 11 Practical Realities and Ground Rules
11.1 Some Thoughts on Performance 189
11.2 Further Thoughts on Floorplans/Layout 190
11.3 Floorplan Layout of the 4-bit Processor 194
11.3.1 Some realities * 198
11.4 Input/Output (I/O) Pads 198
11.5 "Real Estate" 201
11.6 Further Thoughts on System Delays 205
11.6.1 Buses 205
11.6.2 Control paths, selectors, and decoders 205
11.6.3 Use of an asymmetric two-phase clock 208
11.6.4 More nasty realities 208
11.7 Ground Rules for Successful Design 209
Chapter 12 The Real World of VLSI Design
12.1 Design Styles and Philosophy 220
12.2 The Interface with the Fabrication House 222
12.2.1 CIF (Caltech. Intermediate Form) Code 222
12.3 CAD Tools for Design and Simulation 225
12.3.1 A basic textual entry layout language 226
Design process using BELLE 226
Design examples using BELLE 227
12.3.2 A symbolic textual entry layout language and virtual
grid-based design 232
The ABCD language 233
Brief notes on ABCD 233
12.3.3 Graphical entry layout 237
12.4 Design Verification Prior to Fabrication 248
12.4.1 Design rule checkers (DRC) 248
12.4.2 Circuit extractors - 248
12.4.3 Simulators 249
Channel length modulation 249
Velocity saturation 250
12.5 Test and Testability 250
12.5.1 System partitioning 250
12.5.2 Layout and testability 251
12.5.3 Reset/initialization 251
12.5.4 Design for testability 251
12.5.5 Notes on test and testability 252
Ad hoc testability 252
Structured testability 252
Self-test circuitry . 253
Built-in logic block observation (BILBO) 254
12.6 VLSI Design The Final Ingredients 256
A1 BELLE Definitions 257
A2 Notes on PASCAL 262
A3 Parameterized Design Using BELLE 265
Contents
v
"
A4 Symbolic Design Description Language ABCD 267
B HMOS, Native Transistors, and Super Buffers 281
C Color Diagrams (Stick and Layout) for Examples from the Text and
Appendix B 285
Bibliography for General Reading 303
Index 305