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2004 Microchip Technology Incorporated. All Rights Reserved. Introduction to the dsPIC30F Architecture (Part 2) 1
DS
Digital Signal Controller
Introduction to the dsPIC30F
Architecture (Part 2 of 2)
Microchip Technology Inc.
Welcome to the third dsPIC30F web seminar: Introduction to the
dsPIC30F Architecture, Part 2. The focus in todays seminar will be on
various features related to device system integration, which will be
followed by an overview of Program Flash Memory and Data EEPROM.
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2004 Microchip Technology Incorporated. All Rights Reserved. Introduction to the dsPIC30F Architecture (Part 2) 2
System Integration Features
Let us start todays session by looking at some useful features provided
by the dsPIC30Fs System Integration hardware. First we will take a
look at how the dsPIC30F handles interrupts, traps and resets. Then we
will look at methods of clock generation, ways of saving power, and
features that increase system robustness and security.
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2004 Microchip Technology Incorporated. All Rights Reserved. Introduction to the dsPIC30F Architecture (Part 2) 3
Interrupts
l Prioritized, vectored interrupts
l Up to 45 sources (excluding traps and
reset)
l 7 levels of priority
l Fixed latency : 5 cycles (from IRQ to
ISR entry)
l PC and lower byte of Status Register
saved
The dsPIC30F has an efficient and robust interrupt system that works in
tandem with buffered peripheral events to minimize CPU time spent
handling interrupts.
Depending on the variant, the dsPIC30F can respond to up to 45
individual interrupt sources, excluding traps and reset. Each individual
interrupt is assigned to one of seven priority levels. Within each level,
the lower the interrupt vector number, the higher its relative priority.
Interrupt latency time is fixed at 5 cycles, from the latching of the
interrupt request to the start of interrupt service routine, or ISR,
processing. This deterministic and consistent interrupt latency is very
crucial for applications with real-time response requirements, such as
when processing streaming audio signals.
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2004 Microchip Technology Incorporated. All Rights Reserved. Introduction to the dsPIC30F Architecture (Part 2) 4
Interrupts
l Interrupt stack built in on-chip SRAM
with automatic bounds checking
l Nesting of Interrupts - Higher priority
interrupts can interrupt lower priority
interrupts
l DISI instruction suspends interrupts for
N cycles
l Quick way to protect critical code
segments
l Priority 0 6 interrupts disabled
When an interrupt occurs, some basic processor context is
automatically saved on to the software stack. Similarly, the context data
is automatically restored when code execution returns from the
interrupt.
Interrupts may optionally be nested, that is, a higher priority interrupt
may occur and be serviced while a lower priority interrupt is being
serviced.
A novel feature of the dsPIC30F is the DISI instruction. This command
temporarily suspends processing of all interrupts up to level 6, for a
user-programmable number of instruction cycles. This is a quick and
easy way to protect critical code sequences or operating system
resources.
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2004 Microchip Technology Incorporated. All Rights Reserved. Introduction to the dsPIC30F Architecture (Part 2) 5
Traps
l Oscillator Failure Trap:
l Main clock failure (switches to Internal RC)
l Address Error Trap:
l Unimplemented data space access
l Any access of unimplemented program space
l Misaligned data read or write
l Stack Error Trap:
l Programmable overflow limit register
l Hardwired underflow limit to protect SFRs
l Math Error Trap:
l Divide by Zero
l Unsaturated Accumulator Overflow
Traps, also known as processor exceptions, help guard against
unexpected events. They are processed similar to interrupts, with the
application code including Trap Service Routines to handle such events
and take corrective action. In the dsPIC30F, there are 4 types of events
that generate traps, each with a unique trap vector with a fixed vector
processing priority.
An oscillator failure, typically due to a fault in the external system,
causes the dsPIC30F to switch to a back-up clock source inside the
chip, before processing the exception.
Address Error Traps guard against invalid data accesses, such as a
data read or write of unimplemented data space, or a misaligned data
read or write. It also guards against invalid program memory accesses,
such as trying to execute out of unimplemented program space or the
interrupt vector table.
When the stack pointer grows beyond the user-specified Stack Pointer
Limit, a Stack Error Trap occurs. A Stack Error Trap is also generated if
the stack underflows into the region of data memory reserved for
special function registers.
In general, there are 2 types of events that cause math errors: divide by
zero and unsaturated accumulator overflow. The former occurs when
the CPU detects that the divisor used in a divide instruction equals zero.
The latter occurs if either of the two 40-bit accumulators overflows into
either bit 31 or bit 39. This provides a mechanism to detect and correct
overflows without loss of data when saturation is not being used.
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2004 Microchip Technology Incorporated. All Rights Reserved. Introduction to the dsPIC30F Architecture (Part 2) 6
System Resets
l Power-On Reset (POR):
l Programmable delay timer: 0, 4, 16, 64ms
l MCLR (External Reset Pin)
l Reset Instruction execution
l Watchdog Timer (WDT) Reset:
l Runs from its own RC oscillator
l Programmable timeout: 2 ms - 16 sec
l Brown-out Reset (BOR):
l Programmable voltage levels
l Illegal Program Operation Reset:
l Illegal Opcode fetch
l Uninitialized W register used as an address pointer
The dsPIC30F can be reset for several different reasons. Shown here is
a complete list of such events:
Power-On Reset, or POR, is the standard reset that occurs when the
supply voltage to the device is turned on. This has been enhanced by
the dsPIC30F with the addition of a user programmable delay. This
delay provides some time for external crystals with slow rise times to
start operation before the CPU starts executing instructions.
If needed, the user can force a device reset in one of two ways, either
by pulling the external Master Clear pin low, or by executing the RESET
instruction in software.
The dsPIC30F devices contain an on-chip Watchdog Timer to improve
system robustness. The Watchdog Timer runs from an internal RC
oscillator source, and which is independent of system clock operation.
The programmable time-out ranges from 2 milliseconds to 16 seconds,
providing a wide response time range for the user to clear the timer.
Failure to respond within this time period results in a device reset.
The Brown-Out Reset, or BOR, occurs when the supply voltage drops
below a user-programmable voltage threshold. This prevents glitches in
the power-line from adversely affecting system operation.
Illegal program operations can also reset the device. These include an
attempt to fetch an illegal opcode or an attempt to use an uninitialized
W register as an address pointer in an instruction.
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Clock Sources
XTL, XT, HS
Primary
Xtal OSC
Clock Divide
By
1, 4, 16, 64
32KHz
Timer1 Xtal
OSC
System
Clock
Fast RC 8.0 MHz
Low Pwr RC 512KHz
EC Clock
SOSCI
SOSCO
OSC1
OSC2
PLL
4x,
8x,
16x
or bypass
l Primary Oscillator for Crystals
l 32 kHz for Real Time Clock
l 2 internal RC oscillators
l PLL multiplies oscillator source for
high frequency operation
l Clock divide can optionally slow
clock to conserve power
The dsPIC30F has a very flexible set of oscillator sources to generate the
system clock. Each instruction cycle consists of 4 system clock cycles. For
example, a 120 MHz system clock would result in a 30 MHz instruction clock,
or approximately 30 MIPS performance.
The system clock may be obtained from a variety of internal or external
sources. An external crystal oscillator is a popular clock source option. This
may be further categorized into three frequency ranges, called XTL, XT, and
HS. Alternatively, one could directly use an external clock signal. Internal
sources provided on the dsPIC30F include an 8 Megahertz Fast RC oscillator
and a 512 kilohertz Low Power RC oscillator.
There is also a secondary 32 kHz low power crystal oscillator input which can
be used to provide the time base for the Timer1 counter, thereby using Timer1
as a Real Time Clock. This clock source can also be used as the system clock
source to minimize power consumption.
In order to get the maximum performance out of the dsPIC30F, the output of
an XT crystal, an external clock signal or the output of the Fast RC Oscillator,
can be applied to an on chip Phase Locked Loop, or PLL. This input signal, in
the 4 MHz to 10 MHz range is then multiplied by 4, 8, or 16 to achieve a
system clock frequency between 16 and 120 MHz. Using the Fast RC
oscillator with the PLL provides a means to generate high clock frequencies
without using external system components like crystals and resonators.
The dsPIC30F oscillator system also provides a method of conserving power
by temporarily slowing down the system clock, using a user-programmable
clock post-scaler which divides the clock frequency by 4, 16, or 64.
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Power Management
l Execute the PWRSAV Instruction:
l IDLE mode:
l CPU is stopped, but the system clock continues to run
l Peripherals continue to run (unless disabled)
l Wake up: WDT, change notification pin, interrupt,
Reset
l SLEEP mode:
l CPU and system clock are stopped
l Peripherals are stopped, unless clocked externally
l Wake up: WDT, change notification pin, external
interrupt pin, Reset, or certain peripheral events
An important requirement of many embedded applications is the need to
conserve energy. The dsPIC30F provides several mechanisms to lower its
power consumption.
Depending on your application, you may be able to use the Power Save
instruction to obtain the most reduction in energy consumption. Executing this
instruction can put the device in one of two states:
Idle Mode halts the CPU, thereby stopping bus activity and data transfers.
The system clock and peripherals continue running so that an interrupt can
be used to restart CPU operation. Additionally, each peripheral can be
individually configured to stop operation during Idle mode.
Sleep Mode places the device in the lowest power consumption state. In this
state, the CPU as well as the system clock are halted. A few peripherals may
optionally continue to run during Sleep Mode. These peripherals include
serial communication modules that can operate in a clock slave mode, or
peripherals that can generate their own clock. Some I/O pins, if enabled, can
asynchronously wake up the CPU on a change in input.
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Power Management
l Use the System Clock Postscaler: 1, 4,
16, 64
l Reduce the PLL Multiplier, e.g. from x16
to x8
l Switch to a slower clock source: FRC,
LPRC, LP, EC
As current consumption bears a direct relation to processor speed, reducing
the speed of operation is a very effective way of reducing overall power
consumption. This can be accomplished either by postscaling the system
clock by 4, 16, or 64, or by reducing the PLL multiplier.
It is also possible to switch to a slower clock source at run time. During any
clock switch, the dsPIC30F monitors the new clock source to ensure a
successful clock switch. If the new clock source fails to start up, the device
will continue operation using the original clock source.
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2004 Microchip Technology Incorporated. All Rights Reserved. Introduction to the dsPIC30F Architecture (Part 2) 10
Fail-Safe Operation
l Clock monitor with automatic switch to an internal
clock
l Watchdog Timer with its own RC Osc and fuse
protection
l Resets
l Traps
l Programmable Low Voltage Detect (LVD) Interrupt
l Program Memory Read and Write Protection
Sometimes the best offense is a good defense, and the dsPIC30F provides an array of
defensive techniques to protect your application.
A key element ensuring robust operation is a clock monitor that keeps an eye on the
primary clock source. Should the system clock fails, the clock monitor can automatically
switch operation to the low power internal Fast RC Oscillator and notify the CPU.
A Watchdog Timer helps detect errant software operation. It runs from the Low Power
RC oscillator, so that even applications which do not use the clock monitor can be
protected.
Resets prevent catastrophic events from adversely affecting system operation. The
dsPIC30F resets itself upon a watch dog timer timeout, a dip in the power supply, or an
unrecoverable program addressing error. In addition, the cause of the most recent
system reset is saved in a status register and can be accessed by user code.
Traps allow recovery from processor exceptions by interrupting the CPU and executing
user-programmed Trap Service Routines. Several abnormal conditions can cause traps,
including oscillator failure, data addressing errors, stack errors, and math errors.
The Low Voltage Detect, or LVD, provides a convenient means of monitoring supply
voltage level in an application. This is particularly useful for battery-powered systems. It
may be configured to generate an interrupt, which provides the application sufficient time
to save data and perform a clean shutdown before the falling battery level causes a
potential system failure.
Finally, the Flashprogram memory can be read-protected to prevent unauthorized
access of proprietary code, or write-protected to prevent accidental or malicious
modification of program memory contents.
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2004 Microchip Technology Incorporated. All Rights Reserved. Introduction to the dsPIC30F Architecture (Part 2) 11
Program Flash and
Data EEPROM
The final section of this presentation briefly describes the on-chip Flash
Program Memory and Data EEPROM of the dsPIC30F.
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2004 Microchip Technology Incorporated. All Rights Reserved. Introduction to the dsPIC30F Architecture (Part 2) 12
Flash Performance Summary
l All dsPIC

devices are Flash-based

l PMOS Electrically Erasable Cell (PEEC) Flash
l High reliability
l Endurance up to 1M E/W Cycles
l Data retention >40+ years
l Flexible operation
l Fast programming times for program memory
l Self-programmable
Microchip is a leader in Flash memory manufacturing. For over 15
years, Microchip has been producing MCUs with integrated Flash
memory.
The key to Microchips Flash technology success is our proprietary
PEEC Flash cell, produced in both 0.5 and 0.4 micron technologies. On
the dsPIC30F, both Program Flashand data EEPROM memories are
constructed using the same PEEC Flash cell.
The Flash memory in the dsPIC30F devices provide a high level of
reliability, with a Flash cell endurance of well over one million
program/erase cycles at 85 degrees Centigrade, and data retention
exceeding 20 years. This, in turn, helps ensure reliable operation of
user applications.
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2004 Microchip Technology Incorporated. All Rights Reserved. Introduction to the dsPIC30F Architecture (Part 2) 13
l Device is soldered in the system
l Programming is done using:
l 2 data/clock pins + Reset pin forced high
l Ideal for programming, testing and field upgrades
l All dsPIC

devices support ICSP capability

l Programming time: ~18 seconds for 144kbytes
In-Circuit Serial Programming
(ICSP)
The dsPIC30F allows users to modify the on-chip Program Flash
Memory and Data EEPROM using a serial interface. This supports
erasing and reprogramming of a device either in a stand-alone device
programmer or in-circuit with the device embedded in an application
circuit board.
The serial interface requires access to only three device pins:
programming data or PGD, programming clock or PGC, and Master
Clear or MCLR. Power and ground may optionally be supplied.
A two-step process is used to program the device. First, the dsPIC30F
device is reset into the Standard Device-Under-Test Programming or
SDTP mode. In this mode, a Programming Executive software is
programmed into a special section of Flash memory. The dsPIC30F
device is then reset into the In-Circuit Serial Programmingor ICSP
mode, which uses the Programming Executive to efficiently program the
Program FlashMemory, Data EEPROM and Device Configuration
Registers.
Microchips Promate

II and PM3 device programmers, and the low-

cost MPLAB

In-Circuit Debugger 2, ICD2, support programming of

dsPIC30F devices using the ICSP methodology. Using ICSP, the
largest-memory dsPIC30F devices can be programmed in about 18
seconds.
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2004 Microchip Technology Incorporated. All Rights Reserved. Introduction to the dsPIC30F Architecture (Part 2) 14
Run-Time Self Programming
(RTSP)
l Run Time Self Programming OR Self Programming
l Device can program its own Flash memory
l Programs a block of 96 bytes at a time in ~ 2ms
l Ideal for system calibration or parameterization
l Ideal for Remote code update, e.g. in a Boot Loader
l All dsPIC

devices support RTSP

Another method of modifying the Program Flash Memory and Data
EEPROM is called Run-Time Self-Programming, or RTSP. This
technique allows the dsPIC30F to reprogram itself during program
execution, without external tools or serial interface connections.
Using RTSP, the dsPIC30F can erase and reprogram a block of
program memory while executing from a different address in Program
Flash Memory. There is a two millisecond CPU stall during the
operation, but the peripherals continue operating normally. Data
EEPROM may also be erased and reprogrammed using RTSP, but this
does not incur any CPU stall.
This method provides the capability for applications to update the data
EEPROM or to modify the code in Program Flash Memory at run-time.
This is ideal for applications requiring remote code updates or updates
of calibration data. RTSP is also useful for Boot Loaders.
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2004 Microchip Technology Incorporated. All Rights Reserved. Introduction to the dsPIC30F Architecture (Part 2) 15
l Up to 4K bytes Data EE Memory
l Run-Time programmable
l Row and Word erasable
l Row and Word programmable
l Modify a Row of 16 words in 2 milliseconds
l Can access Data EEPROM for 16-bit data read
operations
MOV [++w4], [w6++]
Data EE Memory used as source address for data read operation
Data EEPROM Memory
Besides Program Flash Memory, the dsPIC30F contains up to 4
kilobytes of Data EEPROM. This is useful for storing start-up calibration
constants or constant data. It can also be used to store diagnostic data
for application debugging purposes.
The Data EEPROM is located in a separate region of Program Space
from user Program FlashMemory, and allows erasing and
programming of data to occur without halting CPU instruction execution.
For improved flexibility, the dsPIC30F devices data EEPROM is not
only row erasable and row programmable, but is also word erasable
and word programmable. One row of Data EEPROM, which consists of
16 words of 16-bit data, can be erased and reprogrammed in 2
milliseconds.
The instruction example shown here demonstrates the access of a
constant stored in Data EEPROM using a simple Move instruction.
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2004 Microchip Technology Incorporated. All Rights Reserved. Introduction to the dsPIC30F Architecture (Part 2) 16
Device Selection Reference Document #
l General Purpose and Sensor Family Data Sheet DS70083
l Motor Control and Power Conv. Data Sheet DS70082
l dsPIC30F Family Overview DS70043
Base Design Reference Document #
l dsPIC30F Family Reference Manual DS70046
l dsPIC30F Programmers Reference Manual DS70030
l MPLAB

C30 C Compiler Users Guide DS51284

l MPLAB ASM30, LINK30 & Utilities Users Guide DS51317
l dsPIC

Language Tools Libraries Users Guide DS51456

Key Support Documents
For more information, here are references to some important
documents that contain a wealth of information about the dsPIC30F
family of devices.
The Family Reference Manual contains detailed information about the
architecture and peripherals, whereas the Programmers Reference
Manual contains a thorough description of the instruction set.
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2004 Microchip Technology Incorporated. All Rights Reserved. Introduction to the dsPIC30F Architecture (Part 2) 17
Device Specific Reference Document #
l dsPIC30F2010 Data Sheet DS70118
l dsPIC30F2011/2012/3012/3013 Data Sheet DS70139
l dsPIC30F3014/4013 Data Sheet DS70138
l dsPIC30F4011/4012 Data Sheet DS70135
l dsPIC30F5011/5013 Data Sheet DS70116
l dsPIC30F6010 Data Sheet DS70119
l dsPIC30F6011/12/13/14 Data Sheet DS70117
Microchip Web Site: www.microchip.com
Key Support Documents
For device-specific information such as pinout diagrams, packaging and
electrical characteristics, the device datasheets listed here are the best
source of information.
All these documents can be obtained from the Microchip web site
shown, by clicking on the dsPIC

Digital Signal Controllers or

Technical Documentation link.