CREATING A PROJECT IN MODELSIM APPLICATION FOR WRITING A VHDL

PROGRAM

1. Click the icon on the desktop

2. The Model Sim software opens and In the File Menu  Select New  Project

3. New Project Dialog box appears

4. Enter the Project name in the project Name dialog box. And select the project
location to be stored.
5. On Clicking Ok. Add items to project dialog box opens. Click New File

6. Create Project File dialog box appears. Enter the project file as the entity
name that is used in the VHD program
7. Create Project File dialog box appears. Enter the project file as the entity
name that is used in the VHD program
8. Double click the file in the workspace tab (or) right click and click Edit.

9. The following window appears.

10.Enter the VHD code in the opened editor and save
11.Click compile to compile the typed program.
12.On completion of compilation the compilation status window appears as
shown below
13.DOUBLE CLICK ON THE ERROR AND CORRECT THE ERRORS ON SUCCESSFUL
COMPILATION THE WINDOW APPEARS AS SHOWN BELOW.

14.Go to Library tab and expand the Work Entity  Architecture.

15.Right Click and click simulate.

16.Right Click and click simulate and in view menu select the signal and wave
windows

17.The signal window and wave window appears as shown below

18.Select all the input and outputs and right click to add to wave form (or) drag
to the wave form
19.The wave form appears as shown below
20.Select the input and click Edit Menu and select Force
21.The input force window appears as shown below.
22.Change the Value to zero or 1 and Click Ok.

23.Click the Run button in the Wave window

24.Click Run will update the wave form page
 LOGIC GATES
Ex No: 1

Date: 18 – JULY-2010

AIM:

To implement the logic gates using the data flow model

VHDL PROGRAM:

AND GATE
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY AND_GATE IS
PORT(A,B:IN STD_LOGIC;X :OUT STD_LOGIC);
END AND_GATE;
ARCHITECTURE LOGIC_GATES OF AND_GATE IS
BEGIN
X <= A AND B;
END LOGIC_GATES;

OR GATE
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY OR_GATE IS
PORT(C,D:IN STD_LOGIC;Y :OUT STD_LOGIC);
END OR_GATE;
ARCHITECTURE LOGIC_GATES OF OR_GATE IS
BEGIN
Y <= C OR D;
END LOGIC_GATES;

NOT GATE
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY NOT_GATE IS
PORT(E:IN STD_LOGIC;Z :OUT STD_LOGIC);
END NOT_GATE;
ARCHITECTURE LOGIC_GATES OF NOT_GATE IS
BEGIN
Z <= NOT E;
END LOGIC_GATES;

XOR GATE
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY XOR_GATE IS
PORT(F,G:IN STD_LOGIC;W :OUT STD_LOGIC);
END XOR_GATE;
ARCHITECTURE LOGIC_GATES OF XOR_GATE IS
BEGIN
W <= F XOR G;
END LOGIC_GATES;

NOR GATE
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY NOR_GATE IS
PORT(H,I:IN STD_LOGIC;S:OUT STD_LOGIC);
END NOR_GATE;
ARCHITECTURE LOGIC_GATES OF NOR_GATE IS
BEGIN
S <= H NOR I;
END LOGIC_GATES;
OUTPUT:

AND GATE

INPUT OUTPUT
A B X
0 0 0
0 1 0
1 0 0
1 1 1

OR GATE

INPUT OUTPUT
C D y
0 0 0
0 1 1
1 0 1
1 1 1
NOT GATE

INPUT OUTPUT
E Z
0 1
1 0

XOR GATE

INPUT OUTPUT
F G W
0 0 0
0 1 1
1 0 1
1 1 0
NOR GATE

INPUT OUTPUT
F G W
0 0 1
0 1 0
1 0 0
1 1 0

RESULT:

The VHDL program for the LOGIC GATES is implemented.

 BINARY TO GRAY CONVERTOR
Ex No: 2

Date:25- JULY -2010

AIM:

To implement the VHDL program for Binary to Gray Convertor

VHDL PROGRAM:

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY BTOG_D_F IS
PORT(B:IN STD_LOGIC_VECTOR(0 TO 3);G:OUT STD_LOGIC_VECTOR(0 TO 3));
END BTOG_D_F;
ARCHITECTURE BTOG_D_F_ARCH OF BTOG_D_F IS
BEGIN
G(0)<=B(0);
G(1)<=B(0) XOR B(1);
G(2)<=B(1) XOR B(2);
G(3)<=B(2) XOR B(3);
END BTOG_D_F_ARCH;

CIRCUIT DIAGRAM:-
OUTPUT

INPUT OUTPUT
B0 B1 B2 B3 G0 G1 G2 G3
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 0 0 0 1 1
0 0 1 1 0 0 1 0
0 1 0 0 0 1 1 0
0 1 0 1 0 1 1 1
0 1 1 0 0 1 0 1
0 1 1 1 0 1 0 0
1 0 0 0 1 1 0 0
1 0 0 1 1 1 0 1
1 0 1 0 1 1 1 1
1 0 1 1 1 1 1 0
1 1 0 0 1 0 1 0
1 1 0 1 1 0 1 1
1 1 1 0 1 0 0 1
1 1 1 1 1 0 0 0

RESULT:

The VHDL program for the Binary to Gray is implemented.

 GRAY TO BINARY CONVERTOR
Ex No: 3

Date:01 – AUG -2010

AIM:

To implement binary to gray convertor in VHDL program.

VHDL PROGRAM:

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY GTOB_D_F IS
PORT(G:IN STD_LOGIC_VECTOR(0 TO 3);B:INOUT STD_LOGIC_VECTOR(0 TO 3));
END GTOB_D_F;
ARCHITECTURE GTOB_D_F_ARCH OF GTOB_D_F IS
BEGIN
B(0)<=G(0);
B(1)<=G(0) XOR G(1);
B(2)<=G(2) XOR B(1);
B(3)<=G(3) XOR B(2);
END GTOB_D_F_ARCH;

CIRCUIT DIAGRAM:-
OUTPUT

INPUT OUTPUT
G0 G1 G2 G3 B0 B1 B2 B3
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 0 0 0 1 1
0 0 1 1 0 0 1 0
0 1 0 0 0 1 1 1
0 1 0 1 0 1 1 0
0 1 1 0 0 1 0 0
0 1 1 1 0 1 0 1
1 0 0 0 1 1 1 1
1 0 0 1 1 1 1 0
1 0 1 0 1 1 0 0
1 0 1 1 1 1 0 1
1 1 0 0 1 0 0 0
1 1 0 1 1 0 0 1
1 1 1 0 1 0 1 1
1 1 1 1 1 0 1 0

RESULT:

The VHDL program for the Gray to Binary is implemented.

 HALF SUBTRACTOR
Ex No: 4

Date: 8 – AUG -2010

AIM:

To implement a Half Subtractor using the data flow model

VHDL PROGRAM:

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY HALF_SUBTRACTOR IS
PORT(A,B :IN STD_LOGIC;X,Y:OUT STD_LOGIC);
END HALF_SUBTRACTOR;
ARCHITECTURE ARCH_HALF_SUBTRACTOR OF HALF_SUBTRACTOR IS
BEGIN
X<=(A XOR B);
Y<=(A AND (NOT B));
END ARCH_HALF_SUBTRACTOR;
CIRCUIT DIAGRAM:-
OUTPUT:

INPUT OUTPUT
A B X Y
0 0 0 0
0 1 1 0
1 0 1 1
1 1 0 0

RESULT:

The VHDL program for the half Subtractor is implemented.

 FULL SUBTRACTOR
Ex No: 5

Date: 15- AUG - 2010

AIM:

To implement a Full Subtractor using the data flow model

VHDL Program:

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY FULL_SUB IS
PORT(A,B,C:IN STD_LOGIC;DIFF,BOR:OUT STD_LOGIC);
END FULL_SUB;
ARCHITECTURE FS_A OF FULL_SUB IS
BEGIN
DIFF<=((A XOR B)XOR C);
BOR<=((NOT A)AND B)OR(NOT(A XOR B)AND C);
END FS_A;

Circuit Diagram:-
OUTPUT:

INPUT OUTPUT
A B C DIFF BOR
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1

RESULT:

The VHDL program for the FULL Subtractor is implemented.

 HALF ADDER
Ex No: 6

Date: 22- AUG - 2010

AIM:

To implement a half Adder using the data flow model

VHDL PROGRAM:

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY HALFADDER IS
PORT (A,B:IN STD_LOGIC;X,Y:OUT STD_LOGIC);
END HALFADDER;
ARCHITECTURE HALF_ADD OF HALFADDER IS
BEGIN
X<= (A XOR B);
Y<= (A AND B);
END HALF_ADD;

CIRCUIT DIAGRAM:
OUTPUT:

INPUT OUTPUT
A B S C
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1

RESULT:

The VHDL program for the half adder is implemented.

 FULL ADDER
Ex No: 7

Date: 29 – AUG - 2010

AIM:

To implement a Full Adder using the data flow model

VHDL PROGRAM:

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY FULL_ADDER IS
PORT(A,B,C:IN STD_LOGIC;X,Y :OUT STD_LOGIC);
END FULL_ADDER;
ARCHITECTURE FULL_ADDER_ARCH OF FULL_ADDER IS
BEGIN
X<=(C XOR (A XOR B));
Y<=(((A XOR B) AND C) OR (A AND B));
END FULL_ADDER_ARCH;
OUTPUT:

INPUT OUTPUT
A B C X Y
0 0 0 0 0
0 1 0 1 0
1 0 0 1 0
1 1 0 0 1
0 0 1 1 0
0 1 1 0 1
1 0 1 0 1
1 1 1 1 1

RESULT:

The VHDL program for the full adder is implemented.

 PARITY GENERATOR
Ex No: 8

Date: 05 – SEP – 2010

AIM:

To implement PARITY GENERATOR using the data flow model

VHDL PROGRAM:

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY PARITY_GEN_D_F IS
PORT(D:IN STD_LOGIC_VECTOR(0 TO 8); E:INOUT STD_LOGIC_VECTOR(0 TO 3); F:
INOUT STD_LOGIC_VECTOR(0 TO 1);H: INOUT STD_LOGIC;ODD: OUT STD_LOGIC;
EVEN:OUT STD_LOGIC);
END PARITY_GEN_D_F;
ARCHITECTURE PARITY_GEN_D_F_ARCH OF PARITY_GEN_D_F IS
BEGIN
E(0) <= (D(0) XOR D(1));
E(1) <= D(2) XOR D(3);
E(2) <= D(4) XOR D(5);
E(3) <= D(6) XOR D(7);
F(0) <= E(0) XOR E(1);
F(1) <= E(2) XOR E(3);
H <= (F(0) XOR F(1));
EVEN <= NOT(H XOR D(8));
ODD <= H XOR D(8);
END PARITY_GEN_D_F_ARCH;
OUTPUT:

INPUT OUTPUT
D ODD EVEN
000000000 0 1
000000001 0 1
000000010 0 1
000000011 1 0
001000011 0 1
101000011 1 0

RESULT:

The VHDL program for the parity generator is implemented.

 2 BIT COMPARITOR
Ex No: 9

Date: 12 – SEP - 2010

AIM:

To implement 2 BIT COMPARITOR using the data flow model

VHDL PROGRAM:

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY BIT2_CMP IS
PORT(A,B:IN STD_LOGIC_VECTOR(1 DOWNTO 0);
GREAT,LESS,EQU:OUT STD_LOGIC);
END BIT2_CMP;
ARCHITECTURE BIT4_CMP_A OF BIT2_CMP IS
SIGNAL X1,X2,X3,X4:STD_LOGIC;
BEGIN
X1<=((NOT A(0) AND NOT B(0)) OR (A(0) AND B(0)));
X2<=((NOT A(1) AND NOT B(1)) OR (A(1) AND B(1)));
GREAT<=((A(1) AND NOT B(1)) OR (X2 AND (A(0) AND NOT B(0))));
LESS <=((B(1) AND NOT A(1)) OR (X2 AND (B(0) AND NOT A(0))));
EQU <=(X1 AND X2 AND X3 AND X4);
END BIT4_CMP_A;
OUTPUT:

INPUT OUTPUT
B GREA EQU
A LESS
T
00 00 0 0 1
10 00 1 0 0
10 11 0 1 0

RESULT:

The VHDL program for the TWO BIT COMPARITOR is implemented.