SRC Ece 25
SRC Ece 25
SRC Ece 25
main divider; RFR is the radio frequency reference specifically the varying voltage at the pins of the
divider, these two values are stored in local registers variable capacitor ) In the simulation it is
inside the chip. considered to be a triangular signal buty any
periodic signal would lead to the same results.
c) Covering uplink/downlink The signal was given a triangular variation from
The noise signal with a low bandwidth is supplied to the 0 Æ 5v and a period of 0.2885 msec1.
IC, and for covering the whole range one of two options • The VCO which represents the oscillator formed
may be considered: by the varactor and an inductor, the range to be
a. Supplying a constant fREF for the max2364 from traversed by fREF is 285.9 KHz which
a simple oscillator system, while continuously corresponds to a 5v variation in the input signal
changing the contents of the RFM and RFR and thus a sensitivity of 57.11 KHz/volt. A
registers through a 3-wire control. Discrete-time VCO was used to allow the use of
b. Keeping the values of the previously mentioned the fast fourier transform to analyze the signal.
registers fixed, and supplying a continuously • The last part is the buffer and the FFT which
varying fREF through a circuit containing a help construct the frequency domain
voltage controlled oscillator (VCO) with a representation of the output signal achieved.
varactor, whose input voltage is a time varying
periodic signal which increases/decreases in a Results
manner such that the corresponding values of RF On Running the simulation, and observing the output of
traverse the whole Uplink/Downlink range. the scope, a signal whose carrier repeatedly moves from
10.6927 to 10.9786 MHz is observed ( In fact, this is an
d) Stopping Transmission FM signal with a varying carrier frequency).
The output of this circuit is the input to pin#36 of the IC
In order to insure minimum power consumption and
and we can see that the result is a signal at frequency RF
dissipation, while maintaining full efficiency of the
which moves on the range of 935 Æ 960 MHz and thus
scrambling system, the transmitter operation may be
covering the whole downlink.
stopped after making sure that no speech channel
establishment was possible.
5. Simulation
A Matlab/Simulink simulation to show the generation of
fREF was carried out to illustrate the behavior of the
oscillating generated signal. The block diagram modeling
the oscillator is shown next:
where :
• The repeating sequence block represents the 1
periodic input signal to the VCO ( more This value was calculated based on channel allocation time and
frequency hopping
4
6. Conclusion
The increased need for mobile scramblers makes it
vital that they integrate more features and provide more
control on the whole process. This paper discusses mobile
jamming technology, and introduces suggested
improvements on existing designs. It presents possible
approaches for a more intelligent design. The first
approach (Selective Jamming) was not implemented due
to hardware speed limitation, which may be overcome
with certain technologies. The proposed design achieves
lower power consumption, taking into consideration
health and cost issues.
Acknowledgment
We are very grateful to Professor Karim Kabalan who
provided us with helpful feedback. We also thank Mr. Joe
Samaha for his technical support. Special appreciation
Figure 3: varying frequency oscillator
goes to Elias Nahra and Najwa Hamzeh for helping us in
C6 is varied from 2 to 2.20891 pF to ensure the required getting the required circuit components.
frequency variation.