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GATE CS Topic wise Questions Digital Logic

YEAR 2001

Question. 1

Given the following Karnaugh map, which one of the following represents the minimal sum-of-Products of the map ?

(A) xy + y'z (C) w'x + y'z + xy

(B) wx'y' + xy + xz (D) xz + y

Question. 2

Consider the following circuit with initial state Q 0 = Q1 = 0 . The D flip-flops are positive edged triggered and have set up times 20 nanosecond and hold times 0.

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Consider the following timing diagrams of X and C ; the clock of C $ 40 nanosecond. Which one is the correct plot of Y

Question. 3

The 2s complement representation of ( 539) 10 is hexadecimal is (A) ABE (C) DE5

(B) DBC (D) 9E7

Consider the circuit shown below. The output of a 2:1 Mux is given by the function (ac' + bc).

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www.gatehelp.com Which of the following is true ? (A) f = x1' + x2 (C) f = x1x2 + x1'x2'
Question. 5

CS Topicwise 2001-2010 Digital Logic

(B) f = x1'x2 + x1x2' (D) f = x1 + x2

Consider the circuit given below the initial state Q 0 = 1, Q1 = Q2 = 0 . The state of the circuit is given by the value 4Q2 + 2Q1 + Q 0

Which one of the following is the correct state sequence of the circuit ? (A) 1, 3, 4, 6, 7, 5, 2 (B) 1, 2, 5, 3, 7, 6, 4 (C) 1, 2, 7, 3, 5, 6, 4 (D) 1, 6, 5, 7, 2, 3, 5

YEAR 2002 Question. 6

Minimum sum of product expression for f (w, x, y, z) shown in Karnaugh-map below is

(A) xz + y'z

(B) xz' + zx'

CS Topicwise 2001-2010 Digital Logic

www.gatehelp.com (C) x'y + zx'

(D) None of the above

The decimal value of 0.25 (A) is equivalent to the binary value 0.1 (B) is equivalent to the binary value 0.01 (C) is equivalent to the binary value 0.00111..... (D) cannot be represented precisely in binary.
Question. 8

The 2s complement represent representation of the decimal value 15 is (A) 1111 (C) 111111
Question. 9

(B) 11111 (D) 10001

Sign extension is a step in (A) floating point multiplication (B) signed 16 bit integer addition (C) arithmetic left shift (D) converting a signed integer from one size to another.
Question. 10

In 2s complement addition, overflow (A) Relational algebra is more powerful than relational calculus (B) Relational algebra has the same power as relational calculus. (C) Relational algebra has the same power as safe relational calculus. (D) None of the above.
Question. 11

Consider the following logic circuit whose inputs are functions f1, f2, f3 and output is f
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CS Topicwise 2001-2010 Digital Logic

Given that f1 (x, y, z) = (0, 1, 3, 5) f2 (x, y, z) = (6, 7), and f (x, y, z) = (1, 4, 5) f3 is (A) (1, 4, 5) (C) (0, 1, 3, 5)
Question. 12

(B) (6, 7) (D) None of the above

Consider the following multiplexor where 10, 11, 12, 13 are four data input lines selected by two address line combinations A1A0 = 00, 01, 10, 11 respectively and f is the output of the multiplexor. EN is the Enable input.

The function f (x, y, z) implemented by the above circuit is (A) xyz' (C) x + y
Question. 13

(B) xy + z (D) None of the above

Let f (A, B) = A' + B . Simplified expression for function f (f (x + y, y), z) is (A) x' + z (C) xy' + z (B) xyz (D) None of the above
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Question. 14

What are the states of the Auxiliary Carry (AC) and Carry Flag (CY) after executing the following 8085 program ? MIV H, MIV L, MOV A, ADD L (A) AC = 0 and CY = 0 (C) AC = 1 and CY = 0
Question. 15

5DH 6BH H (B) AC = 1 and CY = 1 (D) AC = 0 and CY = 1

The finite state machine described by the following state diagram with A as starting state, where an arc label is x and x stands for y 1-bit input and y stands for 2-bit output.

(A) Outputs the sum of the present and the previous bits of the input. (B) Outputs 01 whenever the input sequence contains 11 (C) Outputs 00 whenever the input sequence contains 10 (D) None of the above.

YEAR 2003

Question. 16

Assuming all numbers are in 2s complement representation, which of the following number is divisible by 11111011? (A) 11100111 (C) 11010111
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(B) 11100100 (D) 11011011

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Question. 17

CS Topicwise 2001-2010 Digital Logic

The following is a scheme for floating point number representation using 16 bits.

Let s, c and m be the number represented in binary in the sign, exponent, and mantissa fields respectively. Then the flouting point number represented id ( 1) 2 (1 + m # 2 9)2 e 31, if the exponent 111111 ) 0 otherwise What is the maximum difference between two successive real numbers representable in this system? (B) 2 9 (A) 2 40 (C) 222
Question. 18

(D) 231

A 1-input, 2-output synchronous sequential circuit behaves as follows. Let zk , nk denote the number of 0s and 1s respectively in initial k bits of the input (zk + nk = k). The circuit outputs 00 until one of the following conditions holds. 1. nk nk = 2 . In this case, the output at the k -th and all subsequency clock ticks is 10. 2. nk zk = 2 . In this case, the output at the k -th and all subsequent clock ticks is 01. What in the minimum number of states required in the state transition graph of the above circuit? (A) 5 (B) 6 (C) 7
Question. 19

(D) 8

The literal count of a boolean expression is the sum of the number of times each literal appears in the expression. For example, the literal count of (xy + xz) is 4. What are the minimum possible literal counts
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CS Topicwise 2001-2010 Digital Logic

www.gatehelp.com of the product-of-sum and sum-of-product representations respectively of the function given by the following karnaugh map? Here, denotes dont care

(A) (11,9) (C) (9,10)

(B) (9,13) (D) (11,11)

Consider the following circuit composed of XOR gates and noninverting buffers.

The non-inverting buffers have delays 1 = 2ns and 2 = 4ns as shown in the figure. both XOR gates and al wires have zero delay. Assume that all gate inputs, outputs and wires are stable at logic level 0. If the following waveform is applied at input. A, how many transition (s) (change of logic levels) occur (s) at B during the interval from 0 to 10 ns ?

(A) 1 (C) 3
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(B) 2 (D) 4

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YEAR 2004 Question. 21

CS Topicwise 2001-2010 Digital Logic

The Boolean function x'y' + xy + x'y is equivalent to (A) x' + y' (C) x + y'
Question. 22

(B) x + y (D) x' + y

In an SR latch made by cross-coupling two NAND gates, if both S and R inputs are set to 0, then it will result in (A) Q = 0, Q' = 1 (C) Q = 1, Q' = 1
Question. 23

(B) Q = 1, Q' = 0 (D) Indeterminate states

If 73x (in base-x number system) is equal to 54, (in base-y number system), the possible values of x and y are (A) 8, 16 (C) 9, 13
Question. 24

(B) 10, 12 (D) 8, 11

What is the result of evaluating the following two expressions using three-digit floating point arithmetic with rounding? (113.+111.)+7.51 113.+(111.+7.51) (A) 9.51 and 10.0 respectively (C) 9.51 and 9.51 respectively
Question. 25

(B) 10.0 and 9.51 respectively (D) 10.0 and 10.0 respectively

A circuit outputs a digit in the form of 4 bits. 0 is represented by 0000, 1 by 0001,...9 by 1001. A combinational circuit is to be diesigned which takes these 4 bits as input and outputs 1 if the digit $ 5, and 0 otherwise. If only AND, OR and NOT gates may be used, what is the minimum number of gates required? (A) 2 (C) 4 (B) 3 (D) 5
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Question. 26

Which are the essential prime implicates of the following Boolean function? f (a, b, c) = a'c + ac' + b'c (A) a'c and ac' (C) a'c only
Question. 27

(B) a'c and b'c (D) ac' and bc'

Consider the partial implementation fo a 2-bit counter using T flip flops following the sequence 0-2-3-1-0, as shown below

To complete the circuit, the input X should be (A) Q2 ' (C) (Q1 5 Q2)'
Question. 28

(B) Q2 + Q1 (D) Q1 5 Q2

A 4-bit carry look ahead adder, which adds two 4-bit numbers, is designed using AND, OR, NOT, NAND, NOR gates only. Assuming that all the inputs are available in both complemented and uncompensated forms and the delay of each gate is one time unit, what is the overall propagation delay of the adder? Assume that the carry network has been implemented using two-level AND-OR logic. (A) 4 time units (C) 10 time units
Question. 29

(B) 6 time units (D) 12 time units

Let A = 11111010 and B 0000 1010 be two 8-bit 2s complement numbers. Their product in 2s complement is
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www.gatehelp.com (A) 1100 0100 (C) 1010 0101 (B) 1001 1100 (D) 1101 0101

CS Topicwise 2001-2010 Digital Logic

YEAR 2005

Question. 30

Consider the following circuit.

Which one of the following is TRUE? (A) f is independent of X (C) f is independent of Z

(B) f is independent of Y (D) None of X, Y, Z is redundant

The range of integers that can be represented by an a bit 2s complement number system is (A) 2n 1 to (2n 1 1) (C) 2n 1 to 2n 1
Question. 32

(B) (2n 1 1) to (2n 1 1) (D) (2n 1 + 1) to (2n 1 1)

The hexadecimal representation of 6578 is (A) 1AF (C) D71

(B) D78 (D) 32F

The switching expression corresponding to f (A, B, C, D) = / (1, 4, 5, 9, 11, 12) is (A) BC'D' + A'C'D + AB'D (C) ACD' + A'BC' + AC'D' (B) ABC' + ACF + B'C'D (D) A'BD + ACD' + BCD'
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Question. 34

Consider the following circuit involving a positive edge triggered D -FF.

Consider the following timing diagram. Let Ai represent the logic level on the line A in the i th clock period.

Let A represent the complement of A . The correct output sequence on Y over the clock perids 1 through 5 is (A) A0 A1 A1 'A3 A4 (C) A1 A2 A2 'A3 A4
Question. 35

(B) A0 A1 A2 'A3 A4 (D) A1 A2 'A3 A4 A5

The following diagram represents a finite state machine which takes as input a binary number from the least significant bit

Which one of the following is TRUE? (A) It computes 1s complement of the input number (B) It computes 2s complement of the input number (C) It increments the input number
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www.gatehelp.com (D) It decrements the input number

CS Topicwise 2001-2010 Digital Logic

Consider the following circuit

The flip-flops are positive edge triggered D FFs . Each state is designated as a two bit string Q0, Q1 . Let the initial state be 00. The state transition sequence is (A) 00 " 11 " 01 A BBBBBB BC (C) 00 " 10 " 01 " 11 A BBBBBBBBB BC (B) 00 " 11 A BBB BC (D) 00 " 11 " 01 " 10 A BBBBBBBBBB C

Data for Q. 37 & 38 are given below.

Mantissa is a pure fraction is sign-magnitude form.

The decimal number 0.239 # 213 has the following hexadecimal representation without normalization and rounding off (A) 0D 24 (C) 4D 0D (B) 0D 4D (D) 4D 3D
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CS Topicwise 2001-2010 Digital Logic

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Question. 38

The normalized representation for the above format is specified as follows. The mantissa has an implicit 1 preceding the binary (radix) point. Assume that only 0s are padded in while shifting a field. The normalized representation of the above number (0.239 # 213) is (A) 0A 20 (C) 4D D0 (B) 11 34 (D) 4A E8

YEAR 2006

Question. 39

You are given a free running clock with a duty cycle of 50% and a digital waveform f which changes only at the negative edge of the clock. Which one of the following circuits (using clocked D flip flops) will delay the phase of f by 180c ?

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CS Topicwise 2001-2010 Digital Logic

Question. 40

Consider the circuit below. Which one of the following options correctly represents f (x, y, z)?

(A) xz + xy + yz (C) xz + xy + yz
Question. 41

(B) xz + xy + yz

(D) xz + xy + yz

Given two three bit numbers a2 a1 a0 and b2 b1 b0 and c , the carry in, the function that represents the carry generate function when these two numbers are added is (A) a2 b2 + a1 a1 b1 + a2 a1 a0 b0 + a2 a0 b1 b0 + a1 b2 b1 + a1 a0 b2 b0 + a0 b2 b1 b0 (B) a2 b2 + a2 b1 b0 + a2 a1 b1 b0 + a1 a0 b21 b1 + a1 a0 b2 + a1 a0 b2 b0 + a2 a0 b1 b0 (C) a2 + b2 + (a2 5 b2)[ a1 + b1 + (a1 5 b1)( a0 + b0)] (D) a2 b2 + a2 a1 b1 + a2 a1 a0 b0 + a2 a0 b1 b0 + a1 b2 b1 a1 a0 b2 b0 + a0 b2 b1 b0
Question. 42

Consider a boolean function f (w, x, y, z). Suppose that exactly one of its inputs is allowed to change at a time. If the function happens to be true for two input vectors i1 + < w1, x1, y1, x1 > and i2 + < w2, x2, y2, z2 > , we would like the function to remain true as the input changes from i1 to i2 (i1 and i2 differ in exactly one bit position), without becoming false momentarily. Let f (w, x, y, z) = / (5,, 711, 12, 13, 15). Which of
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CS Topicwise 2001-2010 Digital Logic

www.gatehelp.com the following cube covers of f will ensure that the required property is satisfied? (A) wxz, wxy, xyz, xyz, wyz (B) wxy, wxz, wyz (C) wxyz, xz, wxyz
Question. 43

(D) wzy, wyz, wxz, wwxz, xyz, xyz

We consider addition of two 2s complement numbers bn 1 bn 2 .....b0 and an 1 an 2 ....a0 . A binary adder for adding unsigned binary numbers is used to add the two numbers. The sum is denoted by cn 1 cn 2 ....c0 and the carryout by cout . Which one of the following options correctly identifies the overflow condition? (A) cout (an 1 5 bn 1) (B) an 1 bn 1 cn 1 + an 1 bn 1 cn 1 (C) cout 5 cn 1
Question. 44

(D) an 1 5 bn 1 5 cn 1

Consider number represented in 4-bit gray code. Let h3 h2 h1 h0 be the gray code representation of a number n and let g3 g2 g1 g0 be the gray code of (n + 1) (modulo 16) value of the number. Which one of the following functions is correct? (A) g0 (h1 h2 h1 h0) = / (1, 2, 3, 6, 10, 13, 14, 15) (B) g1 (h1 h2 h1 h0) = / (4,9,10,11,12,,13,14,15) (C) g2 (h1 h2 h1 h0) = / (2,4, 5, 6, 7,12,,13,15) (D) g3 (h1 h2 h1 h0) = / (0, 1,6,7, 10, 11,12,,13,)

YEAR 2007 Question. 45

What is the maximum number of different Boolean functions involving n Boolean variables? (A) n2 (B) 2n (C) 22
n

(D) 2n

Question. 46

How many 3-to-8 line decoders with an enable input are needed to construct a 6-to-64 line decoder without using any other logic gates? (A) 7 (B) 8
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www.gatehelp.com (C) 9
Question. 47

CS Topicwise 2001-2010 Digital Logic

(D) 10

Consider the following Boolean function of four variables f (w, x,, y, z) = / (1, 3, 4, 6, 9, 11, 12, 14) The function is (A) independent of one variable (B) independent of two variables (C) independent of three variables (D) dependent on all the variables
Question. 48

Let f (w, x, y, z) = / (0, 4, 5, 7, 8, 9, 13, 15). Which of the following expressions are NOT equivalent to f ? (A) x'y'z + w'xy' + wy'z + xz (C) w'y'z' + wx'y' + xyz + xy'z
Question. 49

(B) w'y'x' + wx'y' + xz (D) x'y'z + wx'y' + w'y

Define the connective* for the boolean variable X and Y as: X * Y = XY + X'Y' Let Z = X * Z Consider the following expression P, Q and R . P: X = Y * ZQ: Y = X * Z R: X * Y * Z = 1 Which of the following is TRUE? (A) only P and Q are valid (C) Only P and R are valid
Question. 50

(B) Only Q and R are valid (D) All P, Q , R are valid

Suppose only one multiplexer and one inverter are allowed to be used to implement any Boolean function of n variables. What is the minimum size of the multiplexer needed? (A) 2n line to 1 line (C) 2n 1 line to 1 line (B) 2n + 1 line to 1 line (D) 2n 2 line to 1 line
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Question. 51

In a look-ahead carry generator, the carry generate function Gi and the carry propagate function Pi for inputs, Ai and Bi are given by Pi = Ai 5 Bi and Gi = Ai Bi The expressions for the sum bit S and carry bit Ci + 1 of the look ahead carry adder are given by Si + Pi 5 Ci and Ci + 1 Gi + Pi Ci , Where C0 is the input carry. Consider a two-level logic implementation of the look-ahead carry generator.. Assume that all Pi and Gi are available for the carry generator circuit and that the AND and OR gates can have any number of inputs. The number of AND gates and OR gates needed to implement the look-ahead carry generator for a 4-bit adder with S3, S2, S1, S0 and C4 as its outputs are respectively (A) 6,3 (C) 6,4
Question. 52

(B) 10,4 (D) 10,5

The control signal functions of 4-bit binary counter are given below (where X is dont care) Clear Clock Load Count Function 1 0 0 0 X X X 0 1 0 X 0 X 1 Clear to 0 No change Load input Count next

The counter is connected as follows

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www.gatehelp.com Assume that the counter and gate delays are negligible. If the counter starts at 0, then it cycles through the following sequence (A) 0,3,4 (B) 0,3,4,5 (C) 0,1,2,3,4 (D) 0,1,2,3,4,5

CS Topicwise 2001-2010 Digital Logic

YEAR 2008 Question. 53

In the IEEE floating point representation the hexadecimal value 0x00000000 corresponds to (A) the normalized value 2 127 (B) the normalized value 2 126 (C) the normalized value + 0
Question. 54

(D) the special value + 0

In the karnaugh map shown below, X denoted a dont care term. What is the nominal form of the function represented by the karnaugh map

(A) b.d + a.d

(B) a.b + b.d + a.b.d (D) a.b + b.d + a.d

(C) b.d + a.b.d

Let a denote number system radix. The only value(s) of r that satisfy the equation 121 + 11, is/are (A) decimal 10 (B) decimal 11 (C) decimal 10 and 11 (D) any value> 2

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Question. 56

Give f1, f3 and f in canonical sum of products form (in decimal) for the circuit

f1 = /m (4, 5, 6, 7, 8) f3 = /m (1, 6, 15) f = /m (1, 6, 8, 15) Then f2 is (A) /m (4, 6) (C) /m (6, 8)
Question. 57

(B) /m (4, 8) (D) /m (4,6,8)

If P , Q , R are Boolean variables, (P + Q) (P.Q + P.R) (P.R + Q) simplifies to (A) P.Q (C) P.Q + R

(B) P.R (D) P.R + Q

YEAR 2009

Question. 58

(1217) 8 is equivalent to (A) (1217) 16 (C) (2297) 10

(B) (028F) 16 (D) (0B17) 16

What is the minimum number of gates required to implement the Boolean function (AB + C) if we have to use only 2-input NOR gates ? (A) 2 (C) 4
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(B) 3 (D) 5

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YEAR 2010

CS Topicwise 2001-2010 Digital Logic

Question. 60

The minterm expansion of f (P, Q, R) = PQ + QR + PR is (A) m2 + m 4 + m6 + m1 (C) m 0 + m1 + m6 + m1 (B) m 0 + m1 + m 3 + m5 (D) m2 + m 3 + m 4 + m5

Question. 61

P is a 16-bit signed integer. The 2s complement representation of P is (F87B) 16 . The 2s complement representation of 8)P is (A) (C3D8) 16 (C) (F878) 16 (B) (187B) 16 (D) (987B) 16

Question. 62

The Boolean expression for the output f of the multiplexer shown below is

(A) P 5 Q 5 R (C) P + Q + R

(B) P 5 Q 5 R (D) P + Q + R

Question. 63

What is the boolean expression for the output f of the combinational logic circuit of NOR gates given below ?
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(A) Q + R (C) P + R
Question. 64

(B) P + Q (D) P + Q + R

In the sequential circuit shown below, if the initial value of the output Q1 Q 0 is 00, what are the next four values of Q1 Q 0 ?

(A) 11, 10, 01, 00 (C) 10, 00, 01, 11

(B) 10, 11, 01, 00 (D) 11, 10, 00, 01

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