SN74LS122 SN74LS123 Retriggerable Monostable Multivibrators

These dc triggered multivibrators feature pulse width control by three methods. The basic pulse width is programmed by selection of external resistance and capacitance values. The LS122 has an internal timing resistor that allows the circuits to be used with only an external capacitor. Once triggered, the basic pulse width may be extended by retriggering the gated low-level-active (A) or high-level-active (B) inputs, or be reduced by use of the overriding clear. Overriding Clear Terminates Output Pulse Compensated for VCC and Temperature Variations DC Triggered from Active-High or Active-Low Gated Logic Inputs Retriggerable for Very Long Output Pulses, up to 100% Duty Cycle Internal Timing Resistors on LS122
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LOW POWER SCHOTTKY

14 1

PLASTIC N SUFFIX CASE 646

GUARANTEED OPERATING RANGES

Symbol VCC TA IOH IOL Rext Cext Rext/Cext Parameter Supply Voltage Operating Ambient Temperature Range Output Current High Output Current Low External Timing Resistance External Capacitance Wiring Capacitance at Rext/Cext Terminal 5.0 Min 4.75 0 Typ 5.0 25 Max 5.25 70 0.4 8.0 260 No Restriction 50 pF Unit V C mA mA kW
16 1 14 1

SOIC D SUFFIX CASE 751A

PLASTIC N SUFFIX CASE 648

16 1

SOIC D SUFFIX CASE 751B

ORDERING INFORMATION
Device SN74LS122N SN74LS122D SN74LS123N SN74LS123D Package 14 Pin DIP 14 Pin 16 Pin DIP 16 Pin Shipping 2000 Units/Box 2500/Tape & Reel 2000 Units/Box 2500/Tape & Reel

Semiconductor Components Industries, LLC, 1999

December, 1999 Rev. 6

Publication Order Number: SN74LS122/D

SN74LS122 SN74LS123
SN74LS123 (TOP VIEW) (SEE NOTES 1 THRU 4)
VCC 16 1 Rext/ 1 Cext Cext 15 14 1Q 13 2Q 12 2 CLR 11 2B 10 2A 9

Q CLR Q 1 1A 2 1B 3 1 CLR 4 1Q 5 2Q

Q Q

CLR

6 2 Cext

8 7 2 GND Rext/ Cext

SN74LS122 (TOP VIEW) (SEE NOTES 1 THRU 4)

VCC 14 Rext/ Cext 13 NC 12 Cext 11 NC 10 Rint Q CLR Q 1 A1 2 A2 3 B1 4 B2 5 CLR 6 Q 7 GND Rint 9 Q 8

NC NO INTERNAL CONNECTION.

NOTES: 1. An external timing capacitor may be connected between Cext and Rext/Cext (positive). 2. To use the internal timing resistor of the LS122, connect Rint to VCC. 3. For improved pulse width accuracy connect an external resistor between Rext/Cext and VCC with Rint open-circuited. 4. To obtain variable pulse widths, connect an external variable resistance between Rint/Cext and VCC.

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SN74LS122 SN74LS123
LS122 FUNCTIONAL TABLE
INPUTS CLEAR L X X X H H H H H H H A1 X H X X L L X X H L X A2 X H X X X X L L H X L B1 X X L X H H H H H H H B2 X X X L H H H H H H H OUTPUTS Q L L L L Q H H H H CLEAR L X X H H

LS123 FUNCTIONAL TABLE

INPUTS A X H X L L B X X L H H OUTPUTS Q L L L Q H H H

TYPICAL APPLICATION DATA The output pulse tW is a function of the external components, Cext and Rext or Cext and Rint on the LS122. For values of Cext 1000 pF, the output pulse at VCC = 5.0 V and VRC = 5.0 V (see Figures 1, 2, and 3) is given by tW = K Rext Cext where K is nominally 0.45 If Cext is on pF and Rext is in k then tW is in nanoseconds. The Cext terminal of the LS122 and LS123 is an internal connection to ground, however for the best system performance Cext should be hard-wired to ground. Care should be taken to keep Rext and Cext as close to the monostable as possible with a minimum amount of inductance between the Rext/Cext junction and the Rext/Cext pin. Good groundplane and adequate bypassing should be designed into the system for optimum performance to ensure that no false triggering occurs. It should be noted that the Cext pin is internally connected to ground on the LS122 and LS123, but not on the LS221. Therefore, if Cext is hard-wired externally to ground, substitution of a LS221 onto a LS123 socket will cause the LS221 to become non-functional. The switching diode is not needed for electrolytic capacitance application and should not be used on the LS122 and LS123. To find the value of K for Cext 1000 pF, refer to Figure 4. Variations on VCC or VRC can cause the value of K to change, as can the temperature of the LS123, LS122.

Figures 5 and 6 show the behavior of the circuit shown in Figures 1 and 2 if separate power supplies are used for VCC and VRC. If VCC is tied to VRC, Figure 7 shows how K will vary with VCC and temperature. Remember, the changes in Rext and Cext with temperature are not calculated and included in the graph. As long as Cext 1000 pF and 5K Rext 260K, the change in K with respect to Rext is negligible. If Cext 1000 pF the graph shown on Figure 8 can be used to determine the output pulse width. Figure 9 shows how K will change for Cext 1000 pF if VCC and VRC are connected to the same power supply. The pulse width tW in nanoseconds is approximated by tW = 6 + 0.05 Cext (pF) + 0.45 Rext (k) Cext + 11.6 Rext In order to trim the output pulse width, it is necessary to include a variable resistor between VCC and the Rext/Cext pin or between VCC and the Rext pin of the LS122. Figure 10, 11, and 12 show how this can be done. Rext remote should be kept as close to the monostable as possible. Retriggering of the part, as shown in Figure 3, must not occur before Cext is discharged or the retrigger pulse will not have any effect. The discharge time of Cext in nanoseconds is guaranteed to be less than 0.22 Cext (pF) and is typically 0.05 Cext (pF). For the smallest possible deviation in output pulse widths from various devices, it is suggested that Cext be kept 1000 pF.

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SN74LS122 SN74LS123

WAVEFORMS

RETRIGGER PULSE B INPUT

(See Application Data)

Q OUTPUT tW OUTPUT WITHOUT RETRIGGER

EXTENDING PULSE WIDTH

B INPUT

CLEAR INPUT

CLEAR PULSE

OUTPUT WITHOUT CLEAR PULSE Q OUTPUT

OVERRIDING THE OUTPUT PULSE

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SN74LS122 SN74LS123
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
Limits Symbol VIH VIL VIK VOH Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage 2.7 0.65 3.5 0.25 VOL O Output LOW Voltage 0.35 IIH IIL IOS ICC Input HIGH Current 0.1 Input LOW Current Short Circuit Current (Note 1) LS122 Power Supply Current LS123 20 20 0.4 100 11 mA VCC = MAX 0.5 20 V A mA mA mA IOL = 8.0 mA 0.4 Min 2.0 0.8 1.5 Typ Max Unit V V V V V Test Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for All Inputs VCC = MIN, IIN = 18 mA VCC = MIN, IOH = MAX, VIN = VIH or VIL per Truth Table IOL = 4.0 mA VCC = VCC MIN, VIN = VIL or VIH per Truth Table

VCC = MAX, VIN = 2.7 V VCC = MAX, VIN = 7.0 V VCC = MAX, VIN = 0.4 V VCC = MAX

Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.

AC CHARACTERISTICS (TA = 25C, VCC = 5.0 V)

Limits Symbol tPLH tPHL tPLH tPHL tPLH tPHL tW min tWQ Parameter Propagation g Delay, y A to Q Propagation Delay, A to Q Propagation g Delay, y B to Q Propagation Delay, B to Q Propagation g Delay, y Clear to Q Propagation Delay, Clear to Q A or B to Q A to B to Q 4.0 Min Typ 23 32 23 34 28 20 116 4.5 Max 33 ns 45 44 ns 56 45 ns 27 200 5.0 ns s Cext = 1000 pF, Rext = 10 k, CL = 15 pF, RL = 2.0 k Cext = 0 CL = 15 pF Rext = 5.0 k RL = 2.0 k Unit Test Conditions

AC SETUP REQUIREMENTS (TA = 25C, VCC = 5.0 V)

Limits Symbol tW Pulse Width Parameter Min 40 Typ Max Unit ns Test Conditions

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SN74LS122 SN74LS123
VCC VRC Rext Cext Cext Rext/ VCC Cext Q CLR 1/2 LS123 B Pin 51 A Q GND 0.1 F Pout VCC VCC VRC Rext Cext Cext Rext/ VCC CLR Cext Q B2 LS122 B1 A2 Q A1 GND 0.1 F VCC

Pout

Pin 51

Figure 1.

Figure 2.

Pin

Pout

tW

RETRIGGER

Figure 3.

10 5K Rext 260K EXTERNAL CAPACITANCE, Cext ( F) 1

0.1

0.01

0.001

0.3

0.35 0.4

0.45 0.5

0.55

Figure 4.

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SN74LS122 SN74LS123
0.55 VRC = 5 V Cext = 1000 pF 0.5 0.5 55C 0C 25C 70C 0.4 125C 0.4 0C 0.55 VCC = 5 V Cext = 1000 pF 55C 25C 70C 125C 0.4 0.5 55C 0.55 Cext = 1000 pF

K
0.45

K
0.45

K
0.45

0C 25C 70C 125C

0.35 4.5 5 VCC 5.5

0.35 4.5 5 VRC 5.5

0.35 4.5 5 VCC = VRC 5.5

Figure 5. K versus VCC

Figure 6. K versus VRC

Figure 7. K versus VCC and VRC

100000

10000 t W, OUTPUT PULSE WIDTH (ns)

Rext = 260 k Rext = 160 k

1000

100

Rext = 80 k Rext = 40 k Rext = 20 k Rext = 10 k Rext = 5 k 1 10 100 1000

10

Cext, EXTERNAL TIMING CAPACITANCE (pF)

Figure 8.

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SN74LS122 SN74LS123
0.65

Cext = 200 pF 55C 0.6 0C 25C

70C K 0.55

125C

0.5

4.5

4.75

5 VCC VOLTS

5.25

5.5

Figure 9.

VCC Rext REMOTE

PIN 7 OR 15 Cext PIN 6 OR 14

Rext

Figure 10. LS123 Remote Trimming Circuit

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SN74LS122 SN74LS123
VCC PIN 9 OPEN Rext PIN 13 Cext PIN 11 Rext REMOTE

Figure 11. LS122 Remote Trimming Circuit Without Rext

VCC Rext REMOTE

PIN 9 PIN 13

PIN 11

Figure 12. LS122 Remote Trimming Circuit with Rint

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SN74LS122 SN74LS123
PACKAGE DIMENSIONS

N SUFFIX PLASTIC PACKAGE CASE 64606 ISSUE M

14 8

B
1 7

NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. INCHES MIN MAX 0.715 0.770 0.240 0.260 0.145 0.185 0.015 0.021 0.040 0.070 0.100 BSC 0.052 0.095 0.008 0.015 0.115 0.135 0.290 0.310 10_ 0.015 0.039 MILLIMETERS MIN MAX 18.16 18.80 6.10 6.60 3.69 4.69 0.38 0.53 1.02 1.78 2.54 BSC 1.32 2.41 0.20 0.38 2.92 3.43 7.37 7.87 10_ 0.38 1.01

A F N T
SEATING PLANE

L C

K H G D 14 PL 0.13 (0.005)
M

J M

DIM A B C D F G H J K L M N

D SUFFIX PLASTIC SOIC PACKAGE CASE 751A03 ISSUE F

A
14 8

B
1 7

P 7 PL 0.25 (0.010)
M

NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION.

G C

R X 45 _

T
SEATING PLANE

D 14 PL 0.25 (0.010)

K
M

M
S

T B

DIM A B C D F G J K M P R

MILLIMETERS MIN MAX 8.55 8.75 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50

INCHES MIN MAX 0.337 0.344 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.228 0.244 0.010 0.019

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SN74LS122 SN74LS123
PACKAGE DIMENSIONS

N SUFFIX PLASTIC PACKAGE CASE 64808 ISSUE R

A
16 9 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. DIM A B C D F G H J K L M S INCHES MIN MAX 0.740 0.770 0.250 0.270 0.145 0.175 0.015 0.021 0.040 0.70 0.100 BSC 0.050 BSC 0.008 0.015 0.110 0.130 0.295 0.305 0_ 10 _ 0.020 0.040 MILLIMETERS MIN MAX 18.80 19.55 6.35 6.85 3.69 4.44 0.39 0.53 1.02 1.77 2.54 BSC 1.27 BSC 0.21 0.38 2.80 3.30 7.50 7.74 0_ 10 _ 0.51 1.01

B
1 8

F S

T H G D
16 PL

SEATING PLANE

J T A
M

0.25 (0.010)

D SUFFIX PLASTIC SOIC PACKAGE CASE 751B05 ISSUE J

A
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.229 0.244 0.010 0.019

16

B
1 8

8 PL

0.25 (0.010)

G F

K C T
SEATING PLANE

X 45 _

M D
16 PL M

0.25 (0.010)

T B

DIM A B C D F G J K M P R

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SN74LS122 SN74LS123

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SN74LS122/D