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    Advanced Testing With VHDL

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    This document discusses advanced testing techniques using VHDL, including: 1. Adding an SRAM model to a testbench for testing purposes. 2. Using VHDL attributes to retrieve information about signals for testing, such as checking for setup time violations. 3. Different types of loop statements (for, while, loop) that can be used in testbenches. 4. Examples of more advanced testbenches using techniques like reading in test vectors from a file and writing results back out.

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    Advanced Testing With VHDL

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    134 views43 pages
    This document discusses advanced testing techniques using VHDL, including: 1. Adding an SRAM model to a testbench for testing purposes. 2. Using VHDL attributes to retrieve information about signals for testing, such as checking for setup time violations. 3. Different types of loop statements (for, while, loop) that can be used in testbenches. 4. Examples of more advanced testbenches using techniques like reading in test vectors from a file and writing results back out.

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    This document discusses advanced testing techniques using VHDL, including: 1. Adding an SRAM model to a testbench for testing purposes. 2. Using VHDL attributes to retrieve information about signals for testing, such as checking for setup time violations. 3. Different types of loop statements (for, while, loop) that can be used in testbenches. 4. Examples of more advanced testbenches using techniques like reading in test vectors from a file and writing results back out.

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    Attribution Non-Commercial (BY-NC)
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    Download as pdf or txt
    134 views43 pages

    Advanced Testing With VHDL

    Uploaded by

    Lê Văn Lợi
    This document discusses advanced testing techniques using VHDL, including: 1. Adding an SRAM model to a testbench for testing purposes. 2. Using VHDL attributes to retrieve information about signals for testing, such as checking for setup time violations. 3. Different types of loop statements (for, while, loop) that can be used in testbenches. 4. Examples of more advanced testbenches using techniques like reading in test vectors from a file and writing results back out.

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    Advanced Testing using VHDL

    Module 9

    Jim Duckworth, WPI

    Advanced Testing using VHDL

    Overview
    SRAM Model Attributes Loop Statements Test Bench examples using
    TEXTIO Conversion functions Reading file containing test vectors Writing test results to file

    Jim Duckworth, WPI

    Advanced Testing using VHDL

    Adding the SRAM model


    New testbench

    Battleship/RISC SRAM Model


    Display

    Picoblaze

    Jim Duckworth, WPI

    Advanced Testing using VHDL

    SRAM - Simplified Read Operation

    Jim Duckworth, WPI

    Advanced Testing using VHDL

    SRAM Model - Verilog

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    Advanced Verilog Testing for Testing using VHDL Module

    SRAM Model - VHDL

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    Advanced Testing using VHDL

    SRAM Model Read and Write

    Jim Duckworth, WPI

    Advanced Testing using VHDL

    VHDL Attributes
    Signals can have attributes associated with them Example predefined signal attributes are
    function value type range

    Also possible to have user-defined attributes

    Jim Duckworth, WPI

    Advanced Testing using VHDL

    Function Attributes
    Predefined functions Returns information about the behavior of signals
    sEVENT
    returns true if an event occurred change in value

    sACTIVE
    returns true if signal s is active new value assigned to signal s (may be same value)

    sLAST_EVENT
    returns elapsed time since last event

    sLAST_ACTIVE sLAST_VALUE
    returns value of s before the last event

    Jim Duckworth, WPI

    Advanced Testing using VHDL

    Function Attribute example


    Check for setup time violation on d input changing
    CONSTANT setup_time : TIME := 12 ns; -- TIME is predefined PROCESS(clk) BEGIN IF clkEVENT AND clk = 1 THEN ASSERT(dLAST_EVENT >= setup_time) REPORT setup violation SEVERITY error; END IF;

    Assert statement checks that the input d has not had an event during the setup time. If time returned is less than setup time - assertion will fail
    Jim Duckworth, WPI 10 Advanced Testing using VHDL

    now function
    NOW
    predefined function that returns simulation time
    IF dEVENT THEN lasteventonD := NOW; IF clkEVENT AND clk = 1 THEN ASSERT(now lasteventonD) >= setup_time REPORT setup violation SEVERITY error

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    Advanced Testing using VHDL

    RANGE attributes
    Only for constrained array types Returns range of specified type Two range attributes
    aRANGE aREVERSE RANGE
    TYPE address_bus IS ARRAY (63 DOWNT0 0) OF std_logic; SIGNAL cpu_address : address_bus; -- declare array -- 63 DOWNTO 0 -- 0 TO 63

    FOR j IN cpu_addressRANGE LOOP FOR j IN cpu_addressREVERSE_RANGE LOOP

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    Advanced Testing using VHDL

    VALUE and ARRAY Attributes


    These return the bounds of a type Four predefined attributes
    aLEFT
    returns left bound of type

    aRIGHT
    returns right bound of type

    aHIGH
    returns upper bound of type

    aLOW
    returns lower bound of type

    Also
    aLENGTH
    returns total length of the array
    Jim Duckworth, WPI 13 Advanced Testing using VHDL

    Value and Array Attribute examples


    TYPE address_bus IS ARRAY (63 DOWNT0 0) OF std_logic; SIGNAL cpu_address : address_bus; -- declare array BEGIN PROCESS VARIABLE i, j, k, l, m : INTEGER; BEGIN i := cpu_addressLEFT; j := cpu_addressRIGHT; k := cpu_addressHIGH; l := cpu_addressLOW; m := cpu_addressLENGTH; END PROCESS;

    ------

    63 0 63 0 64

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    Advanced Testing using VHDL

    Enumerated type example


    TYPE days IS (mon, tues, wed, thurs, fri, sat, sun); SUBTYPE weekend IS days RANGE sat TO sun; SIGNAL day1, day2, day3, day4, day5 : days; SIGNAL count : INTGER; BEGIN PROCESS BEGIN day1 day2 day3 day4

    <= <= <= <=

    daysLEFT; daysRIGHT; daysHIGH; weekendLOW;

    -----

    mon sun sun sat -- 1 -- thurs

    count <= daysPOS(tues); day5 <= daysVAL(3)); END PROCESS;

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    Advanced Testing using VHDL

    LOOP Statements
    Used to iterate through a set of sequential statements Three types
    FOR identifier IN range LOOP END LOOP; WHILE boolean_expression LOOP END LOOP; LOOP EXIT WHEN condition_test END LOOP;

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    Advanced Testing using VHDL

    FOR LOOP
    general syntax
    FOR identifier IN range LOOP END LOOP;

    example:
    factorial := 1; FOR number IN 2 TO n LOOP factorial := factorial * number; END LOOP;

    number = 2, 3, 4 no explicit declaration for loop identifier required also DOWNTO

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    Advanced Testing using VHDL

    WHILE Loop
    general syntax
    WHILE boolean_expression END LOOP;

    example:
    j := 0; sum := 10; wh_loop: WHILE j < 20 LOOP sum := sum * 2 j := j + 3; END LOOP wh_loop;

    Note: optional label for loop statement


    Jim Duckworth, WPI 18 Advanced Testing using VHDL

    LOOP
    No iteration scheme
    statements in body executed repeatedly until loop exits

    General syntax
    LOOP EXIT WHEN boolean_expression; -- optional EXIT statement END LOOP;

    Example:
    j := 0; sum := 1; l2: LOOP sum := sum * 10 j := j + 17; EXIT WHEN sum > 100; END LOOP l2;

    If exit statement not present loop executes indefinitely


    Jim Duckworth, WPI 19 Advanced Testing using VHDL

    LOOP contd
    EXIT statement
    only used inside a loop

    General syntax
    EXIT [loop_label] [WHEN condition] EXIT WHEN boolean_expression; -- optional EXIT statement END LOOP;

    Example (alternative to previous example):


    IF sum > 100 THEN EXIT; END IF;

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    Advanced Testing using VHDL

    LOOP contd
    NEXT statement
    used to exit a loop for the current iteration of a loop continue to the next iteration

    General syntax
    NEXT [loop_label] [WHEN condition]

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    Advanced Testing using VHDL

    LOOP example
    PROCESS BEGIN l1: LOOP -- statements -l2: LOOP -- statements -test_num := test_num + 1; EXIT l2 WHEN test_num = 25; IF solenoid_1 = 1 THEN drive_b := 0; NEXT l1; -- go to top of loop1 END IF; IF trigger = 0 THEN -- statements END LOOP l2; EXIT l1 WHEN sim_tests = 200; END LOOP l1; Jim Duckworth, WPI 22 Advanced Testing using VHDL

    Test Bench example


    example test bench:
    -- Test Bench to exercise and verify correctness of DECODE entity ENTITY tb2_decode IS END tb2_decode; ARCHITECTURE test_bench OF tb2_decode IS TYPE input_array IS ARRAY (0 TO 3) OF std_logic_vector(1 DOWNTO 0); CONSTANT input_vectors: input_array := ("00", "01", "10", "11"); -- input_vectors array contains test vectors for input SIGNAL in1 : STD_LOGIC_VECTOR (1 DOWNTO 0); SIGNAL out1 : STD_LOGIC_VECTOR (3 DOWNTO 0); COMPONENT decode PORT ( sel : IN std_logic_vector(1 downto 0); y : OUT std_logic_vector(3 downto 0)); END COMPONENT; Jim Duckworth, WPI 23 Advanced Testing using VHDL

    Test Bench example (contd)


    BEGIN decode_1: decode PORT MAP(sel => in1, y => out1); apply_inputs: PROCESS BEGIN FOR j IN input_vectors'RANGE LOOP in1 <= input_vectors(j); WAIT FOR 50 ns; END LOOP; END PROCESS apply_inputs; test_outputs: PROCESS BEGIN WAIT UNTIL (in1 = "01"); WAIT FOR 25 ns; ASSERT (out1 = "0110") REPORT "Output not equal to 0110" SEVERITY ERROR; END PROCESS test_outputs; END test_bench; Jim Duckworth, WPI 24 Advanced Testing using VHDL

    Assert Statements
    During testing
    Usually want to display information about signals and variables

    Assert statement is rather limited


    Report clause only allows a single string no built-in provision for formatting data
    ASSERT FALSE REPORT first line & CR & second line;

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    Advanced Testing using VHDL

    Test Bench example


    Adapted from Pellerin and Taylor (pages 242-246)
    demonstrates use of
    textio to read in a test vector file complex strings in Assert Statements string to vector and vector to string conversion functions

    uses a decoder component for test

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    Advanced Testing using VHDL

    VHDL for Synthesis

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    Advanced Testing using VHDL

    test_vec.txt File
    Format is
    3 bits for SEL input 8 bits for expected output

    00000000001 00100000010 01000000100 01100001000 10000010000 10100110000 11001000000 11110000000


    Jim Duckworth, WPI 28 Advanced Testing using VHDL

    Test Bench VHDL file


    LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE std.textio.ALL; -- use text I/O features of standard library ENTITY test_bench IS END test_bench; ARCHITECTURE tb1 OF test_bench IS COMPONENT decoder -- component to be tested PORT(sel : IN std_logic_vector(2 DOWNTO 0); y : OUT std_logic_vector(7 DOWNTO 0)); END COMPONENT; -- FOR all: decoder USE ENTITY work.decoder; -- configuration

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    Advanced Testing using VHDL

    Test Bench VHDL file (contd)


    -- function to convert string of character to vector FUNCTION str2vec(str : string) RETURN std_logic_vector IS VARIABLE vtmp: std_logic_vector(str'RANGE); BEGIN FOR i IN str'RANGE LOOP IF str(i) = '1' THEN vtmp(i) := '1'; ELSIF str(i) = '0' THEN vtmp(i) := '0'; ELSE vtmp(i) := 'X'; END IF; END LOOP; RETURN vtmp; END str2vec;

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    Advanced Testing using VHDL

    Test Bench VHDL file (contd)


    -- function to convert vector to string -- for use in assert statements FUNCTION vec2str(vec : std_logic_vector) RETURN string IS VARIABLE stmp : string(vec'LEFT+1 DOWNTO 1); BEGIN FOR i IN vec'REVERSE_RANGE LOOP IF vec(i) = '1' THEN stmp(i+1) := '1'; ELSIF vec(i) = '0' THEN stmp(i+1) := '0'; ELSE stmp(i+1) := 'X'; END IF; END LOOP; RETURN stmp; END vec2str;

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    Advanced Testing using VHDL

    Test Bench VHDL file (contd)


    SIGNAL clk : std_logic := '0'; -- create internal signals to connect to test component SIGNAL sel : std_logic_vector(2 DOWNTO 0); SIGNAL y : std_logic_vector(7 DOWNTO 0); BEGIN -- instantiate decoder test component u1: decoder PORT MAP(sel => sel, y => y); clk <= NOT clk AFTER 50 ns; -- create clock for timing

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    Advanced Testing using VHDL

    Test Bench VHDL file (contd)


    PROCESS -- declare and open file (1987 style) FILE vector_file: text IS in "test.vec"; VARIABLE file_line : line; -- text line buffer VARIABLE str_stimulus_in: string(11 DOWNTO 1); VARIABLE stimulus_in : std_logic_vector(10 DOWNTO 0); VARIABLE y_expected : std_logic_vector(7 DOWNTO 0); BEGIN -- loop through lines in test file WHILE NOT endfile(vector_file) LOOP -- read one complete line into file_line readline(vector_file, file_line); -- extract the first field from file_line read(file_line, str_stimulus_in); -- convert string to vector stimulus_in := str2vec(str_stimulus_in);

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    Advanced Testing using VHDL

    Test Bench VHDL file (contd)


    WAIT UNTIl clk = '1'; -- rising edge of clock -- now get sel input and apply to decoder sel <= stimulus_in(10 DOWNTO 8); -- top 3 bits for input; WAIT UNTIL clk = '0'; -- falling edge -- now check if decoder outputs are correct y_expected := stimulus_in(7 DOWNTO 0); -- expected output -- compare decoder output with expected value IF y /= y_expected THEN ASSERT false REPORT "decoder failure" & CR & "Expected y to be " & vec2str(y_expected) & " but its value was " & vec2str(y) SEVERITY ERROR; END IF; END LOOP; WAIT; END PROCESS; END tb1; -- suspend the simulation

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    Advanced Testing using VHDL

    VHDL Test Bench - Results

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    Advanced Testing using VHDL

    Test Bench Waveform

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    Advanced Testing using VHDL

    Simulation of post-place and route

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    Advanced Testing using VHDL

    Writing Test Results to File

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    Advanced Testing using VHDL

    Writing Test Results to File (contd)

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    Advanced Testing using VHDL

    results_file

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    Advanced Testing using VHDL

    Assert Statement Limitations


    Assert statements are limited to strings only
    need conversion functions for displaying signals

    Use TEXTIO instead of Assert Statements to print messages


    supports most data types allows writing to multiple files

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    Advanced Testing using VHDL

    Improving output messages


    Use ieee.std_logic_textio.ALL package Removes need for conversion functions

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    Advanced Testing using VHDL

    Modified write statements

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    Advanced Testing using VHDL

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