82563eb 82564eb Gbe Platform Lan Connect Datasheet

82563EB/82564EB Gigabit Platform LAN
Connect
Networking Silicon
Datasheet
Product Features
IEEE 802.3ab compliant
Robust operation over the installed base of
Category-5 (Cat-5) twisted pair cabling
PICMG 3.1 compliant
Robust operation in backplane over
Ethernet applications.
Support for cable line lengths greater than
100 m (spec); 123 m physical
Robust end to end connections over
various cable lengths
Full duplex at 10, 100, or 1000 Mb/s and half
duplex at 10 or 100 Mb/s.
IEEE 802.3ab Auto-negotiation with Next
Page support
Automatic link configuration including
speed, duplex, and flow control
10/100 downshift
Automatic link speed adjustment with
poor quality cable
Automatic MDI crossover
Helps to correct for infrastructure issues
Advanced Cable Diagnostics
Improved end-user troubleshooting
Kumeran interface
Low pin count, high speed interface to the
Intel 631xESB/632xESB I/O Controller
Hub
Allows PHY placement proximity to I/O
back panel.
7 LED outputs per port (4 configurable plus 3
dedicated)
Link and Activity indications (10, 100,
1000 Mb/s) on each port
Clock supplied to the 631xESB/632xESB
Cost optimized design
Full chip power down
Support for lowest power state
100 pin TQFP Package
Smaller footprint and lower power
dissipation compared to multi-chip MAC
and PHY solutions
Operating temperature: 0C to 60 C
(maximum) heat sink or forced airflow not
required
Simple thermal design
Power Consumption: < 1.0 Watts per port
(silicon power)
Minimize impact of incorporating dual
Gigabit instead of Fast Ethernet
Leaded and lead-free
a
100-pin TQFL with an
Exposed-Pad*. Devices that are lead-free are
marked with a circled e3 and have a
product code: HYXXXXX
a.This device is lead-free. That is, lead has not been intentionally added, but lead may still exist as an impurity at <1000 ppm.
The Material Declaration Data Sheet, which includes lead impurity levels and the concentration of other Restriction on Hazard-
ous Substances (RoHS) -banned materials, is available at:
ftp://download.intel.com/design/packtech/material_content_IC_Pack
In addition, this device has been tested and conforms to the same parametric specifications as previous versions of the device.
For more information regarding lead-free products from Intel Corporation, contact your Intel Field Sales representative.
316534-004
Revision 2.9
82563EB/82564EB Gigabit Platform LAN Connect Networking Silicon
ii
Revision History
Date Revision Comments
Nov 2007 2.9 Updated Tables 19, 20, 23, and 24. Updated Figures 5
and 6.
Oct 2007 2.8 Updated Table 16 Recommended Operating Conditions.
April 2007 2.7 Updated Section 4.2, Table 16 Core Digital Voltage
Range.
Feb 2007 2.6 Updated Table 6.
May 2006 2.5 Initial public release.
April 2006 2.1 Removed Preliminary from section 4.9 Power
Consumption.
Updated 1.9V external power supply parameters in Tables
16 and 19.
Nov 2005 2.0 Initial release (Intel Confidential).
Aug 2005 1.75 Added lead-free information.
Added measured power consumption values.
Updated crystal specifications (drive level now 750 W).
Changed 1.8V power rail references to 1.9V.
Dec 2004 1.0 Major revisions in all sections.
Sep 2004 0.70 Added power sequencing.
Jul 2004 0.51 Changed pin 51 (page13) from AVDD (1.8V) to AVDDR
(3.3V).
May 2004 0.5 Initial release (Intel Secret).
Legal Notice
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INTELLECTUAL PROPERTY RIGHT.
Intel products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in nuclear facility applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
This document contains information on products in the design phase of development. The information here is subject to change without notice. Do not
finalize a design with this information.
Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
The 82563EB/82564EB Gigabit Platform LAN Connects discussed in this document may contain design defects or errors known as errata which may
cause the product to deviate from published specifications. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be obtained from:
Intel Corporation
P.O. Box 5937
Denver, CO 80217-9808
or call in North America 1-800-548-4725, Europe 44-0-1793-431-155, France 44-0-1793-421-777, Germany 44-0-1793-421-333, other Countries 708-
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Intel is a trademark or registered trademark of Intel Corporation or its subsidiaries in the United States and other countries.
*Other names and brands may be claimed as the property of others.
Copyright Intel Corporation, 2007
iii
Contents
1.0 Introduction......................................................................................................................... 1
1.1 Document Scope................................................................................................... 1
1.2 Reference Documents........................................................................................... 1
1.3 Product Codes....................................................................................................... 2
2.0 Block Diagrams .................................................................................................................. 3
3.0 Signal Descriptions............................................................................................................. 5
3.1 Signal Type Definitions.......................................................................................... 5
3.2 Shared PHY Pins .................................................................................................. 6
3.3 MDIO Interface...................................................................................................... 6
3.4 Port A PHY Interface............................................................................................. 7
3.5 Port A Kumeran Interface...................................................................................... 8
3.6 Port A LEDs........................................................................................................... 8
3.7 Reset, Power Down, and Initialization Signals...................................................... 9
3.8 JTAG and IEEE Interface...................................................................................... 9
3.9 Reserved Signals ................................................................................................ 10
3.10 Voltage Control Pins............................................................................................ 10
3.11 Clock Generator Interface ................................................................................... 11
3.12 Power/Ground Pins ............................................................................................. 11
3.13 Port B PHY Interface........................................................................................... 13
3.14 Port B Kumeran Interface.................................................................................... 14
3.15 Port B LEDs......................................................................................................... 15
4.0 Voltage, Temperature and Timing Specifications............................................................. 17
4.1 Absolute Maximum Ratings................................................................................. 17
4.2 Recommended Operating Conditions ................................................................. 17
4.3 DC and AC Characteristics ................................................................................. 17
4.4 Power Supply Connections ................................................................................. 18
4.4.1 External LVR Power Delivery ................................................................. 18
4.4.2 Power Sequencing with External Regulators ......................................... 20
4.4.3 Internally-Generated Power Delivery ..................................................... 21
4.4.4 Internal LVR Power Sequencing ............................................................ 22
4.5 Link (MDI) Interface............................................................................................. 26
4.6 Kumeran (Serial) Interface .................................................................................. 27
4.6.1 Transmit ................................................................................................. 27
4.6.2 Receive .................................................................................................. 28
4.6.3 Electrical Idle.......................................................................................... 29
4.7 Crystal ................................................................................................................ 31
4.7.1 External Clock Oscillator ....................................................................... 31
4.8 Reset and Initial Clock Timing............................................................................. 32
4.9 Power Consumption............................................................................................ 33
5.0 Package and Pinout Information ...................................................................................... 37
5.1 Package Information ........................................................................................... 37
5.2 Thermal Specifications........................................................................................ 39
5.3 Pinout Information ............................................................................................... 40
iv
5.4 Interface Diagrams.............................................................................................. 43
5.5 Visual Pin Assignments....................................................................................... 44
Figures
1 82563EB Dual Port Block Diagram....................................................................... 3
2 82564EB Single Port Block Diagram .................................................................... 3
3 82563EB/82564EB power up sequencing with external regulators .................... 21
4 82563EB/82564EB power up sequencing with internal regulators ..................... 23
5 82563EB 1.9V and 1.2V internal LVR schematic................................................ 26
6 82564EB 1.9V and 1.2V internal LVR schematic............................................... 26
7 Kumeran (Serial) Transmit Eye Diagram............................................................ 28
8 Kumeran (Serial) Receive Eye Diagram............................................................. 29
9 External Clock Oscillator Connectivity to 82563EB/82564EB............................. 31
10 82563EB/82564EB Reset Timing ....................................................................... 32
11 Mechanical Information....................................................................................... 37
12 Mechanical Specifications and Notes ................................................................. 38
13 82563EB/82564EB Interfaces............................................................................. 43
14 82563EB Dual Port Gigabit Platform LAN connect Pinout (Top View) ............... 44
15 82564EB Single Port Gigabit Platform LAN Connect Pinout (Top View) ............ 45
Tables
1 Product Ordering Codes ....................................................................................... 2
1 Shared PHY Pins .................................................................................................. 6
2 MDIO Interface Pins.............................................................................................. 6
3 Port A PHY Interface Pins..................................................................................... 7
4 Port A Kumeran Interface Pins.............................................................................. 8
5 Port A LEDs .......................................................................................................... 8
6 Reset and Power Down Signals............................................................................ 9
7 JTAG Signals ........................................................................................................ 9
8 Test Signals ........................................................................................................ 10
9 Voltage Control Pins ........................................................................................... 10
10 Clock Generator Related Signals........................................................................ 11
11 Power/Ground Pins............................................................................................. 11
12 Port B PHY Interface Pins................................................................................... 13
13 Port B Kumeran Interface Pins............................................................................ 14
14 Port B LEDs ........................................................................................................ 15
15 Absolute Maximum Ratings ............................................................................... 17
16 Recommended Operating Conditions ................................................................. 17
17 DC and AC Characteristics ................................................................................. 17
18 3.3V External Power Supply Parameters............................................................ 19
21 3.3V External Power Supply Parameters........................................................... 21
22 82563EB/82564EB BOM (Bill of
Material) of Components for Internal Regulator .................................................. 23
23 1.9V Internal LVR Specification .......................................................................... 24
24 1.2V Internal LVR Specification .......................................................................... 24
25 PNP Specification ............................................................................................... 25
26 Link (MDI) Interface Electrical Specification........................................................ 26
27 Kumeran (Serial) Transmit Specifications........................................................... 27
v
28 Kumeran (Serial) Receive Specifications............................................................ 28
29 Kumeran (Serial) Electrical Idle Detection........................................................... 30
30 Kumeran (Serial) Electrical Idle Output ............................................................... 30
31 Crystal Parameters.............................................................................................. 31
32 Specification for External Clock Oscillator........................................................... 32
33 Reset Specification.............................................................................................. 33
34 Power Supply Characteristics - D0a (Both Ports) ............................................... 34
35 Power Supply Characteristics - D3cold - Wake Up Enabled (Both Ports)........... 34
36 Power Supply Characteristics - Uninitialized/Disabled........................................ 34
37 Power Supply Characteristics - Complete Subsystem........................................ 35
38 Thermal Characteristics ...................................................................................... 39
39 82563EB/82564EB Pinout by Pin Number Order............................................... 40
vi
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1
1.0 Introduction
The Intel 82563EB Gigabit Platform LAN Connect is a dual, compact Physical Layer
Transceiver (PHY) component designed for 10/100/1000 Mb/s operation. This device uses the
Kumeran interface port of the 631xESB/632xESB I/O Controller Hub enabling the routing of long
distances up to 28 inches (~711 mm). The 82564EB Gigabit Platform LAN Connect is the single
port implementation. The Intel 82563EB and 82564EB allow for Gigabit Ethernet
implementations in a very small package; easing routing constraints from the 631xESB/632xESB
I/O Controller Hub to the PHY.
The Intel 82563EB/82564EB devices are based upon proven PHY technology integrated into
Intels Gigabit Ethernet Controllers. The physical layer circuitry provides a standard IEEE 802.3
Ethernet interface for 1000BASE-T, 100BASE-TX, and 10BASE-T applications (802.3, 802.3u,
and 802.3ab). The 82563EB/82564EB devices are capable of transmitting and receiving data at
rates of 1000 Mb/s, 100 Mb/s, or 10 Mb/s.
1.1 Document Scope
This document contains datasheet specifications for the 82563EB/82564EB Gigabit Platform LAN
Connect, including signal descriptions, DC and AC parameters, packaging data, and pinout
information.
1.2 Reference Documents
This document assumes that the designer is acquainted with high-speed design and board layout
techniques. The following documents provide application information:
82563EB/82564EB LAN on Motherboard Design Guide (AP-467), Intel Corporation.
82563EB/82564EB Gigabit Platform LAN Connect Specification Update, Intel Corporation.
631xESB/632xESB I/O Controller Hub EEPROM Information Guide Application Note (AP-
477), Intel Corporation.
82571/82572/ESB2 LAN System Manageability Application Note (AP-497), Intel Corporation.
IEEE Standard 1149.1, 2001 Edition (JTAG). Institute of Electrical and Electronics Engineers
(IEEE).
IEEE Standard 802.3, 2002 Edition. Incorporates various IEEE Standards previously
published separately. Institute of Electrical and Electronic Engineers (IEEE).
Intel 631xESB/632xESB I/O Controller Hub External Design Specification (EDS), Volumes
1-3, Intel Corporation.
Bensley/Bensley-VS Platform Design Guide (PDG), Intel Corporation.
PICMG3.1 Ethernet/Fiber Channel Over PICMG 3.0 Draft Specification, September 4, 2002,
Version 0.90. PCI Industrial Computer Manufacturers Group (PICMG).
Software driver developers should contact their local Intel Representatives for programming
information.
2
1.3 Product Codes
The following Table 1 lists the product ordering codes for the 82563EB dual port device and the
82564EB single port device.
Table 1. Product Ordering Codes
Device Product Code
Dual Port (Leaded) HU82563EB
Single Port (Leaded) HU82564EB
Dual Port (Lead Free) HY82563EB
Single Port (Lead Free) HY82564EB
3
2.0 Block Diagrams
Figure 1. 82563EB Dual Port Block Diagram
Figure 2. 82564EB Single Port Block Diagram
82563EB
Port A
KUMERAN PHY
Port B
KUMERAN PHY
LINK
PARTNER
LINK
PARTNER
RX TX
TX RX
N
A
R
E
M
U
K
N
A
R
E
M
U
K
SERIAL
SERIAL
CAT 5
CAT 5
RX TX
TX RX
TX
RX
TX
RX
631xESB/
632xESB
82564EB
Port A
KUMERAN PHY
LINK
PARTNER
TX RX
N
A
R
E
M
U
K
SERIAL CAT 5
RX TX
TX
RX
631xESB/
632xESB
4
5
3.0 Signal Descriptions
3.1 Signal Type Definitions
The signals of 82563EB/82564EB are defined as follows:
I: Standard input-only signal
I (T): Functional input signal implemented as a bidirectional for test
O: Standard output-only signal
O (T):Functional output signal implemented as a bidirectional for test
I/O: Bi-directional, tri-state input/output signal
A: Analog signal
A-in: Analog input signal
A-o: Analog output signal
P: Power signal
G: Ground signal
NC: No connect (these signals must not be connected to any traces or planes)
B: Input bias
Signals may be further qualified to indicate whether an internal pull-up or pull-down is normally
active. Unless otherwise stated, internal pull-up and pull-down impedances are between 50 K:
and 130 K.
PU: Internal pull-up to VDD
PD: Internal pull-down to VSS
Note: It may be desirable to leave some input signals as no-connects in certain system applications that
rely on a devices internal pull-up or pull-down signal to be active. Care should be taken to ensure
there are no long traces, such as far-away test points or errant trace routings, on any inputs which
rely solely on internal pull-devices. Excess capacitance of dangling traces may generate charge
and/or noise on inputs which exceeds the capability of the internal pull-device, leading to
unpredictable component behavior.
In addition to a primary type, each pin can be classified according to one of the following sub-types
based on its electrical characteristics, such as input and output voltages and drive strengths.
TTL: TTL compatible inputs
TTL3: TTL compatible pins with at least 3mA drive strength
TTL12:TTL compatible pins with at least 12mA drive strength
6
3.2 Shared PHY Pins
3.3 MDIO Interface
Table 1. Shared PHY Pins
Signal Name Pin Type
Sub-
Type
Description
PHY_REF 50 B B
PHY Reference
External 4.99 K 1% resistor connection to VSS.
Table 2. MDIO Interface Pins
Note: For normal operation, the MDIO interface is strapped externally according to Table 39 due to
MDIO being an in-band operation.
Sub-
Type
Description
MDC 77 I (T) TTL
Management Data Clock
This signal is received from the 631xESB/632xESB as a clock
timing reference for information transfer on the MDIO signal. It is
not required to be a continuous signal and can be frozen when
no management data is transferred. This signal has a maximum
operating frequency of 2.5 MHz.
A 1 - 10 K 5% pull-down resistor should be connected to this
pin.
MDIO 76
I/O
PU
TTL6
Management Data Input/Output
Bi-directional data signal of the management data interface.
This pin has an internal pull-up. This signal can be left
disconnected (or pulled up) if not used.
MDIO_ADD[0]
MDIO_ADD[1]
MDIO_ADD[2]
MDIO_ADD[3]
78
79
18
19
I (T) TTL
Bits 4:1 of MDIO address
These bits are latched at the assertion of PHY_PWR_GOOD or
the de-assertion of PHY_RESET_N or PHY_SLEEP. They set
the MDIO address as follows:
bit 1 = MDIO_ADD[0]
bit 2 = MDIO_ADD[1]
bit 3 = MDIO_ADD[2]
bit 4 = MDIO_ADD[3]
A 1 -10 k 5% pull-down resistor should be connected to each
of these pins.
7
3.4 Port A PHY Interface
Note: Port A on the 82563EB/82564EB corresponds to connection to Port 0 on the 631xESB/632xESB.
Table 3. Port A PHY Interface Pins
Sub-
Type
Description
MDIA_PLUS[0]
MDIA_MINUS[0]
27
28
A A
Media Dependent Interface for Port A, bit 0
1000BASE-T:In MDI configuration, MDI[0]+/- corresponds to
BI_DA+/- and in MDIX configuration MDI[0]+/-
corresponds to BI_DB+/-.
100BASE-TX:In MDI configuration, MDI[0]+/- is used for the
transmit pair and in MDIX configuration MDI[0]+/- is
used for the receive pair.
10BASE-T: In MDI configuration, MDI[0]+/- is used for the transmit
pair and in MDIX configuration MDI[0]+/- is used for
the receive pair.
MDIA_PLUS[1]
MDIA_MINUS[1]
31
32
A A
BI_DB+/- and in MDIX configuration MDI[1]+/-
corresponds to BI_DA+/-.
100BASE-TX:In MDI configuration, MDI[1]+/- is used for the receive
the transmit pair.
10BASE-T: In MDI configuration, MDI[1]+/- is used for the receive
the transmit pair.
MDIA_PLUS[2]
MDIA_MINUS[2]
33
34
A A
BI_DC+/- and in MDIX configuration MDI[2]+/-
corresponds to BI_DD+/-.
100BASE-TX:Unused.
10BASE-T: Unused.
MDIA_PLUS[3]
MDIA_MINUS[3]
36
37
A A
BI_DD+/- and in MDIX configuration MDI[3]+/-
corresponds to BI_DC+/-.
100BASE-TX:Unused.
10BASE-T: Unused.
LINK_A 65 I/O TTL8
PHY A Link Indication
This signal is registered at the rising edge of PHY_PWR_GOOD,
and is used to determine the clock speed used for PHY_CLK_OUT.
Once PHY_PWR_GOOD is 1, LINK_A will always be an output and
indicate link up.
8
3.5 Port A Kumeran Interface
3.6 Port A LEDs
Table 4. Port A Kumeran Interface Pins
Sub-
Type
Description
TXA_PLUS,
TXA_MINUS
90
91
A-o A
Port A KumeranTX Pair
Differential Kumeran Transmit interface.
RXA_PLUS,
RXA_MINUS
93
94
A-in A
Port A Kumeran RX Pair
Differential Kumeran Receive interface.
Table 5. Port A LEDs
Sub-
Type
Description
LEDA_LINK_UP_N 73 O TTL12
LED 0 Link Up LED
This corresponds to port 0s LED#0 from the
631xESB/632xESB.
LEDA_ACTIVITY_N 72 O TTL12
LED 1 10 Mbps LED
631xESB/632xESB.
LEDA_SPEED_100_N 71 O TTL12
LED 2 100 Mbps LED
631xESB/632xESB.
LEDA_SPEED_1000_N 70 O TTL12
LED 3 1000 Mbps LED
631xESB/632xESB.
LEDA_DUPLEX 68 O TTL12
LED 4 Full Duplex LED
This LED will light when port 0s PHY is operating in
Full Duplex Mode
LEDA_TX_ACTIVITY 67 O TTL12
LED 5 Transmit Activity LED
This LED will light when the port 0s PHY transmits a
packet
LEDA_RX_ACTIVITY 66 O TTL12
LED 6 Receive Activity LED
This LED will light when the port 0s PHY receives a
packet
This pin also functions as the clock view pin and will
output clock signals required for IEEE conformance
testing. This pin should have a stuffing option for a test
header.
9
3.7 Reset, Power Down, and Initialization Signals
3.8 JTAG and IEEE Interface
Table 6. Reset and Power Down Signals
Sub-
Type
Description
PHY_PWR_GOOD 83 I TTL
Power Good (Power-On Reset)
The PHY_PWR_GOOD signal indicates good power is
available for The device. When set to 0b, the entire chip will be
held in a reset state.
PHY_RESET_N 81 I TTL
Reset
When set to 0b, resets the device, including PHY and Kumeran
logic. Needs an external pull-up resistor if the signal isnt
continuously being driven from an external source.
PHY_SLEEP 80 I (T) TTL
Sleep / Power Down
This will power down the PHY and the Kumeran of both ports.
Needs an external pull-down resistor, if the signal isnt
continuously being driven from an external source.
TEST_JTAG 95 I PU TTL
Enable JTAG Pin Control
This pin should be pulled high through a 1 to 10 K 5% resistor
in normal operation.
Table 7. JTAG Signals
Sub-
Type
Description
JTAG_TCK 100 I TTL
JTAG Clock
This pin should be pulled high through a 1 to 10 K 5% resistor
in normal operation.
JTAG_TDI 1 I PU TTL
JTAG Serial Data Input
If not using JTAG, this pin may be pulled high through a 1 to
10 K 5% resistor
JTAG_TDO 99 O TTL3 JTAG Serial Data Output
JTAG_TMS 3 I PU TTL
JTAG TMS Input
If not using JTAG, this pin may be pulled high through a 1 to
10 K 5% resistor
10
3.9 Reserved Signals
3.10 Voltage Control Pins
Table 8. Test Signals
Sub-
Type
Description
RESERVED_NC
4
5
6
8
9
10
13
14
15
17
26
49
52
53
98
NC NC
Reserved No Connect
This pin should be left disconnected in normal operation.
Connecting any of these pins may cause adverse effects and will
not be supported.
RESERVED_PD 82 I (T) TTL
Reserved, Pull-down
This signal used in the XOR chain. It should be pulled to VSS via
a 1 to10 K resistor.
Table 9. Voltage Control Pins
Sub-
Type
Description
CTRL_18 25 A A
1.9V LVR Power Output Reference
Voltage control for an external 1.9V PNP transistor in order to
produce a linearly-regulated supply.
If the 1.9V internal voltage regulator control circuit is not used,
connect the CTRL_18 pin to VSS through a 10 K resistor.
CTRL_12 23 A A
1.2V LVR Power Output Reference
Voltage control for an external 1.2V PNP transistor in order to
produce a linearly-regulated supply.
If the 1.2V internal voltage regulator control circuit is not used,
connect the CTRL_12 pin to VSS through a 10 K resistor.
11
3.11 Clock Generator Interface
3.12 Power/Ground Pins
Table 10. Clock Generator Related Signals
Sub-
Type
Description
XTAL1 21 I TTL
25 MHz Clock/Crystal Input
25 MHz +/- 50 ppm input. Can be connected to an oscillator or a
crystal. If using a crystal, XTAL2 must be connected as well. If a
crystal is used, it must be placed within -inch of the XTAL1 and
XTAL2 chip pins.
XTAL2 20 A-o A
25 MHz Crystal Output
Output of internal oscillator circuit used to drive crystal into
oscillation. If using an oscillator, XTAL2 is left as a no connect.
PHY_CLK_OUT 96 O TTL8
Clock Output
Output clock available for use by a 631xESB/632xESB or other
component(s).
The speed depends on the how LINK_A is sampled at
LAN_PWR_GOOD assertion:
If LINK_A is 0b, the clock speed is 62.5 MHz.
If LINK_A is 1b, the clock speed is 25 MHz.
The output clock can be disabled depending on how LINK_B is
sampled at LAN_PWR_GOOD assertion:
If LINK_B is 0b: Clock output enabled (pulled-down).
If LINK_B is 1b: Clock output disabled (no connect).
Table 11. Power/Ground Pins (Sheet 1 of 2)
Sub-
Type
Description
VSS
Central
Pad
G G
Ground Exposed-Pad*
The ground is provided through a large central pad on the
bottom side of the package.
VSS 89 G G Ground
VDDO
11
22
60
75
97
P P 3.3V I/O Ring Power
12
DVDD
2
7
12
16
59
64
69
74
P P 1.2V Digital Power
AVDD
29
30
35
40
45
46
P P 1.9V Analog Power for PHY
AVDDF
86
92
P P 1.9V Analog Power for Kumeran
AVDDR
24
51
P P 3.3V Analog Power for Voltage Regulators
Table 11. Power/Ground Pins (Sheet 2 of 2)
Sub-
Type
Description
13
3.13 Port B PHY Interface
Note: Port B on the 82563EB dual port device corresponds to connection to Port 1 on the 631xESB/
632xESB. There is no port B on the 82564EB.
Table 12. Port B PHY Interface Pins (Sheet 1 of 2)
Sub-
Type
Description
Connection on
82564EB
Single Port Device
MDIB_PLUS[0]
MDIB_MINUS[0]
48
47
A A
Media Dependent Interface for Port B,
bit 0
1000BASE-T:In MDI configuration,
MDI[0]+/- corresponds to
BI_DA+/- and in MDIX
configuration MDI[0]+/-
corresponds to BI_DB+/-.
100BASE-TX:In MDI configuration,
MDI[0]+/- is used for the
transmit pair and in MDIX
configuration MDI[0]+/- is
10BASE-T: In MDI configuration,
transmit pair and in MDIX
No-connect
MDIB_PLUS[1]
MDIB_MINUS[1]
44
43
A A
bit 1
BI_DB+/- and in MDIX
corresponds to BI_DA+/-.
100BASE-TX:In MDI configuration,
receive pair and in MDIX
used for the transmit pair.
10BASE-T: In MDI configuration,
receive pair and in MDIX
used for the transmit pair.
No-connect
14
3.14 Port B Kumeran Interface
MDIB_PLUS[2]
MDIB_MINUS[2]
42
41
A A
bit 2
BI_DC+/- and in MDIX
corresponds to BI_DD+/-.
100BASE-TX:Unused.
10BASE-T: Unused.
No-connect
MDIB_PLUS[3]
MDIB_MINUS[3]
39
38
A A
bit 3
BI_DD+/- and in MDIX
corresponds to BI_DC+/-.
100BASE-TX:Unused.
10BASE-T: Unused.
No-connect
LINK_B 54
I/O
PD
TTL8
PHY B Link Indication
This signal is registered at the rising edge
of PHY_PWR_GOOD, and is used to
determine whether PHY_CLK_OUT is
output. See the PHY_CLK_OUT pin for
details. Once PHY_PWR_GOOD is 1b,
LINK_B will always be an output and
indicate link up.
See Table 10
Table 12. Port B PHY Interface Pins (Sheet 2 of 2)
Sub-
Type
Description
Connection on
82564EB
Single Port Device
Table 13. Port B Kumeran Interface Pins
Signal Name
Pin Type
Sub-
Type
Description
Connection on
82564EB
Single Port Device
TXB_PLUS
TXB_MINUS
88
87
A-o A
Port B Kumeran TX Pair
Differential Kumeran Transmit interface.
No-connect
RXB_PLUS
RXB_MINUS
85
84
A-in A
Port B Kumeran RX Pair
Differential Kumeran Receive interface.
No-connect
15
3.15 Port B LEDs
Table 14. Port B LEDs
Sub-
Type
Description
Connection on
82564EB
Single Port
Device
LEDB_LINK_UP_N 63 O TTL12
LED 0 Link Up/Activity LED
This corresponds to port 1s LED#0
from the 631xESB/632xESB.
No-connect
LEDB_ACTIVITY_N 62 O TTL12
LED 1 10 Mbps LED
No-connect
LEDB_SPEED_100_
N
61 O TTL12
LED 2 100 Mbps LED
No-connect
LEDB_SPEED_1000_
N
58 O TTL12
LED 3 1000 Mbps LED
No-connect
LEDB_DUPLEX 57 O TTL12
LED 4 Full Duplex LED
This LED will light when port 1s PHY
is operating in Full Duplex Mode
No-connect
LEDB_TX_ACTIVITY 56 O TTL12
LED 5 Transmit Activity LED
transmits a packet
No-connect
LEDB_RX_ACTIVITY 55 O TTL12
LED 6 Receive Activity LED
receives a packet
This pin also functions as the clock
view pin and will output clock signals
required for IEEE conformance
testing. This pin should have a
stuffing option for a test header.
No-connect
16
17
4.0 Voltage, Temperature and Timing Specifications
4.1 Absolute Maximum Ratings
4.2 Recommended Operating Conditions
4.3 DC and AC Characteristics
Table 15. Absolute Maximum Ratings
a
Symbol Parameter Min Max Unit
V
DD
DC supply voltage -0.3 4.6 V
V
IN
Input voltage -1.0 V
DD
+ 0.3 V
I
IN
DC input pin current -10 10 mA
T
STG
Storage temperature -40 125 C
a. Maximum ratings are referenced to ground (VSS). Permanent device damage is likely to occur if the rat-
ings in this table are exceeded for an indefinite duration. These values should not be used as the limits for
normal device operations.
Table 16. Recommended Operating Conditions
Symbol Parameter Condition Min Typ Max Unit
T
OP
Operating Temperature Convection only
a
0 60 C
V
DD
Periphery Voltage Range 3.3V 3.00 3.30 3.60 V
V
D
Core Digital Voltage Range 1.2V 1.08 1.20 1.32 V
V
A
Analog V
DD
Range 1.9V 1.80 1.90 2.09 V
a. Higher ambient temperatures may be possible with forced airflow.
Table 17. DC and AC Characteristics (Sheet 1 of 2)
V
IL
Voltage input LOW - -0.5 - 0.8 V
V
IH
Voltage input HIGH - 2.0 -
V
DD
+0.3
V
V
OL
Voltage output LOW - - - 0.4 V
V
OH
Voltage output HIGH - 2.4 - - V
18
4.4 Power Supply Connections
There are two options in providing power to the 82563EB/82564EB:
Connecting the 82563EB/82564EB to three external power supplies with nominal voltages of
3.3V, 1.9V, and 1.2V covered in Section 4.4.1.
Powering the 82563EB/82564EB with only an external 3.3V supply, and using internal power
regulators from the 82563EB/82564EB combined with external PNP transistors to supply the
1.9V and 1.2V levels. covered in Section 4.4.3.
4.4.1 External LVR Power Delivery
The following power supply requirements apply to designs in which the 82563EB/82564EB is
supplied by external voltage regulators. These systems do not use the internal regulator logic built
into the 82563EB/82564EB as described in Section 4.4.3.
I
OL
Output current LOW
3mA drivers (TTL3)
6mA drivers (TTL6)
12mA drivers (TTL12)
V
OL
V
OL
V
OL
3
6
12
- -
mA
mA
mA
I
OH
Output current HIGH
3mA drivers (TTL3)
6mA drivers (TTL6)
12mA drivers (TTL12)
V
OH
V
OH
V
OH
-3
-6
-12
- -
mA
mA
mA
I
IN
Input Current
TTL inputs
Inputs with pull-down resistors
TTL inputs with pull-up resistors
V
IN
= V
DD
or V
SS
V
IN
= V
DD
V
IN
= V
SS
-10
23
-23
1
10
72
-72
A
A
A
I
OZ
3-state output leakage current V
OH
= V
DD
or V
SS
-10 1 10 A
C
IN
Input capacitance
Any input and bi-
directional buffer
- 2.5 - pF
C
OUT
Output capacitance Any output buffer - 2.0 - pF
R
PUD
Internal Pull-up/down Resistor
value
- 50 - 130 k
Table 17. DC and AC Characteristics (Sheet 2 of 2)
19
Table 18. 3.3V External Power Supply Parameters
Title Description Min Max Units
Rise Time Time from 10% to 90% mark 2 200 ms
Monotonicity Voltage dip allowed in ramp - 300 mV
Slope
Ramp rate at any given time between
10% and 90%
Min: 0.8*V(min)/Rise time (max)
Max: 0.8*V(max)/Rise time (min)
- 1500 mV/ms
Operational Range
Voltage range for normal operating
conditions
3.0 3.6 V
Ripple
Maximum voltage ripple (peak to
peak)
a
- 100 mV
Overshoot Maximum overshoot allowed - 660 mV
Overshoot Settling
Time
Maximum overshoot allowed
duration.
(At that time delta voltage should be
lower than 5 mV from steady state
voltage)
- 3 ms
a. The peak to peak output rippled is measured at 20 MHz Bandwidth within the operational range.
Slope
10% and 90%
- 1500 mV/ms
Operational Range
conditions
1.80 2.09 V
Ripple
peak)
a
- 100 mV
Overshoot Settling
Time
duration.
lower than 5 mv from steady state
voltage)
- 1.5 ms
Decoupling
Capacitance
Capacitance range 5 - F
Capacitance ESR
Equivalent series resistance of output
capacitance
- 100 M
a. The peak to peak output ripple is measured at 20 MHz Bandwidth within the operational range.
20
4.4.2 Power Sequencing with External Regulators
The following power-on/off sequence should be applied when external power supplies are in use.
Designs must comply with the required power sequence to avoid risk of either latch-up or forward
biased internal diodes.
The general rule of thumb is that the 82563EB/82564EB power sequencing should power up the
three power rails in the following order: 3.3V 1.9V 1.2V. However, if this general guideline
is not followed, there are specific requirements that must be adhered that are listed in the following
two sections.
4.4.2.1 External LVR Power up Sequencing and Tracking
Sequencing of the external supplies during power up may be necessary to ensure that the device is
not electrically overstressed and does not latch-up. These requirements are shown in Figure 3.
The 82563EB/82564EB core voltage (1.2V) cannot exceed the 3.3V supply by more than 0.5V
at any time during the power up. The 82563EB/82564EB core voltage (1.2V) can not exceed
the 1.9V supply by more than 0.5V at any time during the power up. The core voltage is not
required to begin ramping before the 3.3V or the 1.9V supply.
The 82563EB/82564EB analog voltage (1.9V) cannot exceed the 3.3V supply by more than
0.5V at any time during the power up. The analog voltage is not required to begin ramping
before the 3.3V supply.
Rise Time Time from 10% to 90% mark 1.5 200 ms
Slope
10% and 90%
- 1500 mV/ms
Operational Range
conditions
1.08 1.32 V
Ripple
peak)
a
- 100 mV
Overshoot Duration
duration.
voltage)
- 1 ms
Decoupling
Capacitance
Capacitance range 5 - F
Capacitance ESR
Equivalent series resistance of output
capacitance
- 100 M
a. The peak to peak output ripple is measured at 20 MHz Bandwidth within the operational range. The ripple must be included
within the operational range.
21
Figure 3. 82563EB/82564EB power up sequencing with external regulators
4.4.2.2 External LVR Power down Sequencing
There are no specific power down sequencing and tracking requirements for the 82563EB/
82564EB silicon. The risk of latch-up or electrical overstress is small because only the charge
stored in the decoupling capacitors is left in the system.
4.4.3 Internally-Generated Power Delivery
The 82563EB/82564EB has two internal linear voltage regulator controllers. The controllers use
external transistors to generate 2 of the 3 required voltages: 1.9V (nominal) and 1.2V (nominal).
These two voltages are stepped-down from a 3.3V source.
3.3 V
1.2 V
Max
Difference
0.5 V
1.9 V
Max
Difference
0.5 V
V
t
Slope
10% and 90%
- 1500 mV/ms
Operational Range
conditions
3.0 3.6 V
22
4.4.4 Internal LVR Power Sequencing
All supplies should rise monotonically. Sequencing of the supplies is controlled by the 82563EB/
82564EB.
4.4.4.1 Power up Sequencing and Tracking
During power up, the sequencing and tracking of the internally controlled supplies (1.9V and 1.2V)
is controlled by the 82563EB/82564EB. No specific motherboard requirements are necessary to
prevent electrical overstress or latch-up.
The 82563EB/82564EB analog voltage (1.9V) will never exceed the 3.3V supply at any time
during the power up. This is because the 1.9V supply is generated from the 3.3V supply when
using the internal voltage regulator control logic (see Figure 5 and Figure 6 for a schematic of
the internal LVR circuit). The 1.9V supply will track the 3.3V ramp.
The 82563EB/82564EB core voltage (1.2V) will never exceed the 3.3V at any time during the
power up. This is because the 1.2V supply is generated from the 3.3V supply when using the
internal voltage regulator control logic (see Figure 5 and Figure 6 for a schematic of the
internal LVR circuit). The 1.2V ramp is delayed internally to prevent it from exceeding the
1.9V and 3.3V supply at any time. The delay is proportional to the slope of the 3.3V ramp.
The delay is approximated by T
ramp
(3.3V)*0.25 < T
delay
(1.2V) < T
ramp
(3.3V)*0.75. T
ramp
is
defined to the ramp rate of the 3.3V input to the internal voltage regulator circuit.
Ripple
peak)
a
- 100 mV
Overshoot Settling
Time
duration.
voltage)
- 3 ms
a. The peak to peak output ripple is measured at 20 MHz Bandwidth within the operational range.
23
Figure 4. 82563EB/82564EB power up sequencing with internal regulators
4.4.4.2 Internal LVR Power down Sequencing
There are no specific power down sequencing and tracking requirements for the 82563EB/
82564EB device. The risk of latch-up or electrical overstress is small because only the only charge
storing in decoupling capacitors is left in the system.
4.4.4.3 82563EB/82564EB BOM for Internal Voltage Regulators
1.2 V
3.3 V
1.9 V
Tdelay
V
t
Table 22. 82563EB/82564EB BOM (Bill of Material) of Components for Internal Regulator
Description Quantity
Recommended Component
Manufacturer Part Number Package
PNP Transistor
For 1.2V LVR
1 Philips BCP-69-16 SOT-223
PNP Transistor
For 1.9V LVR
1 Philips BCP-69-16 SOT-223
24
4.4.4.4 1.9V Internal LVR Specification
4.4.4.5 1.2V Internal LVR Specification
Table 23. 1.9V Internal LVR Specification
Parameter
Value
Units Comments
Minimum Maximum
Input Voltage 3.0 3.6 V -
Input Capacitance 4.7 - F -
Input Capacitance ESR - 100 M -
Load Current 1 - A V
OUT
= 1.900 V
Output Voltage Tolerance -5 +10 % -
Output Capacitance 4.7 - F -
Output Capacitance ESR
a
- 100 M -
Current Consumption during power up - 0.5 mA -
Current Consumption during power down - 0.5 mA -
Peak to Peak output Ripple
b
- 100 mV -
PSRR - 20 dB -
Turn-On Time 0.1 1 ms -
External PNP hFE 100 N/A - -
a. The use of Tantalum capacitors is not recommended.
b. The peak to peak output rippled is measured at 20 MHz Bandwidth within the operational range.
Table 24. 1.2V Internal LVR Specification (Sheet 1 of 2)
Parameter
Value
Units Comments
Minimum Maximum
Input Voltage 3.0 3.6 V -
Input Capacitance 4.7 - F -
Input Capacitance ESR - 100 M -
Load Current 1 - A V
OUT
= 1.20 V
25
4.4.4.6 PNP Transistor Specification for Internal LVR
4.4.4.7 Internal LVR Board Schematic
When using the internal voltage regulator controllers built into the 82563EB/82564EB, series
resistors may need to be placed in series with the collector in order to prevent the PNP transistors
from overheating. These series resistors dissipate a portion of the power that would otherwise be
dissipated by the PNP devices. The value and power rating of the resistors must be carefully chosen
to balance thermal limits against the PNP characteristics against total current draw. The regulator
must never drop below the minimum V
ce
and out of the linear region.
Output Voltage Tolerance -10 +10 % -
Output Capacitance 4.7 - F -
Output Capacitance ESR
a
- 100 M -
Current Consumption during power up - 0.5 mA -
Current Consumption during power down - 0.5 mA -
Peak to Peak output Ripple
b
- 100 mV -
PSRR - 20 dB -
Turn-On Time 0.1 1 ms -
External PNP hFE 100 - - -
a. The use of Tantalum capacitors is not recommended.
b. The peak to peak output ripple is measured at 20 MHz Bandwidth within the operational range.
Table 24. 1.2V Internal LVR Specification (Sheet 2 of 2)
Parameter
Value
Units Comments
Minimum Maximum
Table 25. PNP Specification
V
ce,sat
Collector-emitter saturation voltage - 0.5 V
I
c
(max) Collector current, maximum sustained - 1000 mA
I
b
Base current, maximum sustained - 10 mA
V
be
Base-emitter on voltage - 1 V
T
jmax
Maximum junction temperature - 150 C
Power
Dissipation
Maximum total power dissipation - 1.35 W
hFE DC Current gain 100 - -
fT Current Gain Product Bandwidth 10 - MHz
26
The effective resistance of the pass resistors should be approximately 0.5 and have a combined
power dissipation rating of 0.5 Watts for the 82563EB. Figure 5 shows the recommended
implementation.
Figure 5. 82563EB 1.9V and 1.2V internal LVR schematic
Note: No resistors are required for the 82564EB as shown in Figure 6 due to the reduction in current
demand. See Figure 4.9 for more details regarding power consumption.
Figure 6. 82564EB 1.9V and 1.2V internal LVR schematic
4.5 Link (MDI) Interface
The Media Dependent Interface pins (MDIA_PLUS[3:0], MDIA_MINUS[3:0],
MDIB_PLUS[3:0], MDIB_MINUS[3:0]) are analog pins conforming to the IEEE 802.3ab (802.3
Clause 40) requirements.
CTRL_18
Vcc3_3
Vcc1_9
1.0ohm, 5%, 1/4W
1.0ohm, 5%, 1/4W
Note: PNP needs 0.5inchby
0.5inchthermal relief pad
CTRL_12
Vcc3_3
Vcc1_2
1.0ohm, 5%, 1/4W
1.0ohm, 5%, 1/4W
Note: PNP needs 0.5inchby
0.5inchthermal relief pad
CTRL_18
Vcc3_3
Note: PNP needs 0.5 inch by
0.5 inch thermal relief pad
Vcc1_9
CTRL_12
Vcc3_3
Note: PNP needs 0.5 inch by
0.5 inch thermal relief pad
Vcc1_2
Table 26. Link (MDI) Interface Electrical Specification
Symbol Parameter Pins Condition Min Typ Max Unit
V
ODIFF
Absolute peak differ-
ential output voltage
MDI*[1:0]
MDI*[1:0]
MDI*[1:0]
MDI*[3:0]
10Base-T no cable
10Base-T cable
100Base-TX mode
1000Base-T
a
2.2
585
b
0.950
0.67
2.5
-
1
0.75
2.8
-
1.050
0.82
V
mV
V
V
Overshoot MDI[1:0] 100Base-TX mode 0 - 5% (V)
Amplitude Symmetry
(positive / negative)
MDI[1:0] 100Base-TX mode 0.98x - 1.02x
V
+
/
V
-
27
4.6 Kumeran (Serial) Interface
The Kumeran interface is electrically compatible with the SERDES implemented in 1000Base-BX
applications, as defined in the PICMG 3.1 Specification, Version 1.0, Chapter 5, Backplane
Physical Layers Interfaces. It also implements electrical idle as described in section 3.5.4. As part
of the electrical idle implementation, the Kumeran interface also needs to be able to detect when
the 631xESB/632xESB is in electrical idle.
4.6.1 Transmit
The transmit specifications are measured with the following test load.
V
IDIFF
Peak differential input
voltage
MDI[1:0] 10Base-T 585
c
- - mV
Signal Detect Assertion MDI[1:0] 100Base-TX 460
d
1000
mV
peak
-
peak
Signal Detect De-
assertion
MDI[1:0] - 200 360
e
mV
peak
-
peak
a. IEEE 802.3ab Figure 40-19 points A&B.
b. IEEE 802.3 Clause 14, Figure 14.9 shows the template for the far end wave form. This template allows as little as 495mV peak differential
voltage at the far end receiver.
c. See IEEE 802.3, Clause 14, Figure 14.17 for the template for the receive wave form.
d. The ANSI TP-PMD specification requires that any received signal with peak-to-peak differential amplitude greater than 1000 mV should turn on
signal detect. The 82563EB/82564EB will accept signals typically with 460 mV peak-to-peak differential amplitude.
e. The ANSI TP-PMD specification requires that any received signal with peak-to-peak differential amplitude less than 200 mV should de-assert
signal detect. The 82563EB/82564EB will reject signals typically with 360 mV peak-to-peak differential amplitude
Table 26. Link (MDI) Interface Electrical Specification
Symbol Parameter Pins Condition Min Typ Max Unit
Table 27. Kumeran (Serial) Transmit Specifications
Symbol Parameter Min Typ Max Unit Notes
Data Rate (original data) 999.9 1000 1000.1 Mb/s 1000 mb/s 100 ppm
Signaling Speed (raw data
rate of encoded data)
1249.875 1250 1250.125 V 1250 mb/s 100 ppm
Clock Tolerance -100 - +100 ppm
V
DIFFp-p
Differential Output
Amplitude (peak to peak)
750 - 1350 mV
V
DIFFp
Differential Output
Amplitude (peak)
375 - 675 mV Equivalent to V
DIFFp-p
Return Loss 10 - - dB
Impedance at Connection 70 100 130
28
The differential peak and differential peak to peak voltage is defined as follows:
V
DIFFp
= max (|V
+
- V
-
|)
V
DIFFp-p
= (2* V
DIFFp
)
In addition, the transmitter must meet the following eye diagram.
Figure 7. Kumeran (Serial) Transmit Eye Diagram
4.6.2 Receive
The receiver operates with less than 10
-12
Bit Error Rate (BER) when the received signal meets
valid voltage and timing specifications and is delivered from a balanced 100 source.

675mV
375mV
0mV
-375mV
-675mV
1.12 2.72 5.28 6.88 0 8
Time (ns)
D
i
f
f
e
r
e
n
t
i
a
l

a
m
p
l
i
t
u
d
e
Table 28. Kumeran (Serial) Receive Specifications
Data Rate (original data) 999.9 1000 1000.1 Mb/s 1000 mb/s 100 ppm
Signaling Speed (raw
data rate of encoded
data)
1249.875 1250 1250.125 V 1250 mb/s 100 ppm
Clock Tolerance -100 - +100 ppm
V
SENSp-p
Sensitivity (differential
peak to peak)
200 - 1350 mV
V
SENSp
Sensitivity (differential
peak)
100 - 675 mV Equivalent to V
SENSp-p
Differential Skew - - 175 ps
Differential Return Loss 10 - -
29
Note: TDR measurements are recorded times. Record time = TDR transmit time *2.
The receiver expects to receive a signal meeting the following eye diagram.
Figure 8. Kumeran (Serial) Receive Eye Diagram
4.6.3 Electrical Idle
The Kumeran interface also implements electrical idle. As a result, it needs to:
Detect when the 631xESB/632xESB has gone into electrical idle
Go into electrical idle
Common Mode Return
Loss
6 - - dB
TDR Rise - 85 -
Impedance at Connection 70 100 130
Table 28. Kumeran (Serial) Receive Specifications

675mV
100mV
0mV
-100mV
-675mV
2.4 4 5.6 0 8
Time (ns)
D
i
f
f
e
r
e
n
t
i
a
l

a
m
p
l
i
t
u
d
e
30
4.6.3.1 Electrical Idle Detection
The 82563EB/82564EB detects that the 631xESB/632xESB has gone into electrical idle when it
senses that the differential voltage has gone below and is remaining below a threshold voltage.
Note: When the differential peak to voltage is below 65 mV (37.5 mV differential peak), the 82563EB/
82564EB detects that the 631xESB/632xESB has gone into electrical idle. This voltage
corresponds to the minimum output voltage in Electrical Idle plus some noise margin.
When the differential peak to peak voltage is above 200 mV (100 mV differential peak), the
82563EB/82564EB detects that the 631xESB/632xESB is not in electrical idle. This voltage
corresponds to the minimum valid receive level.
4.6.3.2 Electrical Idle Output
The following parameters relate to electrical idle output and the transition into and out of electrical
idle.
Table 29. Kumeran (Serial) Electrical Idle Detection
Symbol Parameter Min Typ Max Unit
V
RX_IDLE_DET_DIFFp-p
Voltage range to detect electrical idle (differ-
ential peak to peak)
65 - 200 mV
V
RX_IDLE_DET_DIFFp
Voltage range to detect electrical idle (differ-
ential peak to peak)
37.5 - 100 mV
Table 30. Kumeran (Serial) Electrical Idle Output
Symbol Parameter Min Typ Max Unit
V
TX_IDLE_DIFFp
Electrical Idle peak output voltage. 0 - 20 mV
V
TX_IDLE_MON
Minimum time spent in electrical idle. 400 - 100 mV
V
TX_IDLE_SET_TO_IDLE
Maximum time for to transition to a valid
electrical idle after electrical idle detected.
1 ms
T
TX_IDLE_TO-DIFF-DATA
Maximum time to transition to valid transmit
after leaving electrical idle.
340 s
31
4.7 Crystal
The quartz crystal is strongly recommended as a low cost and high performance choice with the
82563EB/82564EB device. Quartz crystals are the mainstay of frequency control components and
are available from numerous vendors in many package types with various specification options
4.7.1 External Clock Oscillator
If using an external oscillator to provide a clock to the 82563EB/82564EB, the connection shown
in Figure 9 must be used. Note that the XTAL2 output of the 82563EB/82564EB must not be
connected. The XTAL1 input receives the output of the oscillator directly; AC coupling is not
recommended.
Figure 9. External Clock Oscillator Connectivity to 82563EB/82564EB
Table 31. Crystal Parameters
Parameter Suggested Value Conditions
Vibrational Mode Fundamental
Nominal Frequency 25.000 MHz at 25C
Frequency Tolerance
30 ppm recommended
50 ppm across the entire operating
temperature range (required by IEEE
specifications)
at 25C
Temperature Tolerance 30 ppm at 0C to 70C
Calibration Mode Parallel
Load Capacitance 27 pF
Shunt Capacitance 6 pF maximum
Equivalent Series Resistance 50 maximum at 25 MHz
Drive Level 750 W
Aging 5 ppm per year maximum
3.3V
82563EB/82564EB
XTAL1
XTAL2
32
4.8 Reset and Initial Clock Timing
PHY_PWR_GOOD must be low throughout the time that the power supplies are ramping. This
guarantees that the 82563EB/82564EB resets cleanly.
Figure 10. 82563EB/82564EB Reset Timing
Table 32. Specification for External Clock Oscillator
Parameter Name Symbol Value Conditions
Frequency f
o
25.0 [MHz] @25 [C]
Swing V
p-p
3.3 0.3 [V] -
Frequency Tolerance f/f
o
30 [ppm] -0 to +70 [C]
Operating Temperature T
opr
-0 to +70 [C] -
Aging f/f
o
5 ppm per year -
DVDD (1.2V)
PHY _PWR _GOOD
XTAL1
Tppg
Txoc
PHY _CLK _OUT
Oscillator Stable
Power Stable
Tpco
AVDD, AVDDF (1.9V)
VDDO, AVDDR (3.3V)
33
There are no required timing relationships between PHY_RESET_N, PHY_SLEEP, and either
PHY_PWR_GOOD, the power supply being stable, or the oscillator being stable. The 82563EB/
82564EB will come out of reset when both PHY_PWR_GOOD is asserted (1b) and
PHY_RESET_N is deasserted (1b). It will be active when PHY_PWR_GOOD is asserted (1b),
PHY_RESET_N is deasserted (1b), and PHY_SLEEP is deasserted (0b).
4.9 Power Consumption
The 82563EB/825654EBs power consumption (Tables 34 through 37) is the sum of each ports
power consumption. A ports power consumption depends on whether the ports logic, PHY, and
Kumeran are operational, and the 82563EB/825654EBs operating speeds. These in turn, depend
on the following factors:
Table 33. Reset Specification
PHY_PWR_GOOD pulse
Minimum pulse width for
LAN_PWR_GOOD
100 - s
T
ppg
Minimum time PHY_PWR_GOOD must be
low after power supply is in operating
range
100 - s
T
xoc
Time from oscillator stable to
PHY_PWR_GOOD assertion, when using
an external oscillator.
100 - s
T
pco
Time from PHY_PWR_GOOD assertion
until the 82563EB/82564EB outputs the
PHY_CLK_OUT.
- 350 s
PHY_PWR_GOOD input
Powers off the entire chip (including PHY_CLK_OUT) when 0b. It has priority
over PHY_RESET_N or PHY_SLEEP.
PHY_RESET_N input When 0b, the entire chip is held in reset except PHY_CLK_OUT.
PHY_SLEEP input When 1b the entire chip is powered down, except PHY_CLK_OUT.
Port Disable Register
The ports PHY and Kumeran can be disabled by writing a 1b to the Disable
Port bit of the Power Management Control register.
PHY Power Down
ThE 82563EB/82564EB can be powered down with an indication over the
Kumeran bus or by writing a 1b to the Control Registers Power Down bit.
Link Down
When the link is required but the link is down the 82563EB/82564EB remains
in energy detect mode, attempting to detect energy from the link partner.
Speed
The 82563EB/82564EB uses progressively more power as the speed
increases from 10 Mb/s to 100 Mb/s to 1000 Mb/s. Speed is normally based on
auto-negotiation with the link partner, but may be forced or influenced by the
power state.
Power State
The power state can be used in conjunction with the Low Power Link Up and
Auto-Negotiation 1000 Disable to control the 82563EB/82564EBs speed.
Kumeran Electrical Idle Nothing is transmitted on the differential pairs.
34
Table 34. Power Supply Characteristics - D0a (Both Ports)
D0a (Both Ports)
Unplugged/No Link 10 Mb/s Operation 100 Mb/s Operation 1000 Mb/s Operation
Typ Icc
(mA)
Max Icc
(mA)
Typ Icc
(mA)
Max Icc
(mA)
Typ Icc
(mA)
Max Icc
(mA)
Typ Icc
(mA)
Max Icc
(mA)
3.3 V 12 47 20 22 22 23 35 36
1.9 V 11 11 33 33 79 79 411 411
1.2 V 20 26 140 140 165 165 345 345
Total
Device
Power
145 mW 635 mW 878 mW 2610 mW
Table 35. Power Supply Characteristics - D3cold - Wake Up Enabled (Both Ports)
D3cold - Wake Up Enabled (Both Ports)
D3cold - Wake Up
Disabled (Both Ports)
Unplugged/No Link 10 Mb/s Operation 100 Mb/s Operation
Typ Icc
(mA)
Max Icc
(mA)
Typ Icc
(mA)
Max Icc
(mA)
Typ Icc
(mA)
Max Icc
(mA)
Typ Icc
(mA)
Max Icc
(mA)
3.3 V 12 47 21 22 22 23 12 12
1.9 V 11 11 33 33 79 79 11 11
1.2 V 20 26 140 140 166 166 12 12
Total
Device
Power
145 mW 640 mW 879 mW 115 mW
Table 36. Power Supply Characteristics - Uninitialized/Disabled
Uninitialized/Disabled
D(n) Uninitialized
(PHY PWR GOOD =
0b)
Disabled
a
(via Flash Address)
a. Equivalent to PHY_SLEEP = 1b and/or PHY_RESET_N = 0b.
Typ Icc
(mA)
Max Icc
(mA)
Typ Icc
(mA)
Max Icc
(mA)
3.3 V 10 13 11 13
1.9 V 18 20 19 19
1.2 V 2 2 7 12
Total
Device
Power
116 mW 120 mW
35
Table 37. Power Supply Characteristics - Complete Subsystem
Complete Subsystem
(Including Magnetics, LED, and Regulator Circuits)
10 Mb/s Operation 100 Mb/s Operation 1000 Mb/s Operation
Typ lcc Max lcc Typ lcc Max lcc Typ lcc Max lcc
3.3 V 27 28 35 37 60 63
1.9 V 33 33 78 79 413 413
1.2 V 280 280 220 220 704 704
Subsystem
3.3 V
Current
1121 mW 1107 mW 3883 mW 4248 mW
36
37
5.0 Package and Pinout Information
This section describes the 82563EB/82564EB device physical characteristics. The pin number-to-
signal mapping is indicated beginning with Section 5.3.
5.1 Package Information
The package used for the 82563EB/82564EB is a 100-pin, 14 mm x 14 mm TQFL with an
Exposed-Pad*. An Exposed-Pad* is a central pad on the bottom of the package that serves as a
ground and thermal connection.
Figure 11. Mechanical Information
38
Figure 12. Mechanical Specifications and Notes
39
5.2 Thermal Specifications
The 82563EB/82564EB device is specified for operation when the ambient temperature (T
A
) is
within the range of 0
C to 60

C.
The maximum junction temperature is 120 C. The maximum ambient temperature with airflow
and/or a heatsink can be calculated using the thermal coefficient data below and the power
specification (see section 4.7)
T
C
(case temperature) is calculated using the equation:
T
C
= T
A
+ P (
JA
-
JC
)
T
J
(junction temperature) is calculated using the equation:
T
J
= T
A
+ P
JA

P (power consumption) is calculated by using the typical I
CC
, as indicated in Table 38, and nominal
V
CC
. The preliminary thermal resistances are shown in Table 38.
Table 38. Thermal Characteristics
Value @ Given Airflow (m/s)
Symbol Parameter 0 1 2 3 Units
J
A
Thermal Resistance, Junction to Ambient 26.1 22.9 21.7 21.1 C/watt
J
C
Thermal Resistance, Junction to Case 12.7 - - - C/watt
40
5.3 Pinout Information
Table 39. 82563EB/82564EB Pinout by Pin Number Order (Sheet 1 of 3)
Pin
82563EB
Dual Port
82564EB
Single Port
a
External
Strapping
b
1 JTAG_TDI - 1 - 10 K, 5%, p/u
2 DVDD - -
3 JTAG_TMS - 1 - 10 K, 5%, p/u
4 RESERVED_NC - -
5 RESERVED_NC - -
6 RESERVED_NC - -
7 DVDD - -
8 RESERVED_NC - -
9 RESERVED_NC - -
10 RESERVED_NC - -
11 VDDO - -
12 DVDD - -
13 RESERVED_NC - -
14 RESERVED_NC - -
15 RESERVED_NC - -
16 DVDD - -
17 RESERVED_NC - -
18 MDIO_ADD[2] - 1 - 10 K, 5%, p/d
19 MDIO_ADD[3] - 1 - 10 K, 5%, p/d
20 XTAL2 - -
21 XTAL1 - -
22 VDDO - -
23 CTRL_12 - -
24 AVDDR - -
25 CTRL_18 - -
26 RESERVED_NC - -
27 MDIA_PLUS[0] - -
28 MDIA_MINUS[0] - -
29 AVDD - -
30 AVDD - -
31 MDIA_PLUS[1] - -
33 MDIA_PLUS[2] - -
41
35 AVDD - -
36 MDIA_PLUS[3] - -
38 MDIB_MINUS[3] RESERVED_NC -
39 MDIB_PLUS[3] RESERVED_NC -
40 AVDD - -
45 AVDD - -
46 AVDD - -
49 RESERVED_NC - -
50 PHY_REF - 4.99 K, 1%, p/d
51 AVDDR - -
52 RESERVED_NC - -
53 RESERVED_NC - -
54 LINK_B - See Table 10
55 LEDB_RX_ACTIVITY RESERVED_NC test point
56 LEDB_TX_ACTIVITY RESERVED_NC -
57 LEDB_DUPLEX RESERVED_NC -
58 LEDB_SPEED_1000_N RESERVED_NC -
59 DVDD - -
60 VDDO - -
61 LEDB_SPEED_100_N RESERVED_NC -
62 LEDB_ACTIVITY_N RESERVED_NC -
63 LEDB_LINK_UP_N RESERVED_NC -
64 DVDD - -
65 LINK_A - See Table 10
66 LEDA_RX_ACTIVITY - test point
67 LEDA_TX_ACTIVITY - -
68 LEDA_DUPLEX - -
69 DVDD - -
70 LEDA_SPEED_1000_N - -
71 LEDA_SPEED_100_N - -
Pin
82563EB
Dual Port
82564EB
Single Port
a
External
Strapping
b
42
72 LEDA_ACTIVITY_N - -
73 LEDA_LINK_UP_N - -
74 DVDD - -
75 VDDO - -
76 MDIO - -
77 MDC - 1 - 10 K, 5% p/d
78 MDIO_ADD[0] - 1- 10 K, 5% p/d
79 MDIO_ADD[1] - 1 - 10 K, 5% p/d
80 PHY_SLEEP - 1 - 10 K, 5% p/d
81 PHY_RESET_N - 1 - 10 K, 5% p/u
82 RESERVED_PD - 1 - 10 K, 5% p/d
83 PHY_PWR_GOOD - -
84 RXB_MINUS RESERVED_NC -
85 RXB_PLUS RESERVED_NC -
86 AVDDF - -
87 TXB_MINUS RESERVED_NC -
88 TXB_PLUS RESERVED_NC -
89 VSS - -
90 TXA_PLUS, - -
91 TXA_MINUS - -
92 AVDDF - -
93 RXA_PLUS, - -
94 RXA_MINUS - -
95 TEST_JTAG - 1 - 10 K, 5% p/u
96 PHY_CLK_OUT - -
97 VDDO - -
98 RESERVED_NC - -
99 JTAG_TDO - -
100 JTAG_TCK - 1 - 10 K, 5%,p/d
Central
Pad
VSS - -
a. The 82564EB device uses the same name as the 82563EB device unless otherwise specified.
b. For those external strappings that state 1 - 10 K, 5%, the recommended value within that range
is 3.3 K, 5%.
Pin
82563EB
Dual Port
82564EB
Single Port
a
External
Strapping
b
43
5.4 Interface Diagrams
Figure 13. 82563EB/82564EB Interfaces
Kumeran Port A
Clocks
MDIO Interface
PHY A
TXA_PLUS
Port A LEDs
TXA _MINUS
RXA _PLUS
RXA _MINUS
MDIA_PLUS [3: 0]
MDIA_MINUS [3: 0]
Chipwide
Power /Ground
Reset
/ Power Down
/ Initialization
MDC
MDIO
MDIO_ADD[3: 0]
XTAL 1
XTAL 2
PHY _CLK _OUT
PHY _PWR _GOOD
PHY _RESET _N
PHY _SLEEP
LEDA _LINK _UP _N
JTAG _TCK
JTAG _TDI
JTAG _TDO
JTAG _TMS
JTAG
DVDD (1. 2V)
AVDD (1. 9V)
VDDO (3. 3V)
VSS
LINK _A
PHY B Kumeran Port B
Voltage
Control
CTRL _12
CTRL _18
LINK _B
MDIB_PLUS [3: 0]
MDIB_MINUS [3: 0]
TXB _PLUS
TXB _MINUS
RXB _PLUS
RXB _MINUS
LEDA _ACTIVITY _N
LEDA _SPEED _100_N
LEDA _SPEED _1000 _N
LEDA _DUPLEX _N
LEDA _TX _ACTIVITY _N
LEDA _RX _ACTIVITY _N
Port B LEDs
AVDDF (1. 9V)
AVDDR (3. 3V )
PHY Reference PHY _REF
LEDB _LINK _UP _N
LEDB _ACTIVITY _N
LEDB _SPEED _100_N
LEDB _SPEED _1000 _N
LEDB _DUPLEX _N
LEDB _TX _ACTIVITY _N
LEDB _RX _ACTIVITY _N
TEST _JTAG
44
5.5 Visual Pin Assignments
Figure 14. 82563EB Dual Port Gigabit Platform LAN connect Pinout (Top View)
82563EB
1
0
0
9
9
9
8
9
7
9
6
9
5
9
4
9
3
9
2
9
1
9
0
8
9
8
8
8
7
8
6
8
5
8
4
8
3
8
2
8
1
8
0
7
9
7
8
7
7
7
6
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
2
6
2
7
2
8
2
9
3
0
3
1
3
2
3
3
3
4
3
5
3
6
3
7
3
8
3
9
4
0
4
1
4
2
4
3
4
4
4
5
4
6
4
7
4
8
4
9
5
0
LEDA_SPEED_100_N
DVDD
LEDA_SPEED_1000_N
LEDA_DUPLEX_N
LEDA_TX_ACTIVITY_N
LEDA_RX_ACTIVITY_N
LINK_A
DVDD
LEDB_LINK_UP_N
LEDB_ACTIVITY_N
LEDB_SPEED_100_N
VDDO
DVDD
LEDB_SPEED_1000_N
LEDB_DUPLEX_N
LEDB_TX_ACTIVITY_N
DVDD
LEDB_RX_ACTIVITY_N
LINK_B
XTAL2
XTAL1
VDDO
RESERVED_NC
RESERVED_NC
AVDDR
M
D
I
O
_
A
D
D
[
1
]
J
T
A
G
_
T
D
O
DVDD
J
T
A
G
_
T
C
K
JTAG_TDI
JTAG_TMS
RESERVED_NC
RESERVED_NC
DVDD
RESERVED_NC
RESERVED_NC
RESERVED_NC
RESERVED_NC
DVDD
VDDO
RESERVED_NC
DVDD
RESERVED_NC
RESERVED_NC
RESERVED_NC
MDIO_ADD[2]
MDIO_ADD[3]
CTRL_12
AVDDR
CTRL_18
M
D
I
O
_
A
D
D
[
0
]
M
D
C
M
D
I
O
V
D
D
O
P
H
Y
_
C
L
K
_
O
U
T
T
E
S
T
_
J
T
A
G
R
X
A
_
M
I
N
U
S
R
X
A
_
P
L
U
S
A
V
D
D
F
T
X
A
_
M
I
N
U
S
T
X
A
_
P
L
U
S
V
S
S
T
X
B
_
P
L
U
S
T
X
B
_
M
I
N
U
S
A
V
D
D
F
R
X
B
_
P
L
U
S
R
X
B
_
M
I
N
U
S
P
H
Y
_
P
W
R
_
G
O
O
D
R
E
E
R
V
E
D
_
P
D
R
E
S
E
R
V
E
D
_
N
C
P
H
Y
_
R
E
S
E
T
_
N
P
H
Y
_
S
L
E
E
P
VDDO
R
E
S
E
R
V
E
D
_
N
C
M
D
I
A
_
P
L
U
S
[
0
]
M
D
I
A
_
M
I
N
U
S
[
0
]
A
V
D
D
A
V
D
D
M
D
I
A
_
P
L
U
S
[
1
]
M
D
I
A
_
M
I
N
U
S
[
1
]
M
D
I
A
_
P
L
U
S
[
2
]
M
D
I
A
_
M
I
N
U
S
[
2
]
A
V
D
D
M
D
I
A
_
P
L
U
S
[
3
]
M
D
I
A
_
M
I
N
U
S
[
3
]
M
D
I
B
_
M
I
N
U
S
[
3
]
M
D
I
B
_
P
L
U
S
[
3
]
A
V
D
D
M
D
I
B
_
M
I
N
U
S
[
2
]
M
D
I
B
_
P
L
U
S
[
2
]
M
D
I
B
_
M
I
N
U
S
[
1
]
M
D
I
B
_
P
L
U
S
[
1
]
A
V
D
D
A
V
D
D
M
D
I
B
_
M
I
N
U
S
[
0
]
M
D
I
B
_
P
L
U
S
[
0
]
R
E
S
E
R
V
E
D
_
N
C
P
H
Y
_
R
E
F
LEDA_LINK_UP_N
LEDA_ACTIVITY_N
45
Figure 15. 82564EB Single Port Gigabit Platform LAN Connect Pinout (Top View)
82564EB
1
0
0
9
9
9
8
9
7
9
6
9
5
9
4
9
3
9
2
9
1
9
0
8
9
8
8
8
7
8
6
8
5
8
4
8
3
8
2
8
1
8
0
7
9
7
8
7
7
7
6
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
2
6
2
7
2
8
2
9
3
0
3
1
3
2
3
3
3
4
3
5
3
6
3
7
3
8
3
9
4
0
4
1
4
2
4
3
4
4
4
5
4
6
4
7
4
8
4
9
5
0
LEDA_SPEED_100_N
DVDD
LEDA_SPEED_1000_N
LEDA_DUPLEX_N
LEDA_TX_ACTIVITY_N
LEDA_RX_ACTIVITY_N
LINK_A
DVDD
VDDO
DVDD
DVDD
XTAL2
XTAL1
VDDO
RESERVED_NC
RESERVED_NC
AVDDR
M
D
I
O
_
A
D
D
[
1
]
J
T
A
G
_
T
D
O
DVDD
J
T
A
G
_
T
C
K
JTAG_TDI
JTAG_TMS
RESERVED_NC
RESERVED_NC
DVDD
RESERVED_NC
RESERVED_NC
RESERVED_NC
RESERVED_NC
DVDD
VDDO
RESERVED_NC
DVDD
RESERVED_NC
RESERVED_NC
RESERVED_NC
MDIO_ADD[2]
MDIO_ADD[3]
CTRL_12
AVDDR
CTRL_18
M
D
I
O
_
A
D
D
[
0
]
M
D
C
M
D
I
O
V
D
D
O
P
H
Y
_
C
L
K
_
O
U
T
T
E
S
T
_
J
T
A
G
R
X
A
_
M
I
N
U
S
R
X
A
_
P
L
U
S
A
V
D
D
F
T
X
A
_
M
I
N
U
S
T
X
A
_
P
L
U
S
V
S
S
A
V
D
D
F
P
H
Y
_
P
W
R
_
G
O
O
D
R
E
E
R
V
E
D
_
P
D
R
E
S
E
R
V
E
D
_
N
C
P
H
Y
_
R
E
S
E
T
_
N
P
H
Y
_
S
L
E
E
P
VDDO
R
E
S
E
R
V
E
D
_
N
C
M
D
I
A
_
P
L
U
S
[
0
]
M
D
I
A
_
M
I
N
U
S
[
0
]
A
V
D
D
A
V
D
D
M
D
I
A
_
P
L
U
S
[
1
]
M
D
I
A
_
M
I
N
U
S
[
1
]
M
D
I
A
_
P
L
U
S
[
2
]
M
D
I
A
_
M
I
N
U
S
[
2
]
A
V
D
D
M
D
I
A
_
P
L
U
S
[
3
]
M
D
I
A
_
M
I
N
U
S
[
3
]
A
V
D
D
A
V
D
D
A
V
D
D
R
E
S
E
R
V
E
D
_
N
C
P
H
Y
_
R
E
F
LEDA_LINK_UP_N
LEDA_ACTIVITY_N
R
E
S
E
R
V
E
D
_
N
C
R
E
S
E
R
V
E
D
_
N
C
R
E
S
E
R
V
E
D
_
N
C
R
E
S
E
R
V
E
D
_
N
C
RESERVED_NC
RESERVED_NC
RESERVED_NC
RESERVED_NC
RESERVED_NC
RESERVED_NC
RESERVED_NC
RESERVED_NC
R
E
S
E
R
V
E
D
_
N
C
R
E
S
E
R
V
E
D
_
N
C
R
E
S
E
R
V
E
D
_
N
C
R
E
S
E
R
V
E
D
_
N
C
R
E
S
E
R
V
E
D
_
N
C
R
E
S
E
R
V
E
D
_
N
C
R
E
S
E
R
V
E
D
_
N
C
R
E
S
E
R
V
E
D
_
N
C
46
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