Instructions
Instructions
Instructions
TLA7PG2
Pattern Generator Module
071-1306-00
Warning
The servicing instructions are for use by qualified
personnel only. To avoid personal injury, do not
perform any servicing unless you are qualified to
do so. Refer to all safety summaries prior to
performing service.
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List of Figures
Symbols and Terms Terms in this Manual. These terms may appear in this manual:
CAUTION
Refer to Manual
This manual provides high-level information for use of the Tektronix TLAPG2
Pattern Generator Module. Use this manual together with the Pattern Generator
online help to use your Tektronix pattern generator.
Refer to the TLA700 Series Logic Analyzer Instruction Manual to install and
configure the Tektronix pattern generator module.
Related Documentation
In addition to this instruction manual, the documentation listed in Table i is
available for your Tektronix logic analyzer product. For documentation not
specified in the table, contact your local Tektronix representative.
tektronix.com
Contacting Tektronix
Phone 1-800-833-9200*
* This phone number is toll free in North America. After office hours, please leave a
voice mail message.
Outside North America, contact a Tektronix sales office or distributor; see the
Tektronix web site for a list of offices.
The pattern generator module adds pattern generator capability to the logic
analyzer. You can generate specific data patterns to a target system and then use
the logic analyzer to evaluate the resultant data from the target system.
The pattern generator module functionality can be divided into blocks as shown
in Figure 1. Refer to the figure as you read about the functional blocks.
System clock
External
Clock
Probes
The probe interface serves two purposes: to detect event and inhibit information
and to output data to a target system. In addition to sending pattern generator
data to the target system, the probe also sends clock and strobe information.
You can connect up to four probes to a single module. Each probe supports either
8 or 16 channels.
For information about connecting the Pattern Generator probes to both the
TLA7PG2 module and the target system, refer to the TLA700 Series Logic
Analyzer Installation Manual.
Use the Sequence Definition page of the Program window to set up and define a
sequence events that make up the pattern generator program. Each sequence line
determines how the pattern generator will use blocks of data that you define in
the Pattern Generator Listing or Waveform window. You can set up the program
to wait for specific events or signals and then jump to a different sequence when
an event is either true or false.
You can also set up the pattern generator to single step through programs and
output a single set of vectors with each clock cycle. This is useful for trouble-
shooting or debugging setups.
For information about installing the Pattern Generator program, refer to the
TLA700 Series Logic Analyzer Installation Manual.
The pattern generator modules, like the LA modules, have a Setup window
where you can specify the individual module setups, channel setups, probe
setups, and signal setups. You should define these parameters before setting up
the pattern generator program in the Program window.
After you have defined the module setups, you can use the Program window to
define the pattern generator program. Use the Program windows in the following
sequence:
1. Use the Block Definition window together with the Listing or Waveform
window to define the data blocks and the vectors in each block.
2. Use the Sequence Definition window to define a high-level sequence flow of
the pattern generator program.
3. Use the Subsequence Definition window to define subsequences or macros.
You can call these subsequences in the Sequence Definition window.
4. Use the Event Definition window to define how events are used with the
pattern generator program.
Use the Listing and Waveform windows to enter the data vectors. Click the
Listing window icon to open the Listing window for the current block and enter
the vector data. You can edit the vectors in either the Listing or Waveform
windows.
Each sequence has its own line. Use labels for each line to help with the program
flow. Unless you set up a data block to be repeated an infinite number of times,
the program flow will pass to the next sequence (or jump to a defined label).
When the last sequence has been executed, the program flow stops.
After defining a sequence, you can display a graphical image of the sequence
flow by clicking and dragging the vertical bar on the right side of the Sequence
Definition window (see Figure 9).
The appearance of the sequence flow depends on the sequence definition. Each
sequence line has its graphic (see Figure 10).
Figure 9: Drag the vertical bar to the left to display the sequence flow graphic
The events in each row are logically ANDed together while the rows are
logically ORed together.
Tables 1 through 6 list the specifications for the pattern generator module. For
information on the individual pattern generator probes, refer to TLA7PG2
Pattern Generator Probe Instruction Manual.
Characteristic Description
Operational mode
Normal Pattern data output is synchronized by the internal/external clock input
Step Pattern data output is synchronized by the software command
Output pattern
n Maximum Data Output Rate 134 Mb/s in Full Channel Mode
Output level: 5 V 268 Mb/s in Half Channel Mode
Load: 1 MΩ + 1 pF
Series termination resistor: 75 Ω
Maximum Clock Output Frequency 134 MHz in Full Channel Mode
Output level: 5 V 134 MHz in Half Channel Mode
Load: 1 MΩ + 1 pF
Series termination resistor: 75 Ω
Maximum Operating Frequency The maximum operating frequency of the module is a function of the output level,
output pattern and the load condition, including the series termination resistor in the
probe. Operating conditions exceeding this frequency may result in damage to the
probe.
Pattern length 40 to 262,140 (218 - 4) in Full Channel Mode (standard)
80 to 524,280 (219 - 8) in Half Channel Mode (standard)
40 to 1,048,572 (220 - 4) in Full Channel Mode (option 1M or PowerFlex upgrade)
80 to 2,097,144 (221 - 8) in Half Channel Mode (option1M or PowerFlex upgrade)
Number of channels 64 channels in Full Channel Mode
32 channels in Half Channel Mode
The pattern memory for the following data channel will be shared with strobe
control/internal inhibit control
Probe D data output channel Control
D0:0 STRB0
D0:1 STRB1
D0:2 STRB2
D0:3 STRB3
D0:4 Inhibit probe A
Characteristic Description
D0:5 Inhibit probe B
D0:6 Inhibit probe C
D0:7 Inhibit probe D
Sequences Maximum 4,000
Number of blocks Maximum 4,000
Number of subsequences Maximum 50
Subsequences Maximum 256 steps
Repeat count 1 to 65,536 or infinite
Characteristic Description
Internal clock
Clock Period 2.0000000 s to 7.462865 ns in Full Channel Mode
1.0000000 s to 3.7313432 ns in Half Channel Mode
Period Resolution 8 digits
Frequency Accuracy ± 100 PPM
External clock input
Clock Rate DC to 134 MHz in Full Channel Mode
DC to 267 MHz in Half Channel Mode
Polarity Normal or Invert
Threshold
Range - 2.56 V to +2.54 V
Resolution 20 mV
Input Impedance 1 kΩ terminated to GND
Sensitivity 500 mVp-p
Characteristic Description
Event Action Advance, Jump and Inhibit
Number of Event Inputs 8 External Event Inputs (2 per each probe)
Number of Event Definitions 8 (A maximum of 256 event input patterns can be OR’d to define an event)
Characteristic Description
Event Mode
for Advance Edge or Level
for Jump Edge or Level
Event Filter None or 50 ns
Characteristic Description
Signal Input Input from backplane
Selectable from Signal 1, 2, 3, and 4
Used to define the Event
Signal Output Output to backplane
Selectable from Signal 1, 2, 3, and 4
Specified as High or Low in each Sequence line
Characteristic Description
Number of modules that can be merged Five
together
External Event Input for merged module For Jump and Advance, only the External Event Input of the leftmost module is used.
For Inhibit, each module uses its own External Event Input as a source
Characteristic Description
Slot width Requires two mainframe slots
Weight 2.5 kg (5 lbs. 4 oz.)
(Typical)
Overall dimensions (excluding connectors)
Height 10.32 in (262 mm)
Width 2.39 in (61 mm)
Depth 14.7 in (373 mm)
Mainframe interlock 1.4 ECI keying is implemented
The logic analyzer and DSO modules handle signals 1, 2, 3, and 4 with a logical
expression (True/False). However, the pattern generator module handles these
signals with a physical expression (High/Low). Select whether to use the signals
as AND or OR from the TLA application’s Signals property page of the System
Configuration window. Use Tables 7 and 8 to convert physical expressions to
logical expressions or vice versa.
Only one module in the system can drive Signal 1. Only one module in the
system can drive signal 2. When used with an expansion mainframe, all modules
that drive Signal 3 should be in the same mainframe, and all modules that drive
Signal 4 should be in the same mainframe.