Understanding Glitch in High Speed DAC

1 1-888-INTERSIL or 321-724-7143 | Copyright Intersil Corporation 1999
Understanding Glitch in a High Speed

D/A Converter
Introduction
Todays high speed D/A converters are used in communica-
tions applications such as:
Frequency Hopping Radios
Cellular Base Stations
Direct Digital Synthesis
These converters need to provide good Spurious Free operation
to ensure signal integrity and low inter-channel interference.
The glitch of a given DAC can limit the overall spectral per-
formance of the converter and make it unusable. There are
many denitions of this phenomena known as glitch and this
article will try to explain them.
Glitch Area
When a given converter is updated with a new data value the
output of the DAC tries to generate a new output voltage. As
shown in Figure 1 the output slews to a new nal voltage.
This step response contains glitch, and settling effects, that
must die down in order to reach the new steady state output.
FIGURE 1. DAC OUTPUT RESPONSE
Glitch Area is the measure of the area under the rst tran-
sient of the output of the D/A converter. The glitch is
assumed to be triangular in shape and is calculated as
shown in Figure 2.
FIGURE 2. GLITCH AREA
The glitch is the rst peak transient. Some manufacturers
use the glitch doublet theory where the specication given
is a net glitch area
The glitch doublet sums the area of the initial glitch transient
and the area of the settling effects. These areas are then
added together to yield some very small unrealizable num-
ber by most board level designers.
The singlet or peak glitch area is a more realistic specica-
tion for board and system level designers as they can more
adequately evaluate the severity of the glitch.
Glitch Cause
One cause of glitch is the time skew between bits of the
incoming digital data. In a DAC that has no internal register,
the time delta between logic inputs causes internal current
sources to switch asynchronously resulting in a momentary
surge in current. The HI5721 employs an internal register to
synchronize the incoming data.
Typically the switching time of digital inputs are asymmetri-
cal, meaning that the turn off time is faster than the turn on
time. Unequal delay paths through the device can cause one
current source to change before another.
To reduce this, an internal register is used to latch all the dig-
ital input data on one clock edge so as to synchronize them
in time. Careful layout and sizing of the internal current
sources also helps to maintain concurrent switching times.
Reducing Glitch
In traditional DACs the worst case glitch usually happens at
the major transition i.e. 01 1111 1111 to 10 0000 0000. But
in the HI5721, the worst case glitch is moved to the 00 0001
1111 to 11 1110 0000 transition. This is achieved by the split
R/2R-segmented current source architecture, which
decreases the amount of current switching at any one time
and makes the glitch practically constant over the entire out-
put range.
SLEW RATE
GLITCH
SETTLING EFFECTS
FINAL VALUE
V
T (ps)
HEIGHT (H)
WIDTH (W)
GLITCH AREA = 1/2 (H X W)
Technical Brief January 1995 TB325.1
Authors: Juan Garcia and Stephen G. LaJeunesse
2
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certication.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with-
out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
Deglitching Techniques
Deglitching the output of a high speed converter is no trivial
task. Figure 3 shows an ideal deglitching circuit. A deglitcher
is a sample and hold that holds the previous conversion
while the converter is settling to the new output. A deglitch-
ing sample and hold potentially could have a hold to track
glitch, that can be larger than the DACs glitch. The ampli-
ers in this circuit must be unity gain stable to 500MHz and
have a settling time of 2ns for a 1V
P-P
swing to an error band
of 0.1%.
FIGURE 3. A CLASSIC D/A DEGLITCHING CIRCUIT
The on resistance of the switch must be less than 2 and
have a leakage of less than 1pA to minimize droop. This is
practically impossible with the switches available on the mar-
ket today. The best way to reduce glitch is to optimize the
high speed DAC design as done in the Intersil HI5721.
Filtering Glitch
Since the glitch is a transient event this leads designers to
believe that a simple low pass lter can be used to eliminate
or reduce the size of the glitch. In effect low pass ltering a
glitch tends to smear the event and does little to remove
the energy of the transient. Glitch contains many spectra
from near DC up to and beyond the Nyquist sampling rate of
the converter. By low pass ltering, the high frequency com-
ponents of the glitch are removed but the main or majority of
low frequency components are not.
This leaves a designer with a usable spectral window how-
ever, this technique usually results in a higher noise oor at
low frequencies. Noise also increases closest to the cutoff
frequency of the lter.
Picking a Low Glitch D/A
The best methods for choosing a low glitch converter are to
choose those that specify the rst transient area and those
converters that incorporate architectures to minimize glitch.
Trying to remove the glitch from a glitchey DAC is not trivial
and can simply move the problem to other places as well as
complicate the design.
The HI5721s Peak Glitch
Although the HI5721 species a glitch doublet area of
1.5pV-sec (to meet specs quoted by other D/A manufactur-
ers) the peak glitch is ~3.0pV-sec. Figures 4 and 5 show the
typical glitch height and width.
FIGURE 4. GLITCH HEIGHT
Code 64
D
- 60
D
, Scope 50 GND
FIGURE 5. GLITCH WIDTH
Code 64
D
- 60
D
, Scope 50 GND
FIGURE 6. GLITCH TEST SETUP
Summary
Testing standards are evolving and as technology improves
the real specications become evident. For state of the art
D/A converters, the HI5721 provides designers with the
lowest glitch performance, tested under the most stringent
conditions.
HI5721
I
OUT
50 68pF
V
OUT
(1V
P-P
) +
-
+
-
(20)I
OUT
100MHz
LOW PASS
FILTER
50 50
SCOPE
HI5721
Technical Brief 325

Understanding Glitch in High Speed DAC

Uploaded by

Copyright:

Available Formats

Understanding Glitch in High Speed DAC

Uploaded by

Document Information

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

Understanding Glitch in High Speed DAC

Uploaded by

Copyright:

Available Formats

1 1-888-INTERSIL or 321-724-7143 | Copyright Intersil Corporation 1999

Understanding Glitch in a High Speed

You might also like