EI2403-VLSI DESIGN

DEPT. OF EIE

VALLIAMMAI ENGINEERING COLLEGE

S.R.M. Nagar Kattankulathur-603203

Department of Electronics and Instrumentation Engineering

Question Bank
SUBJECT CODE

: EI2403

BRANCH

: EIE

SUBJECT NAME : VLSI DESIGN

YEAR/SEM

IV / VII

UNIT-I

BASIC MOS TRANSISTOR

PART A
1. Compare Enhancement mode and Depletion mode MOSFET.
2. What factors cause drain punch through condition in MOS transistors?
3. Draw the structure of NMOS transistor.
4. List out the advantages of BiCMOS technology.
5. Compare NMOS and CMOS Technologies.
6. Distinguish NMOS and PMOS device characteristics.
7. Write the equation for threshold voltage.
8. What is the significance of MOS transistor transconductance?
9. What is isolation?
10. What is the special feature of Twin-Tub process?
11. What are the various processes used in SOI? Give its advantages.
12. Compare CMOS and Bipolar Transistor.
13. Give the basic process for IC fabrication.
14. What are the advantages of CMOS process?
15. Why NMOS technology is preferred more than PMOS technology?
16. What are the different operating regions an MOS transistor?
17. What is body effect?
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18. An NMOS transistor has a threshold voltage of 0.8 V. What are the conditions on Vds for
the transistor to operate in the linear and saturation regions if Vgs=2V?
19. Sketch the device model of a MOS device.
20. Does the body effect of a process limit the number of transistors that can be placed in
series in a CMOS gate? Justify your answer.
21. What are the second order effects of the MOSFET device?
22. List the factors which affect the threshold voltage of a MOS transistor.

PART-B
1. With neat diagram explain MOS Transistor theory and its processing technology. (16)
2. Explain the operation of nMOS Enhancement and Depletion mode transistor.

(16)

3. Draw the structure of pMOS and nMOS transistor and explain its working.

(16)

4. With a neat diagram explain the fabrication of nMOS transistor.

(8)

5. Explain the fabrication of pMOS transistor and its substrate fabrication process.

(8)

6. Explain P-well and N-well fabrication process of CMOS inverter.

(16)

7. Explain Twin Tub process of CMOS fabrication in detail.

(16)

8. Explain SOI process of CMOS fabrication in detail.

(16)

9. Describe the important processing steps and masks for BiCMOS fabrication
technology
10. Derive the Threshold voltage for nMOS Enhancement transistor.

(8)

11. Derive an expression nMOS transistor current equation.

(16)

12. Explain about the body effect of MOS transistors.

(6)

13. Explain the second order effects with their equations.

(16)

14. Compare CMOS and Bipolar technology.

(6)

15. Explain substrate bias effect.

(8)

16. Draw and discuss the MOS transistor Model.

(8)

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UNIT-II

NMOS AND CMOS INVERTER AND GATES

PART- A
1. Give the CMOS inverter DC transfer characteristics and operating regions
2. Draw the circuit of a nMOS inverter
3. What are the different MOS layers?
4. How latch up problems can be rectified in CMOS fabrication process?
5. Give the expressions for noise margin high NMH and noise margin low NML for a CMOS
inverter circuit.
6. For an ideal inverter with VDD=5v. What are VOH and VOL?
7. Give the expression for power dissipation in CMOC inverter.
8. Implement NAND gate using CMOS.
9. Define gain factor of MOS transistor.
10. What are the four possible arrangements of pull-up?
11. What is the condition for pull up to pull down ratio of an inverter? (a) directly from the
output of another inverter (b) through one or more pass transistors.
12. Mention with necessary conditions why NMOS is used as pull down device and PMOS is
used as pull up device.
13. What is a stick diagram?
14. Draw the stick diagram for NMOS inverter
15. What is Lambda (O) - based design rules?
16. State the significance of lambda based rule.
17. Write any two design layout rules.
18. What is a Pass transistor?
19. What is a super buffer?
20. Compare inverting and Non inverting super buffers.
21. What are transmission gates?
22. What is ratioed logic?
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23. What is meant by steering logic?

24. What is meant by sneak path?
25. What is charge sharing?
26. Is the transmission of logic 1 degraded as it passes through a nMOS pass transistor?
Why?
27. What are the advantages and disadvantages of CMOS pass transistor?
28. Implement NAND and NOR in Pass transistor logic.
29. Implement Y= ABC and its complement in Steering logic.
30. The W/L ratio of pull up of an inverter is and that of the pull down is . Determine the
pull up to pull down ratio for this inverter.

PART-B
1. Draw the CMOS inverter transfer characteristics and explain its operation, clearly
indicating the various regions.

(16)

2. Derive an expression for pull up to pull down ratio of an NMOS inverter driven by
another NMOS inverter.

(16)

3. Derive an expression for pull up to pull down ratio of an NMOS inverter driven by one
or more pass transistors.

(16)

4. Draw and explain the NMOS and CMOS lambda based design rules for transistors and
wires.

(16)

5. Draw the stick diagram for (i) 3-input NOR gate (ii) CMOS inverter.

(16)

6. Explain the operation of inverting and non inverting type NMOS super buffer.

(16)

7. Give a short note on steering logic.

(8)

8. What is a pass transistor Logic design? Draw the logic circuit of XOR gate using
transmission gates.

(16)

9. Draw and implement NAND and NOR logic using BiCMOS transistor.

(16)

10. With neat schematic explain pass transistor driving capacitive load and Inverter.

(16)

11. Design a digital BiCMOS circuit that implements the function f = c.k.r + r.k.p

(16)

12. Draw the stick diagram for a Gray to BCD converter. Assume aii other relevant details.
(16)
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UNIT III

SUB-SYSTEM DESIGN AND LAYOUT

PART-A
1. Distinguish between absolute skew & clock skew.
2. Single phase dynamic logic structures cannot be cascaded. Why?
3. Draw the logic diagram of simple 2 phase clock generator circuit.
4. Why is barrel shifter very useful in the designing of arithmetic circuits?
5. Define regularity. What is the regularity factor of a 4*4 barrel shifter?
6. Draw the block of an adder element.
7. Implement the following Boolean expression using full static CMOS logic
Y = (A.B) + (D.B.C) + (D.A) + (A.C.B)
8. Write the principle of any one fast multiplier.
9. Why NOR structures are avoided in high speed circuits?
10. Realize 2 input XOR gate using CMOS devices.
11. Give the NAND-NAND implementation of Y=ABC +DEF.
12. Define clocked CMOS logic.
13. Define domino logic.
14. What is a tally circuit?
15. Implement XOR gate using CVSL logic.
16. What is clock Skew?
17. Realize OR/NOR logic functions using CVSL logic.
18. What is the role of stick diagram and Layout in MOS circuit design process
19. How does a demultiplexer differ from a decoder
20. What are the properties of static CMOS gate
21. What is ratioed logic
22. Draw a circuit diagram for a CMOS gate with 2 inputs A and B and an output Z,
where Z=1 if A=0 and B=1 and Z=0 otherwise
23. Implement the function z = ab + cd using CMOS logic
24. What are data path circuits?
25. What is anti-fuse technique? Mention its significances.
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PART B
1. Describe precharge and evaluation operations associated with dynamic CMOS logic with
neat diagrams.

(8)

2. Explain the operation of a 3 input tally circuit designed with pass transistors.

(8)

3. Compare the NMOS and CMOS implementation of 4*1 MUX with necessary diagrams.(8)
4. Draw the circuit diagram and stick diagram of a 4*4 barrel shifter and explain its
operation.

(16)

5. Discuss in detail about the circuit arrangement and stick diagram of a CMOS (Dynamic
logic) 4*8*4 PLA.

(16)

6. Explain the different XOR structures.

(8)

7. Write a short note on dynamic CMOS design.

(8)

8. Draw the schematic and explain the operation of D-CMOS and C-CMOS two- input
NAND gate and NOR gate.

(16)

9. Explain the structure of a booth multiplier and list its advantages.

(8)

10. Give the general arrangement of a 4-bit arithmetic processor and design a 4-bit adder
unit for ALU sub system.

(16)

11. Design a 3 bit barrel shifter.

(8)

12. What is 4*4 carry save multiplier .Calculate the critical path delay.

(8)

13. Explain the following circuits.1.Data path circuits 2.Any one adder circuit.

(16)

14. Implement 1. a parallel adder 2. a transmission gate adder circuit.

(8)

15. Design a 4 bit barrel shifter using multiplexer.

(8)

16. Explain the design of a bit serial adder.

(8)

17. Design a positive edge triggered T register with CMOS gates. Explain the circuit
operation with timing diagram.
18. Design a pass-transistor network that implements the sum function for an adder.

(8)

19. Draw the stick diagram of 3 input tally circuit designed with pass transistor.

(8)

20. Give the NAND-NAND implementation of Y = ABC + DEF.

(8)

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UNIT IV
DESIGN OF COMBINATIONAL ELEMENTS AND REGULAR ARRAY LOGIC

PART A
1. What is a PLA?
2. What is an FPGA?
3. Distinguish between PLA and PAL.
4. List out the advantages of FPGA.
5. Give the difference between FPGA and CPLD.
6. Compare FPGA and PLA.
7. List the methods of programming PAL.
8. Why PLAs are not used in CMOS logic circuits?
9. Define CLB.
10. Define FSM.
11. Differentiate between a Mealy and Moore machine.
12. What is meant by an NMOS PLA?
13. List out the building blocks of Xilinx PLA.
14. Give the XILINX Configurable Logic Block
15. Give the XILINX FPGA architecture.
16. What are Programmable Interconnects?
17. What are macros?
18. What are the different levels of design abstraction at physical design?
19. Give the steps in ASIC design flow.
20. What are the advantages of dynamic logic arrays over PLA?
PART-B
1. Explain the general architecture of FPGA and clearly bring out the different
programmable blocks used.
2. Write the significance of PLA/FSM in VLSI design.

(16)
(6)

3. Design a mealy based finite state machine for serial adder and implement it using suitable
PLA.

(16)

4. What is NMOS pLA? Give the stick diagram for NMOS NOR-NOR PLA realization.(16)
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5. Briefly explain the PLA based FSM design.

(8)

6. With neat sketch explain the CLB, IOB and programmable interconnects of an FPGA
device.

(16)

7. What is a Finite State machine? How is it implemented using PLA?

(8)

8. Draw and explain the general architecture of PAL device.

(8)

9. What are the building blocks of Xilinx CPLD? Explain the functional description of each
block.

(16)

10. Implement a PLA for the function Z0 = Z1 = X1 + ( - X0 - X1 - X2 ) ; Z2 = ( - X1 - X2 ) ;

Z3 = ( - X0 - X1.X2 ) + ( - X0 - X1 - X2 ).

(8)

UNIT V

VHDL PROGRAMMING
PART -A
1. What is VHDL?
2. What are the two delays possible in VHDL?
3. What is done in Synthesis process?
4. List any two features of concurrent Description?
5. What is RTL Description?
6. What are the differences between programming language and HDL?
7. Name the four data types supported by VHDL?
8. What is a test bench?
9. Write a VHDL entity for Half subtractor.
10. Name any four sequential statements.
11. How process statements are concurrent statements?
12. How do a signal and variable differ?
13. Give a simple VHDL architecture for an inverter with inertial delay?
14. Write a VHDL code to realize 2:1MUX.
15. Write the format for process statements?
16. Differentiate simulation and synthesis.
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17. What is overloading of operators?

18. Show the general form of an architecture in VHDL design Entity.
19. Define place and routing.
20. What is meant by simulation and optimization?

PART-B
1. Write the VHDL code to realize full adder using structural modelling and also write the
test bench.

(16)

2. Write the VHDL code to realize 3 to 8 decoder in behavioural level description.

(8)

3. Write the VHDL code to realize D Flip Flop and 4-bit Synchronous counter.

(10)

4. What is a package in VHDL? Explain with a suitable example.

(6)

5. Explain the concurrent and sequential assignments in VHDL.

(8)

6. Describe the differences between VHDL functions and procedures.

(8)

7. Discuss the modelling of a 4-bit ripple counter using VHDL.

(8)

8. Explain the different methods of modelling in VHDL with an example.

(16)

9. Explain (i). Package declaration (ii) Block statement.

(16)

10. Explain in detail about data types used in VHDL with examples.

(16)

11. Write a VHDL code for a universal BCD to seven segment Decoder using if statement.(8)
12. Using structural level VHDL coding, realize a 4-bit adder. Write a test bench to define the
stimulus for the 2-inputs for the 4-bit adder.
13. Explain in detail about Generics and Parameterized components with an example.

(16)
(16)

14. Write a behavioural VHDL code and test bench program for a 4-bit synchronous gray
code counter.

(16)

15. Write a behavioural and structural VHDL code and test bench program for a JK Flip flop.
(16)

PREPARED BY : V. SURESH KUMAR / A.P.( Sr.G).

: AGILYDIAPRIZZI / A.P.(O.G)

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DEPT. OF EIE

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