(An Autonomous Institution, Affiliated to Anna University, Chennai)

ECE DEPARTMENT
V- Semester
EC3552 – VLSI DESIGN

(B.E/B.Tech – ECE)
(Regulations 2021)
UNIT-I MOS TRANSISTOR PRINCIPLES
PART A
1. State channel length modulation. Write down the equation for describing the channel
length modulation effect in NMOS transistors.
2. Define threshold voltage of MOSFET.
3. What is Drain Punch Trrough effect?
4. Why NMOS device conducts strong zero and week one?
5. Sketch a complementary CMOS gate computing W=(XY+YZ)’
6. Why NMOS technology is preferred more than PMOS technology?
7. Why NMOS transistor is selected as pull down transistor?
8. List different types of scaling.
9. Enumerate few non-ideal characteristics of MOS Transistor.
10
What is Body effect?
.
11 What is DIBL?
12 Mention some of the techniques to minimize the power dissipation.
13 Explain the beta ratio effect and its dependance on temeperature.
14 List the Scaling Principles.
15 Compare PMOS and NMOS.
16 List out the source of static and dynamic power dissipation.
17 Sketch a complementary CMOS gate computing W= (AB+BC)’.
18 List the types of power dissipation.
19 Sketch the 2-input CMOS NOR gate.
20 Define Impact Ionization.
UNIT-I
PART – B
1. An nMOS transistor has the following parameters: gate oxide thickness= (13)
10nm, relative permittivity of gate oxide=3.9, electron mobility= 520
cm2/V-sec, threshold voltage= 0.7 V, permittivity of free space= 8.85 x 10-
14 F/cm and (W/L) =8. Calculate the drain current when (VGS = 2V and
VDS =1.2 V) and also compute the gate oxide capacitance per unit area.
Note that W and L refer to the width and length of the channel respectively.
2. Describe equation for source to drain current in three region operation of a (13)
MOS transistor and draw VI characteristics.
3. Explain the significance of threshold voltage and body effect with necessary (13)
equations.
4. Discuss in detail about the scaling principles with its limits and also about the (13)
power consumption.
5. Consider the nMOS transistor in a 65 nm process with a nominal threshold (13)
voltage of0.3 V and a doping level of 8 × 1017 cm–3. The body is tied to
ground with a substratecontact. How much does the threshold change at
room temperature if the source is at0.6 V instead of 0?
6. For the transistor-level schematic. (7)

(6)

a) compute G
b) Implement using CMOS, F= X= [(AB)+E+(CD)]’

7. Illustrate the DC transfer characteristics of a CMOS inverter graphically. (13)

Interpret the graph to explain its behaviour for different input voltage
ranges.
8. (i) Discuss the impact of non-idealities of MOSFETs on device performance (7)
and reliability.
(ii) What are the sources of power dissipation in CMOS? Discuss various (6)
design techniques to reduce power dissipation in CMOS.
9. Consider the nMOS transistor in a 0.6 µm process with gate oxide thickness (13)
of 100Å. The doping level is NA = 2 × 1017 cm–3 and the nominal threshold
voltage is 0.7V. The body is tied to ground with a substrate contact. How
much does the thresholdchange at room temperature if the source is at 4 V
instead of 0?
10 A novel inverter has the transfer characteristics shown in Figure. (7)
. (a) Whatare the values of VIL, VIH, VOL, and VOH that give best noise margins? (6)
(b)What arethese high and low noise margins?

11 What are the implications of secondary effects on MOSFETs when scaling

. down to smaller process nodes in semiconductor manufacturing?
12 Explain the origins of power dissipation in CMOS technology and delve into the
. diverse design strategies employed to minimize power consumption in CMOS
circuits and systems?
13 Create a graphical representation depicting the DC transfer characteristics of a
. CMOS inverter and provide an interpretation of the graph, explaining how the
inverter behaves across different input voltage ranges?
14 (a)Suppose you are asked to design a converter to translate a 4-bit code In (6)
. 3In2In1In0 to a 2-bit code Out1Out0. The schematic diagrams are shown below.
Find out the Boolean equations for Out0 and Out1 based on In0, In1, In2 and In3.

(b) Explain the significance of Sub threshold conduction and Impact (7)
ionization.
PART – C
1. Design a CMOS logic circuit for the given expressions and sketch the stick (15)
diagram
i. X= [(A+B).(C+D)]’and
ii. Z=((A+B+C).D)’

2. Explore the drain current equation of a MOS transistor in the all regions, (15)
considering both NMOS and PMOS transistors, and analyze how the
transistor's dimensions impact its saturation behavior.
3. (15)
An nMOS transistor has the following parameters: gate oxide thickness=
10nm, relative permittivity of gate oxide=3.9, electron mobility= 520
cm2/V-sec, threshold voltage= 0.7 V, permittivity of free space= 8.85 x 10-
 14 F/cm and (W/L) =8. Calculate the drain current when (VGS = 1V and
VDS =1.2 V) and also compute the gate oxide capacitance per unit area.
Note that W and L refer to the width and length of the channel respectively.

4. Design a CMOS logic circuit for the given expression X= [A]’and explain (15)
its DC transfer characteristics.
5. Calculate noise margin at nodes a and b. (15)

UNIT-II ( COMBINATIONAL LOGIC CIRCUITS)

Propagation Delays, stick diagram, Layout diagrams, Examples of combinational logic design,
Elmore’s constant, Static Logic Gates,Dynamic Logic Gates, Pass Transistor Logic, Power
Dissipation, Low Power Design principles
PART A
1. Give Elmore delay expression for propagation delay of an inverter.
2. What is the value of Vout for the figure shown below.

3. Define Elmore constant.

4. How many number of transistors required to implement N- input Pseudo NMOS logic?
5. What is the value of Y in the following circuit, where Vtn is the threshold voltage of the
circuit.

6. Sketch the stick diagram of static CMOS 2-i/p NOR gate.

7. In the following circuit employing pass transistor logic, all NMOS transistors are identical
with a threshold voltage of 1 V. Ignoring the body-effect, the output voltages at P, Q and R
are

8. Implement 2- i/p HI-Skew NOR gate with P/N ratio.

9. What is Stick diagram and uses of Stick diagram?
10 Give the expression for Best stage effort in Linear delay model.
.
11 Differentiate between Symmetric and Asymmetric gates.
12 What is Power Gating and its important features?
13 Realize X=B+C and Y= (A (B+C)) using multiple output domino stages.
14 Draw a 2-input XNOR using NMOS pass transistor logic.
15 What is meant by Ratioed logic? List the drawbacks of ratioed circuits.
16 What makes dynamic CMOS circuits faster than static CMOS circuits?
17 What is Charge sharing in dynamic CMOS logic?
18 What is transmission gate? Give the different symbols for transmission gate.
19 What are the two types of Layout design rules?
20 Write the expression for total power dissipation and need to estimate power dissipation.

PART – B
1. A carry lookahead adder computes G = G3 + P3(G2 + P2(G1 + P1G0)). (13)
Considerdesigning a compound gate to compute G.
a) sketch a transistor-level schematic
b) sketch a stick diagram
2. Estimate the least delay and determine the input capacitance of each stage. (13)

3. Consider the design of a CMOS compound OR-AND-INVERT (OAI21) (13)

gate
computing F = ( A+ B ) . C .
a) sketch a transistor-level schematic
b) sketch a stick diagram
4. Sketch a combinational function Y=(A+B)’ using (13)
(i) Pseudo –nMOS logic
(ii) Domino logic
(iii) Hi-Skewed Logic
5. Explain Dynamic logic circuits with a neat sketch. What is the major (13)
drawback in dynamic circuits and methods to overcome it?
6. (i) Explain Skewed and Ratioed Static logic circuits (7)
(ii) Explain the basic principle of Pass transistor in CMOS design. (6)
7. (i) Explain about DCVSL logic with suitable example. (7)
(ii)What is transmission gate? Explain the use of transmission gate. (6)
8. Realize a 2-input NOR gate using static CMOS logic, Domino logic and (13)
complimentary pass transistor logic. Analyze the hardware complexity in
 terms of transistor count.
9. Implement Y=((A+B)CD)’ using (5)
(i) Pseudo –nMOS logic (6)
(ii) Hi-Skewed &LO-Skewed Logic

10 (i) Explain the domino logic with neat diagram. (5)

. (ii) Explain DCVSL logic and implement the following logic function using the (8)
same.Y = (AB+CD)’
11 (a)Consider the path from A to B involving three two-input NAND gates (7)
. shown in Figure 1.7. The input capacitance of the first gate is C, and the
load capacitance is also C. What is the least delay of this path, and how
should the transistors be sized to achieve least delay? Use un/up = 2. The
NAND2 has the same effective resistance as a reference size inverter.

(6)

(b)Find the least delay achievable along the path from A to B when the
output capacitance is 8C.
12 Consider the following circuit: The input capacitance of each input of the (13)
. NAND4 gate is 10C.Determine the least delay

13 What is the significance of the monotonicity requirement in digital circuit (13)

. design, and how does domino logic address and overcome this particular
challenge?
14 How does an in-depth analysis of the operational principles, power (13)
. consumption, and delay characteristics of NP and Zipper Domino logic
reveal their suitability for specific digital circuit applications?
15 Implement the following gates using transmission gate: (13)
. (a) AND gate and NAND gate
(b) EXOR gate and XNOR gate

PART – C
1. (a) Sketch a 4-input NAND gate with transistor widths chosen to achieve (15)
equal riseand fall resistance as a unit inverter. Show why the logical effort is
6/3.
(b) Sketch HI-skew and LOW-skew 3-input NAND and NOR gates. What are the
logical efforts of each gate on its critical transition.
2. Estimate least delay and determine input capacitance of each stage for the (15)
 logic network shown in the figure, which may represent the critical path of a
more complex logic block. The output of the network is loaded with a
capacitance which is 5 times larger than the input capacitance of the first
gate, which is a minimum sized inverter.

3. Let A, B, C and D be the inputs of a data selector and S0 and S1 be the (15)
select lines. Realize a 4:1 data selector using
(i) nMOS pass transistor and
(ii) Transmission gate approach.

4. (a)Build a 16-input AND logic with Structure of NAND4-NOR4 structure, assuming (6)
primary input cap is Cg, μ = 2, and load cap is 3Cg. Calculate worst case delay using
logical effort.
(b)Calculate the Boolean expression for the following transmission gate
(7)
implementation

5. Draw the pass transistor-based and TG-based structure for the flowing Boolean
𝐹=𝐴𝐵+BC+AC
equation.

UNIT-III ( SEQUENTIAL LOGIC CIRCUITS AND CLOCKING STRATEGIES)

PART A
1. Compare and contrast synchronous design and asynchronous design.
2. Define clock skew.
3. Write the operation of C2MOS register.
4. Draw the schematic of dynamic edge triggered register.
5. What is meant by pipelining?
6. What are the limitations in static lathes and registers?
7. What is clocked CMOS register?
8. What is metastability in Sequential circuits?
9. What are different pipelining techniques used in sequential circuits?
10 Define clock Skew and clock –jitter.
.
11 Draw the schematic of mux based master slave edge triggered static register.
12 What is clocked CMOS register?
13 Define sequential circuits.
14 How does clock skew impact the synchronization of flip-flops and registers?
15 What is setup time and hold time in relation to flip-flops?
16 What is bi-stability principle?
17 What is meant by virtual clock definition and why it is needed?
18 Discuss the advantages of TSPC register.
19 Compare the power consumption of static and dynamic latches.
20 Define about clock jitter.

PART B
1.Discuss in detail various pipelining approaches to optimize sequential (13)
cCircuits.
2. Write short notes on (7)
(i) True single phase clocked registers. (6)
(ii) Clocked CMOS logic register
3. Explain the circuit design of latches and flip flops in detail. (13)
4. Explain the dynamic latches and registers in detail. Discuss the advantages (13)
and limitations of each approach and provide typical applications where
each type of system is beneficial.
5. Explain the operation of (13)
(i) Master – slave based edge triggered register.
(ii) Dynamic Edge Triggered Register

6. Describe the concept of pipelining in sequential circuits with a suitable example. (7)
Explain different types of pipelining methods in sequential circuits. (6)
7. Write short notes on (7)
(i) C2MOS (Clocked CMOS) Latches (6)
(ii) TSPC
8. Design a D-Latch using Transmission gate. Using which realize a two phase non (13)
overlapping master-slave negative edge triggered D-Flip- flop.
9. Write short notes on (7)
(i) TSPC (6)
(ii) C2MOS
10 Explain the underlying principles of dynamic latch and register operation, (13)
. highlighting the benefits they offer in terms of area, power consumption, and
speed. Discuss the challenges associated with dynamic latches and registers, such
as charge leakage and clock signal requirements.
11 How is the circuit design of latches structured, and what are the inherent (13)
. constraints and issues associated with latches? Additionally, could you outline
specific techniques and approaches for addressing these limitations within a
single-latch design context in digital circuitry?
12 Implement the dynamic register using C2 MOS logic and explain how 0-0 (13)
. and 1-1 overlap of clock signals are eliminated.
PART C
1. a) Identify the type of register for the circuit shown in the figure and express set up (15)
time, hold time and propagation delay of register.

b) Implement the register shown in the figure using C2 MOS logic and
explain how 0-0 and 1-1 overlap of clock signals are eliminated.
2. Consider the circuit below (15)

(i)State whether the circuit is a latch or edge triggered register. Justify your answer.

(ii)In the circuit consider C1 and C2 as the intrinsic capacitances of inverters and
transmission gates. Assuming ideal clock, compute the setup time, hold time and
propagation delay in terms of the inverter I1, I2 delay and transmission gate T1, T2
delay.

3. How does the choice between True Single Phase Clocked (TSPC) registers and (15)
Clocked CMOS logic registers impact the power consumption, speed, and area
utilization in digital integrated circuits, and under what circumstances would each
type be preferred in practical design scenarios?
4. Describe the concept of pipelining in sequential circuits with a suitable example. How (15)
is it categorized based on data forwarded fashion?
5. Explain the dynamic latches and registers in detail. Discuss the advantages and (15)
limitations of each approach and provide typical applications where each type of
system is beneficial.

UNIT-IV (INTERCONNECT, MEMORY ARCHITECTURE & ARITHMETIC CIRCUITS )

 PART A
1. Sketch and name the elements in the Configuration Logic Block

2. Draw a 1-transistor dynamic RAM cell.

3. What different lumped delay models are for interconnects?
4. What will be the value of bitline before reading from 1T DRAM cell and SRAM cell?
5. Calculate the number of address lines required for 8KB memory chip.
6. Differentiate between ROM and PLA in terms of functionality.
7. How many SRAMs with 128Kx8 organization are needed to design a 1MB size memory block?
8. What is the primary function of a memory refresh controller in DRAM systems?
9. How many NMOS transistors does SRAM 6T cell have?
10 Explain how capacitance affects signal propagation in high-speed interconnects.
.
11 The figure below shows a 4-word × 4-bit ROM. what is the data stored at address 3 and why?

12 What type of configuration memory is used in FPGA Xilinx Virtex-7?

13 What is partial product generation?
14 How does the reprogrammability of FPGAs benefit prototyping and development?
15 What is latency?
16 What is the purpose of a memory buffer (also known as a data buffer) in memory systems?
17 Draw the structure of 4*4 barrel shifter.
18 Why DRAM requires periodic refreshing?
19 A copper wire has a resistance of 0.2 ohms per meter. Calculate the total resistance of a 2-meter-
long copper wire.
20 In a DRAM system with 64 rows, if the refresh rate is set to 8 ms, calculate how often each row
must be refreshed to ensure data integrity
PART-B
1. The SRAM cell needs to be optimized for both read and write operations while (13)
 meeting stringent speed and power requirements. Explain the construction of the 6T-
based SRAM cell and detail its read and write operations within this scenario.
2. Implement the following function f1=Σm(3,5,7) and f2= Σm(4,5,7) using (7)
(i) PROM (6)
(ii) PLA

3. (i) Determine the logic equation implemented by the following figure (5)

(8)
(ii) Explain Barrel shifter with a neat sketch.
4. Explain the Memory architecture and its control circuits. (13)
5. Design a 4X4 array multiplier circuit and explain its operation. (13)
6. Illustrate the building blocks of Memory architectures and memory peripheral (13)
circuitry adapted to operate for non-volatile memory.
7. (i) Draw and explain the implementation 8 bit fast adder (7)
(ii) Explain about the barrel shifter. (6)
8. Derive the necessary expression of a 4 bit carry look ahead adder and realize the carry (13)
out expression using Dynamic CMOS logic.
9. Explain the operation and structure of a 1T DRAM cell in dynamic random-access (13)
memory (DRAM). Discuss the key advantages and disadvantages of using 1T DRAM
compared to traditional 2T or 3T DRAM cells.
10 Create a schematic representation of the programmable interconnects within an (13)
. FPGA. Describe how these interconnects enable the routing of signals between
different CLBs and IOBs in the device.
11 Design a 8 bit carry select adder and determine its worst case delay. (13)
.
12 Consider a 10mm long, 4λ wide metal 2 wire in a 180nm process. The sheet (13)
. resistance is 0.09ohm/square and capacitance is 0.3fF/micro meter.
Construct a 3 segment π model and T model for the wire.
13 Explain the phenomenon of crosstalk effects in interconnects, considering (13)
. factors such as wire capacitance and wire resistance.
14 Considering the SRAM cell circuit in figure below. Assume VTN = |VTP | = (13)
. 0.5V, Vdd=2V. k’n = 60μA/V2, k’p = 30μA/V2. Ignore body effect and channel
length modulation. The sizing of the SRAM cell is as follows: (W/L)M3, M4 = 2,
(W/L)M1, M2 = 4. (W/L)M5, M6 = 3/2.
(1) Calculate the maximum value of V1 during Read 0.
(2) Calculate the minimum value of V1 during Write 0 when 1 is stored in the cell
previously.
 PART – C

1. With neat sketch explain the CLB, IOB and programmable interconnects of (15)
an FPGA device.In FPGA architecture, what is the relationship between the
number of inputs and the size of a LUT? How does this affect the types of
logic functions that can be implemented?
2. (a)Consider the following SRAM cell in the standby condition. Which (15)
biasing will result in the least leakage without losing the state of the cell?

(b) Program the LUT to implement the following logic function:

(i)F(a,b,c) = ab’c
(ii)g(x,y,z)=xz

3. Realize these functions below with the following devices: (15)

i. i. PROM
ii. ii. PLA
iii. iii. 4 – input FPGA LUTs
iv. f1(a,b,c,d)=Σm(0,1,2,3,6,9,11)
v. f2(a,b,c,d)=Σm(0,1,6,8,9)
vi. f3(a,b,c,d)=Σm(2,3,8,9,11)

4. (a)Consider a 5mm long, 4λ wide metal 2 wire in a 180nm process. The (8)
sheet resistance is 0.08ohm/square and capacitance is 0.2fF/micro meter.
Construct a 3 segment π model and T model for the wire.
(b) Examine the phenomenon of crosstalk in intricate interconnects,
 considering factors such as wire capacitance and wire resistance. (7)
5. What are the key advantages and disadvantages of utilizing 1T DRAM cells (13)
in dynamic random-access memory (DRAM) compared to the more
traditional 2T or 3T DRAM cells? Provide an analytical assessment of the
trade-offs in terms of performance, power efficiency, and overall memory
architecture, highlighting situations where each type of DRAM cell might
be preferred

UNIT-V (IMPLEMENTATION STRATEGIES AND TESTING )

PART A
1. What is the full custom ASIC design?
2. How do you prevent latch up problem?
3. What are the key components of a Verilog HDL test bench?
4. What is fault grading?
5. List the basic process for IC fabrication
6. What is the standard cell-based ASIC design?
7. What are the approaches in design for testability?
8. State the building blocks of FPGA
9. What is an antifuse?
10 What is the aim of adhoc test techniques?
.
11 Distinguish functionality test and manufacturing test.
12 Explain how testbench instantiation facilitates the interaction between the test bench and the
design under test (DUT) during the simulation process.
13 Compare full custom and semi-custom design
14 What are the scan-based test techniques?
15 What is the role of cell libraries in ASIC design?
16 What are the types of gate arrays in ASIC?
17 List any two faults that occur during manufacturing.
18 What is the difference between channeled gate array and channel less gate array?
19 Define controllability and observability.
20 What is boundary scan?

PART -B
1. Explain the various types of ASIC with neat diagram. (13)
2. Examine the boundary scan architectures in digital systems and explain their role (13)
in facilitating testing at both the circuit board level and system level. Describe the
principles behind boundary scan testing and how it helps in diagnosing faults and
verifying the connectivity of integrated circuits. Discuss the specific test
methodologies employed at the circuit board level and how boundary scan is
utilized to enhance the testability of complex digital designs.
3. Explain the principles and advantages of Level-Sensitive Scan Design (LSSD) in (13)
VLSI testing and design for testability (DFT). Discuss the basic structure and
operation of LSSD flip-flops and how they contribute to the testing process.
4. (i) Differentiate between Hard Macro and Soft Macro. (7)
(ii) Explain Standard cell design and cell libraries. (6)
5. Write brief notes on (13)
i) Full custom ASIC.
ii) Semi custom ASIC.
6. What is Automatic Test Pattern Generation (ATPG) in VLSI testing? Explain the (13)
fundamental principles and methodologies used in ATPG to generate test patterns
for detecting and diagnosing faults in integrated circuits. Discuss the significance
of ATPG in ensuring high fault coverage and reliable testing during the
manufacturing process of VLSI chips.
7. Describe the process flow of wafer to chip fabrication in VLSI manufacturing. (13)
Explain the sequential steps involved, starting from the initial wafer preparation to the
final chip packaging.
8. Create a test bench in Verilog HDL for the following circuits and validate its (5)
functionality. (8)
(a) 4X1 Mux(b) Shift register
9. Describe the three main approaches frequently employed for Design for Testability (13)
(DFT) in VLSI (Very Large Scale Integration) circuits. Discuss each approach's key
principles, advantages, and limitations in enhancing testability and ease of testing
during the manufacturing and verification stages of integrated circuits.
10 Discuss how fault models are used in fault simulation, test pattern generation, and (13)
. fault diagnosis processes to assess the circuit's testability and evaluate its robustness
against potential faults.
11 What are the fundamental principles and benefits associated with Level-Sensitive (13)
. Scan Design (LSSD) concerning VLSI testing and Design for Testability (DFT)?
Additionally, could you elaborate on the fundamental structure and functioning of
LSSD flip-flops and their role in facilitating the testing procedure?
12 Discuss in detail about different types of scan design method and explain with neat (13)
. diagram.
13 Create a test bench in Verilog HDL for a 4X1 mux and 1X4 Demux circuit. Explain (13)
. the steps involved in writing the test bench code, including the generation of test
vectors and the implementation of test cases. Describe the expected behavior of the
RCA circuit during simulation and how the test bench can validate the correctness of
the adder's output.
14 How has VLSI manufacturing evolved with advancements in technology, and what (13)
. are the future trends in semiconductor fabrication processes?
15 Create a test bench in Verilog HDL for the following circuits and validate its
. functionality.
(a) Full Adder(b) Code converter
PART -C
1. Compare and contrast the design methodologies of Full Custom ASIC and Semi (15)
Custom ASIC in VLSI (Very Large Scale Integration) circuits. Explain the key
 characteristics, advantages, and limitations of each approach. Discuss the factors that
influence the choice between Full Custom and Semi Custom ASICs for specific
applications, considering factors such as design complexity, performance, area
utilization, time-to-market, and manufacturing cost.
2. Discuss in detail about different types of scan design method and explain with neat (15)
diagram.
3. Create a test bench in Verilog HDL for a 4-bit Ripple Carry Adder (RCA) circuit. (15)
Explain the steps involved in writing the test bench code, including the generation of
test vectors and the implementation of test cases. Describe the expected behavior of
the RCA circuit during simulation and how the test bench can validate the correctness
of the adder's output.
4. Provide a detailed overview of the wafer-to-chip fabrication process in VLSI (15)
manufacturing. Outline the sequential steps involved, commencing with the initial
wafer preparation and culminating in the final chip packaging.
5. Create a test bench in Verilog HDL for the following circuits and validate its (15)
functionality.
(a) 4-bit Asynchronous Counter
(b) PIPO shift register