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Verilog Code For 4

This Verilog code implements a 4-bit Johnson counter, which is a synchronous counter that sequences through the binary numbers in a specific order. It uses a case statement to define the next state based on the current state, and assigns the next state value to a temporary register 'temp' which then gets assigned to the output 'q' on each clock cycle. A testbench module is provided to simulate the Johnson counter by toggling the clock input and displaying the output 'q' over time.

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AakarshBhusanur
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118 views

Verilog Code For 4

This Verilog code implements a 4-bit Johnson counter, which is a synchronous counter that sequences through the binary numbers in a specific order. It uses a case statement to define the next state based on the current state, and assigns the next state value to a temporary register 'temp' which then gets assigned to the output 'q' on each clock cycle. A testbench module is provided to simulate the Johnson counter by toggling the clock input and displaying the output 'q' over time.

Uploaded by

AakarshBhusanur
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOCX, PDF, TXT or read online on Scribd
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//Verilog code for 4-bit Johnson counter [synchronous counter]

module jhncntr(clk, q);


input clk;
output [3:0] q;
reg [3:0] q;
reg [3:0] temp;
always@(posedge clk)
begin
case (temp)
4'b0000: temp = 4'b1000;
4'b1000: temp = 4'b1100;
4'b1100: temp = 4'b1110;
4'b1110: temp = 4'b1111;
4'b1111: temp = 4'b0111;
4'b0111: temp = 4'b0011;
4'b0011: temp = 4'b0001;
4'b0001: temp = 4'b0000;
default temp = 4'b0000;
endcase
q= temp;
end
endmodule

//Testbench for 4-bit Johnson counter [synchronous counter]


module jhncntrtest_v;
// Inputs
reg clk;
// Outputs
wire [3:0] q;
// Instantiate the Unit Under Test (UUT)
jhncntr uut (
.clk(clk),
.q(q)
);
always
#10 clk=~clk;
initial begin
// Initialize Inputs
clk = 0;#400;
$stop;
end
endmodule

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