1. Write a Verilog to generate the three times multiplication table.
// Define a module that generates the three times multiplication table
module ThreeTimesTable(
input clk, // Clock input for synchronization
input reset, // Reset input to initialize or restart the table
generation
output reg [7:0] result, // 8-bit output for the multiplication result
output reg [3:0] index // 4-bit output for the current multiplier index
);
reg [3:0] counter; // 4-bit counter used as multiplier
// Process block triggered on the rising edge of the clock
always @(posedge clk) begin
if (reset) begin
// Resetting the counter, result, and index to 0
counter = 4'b0000; // Initialize counter with a 4-bit width for
consistency
result <= 8'b00000000; // Reset result to 0
index <= 4'b0000; // Reset index to 0
end else if (counter < 10) begin
// On each clock cycle, increment the counter and calculate the new
result
counter <= counter + 1; // Increment counter
result <= counter * 3; // Calculate three times the counter
index <= counter; // Update the index to current counter value
end
end
endmodule
// Testbench module to simulate the ThreeTimesTable module
`timescale 1ns/1ps
module tb_three_times_table;
// Inputs to the module
reg clk;
reg reset;
// Outputs from the module
wire [7:0] result;
wire [3:0] index;
// Instantiate the ThreeTimesTable module
ThreeTimesTable uut (
.clk(clk),
.reset(reset),
.result(result),
.index(index)
);
// Clock generation process
initial begin
clk = 0; // Initialize clock to low
forever #5 clk = ~clk; // Toggle clock every 5 time units
end
// Test stimulus process
initial begin
// Monitor output on each clock cycle
$monitor("Time=%t, 3 * %d = %d", $time, index, result);
// Initialize the simulation with a reset
reset = 1; // Apply reset
#10; // Wait for 10 time units
reset = 0; // Release reset
// Wait for 100 time units to observe the outputs
#100;
// Stop the simulation
$stop;
end
endmodule
2. Write a Verilog code to implement a counter that cycles through two distinct ranges based
on a mode: initially counting from 5 to 12, and then, upon reaching the end of this range,
switching to count from 0 to 15.
module counter (
input wire clk, // Clock input
input wire reset, // Reset signal input
output reg [3:0] count // Output: 4-bit counter (5 to 12, then 0 to 15)
);
// State variable to indicate the mode: 0 for 5 to 12, 1 for 0 to 15
reg mode;
always @(posedge clk or posedge reset) begin
if (reset) begin
count <= 4'b0101; // Reset the counter to 5
mode <= 1'b0; // Set mode to 5 to 12 counting
end else begin
if (mode == 1'b0) begin
if (count < 4'b1100) begin
count <= count + 1; // Increment the counter from 5 to 12
end else begin
count <= 4'b0000; // Reset the counter to 0 when it
reaches 12
mode <= 1'b1; // Switch to 0 to 15 counting mode
end
end else begin
if (count < 4'b1111) begin
count <= count + 1; // Increment the counter from 0 to 15
end else begin
count <= 4'b0000; // Reset the counter to 0 when it
reaches 15
end
end
end
end
endmodule
module tb_counter;
// Inputs
reg clk;
reg reset;
// Outputs
wire [3:0] count;
// Instantiate the counter module
counter counter_inst (
.clk(clk),
.reset(reset),
.count(count)
);
// Clock generation
always begin
#5 clk = ~clk; // Toggle the clock every 5 time units
end
// Testbench logic
initial begin
// Initialize inputs
clk = 0;
reset = 0;
// Apply reset for the first few clock cycles
#10 reset = 1;
#10 reset = 0;
// Monitor the counter value for 50 time units
// Display the value each time it changes
$monitor("Time=%t, Count=%d", $time, count);
#500 $finish; // End the simulation after 50 time units
end
endmodule
3. Write a Verilog module that determines if a given number is even or odd, and outputs a
result of 1 for even numbers and 0 for odd numbers using function.
module Test;
// Define a function named isEvenOrOdd which takes an input 'a' and returns
a bit indicating if the number is even or odd
function bit isEvenOrOdd(input logic a);
bit result; // Declare a variable 'result' of type bit
// Check if the input number is divisible by 2
if (a % 2 == 0)
result = 1; // Set result to 1 if the number is even
else
result = 0; // Set result to 0 if the number is odd
return result; // Return the result
endfunction
// Initial block to execute code at the beginning of simulation
initial
begin
bit result; // Declare a variable 'result' of type bit
logic input_value = 10; // Declare and initialize an input value
// Call the isEvenOrOdd function with input_value and store the result
result = isEvenOrOdd(input_value);
// Display the input value and the result
$display("Input: %0d, Result: %0d", input_value, result);
end
endmodule
4. Write a SystemVerilog code to identify and display numbers divisible by 8 within the range
of 0 to 100?
// Define a SystemVerilog class named DivisibleByEight
class DivisibleByEight;
// Method to find and display numbers divisible by 8
static function void findDivisibleByEight();
// Loop through numbers from 0 to 100
for (int i = 0; i <= 100; i++) begin
// Check if the current number is divisible by 8
if (i % 8 == 0)
// If divisible by 8, display the number
$display("Number %0d is divisible by 8", i);
end
endfunction
endclass
// Testbench module
module TestBench;
// Initial block to execute at the beginning of simulation
initial begin
// Call the findDivisibleByEight method of the DivisibleByEight class
DivisibleByEight::findDivisibleByEight();
// Finish simulation
$finish;
end
endmodule
5. Write a SystemVerilog program that utilizes a function to calculate the sum of two numbers
and determine whether the result is odd or even.
class packet;
rand bit[31:0] data; // Declare a random 32-bit data variable
rand bit[31:0] addr; // Declare a random 32-bit address variable
rand bit [31:0] sum; // Declare a random 32-bit sum variable
// Constructor for the 'packet' class
function new (int data, int b);
this.data = data; // Assign the input 'data' to the class data variable
addr = b; // Assign the input 'b' to the class address variable
sum = data + addr; // Calculate the sum of data and address and assign it
to the class sum variable
// Check if the sum is odd or even and display the result
if (sum % 2 == 1)
$display("Sum is ODD");
else
$display("Sum is EVEN");
endfunction
endclass
// Define a testbench module named 'tb'
module tb;
initial
begin
// Create an instance of the 'packet' class with data=10 and address=20
packet pkt = new(10, 20);
// Display the data and address of the 'pkt' instance
$display("DATA = %0d, ADDR = %0d", pkt.data, pkt.addr);
// Display the sum of data and address in the 'pkt' instance
$display("SUM = %0d", pkt.sum);
end
endmodule
6. Check output is high within in 20ns.
module test;
timeunit 1ns;
timeprecision 100ps;
// Declare input/output signals and a reset signal
bit a, b, y, reset = 1;
property data;
// Waits for a rising edge on both a and b signals, disables if reset is
low
@(posedge(a && b)) disable iff (reset == 0)
// Upon event, execute the following sequence
(1, set()); // Call the set task
endproperty
task automatic set();
// Declare a variable to store real-time
realtime t;
// Start parallel execution
fork
// Wait for transition on signals a and b, then record the current time
@(a && b) t = $realtime;
// Wait for 20 ns
#20;
join_any
// If y becomes 1 within 20ns, assert the condition
am_aby: assert(y == 1)
// Display the time taken for y to go high
$display("y went to 1 after %t", $realtime - t);
else
// If y does not become 1 within 20ns, display a message
$display("y did not go to 1 within 20ns");
endtask
// Initial block to finish simulation after 100ns
initial
begin
#100;
$finish;
end
endmodule
7. How can you define a constraint in SystemVerilog to generate a 10-bit number where more
than one bit is set to 1, but no two set bits are adjacent to each other?
// Define a class named "sample"
class sample;
rand bit [9:0] x; // Declare a 10-bit random variable x
// Define a constraint named "c"
constraint c
{
$countones(x) > 1; // Ensure x has more than one bit set to 1
foreach(x[i]) // Iterate through each bit of x
{
// If the current bit is set and is not the last bit in x,
// ensure the next bit is not set (i.e., no two adjacent bits are set)
if(i < 9 && x[i] == 1)
x[i+1] != 1;
}
};
endclass
// Testbench module to instantiate and test the "sample" class
module tb;
sample s = new(); // Instantiate an object of class sample
initial begin
repeat(2) begin // Generate and display the random value twice
s.randomize(); // Randomize the object s according to its constraints
$display("%b", s.x); // Display the generated 10-bit number in binary
end
end
endmodule
8. Write the constraint to gen. this seq. 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 0 1 0 2 0 3 0 4 0 5
... in array.
// Define a SystemVerilog class named sample
class sample;
// Declare a rand array of 8-bit elements
rand bit[7:0] array[];
// Constraint block to constrain the properties of the array
constraint array_c {
// Constraint to limit the size of the array between 20 and 30 elements
array.size() inside {[20:30]};
// Loop through each element of the array
foreach(array[i]) {
// Constrain even-indexed elements to be 0
if (i % 2 == 0)
array[i] == 0;
// Constrain the first element to be 1
else if (i == 1)
array[i] == 1;
// Constrain elements at multiples of 19 to be 1
else if (i % 19 == 0)
array[i] == 1;
// Constrain other elements to increment by 1 compared to the previous
odd-indexed element
else
array[i] == array[i-2] + 1;
}
}
endclass
// Define a top-level module named top
module top;
// Instantiate an object of the sample class
sample s = new();
// Initial block to execute at the beginning of simulation
initial begin
// Repeat the simulation 5 times
repeat(5) begin
// Randomize the properties of the sample object and assert success
assert(s.randomize());
// Display the randomized array
$display("array = %p", s.array);
end
end
endmodule
9. Constraint that should follow the below Rules
I. The dynamic array should contain 20 items.
II. Out of 20 items, the values of 3 items should be equal to 5 at random positions.
III. The values of 5 items must be 10 at random positions
IV. The values of 8 items must be 15 and the remaining 4 items must be 20.
// Define a SystemVerilog class named test
class test;
// Declare a rand array of 5-bit elements
rand bit[4:0] array[];
// Constraint block to constrain the properties of the array
constraint c1{
// Constraint to ensure the size of the array is 20
array.size == 20;
// Constraint to ensure the sum of elements equal to 5 occurs 3 times
array.sum() with ((item == 5) ? 1 : 0) == 3;
// Constraint to ensure the sum of elements equal to 10 occurs 5 times
array.sum() with ((item == 10) ? 1 : 0) == 5;
// Constraint to ensure the sum of elements equal to 15 occurs 8 times
array.sum() with ((item == 15) ? 1 : 0) == 8;
// Constraint to ensure the sum of elements equal to 20 occurs 4 times
array.sum() with ((item == 20) ? 1 : 0) == 4;
}
endclass
// Define a top-level module named sum
module sum;
// Instantiate an object of the test class
test t1;
// Initial block to execute at the beginning of simulation
initial begin
// Create a new object of the test class
t1 = new;
// Randomize the properties of the test object and assert success
assert(t1.randomize);
// Display the randomized array
$display("array = %p", t1.array);
// Sort the array for better understanding
t1.array.sort();
// Display the array after sorting
$display("\narray value after sorting for understanding\narray = %p",
t1.array);
end
endmodule
10. Write a constraint for an array of numbers such that the size of array ranges from 6 to 15
elements, and even index locations should have odd numbers and odd index locations
should have even numbers, numbers rage is between 16 to 127.
// Define a SystemVerilog class named packet
class packet;
// Declare a rand array of 7-bit elements
rand bit[6:0] array[];
// Constraint block to constrain the properties of the array size
constraint array_c {
array.size() inside {[6:15]}; // Constraint to limit the size of the
array between 6 and 15 elements
}
// Constraint block to constrain the range of elements in the array
constraint elements {
foreach (array[i])
array[i] inside {[16:127]}; // Constraint to limit each element to the
range between 16 and 127
}
// Constraint block to ensure even-indexed elements are odd and odd-indexed
elements are even
constraint even {
foreach(array[i]) begin
if (i % 2 == 1) // For odd-indexed elements
array[i] % 2 == 0; // Constrain to be even
else // For even-indexed elements
array[i] % 2 != 0; // Constrain to be odd
end
}
endclass
// Define a test module
module test;
// Instantiate an object of the packet class
packet pkt;
// Initial block to execute at the beginning of simulation
initial begin
// Create a new object of the packet class
pkt = new;
// Repeat the simulation 5 times
repeat(5) begin
// Randomize the properties of the packet object
pkt.randomize();
// Display the values of the array
$display("The values of odd and even: %p", pkt);
end
end
endmodule
/or/
// Define a SystemVerilog class named sample
class sample;
// Declare a rand array of 7-bit elements
rand bit[6:0] array[];
// Constraint block to constrain the properties of the array
constraint array_c {
// Constraint to limit the size of the array between 6 and 15 elements
array.size() inside {[6:15]};
// Iterate through each element of the array
foreach(array[i]) {
// Constraint to limit each element to the range between 16 and 127
array[i] inside {[16:127]};
// Constrain the most significant bit (MSB) of each element based on
the index parity
if (i[0] == 0)
array[i][0] == 1; // Set MSB to 1 for even-indexed elements
else
array[i][0] == 0; // Set MSB to 0 for odd-indexed elements
}
}
endclass
// Define a top-level module named top
module top;
// Instantiate an object of the sample class
sample s = new();
// Initial block to execute at the beginning of simulation
initial begin
// Repeat the simulation 5 times
repeat (5) begin
// Randomize the properties of the sample object
s.randomize();
// Display the randomized array
$display("array = %p", s);
end
end
endmodule
