FPGA Based Sine-Cosine Encoder

er Feedback
Processing for Servo Drive Applications
Appl cations
Jens Onno Krah - Heiko Schmirgel
Cologne University of Applied Sciences,
Betzdorfer Str. 2, 50679 Kln, Germany
Keywords:
Sine Cosine Encoder, Observer, Servo Drives, Programmable Logic Device,
Device FPGA,

BiSS , EnDat , Hiperface DSL , DRIVE CLiQ , Embedded Control, Motion Control

Abstract
Controlled servo drives are used in many areas of automation technology, robotics
and handling systems as well as in the drive technology of production machines and
machine tools. The requirements regarding dynamics, speed stability and rigidity require ever increasing bandwidth in the control loops. This contribution describes
FPGA based concepts to connect encoders to servo drives. Due to digital filters imi
plemented in an FPGA the position signal quality can be significantly
significant increased. In a
servo drive the better signal to noise ratio can be used to build a smoother motor curcu
rent (less noisy), or to increase the control loop gain factors.
Introduction

served to realize digital interface logic. This logic

configuration is usually able to cover several digital
feedback interfaces.

High performance servo drives are still a fast growing

market segment. High resolution encoders are comco
monly used as motor position sensing device,
device fig. 1.
Also, most modern controllers derive velocity feedfee
back from the position sensor. The conversion of sinecosine-encoder
encoder signals to measure position
posi
is more
and more accomplished within the encoder. Due to a
digital link to the drive long cables with fewer wires
do not limit the maximal signal frequency and do not
reduce the feedback signal quality.

Sine-cosine encoders are an extension to standard A

quad B encoders. For the manufacturers
manufacture it is much
easier to design optical encoders with sinusoidal sigsi
nals than TTL encoders with very high line numbers.
The operating principle is that the subsequent electronics counts the sine waves and also performs tan-1
fine interpolation within one signal period, fig 2.

Fig. 1: Hengstler sine cosine encoder AD 5858

BiSS [1]
Most servo drive designers are not willing to design in
special dedicated chips. Modern drives
rives usually feature
Field Programmable Gate Array
rray (FPGA)
(
area re-

PCIM 2007 Session 4d-3

Fig. 2: Decoding sinus

us cosine encoder signals
-1
with a counter and tan fine interpolation

Krah, Schmirgel

Offset and Gain Error

The position resolution and the position error within one signal period
are the most relevant factors for fine interpolation.
interpolation The selection of the
encoder technology is strongly dependent on the accuracy requirements
of the respective application.
The measured angle
 from a sine cosine encoder with tan-1 fine interpolation is the sum of the real angle and an additional interpolation
error
:

 


The offset and gain interpolation error depends on:

cosoff:
rcos:
sinoff:
rsin:
n:

cosine signal
offset
cosine signal
amplitude
sine signal
offset
sine signal
amplitude
sine cosine lines per revolution
olution (usually 512 or 2048)

Fig. 3: Sine cosine offset error

With no significant errors (Taylor approximation) the interpolation error
can be calculated by:



1


78
=

tan
cos
 6 tan
sin
  < 6 tan
? sin/2
 1F

9:
9:

Using 1 Vss encoder signals rcos and rsin are ~500 mV. One percent
(5 mV) offset (cosoff and sinoff) and n = 512 lines per revolution are also
reasonable values. Due to a gain error rcos can be one percent greater

than rsin :
 1.01 :
 !"



1
'(0.01 cos
 ) 0.01 sin
 ) 0.005 sin/2
 1@
512

The maximum angle error
*+ with the used offset and gain error is:
is

*+ 

1
1
,0.01 2  0.005A
0

rad
512
26747

This offers a maximum of 17.33 bit resolution per revolution due to the
gain and offset error. Where 9 bit come from the counter (n) and additional 8.3 bit are achievable due to the tan-1 fine interpolation. In case of
higher requirements an encoder with more lines per rev and/or an ex- Fig. 4: Sincos gain error
tended fine interpolation with on-line
line gain and offset adjustment are
necessary.
In most cases the bottleneck of the system is not the position precision. Most servo systems derive the more
critical velocity feedback signal from the measured position signal with an observer:
. /01 

23

 /01

To examine the velocity error . it is enough to derive the position error:

./01 

23

/01 with

/01  '(0.01 cos
 /01 ) 0.01 sin
 /01 ) 0.005 sin/2
 /011@
4

and

 /01  .5 0 
. 0

PCIM 2007 Session 4d-3

Krah, Schmirgel

We get


/01  '(0.01 cos/

. 01 ) 0.01 sin/
. 01 ) 0.005 sin/2
. 01@
4

After some math we get an equation for the relative speed error:
G/31
G

 )0.01 sin/
. 01 ) 0.01
01 cos/
. 01 ) 0.01 cos/2
. 01

Not Synchronous Sampling Error.

E
Not exactly synchronous sampling of the two channels generates also an additional position error: For a mathematical analysis the cosine signal is viewed as
delayed with the delay time TD. This shows the same behavior like sampling
the cosine signal TD earlier compared with the sine sampling time. This is degenerating the circle to an ellipse with 45 rotated axis, Fig. 5.
At zero speed the encoder signal is constant and so the delay TD does not matter. In case of a rotating motor with the encoder signal frequency . 
.
the delay time generates a speed proportional phase shift of the cos signal:

H  . IH  .
IH

Fig. 5: Cosine delay error

This phase lag causes a velocity dependent position error:



H 1 6 cos/2
 1
1 6 cos/2
. 01
 . IH

2
2

And a velocity error:

./01

H sin/2
. 01
.

Analog to Digital Conversion Error

ADC based offset and gain errors do not need a separate review. These errors are handled together with
the analog encoder offset and gain error. With a 12-bit
analog to digital converter (industry standard) the
quantization noise is about 0.05
0.05 % (100 % / 2048).
There are two ways to reduce this noise:
Select higher resolution ADC (higher SNR)
SNR
Take advantage of oversampling technique

Rotating a 2048 line encoder with n = 3000 rpm generates a fE = 50 Hz * 2048 = 102.44 kHz encoder signal
frequency. A delay time of only 15.6 ns generates a
phase lag of:

H  . IH 

 2= 102.4 kHz 15.5 ns  0.01 rad

Due to the noisy environment inside a servo drive the

use of a higher resolution ADC is not trivial. Setting a
low pass filter is more or less not possible because of
the high frequency encoder signals
signal (>250 kHz).

And also a one percent (high speed) velocity error:

./01
 0.01 sin/2
. 01
.
Looking at these equations we conclude:
conclude

Usually the encoder position is required with the

feedback loop update frequency:
The current controller uses the commutation (low
resolution is ok)
The velocity controller needs a speed feedback
fe
signal (position derivative))
Thee position controller requires a position feedfee
back signal

1%
% offset on the encoder sine and/or cosine sigsi
nal forces a 1% velocity error with encoder signal
frequency.
1%
% gain error between the signals forces
f
a 1%
velocity error with double encoder signal frefr
quency.
0.01 radiant phase error between the signals
forces a 1% high speed velocity error with double
encoder signal frequency.

PCIM 2007 Session 4d-3

Krah, Schmirgel

This update frequency is usually related to the power

stage switching frequency. In a servo drive with
fs = 8 kHz switching frequency is the fastest current
loop update (sample) time usually T0 = 62.5 s.

pass with minor phase lag if the acceleration

(

10

15
E T0

20

GD(jj)

Due to the oversampling technique the Danaher Motion S 700 Servo Drive is offering outstanding perpe
formance in processing analog sine cosine signals [2].

-20
-30

Digital Encoder Interfacing

ing

-40

If the full achievable performance is not required

digital feedback busses are options to reduce cost: less
wires
res and less electromagnetical interference influenced by using long cables. There are several digital
feedback busses on the market..

-50
-60
Fig. 6: Encoder frequency E and sample time
tim
T0 velocity
elocity ripple damping function

BiSS

The position error is not affected by the sample time.

The bidirectional digital sensor interface standard

BiSS provides communication between position ene
coders or measuring devices and industrial controls,
such as a drive control,
ntrol, for example. BiSS is based on
two unidirectional RS 485 channels with baud rates
up to 10 MBaud.
One clock channel from the control unit to the
sensor and
One data channel from the sensor to the control
unit.

If the system is powerful enough to process the ene

coder signal several times within one servo loop update time the quantization noise can be significantly
significant
reduced by oversampling, Fig. 7.

The BiSS protocol classifies each subscriber in one of

the following data sections: sensor data, multi cycle
data or register data. Using the digital communication
as a bidirectional service data channel (BiSS Register-Mode)
Mode) the drive manufacturer can read an elecele
tronic type
pe plate to configure the drive within an auto
setup process. In this mode the clock is PWM modumodu
lated to transmit data from the control unit to the
encoder.

Fig. 7: Position signal filter (with oversampling)

o
Oversampling by utilizing flash ADCs and FPGA
based digital signal processing with a sampling rate of
16 MHz and more is realistic. Fig. 7 shows the block
diagram of a third order velocity observer. The posipos
tion is calculated with an update rate of 16
1 MHz.
This position is compared with the estimated observer
position
R.. The difference is used as observer feedfee
back signal. In fact the observer is acting like a low

PCIM 2007 Session 4d-3

TU  U  T   TQ
 TU  U  T   TQ

This boosts a 12-Bit ADC up to 15-Bit SNR performance. Another option is to use the DSP capability of
the FPGA to execute an on-line
line offset and gain adjustment.

dB
-10

V

By setting
etting this low pass cut off frequency to 50 kHz
(with a0 , a1 , a2) the quantization
uantization noise can be reduced
by approximately 20 dB:
5 MHz
W  10 dB logQ
50 kHz

sin/. P IQ 1
. P IQ

1 is not constant:
M/1 

Sampling itself is also an important issue. If the ene

coder frequency is near or higher than the sampling
frequency the speed error amplitude is damped to a
lower value with a different frequency (aliasing),
fig 6.
MN /j.1 

2S

23 S

Using the digital communication as a fast process

data channel (BiSS Sensor-Mode)
Mode) the encoder will

Krah, Schmirgel

provide a high resolution position signal and additional alarm and warning bits with high update rates. A
motor winding over temperature signal could be
mapped into the alarm bit for example. Via the optional Multi Cycle Data (MCD) channel the position
sensor can send sequential low update rate informainform
tion, like encoder temperature.
The fastest position update rate is below 20 s. Most
BiSS Encoders offer optionally also 1 Vss analog
sine/ cosine signals [3].
The servo drive manufacturer design engineer gets a
proved ready to use solution with well known specifispecif
cations by using a specific BiSS master chip. The
disadvantages are the high component cost for the
BiSS master and the necessary PCB-space [4].
An ALTERA BiSS FPGA implementation template is
as QUARTUS
ARTUS II project with VHLD source code as
download available [5, 6].

Fig. 9: SINAMIC S120 with DRIVE-CLiQ

D
[7]

EnDat
The EnDat interface from HEIDENHAIN is a digital,
bidirectional interface for encoders. It is capable both
of transmitting position values from incremental and
absolute encoders as well as transmitting or updating
information stored in the encoder, or saving new ini
formation. EnDat is based on one unidirectional
unidirec
RS485 clock channel and one bidirectional data chancha
nel. The data is transmitted in synchronism with the
clock signal from the subsequent electronics. The type
of transmission (position values, parameters, diagnosdiagno
tics, etc.) is selected by mode commands that the
subsequent electronics send to the encoder.

Fig. 8: BiSS interface

face data transmission with
two unidirectional terminated RS485
lines plus power supply

DRIVE-CLiQ
DRIVE-CLiQ, the Siemens standard digital interface
between the essential SINAMIC S120 drive compocomp
nents including motors and encoders reduces the
t
number of different parts. Electronic type plates in the
components allow all of the drive components to be
automatically detected via the Drive-CLiQ
Drive
cable.

EnDat version 2.1 supports clock rates up to 1 MHz

andd no cable length compensation. EnDat
EnD version 2.2
supports clock rates up to 16 MHz with cable length
compensation.

It is used to connect a motion controller with several

servo drives and also to connect the drives with the
motor build in feedback device. It is a non standarstanda
dized closed system based on fast (100 MBit) EtherEthe
net with a 24 V feedbackk power supply extension.
Fastest position update rate is 31.225 s. Electronic
type plate functionality is available. Analog signals
are not supported. Until now Siemens is not interested
in opening the DRIVE CLiQ interface specification to
third party industrial controls or motor manufacturers.
manufacturers

PCIM 2007 Session 4d-3

In high performance servo drives EnDat

EnD 2.1 is always
used in combination with analog sine
sin and cosine signals. The digital channel is used for
f type plate data,
commutation information and multi turn data.
With EnDat 2.2 the use of the analog signals is not
necessary due to the much faster communication.
That saves several wires of the feedback cable. The
fastest position update rate is below 18 s.

Krah, Schmirgel

a standard (RS232) UART, as implemented on almost

all popular microcontrollers/DSPs.
controllers/DSPs. The interface is
configured to 9600 baud, as standard. Each protocol is
completed with an easy to calculate XOR checksum.
The end of the protocol is detected using a timeout
control.
STEGMANN interface is under
A full digital SICK-STEGMANN
development. HIPERFACE DSL is planned to be
available in two interface versions:
A RS485
485 version with separate logic power and
signal wires
A DSL version with power and signals using the
same wires

Figure 10: EnDat 2.2 required only 6 wires [8]

EnDat 2.2 FPGA sample code download for the EBV
Electronic development board (Altera Quartus II
VHDL) is available [5, 6].
MAZeT is also offering a commercial soft-macro (IP)
of the EnDat 2.2 interface. It describes the control
side part (also referred to as the master component) of
the interface between an absolute position encoder
from HEIDENHAIN and a users subsequent elecele
tronics [9].

Detailed technical data is not published until now.

HIPERFACE DSL is planned to be available in 2008.

Conclusion
This paper describes methods to interface high resoluresol
tion encoders with a drive using FPGA and microconmicroco
troller technology.

HIPERFACE
Is the short for High Performance
formance Interface
Inter
and the
standard interface for SICK-STEGMANN
STEGMANN motor
feedback systems.

There is no microcontroller on the market which can

support industrial digital encoder interfaces. No drive
Manufacturer is willing to use several dedicated integrated circuits to interface different encoders. Siemens for example supports only their company interinte
nal DRIVE CLiQ. However BiSS and EnDat can be
easily implemented in a standard FPGA with RS485
drivers [5].. HIPERFACE DSL is probably also a
candidate for an FPGA solution
olution using the same hardware.

This interface was also developed for the requirerequir

ments of digital drive control and offers the user a
standardized and simplified electrical interface.
interfac
HIPERFACE defines the standardized electrical
interface with 8 wires:
2x supply voltage 7 12 V
4x analog incremental,
ncremental, differentially transmitted,
sine/cosine signals
2x digital,
igital, bidirectional RS485 interface

Real high performance (direct drive) applications can

take advantage of an FPGA integrated observer based
encoder interface solution
on with flash ADC, oversamoversa
pling and on-line offset / error correction.

References
1. Hengstler,

www.Hengstler.com

2. SR 700 Manual

www.DanaherMotion.net

3. BiSS-Interface

www.biss-interface.de
interface.de

4. IC-Haus,

www.icHaus.de

5. Download:

Figure 11: HIPERFACE still uses analog signals [10]

[
A fully screened 8TP cable securely transmits the
signals to the controller. The protocol is handled with

PCIM 2007 Session 4d-3

www.f07.fh-koeln.de/fakultaet/
koeln.de/fakultaet/
personen/professoren/
personen/professoren/jens.krah/

6. EBV,

www.ebv.com www.devboards.de
www.ebv.com,

7. Siemens,

www.automation.siemens.com

8. Heidenhain,

www.heidenhain.de

9. MAZeT:

www.MAZeT.de

10. Sick-Stegmann,

www.stegmann.de

Krah, Schmirgel