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    GC3355 Application NOTE

    Uploaded by

    MarcianoValverde
    This document describes the UART mode of the GC3355 Application chip, which supports both Bitcoin (BTC) and Litecoin (LTC) mining. It provides examples of configuring the chip to operate in BTC-only mode, LTC-only mode, and combined BTC+LTC mode. Registers are configured via commands sent from a host CPU to individual chips or broadcast to all chips. Data and control registers are defined for the BTC and LTC modules to initialize the mining work.

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    © All Rights Reserved
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    GC3355 Application NOTE

    Uploaded by

    MarcianoValverde
    183 views5 pages
    This document describes the UART mode of the GC3355 Application chip, which supports both Bitcoin (BTC) and Litecoin (LTC) mining. It provides examples of configuring the chip to operate in BTC-only mode, LTC-only mode, and combined BTC+LTC mode. Registers are configured via commands sent from a host CPU to individual chips or broadcast to all chips. Data and control registers are defined for the BTC and LTC modules to initialize the mining work.

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    This document describes the UART mode of the GC3355 Application chip, which supports both Bitcoin (BTC) and Litecoin (LTC) mining. It provides examples of configuring the chip to operate in BTC-only mode, LTC-only mode, and combined BTC+LTC mode. Registers are configured via commands sent from a host CPU to individual chips or broadcast to all chips. Data and control registers are defined for the BTC and LTC modules to initialize the mining work.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    183 views5 pages

    GC3355 Application NOTE

    Uploaded by

    MarcianoValverde
    This document describes the UART mode of the GC3355 Application chip, which supports both Bitcoin (BTC) and Litecoin (LTC) mining. It provides examples of configuring the chip to operate in BTC-only mode, LTC-only mode, and combined BTC+LTC mode. Registers are configured via commands sent from a host CPU to individual chips or broadcast to all chips. Data and control registers are defined for the BTC and LTC modules to initialize the mining work.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
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    GC3355 APPLICATION NOTE

    GC3355 Application NOTE

    Version 1.0

    Page 1 of 5

    GC3355 APPLICATION NOTE

    Version

    Date

    Description

    1.0

    2013-11-28

    Initial version

    Page 2 of 5

    GC3355 APPLICATION NOTE

    1. General Description
    GC3355 supports two configuration mode: PN mode(CFG_P/CFG_N mode) and
    UART mode. PN mode is back compatible with previous BTC mining ASIC chips, and
    support BTC mining only. UART mode can support BTC and LTC, this Application note
    describe UART mode only.
    The following is one example of Mining System, with one Host CPU and 4
    GC3355 chips. The CPU will run two cgminer programs, one for BTC mining and
    another for LTC mining. Each GC3355 chip is assigned with one different ID to be
    accessed by the Host CPU. The ID is used as chip address in the Mining System.

    The following is the communication command from Host CPU to GC3355:


    55, AA, {CLUS_ADDR[3:0], CHIP_ADDR[3:0]}, REG_ADDR[7:0], DATA[7:0],
    DATA[15:8], DATA[23:16],DATA[31:24]
    The UART mode also supports burst command, the data can be 32*N bits, for
    example:
    55, AA, {CLUS_ADDR[3:0], CHIP_ADDR[3:0]}, REG_ADDR[7:0], DATA0[7:0],
    DATA0[15:8], DATA0[23:16], DATA0[31:24], DATA1[7:0], DATA1[15:8], DATA1[23:16],
    DATA1[31:24], ..., DATAN-1[7:0], DATAN-1[15:8], DATAN-1[23:16], DATAN-1[31:24]
    The DATA0, DATA1, DATAN-1 will be written to the following register
    address: REG_ADDR, REG_ADDR+1, REG_ADDR+N-1.

    Page 3 of 5

    GC3355 APPLICATION NOTE

    Each GC3355 chip only responses the command with the chip_id == the
    CHIP_ADDR, or the CHIP_ADDR is 0xf which denote broadcast. In another words, if
    the command is broadcast (the CHIP_ADDR is 0xf), all the chips will response the
    command.
    The CLUS_ADDR denote the function module in the GC3355: 0 is BTC module,
    1 is LTC module; 0xE is CPM module.
    The REG_ADDR is the register address in each function module. Please
    reference the registers description for detailed information.

    2. BTC work Mode


    The following code is an example: xclk is 25MHz, core clock is 500MHz, force_start=0,
    rpt_cycle = 0x10
    cfg_chip_reg(8'hef, 8h00, 32h94e00005);
    cfg_chip_reg(8h0f, 8hff, 32h00000010);
    cfg_btc_data; //configure the BTCs data, which address is 0x00xb

    3. LTC work mode


    the following code is an example: xclk is 25MHz, core clock is 500MHz,
    configure the UARTs, timeout = 0x10
    cfg_chip_reg(8'h1f, 8'h28, ltc_cfg_ctrl); // ltc_cfg_ctrl = 0x00000013
    cfg_chip_reg(8'hef, 8'h30, ltc_cfg_reg); //ltc_cfg_reg = 0x00000020
    cfg_chip_reg(8'hef, 8h00, 32h 94e00005);// pll config
    cfg_chip_reg(8hef, 8h02, 32h0000_0000);//gating BTCs core0- core31 clk
    cfg_chip_reg(8hef, 8h03, 32h0000_0000);//gating BTCs core31-core63 clk
    cfg_chip_reg(8hef, 8h04, 32h0000_0000);//gating BTCs core64-core95 clk
    cfg_chip_reg(8hef, 8h05, 32h0000_0000);//gating BTCs core96-core127 clk
    cfg_chip_reg(8hef, 8h06, 32h0000_0000);//gating BTCs core128-core159 clk
    Page 4 of 5

    GC3355 APPLICATION NOTE

    cfg_chip_reg(8'hef, 8'h20, uart_bps); // uart_bps


    cfg_chip_reg(8'hef, 8'h21, uart_timeout);//uart_timeout= 0x80000018
    cfg_ltc_data;//config the ltcs data, which address are 0x00x22, min/max nonce: 0x23,
    0x24

    4. BTC+LTC work mode


    the following code is an example: xclk is 25MHz, LTC/BTC core clk is 500MHz, configure
    the UARTs BPS

    cfg_chip_reg(8'hef, 8'h20, uart_bps); // uart_bps


    cfg_chip_reg(8'hef, 8'h21, uart_timeout);//uart_timeout= 0x80000018
    cfg_chip_reg(8'hef, 8'h30, ltc_cfg_reg); //ltc_cfg_reg = 0x00000020
    cfg_chip_reg(8'h1f, 8'h28, ltc_cfg_ctrl); // ltc_cfg_ctrl = 0x00000017
    cfg_chip_reg(8h0f, 8hff, 32h80000010);//btcs misc register
    cfg_chip_reg(8'hef,8h00, 32h 94e00005);// pll config
    fork
    cfg_btc_data
    cfg_ltc_data
    join

    Page 5 of 5

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