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    Reduced Instruction Set Computer (Risc) Complex Instruction Set Computer (Cisc)

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    Sundari Muthu
    The document compares and contrasts RISC and CISC processor architectures. RISC uses a minimal set of simple instructions that can perform essential operations like arithmetic and branching in a single cycle. CISC allows instructions to perform multiple operations like memory access and arithmetic. RISC has advantages like multiple register sets, 3-operand instructions, and efficient parameter passing through registers. CISC has disadvantages like variable length instructions, inefficient parameter passing through memory, and multiple cycle instructions. The example calculations show RISC performing a multiplication in fewer clock cycles than CISC.

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    Reduced Instruction Set Computer (Risc) Complex Instruction Set Computer (Cisc)

    Uploaded by

    Sundari Muthu
    35 views7 pages
    The document compares and contrasts RISC and CISC processor architectures. RISC uses a minimal set of simple instructions that can perform essential operations like arithmetic and branching in a single cycle. CISC allows instructions to perform multiple operations like memory access and arithmetic. RISC has advantages like multiple register sets, 3-operand instructions, and efficient parameter passing through registers. CISC has disadvantages like variable length instructions, inefficient parameter passing through memory, and multiple cycle instructions. The example calculations show RISC performing a multiplication in fewer clock cycles than CISC.

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    The document compares and contrasts RISC and CISC processor architectures. RISC uses a minimal set of simple instructions that can perform essential operations like arithmetic and branching in a single cycle. CISC allows instructions to perform multiple operations like memory access and arithmetic. RISC has advantages like multiple register sets, 3-operand instructions, and efficient parameter passing through registers. CISC has disadvantages like variable length instructions, inefficient parameter passing through memory, and multiple cycle instructions. The example calculations show RISC performing a multiplication in fewer clock cycles than CISC.

    Copyright:

    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd
    Download as docx, pdf, or txt
    35 views7 pages

    Reduced Instruction Set Computer (Risc) Complex Instruction Set Computer (Cisc)

    Uploaded by

    Sundari Muthu
    The document compares and contrasts RISC and CISC processor architectures. RISC uses a minimal set of simple instructions that can perform essential operations like arithmetic and branching in a single cycle. CISC allows instructions to perform multiple operations like memory access and arithmetic. RISC has advantages like multiple register sets, 3-operand instructions, and efficient parameter passing through registers. CISC has disadvantages like variable length instructions, inefficient parameter passing through memory, and multiple cycle instructions. The example calculations show RISC performing a multiplication in fewer clock cycles than CISC.

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    Reduced Instruction Set Computer

    ( RISC )

    Complex Instruction Set Computer


    ( CISC )

    provide a set of minimal instructions that could do


    all the essential operations (move data, arithmetic
    logic unit operations, branching)

    is a processor where each instruction can


    perform several low-level operations such as
    memory access, arithmetic operations or
    address calculations

    Multiple register sets, often consisting of more


    than 256 registers

    Single register set, typically 6 to 16 registers total

    Three register operands allowed per instruction


    (add R1, R2, R3)

    One or two register operands allowed per


    instruction (add R1, R2)

    Parameter passing through efficient on-chip


    register windows

    Parameter passing through inefficient off-chip


    memory

    has Single-cycle instructions (except for load and


    store)

    has Multiple-cycle instructions

    Hardwired control

    Microprogrammed control

    Highly pipelined

    Less pipelined

    Simple instructions that are few in number

    Many complex instructions

    Fixed length instructions

    Variable length instructions

    Complexity in compiler

    Complexity in microcode

    Only load and store instructions can access


    memory

    Many instructions can access memory

    Few addressing modes

    Many addressing modes

    Example : 5 X 10 = ?
    MOV AX, 0
    MOV BX, 10
    MOV CX, 5
    BEGIN : ADD AX, BX
    LOOP BEGIN

    Example : 5 X 10 = ?
    MOV AX, 10
    MOV BX, 5
    MUL BX, AX

    10+10+10+10+10=50
    Total clock cycles =
    (3 MOV X 1 clock cycle) +
    (5 ADD X 1 clock cycle) + (5 LOOP X 1 clock cycle)
    = 13 clock cycles

    10 x 5 = 50
    Total clock cycles =
    (2 MOV X 1 clock cycle) +
    (1 MUL X 30 clock cycle)
    = 32 clock cycles

    Superscalar Vs Superpipeline

    Base machine: 4-stage pipeline


    Instruction fetch
    Operation decode
    Operation execution
    Result write back
    *Although several instructions are executing
    concurrently, only one instruction is in its
    execution stage at any one time.
    Superpipeline of degree 2
    performing two pipeline stages per clock
    cycle
    The functions performed in each stage
    can be split into two nonoverlapping
    parts and each can execute in half a
    clock cycle.
    Benefit: achieved a very high clock
    frequency for its time. The single
    pipelined functional unit was simple to
    control and took up little space on the
    chip, leaving room for more cache and
    other components including a floating
    point unit and memory management
    unit.
    Disadvantages: with deeply pipeline
    instruction unit, branching instruction give a major problem. Branch penalty will increase with the
    increasing number of stages in pipeline.
    Superscalar of degree 2
    Two instructions are executed concurrently in each pipeline stage
    Duplication of hardware is required by definition
    Benefits :allows processors to execute more than one instruction per clock cycle with multiple
    pipelines
    Disadvantages : increase the level of complexity in hardware designing, Need additional register file
    ports, More complex hazard detection

    Pipelines

    Pipelines in computers are used to improve the performance of the basic instruction cycle.

    The goal is to improve the throughput of the computer, the number of instructions per second (MIPS),
    by overlapping tasks in the instruction cycle.

    Pipeline Stages:

    Fetch instruction (FI): Fetch the next instruction into the computer.

    Decode instruction (DI): Determine the opcode and the operand specifiers.

    Calculate operands (CO): Calculate the effective address of each source operand.

    Fetch operands (FO): Fetch each operand from memory. Operands in registers need not be fetched.

    Execute instruction (EI): Perform the requested operation.

    Write operand (WO): Write the result in memory.

    Pipeline Hazards :

    A risk in which pipeline operations stall (stop) for one or more clock cycles

    Three classes of pipeline hazards


    Resource hazard:

    Occur when two or more instructions in pipeline need the same resource

    Example : a simplified five stage pipeline, in which each stage takes one clock cycle

    Now assume that main memory has a single port

    All instruction fetches and data R/Ws must be performed one at a time

    An operand R/Ws from memory cannot be performed in parallel with an instruction fetch.

    Assumes that the source operand for I1 is in memory, rather than a register.

    Therefore, the fetch instruction stage of the pipeline must idle for one cycle before beginning
    the instruction fetch for I3.

    The figure assumes that all other operands are in registers.

    Solution :

    Increase available resources, such as having multiple ports into main memory and multiple
    ALU units.

    Data Hazard:

    Two instructions in a program are to be executed in sequence and both access a particular memory or
    register operand.

    Example : ADD EAX, EBX /* EAX = EAX + EBX


    SUB ECX, EAX /* ECX = ECX - EAX

    The ADD instruction does not update


    register EAX until the end of stage 5, which occurs at clock cycle 5.

    But the SUB instruction needs that value at the beginning of its stage 2, which occurs at clock
    cycle 4.

    To maintain correct operation, the pipeline must stall (stop) for two clocks cycles.

    Solution : data or register forwarding (bypassing or short-circuiting)

    Three types of data hazards

    Read After Write (RAW), a true dependency


    i1. R2 <- R1 + R3
    i2. R4 <- R2 + R3
    -

    The i1 is calculating a value to be saved in R2, and the i2 is going to use this value to compute a
    result for R4.

    However, in a pipeline, when we fetch the operands for the 2nd operation, the results from
    the first will not yet have been saved, and hence we have a data dependency.

    We say that there is a data dependency with instruction i2, as it is dependent on the
    completion of instruction i1.

    Write After Read (WAR), an anti-dependency


    i1. R4 <- R1 + R5
    i2. R5 <- R1 + R2
    -

    If we are in a situation that there is a chance that i2 may be completed before i1 (i.e. with
    concurrent execution) we must ensure that we do not store the result of register R5 before i1
    has had a chance to fetch the operands.

    Write After Write (WAW), an output dependency


    i1. R2 <- R4 + R7
    i2. R2 <- R1 + R3
    -

    Two instructions both write to same location

    We must delay the WB (Write Back) of i2 until the execution of i1.

    Control hazard:

    Occurs when the pipeline makes the wrong decision on a branch prediction and therefore brings
    instructions into the pipeline that must subsequently be discarded.

    Example :

    Inst. 3 is a conditional branch to inst. 20, which is taken.

    As soon as it is executed in step 6, the pipeline is flushed (instruction 3 is able to complete) and
    instructions starting at #20 are loaded into the pipeline.

    Note that no instructions are completed during cycles 7 through 10.

    Solution :
    -

    Multiple Streams

    Prefetch Branch Target

    Loop buffer

    Branch prediction

    Delayed branching

    Instruction Issue Policy

    In-order issue with in-order completion

    We assume a superscalar pipeline capable of fetching and decoding two instructions at a time,
    and having two instances of the write-back pipeline stage.

    The example assumes the following constraints on a six-instruction code fragment:


    I1 requires two cycles to execute.
    I3 and I4 conflict for the same functional unit.
    I5 depends on the value produced by I4.
    I5 and I6 conflict for a functional unit.

    Instructions are fetched two at a time and passed to the decode unit.

    Because instructions are fetched in pairs, the next two instructions must wait until the pair of
    decode pipeline stages has cleared.

    To guarantee in-order completion, when there is a conflict for a functional unit or when a
    functional unit requires more than one cycle to generate a result, the issuing of instructions
    temporarily stalls.

    In this example, the elapsed time from decoding the first instruction to writing the last results is
    eight cycles.

    In-order issue with out-of-order completion

    Instruction I2 is allowed to run to completion prior to I1.

    This allows I3 to be completed earlier, with the next result of a savings of one cycle.

    With out-of-order completion, any number of instructions may be in the execution stage at any
    one time, up to the maximum degree of machine parallelism across all functional units.

    Instruction issuing is stalled by a resource conflict, a data dependency, or a procedural


    dependency.

    Out-of-order issue with out-of-order completion

    During each of the first three cycles, two instructions are fetched into the decode stage.

    During each cycle, subject to the constraint of the buffer size, two instructions move from the
    decode stage to the instruction window.

    In this example, it is possible to issue instruction I6 ahead of I5 (recall that I5 depends on I4, but I6
    does not).

    Thus, one cycle is saved in both execute and write-back stages, and the end-to-end savings.

    However, this window is not an additional pipeline stage.

    An instruction being in the window simply implies that the processor has sufficient information
    about that instruction to decide when it can be issued.

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