EDN Design Ideas 2003

design
ideas
Edited by Bill Travis
Design makes handy audible circuit tracer

Jerry OKeefe, Cupertino, CA
output takes the form of audio tones. An
open circuit produces ticks at the rate of
approximately one per second, and a
short circuit results in a 2-kHz tone. An
audible sensing device is ideal for a circuit tracer, because your eyes can focus
on the circuit paths youre tracing and
not on a meter movement. If you want
to find the connections to a circuit point,
a useful technique is to attach a lead to
that point and just scan the other lead
over the other sections of the circuit.
When you hear a high-pitched tone, then
you know that you have a pc-board connection.
With practice, you can quickly determine the quality of the circuit path by
discerning the wide dynamic range of
ticks to tones. You can also detect the
presence of capacitors, which produce a
sweeping tone as they charge. The circuit
in Figure 1 is sensitive enough to produce a noticeable audio change if you
he circuit tracer in Figure 1 is a

handy tool for finding connectivity
paths on a pc board. Because the
sense voltage you use to measure the path
is lower than a transistors VBE voltage,
you can use the design in circuits containing semiconductor elements without
affecting the measurement. The tracers
Design makes handy audible

circuit tracer......................................................71
Design a visible optical link
for RS-232C communications ....................72
Hot-swap structure offers
improved redundancy ..................................72
Embedded processor
directly drives LCD..........................................76
Publish your Design Idea in EDN. See the
Whats Up section at www.edn.com.
make contact with a circuit with wet fingertips. R1 produces a 0.4-mA current to
bias the current mirror comprising Q1
and Q2. Q1, the resistance-sense transistor, is the heart of the circuit. The resistance between its emitter and VCC determines C2s charge current. Because C2
receives current from a constant-current
source, the waveform on the capacitor is
a linear ramp. When C2 charges and passes IC1s threshold, IC1 generates an output pulse. R2 determines the discharge
rate for C2. IC2, a 74C74, converts the
NE555 pulses to symmetrical square
waves to differentially drive the piezoelectric speaker. With normal, day-to-day
use, the 9V battery should last approximately a year.
Is this the best Design Idea in this

issue? Select at www.edn.com.
1N4148
TEST LEAD 1
D1
0.1 F
8
TEST LEAD 2
Q1
Q2
R2
100
Figure 1
VCC
7
6
RESISTANCE
SHORT
1
10
100
1 k
10 k
100 k
OPEN
1933
1888
1541
741
190
30
5.6
~1
D2
C1
0.1 F
TONE
FREQUENCY
(Hz)
S1
2N3906
R1
20k
C2
0.047
F
4
RESET
DISC
IC1
THRES NE555
2
3
TRIG
OUT
1 GND
B1
9V
10 F
CTRL
0.1 F
4
CLR
D
IC2
74C74
CLK
RADIO SHACK 273-073

Q 5
PIEZO SPEAKER
PRE
1
Use your ears to test continuity with this audible-tone circuit tracer.
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January 9, 2003 | edn 71
design
ideas
Design a visible optical link

for RS-232C communications
Shyam Tiwari, Sensors Technology Ltd, Gwalior, India
he design in Figure
12V
12V
1 is a visible
AC
D3
F
i
g
u
r
e
1
optical link
5V
1N4007
5V
for those who need to see
R5
D1
4.7k
the transmitted data. An
1N4007
12V 1
Rx
2
3
R2
R3
R4
isolation figure of more
LM7805
110V
22
22
22
5
2
than 5000V is a bonus.
MC1488
60 Hz
TIL99
Tests of the system used
D2
RS-232C
MRD5009
1N4007
12V COM PORT
the COM input of a
12V
RECEIVE
SUPERAC
R1
data-acquisition system,
2
D4
BRIGHT
Tx
1k
1N4007
3
LEDS
as well as a standard PCs
Q1
5
COM port. The MC1489
7404
MC1489
2N3055
converts the RS-232C
RS-232C
COM PORT
data to TTL signals. A
TRANSMIT
7404 gate then inverts
the signal. The output of This circuit provides a visible indication of RS-232C data transmission.
the 7404 drives Q1, a
2N3055 power transistor. The transistor away from the LEDs to obtain maximum receiver circuit. The MC1488 is a TTLdrives the set of three LEDs to form a isolation. The MRD5009 phototransistor to-RS-232C converter.
light source. When no data exists on the directly converts the light to a TTL outRS-232C port, the LEDs remain off. put. (A TIL99 phototransistor also works
When data transmission takes place, the well.) You should also isolate the power
LEDs glow at the rate of the data trans- supply to the MRD5009/TIL99 and the Is this the best Design Idea in this
mission. Keep the optical receiver 50 cm MC1488 from the power supply of the issue? Select at www.edn.com.
Hot-swap structure offers improved redundancy

Samuel Kerem, Corvus Corp, Columbia, MD
or redundancy purposes, a numVCC
LOAD
PS1
D1
ber of power supplies, using ORing
OUT
diodes, can work into the same load.
FB
R1A
During maintenance, when you can remove any power supply, the minimum
R1B
possible power perturbation at the load
PS2
D2
is desirable. To compensate for the voltOUT
age drop across the ORing diodes, you
FB
R2A
must connect the power-supply
feedback lines after the diodes, at
R2B
Figure 1
the load. Thus, the feedback connection is common for all participating
power supplies (Figure 1). Because of A standard redundant configuration of powernatural variations in each power supply, supply modules uses ORing diodes at the outonly the one with the highest VOUT is ac- puts.
tive. The others, sensing the higher output voltage, try to reduce their own ulation. If you remove the active modoutputs, effectively turning off their reg- ule from the setup similar to Figure 1, it
72 edn | January 9, 2003
causes VOUT to dip (Figure 2). Figure 2a

applies to a linear module that comprises two regulators that have independent
3.339 and 3.298V output voltages. Both
have loads of approximately 10 in parallel with 100 F. Figure 2b applies to a
boost configuration that comprises two
regulators with 5.08 and 4.99V outputs,
each loaded with approximately 2.5 in
parallel with 100 F. The sags and glitches in the voltages arise from the inevitable
delay for another power supply to step in
and to start the regulation. Costly powersupply bricks deal with this problem by
using current-sharing techniques. The
techniques provide roughly equal output-current distribution among all power modules, thus keeping all modules acwww.edn.com
design
ideas
(a)
(b)
Figure 2
When you remove one supply from the redundant configuration, you incur sags (a) and glitches (b) in the output voltage.
tive. The configuration in Figure 3 adds

little cost to a power system. The
Figure 3
improvements in performance
MODULE 1
are evident in Figures 4a and 4b, repreVCC
PS1
D1.1
senting the two types of redundant powHOT
VOUT1
OUT
SWAP
LOAD
er-supply modules.
FB
R1
R
1A
An instrumentation amplifier, IC1,
SENSE
measures and produces a voltage,
VC
VC, proportional to the current going
IN
R11 D1.2
RG
into the regulator. VC in turn controls
R13
R1B
IC1 OUT
RG
R12
VOUT, pushing the regulator into active
C1
IN+
mode. For most adjustable controllers,
VOUTVREF(1RA/RB), where RA is R1A,
VCC
and RB is R1B for module 1. If no current
VOUT2
R2
SENSE
flows through RSENSE, IC1s output is close
MODULE 2
D2.1
to ground, paralleling R1B with the resistances of D1.2, R11, and R12, thereby
making RB smaller and VOUT1 consequently higher. The increase needs only The addition of an instrumentation amplifier and a few passive components provides sag- and
to compensate the VOUT variation be- glitch-free redundant performance.
Figure 4
(a)
(b)
Linear (a) and boost (b) regulators use the scheme in Figure 3 to eliminate sags and glitches in the output voltage.
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design
ideas
tween same-configuration power supplies. This variation is only a few percentage points. If the current into the
load rises, VC also rises, reducing the current through D1.2 and consequently reducing VOUT1. When IC1s output rises
and differs from VFB by less than the di-
rect voltage drop across D1.2, no current

flows through D1.2. Thus, VOUT1, for any
higher current, stays at the value the
above equation defines. With the proper
selection of R3 (the instrumentation amplifiers gain-setting resistor), R2 and R1
from other modules provide the required
current into the load from all power supplies, guaranteeing that they stay in active
condition.

Embedded processor directly drives LCD

Daniel Malik, Motorola, Czech Republic
riving a bare LCD does not necessarily require specialized
Figure 1
interface circuitry or peripherals. This Design Idea describes an
alternative drive scheme, which you can
easily implement using the general-purpose outputs of a microcontroller. Many
embedded-system applications need to
interact with a user by displaying simple
numeric or alphanumeric characters.
Seven- or 14-segment LED displays are
readily available at low cost and in many
sizes. However, their relatively high power requirements and limited readability
in direct sunlight restrict their use in battery-powered, portable devices. LCD
modules driven by HD44780-compatible
controllers offer simple interface characteristics, low power consumption, and
good readability. However, their cost is
relatively high, and their large dimensions sometimes preclude their use in
small enclosures. Bare LCDs overcome
these disadvantages. However, their drive
requirements are usually nontrivial. Figure 1 shows the usual waveforms you use
to drive an LCD with four backplanes.
The algorithm uses four discrete voltage
levels for all LCD signals. Synthesis of
such signals without dedicated peripherals or an external controller is difficult
and requires many components. Fortunately for users of general-purpose microcontrollers without specialized onchip peripherals, an alternative exists.
Figure 2 shows the alternative waveforms.
The algorithm uses only three voltage
levels on the backplane pins and only two
voltage levels on the front-plane pins of
the LCD. Such waveforms are easy to syn- In the standard waveforms for driving LCDs, the algorithm uses four discrete voltage levels for all
thesize using the general-purpose pins of LCD signals.
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design
ideas
a microcontroller. Figure 3 shows a typical application of the alternative algorithm, using a general-purpose microcontroller. You implement the BPx
(backplane) connections using generalpurpose, tristatable outputs of the microcontroller. The FPx (frontplane)
connections require only ordinary, general-purpose outputs. You obtain the
VDD/2 voltage on the BPx pins by tristating the microcontrollers pins. (You can
usually obtain this result by configuring
VDD VDD VDD VDD

the pins as inputs.) Modern
MICROCONTROLLER
microcontrollers
operate
from a wide range of powersupply voltages. Altering the
BPO..3
microcontrollers power-supply voltage is an effective way
FPxx
of adjusting the LCDs contrast. Figure 4 shows examples of LCDs drivFigure 3
en by general-purpose microcontrollers from You can use a general-purpose microcontroller to drive any
Motorola (www.motorola. size LCD.
com). Figure 4a shows a display with

two11-segment organization; for Figure 4b, the organization is four16 segments. Figure 5 shows the modification
of the waveforms for the smaller display
of Figure 4a, using only two backplanes.
Figure 4
(a)
(b)
11A general-purpose MC68HC908GP32 drives a two

16-segment LCD (b).
segment LCD (a) and a four
Figure 5
Figure 2
Alternative LCD-drive waveforms use only three voltage levels on the backplane pins.
This modification of an LCD has only two backplanes.
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design
ideas
Fleapower flasher draws less than 50 A

Gary Butterfield, IEC Electronics Technology Center, Newark, NY
ome applications require a circuit to indicate that a batFigure 1
terys voltage has fallen below
R3
a certain value. However, if you dont fre1M
quently check the indicator, the low-batD1
tery indicator itself can easily discharge
470
C1
the battery. The circuit in Figure 1 indi940k
1 F
R2
cates when the battery voltage has
30M
dropped below a preset value. The circuit
CW
R1
6 _
250k
IC1B
draws less than 50 A, regardless of
3 +
7
LMC6762A
IC1A
whether the indicator flashes. IC1A oper1
5
+
LMC6762A
2 _
ates as a simple comparator. IC2, a lowcurrent voltage reference, supplies the
IC2
reference voltage to Pin 2 of comparator
LM28.5-1.2
.
Resistor
R
provides
an
adjustable
IC1A
R4
1
10M
trip point. A potentiometer setting of
510k
R6
124 k yields a trip point of approximately 10.3V. When the power-supply
10M
R5
voltage is above the trip point, IC1As Pin
10M
1 is high, forward-biasing diode D1 and
holding the flasher in the off state. R2
provides approximately 300 mV of hysteresis for the detector. IC1B provides the This fleapower flasher indicates a low-battery condition with a flashing LED.
flashing of the LED. C1 charges through
R3, and, when its voltage exceeds the volt- sis of approximately one-third of the
Another trade-off is that the LED afage at IC1Bs Pin 5, Pin 7 pulls low, dis- supply voltage.
fects the minimum operating voltage beThe circuits current consumption is cause of the forward voltage drop of the
charging the capacitor through the LED.
Resistors R4 and R5 provide a voltage ref- 45 A at 10V, climbing to 48 A at 12V. diode. In the prototype, a red LED works
erence, and resistor R6 provides hystere- The state of the flasher does not affect down to a lower operating voltage of
current consumption, because the LED 4.3V. A yellow LED in the same circuit
receives its power via the capacitor. You operates down to 6.4V. Additionally, the
have to make a number of trade-offs to high resistances on the board, most noFleapower flasher draws
achieve this low current consumption:
tably the resistors attached to IC1Bs Pin
less than 50 A ..............................................75
5, require careful attention to board
For
example,
discharging
the
capacitor
PC-based configurable filter
cleanliness. Small leakage currents can
through
the
LED
allows
the
circuit
to
uses no digital potentiometers ..................76
reuse the capacitors charge, instead of significantly affect circuit operation and
Frequency source feeds entire lab ............80
dumping it to ground. It also eliminates current drain. You can reduce the values
the current spikes that occur when driv- of these resistances to improve manufacCircuit sequences supplies
ing the LED from the supply rail. How- turability at the expense of higher current
for FPGAs ........................................................82
ever, the charge on the capacitor limits consumption.
the resulting LED brightness, so you
should use high-efficiency LEDs when Is this the best Design Idea in this
possible.
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January 23, 2003 | edn 75
design
ideas
PC-based configurable filter

uses no digital potentiometers
Saurav Gupta and Tejinder Singh, New Delhi, India
odern instrumentation requires digital control signals. These
signals come from a central microprocessor or, in modern context, the
popular parallel or serial PC ports. In recent times, digital potentiometers have
eliminated the hassles from this interface
for the analog section. Designers can replace the resistors of the analog design
with digital potentiometers, thus providing the necessary digital control. However, digital potentiometers suffer more severely from temperature-sensitive
performance drifts than their manual
counterparts, and they exhibit finite
wiper-resistance effects. The design in
Figure 1 represents a multifunction, analog biquadrature design for automated
mixed instrumentation. You can configure the design for both Q factor and center frequency via a PCs parallel
Figure 2
port. The circuit requires no DACs
or digital potentiometers. The circuit,
This user-friendly screen helps you configure the desired filter.

5V
0.1 F
Figure 1
0.01 F
5V
0.1 F
0.01 F
VCC
0.01 F
R5
4.7k
4.7k
2.2k

14
16
18
PARALLEL
PORT
1
2
D0
D1
D2
D3
D4
7
20
8
9
22
10
LE
CE
IN0
OUT0
IN1
OUT1
+
R1
1k
VHP
IN4
OUT4
R4
4.7k
IN5
D6 IN6
D7
IN7
OUT5
VLP
OUT7
VCC
R6
220
R7
R2
13
10k
100k
IN4 IN3 IN2 IN1

S1
D1
IC3
S2
D2
DG308A
S3
D3
VBP
D4 V+ V GND S4
V+ V GND
D2
5V
IC5
1
/ 4 OPA4242
S1
D1
22k
24
12

IC5
D4 V+ V+ GND S4
2.2k
10k
11
S3
1
/ 4 OPA4242
OUT6
S2
100k
0.01 F
IC1 OUT2
74573
IN3
OUT3
GND
IC2
DG308A
D3
IC5
1
/ 4 OPA4242
23
25
D2
10k
VIN
IN2
D5
IN4 IN3 IN2 IN1

D1
S1
220
R3
4.7k
47k
D3
100k
D4
IC4
DG308A
S2
S3
S4
IN1 IN2 IN3 IN4
You can use a PC-configurable filter design to select both Q and center frequency.
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design
ideas
based on a two-integrator configuration, provides simultaneous

highpass, lowpass, and bandpass
outputs.
By running simple code on the
PC, you can choose from more
than 150 programmable combinations of Q factor and center frequency (Listing 1). You can thus
build a filter of desired parameters
on the fly. The design uses quad
analog switches DG308 from Maxim (www.maxim-ic.com) together
with octal latches for programmability. A micropower precision op
amp, OPA4242, from Burr-Brown
(www.ti.com) makes up the ana-
TABLE 1DATA BITS FOR Q SELECTION

D9
(100k)
1
0
1
0
1
0
1
0
1
0
0
1
0
1
1
D8
(47k)
1
1
0
0
1
1
0
0
1
1
1
0
0
1
0
D7
(22k)
1
1
1
1
0
0
0
0
1
1
0
1
1
0
0
D6
(j10k)
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
Q
2.24
2.35
2.5
2.65
2.9
3.12
3.4
3.72
4.7
5.36
6
6.38
7.72
11.01
33.72
log-filter section. The software

provides the data bits on ports
pin 2 through 9, stored in the
latch that controls the analog
switches and, hence, selects the
appropriate resistance combination to select the desired Q and f0
values. The center frequency and
Q values are: f0[1/C1C2RP6RP7]1/2
and Q(1RP2/R1)/3, where RP2,
RP6, and RP7 are PC-programmable resistances.
Data nibbles from port pins D2
through D5 provide gangedswitch settings for RP6 and RP7,
ensuring that they are always
equal. Data nibbles correspon-
LISTING 1C PROGRAM FOR PC-CONFIGURABLE FILTER
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design
ideas
ding to pins D6 through D9 control

the value of RP2; hence, you use them
for Q-value selection. For the given
resistance values, Table 1 shows the
data bits for different values of Q
(ranging from 2.24 to 33.72). Table 2
shows the data bits for various center frequencies (159 Hz to 38.70
kHz). Figure 2 shows the software
front-end screen to make the selection. The design uses an 8.11-kHz filter with Q-factor 2.9 for demonstration and hardware validation.
Listing 1 gives the necessary backend C code. The switches employed have
a finite on-resistance, RDS, of approxi-
TABLE 2DATA BITS FOR CENTERFREQUENCY SELECTION

D5
1
0
1
0
0
1
0
0
0
1
D4
0
1
1
0
1
1
0
1
0
1
D3
0
0
0
1
1
1
0
0
1
1
D2
0
0
0
0
0
0
1
1
1
1
f0 (kHz)
0.159
1.519
1.75
6.37
7.96
8.11
30.68
32.2
37
38.7
mately 150, which the design takes into

account. For higher precision, you can
use better switches having on-resistances of approximately 35.

Note that more switches provide a
wider range from which to select.
You can choose the resistances to
suit the applications bandwidth
range. You can download the filter
software from the Web version of
this Design Idea at www.edn.com.

Frequency source feeds entire lab

Mitchell Lee, Linear Technology Corp, Milpitas, CA
lumbing a laboratory with a double-terminated 50 or 75 loads.
hp.com) HP10811A component oscillastandard frequency makes a lot of
As Figure 1 shows, the outputs use tor for the Colpitts oscillator. Connect the
sense if the lab uses multiple fre- 75 impedance levels to take advantage HP10811As output through a 510 requency counters, spectrum analyzers, and of inexpensive F-type connector hard- sistor and a 10-nF coupling capacitor, diother frequency-dependent test equip- ware and low-cost video coaxial cable. IC1 rectly to the emitter of Q2. If you need
ment. Rather than spending time keeping also provides good isolation between its more than four outputs, you can dupliall of the instruments oscillators in cali- outputs, so that changes in loading on cate the IC1 stage as many times as necbration or buying expensive, high-preci- one output do not affect the other out- essary.
sion oscillators, you can use the circuit in puts. The circuit delivers more than 6
Figure 1 to distribute a single calibrated dBm to each termination. If high accufrequency source to the external-refer- racy and low drift are critical needs, you Is this the best Design Idea in this
ence input of each instrument. The cir- can substitute Hewlett-Packards (www. issue? Select at www.edn.com.
cuit represents a simple,
10-MHz source and distribution amplifier. The
5V
output comes not from
10 F
the emitter or collector
of the Colpitts-oscillator
47 nF
IC1
47 nF
LT6551
Q1
transistor, Q1, but rather
10k
330
2N3904
10 MHz 7 TO 45 pF
from the current flowing
Q2
2N3906
10k
in the 10-MHz crystal.
RG-59/U
100 pF
10k
The common-base stage,
75
10 nF
Q2, converts this current
20k
100 pF
47 nF
3.3k
330
RG-59/U
into a voltage and estab75
10 nF
CLOCK
lishes the correct dc
OUTPUTS
RG-59/U
level for the output am75
10 nF
plifier, IC1. This IC conRG-59/U
tains four gain75
Figure 1
10 nF
of-two buffers
with 110-MHz, 3-dB
bandwidth and can drive A laboratorywide distribution system is an alternative to multiple frequency sources.
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design
ideas
Circuit sequences supplies for FPGAs

David Daniels, Texas Instruments, Dallas, TX
ystem designers must consider the
timing and voltage differences between core and I/O power supplies (in
other words, power-supply sequencing)
during power-up and power-down. The
possibility of a latch-up failure or excessive current draw exists when power-supply sequencing does not occur properly.
The trigger for latch-up may occur if power supplies apply different potentials to the
ENABLE
J2
1
2
Figure 1
J1
1
2
OUT 8
7
IC1
IN
OUT
3 TPS2034DOUT 6
IN
4
OC 5
EN
GND
10 F
10k
3.3V
INPUT
SUPPLY
core and the I/O interfaces. FPGAs and

other components with different sequencing requirements further complicate the power-system design. To eliminate
the sequencing problem, you should minJ3
3.3V
I/O SUPPLY
10 F
1
2
10 F
10 F
1 AGND
2
VSENSE
3 COMP
4
R2
9.78k
0.047 F
10k 470 pF
12 pF
R3
10k
28
RT
ENA 27
TRACKIN 26
VBIAS 25
PWR80
5
VIN 24
BOOT
6 PH
VIN 23
7
IC2
VIN 22
PH
TPS546B0PWP
8
21
PH
VIN
9
VIN 20
PH
10
PGND 19
PH
11
PGND 18
PH
12
PGND 17
PH
13
PGND 16
PH
15
14
PH
PWRPAD PGND
1 F
71.5k
R4
9.76k
10 F
301
R1
10k
0.68 H
1
2
470 pF
22 F
22 F
22 F
J4
1.8V
CORE
SUPPLY
This power-supply-sequencing circuit eliminates latch-up problems and reduces FPGA start-up transient currents.
Figure 2
When the I/O-supply voltage decays, the core voltage gracefully follows
suit.
Figure 3
As the I/O-supply voltage rises smoothly toward 3.3V, the core voltage
clamps cleanly at 1.8V.
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design
ideas
imize the voltage difference between the

core and the I/O supplies during powerup and -down. The power supply in Figure 1 regulates the 3.3V input voltage to
the 1.8V core voltage and tracks the 3.3V
I/O during power-up and -down to minimize the voltage differences between the
supply rails.
The circuit in Figure 1 comprises IC1
and IC2, a TPS2034 power switch and a
TPS54680 step-down switching regulator,
respectively. Component IC1 is a high-side
power switch that generates a slow ramp
that IC2 tracks during start-up. The ramp
time of 6 msec minimizes the inrush currents to the bulk capacitors on the powerswitch and supply outputs. The slow ramp
minimizes the transient-current draw of
the FPGA. The power switch ensures that
the I/O voltage is not applied to the load
before IC2 has enough bias voltage to operate and generate the core voltage. Assuming that the input supply voltage is at
3.3V on J1, floating the J2 connector en-
ables component IC1. The I/O supply voltage, J3, slowly rises until it reaches 3.3V. As
the I/O voltage rises, the core voltage supply, J4, rises accordingly until the voltage
reaches 1.8V (Figure 2). The TPS54680
device incorporates an analog multiplexer on the TRACKIN pin to implement the
tracking function.
During power-up and -down, when the
voltage on the TRACKIN pin is lower than
the internal reference of 0.891V, the voltage on the TRACKIN pin connects to the
noninverting node of the error amplifier.
When the TRACKIN pin is below 0.891V,
the pin effectively functions as the switching regulators reference. The resistor divider of R3 and R4 on the TRACKIN pin
must equal the resistor divider of R1 and
R2 in the feedback compensation to track
with minimal voltage difference during
power-up and -down. The TPS2034 has
an on-resistance of 37 m and can supply
as much as 2A output current. The
TPS54680 is a synchronous buck regula-
tor that contains two 30-m MOSFETs.

Because the TPS54680 can source and sink
as much as 6A load current at efficiencies
greater than 90%, the output can track another power-supply rail during powerdown. When the IC1 device becomes disabled by shorting J2 to ground, the I/O
supply voltage decays, and the core supply voltage follows once the I/O voltage
falls below the core voltage (Figure 3).
Typically, Schottky diodes connect to the
output of a dual power supply to clamp
the voltage difference between the core
and the I/O supplies during power-down,
but most applications do not require the
diodes with the power-supply circuit in
Figure 1. Using this power-supply design
reduces component count and increases
reliability by eliminating the potential for
latch-up and reducing FPGA start-up
transient currents.
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ideas
Oscillating output improves system security

Jorge Marcos and Ana Gmez, University of Vigo, Vigo, Spain
any electronic-control systems have digital outputs
Figure 1
that use transistors. One
STATIC
VARIABLE
method of improving the security in
these outputs is to use an oscillating sigDYNAMIC
VARIABLE
nal to represent a logic-high state instead
LEVEL 1
LEVEL 0
LEVEL 0
of a fixed voltage level (Figure 1). This
type of signal, a dynamic variable, can
drive the circuit shown in Figure 2. This
circuit connects to the output transistor
of the electronic-control system. The dy- You can improve the reliability of an electronic-control output by using an oscillating, instead of
namic-variable signal connects to the steady-state, signal to represent a logic-high state.
output transistor, whose collector connects to a pulse transformer. If the system
24V
cannot produce pulses because of a fault,
the relay deactivates. If a fault exists in the
1N5347B
drive circuitry, the output system stays
ZENER
3
VZ10V
off. This solution guarantees the securi1
4
ty function when one fault occurs. HowRELAY
1N4002
1N4002
5
16
ever, it does not guarantee the detection
2
1
1 F
of all faults. However, you can use a
6
9
DPDT relay and connect one of
NO1
TRANSFORMER
Figure 2
13
the contacts to one of the elecSKPT25B3
COM1
11
NC1
tronic-control inputs; thus, you can conFUSE
8
NO2
firm the relays activation or deactivation
4
COM2
in the control program.
6
NC2
The circuit in Figure 2 performs effiD
ciently if the system can generate a freGATE_MOS
MOS
quency greater than 1 kHz to excite the
G
IRFD110
Oscillating output improves

system security................................................85
Polarity protector outperforms
Schottky diodes ..............................................86
Circuit offers improved
active rectification ..........................................86
Build an adjustable high-frequency
notch filter ........................................................90
Bootstrapping allows single-rail
op amp to provide 0V output ....................92
Filter allows comparison
of noisy signals ..............................................94
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A dynamic-variable signal drives the output relay in this circuit.
pulse transformer. Many electronic systems that use an output transistor can
generate a dynamic variable. Many systems, such as PLCs (programmable-logic controllers), have long cycle times and,
thus, cannot generate signals of adequate
frequencies. In these cases, you can obtain an appropriate signal using the lowfrequency dynamic variable from the
PLC. To accomplish that task, you must
use an external oscillator and a pulse detector implemented with a monostable
multivibrator. The oscillator produces a
square-wave signal of a frequency that

suits commercial pulse transformers.
This signal drives the MOSFET when the
pulse detector receives pulses from the
PLC. Because the pulse detector can fail,
you must duplicate the external circuit
for redundancy. In this way, the final result is the same as that of Figure 2, except that the safe output comprises two
relays.
February 6, 2003 | edn 85
design
ideas
Polarity protector outperforms Schottky diodes

Mike Hovenga, BAE Systems, Austin, TX
he polarity-protection circuit in
Figure 1 is a high-performance alternative to the usual series diode
(often Schottky). The circuit incurs a

much lower voltage drop than even the
best Schottky diode. The circuit uses
Q2
IRF7425
Q1
IRF7822
Figure 1
+
D1
IN4002
R2
2.2M
7
100k
INPUT
R3
2.2M
R1
1.2k
IC1
PVI5033
D2
14V FOR
15.5V OVP
OUTPUT TO
PROTECTED
CIRCUITRY
10k
MOSFET devices because of their low

on-resistance. For the transistors in this
design, the combined on-resistance is
0.013. With a 10A load, the voltage
drop is 0.13V at 25C. Compare this figure with forward-voltage drops of several hundred millivolts for Schottky diodes
under the same conditions. You must use
p- and n-channel transistors in series because of their intrinsic diodes. A photovoltaic isolator provides the appropriate
gate drive to the MOSFETs. The performance is even better at lower currents.
You can replace the two discrete transistors by a single-package, complementary-MOSFET pair, such as an IRF7389,
which has a combined on-resistance of
0.108. Resistors R2 and R3 are necessary
to turn off the transistors when IC1 turns
off. R1 provides a nominal 12V input.
This polarity-protection circuit incurs lower forward-voltage drop than the best Schottky diodes.

Circuit offers improved active rectification

Reza Moghimi, Analog Devices Inc, San Jose, CA
ectifiers convert ac
signals to dc. You can
VCC
combine a diode
Figure 1
VOUT2
VOUT1
and a load resistor to
3
V
+
create a half-wave rectifier,
1
VIN
AD8591
provided that the amplitude
4 _ SD
1N4154
V
of the ac source is much larger than the forward drop of
VEE
the diode (typically 0.6V).
Unfortunately, you cant use
VCC
this method to rectify signals
that are smaller than a diode
drop. For these applications,
active rectifiers using amplifiers are available. The diode This circuit is a typical half-wave-rectifier configuration.
is inside the feedback loop of
an amplifier (Figure 1). For VIN0V, the conduct, the amplifier is in an open-loop
diode provides negative feedback, and the configuration, and VOUT2~0V. Figure 2
output, VOUT2, follows the input (VOUT2 shows the response of the circuit in FigVIN). For VIN0V, the diode does not ure 1. The output is shown in green; the
86 edn | February 6, 2003
input is shown in red.

If VIN0V, the amplifier
behaves as a comparator.
Its negative input is at a
higher potential than its
positive input, so its output, VOUT1, saturates to VEE.
When the input again be5k
comes positive, the amplifier has to recover from saturation and respond as
quickly as its slew rate and
saturation recovery time
allow. This response takes
some time, and the input
may have changed by the
time the amplifier is ready to respond to
the positive input. The signals at VOUT1
(red) and VOUT2 (green) clarify this point
(Figure 3). VOUT2 is the same waveform as
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design
ideas
in Figure 2. Note the change in scale factor. VOUT1 is a diode drop higher for positive inputs and saturates to VEE for negative inputs. The time delay in the
response may result in a significant error in the output.
For example, an amplifier that has a
slew rate of 2.5V/sec and saturates to
2.5V takes at least 1 sec to get
ready to respond to positive inFigure 2
puts. During this time, the fast input has changed, so rectification starts at
the wrong part of the input. One way to
minimize this error is to use a high-slewrate amplifier, but this solution comes at
the expense of high power consumption.
Another option is to use an invertingamplifier configuration and two diodes,
followed by a unity-gain inverting amplifier to obtain the noninverting rectification. This method appears in many
textbooks. The circuit in Figure 4 represents a one-stage, noninverting rectifier
that improves the accuracy of the
Figure 3
rectification and reduces the power consumption. In this circuit, an
AD8561 amplifier acts as a comparator.
The AD8591 performs the rectification.
When VIN0V, the output of the
AD8561 is high, and the AD8591 acts as
a follower. When VIN0V, the output of
the AD8561 is low, and the AD8591 shuts
down. This shutdown puts the output of
the AD8591 into a high-impedance state,
so it remains at approximately 0V, rather
than saturating to VEE as it did in the previous circuit. When VIN goes positive, the
amplifier comes out of shutdown
Figure 4
and again follows the input. This
turn-on time (the time it takes to come
out of shutdown) is much shorter than
the saturation recovery time and slewrate limiting that occurs in the previous
circuit. Figure 5 shows the signals at the
input (red) and output (green) of the improved rectifier circuit.

Figure 5
These signals appear at the input (red) and the output (green) of the circuit in Figure 1.
These signals are the waveforms at VOUT2 (green) and VOUT1 (red) in the circuit in
Figure 1.
VCC
3+
V
AD8591
4_
SD V
VIN
VCC
V
3 _
5k
VEE
AD8561
2
VOUT1
1
4 V
7
5
6
VEE
This circuit greatly improves on the performance of the circuit in Figure 1.
These signals appear at the input (red) and output (green) of the circuit in Figure 4.
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design
ideas
Build an adjustable high-frequency notch filter

John Ambrose, Mixed Signal Integration Corp, San Jose, CA
lthough you can obtain universal,
resistor-programmable switched-capacitor filters that are configurable
as notch filters, most cannot operate at
bandwidths higher than 100 kHz. Further, the typically 16- to 20-pin packages
do not include a continuous-time, antialiasing filter to prevent spurious signals
from appearing at the output. By using
an eight-pin, dual operational amplifier
and an eight-pin, switched-capacitor
bandpass filter, you can construct a notch

filter (Figure 1). IC2, a TLC082 is a dual
BiCMOS op amp, replacing the older
JFET-input stage with lower noise CMOS
but retaining the bipolar output for high
drive capability. The gain-bandwidth
product of the TLC082 is 10 MHz, allowing you to use it for filtering at frequencies as high as 1 MHz. The minimum (VCCVEE) span with the TLC082
is 5V, unlike the older TL082, which re-
quired 6V. This supply span matches well

with IC1, an MSHFS6, with its 5V nominal operating voltage. Using half of the
TLC082, you can construct a third-order,
elliptic lowpass filter.
You set the passband ripple at approximately 5 dB to increase the out-of-band
rejection.You set the continuous-time filter for 800 kHz, providing greater than 40
dB of rejection at 12.5 MHz. Figure 2
shows the frequency response of the
5V
VDD
47k
100 nF
Figure 1
IC2B
TLC082
_ 6
4
FSEL
OUT
10k
8
IN
1
2.4k
GND
IC1
TYPE MSHFS6S VSS
CLK
VDD
SUMMING STAGE
+
4.7k
4.7k
100k
47 pF
47k
470 nF
1k
SIGNAL
INPUT
20
10 pF
100 nF
2.4k
10k
IC2A
TLC082
NOTCH
OUTPUT
+ 5
10k
8
10 pF
10 pF
4.7k
THIRD-ORDER, 800-kHz ELLIPTIC
LOWPASS FILTER
V2
6.25 MHz
5V
TUNABLE SIXTH-OCTAVE BANDPASS FILTER
An op amp and a switched-capacitor filter combine to form a highly selective notch filter.
edn021226di30991
Heather
Figure 2
This plot is the frequency response of the thirdorder lowpass-filter stage.
Figure 3
This Bode plot represents the passband of the

MSHFS6 filter.
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design
ideas
third-order lowpass filter using the

TLC082. The MSHFS6 switchedcapacitor selectable lowpass/bandpass filter with its 12.5-to-1 clockto-corner ratio allows for distortion
measurements to 6.25 times the
notch center frequency before
aliased signals cause measurement
error. With the TLC082 lowpass filter set at 800 kHz, you can measure
distortion products as high as the
third harmonic. If the notch center
frequency is always set lower than
260 kHz (MSFS6 clock at 3.3 MHz),
then you can set the continuoustime lowpass filter corner to
Figure 4
a lower frequency by adjust-
ing the resistor and capacitor

values. By summing the output
of the bandpass filter with the input, cancellation of the input signal occurs at 180 phase shift in
the passband. Figure 3 shows the
Bode plot of the passband of the
MSHFS6 sixth-octave filter setting. The output of the other half
of the TLC082 provides the
notch-filter output. Figure 4
shows the depth of the notch filter at 50 dB.
The circuit in Figure 1 delivers a 50-dB notch.
Is this the best Design Idea in

this issue? Select at www.edn.
com.
Bootstrapping allows single-rail op amp

to provide 0V output
Jim Williams, Linear Technology Corp, Milpitas, CA
any single-supply-powered applications require amplifier-output swings within 1 mVor even
submillivoltsof ground. Amplifieroutput-saturation limitations normally
preclude such operation. Figure 1s power-supply bootstrapping scheme achieves
the desired characteristics with minimal
parts count. IC1, a chopper-stabilized am-
plifier, features a clock output. This output switches Q1, providing drive to the
diode-capacitor charge pump. The
charge pumps output feeds IC1s V terminal, pulling it below 0V, thus permitting an output swing to and below
ground. In Figure 2, the amplifiers V
pin (Trace B) initially rises at supply
turn-on but heads negative when ampli-
fier clocking commences at approximately midscreen. The circuit provides a

simple way to obtain output swing to 0V,
allowing a true live-at-zero output.

5V/DIV
A
Figure 1
5V
5V
V+
1k
IC1
LTC1150
_
CLOCK
OUT
V
0.2V/DIV
B
10 F
+
Q1
2N3904
BAT85
39k
+
10 F
100k
5 mSEC/DIV
This configuration uses bootstrapping to allow a single-rail op amp to operate at 0V output.
This start-up photo shows that the amplifiers

V pin (Trace B, midscreen) goes negative
when the bootstrapping takes hold.
Figure 2
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design
ideas
Filter allows comparison of noisy signals

Mario Milberg, CNEA, Buenos Aires, Argentina
15V
hen you need to compare the dc

R3
level of a noisy signal with
7.5k
R2
Figure 1
220k
a reference for further processing, the output of the comparator
15V
R1
changes in a chaotic way when the dc lev3.3k
3
5 +
VSIG
el approaches that of the reference. You
2
LM339
have a choice of two classic solutions to
4 _
12
this problem: One is to add hysteresis to
C1
0.68 F
the comparator, but, if the noise level is
15V
R6
R4
high, the hysteresis must be correspond470k
270k
ingly high. In this situation, you face a
R5
wide dead-band zone around the com100k
parison trip point. The second solution
is to add lowpass filtering to the noisy signal. This approach increases the response By presenting the noise signal to both inputs of
time, slowing down the system. This De- the comparator, this circuit can compare the dc
sign Idea proposes a third solution that levels of the signal and the reference.
avoids the cited drawbacks. In the circuit
in Figure 1, the noise adds to the reference between the two dc levels:
ence through a highpass filter, so the
VVDCSIGVNOISEVHYS, VVDCREF
comparators inputs see only the differ- VNOISE, and VVVDCSIGVCREF
VHYS, where V is the voltage on the comparators positive input, V is the voltage
on the negative input, VNOISE is the noise
riding on the signal, and VHYS is the hysteresis accruing from the positive feedback to the positive input.
C1, R4, R5, and R6 form the highpass filter, whose cutoff frequency is fC
1/[2C1(R4R5)||R6]. The cutoff frequency should be lower than the lowest
frequency of the noise band. R1 and R2 establish the still-needed small amount of
hysteresis. R3 is a pullup resistor for the
open-collector output of the comparator.
The comparator circuit worked successfully in a system that processes the fluctuating current generated by an ionization chamber in a neutron-flux measurement system.
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design
ideas
Build a precision deadband circuit

V Manoharan, Kochi, India
eadband circuits find applications
in servo-control systems. A precision
current source and a half-wave inverting rectifier form a positive deadband
circuit (Figure 1). The REF01, IC1, is a precision 10V voltage reference. It forms a
precision current source with the addition
of a unity-gain buffer (IC2A) and resistor
R1. IC2A forces the ground pin (Pin 4) of
IC1 to assume the potential at IC2As noninverting input. IC1 forces its highly accurate reference voltage (10V) across R1, so
the current I1 through R1 is 10V/R1. Because the inverting input of IC2B connects
Build a precision deadband circuit ............79

DDS and converter form
signal generator ............................................80
48-input16-output crosspoint IC eliminates the need for multiplexer amps ........84
Transmission line tests 1-kW device
using only 100W ............................................86
VOUT
to the output of the current source, the

feedback diode, D1, becomes forward-bi8
ased with current I1. The forward-biased
diode keeps the output of IC2B at approx4
imately 0.6V. Because the cathode end
of D2 stays at virtual ground through R3,
VIN
D2 remains reverse-biased. Hence,VOUT re_8
_4
4
8
mains at virtual ground (0V).Any positive
voltage applied to VIN further forward_4
and reverse-biases D1 and D2, reFigure 2
spectively, and the output remains
_8
at 0V (deadband zone) for VIN0V.
Negative inputs tend to forward-bias
D2 and reverse-bias D1. This bias situation With R120 k, the circuit in Figure 1 is
occurs only when the current through R2 dead for input voltages higher than 5V.
(because of the negative VIN) equals or exceeds 10V/R1. So, the output is 0V (dead- straightforward circuit by prebiasing the
band) until VIN reaches a value equal to inverting half-wave rectifier through a
10R2/R1. If you choose R120 k, VOUT precision resistor connected to a voltage
remains at 0V for VIN(5V); for reference without using the unity-gain
VIN(5V), VOUT(VIN5V). Figure buffer, IC2A. However, this alternative
2 shows the transfer function for this sce- would increase the noise gain, thereby innario. C1, C2, and C3 are decoupling ca- creasing the offset and noise at the output.
pacitors for IC1 and IC2. R4 reduces the
offset voltage of IC2B in the nondeadband Is this the best Design Idea in this
region. You could realize an alternative issue? Select at www.edn.com.
R3
REF01
15V
C1
0.1 F
VOUT
VIN
0.1 F
10k
10V
IC1
GND
D1
1N4148
I1=10V/R1
_15V
C2
0.1 F
R1
OP271
1
C4
6.8 pF
_ 2
R2
VIN
10k
IC2A
3
+
6 _
I1
Figure 1
IC2B
+
8
OP271
7
D2
1N4148
VOUT
C3
0.1 F
R4
5k
15V
This circuit exhibits a deadband for signals more positive than an arbitrary voltage, which R1 determines.
www.ednmag.com
February 20, 2003 | edn 79
design
ideas
DDS and converter form signal generator

Colm Slattery, Analog Devices, Limerick, Ireland
any applications require lowfrequency signal generators that
can deliver high-performance,
high-resolution signals. This Design Idea
presents a circuit that generates frequencies of 0 to 1 MHz. Sinusoidal, triangular,
and square-wave outputs are available.
You can achieve frequency resolution of
better than 0.1 Hz and phase resolution
of better than 0.1; thus, you can program
exact coherent frequencies. This feature
is useful in digital modulation and frequency-tuning applications. The circuit
uses the ADC831 and AD9834 to generate the required frequencies (Figure 1).
You can program the microcontroller
from either a PC or a Unix-based workstation. You then program the AD9834
using a three-wire serial interface via the

microcontroller. The interface word is 16
bits long.
You can program the AD9834 to provide sinusoidal, triangular, and squarewave outputs using the DDS (direct-digital-synthesis) architecture. The chip
operates as an NCO (numerically controlled oscillator) using an on-chip, 28bit phase accumulator, sine-coefficient
ROM, and a 10-bit D/A converter. You
typically consider sine waves in terms of
their magnitude form, A(t)sin(t). The
amplitude is nonlinear and is, therefore,
difficult to generate. The angular information, on the other hand, is perfectly
linear. That is, the phase angle rotates
through a fixed angle for each unit in
time. Knowing that the phase of a sine

wave is linear, and, given a reference interval (clock period), you can determine
the phase rotation for that period:
Phase dt; Phase/dt2
f, and
f( PhasefMCLK)/(2
), where dt1/fMand fMCLK is the master clock.
CLK ,
Using this formula, you can generate
output frequencies, knowing the phase
and master-clock frequency. The phase
accumulator provides the 28-bit linear
phase. The amplitude coefficients of the
output sine wave are stored in digital format in the sine-coefficient ROM. The
DAC converts the sine wave to the analog
domain. If you bypass the ROM, the
AD9834 delivers triangular waveforms
instead of sinusoidal waveforms. A
RDRIVE
Figure 1
R1
DVDD
48
R6
AVDD
R2
13
R7
R4
REFERENCE
R3
ADC
DAC0
8052
CORE
DAC1
10
OP
AMP
1
16
17
48
AVDD
DVDD
5
R5
24
27
26
19
ADC831
32
OP
AMP
2
RDRIVE
13
13
14
15
8
33
PHASE
ACCUMULATOR
SINECOEFFICIENT
ROM
RDRIVE
R8
FREQUENCY
REGULATOR
R9
DAC
SERIAL
INTERFACE
19
HC49/4H
11
OP
AMP
3
12
ADM3202
7
C1
TO PC
16
AD9834
VDD
AGND
18
DGND
OSCILLATOR
A DDS chip and a microcontroller combine to form a multiwaveform signal generator.
www.ednmag.com
design
ideas
DAC0, the internal reference

square-wave output is also
available on the part.
of the MicroConverter, and op
Figure 2
Figure 2 shows the
amp 2 allow for offset control
various waveforms available
of the output voltage of the
from the system. As shown in
DDS. You can program this dc
Figure 1, the sinusoidal/ trianoffset to 10 V at 10-bit resogular output waveforms are
lution. When R1R2 and the
gain of op amp 28, then the
available on the IOUT pin (Pin
output of op amp 2 is: VOUT
19); and the square wave out(DAC output(VREF/2))8,
put is available on the (a)
yielding a 10V range.
SIGN_BIT_OUT pin (Pin 16).
Resistors R6 through R9 alYou program the DDS by writlow for control of gain
ing to the frequency registers.
through op amp 3. The gain of
The analog output from the
the op amp is a function of repart is then: fOUTfMCLK/228
(frequency-register word).
sistor switching, which you enThe outputs of the DDS
able using the RDRIVE pin available on the MicroConverter.
have 28-bit resolution, so efThis operation allows for an
fective frequency steps on the
effective programmable-outorder of 0.1 Hz are possible to
put amplitude of approxia maximum of approximately (b)
mately 10V p-p. Thus, the
1 MHz. Figure 2 shows the
circuit allows for programmatypical waveform outputs. Two
ble sinusoidal and triangular
phase registers are available
waves, including dc offsets,
that allow 12-bit phase resoluand the ability to set peak-totion. These registers phasepeak amplitude of approxishift the signal by: Phase shift
mately 10V. The square
2
/4096(phase-register
wave output on the SIGN_
word).
BIT_OUT pin has 0 to 5V amA 50-MHz crystal oscillator
plitude. For low-frequency
provides the reference clock for
operation, a lowpass filter
the DDS. The output stage of
normally serves to filter referthe DDS is a current-output (c)
Sinusoidal (a), triangular (b), and square-wave (c) waveforms are
ence-clock frequencies, spurs,
DAC loaded by an external reall available from the circuit in Figure 1. The 500-kHz waveforms
and other images. For applisistor. A 200 resistor generall use a 50-MHz sampling rate.
cations in which the output
ates the required peak-to-peak
signal needs amplification,
voltage range. The output is
ac-coupled through capacitor C1. The rent of the DDS via the FSADJUST pin. you should use a narrowband filter to filMicroConverter contains two on-chip, The equation to control the full-scale ter out unwanted noise before the gain
12-bit DACs. DAC1 varies the current current of the DDS DAC is: IOUT (full- stage. A third-order filter would be good
through R5, adjusting the full-scale cur- scale)18IR5.
enough to remove most of the unwanted noise. Figure 3 shows a typical spectral plot of the output. Applications for
Figure 3
this circuit range from signal-waveform
generation to digital modulation. You
can use the system in frequency-sweeping and -scanning applications and in
resonance applications that use the frequency as an excitation signal to determine circuit resonance. Another useful
application is as a reference oscillator for
a PLL system.
This spectral plot shows the fundamental, second harmonic, and third harmonic for a 3.857-MHz signal.

www.ednmag.com
design
ideas
16-output crosspoint IC
48-input
eliminates the need for multiplexer amps
Mike Hess, Maxim Integrated Products, Sunnyvale, CA
rosspoint switches are ideal for
use in video-security systems, which
accept multiple camera inputs while
providing playback and multiple loopthrough to multiple monitors. To provide
video loop-through or monitor outputs,
these systems often require additional
multiplexer amplifiers that can drive
standard video loads. Thus, one or more
external multiplexer amps often follow a
crosspoint-matrix switch. As an alternative, you can employ a 3216 nonblocking crosspoint-matrix switch, whose 16
2-to-1 multiplexers eliminate the need
for extra multiplexer amps (Figure 1).
The internal 2-to-1 multiplexers appear
before the video-output buffers, which

can each directly drive a standard video
load. That configuration eliminates the
need for external multiplexer amps and
their associated cost, space requirement,
and power consumption.
The MAX4358 IC is a fully buffered,
32-input16-output nonblocking crosspoint switch that includes 16 additional
buffered analog-video inputs (OSDFILL)
intended for the insertion of OSD (onscreen-display) information. (Nonblocking means that the IC can route
any input to any output.) The 16 fully
buffered OSDFILL analog inputs are
identical to the 32 inputs of the buffered
crosspoint-switch matrix, so the 16 additional video inputs can implement a single-chip, 48-input16-output crosspoint-switch matrix. The output buffers
feature programmable gain (AV1V/V
or 2V/V). The programmability allows
versatility in routing short video traces or
driving video-transmission lines. Operating from dual 3 to 5V supplies or a
single 5V supply, the device reduces power consumption by as much as 60% versus standard 5V-only ICs.
MULTIPLEXER/QUAD
VIDEO PROCESSOR
Figure 1
16 BUFFERED
INPUTS
OSDFILL15
OSDFILL1 OSDFILL0
IN0
OUT0
75
C
IN1
MONITOR 0
OUT1
75
32-INPUT
16-OUTPUT
NONBLOCKING
MATRIX
SWITCH
32 BUFFERED
INPUTS
MONITOR 1
16 2-TO-1
MULTIPLEXERS
16 BUFFERED VIDEOLINE-DRIVING OUTPUTS
OUT15
RECORDER
75
C
IN31
SERIAL
INTERFACE
MAX4358
MICROPROCESSOR
CONTROL
OSDKEY15
OSDKEY1
OSDKEY0
ASYNCHRONOUS 162-TO-1
MULTIPLEXER CONTROL
16-output matrix switch without the need for external multiplexer amps.
Internal buffers allow this IC to implement a 48-input
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ideas
Transmission line tests 1-kW device using only 100W

David Cuthbert, Meridian, ID
13.56-MHz, ISM (industrial, scienCURRENT
VOLTAGE
MAGNITUDE
MAGNITUDE
tific, and medical)-band RF-measurement device had the test
Figure 1
requirement of a 50-hour, 1-kW
burn-in. The device under test needed to
T1
T2
be simultaneously stressed at an RF po4
43 LINE
43 LINE
ANTENNA
DEVICE
tential and RF current equivalent to 1
TUNER
UNDER
kW, but the only spare RF source at hand
TEST
was a 100W RF generator. Besides, savRF
ing energy seemed important. The cirSOURCE
cuit in Figure 1 develops 1 kW from the
100W RF source by storing energy in a
transmission line. The circuit comprises
two 43 sections (approximately 6 feet) As if by magic, this setup allows you to apply 1 kW to a device using only a 100W generator.
of RG-213 coaxial cable with UHF connectors at each end. The device under tuner matches the 50 RF generator to the shorted end of the line, where it is reflected and travels back to the input. The
test, which has an electrical length of 4, the lines input impedance.
Circuit operation is simple. The RF en- reflected energy then reflects off the conconnects between the two lines, T1 and
T2, making the total line length 90. An ergy connects to the lines input through jugate match, which the antenna tuner
off-the-shelf amateur-radio antenna the antenna tuner. The energy travels to provides, and combines with the next
www.ednmag.com
design
ideas
half-cycle of input energy to flow toward

the short again. This process continues
with the stored energy continuing to
build until the circuit losses equal the
generator power. Considering the circuit
operation in terms of impedances reminds you that the input impedance of
a shorted, lossless, 90 transmission line
is infinite. At the shorted end of the line,
V/I is zero, and, at the input of the line,
V/I is infinite. At the center, where the device under test is located, the magnitude
of V/I is equal to the characteristic impedance of the transmission line50
in this case. The RF voltage and current
are 90 out of phase, but that fact does not
affect the burn-in of the device.
Consider how much line input power is
required to develop 1 kW at the device under test. The loss of each 6-foot section of
RG-213 is 0.025 dB, and the device-undertest loss is 0.05 dB. The loss for a wave traveling down the line is therefore 0.1 dB. The
return loss, RL, is twice this amount, or 0.2
dB, because the wave must travel down the
line to the short circuit and return to the
source. Now, you can calculate the reflected power, PR, for an incident power, PIN, of
1000W using the following formula:
P R (P IN )10 (RL/10) (1000)10 (0.2/10)
955W.
So, when 1000W flows down the line,
955W returns to the input. The line input
power required is equal to the incident
power minus the reflected power, which is
1000955, or 45W. Because the line loss
and device-under-test loss are both 0.05
dB, half of the 45W loss is dissipated in the
coax, and half is dissipated in the device
under test. The measured antenna-tuner
loss is 40W, which makes the total circuit
loss 85W. You can determine the lines input impedance by calculating the line-input complex reflection coefficient () and
solving for the input impedance using
10(RL/20)10(0.2/20)0.9772, and
Z LINE ( + 1)
=
1
50(0.9772 + 1)
4.3 k .
10.9772
The antenna tuner must match the

50 generators output impedance to the
4.3-k line-input impedance. You can
confirm the circuits operation by measuring the amplitude and phase of the devices voltage and current. The measurement uses an oscilloscope with voltage
and current probes. A power meter at the
device under test measures forward and
reflected power of 1 kW. Because of the
high circuit Q, youll find that adjusting
the RF-source frequency to obtain circuit
resonance is easier than trimming cable
lengths to obtain circuit resonance. The
primary limiting factors with this circuit
are the temperature rise of the coaxial cable and the losses incurred in the impedance-matching circuit. Coax having lower loss allows you to achieve a higher
power multiplication and higher device-under-test power.
Z IN =

issue? Vote at www.ednmag.com.
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design
ideas
Key-reading circuit saves I/O pins

Gustavo Santaolalla, Digital Precision Systems, Buenos Aires, Argentina
ome microcontroller applications usually use too many I/O pins
to read keys or onboard switches; in
many cases, few pins remain available for
other uses. Some alternative ways to read
keys yield more free pins. First, consider
some ways to effect key reading. Table 1
presents a comparison of four methods
with references to circuit configurations
(figures 1, 2, 3, and 4). As you can see, the
best choice for reading many keys is to
Key-reading circuit saves I/O pins............117

Synchronous buck circuit produces
negative voltage ..........................................120
Rotary encoder mates
with digital potentiometer ........................124
Amplifiers perform
precision divide-by-2 circuit ......................126
1
2
3
4
5
IRQ1
RST
10
18
19
16
17
Figure 1
Figure 2
Figure 3
Figure 4
20
2
3
OSC1
OSC2/PTA6
VDD
PTB7
PTD7
PTB5
PTD6
PTB4
PTD5
PTD4
PTB3
PTB2
PTD3
PTB1
PTD2
PTB0
VCC
IRQ1
11
10
12
18
13
19
14
16
15
17
In this simple configuration, you need as many

I/O pins as you have keys.
RST
Notes
16 pins=16 keys
With ADC, 16 keys=two pins
16 keys=eight pins (four inputs and four outputs)
16 keys=five pins (four more keys available)
microcontroller scans each input for a logic 1, and, if it finds it, a key press has occurred. If not, it turns the next line into
an output, sets it, and turns the other two
into inputs, and so on. In this way, you can
confirm each time a key press takes place.
R4, R5, and R6 are current-limiting resistors, and R1, R2, and R3 are simple pulldown resistors. The circuit uses three
LEDs for debugging.
Listing 1 shows the complete program. An MC68HC908JK3 tested the
software, but the routine is probably applicable to other microcontrollers. The
program has no debounce function; you
(continued on pg 120)
20
OSC1
OSC2/PTA6
VDD
PTB7
PTB6
Figure 1
No. of pins
No. of pins
N/8
NIN+NOUT
N
VSS
7
PTD7
PTB5
PTD6
PTB4
PTD5
PTB3
PTD4
PTB2
PTD3
PTB1
PTD2
PTB0
vcc
7
8
11
12
13
14
15
68HC908JK3
68HC908JK3
www.edn.com
No. of keys
N
N
NINXNOUT
N
use the A/D converter that is inherent in

many microcontrollers. This option
needs many lines of code and is not
amenable to resistive buttons, such as
flexible key pads (Reference 1). Another
option is to read one key with one I/O
port, but it needs as many pins as the keys
to read.
Figure 4 shows another possibility, the
subject of this Design Idea. In this configuration, the microcontroller reads six keys
with only three lines of I/O pins. This
method entails the use of a few external
components. The idea is to turn one of the
three lines into output, set it at logic 1, and
use the other two lines as inputs. Then, the
VSS
PTB6
9
TABLE 1VARIOUS KEY-READING SCHEMES
Figure 2
Using the microcontrollers internal ADC, you need only two I/O pins to control 16 keys.
March 6, 2003 | edn 117
design
ideas
Figure 3
1
2
3
4
5
IRQ1
RST
VSS
OSC1
OSC2/PTA6
PTB7
VDD
PTB6
9
10
18
19
16
17
20
PTB5
PTD7
PTD6
PTB4
PTD5
PTB3
PTD4
PTB2
PTD3
PTB1
PTD2
PTB0
6
7
8
11
12
13
14
15
68HC908JK3
In a matrix configuration, you need eight I/O pins to control 16 keys.
Figure 4
27 pF
VCC
VCC
5V
20
0.1 F
LED
330
13
RST
IRQ1
PTB1
LED
4 MHz
2
VSS
3
OSC1
4
OSC2/PTA6
5
VDD
68HC908JK3
19
PTB4
PTB2
14
27 pF
Y1
10M
1N4148
VCC
R4
100
16
R5
100
17
R6
100
15
1N4148
1N4148
PTB2
KEY
13
VCC
LED
KEY
32
PTB3
330
PTB0
KEY
23
1N4148
1N4148
KEY
31
1N4148
330
0.1 F
R1
10k
R2
10k
R3
10k
KEY
12
KEY
21
With an expansion of this scheme, five I/O lines control 16 keys with room to add four more keys.
118 edn | March 6, 2003
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design
ideas
can add it for a real application. The

program shows the variable KeyVal on
three LEDs. You can probably write
more efficient code that that of Listing
1; the code shown is just for testing.
Table 1 shows how many pins you need
to read 16 keys. As you can see, with the

circuit in Figure 4, you need only five
pins, but you can add four more keys.
You can download Listing 1 from the
Web version of this Design Idea at
www.edn.com.
Reference
1. Motorola application note AN1775,
www.motorola.com.
LISTING 1PROGRAM TO READ SIX KEYS AND DISPLAY RESULTS ON SIX LEDs
Synchronous buck circuit produces negative voltage

John Betten, Texas Instruments, Dallas, TX
120 edn | March 6, 2003
ponents that a negative flyback circuit reQ1

quires. When FET Q1 turns on, the input
D1
voltage appears across inductor L1 with
VIN
VOUT
no input current going to the load at this
point. All the output current delivered to
the load at this time comes from output
L1
C1
capacitor C1, because diode D1 is reverseCONTROL
biased. The current in the inductor continues building until the control circuit
determines the proper time to
Figure 1
switch off FET Q1. At that point,
the voltage polarity across inductor L1 reverses in an attempt to maintain current This flyback topology produces negative output
flow, pulling the top side of the inductor voltage from positive inputs.
+
any electronic systems require

both positive and negative voltages
to operate properly. Generating an
efficient, low-voltage positive output
from a higher voltage input typically entails the use of a synchronous buck regulator. But when generating a negative
output voltage from a positive input voltage, youd typically use a flyback topology, especially at higher output currents.
The operation and control characteristics
of a synchronous buck and a negative flyback (also called a buck-boost) differ significantly. Figure 1 shows the basic com-
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ideas
negative with respect to ground and forc- when both FETs Q1 and Q2 are off, furing diode D1 to conduct. The output volt- ther reducing losses. The feedback voltage goes negative to within a diode drop age appears at the output ground
through resistor R1, because the control
of the inductor voltage.
The duty cycle at which the control cir- circuit is referenced to the negative outcuit operates also differs from that of a put voltage. R2 typically sets the output
synchronous buck. Although the operat- voltage to the desired level, because it
ing duty cycle of a synchronous buck is does not change the feedback compensaDVOUT/VIN, the negative flyback oper- tion network, as changing R1 would. Deates at DVOUT/(VOUTVIN). For exam- sired changes to the input voltage, the
ple, if the desired output voltage is half output voltage, or both may necessitate
the input voltage, the synchronous buck an inductor-value change. The minimum
runs at 50% duty cycle, whereas the neg- inductor value is:
ative flyback runs at 33% duty cycle. The
comparisons between the simple negative
VOUT (VINMAX )2
.
flyback circuit of Figure 1 and the syn- L MIN =
2
2fMIN IOUTMIN VOUT + VINMAX
chronous-buck-controller negative flyback circuit in Figure 2 are straightforward. In Figure 2, FET Q2 mirrors the
Take note of certain limitations with
function of diode D1 in Figure 1 but with using the controller in this type of ima decrease in the forward drop that oc- plementation. Because the control circurs in the diode. This lower drop signif- cuit is referenced to the negative outicantly improves efficiency. Diode D3 put-voltage rail, the controller must
conducts during the small dead time, have an input-voltage rating greater
than VIN|VOUT|. The controller must

also be rated for VIN (minimum), which
occurs at system power-up when the
output voltage is zero. A controller that
operates over a wide input-voltage
range typically works best. The FETs
drain-to-source rating must also withstand VIN|VOUT|, and the FET carries
peak currents that are greater than twice
the output current. Low-resistance, fastswitching FETs produce the lowest losses. High efficiency is the major advantage of this circuit. Because the circuit
uses n-channel FETs, as opposed to
higher resistance and costlier p-channel
parts, the circuit achieves peak efficiencies greater than 90%.

R1
100k
1
8 7 6 5
20k
220
pF
3.24k
D1
MBR0530
0.01
F
470 F
35V
12VIN
GND
4
Q1
IRF7811
3 2 1
0.01
F
1
SOFTSTART
INV
3
33 pF
182k
R2
11k
FB
4
5
6
1 F
7
8
10
0.1 F
LH
OUTU
IC1
TPS5103
20
1 F
19
OUTD
RT
OUTGND
GND
TRIP
REF
VCCSENSE
VCC
PWM/SKIP
VREF5
STBY
5VIN
FREQUENCY=250 kHz
47 H
3.3
LL 18
CT
COMP
Figure 2
2.2 F
35V
17
16
15
14
8 7 6 5
13
10 F
16V
12
10 F
16V
330 F +
16V
4
Q2
IRF7811
11
1 F
1 F
D2
MBR0530
D3
MBRS340
3 2 1
1
2
GND
12V
AT 1A
A synchronous buck controller forms the heart of this negative-flyback configuration.
122 edn | March 6, 2003
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ideas
Rotary encoder mates with digital potentiometer

Peter Khairolomour, Analog Devices, San Jose, CA
n developing electronic systems,
designers look for products or ideas
5V
that may benefit from the
Figure 1
better performance, smaller
A1
size, lower cost, and improved reliabilR1
R2
DIGITAL
QUADRATURE
ity that an IC can offer. Toward that
10k
10k
R3
POTENTIOMETER
DECODER
end, the digital potentiometer emerged
10k
ROTARY
1 RBIAS CLK 8
1 CLK
VDD 8
ENCODER
as an alternative to its mechanical
AD5220
2 VDD
2
7
counterpart, the mechanical potenU/D 7
U/D
CS
B
B1
tiometer. The digital potentiometer ofRWB
1 B1 6
3 VSS X4/XT 6
3 A1
C
fers most of the cited advantages but
W1 5
4 A LS7084 B 5
4
falls short for users of mechanical poGND
A
W1
tentiometers, who require a simple rotary interface for front-panel adjustment or calibration without external
controllers. The circuit in Figure 1 represents an attempt to combine the best
of both worlds: the simplicity of a rotary interface and the performance of a A quadrature decoder and a digital potentiometer form a simple rotary-encoder interface.
digital potentiometer. The rotary encoder in this circuit is the RE11CT- in synchronism with its output, which fects. This feature is important for this
V1Y12-EF2CS from Switch Channel also connects directly to the AD5220. You type of application. Unlike optical en(www.switchchannel.com). This type of linearly vary the clocks pulse width by coders, the RE11CT-V1Y12-EF2CS is a
rotary encoder has one ground termi- adjusting RBIAS.
low-cost electrical encoder, in which
nal, C, and two out-of-phase signals, A
Aside from decoding the quadrature each turn can create some bounce or
and B (Figure 2). When the rotary en- output of the rotary encoder and pro- noise issues because of the imperfect
coder turns clockwise, B leads A (Figure viding a clock signal, the LS7084 also fil- nature of the metal contacts within the
2a), and, when it turns counterclock- ters noise, jitter, and other transient ef- switch. The LS7084 prevents such errowise, A leads B (Figure 2b).
neous signals from reaching the
Signals A and B of the rotary enAD5220. The operation of the
coder pass through a quadrature
circuit in Figure 1 is simple.
CLOCKWISE
decoder (LS7084 from
When the rotary encoder turns
Figure 2
LSI Computer Systems,
clockwise, the resistance from
A
www.lsisci.com), which translates
the wiper to terminal B1 of the
the phase difference between A and
digital potentiometer, RWB1,
increments until the device
B of the rotary encoder into a
reaches full scale. Any further
compatible output, CLK and U/D,
B
(a)
turning of the knob in the same
that the AD5220 can accept. The
direction has no effect on the
AD5220 from Analog Devices
resistance.
(www.analog.com) is a 128- step,
COUNTERCLOCKWISE
Likewise, a counterclockwise
pushbutton digital potentiometer.
turn
of the knob reduces RWB1
It operates with a negative-edgeA
until it reaches the zero scale,
triggered clock, CLK, and an inand any further turning of the
crement/decrement direction sigknob in the same direction has
nal, U/D. When B leads A
no effect. One example of the
(clockwise), the quadrature deflexibility and performance this
coder provides the AD5220 with a
B
(b)
circuit offers becomes apparent
logic-high U/D. When A leads B
when you consider systems with
(counterclockwise), the quadrafront-panel rotary adjustment.
ture decoder provides the AD5220
In clockwise rotation, signal B leads A (a); in counterclockYou can lay out the compact
with a logic-low U/D. The quadrawise rotation, A leads B (b).
digital potentiometer and quadture decoder also produces a clock
124 edn | March 6, 2003
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design
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rature decoder anywhere in the system.

All the ICs need are two digital control
signals routed to the front panel where
the rotary encoder is located. This setup proves impervious to interference,
noise, and other transmission-line effects that arise in traditional designs

with mechanical potentiometers. These
designs force the sensitive analog signal
to travel all the way to the front of the
panel to be processed and then back to

its destination.
Amplifiers perform precision divide-by-2 circuit

Glen Brisebois and Jon Munson, Linear Technology Corp, Milpitas, CA
he classic implementation of a
voltage-halving circuit uses two
equal-value resistors. Using 1% resistors provides a divider outFigure
put with 2% accuracy. For
most applications, this performance is
cost-effective and more than adequate.
However, when you need extreme precision, this approach requires correspondingly accurate resistors and can become
expensive. Putting feedback around a finite-gain instrumentation amplifier
yields a divide-by-2 circuit with the
added benefit of a buffered output (Figure 1). The operation of the circuit is
straightforward. The instrumentation
amplifier has unity gain, so the voltage it
sees across its inputs appears between
VREF and VOUT: VOUTVREFVIN()
VIN(). But, considering the circuit in
Figure 1, note that VOUTVIN(), and
VREF0. Substituting in the first equation, you obtain VOUTVIN()VOUT,
2VOUTVIN(), or VOUT 1/2 VIN().
Thus, you have a divide-by-2 circuit. One
of the interesting features of this approach is that the input and the output
VIN
VIN(+)
VIN()
INSTRUMENTATION
AMPLIFIER
+
VOUT
VREF
REFERENCE
An instrumentation amplifier makes a simple

divide-by-2 circuit.
offsets of the instrumentation amplifier

are divided by 2 as well.
You can implement the circuit on the
bench using the LT1167 or the LTC2053
instrumentation amplifiers (Figure 2).
Although benchtests are unnecessary,
you can introduce an RC network into
the feedback path for noise shaping and
to guarantee dominant-pole behavior. To
test for LT1167 offset, set VIN() to 0V
and alternate VIN() between 0V and
VOUT. This test confirms that the feedback
halves the total offset voltage. Dividing
10V to 5V, the LT1167 shows an error of
100 V. With the more precise LTC2053,
the output error in dividing 2.5V to
1.25V is an almost-immeasurable 2.5 V.
Using cold spray and a heat gun, you can
5V
Figure 2
8
15V
VIN
1 nF
VOUT =
VIN/2
+
1
8 LT1167
6
_
5
4
3
_15V
VIN
10 nF
+IN
3
_IN
CH
OUT
1k
Practical implementations of the circuit in Figure 1 use the LT1167 (a) and the LTC2053 (b).
126 edn | March 6, 2003
VOUT =
VIN/2
7
REF RG VS_ EN
5
(b)
VS+
+
CS
2
2k
(a)
LTC2053
degrade this error to 15 V. However,

perhaps equally important are the calculated worst-case results.
Worst-case calculations for the LT1167
show a maximum 1.12-mV error over 0
to 70C with 10V input and 5V output.
This figure constitutes a total error of 224
ppm over temperature. Resistors that
guarantee this accuracy would need a
maximum tolerance of 112 ppm each
over temperature. The error budget of a
resistor-divider solution would require
an initial ratio match of approximately 50
ppm with a temperature-coefficient
match better than 1 ppm/C. Worst-case
calculations for the LTC2053 with 2.5V
input and 1.25V output show a maximum 80-V error over 0 to 70C. This
figure constitutes a total error of 64 ppm
over temperature. Resistors that guarantee this accuracy would need a maximum
tolerance of 32 ppm each over temperature. The error budget of a resistor-divider solution would require an initial ratio match of approximately 15 ppm
(0.0015%) with a temperature-coefficient match better than 0.25 ppm/C. In
either case, resistors of this caliber would
be extraordinarily expensive if available
at all. Also, the amplifiers provide the additional benefits of high input impedance
and output buffering. Moreover, the error calculations include the effects of input offset voltage, bias current, gain error, and common-mode rejection ratio,
which a resistor op amp would still have
to add.

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Correct voltage drop and phase shift

in transmission lines
Ron Shakery, Texas Instruments, Dallas, TX
any precision test-and-measure1
+
3
ment and high-speed analog appli2
4
cations require an exact targeted

voltage to be delivered to the deFigure 1
vice under test or intended load

2
2
to accurately analyze the device. Design
+
1
+
and test engineers are well-aware that this
1
15V
goal is sometimes unattainable, because
RTRACE
the impedance across the traces delivering
A
B
C
the signal to the load alters the original sig3
THS45XX
nal. Traditionally, engineers use a Kelvin
LOAD
1
4
+
DEVICE
connection to measure the accurate volt6
6
UNDER
+
age that the load or the device under test
TEST
VOCM
3
sees at its terminals. The Kelvin-connecRTRACE
tion method enables you to accurately
measure the voltage at the load terminal,
15V
but it may not correct for the voltage drop
1
or the phase shift that occurs dynamical+
3
ly across the signal lines with various im2
pedances. In high-frequency signals, the
2
RLC (transmission-line effects) of the
+
traces come into play and cause a signifi1
3
2
cant signal phase shift. As a result, design+
1
ers always look for the least expensive
methods to correct the voltage drop and
the phase shift across the transmission
lines. The circuit in Figure 1 is a fully dif- This fully differential circuit compensates for voltage drop and phase shift in transmission lines.
ferential line driver comprising a fully differential amplifier and two high-frequenThe resistance associated with each voltage drop across RTRACE. This voltage
cy, high-impedance feedback paths.
trace causes a voltage drop through the then adds to the input of the line driver
path. Thus, the signal amplitude delivered at the summing Node A. Because the cirto the load is lower than the signal am- cuit is symmetrical, the same function ocCorrect voltage drop and phase shift
plitude at the output of the fully differ- curs at the opposite corresponding points.
in transmission lines....................................105
ential line driver. This voltage drop is pro- As a result, regardless of the value of the
Why limit your power supplys
portional to the resistance value of the total voltage drop across RTRACE, the subinput range?..................................................106
trace, RTRACE, and the current flow
Virtual-zener circuit simplifies
through the corresponding trace. For exhigh-voltage interface ................................108
10
1 nH
1 nH
B
C
ample, if the output current of the line
Multilayer capacitor doubles
driver is 100 mA and the trace resistance
10 nF
as varactor ....................................................110
is 10, a 1V drop develops across
F
i
g
u
r
e
2
Buck regulator and two inductors
RTRACE. As a result, if the output ammake dual-polarity converter....................112
plitude is 10V p-p, the load sees a 9V p-p
signal. The feedback paths, which work as This circuit represents a simulated transmisPublish your Design Idea in EDN. See the
subtracters, accurately measure this volt- sion line inserted between points A and B of
age drop. The feedback paths measure the the circuit in Figure 1.
www.edn.com
March 20, 2003 | edn 105
design
ideas
300
tracter measures it and adds it back into

the input signal of the line driver. Consequently, the output of the line driver increases by the measure of the voltage drop
across RTRACE, and the load sees the exact
voltage it was initially intended to see. Because the circuit is a closed-loop system
and has negative feedback, the circuit remains in a stable condition.
The buffers in the feedback paths form
a high-input-impedance node to prevent
any load alteration. For example, without
buffers, the series and parallel resistors of
the subtracter would cause the value of the
load to vary. These buffers, in conjunction
with the subtracter, form an instrumentation amplifier. You can adjust this configuration for different gains to create variations of this circuit for different applications. The instrumentation amplifier
creates a high-input-impedance path that
works similarly to the sense lines of a
Kelvin connection. The main difference is
that the sense line in this circuit measures
the actual voltage drop across RTRACE over
various frequencies and adds it back to the
original signal. You should pay attention
to the ratio of the line drivers gain configuration and the subtracters gain configuration to ensure stability of the circuit.
Additionally, you should verify that the
bandwidths of the feedback-path devices
are greater than the bandwidth of the line
driver to prevent any added errors to the
system via feedback pathsbandwidth limitations. You may choose to design the
feedback paths with much greater band-
NODE B
width than the line driver
WITH FEEDBACK
200
(two times greater, for exNODE B
NODE C
WITHOUT
ample). Doing so enables
WITHOUT
FEEDBACK
PHASE
this circuit to correct the
FEEDBACK
SHIFT() 100
phase shift across the
NODE C
transmission line if the
WITH
0
traces manifest RCL charFEEDBACK
acteristics.
Figure 3
For exam100
1 GHz
1 Hz
1 kHz
1 MHz
ple, assume that you insert
FREQUENCY
a transmission-line model between nodes B and C The phase-shift curves at Node B before the transmission line
in the circuit of Figure 1, as and at Node C after the transmission line show the effect of the
in Figure 2. The bandwidth feedback path in correcting the phase shift at the end of the
of the fully differential am- transmission line.
plifier is 300 MHz at unity
gain, and the input signal is 2V p-p. The to using a single-ended line driver with
bandwidth of the feedback paths is 600 the same power supplies and similar specMHz to prevent any added phase shift to ifications. However, the nature of fully difthe signal from the feedback circuit. Con- ferential configurations requires that you
figuring the test circuit as such lets you see pay close attention to maintaining the
the phase shift that the transmission line balance of passive and active components
alone introduces. The transmission line to preserve the signal integrity delivered
causes a significant phase shift in the sig- to the load. Therefore, you should set
nal delivered to the load. Figure 3 shows equal resistor values on the top and the
the phase-shift curves at Node B before bottom feedback paths. This design can
the transmission line and at Node C after correct for voltage drop and phase shifts
the transmission line, right above the across the transmission lines in low- and
load. These curves show the effect of the high-frequency cases. Design simplicity
feedback path in correcting the phase shift and the fact that the design uses few comat the end of the transmission line where ponents make it cost-effective for many
the load is located. This circuit configu- applications dealing with voltage-correcration essentially corrects the phase shift tion and phase-shift issues.
of the signal that the RCL of the transmission line causes. The fully differential
line driver enables you to deliver twice the Is this the best Design Idea in this
voltage swing across the load as opposed issue? Select at www.edn.com.
Why limit your power supplys input range?

Michael Day, Texas Instruments, Dallas, TX
aking only a cursory look at the
input-voltage ratings of your powersupply IC can limit the usable inputvoltage range. With careful examination
of an ICs operating specifications and
circuit topology, you may be able to work
around that input-voltage limitation. For
instance, The data sheet for TIs
(www.ti.com) TPS61042 shows that it
has all the functions necessary for providing a constant-current drive to a
white-LED circuit; however, the input
voltage of the IC does not meet the input-
106 edn | March 20, 2003
voltage requirements of this Design Idea.

The dual lithium-ion input voltage varies
from 6 to 8.4V, but the TPS61042 inputvoltage range is 1.8 to 6V. Closer examination of the circuit shows that the power stage need not connect to the same
voltage rail as the control IC. Figure 1
shows that by separating the input voltage to the TPS61042 from the power
stage, you can power the LED driver from
an input voltage greater than 6V.
The IC can receive power from any
available system voltage of 1.8 to 6V by
connecting this voltage to the VIN pin.

The input to the power stage can now connect directly to the battery. In general, the
power stage can connect to any voltage
that is lower than the required output voltage. With a boost topology, the input voltage to the power stage must be less than
the output voltage, or the inductor and
diode pass the input voltage directly to the
output. The maximum allowable voltage
on the SW pin, 28V, also limits the maximum input voltage to the power stage.
This technique also improves system efwww.edn.com
design
ideas
WHITE
DUAL LITHIUM-ION
BATTERY
6 TO 8.4V
WHITE
WHITE
WHITE
2.2 H
4.7 F
BREAK
THIS
CONNECTION
SYSTEM 3.3V
0.1 F
13.7
IC1
TPS61042QFN
1
8
LED
SW
2
7
RES
OVP
3
6
VIN
GND
4 FB
CTRL 5
ZHCS400
PWP
9
Figure 1
This circuit provides a way to get around a power-supply ICs input-voltage limitations.
1 F
ficiency. Efficiency data for this circuit

shows that higher input voltages provide
higher efficiency. If you have to run the
LED driver from a voltage that is lower
than 6V, the power to drive the LED is
double-converted.It first converts from
the raw lithium-ion input into an intermediate system voltage and then converts
from the intermediate-system voltage
into the LED-drive current. By carefully
examining the operating specs for the IC,
you can get around around its input-voltage limitation, save cost and board space,
and increase system efficiency.
Virtual-zener circuit simplifies high-voltage interface

Philip Lane, Transparent Networks Inc, Bellevue, WA
his design for a photonic switch
80V (EXTERNAL POWER)
needs more than approximately 70V
(GROUND-REFERRED)
70V
at the cathode of a duo-lateral optiSHUNT
cal position-sensing device.
REGULATOR
Figure 1
60V
This voltage gets speedy response at longer wavelengths, such as 980
80V
1k
nm. The circuit uses fast transimpedance
amps,floated at 70V. Two virtual-zener circuits step down the high-voltage
VIRTUAL
I TO V
signals for subsequent processing in a
ZENER
Y POSITION
ground-referred differential-amplifier
70V
stage (Figure 1). The circuit drops ex10V POWER
"FLOATING"
actly 65.58V dc with the component valAT 70V
VIRTUAL
DIFFERENTIAL
16-BIT, 500kI TO V
CATHODES
ues shown, notwithstanding errors arisZENER 5V
AMPLIFIER
SAMPLE/SEC ADC
(X AXIS)
ing from op-amp offset voltages and
(70V)
resistor tolerances (Figure 2). The func1k
HIGH-VOLTAGE
CIRCUITRY
tion of the virtual-zener circuit is to proPOSITION-SENSING DEVICE/
DUO-LATERAL SENSOR
vide a regulated, floating dc voltage drop
between input and output. The size of
1k
the drop depends on the ratio of R1 to R2
ANODES
and the magnitude of the reference volt(X AXIS)
age. The input of the circuit, nominally
(GND)
I TO V
10V POWER
at 70V dc, draws a constant 3.65 mA. The
X POSITION
(EXTERNAL
THS3001 sources or sinks this current
GROUND-REFERRED)
plus any additional current as necessary,
adjusting the output voltage until the
DIFFERENTIAL
16-BIT, 500kI TO V
AMPLIFIER
SAMPLE/SEC ADC
voltages at its two inputs are equal. This
equality occurs when VZ(VINVOUT)
TOTAL POWER
1k
VREF(1R1/R2).
The op amps power-supply rails and
output range, along with the voltage
SUMMING
16-BIT, 500kdrop across R3, limit the output-voltage
AMPLIFIER
SAMPLE/SEC ADC
bypasses
R
.
This
bypass
compliance. C1
1
swamps the bandwidth-reducing effect of Virtual-zener circuits simplify the high-voltage interface in this position-sensing system.
108 edn | March 20, 2003
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design
ideas
TP1
VIN
TEK RUN: 500MS/s

SAMPLE
R4
100k
332k
C1
1F
250V
D1
1N5240B
IN
OUT
C1 P-P
1.000V
0.047 F
R1
332k
25V
6.8 F
35V
+
7
3
IC1
2 THS3001
_
6 2.74k
IC2
LT1021-5
7
3 HEAT
TEMP
5
TRIM GND
4
4 8
R2
2.74k
6.8 F
35V
_5V
C2
0.047 F
0.047 F
6.8 F
35V
R3
150k
CH1 200 mV
RLOAD
Figure 2
This virtual-zener circuit provides a regulated, floating voltage between the input and output.
capacitance at the noninverting input,

and it greatly reduces the noise at the output. Without C1, the op amps inherent
noise would gain up by a factor of
(1R1/R2). R4 protects IC1s noninverting
input by limiting the transient current
supplied by C1 during power-up and
power-down. R3 and the output, RLOAD,
BW
CH2 200 mV
BW
_20 mV
M 100 nSEC CH1
VOUT
have a similar protective effect on the inverting input, limiting any transient current in C2. R3 is necessary to ensure feedback stability of the op amp. The
inclusion of this resistor is standard operating procedure for a current-feedback
op amp, such as the THS3001. If you use
a voltage-feedback type, you could possi-
Figure 3
The transient response of the circuit in Figure 2
is exceedingly fast.
bly eliminate R3. Bandwidth is extremely

high. Figure 3 shows the pulse response
at 100 nsec per division. (Blue is the input, and red is the output.)
Multilayer capacitor doubles as varactor

Susanne Nell, Breitenfurt, Austria
he main purpose for building the
R1
10k
circuit in Figure 1 is to study the idiosyncrasies of X5R, Z5U, and Y5V
multilayer ceramic capacitors. The circuit
is also an inexpensive VCO (voltFigure 1
age-controlled oscillator) with
2
1
only five components. Many types of ceramic capacitors for surface-mount
IC1
placement are on the market. The parts
74HC14
2
become continually smaller because of
C
space problems on the board, and the ca1
1
10 F
R2
pacitance values continually increase to
100k
compete with more expensive tantalumJ1
2
electrolytic units. Unfortunately, capaci1
tors with X5R, Z5U, or Y5V dielectrics
C2
VBIAS
CERAMIC
have some undesirable properties. They
exhibit voltage-dependent capacitance
values. The idea behind the circuit in FigThis simple oscillator shows the effect of a dc bias on a multilayer capacitor, C2.
ure 1 is to check the influence of a dc bias
110 edn | March 20, 2003
J2
fOUT
www.edn.com
design
ideas
voltage on the frequency of a simple oscillator. The net result is a low-frequency VCO with a relatively large voltagegain figure, which depends largely on the
type of capacitor you use.
The circuit is a simple oscillator using
a Schmitt-trigger inverter. The frequency is a function of R1, C1, and C2. C2 is the
200
150
4.7 F
fOUT
(Hz) 100
10 F
50
0
0
10
15
VBIAS (V)
Figure 2
The frequency of the oscillator in Figure 1
F Z5U
exhibits almost a 4-to-1 shift for a 4.7-
multilayer capacitor.
ceramic capacitor with voltage-depend2000

ent capacitance. Using the value of C1,
1 F
1500
you can shift the frequency independ10 F
ently of C2. This design uses a stable-foilfOUT
1000
(Hz)
type capacitor for C1 to avoid bias-voltage-dependent effects in the measured
500
results. If necessary, you can compensate
the temperature coefficient of the ca0
0
5
10
15
pacitor with a combination of NTC,
VBIAS (V)
PTC, and metal-film resistors for R1.
Figure 3
For measurements, this design uses
a simple metal-film resistor. The capacThe value of C1 has little effect on the frequenitance change with temperature is norcy curves for the circuit in Figure 1.
mally less than 10% from 10 to 35C for
Z5U and Y5V and much lower for X5R. ange: 1 F; purple: 10 F). The moral of
Figure 2 shows the measured voltage- the story is: Be wary when using high-caversus-frequency graphs with different pacitance ceramic capacitors with high
values and types for C2. For Figure 2, or variable dc bias; the varying capaciC110 F; the orange curve represents tance can greatly influence circuit pera 4.7-F, 10V, Z5U multilayer capacitor, formance.
and the purple curve represents a 10-F,
10V, Z5U multilayer capacitor. Figure 3 Is this the best Design Idea in this
shows similar plots for values of C1 (or- issue? Select at www.edn.com.
Buck regulator and two inductors

make dual-polarity converter
Keith Szolusha, Linear Technology Corp, Milpitas, CA
common problem for power-sup9 TO 16V
D2
36V TRANSIENT
ply designers is to create a compact,
1N4148
VIN
dual-polarity step-down converter.
C1
VOUT1
If space and cost are not concerns, the ob0.1 F
BOOST
vious solution is a pair of dc/dc convertVIN
VSW
L1
5V
ers, one for each output. But space and
CDRH4D28-150
700 mA
VBIAS
SYNC
IC
1
cost are almost always issues for commuLT1956EFE
nications, data-acquisition, and disk15.4k
2.2 F
SHDN
50V CERAMIC
drive applications. Figure 1 shows a sin10 F
FB
VC
6.3V
GND
gle current-control- regulator approach
C2
0805 CERAMIC
10 F
2.2k
4.99k
X5R
that supplies 5V at 700 mA and 5V at
220 pF
D1
6.3V
B0540W 0805 X5R
500 mA from a 12V system source. The
CERAMIC
3300 pF
circuit features efficiency similar to that
of a two-regulator solution and has no
component measuring more than
10 F
L2
6.3V
CDRH4D28-150
3 mm high. The low profile and
Figure 1
0805 X5R
VOUT2
CERAMIC
low board real estate that this design requires are almost impossible to
5V
D3
500 mA
match using a flyback design or a similar
B0540W
dual-output SEPIC design using a transThis dual-polarity dc/dc converter uses a single-switch buck regulator.
former instead of two inductors. Note,
however, one important limitation of this must always outweigh the negative load. similar to that of a typical single-output
circuit that makes it inappropriate for Figure 2 shows some efficiency curves at positive buck regulator. The circuit adds
some applications: For the circuit to various positive-output currents.
a secondary negative output by attaching
maintain regulation, the positive load
The dual-polarity output circuit is a coupling capacitor (C1), a second in-
112 edn | March 20, 2003
www.edn.com
design
ideas
83
750-mA POSITIVE-OUTPUT CURRENT
ductor (L2), a catch diode (D3), and an

output capacitor (C2). The negative out82
put voltage maintains regulation based
on the voltage of the coupling capacitors
remaining constant and equal to the 5V
81
output voltage. Current ramps up and
down in the secondary inductor, L2, with
80
(%)
the same peak-to-peak ripple as that of
the primary inductor, L1. The low-im79
pedance path of the coupling capacitor
provides the current to L2 during
Figure 2
the on-time of the switch and in78
duces the same voltage across L2 as appears across L1. The Schottky catch diode,
77
D3, provides a current path for the in0
200
300
400
100
500
ductor during the off-time of the switch
NEGATIVE-OUTPUT (5V) CURRENT (mA)
and a current path from the coupling caThese curves represent efficiency figures for various positive and negative output currents.
pacitor when discharging into the positive output. Current must flow from the
coupling capacitor into L1 during the off- ing into the positive inductor during the ing the losses in D1 but increasing the
time of the switch for the capacitor to off-time takes the place of some of the losses in D3.
The need for the coupling capacitor
discharge all the charge gained during the current that would normally be sourced
on-time of the switch. This current flow- from the positive catch diode, D1, reduc- to charge and discharge equally creates
edn030109di3144
Heather
114 edn | March 20, 2003
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design
ideas
500
an important limitation of the circuit:

To maintain regulation on both outputs,
the negative-supply output current
400
must always be less than the positiveMAXIMUM
supply output current (Figure 3). If the
AVAILABLE
300
negative-supply output current increasCURRENT
FROM
5V
es enough to equal the positive-supply
SUPPLY
output current, regardless of how great
(mA)
200
the positive current is, the output voltage begins to collapse. Also, if
Figure 3
the negative-supply output cur100
rent is too low (below 5 to 25 mA, depending on input voltage), the negative0
supply voltage can balloon. With
0
700
200
300
400
600
100
500
extremely light negative loads, the couPOSITIVE SUPPLY (mA)
pling-capacitor discharge current during switch off-time and the inductor This curve gives the maximum available negative-output current as a function of positive-supply
current (L2) during switch on-time current.
come only from the negative output capacitor, C2 (as opposed to both the neg- because no negative dc load is available a 25-mA preload to maintain regulaative output capacitor and the negative to discharge the capacitor. If you use this tion.
dc load). Thus, the output capacitor circuit in an application in which the Is this the best Design Idea in this
charges well past its intended voltage negative output will see light loads, use issue? Select at www.edn.com.
edn03010
Hea
www.edn.com
March 20, 2003 | edn 117
design
ideas
Temperature-measurement scheme
uses IR sensor and sigma-delta ADC
Albert OGrady and Mary McCarthy, Analog Devices, Limerick, Ireland
any noncontact temperatureEXCITATION VOLTAGE5V
measurement systems use infrared
sensors, such as thermopiles,
REF192/
which can detect small amounts of heat
AD780
AVDD
DVDD
radiation. Biomedical therF
i
g
u
r
e
1
mometers that measure the
REFIN2
CONTROLLER
temperature of an ear or a temple use
REFIN1 ()
DATA OUT
DIN
noncontact temperature measurement,
as do automotive-HVAC systems that adDATA IN
REFIN1 ()
DOUT
just temperature zones based on the
SCLK
body temperature of passengers. HouseSERIAL CLOCK
MLX90247
hold appliances and industrial processes
AD7719
OUTIR
AIN1
can also benefit from the use of nonconVSS
tact temperature measurement. Infrared
thermometers can measure objects that
OUTIR
AIN2
move, rotate, or vibrate, measuring tem26k
perature levels at which contact probes
AIN5
RSENSE
either would not work or would have a
15k
AIN6
shortened operating life. Infrared measAGND
DGND
urements do not damage or contaminate
the surface of the item being measured.
Thermal conductivity of the object being
measured presents no problem, as would
be the case with a contact temperaturemeasurement device. The circuit in Fig- Using an infrared sensor and a sigma-delta ADC, you can make noncontact temperature measureure 1 provides a design for a high-reso- ments.
lution digital thermometer that uses a
thermopile sensor and a sigma-delta ADC. The design provides high resolu- cision signal-conditioning components
tion and response times of approximate- preceding the ADC. The MLX90247D
ly 1 msec, and it eliminates the need for sensor comprises a thin, micromachined
Temperature-measurement scheme
high-performance, low-noise signal con- membrane embedded with semiconducuses IR sensor and sigma-delta ADC........65
ditioning before the ADC.
tor thermocouple junctions. The SeeThe high-accuracy, noncontact digital beck-coefficient thermocouples generate
Automotive link uses single wire ................66
temperature measurement system uses a dc voltage in response to the temperaNovel idea implements
the MLX90247D thermopile from ture differential generated between the
low-cost keyboard..........................................69
Melexis (www.melexis.com) and the hot and the cold junctions. The low therGet more power with
AD7719 high-resolution, sigma-delta mal conductivity of the membrane ala boosted triode ............................................72
ADC from Analog Devices (www.ana- lows absorbed heat to cause a higher temlog.com). The AD7719 provides differ- perature increase at the center of the
Anticipating timer switches
ential inputs and a programmable-gain membrane than at the edge, thus creatbefore you push the button ........................74
amplifier; thus, you can connect it di- ing a temperature difference that is conPublish your Design Idea in EDN. See the
rectly to the sensor, allowing the temper- verted to an electric potential by the therWhats Up section at www.edn.com.
ature-measurement system to provide moelectric effect in the thermopile
high accuracy without the need for pre- junctions. The MLX90247D also con-
www.edn.com
April 3, 2003 | edn 65
design
ideas
tains a thermistor, allowing you to configure a temperature-compensated system in relative-measurement mode.

The AD7719, a dual-channel, simultaneously converting ADC with an internal
programmable-gain amplifier is an ideal
ADC when you use it with the
MLX90247D sensor in temperaturemeasurement applications. The main
channel is 24 bits wide, and you can configure it to accept analog inputs of 20 mV
to 2.56V at update rates of 5 to 105 Hz.
The auxiliary channel contains a 16-bit
ADC and accepts full-scale analog inputs
of 1.25 or 2.5V with an update rate equal
to that of the main channel. The AD7719
accepts signals directly from the sensor;
the internal programmable-gain amplifier eliminates the need for high-accura-
cy, low-noise external-signal conditioning. The AD7719 simultaneously converts both the thermopile and the thermistor sensor outputs. The main channel
with its programmable-gain amplifier
monitors the thermopile, and the auxiliary channel monitors the thermistor.
You can use on-chip chopping and calibration schemes in optimizing the design. The AD7719 features a flexible serial interface for accessing the digital data
and allows direct interface to all controllers.
The sensitivity of the thermopile is 42
V/K; thus, it produces an output voltage
of 9.78 to 15 mV over the industrial temperature range of 40 to 85C, an output that the AD7719 can directly measure. The thermistors impedance ranges
from 15.207 k at 40C to 38.253 k

at 85C with a nominal impedance of
26 k at 25C. Again, you can directly
measure voltages from the thermistor, as
Figure 1 indicates. Biomedical thermometers generally have a measurement
range of 34 to 42C. In this range, the
thermopiles differential output is 336
V. Operating the AD7719 in its 20mV input range with a 5-Hz update rate
allows temperature measurement with a
resolution of 0.05C.

Automotive link uses single wire

Anthony Smith, Scitech, Biddenham, Bedfordshire, UK
12V
n the automotive industry, in
V
(NOMINAL)
which the goal is to produce cars with
5V
R
LED
V
simpler, lighter wiring looms, any in(TYPICAL)
43
terface that uses just one wire instead of
Q
two offers a distinct advantage.
C
Figure 1
R
10 nF
The circuit in Figure 1 imple1k
Q
TX
ments a bidirectional link using a single
R
wire, with the cars chassis or ground conR
R
MICROCONTROLLER
330k
330k
ductor providing a negative return path.
D
RX
The microcontroller communicates with
REMOTE SWITCH
R
AND INDICATOR LED
10k
the driver of the car by illuminating
Q
LED1. The driver communicates by opS
R
C
D
LED
430
erating switch S1. Detecting the switch
10 nF
0V
closure requires no current sensing: The
circuit simply exploits the fact that the
CHASSIS OR
GROUND CONDUCTOR
forward voltage drop of a properly biased
LED is usually two or three times the VBE This circuit implements a bidirectional link using a single wire and a ground return.
of a bipolar transistor. Q1, LED2, and Q2
form a semiprecision current source. Q3 across it to fairly precise and constant valWith S1 open, R6 biases Q3 on, pulling
in the receiver path detects the switch clo- ues. For example, with R3430, the the receiver pin, RX, low. RX remains low,
sure. When the microcontrollers TX pin current in LED2 is approximately 10 mA regardless of whether LED1 is on. When
goes high, Q2 illuminates LED2 and bias- with 5V at Q2s base (TX high). If you use the switch closes, the values for R4 and R6
es Q1 on. Q1 sources a constant current to a device such as the HLMP-1000 for ensure that Q3s base pulls down to apLED1 via R2 and D1.
LED2, its forward voltage remains con- proximately 150 mV (with VS5V),
LED2 constitutes an inexpensive but ef- stant at approximately 1.6V, putting ap- thereby turning off Q3 and allowing RX
fective voltage reference, which imposes proximately 0.9V across R1. The resulting to go high. As long as the switch remains
a constant voltage across current-setting 20 mA or so flowing in Q1 provides ade- closed, RX stays high, whatever the state
resistor R1. Provided that you choose R3s quate brightness for LED1 and remains of the TX pin. Powering the current
value to suit Q2s base drive, you can set acceptably constant with changes in VB or source directly from the cars battery voltthe current in LED2 and the voltage temperature.
age, VB, rather than from the microcon-
66 edn | April 3, 2003
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design
ideas
trollers supply, not only relieves the burden on the low-voltage regulator, but also
ensures that LED1 receives proper bias,
even with a very low value for VS. Thus,
provided that R3, R4, and R6 have appropriate values, the circuit functions with
VS as low as 3V or even lower. A further
advantage is that you can replace LED1
with several LEDs connected in series.
With VB12V, the current source has adequate compliance to drive four or five
LEDs.
R2 is a nonessential component, but it
reduces the power consumption in Q1. D1
provides positive overvoltage protection
for the current source, and voltage-suppressor D2 can protect against the harmful transients that systems often en-
counter in the harsh automotive environment. C2 with R4 provides a degree of

noise filtering and has negligible effect on
the switching of Q3. You may need C1 and
R5 to roll off Q2s frequency response to
avoid the possibility of high-frequency
oscillation. The transistor types are not
critical; most devices with respectable
current gain and adequate power rating
are satisfactory. LED2 provides a triple
function. As well as acting as a voltage reference for the current source, it also provides local indication of the external LED
status by illuminating in synchronism
with LED1. Additionally, it provides
open-circuit (broken-wire) indication by
turning off completely (even when TX is
high) if the connection between D1 and
the external LED breaksa feature that

may be useful for troubleshooting purposes. In the event of a broken wire, little collector current flows in Q1, and its
base-emitter junction shunts LED2; provided that R1 is much smaller than R3, the
shunt steals LED2s bias current, thereby
turning it off. Although the circuit was
developed for an automotive product,
you could easily adapt it for use in other
applications in which a simple user interface must operate on a single line.

Novel idea implements low-cost keyboard

Jean-Jacques Thevenin, Thomson Plasma, Moirans, France
any applications that use a miKEYBOARD BUTTONS
crocontroller also use a keyboard.
If your application uses a
RS
Figure 1
I/O
...
relatively powerful microcontroller, you can use several free I/O pins
BA
BB
BC
BD
C
or an unused input with an ADC to efMICROCONTROLLER
RD
RA
RB
RC
fect an easy keyboard connection. But, if
the microcontroller in your system has
...
too few free I/O pins and no on-chip
ADC, you can be in trouble. However, if
your system doesnt require a high-perThis circuit provides an inexpensive and easy way to read a small keyboard using only one I/O line
formance keyboard, you can solve the
of a microcontroller.
problem by using the circuit in Figure 1.
How does it work? At system initializathe duration of TX with the following extion, the I/O connection is an output, set whether it resets to logic 0.
5. If, after TMAX, the input I/O is still at pression: TXRXCloge(VC/VTH). If RX is
to logic 0; hence, C is discharged. In readnot negligible with respect to RXMIN (but
ing the keyboard, the following steps take logic 1, no button has been activated.
6. If within TMAX, the input I/O resets the RINPUT of the microcontroller greatly
place:
1. I/O (output) assumes the state log- to logic 0, the measured time indicates exceeds RX), then
the activated buttons.
ic 1, VOUT.
V
2. VC charges to logic 1 (VOUT) or to a

7. I/O becomes output again and resets
RX
TX R X C log e OUT
,
voltage that RS and the other resistors de- to logic 0 to discharge C.
VTH (R X + R S )
termines. (You can set the output I/O to
Several equations describe the operalogic 1 by default. In this case, you can tion of the scheme. First, assume some where VOUT is the voltage at logic 1 on the
omit steps 1 and 2, and the routine be- conditions: VOUT is the voltage of the out- I/O output. From the last equation, a
comes faster. This design uses 0 instead of put I/O at logic 1; VTH is the threshold for condition for RX is:
1 to have an inactive signal on the line logic 0 input to the microcontroller; and
VTH
RX is the value of the parallel combinawhen the keyboard is not checked.)
R XMIN > R S
.
VOUTVTH
tion of RA, RB, and the other resistors.
3. I/O becomes an input.
Figure 2 shows the timing diagram for
4. For a duration TMAX, the microcontroller checks the input I/O to see the circuit of Figure 1. You can evaluate
Note that, if RA, RB, and the other re-
www.edn.com
April 3, 2003 | edn 69
design
ideas
VC = VOUT*
Figure 2
Figure 3
VTH
DURATION TX IF BUTTONS ARE PUSHED

C IN
CHARGE
TIME
DURATION TMAX IF NO BUTTON IS PUSHED
C IN DISCHARGE WITH PUSHED BUTTONS

I/O OUTPUT
I/O OUTPUT
I/O INPUT WITH PUSHED BUTTONS
*IN FACT, IF SOME BUTTONS ARE PUSHED, VC = RX/(RX = RS) . VOUT.
The duration, TX, indicates which buttons or combinations thereof you

pushed.
sistors form an R-2R string, RXMIN is

approximately equal to RA/2. RS limits
the current from the microcontroller
and must have a minimum value of
VOUTMIN/VOUTMAX. This resistor creates a
delay for charging and discharging C of
approximately 5RSC. The following is an
These waveforms at the I/O pin and table show the returned
value (duration) with different combinations.
example of a small keyboard with four

buttons: To choose RS, IOUTMAX of the microcontroller is 25 mA at VOUT5V, so
RSMIN200. So this design uses
RS220. RA, RB, RC, and RD are 1, 2.2,
3.9, and 8.2 k, respectively. You can select values that greatly exceed RS. In this
LISTING 1THE DURATION BETWEEN TWO MEASUREMENTS
case, the effect of RS is negligible, but you

should then consider the effects of the input resistance of the microcontroller.
The duration between two measurements is approximately 2 sec (Listing
1). With one byte, the maximum duration, TMAX, is 512 sec (when no button
is pushed). So, time TX with RXMAX (in
other words, RD) must be inferior to
TMAX. Assuming that VTH is 1.5V (minimum), the equation for TX becomes
5
8200
8200 C MAX log e

1.5 (8200 + 220)
< 512 SEC C MAX < 53 nF.
So, at the beginning of each measurement, you must append a delay of

522047 nF52 sec to charge C.
Figure 3 shows the waveforms at the I/O
pin and the returned values with different button combinations. The power
consumption of the circuit, with C47
nF, VCC5V, and a keyboard reading
every 30 msec, is approximately 0.04 mW
(practically negligible). You can use this
scheme in all applications that dont require great accuracy or high speed. You
can download Listing 1 from the Web
version of this Design Idea at www.
edn.com.

70 edn | April 3, 2003
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design
ideas
Get more power with a boosted triode

Dave Cuthbert, Boise, ID
250
ven though 6L6 beampressor grid provided by two
0
power tubes have been
beam-forming plates, but you
2.5
200
around for 66 years, they
can treat the 6L6 beam-pow5
7.5
are still quite popular for use
er tube as a pentode. You can
150
10
in electric-guitar amplifiers,
think of a pentode as an nPLATE
CURRENT
12.5
and its cousin, the 6CA7
channel JFET with the fol(mA)
15
100
(EL34) power pentode, is a falowing electrode functions:
17.5
vorite among audiophiles.
Thermionic cathode:
20
50
The developers of these tubes
source of electrons (corre22.5
25
designed them for
sponds to the JFET source);
0
Figure 2
pentode-mode op Control grid: controls the
0
100
200
300
400
500
600
700
800
PLATE VOLTAGE (V)
eration, and they deliver maxcathode current; operated at
imum audio power in this The load lines for a pentode show that the plate can draw 150 mA at a
a negative potential relative to
mode. On the other hand, plate voltage of only 50V.
the cathode (corresponds to
many audiophiles prefer trithe JFET gate);
300
ode-mode operation and, un Screen grid: electrostati0
til now, had to be content with
cally screens the control grid
250
10
a 50% reduction in output
from the plate, thereby re20
200
power. This reduction means
ducing the effect that the
30
that they require larger powplate voltage has on the cath150
PLATE
40
CURRENT
er supplies and twice as many
ode current; operates at a
50
(mA) 100
expensive tubes to obtain
positive potential relative to
60
pentode power from a triode
the cathode;
70
50
80
amplifier. Figures 1a, 1b, and
Suppressor grid: prevents
0
90
1c show the 6L6
secondary electrons from
Figure 3
-50
connected as a
leaving the plate and traveling
0
100
200
300
400
500
600
700
800
pentode, a true triode, and a
to the screen grid; operates at
PLATE VOLTAGE (V)
boosted triode, respectively.
the cathode potential; and
The boosted-triode configu- A pure triode needs 200V plate voltage to draw 150 mA.
Plate: collects the elecration allows pentodes to protrons (corresponds to the
duce pentodelike power while operating The 6L6 is a beam-power tube and has JFET drain).
in a true-triode mode. To understand the cathode, control-grid, screen-grid, supFigure 2 shows the pentodes characoperation of the boosted triode, its use- pressor-grid, and plate electrodes. The teristic curves for control-grid voltages of
ful to review some vacuum-tube theory. suppressor grid is actually a virtual sup- 0 to 25V and a screen-grid voltage of
400V
400V
400V
Figure 1
6L6
6L6
1 F
6L6
1 F
1 F
100V
47k
_
47k
250V
_
14V
(a)
47k
_
32V
(b)
44V
(c)
A pentode (a) can deliver much more power than a triode (b), unless you use a boosted-triode configuration (c).
72 edn | April 3, 2003
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ideas
250V. Note the idealized load line and

that the tube can draw a plate current of
150 mA at a plate voltage of only 50V.
High voltage gain, high plate impedance,
and high output power characterize pentode-mode amplification. By connecting
the screen grid directly to the plate, you
can operate the tube in triode mode. Low
voltage gain and low output impedance
characterize this mode. Figure 3 shows
how the triode curves differ from the
pentode curves. The curves represent
control grid voltages of 0 to 90V. Note
the load line and that, in triode mode, the
TRIAD N-48X
120V AC
Amplifier
Pentode
Triode
Boosted triode
DC plate
current (mA)
75
75
75
Grid bias
(V)
14
32
44
plate cannot draw 150 mA at a plate voltage lower than 200V. This fact greatly
limits amplifier efficiency and power output. However, in spite of the limited output power, some people still prefer triode
mode because they claim it produces a
superior-sounding amplifier.
1.5k
25W
1N4007
120V AC
TABLE 1PENTODE, TRIODE, AND BOOSTED-TRIODE PARAMETERS
330 F
160V
2SC4953
100V DC
1N5378B
Figure 4
A 100V screen-grid power supply transforms a normal triode into a boosted triode.
TRIAD N-48X
120V AC
1N4007
120V AC
22O F +
250V
1.5k
20W
100V DC
40 mA
(PD=3W)
2SC4953 WITH HEAT SINK

OR SIMILAR
1N5378B
Figure 5
With a boosted triode, the plate can draw 150 mA with a plate voltage of 100V, versus 200V
for a pure triode.
Grid swing
(V)
22
64
88
Output power
(W)
11
6
10
For the boosted-triode circuit in Figure 1c, you simply add a 100V screen-toplate power supply (Figure 4) to the standard triode-amplifier circuit. This addition shifts the triode characteristic
curves 100V to the left (Figure 5). Note
the load line and that the plate can now
draw 150 mA at a plate voltage of only
100V, rather than 200V as with the puretriode-mode circuit. You can obtain significantly higher power with boosted-triode amplification and still maintain the
characteristics of triode amplification. In
Spice simulations of three single-ended
Class A audio amplifiers using MicroCap-7 evaluation software (www.spec
trum-soft.com), the control-grid bias for
a quiescent plate current is 75 mA, and
the ac grid signal is just short of amplifier clipping. The transformer ratios provide a plate-load impedance of 5 k for
the pentode and 3 k for both the triode
and the boosted triode. Table 1 details the
parameters.
Anticipating timer switches

before you push the button
Jean-Bernard Guiot, DCS AG, Allschwil, Switzerland
(Editors note: This Twilight Zone-worthy circuit will be the subject of an upcoming network sitcom, My Big Fat Anticipating Timer.)
t happens to almost everyone that
an apparatus or system should have
been turned off a moment ago. The
device in question could be the car heater,
the air conditioner, the lights...
This Design Idea offers a solution to
the challenge of turning devices on or off
74 edn | April 3, 2003
in the past. In Figure 1, IC2 is a 555-type

timer (preferably CMOS) connected as a
monostable one-shot multivibrator. The
pushbutton switch, S1, triggers IC2. You
can replace S1 with a transistor or an optocoupler, for example. You can connect
VOUT to a relay or a transistor, if needed.
You might need to adjust the values of R4
and R5, depending on the output load
and the characteristics of S1. The interval during which VOUT remains high is
T1.1RC2. In Figure 1, you replace the

resistor, R, that normally connects to C2
with the circuit inside the dashed line.
This circuit comprises a 741 op amp, IC1,
and three resistors: R1, R2, and R3. You
could replace the war-horse 741 with a
TL081 if your design needs longer time
delays.
Taking into account the usual op-amp
assumptionsequal voltage on both
inputs and zero input currentyou dewww.edn.com
design
ideas
VCC
rive the following expressions:
R2
VOV(R2R1)/R1, and VO
100
VR3IC, where VO is the op
V0
R1
amps output voltage, V is the
100k
voltage at the noninverting inR5
R4
2.2k
2.2k
put, and IC is the current
IC1
741
through R3. IC is also the current
+
GND
VCC
that charges C2.
R3
F
i
g
u
r
e
1
Combining the cited
1M
V
TRIG
DISCH
expressions, you can compute
IC2
555
IC
the value of resistor R that the
VOUT
OUT
THRESH
op-amp circuit replaces: R
V/ICR3R1/R2. The timing
RESET
CTRL
interval of this timer is thus
S1
C3
C2
C1
T1.1C2R3R1/R2. Using ap10 nF
1 F
0.1 F/
100 F
propriate values, you can ob0V
tain long time delays that you
cant attain with the basic 555 This innovative timer turns on approximately 18 minutes before you press switch S1.
circuit. But the real innovation
inherent in this circuit is that its output er supply, adjusting R1 contributes min- shown in Figure 1, the interval T is apturns on at a defined time, T, before you imal EMI and other insidious effects to proximately 18 minutes.
press S1. To adjust interval T, use a po- the op amps input. C1 is a power-suptentiometer for R1. Because the wiper of ply bypass capacitor, and C3 stabilizes the Is this the best Design Idea in this
the potentiometer connects to the pow- 555s control voltage. With the values issue? Select at www.edn.com.
76 edn | April 3, 2003
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ideas
Reset supervisor waits for stable supply

Mike Mitchell, Texas Instruments, Dallas, TX
he power-up cycle of the supply
1
voltage in embedded-system applicaR4
tions is sometimes not a clean event.
1k
This fact holds especially true in batteryR1
2
operated systems, because the insertion
150k
+ TLV3491 4
of a battery often causes significant ringRESET
ing or glitching on the supply line (Fig3

MSP430
MICROCONTROLLER
ure 1). In products with on-off switches,
R2 46k
the contact bounce of the switch can
C1
cause an unclean power-up. A power-up
0.1 F
cycle such as the one in Figure 1 can ofR3 1M
ten cause a processor to enter a brownout
condition. This condition constiFigure 2
tutes an errant condition of the
processor, which requires a reset to take
place before the processor behaves as ex- This circuit resets a processor based on the stabilization time of the supply voltage.
pected. The processor is often lost or
in the weeds during a brownout con- of the supply voltage and not on
dition. Usually, a reset supervisor con- a predetermined value.
trols the reset line to the processor and
The circuit uses a TLV3491
thus avoids the brownout condition. Tra- from Texas Instruments
Figure 1
ditional supply-voltage-supervisor cir- (www.ti.com). The comcuits hold the processor in reset until the parator draws approximately 1
supply voltage reaches a predetermined A and operates from 1.8 to 5.5V,
value. They also reset the processor if the making it well-adapted to batteryvoltage dips below the predetermined operated applications. The input
value. However, the level at which the SVS to the minus terminal is a simple
operates often does not suit the system. resistor divider. The resistor valFor example, the level may be lower than ues should be relatively high to rethe minimum operating voltage of the duce the power consumption of
processor, or it may be higher than the the circuit. The input to the plus
desired operating voltage of the system. terminal is basically an RC circuit.
The reset circuit in Figure 2 provides a re- The RC time constant provides a Insertion of a battery supply often results in glitching
set to the processor based on stabilization tunable power-up delay. When and ringing.
you apply power or insert a batReset supervisor waits
tery, the output of the comparator is low, supply stabilization. By selecting R1, C1,
for stable supply ............................................91
holding the processor in the reset condi- R2, and R3, you can guarantee a reliable
tion. The plus input of the comparator reset signal to the processor for a given
Small circuit forms programmable
becomes higher than the minus input dV/dt for VCC. The equations for the volt4- to 20-mA transmitter ................................92
only after the supply voltage stabilizes, re- ages at the comparators inputs are:
High-side current sensor monitors
sulting in a high output state and thus ret
negative rail ....................................................96
leasing the processor for operation. The
+
R1C1
V = VCCVCC e
;
stabilization time for the supply voltage
Transconductance amp gives
depends on the RC-network component
oscillator reciprocal response......................98
R3
V = VCC
.
values. Here, the use of low-value resisPublish your Design Idea in EDN. See the
R2 + R3
tors carries no penalty, because no curWhats Up section at www.edn.com.
To hold the processor in reset, you
rent flows through the RC network after
www.edn.com
April 17, 2003 | edn 91
design
ideas
need the condition VV. That condition yields:

t
R3
> VCCVCC e R1C1 .
R2 + R3
Solving for t, you obtain
VCC
R2
t <R1C1 ln
.
R 2 + R 3
From the last equation, you can calculate the amount of time the processor stays
in reset. Therefore, as long as the supply
ramps to a steady state in a shorter time,
youre guaranteed a reliable reset. The reverse-biased diode and resistor R4 provide
a faster discharge path for the capacitor.
This fast discharge allows the circuit to
quickly react to negative glitches in the
supply voltage during normal operation,
in which it may be desirable to reset the
processor. R4 allows you to tune the response time of the circuit for any expected supply-voltage glitches. Removal of the
resistor yields the fastest response time to
supply-voltage glitches but may result in
undesired resets for the processor. The
pullup resistor at the output of the

comparator is necessary because
of the comparators open-drain
output. The capacitor at the comparators output smoothes any fast
switching the comparator
Figure 3
may encounter.
The current consumption of
the circuit in Figure 2 is approximately 1 A (the current consumption of the comparator)
plus the current through R2 and
R3. The circuit costs less than
many dedicated supply-voltage
supervisors. Figure 3 illustrates
the performance of the circuit.
Figure 3 is a scope capture of the
The circuit in Figure 2 enables the processor well
same battery insertion of Figure
after the stabilization of the power-supply voltage.
1. The top trace is the supply voltage; the next trace is the positive input to supply stabilizes. Thus, the perfomance
the comparator. The negative input to the depends not on any predefined supplycomparator is the next trace, and the bot- voltage level, but rather on stabilization
tom trace is the comparators output time.
(connected to the microcontrollers reset pin). You can clearly see that the cir- Is this the best Design Idea in this
cuit holds the processor in reset until the issue? Select at www.edn.com.
Small circuit forms programmable

4- to 20-mA transmitter
Alan Li and Jeritt Kent, Analog Devices, Bellevue, WA
ne of the key challenges in the design of 4- to 20-mA current transmitters is the voltage-to-current
conversion stage. Conventional transmitters use multiple op amps and transistors to perform the conversion function. These approaches have been around
for a long time, but they are usually inflexible, have poor power efficiency, and
have limited current compliance. An improved Howland current pump, on the
other hand, can be cost-effective, because
it addresses the cited problems. In addition, it closely models an ideal current
source with the potential for nearly infinite output impedance. Figure 1 shows
the improved Howland-current-pump
topology, implemented with a high-resolution DAC, a precision reference, and a
high-current op amp. Analyzing the circuit in Figure 1 (neglecting the loading
effects at the output of IC3), the voltage
at VX is VX(VREFD)/2N, where D is the
92 edn | April 17, 2003
decimal equivalent of the DACs digital

code and N is the number of bits.
Analyzing nodes VL and VN, you obtain
IL =
VOUTVL
VL
.
R 3
R1 + R 2
VNVX VOUTVN
=
.
R1
R2 + R3
(1)
(2)
Because VN and VP are virtually shorted,

you obtain
VN =
R1
VL .
R1 + R 2
(3)
Substituting VN and VOUT, IL becomes

(R 2 + R 3 )/ R1
VX +
R 3
(4)
(R1R 2R1R 2 ) + (R1R 3R1R 3 )
VL .
R1R 3 (R1 + R 2 )
IL =
Making R1R1, R2R2, and R3R3

simplifies Equation 4 to
IL =
(R 2 + R 3 )/ R1 VREF D
.
R 3
2N
(5)
According to Equation 5, you can use

R3 to set the circuits sensitivity. You can
make R3 as small as necessary to achieve
the desired current and improve the load
range. As an alternative, you can make the
other resistors large to keep the quiescent
current low for high power efficiency.
The improved Howland current pump is
flexible. It offers both current-sink and
-source capability. The input voltage at
VX is polarity-insensitive; you can apply
it to either R1 or R1. You can connect the
load to the supply rail as a high-side load,
or you can refer it to a low-side supply or
ground (Figure 1). Further, one of the
primary advantages of this topology is
that the current pump provides potenwww.edn.com
design
ideas
15V
15V
5V
RF
VIN
VDD
IO
IC1 VOUT
ADR01
VREF
10V
IC2
AD5544
VREF
IO
_
IC3
AD8512
V+
VX
R1
150k
R2
15k
VN
R3
50
C1
10 pF
GND
GND
_
15V
_
IC4
AD8512
DIGITAL INPUT
Figure 1
CODE 20 TO 100% FULL SCALE
VOUT
+
R1
150k
R3
50
R2
15k
VL
VP
RL
500
IL
4 TO 20 mA
An improved Howland current pump forms the heart of this precision 4- to 20-mA transmitter.
tially infinite output impedance, like that

of an ideal current source. However, you
must pay strict attention to resistor
matching. You can see the importance of
matching by examining the circuits output impedance. If you ground all inputs
and apply a test voltage at VL, you can see
that
the open-loop response at a slope (rate of requirements. Note that optimum comclosure) equal to or greater than 40 dB pensation attempts to balance the fact
per decade and the open-loop gain at the that a small C1 cannot compensate for all
intersection exceeds unity, then the cir- possible causes of oscillation, whereas
cuit is likely to be unstable. The circuit large values of C1 could adversely affect
may ring, show gain peaking, or condi- the settling time of any DAC. Consider
tionally oscillate after a step function in the following design objectives: 16-bit
programmability, four channels, small
the DAC adjustment.
form factor, a maximum ground-referred
An
effective
approach
to
the
stability
(6)
V(t)
R1R 3 (R1 + R 2 )
=
. problem is to insert a pole into the noise- load of 500 with 10V compliance, 90%
Z OUT =
I(t) R1 (R 2 + R 3 )R1(R 2 + R 3 ) gain transfer function by adding a com- minimum efficiency, and 50-mW maxiEquation 6 shows that, if the resistors pensation capacitor, C1. This capacitor mum dissipation from each resistor.
are perfectly matched, ZOUT is infinite. In- creates a pole to keep the rate of closure
Given the requirements of small form
finite output impedance is a desirable at 20 dB per decade. Optimum compen- factor and high precision, the design in
characteristic of a current source because sation occurs when R1CPARASITIC R2C1. Figure 1 uses IC2, the a 16-bit currentthe resistance of the load does not affect Because CPARASITIC is unknown, you output AD5544 DAC, with an external op
the current flowing in the load. On the should determine C1 empirically to ob- amp instead of a voltage-output DAC.
other hand, if the resistors are not tain optimum results. In general, C1 in You face some important trade-offs in
matched, ZOUT can be either positive or the range of some tenths of a picofarad to deciding whether to use a current-output
negative. Negative ZOUT causes instabili- a few picofarads satisfies compensation or a voltage-output DAC. Current-outty because of the existence of
put devices typically cost less
5
a right-half-plane pole in the
than voltage-output DACs.
RL=500.
s-plane domain. Any amount
The design must convert the
IL=0 TO 20 mA.
4
of parasitic capacitance
current to a voltage to run the
from poor pc-board layout,
current pump, and the exter3
op-amp differential capacinal op amp determines the acINTEGRAL
tance, or bothat the invertcuracy of this conversion.
NONLINEARITY 2
(LSBs)
ing node of IC4 could cause
Thus, you have control of the
1
instability or worse. These
amount of accuracy as your
parasitics, along with
application requires. Voltage25C
Figure 2
0
70C
R1, introduce a zero
output DACs generally cost
into the noise-gain transfer
more than current-output de1
0 8192 16,384 24,576 32,768 40,960 49,152 57,344 65,536
function, resulting in a slope
vices because the current-toCODE (DECIMAL)
of 20 dB per decade. If the
voltage conversion takes place
noise-gain transfer function Integral-nonlinearity errors from the circuit in Figure 1 dont exceed 4
in the package, entailing the
of the amplifier intersects with LSBs at 16-bit resolution.
inclusion of an op amp. Al-
94 edn | April 17, 2003
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design
ideas
though a voltage-output DAC reduces

component count in this design, you have
to accept a particular accuracy figure
based on the specifications of the op-amp
buffer inside the DAC. Both approaches
typically require an external reference. In
the end, a current-output approach
yields the highest accuracy at comparable cost and board space.
Although IC3, which performs the current-to-voltage conversion, can be almost
any precision op amp using 15V supplies, IC4 requires adequate current-driving capability to handle the maximum
20-mA load. The improved Howland
current pump is insensitive to load-resistance perturbations. Only IC4s supply
voltages limit the compliance voltage. A
500 load, for example, can place VL as
high as 10V at 20-mA load current. This
scenario sets VOUT at 11V, requiring the
op amp to swing within 4V of the positive rail. The AD8512 dual op amp can
drive 20 mA into a 500 load using
15V supplies. However, IC4s outputvoltage swing is likely to limit resistive
loads to 500 in this application. This
design uses the 10V ADR01 reference because it is precise and compact.
To minimize the power in the resistors,
you start with R350. R3 is in the direct load-current path, and it carries just
slightly more current than the load, assuming R2R1RL. At the 20-mA
peak current, the power dissipation is just
above 20 mW. With the limited headroom between the supply and the compliance voltages, you should scale the ratio between R2 and R3 such that the
additional gain does not saturate IC4. As
a result, you should choose R2 to be 10
times smaller than R1. Using Equation 5
and the resistance-matching criteria, you

obtain the following values: R1R1150
k; R2R215 k, and R3R350.
Its desirable to add a 1- to 10-pF capacitor, C1, to the negative-feedback path to
avoid possible oscillation arising from
eventual resistor mismatch.
A 16-bit, programmable, 4- to 20-mA
current transmitter theoretically has 0.3A resolution. The actual measured performance of the circuit in Figure 1 shows
that the worst-case integral-nonlinearity
error is approximately 4 LSBs. This error
is equivalent to 1.2 A, or 0.006% total
system error, well within most systems
requirements. Figure 2 shows the measured results at 25 and 70C.
High-side current sensor monitors negative rail

Ken Yang, Maxim Integrated Products, Sunnyvale, CA
ll dedicated current-sense amplifiers provide high-side sensing on a
positive supply, but you can adapt
such circuits for monitoring a negative
supply (Figure 1). The positive-supply
pin, V, connects to the systems positive
supply, and the ground pin, GND, connects to the negative supply, VEE. That
arrangement monitors the negative supply and provides a positive output voltage for the external interfacetypically,
an A/D converter. The RS pin of the
current-sense amplifier, IC1, connects to

the load, and the RS pin connects to the
negative supply. IC1s current-source output drives a current that is proportional
to load current flowing to ground, not to
the GND pin. Output resistor ROUT converts the current to a voltage, which an
optional ADC then digitizes.
Saturation in the internal transistors,
which occurs at approximately ((V)
1.2V), limits the maximum output voltage. Thus, V must exceed the full-scale
output by at least 1.2V. If, for instance,

the full-scale output is 1V, then
V2.2V. To meet the devices maximum and minimum operating voltages,
0VEE(32V), and ((V)
VEE))3V. Figure 2 shows the variation
of current measurement accuracy with
load current.
RS
0.2
0
VEE
(32VV+) TO 1V
RS=0.2, ROUT=500,
V+=3.3V, VEE= 5V.
_
2
5
8
V+
2.2 TO 5V
RS
RS+
1
LOAD
GND
V+
IC1
MAX4172
A/D
CONVERTER
+
_
OUT
SENSING 2
ERROR
(%)
3
4
5
0
ROUT
Figure 1
Connecting this positive-supply monitor allows it to monitor a negative current
and generate a positive output voltage for the ADC.
96 edn | April 17, 2003
0.2
0.6
0.4
LOAD CURRENT (A)
0.8
Figure 2
The current-sensing error of the circuit in Figure 1 varies with
load current.
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design
ideas
Transconductance amp gives

oscillator reciprocal response
Mike Irwin, Shawville, PQ, Canada
he circuit in Figure 1 is a variation
on the familiar integrator/comparator triangle-wave oscillator, which
you typically implement with two op
+
amps. An integrator and a comparator
HYSTERETIC
_
COMPARATOR
connect in a positive-feedback loop; the
RATE
_
comparator drives the integrator
+
Figure 1
and vice versa. A fixed amount of
INTEGRATOR
hysteresis exists in the comparator, producing a triangle wave at the integrators This circuit is a classic triangle-wave generator, using an integrator and a comparator with
output. The wave oscillates between the hysteresis.
fixed threshold voltages. You can vary the
oscillation rate using a potentiometer to variable. An OTA (operational transcon- age; in other words, the oscillator has a
set the integrators gain and thus obtain ductance amplifier), IC2, sets the hystere- 1/x response. Such an oscillator is useful
a constant-amplitude, variable-frequen- sis, producing an oscillator in which the in A/D-converter applications and for
cy, triangle-wave output. In the circuit of period is a linear function of an externally clocking time-delay systems, such as auFigure 2, the integrators gain is fixed, applied voltage. The oscillation rate is in- dio-delay lines.
In Figure 2, R3 and the 15V output
whereas the comparators hysteresis is versely proportional to the control voltof comparator IC3A fix the
RIN =P1+R1=20 k, NOMINAL.
integrator current at 20
CONTROL
A. The integrator proP1
R1
VOLTAGE
VIN
duces a triangle of fixed
17.4k
5k
0 TO 10V
OFFSET
200V/sec slope, and the
TRIM
OP07
Q1
2 _
P2
peak amplitude is a funcFULL-SCALE
6
1OOk
TRIM
IC1
tion of the hysteresis. OTA
15V
15V
+
IC2 provides voltage con3
2N5087
trol of the hysteresis. With
R11
C1
increasing VIN, the hystereR10
0.1 F
4.7k
sis and triangle-wave peak1.5M
to-peak amplitude inIABC
R3
750k
R2
15
crease, consequently in3
2 _
IC4
20k
6
creasing the oscillator periAD843
IC2
CA3140
13
od, T. The triangle waves
+
+
16
3
CA3280
amplitude changes from
approximately 1 mV p-p to
15V
a maximum of 20V p-p as
VIN varies from 0 to 10V.
R
R5
6
R8
R9
With
the same VIN span, the
1.2M
1k
220
220
period increases from 20
sec to 200 msec. IC1 and
15V
Q1 form a linear voltageR7
R4
controlled current source
45.3k
1k
R13
that supplies bias current,
Figure 2
3
4.7k
+
R12
IABC, to the OTA. The curBUFFERED
1
6 _
IC3A
OUTPUT
rent
IABCVIN/RIN. You can
7
2 _
2.2k
IC3B
15V
LM393
increases from
15V see that I
ABC
+
5
LM393
0
to
0.5
mA
as VIN varies
15V
15V
from 0 to 10V. The OTA is a
switched-current generator, producing a bidirecThis VCO uses an OTA and a hysteretic comparator to deliver a reciprocal (1/x) response to the control voltage.
98 edn | April 17, 2003
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design
ideas
tional output current approximately

equal in amplitude to IABC, when it receives drive from the comparators opencollector output.
The OTA sources current when the
comparators output is 15V and sinks an
identical current when the output is
15V. Pullup resistors R4 and R5, along
with resistors R6 through R9, provide a
symmetrical 70-mV drive to the OTAs
noninverting input. The high-compliance output of the OTA provides hysteresis by translating the voltage at the
comparators noninverting input up and
down by the amount R2IABCR2VIN/RIN.
The resulting threshold voltages are symmetrical around the comparators input
offset voltage. This symmetry reduces the
effect of offset voltage on the oscillators
period. This design uses an LM393 comparator for its relatively low maximum
bias current of 25 nA. The comparators
output changes state when the integrators output begins to exceed the thresh-
100 edn | April 17, 2003
old voltage set by hysteresis, reversing the

direction of the OTAs output current
and the threshold polarity. This action
makes the integrators slope reverse and
initiates the next half-cycle.
You can calculate the oscillators period as follows:
=
4I ABC R 2C 4(VIN / R IN )R
R 2C
=
.
IINT
VSUPPLY / R 3
For the given component values,

4(VIN / 20 k)(20 k) 107
=
15V / 750 k
0.02 VIN (SEC).
50
RATE =
(Hz).
VIN
=
Potentiometer P1 sets the full-scale period for VIN10V, and P2 nulls the OTAs
input offset voltage to optimize the performance at small values of VIN. With the
component values shown, the circuit
covers a three-decade range from 200

sec to 200 msec with lower than 1%
linearity error. The error increases to 2%
for T100 sec. With a 10-nF integrator capacitor, the circuit oscillates at frequencies as high as approximately 150
kHz (T6.7 sec). The CA3280 OTA
provides the best performance in this
circuit, thanks to its excellent offset specifications. Using the CA3080 and
LM13600 in the circuit reduces performance. The integrator op amp should
have low input-bias current and highspeed response to minimize ringing on
triangle peaks. The AD843 and CA3140
both work well. You could add temperature compensation by including a thermistor in the OTAs input-attenuator circuit. Finally, note that you should use
polystyrene or polypropylene capacitors
in the integrator.
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Buck IC boosts battery voltage for white LED

Robert Kollman, Texas Instruments, Dallas, TX
hite-light LEDs are finding
their way into many markets that
incandescent bulbs once served.
Flashlights are among the newer applications in which reliability, ruggedness, and
ability to control the power draw of the
LEDs make these devices attractive. With
incandescent bulbs, the power management for the device is a simple on-off
switch. However, the LEDs cannot operate directly from the two cells you typi-
cally find in most flash100

NO CURRENT SENSE
lights, because their re95
quired voltage is 2.8 to
90
4V, compared with a
85
EFFICIENCY
battery voltage of 1.8 to
AT 350 mA 80
3V. The power manageCURRENT SENSE
(%)
75
ment has a further com70
plication because the
65
light output of the LED
60
relates to curFigure 2
1.5
2
2.5
3
3.5
rent, and the
INPUT VOLTAGE (V)
LEDs characteristics are
Resistive current sensing has an adverse effect on the efficienextremely nonlinear
cy of the circuit in Figure 1.
with voltage. One approach to this problem
is to boost the power supply with a cur- by turning on the high switch, thereby
rent limit. A number of devices for LED connecting the battery voltage across inapplications are available; however, their ductor L1. Once inductor L1 stores sufficurrent ratings are typically too low for cient energy, the high-side switch turns
the 1 to 5W that flashlight applications off. The inductor current drives the
switching node negative, and energy
need.
Figure 1 presents an alternative to the transfers through the low side into outtypical boost power regulator. A buck- put capacitor C1, creating an essentially
converter IC, IC1, generates the higher lossless switching event. Also, because the
voltage that the white-light LED needs. high- and low-side switches are MOSAn internal buck power stage connects FETs, voltage drop is lower than that of a
between VIN and PGND, sourcing cur- diode implementation; therefore, effirent to output Pin L. This circuit operates ciency can be high. The converter IC
Buck IC boosts battery voltage

for white LED ..................................................63
Switched-capacitor IC and reference
form elegant 48 to10V converter ....64
Buck converter handles
battery-backup system..................................66
Circuit disconnects load
from low-voltage supply ..............................68
Circuit forms gamma-photon detector ....70
Circuit ensures safety
in power-on operation..................................72
Figure 1
2
3
0.1 F
4
5
VIN
PGND
FC
GND
PG
FB
IC1
TPS6200X
EN
SYNC
ILIM
10
L1
10 H
9
BP1
BH2AAPC
8
C1
10 F
16V
100
OPEN175 mA.
SHORT350 mA.
6
2
10k
1 F
10 F
16V
2.7
2.7
A buck-converter IC is a good choice for boosting voltages for white-LED drive.

www.edn.com
April 24, 2003 | edn 63
design
ideas
monitors the current through the LED

via a current-sense resistor and compares
the current-sense voltage with an internal 0.45V reference within the converter
IC to achieve regulation. Current and,
therefore, illumination are functions of
the current-sense resistor voltage. Although the internal reference voltage of
the IC is lower than that of most other
ICs, it does cause an appreciable power
loss. With the LED voltage of 2.8 to 4V, it
degrades efficiency by 10 to 14%. Reducing the resistors value and using an amplifier to sense the current at a lower voltage could reduce this loss.
Figure 2 shows load-current regulation and boost voltage at a 350-mA cur-
rent setpoint. Efficiency is 80% or better over the normal battery-voltage range
but falls as battery voltage drops to endof-life values. Also, the figure shows the
impact of the resistive-current sensing.
At high input voltages, the efficiency approaches 95%, and, at low input voltages,
it falls to 80%. The trend for the curves
stems from two interrelated effects: At
high input voltage, input current and,
hence, switch current are low. Therefore,
conduction and switching losses are low.
Second, much like an autotransformer,
the boost power stage does not handle the
total output power. The amount of power that the power stage handles relates to
the boost voltage, or the difference be-
tween the input voltage and the LED voltage. In this design, the LED voltage is approximately 3.7V, so that at high line of
3.2V, the power stage handles only 13%
((3.73.2)/3.7) of the power. At low line,
in which the currents are much higher,
the power stage handles almost four
times as much, or 50%, of the power. Although a buck controller is not an obvious choice for this application, it provides
low-cost, low-input-voltage operation
and good efficiency over a wide inputvoltage variation.
Switched-capacitor IC and reference form

elegant 48 to 10V converter
Wallace Ly, National Semiconductor, Santa Clara, CA
system designer must almost always face a trade-off in choosing the
right part for an applicaFigure
tion. The trade-off usually involves performance, price, and function.
An example is the issue of powering circuits from a telecom-voltage source. Telecom systems almost exclusively use highpotential negative rails, such as 48V.
Digital circuits typically in use in such applications usually operate from a bricktype power supply. However, analog circuits rarely require enough power to
justify using a costly brick. At the heart of
these bricks is nothing more than a specialized switching converter in tandem
with an isolated flyback-transformer coil.
But some applications neither require nor
can tolerate the use of a coil-based approach. Figure 1 depicts a way to address
the problem. The circuit provides a small
amount of power to analog/digital circuits, such as the LMH6672 DSL op amp.
The LMV431 voltage reference, along
with the voltage-setting resistors sets the
output voltage to approximately (11
k/280)1.24V5.7V. This output
voltage then goes to the base of Q1, the
2N2222 transistor. The configuration of
the transistor causes a VBE drop of approximately 0.7V, resulting in a net volt-
64 edn | April 24, 2003
R3
10k
Q1
N2222
R2
1k
VIN
C1
GND
LMV431
C1
3.3 uF
3.3 F
C1+
R1
280
C2
VOUT
C2
3.3 uF
C2+
FUSE
INPUT 48V
LM2682
OUTPUT 10V
This simple circuit provides a 10V power source from 48V telecom power rails.
age of 5V for the next stage. The purpose

of the transistor is to provide additional
current to the LM2682 switched-capacitor converter. Note that the converter has
a 5V reference (GND pin). Small capacitors C1 and C2 enable the pumping
and inverting action required to convert
the 5V to 10V. Furthermore, the MSO8 package of the LM2682 and the SOT-23-
3 package of the LMV431 allow the circuit

to consume little board space. In roughly
the size of a small transformer, the proposed circuit does an elegant job of powering low-power circuits from a negative
high-voltage source.
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design
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Buck converter handles battery-backup system

Haresh Patel, Linear Technology Corp, Milpitas, CA
synchronous buck converter is inherently bidirectional. That is, it
transfers energy from input to output as a buck regulator when the output
voltage is low, but, when the output voltage is high, the converter acts as a boost
regulator, transferring power from output to input. This Design Idea shows how
to use this bidirectional energy transfer
to automatically recharge a battery when
the main 5V supply is available in a battery-backed 5V system. The circuit in
Figure 1 provides as much as 7A current
inductor current and the boost function

by turning off the bottom MOSFET.
Figure 2 shows a 5V power supply
backed up by a battery-powered, LTC3778-controlled power supply. The synchronous, bidirectional LTC3778 buck
circuit acts as a battery-to-5V converter
if the main 5V supply is off and as a battery charger when the 5V supply is alive.
As Figure 1 shows, in the charging mode,
the circuit regulates the battery current
by sensing the charge current through R1
by means of an LT1787 current-sense
at 5V output set at 4.8V and recharges a

12V sealed lead-acid battery with a current as high as 2A. The basic concept is
that the ITH-pin voltage of the LTC3778
controls the L1 inductor current, or the
valley level. Above approximately 0.7V at
the ITH pin, the net inductor current is
positive from input to output. Below that
level, the inductor current becomes increasingly negative, resulting in a boost
function that transfers energy from output to input. When the FCB pin of the
LTC3778 is high, the IC inhibits negative
VIN
R1 0.02
2W
5VOUT
SHDWN
ICI
LTC3778EF
RUN/SS
BOOST
0.01 F
1k
Figure 1
4.75k
200
Vin
330k
VON
TG
PGOOD
SW
VRNG
SENSE+
ITH
SENSE
FCB
PGND
SGND
1 nF
12.1k
0.1 F
LT1460GCZ
IC4
VIN
VOUT
VIN
GND
1 F
0.1 F 12
13
0.1 F
LTC1639
+
14
IC
3D
FIL+
VS+
VBIAS
VOUT
FIL
VS
DNC
VEE
IC2
LT1787
470 F
6.3V
0.01 F
VBATT
OR1
1
0.005
1 F
12V
10k
PWR_
_GOOD
4.7 F
SYS
SV
P/S
10 F
25V
100k
5 + LTC1639
7
6 IC3B
LTC1639
10
+
8
9 IC3C
+ IC
LTC1639
1
3A
23.2k
100k
100k 100k
75 pF
1M
100
100k
3
13.7k
0.01 F
+180 F
20V
10 F
25V
L1
(4.8V)
7.2 F 8A 5V
OUT
B340
INTVCC
EXTVCC
Q1
Q2
DRVCC
38.3k
5VOUT
0.22 F
BG
ION
VFB
INTVCC
CIN1,2
CMDSH1
0.01 F
0.068 F
1M
24.9k
24.9k
1N4148
22 pF
1.1k
383
VBATT
51k
51k
8.2V
100k
_GOOD
PWR_
20k
2N3904
SHDWN
Q3
Q5
2N7002
Q6
2N7002
Q4
2N7002
NOTES:
Q1 AND Q2: SI488DY.
L1 SUMIDA CDEP1304 (H) - 7R2.
CIN1 AND CIN2: SANYO 20SP180M.
This bidirectional converter automatically recharges a battery when the 5V main supply is active.
66 edn | April 24, 2003
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design
ideas
POWER GOOD
amplifier, IC2. An error ampliply to change the reference voltAC
fier, IC3B and IC3C, compares
age to the desired value when
5V
5V BUS
the current-sense signal with
the power-good signal is low.
a reference voltage from the
Q3 through Q6 prevent low-battery discharge by shutting
LT1460GCZ, IC4, and drives
LOAD
LOAD
the ITH pin of IC1. When the
down IC1 when the battery
LTC3778
ITH-pin voltage falls lower
voltage is low and the powerthan approximately 0.7V, the
good signal from the main supcircuit forces the average inply is inactive. You could imductor current to a negplement more sophisticated
Figure 2
ative value, causing recharging algorithms using a
verse power flow from the The battery charges when the 5V main supply is alive and provides
system microcontroller or anaoutput to the input of the 5V power when the main supply goes down.
log circuitry that sets the charge
LTC3778, thereby charging
current as a function of battery
the battery. The lower the voltage at the senses the output-voltage drop to 4.8V voltage. You can implement float chargand drives the ITH pin to maintain the ing by reducing the charge current to apITH pin, the higher the charge current.
At the beginning of the charge cycle, output voltage at 4.8V. The recharging proximately 100 mA when the battery is
a constant current charges the battery. resumes when the systems 5V power re- nearly fully charged. A gradually tapering
When the battery voltage reaches 13.8V, turns and the 5V bus goes higher than charge current can mimic constant-voltIC3D pulls the FCB pin of IC1 high, there- 4.8V. In this scheme, the main supply age charging as a alternative to pulse
by not allowing Q2 to turn on. So, the voltage must be slightly higher than the charging. The circuit can use a three-cell
circuit inhibits boost mode regardless of backup-supply voltage for proper (in series) lithium-ion battery if you set
the level at the ITH pin. The interrup- switchover. Approximately 100 to 200 the maximum voltage to 12.6V.
tion in charging current causes the bat- mV should be adequate to prevent untery voltage to drop below 13.2V to necessary mode switching attributable
restart charging. This action results in to ripple.
pulse charging with the pulse frequenIf the lower voltage in the backup
cy gradually decreasing until the battery mode is objectionable, then you can use Is this the best Design Idea in this
fully charges. In the backup mode, IC3A a power-good signal from the main sup- issue? Select at www.edn.com.
Circuit disconnects load from low-voltage supply

Steve Caldwell, Maxim Integrated Products, Chandler, AZ
of approximately 2VCC,
ower supplies often inVGS = 2.7V OR LESS.
clude a circuit that disconwhich provides a gate-source
1.5V
nects the load when the supvoltage adequate to keep the
ply voltage drops too low, such as
MOSFET on. When the
100k
RL
when a battery is nearly
monitored voltage drops beFigure 1
VCC 3
discharged. A p-chanlow the threshold of the sunel MOSFET connected between
pervisor, its reset output goes
2 IN 5 SHDN
IC2
2
supply and load is the typical apup to VCC and turns off the
6
MAX6327XR26-T
RESET
MOSFET. The supervisor has
proach. However, a 1.5V singleOUT
IC1
1 F
a threshold of 2.6V. Because
cell battery or other low-voltage
GND
1
MAX1697
1
the voltage it detects is twice
supply is insufficient to fully turn
3
the supply voltage, this ciron the MOSFET. For such low4 GND
cuit disconnects the load
voltage systems, consider the cir1 F
when the supply voltage
cuit of Figure 1. A small invertdrops below 1.3V, making it
ing charge pump, IC1, generates a This low-voltage circuit disconnects the load when the supply voltage
negative voltage approximately drops below a predetermined threshold of 1.3V in this case.
suitable for use with a typiequal to the input supply, VCC.
cal 1.5V battery. Other inThat voltage connects to the ground ter- pins. As long as this difference is greater ternal threshold voltages are available.
minal of a microprocessor supervisor, than the supervisors internal trip-voltIC2, which monitors the voltage differ- age threshold, the reset output voltage as- Is this the best Design Idea in this
ence between its own VCC and ground sumes the charge-pump output voltage issue? Select at www.edn.com.
68 edn | April 24, 2003
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Circuit forms gamma-photon detector

Bruce Denmark, Maxim Integrated Products, Sunnyvale, CA
C1
he circuit of Fig12V
4.7 pF
ure 1 includes a
PIN photodiode
1M
100 pF
R2
that detects individual
10M
100 pF
photons of gamma ra10k
0.1 F
5V
diation. The reverse
R1
10k
10M
5V
bias on the photodiode
0.1 F
0.01 F
8
2
1000
pF
sometimes creates a de
1k
1
0.1 F
6
0.01 F
8
3
pletion region. When
2
7
IC1A
+
1
5
4
+
IC1B
MAX4477
1k
such a photon strikes
3 +
IC2A
MAX4477
PIN
4
this depletion region, a
MAX4477
DIODE
GAMMA
small amount of charge
RADIATION
develops. This charge is
100 pF
proportional to the
5V
TEST POINT 1
10k
photons ener5V
Figure 1
gy. Four ampli0.01 F 1k
100k
0.1 F
6
2
fiers following the PIN
4
7
1
5
+
IC2B
VOUT
photodiode amplify
3 +
IC3
0.1 F
MAX4477
5
and filter the resulting
MAX987
10k
signal. A final comparator distinguishes be0.1 F
tween the signal and
150k
the noise. Thus, the
comparators output
pulses high each time a When a single gamma photon with sufficient energy strikes the PIN photodiode in this circuit, the output of the comgamma photon with parator pulses high.
sufficient energy strikes
the photodiode. Small signal levels make in Figure 1 includes the QSE773 PIN tal capacitance at the op amps inverting
this design an interesting challenge. The photodiode from Fairchild (www.fair node. That capacitance includes the PINdesign requires very-low-noise circuitry childsemi.com). Though readily available photodiode capacitance; the op-amp inbecause the individual gamma photons and inexpensive, it is probably not the put capacitance; and the feedback capacgenerate a small amount of charge and optimal choice. Certain PIN diodes from itance, C1. Thus, to minimize circuit
because lowering the overall noise level Hamamatsu (www.hamamatsu.com) can noise, minimize the op amps input-voltallows the circuit to detect lower energy work nicely in this application. Choosing age noise. The op amp in this circuit,
gamma photons.You must pay special at- a detector with 25- to 50-pF capacitance IC1A, a MAX4477, well suits this design.
tention to the first stage, which is the with reverse bias applied provides a fair It has negligible input-current noise and
most noise-critical.
compromise between sensitivity and low input-voltage noise of 3.5 to 4.5
nV/Hz at the critical frequencies of 10
The most critical component is the noise.
PIN photodiode, whose selection often
Important considerations for the first- to 200 kHz. Its input capacitance is 10 pF.
R1 and R2 contribute equally to noise
involves conflicting considerations. De- stage op amp include input-voltage noise,
tector sensitivity (the number of photons input-current noise, and input capaci- because they are directly in the signal
detected for a given radiation field), for tance. Input-current noise is directly in path. Resistor-current noise is inversely
example, depends on the size of the de- the signal path, so the op amp should proportional to the square root of the repletion region, which in turn depends on keep that parameter to a minimum. sistance, so use as large a resistance value
the area of the diode and the reverse bias JFET- or CMOS-input op amps are a as the circuit can tolerate. Keep in mind,
applied to the diode. To maximize sensi- must. Also, if possible, the op amps input though, that leakage current from the
tivity, therefore, you should choose a capacitance should be smaller than that PIN diode and first-stage op amp place a
large-area detector with high reverse bias. of the PIN photodiode. If you use a high- practical limit on how large the resistance
Large-area detectors tend to have high ca- quality PIN photodiode and an op amp can be. The MAX4477s maximum leakpacitance, which increases the noise gain with low current noise and pay careful at- age current is only 150 pA, so R2 could
of the circuit. Similarly, a high bias volt- tention to design, the limiting factor for be much larger than the 10 M shown.
age means high leakage current. Leakage noise should be the first-stage op amps R1 can also be substantially larger when
current also generates noise. The circuit input-voltage noise multiplied by the to- the circuit operates with a high-quality
70 edn | April 24, 2003
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design
ideas
STOP
M POS: 15.20 SEC CURSOR
PIN photodiode. C1 affects the
from Test Point 1, and the botcircuit gain, and smaller values
tom waveform represents the
TYPE
VOLTAGE
benefit both noise and gain. Use
comparators output. A possible
a capacitor with low temperature
improvement would be to reSOURCE
coefficient to avoid
place C1 with a digitally trimCH1
Figure 2
mable capacitor, such as the
gain changes with
MAX1474, which provides the
temperature. This capacitance
DELTA
216 mV
circuit with digitally programvalue also affects the requiremable gain. Similarly, replacing
ment for gain-bandwidth prodCURSOR 1
the mechanical potentiometer
uct in the op amp. Smaller ca216 mV
with a digital potentiometer,
pacitance values require a higher
CURSOR 2
such as the MAX5403 allows
gain-bandwidth product.
0V
digital adjustment of the comTo ensure that the circuit
parator threshold. Finally, drivmeasures gamma radiation and
CH1 100 mV CH2 5V
M 5 SEC
CH2 / 1.36V
ing the comparators noninnot light, cover the PIN photodi- These waveforms from the Figure 1 circuit show the signal at Test
verting input with a reference
ode with an opaque material. To Point 1 (top trace) when a gamma photon strikes the PIN photodiinstead of the 5V supply imblock radiated emission from ode, and the resulting comparator output (bottom trace).
proves the comparators threshpower lines, computer monitors,
and other extraneous sources, be sure to ton. (The more expensive photoelectric old stability.
shield the circuit with a grounded enclo- smoke detectors do not contain americisure. You can test the circuit by using an um.) A 60-keV gamma is close to the cirinexpensive smoke detector. The ionizing cuits noise floor but should be detectable.
types of smoke detectors use americium A graph shows the result of a typical gam- Is this the best Design Idea in this
241, which emits a 60-keV gamma pho- ma strike (Figure 2). The top waveform is issue? Select at www.edn.com.
Circuit ensures safety in power-on operation

Jean-Bernard Guiot, DCS AG, Allschwil, Switzerland
controllers output that is shortomputers find universal
er than 5 sec has no effect on the
use in industrial-control sysVCC
R2
R3
output of the circuit. Output Q13
tems. During power- and
16 9
10
11
of the counter turns on after 11
start-up sequences (booting), the
VCC C0 C1
C2
R5
sec, Q14 after 23 sec, and so on.
outputs of such conOUTPUT
Figure 1
1
R1
IC2
The LED, connected to Q7
trol systems may yield
Q12
through R4, flashes during the
uncontrolled pulses before the
12
6
timing period. With VCC12V
software defines the correct staIC1
RESET
Q7
CD4060
and an LED current of 10 mA,
tus. If these outputs control the
R4
CONTROL
R4(VCC2)/101 k. For safepower-on state of a system, these
OUTPUT
ty
reasons, you can add the optouncontrolled pulses could have
0V
LED
coupler, IC2. If output Q12 of the
dramatic consequences. Safety
8
counter fails (shorted to VCC), the
regulations forbid such erratic be0V
output turns on only if the conhavior. The circuit in Figure 1 is
trollers output is on. Choose the
a cost-effective approach to the This simple timing circuit ensures that a controllers spurious
value of R1 depending on the conspurious-pulse problem. The cir- pulses do not affect a systems start-up operation.
trollers output and the noise levcuit costs approximately 10 times
less than other available timers. The puts are low. C, R2, and R3 are the timing el; in this design, R110 k. Note that
open-collector output of the controlling components for IC1. With R2R310 k VCC should have a maximum value of
device connects to the reset input of the and C0.1 F, the measured clock fre- 15V for the CD4060 and 6V for the
74HC4060.
CD4060 counter, IC1. You can easily quency is approximately 360 Hz.
adapt this circuit to other controller-outThe output of the circuit is Q12. The
put configurations, such as an optocou- reset input must stay low longer than
pler. As long as R1 pulls the reset input T(2n1)/f(2048)/3605 sec for the
high (controller-output off), the output to turn on (n is the output num- Is this the best Design Idea in this
counters clock stays disabled and all out- ber, 12). Any spurious pulse from the issue? Select at www.edn.com.
72 edn | April 24, 2003
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design
ideas
Supply delivers pin-programmable

multiple references
V Manoharan, Kochi, India
obtain precisely 5V at
n the circuit of Fig15V
VOUT2, you must ratioure 1, the REF01, IC1, is
2
VOUT 6
VIN
VOUT1
a buried-zener-diodematch
R1 and R2 and also
IC1
C1
based, precision 10V refmatch their temperature
REF01
0.1 F
erence that features minicoefficients. Now assume
GND
mal noise and drift over
R2/R1A and Point 1 con4
nects to Point 3. In this
temperature. The circuit
1
case, the gain of the inprovides not
2
JUMPERS
Figure 1
verting amplifier is A.
only the 10V
Therefore, VOUT1 and
output of the REF01, but
3
VOUT2
VOUT2 deliver unbalanced
also a 5V output that a
R2
outputs, the sum of which
REF02 reference would
15k
is 10V. You can easily dedeliver. In addition, the
15V
C2
rive that VOUT110/(1A)
circuit provides 5V,
0.1 F
and VOUT210A/(1A).
10V, and an unbalanced
The flexibility of this
dual reference, the sum of
4
R1
circuit
eliminates the need
whose voltages is precisely
2
to
design
and inventory
10V. In addition to the
15k
6
IC2
several voltage sources.
REF01, the circuit uses a
3
C3
Moreover, the circuit can
highly precise, unity-gain
0.1 F
7
R3
serve as a dual reference.
inverting amplifier, IC2.
7.5k
Tables 1 and 2 define the
The circuit finds applicaoutput voltages as a function in D/A converters
15V
tion of the jumper conneeding external refernections and as a function This pin-configurable voltage reference delivers a variety of positive and negaences, portable instruof the optional use of a tive output voltages.
ments, digital multimeREF02 reference in place
ters, and A/D converters. It
of the REF01. In Figure 1, assume the use connects to Point 2. (Pin 4 of IC1 con- is advisable to use the ultralow-offsetof a REF01 reference, and that Point 1 nects to ground.) IC2 inverts the 10V voltage OP07 or ultralow-noise OP27 for
output of IC1 to deliver 10V at VOUT2.
the inverting amplifier.
Now assume that Point 1 connects to
Point 3. (Pin 4 of IC1
Supply delivers pin-programmable
connects to the output
multiple references ........................................87
TABLE 1AVAILABLE OUTPUT VOLTAGES
of IC2). If VOUT1 is at X
Device
Jumper
VOUT1
VOUT2
Design an efficient reset circuit ..................88
volts, VOUT2 assumes a
IC1
connection
(V)
(V)
One-shot provides frequency
level of X volts. The
10
REF01
1 to 2
10
discrimination ................................................90
5
REF01 forces exactly
REF01
1 to 3
5
5
REF02
1
to
2
5
10V
between
its
output
Circuit forms novel floating
2.5
REF02
1 to 3
2.5
and Pin 4. Therefore,
current source ................................................92
X(X)10, 2X10,
Circuit provides Class D
and X5V. In this
TABLE 2UNBALANCED OUTPUT VOLTAGES
motor control ..................................................96
arrangement, 5V and
Device
5V are simultaneousIC1
R2/R1
VOUT1
VOUT2
10A/(1+A)
REF01
A
10/(1+A)
ly available at VOUT1 and
5A/(1+A)
REF02
A
5/(1+A)
VOUT2, respectively. To
www.edn.com
May 1, 2003 | edn 87
design
ideas
Design an efficient reset circuit

Guillermo Bosque, Asesora e Integracion de Tecnologas, Urduliz, Spain
hen you work with microprocessors, you must ensure that
when the power-supply voltage
fluctuates to the minimum perFigure 3
missible level,VL, that the processors ALU continues to operate normalVBAT
ly. Also, when you switch on the power
supply, the ALU must operate normally
RREF
when the supply voltage equals or exceeds
VCC
R3
VCC
VCC
R1
R2
ROUT
V _
VOUT1
IC1
RRST
+
IC2
VOUT2
_
CRST
VREF
VH
VL
This circuit introduces a time constant in the reset function.
tA
tB
tC
t
NOTES:
IF t < tA, THEN RESET.
IF tBtA,>tMIN , THEN THE RESET DISAPPEARS.
tC: RESET INSTANT APPEARS.
Figure 1
A proper reset signal plays an important role in
microprocessor operation.
VCC
R3
R1
+
VBAT
R2
ROUT
VOUT
RREF
VREF
Figure 2
This comparator has built-in hysteresis to provide a reset signal when the supply voltage
falls outside the limit band.
ple, 40 to 85C. Several reset circuits

VOUT1
are available that meet the voltage conditions, but the temperature constraints
render them unsatisfactory. This Design
VOUT2
t
Idea proposes a small, inexpensive reset-circuit structure.
VRSTEND
The supervisor circuit includes a
comparator with hysteresis (Figure 2).
t
tRST
The circuit represents a noninvertFigure 4
ing comparator; the voltage to supervise is VCC. The comparator takes a The reset signal ends after one time constant in
sample of VCC via the R1-R2 voltage di- the circuit of Figure 3.
vider and compares it with the reference
voltage, VREF. You obtain VREF by using a
APPROXIMATE
EXACT
battery voltage, VBAT, but VCC would work
EQUATIONS
EQUATIONS
as well. The pullup resistor, ROUT, is necessary to obtain a positive voltage at the
R2 + R3
1 VH
=
1 .
R1 = R 2 L 1 .
output, because the comparators output
R 2R 3
R1 VREF
VREF
has an open-collector or open-drain
VL
VLVREF
R1(R 3 + R OUT )
= R2
1 .
R3 = R2
.
structure. The following approximate
R1 + R 3 + R OUT
VREF
VHYST
and exact equations are based on selecIn the approximate equations, you distion of VH and VL. (Remember that
VHYSTVHVL.)
regard ROUT, because its value is negligiVCC
R3
VCC
VCC
R1
ROUT
VCC
a certain high level,VH. The min+

RRST
Figure 5
VOUT1
imum and high levels constitute
IC1
+
R4
VOUT2
R2
_
+
IC2
a hysteresis band (VHYSTVHVL), and
IC3
_
+
fluctuations in supply voltage within this
VBAT
CRST
_
band should not perturb the logic operRREF
ations of the processor (Figure 1). A
properly designed reset circuit can ensure
proper operation of a microprocessor.
VREF
One requirement of an efficient reset circuit is that it operates properly over the
intended temperature rangefor exam- The additional comparator in Figure 5 switches when the exponential signal reaches VREF.
VOUT3
edn030306di31733
Heather
88 edn | May 1, 2003
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design
ideas
VCC
3
VCC
ble compared with that of R3. But
VCC
Figure 7
the value of ROUT affects VL, because
R1
R4 5k TO 100k
+
ROUT and R3 are additive when the com+
IC
RESET
parator is in the high-impedance (off)
3
IC1
+
_
R2
MICROPROCESSOR
state. Choosing values for VHYST and VL
C1
_
100 F
and knowing VREF, you obtain the
VBAT
following approximations: R1R2
VBAT
VCC
(VL/VREF1), and R3R1(VREF/VHYST).
RRST
Now, you add a timing circuit to the hysRREF
+
R5 5k TO 100k
+
teretic comparator (Figure 3). When
IC2
RESET
IC
VOUT1 assumes a low level, VOUT2 switch4
+
_
CRST
GENERAL
_
es to a low level and discharges CRST.
C2
+
VREF
When VOUT1 switches high, comparator
100 F
IC2 switches to its high-impedance state,
and CRST begins to charge through RRST.
VOUT2 follows an exponential curve and The complete reset circuit can handle microprocessors and other circuitry.
arrives at a value, VRSTEND, which signals
the end of the reset signal (Figure 4). You other comparator, IC3 (Figure 5), you ob- and R3355 k. For timing the reset, you
use the capacitor-charging equation,
can modify the tRST by adjusting the val- tain the waveforms of Figure 6.
ues of CRST and RRST. Now, if you add anThe final reset circuit appears in Fig- VVCC(1et/RRST/CRST).
The final instant of reset occurs when
ure 7. The circuit has four comparators,
one voltage reference, seven resistors, and VVREF1.2V. Choose 5V for VCC. The
VOUT1
three capacitors. To determine the resis- equation then becomes tRRSTtor values, you can use the following CRSTln(1V/VCC). If you choose t1 sec
equations: R1R2(VL/VREF1), and and CRST10 F, then
VOUT2
t
R3R1(VREF/VHYST). An appropriate
t
R RST =
.
comparator IC is the quad LM239 (25
V
VREF
C RST 1
to 85C) or the LM139 (55 to

VCC
125C). The voltage reference is the

VOUT3
t
You obtain RRST36.4 k. If CRST1
1.2V ICL8069CMSQ (55 to 125C).
C1 and C2 stabilize high-frequency fluc- F, then RRST364 k. Its preferable to
tuations and have values of 100 nF and 10 have a low value for CRST because of the
F, respectively. RREF has a value of 50 k, low current in the comparators output
t
tRST
and R4 and R5 have values of 5 to 100 k, transistor. Solving for R2, you obtain
Figure 6
depending on the circuit you wish to con- R210 k.
One additional comparator produces a positive
trol. If you chose VL4.75V, VHYST0.1V,
signal at the processors reset port.
and R210 k, you obtain R129.6 k
One-shot provides frequency discrimination

Victor Aksenenka, CSRI Elektropribor, St Petersburg, Russia
5
ou use a frequency discriminator
2
2 D
Q 13
Q
Q
fIN
D
to compare one signal frequency
with another one. A functional fea1
3 C
4
D
IC1
IC2
Q
ture, retriggering, of a monostable, oneR1
74LS74
74LS123
shot 74xx123 multivibrator can
10k
3
15
Figure 1
5V
R/C
R
yield frequency discrimination.
1,4 R,S
R1
6
Q
Figure 1 shows a frequency discrimina10k
R3
C1
tor that determines the relation of input10k
5100 pF
5V
14
pulse frequency to a reference frequency.
C
The external components, R1 and C1, set
5V
the reference frequency. These values determine the 74xx123s reference frequen- This simple circuit can reveal whether an input frequency is above or below a reference frequency.
90 edn | May 1, 2003
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design
ideas
cy as follows: fR1/tW, and tWkR1C1.

The multiplication factor k depends on
C1s value and the power-supply voltage.
The rising edge of the input pulse starts
the one-shot, whose output switches
high for the interval tW. The same pulse
edge sets the 74xx174 flip-flop to the
same state as the output of
Figure 2
the one-shot. If the interval
between pulses is longer than tW, the next
pulse arrives after the one-shot returns
to its initial state. The one-shots output
is low, and the rising edge of the input
pulse sets the flip-flop low. The low flipflop output indicates that the input-pulse
frequency, fIN, is lower than fR.
If the interval between input pulses is
fIN
2
1
3
R1
10k
R/C
ICIA C
74LS123
13
4
15
14
2
R3
10k
C1 5V
5100 pF
3
1,4
D IC2A Q
74LS74
C
R,S
Q1
R5
10k
1
5V
5V
10
9 D
11
R2
10k
Q 12
R/C
ICIB C
74LS123
7
6
12
R4
30k
C2 5V
5100 pF
5V
11
10,13
D IC2B Q
74LS74
C
R,S
IC3
74LS86
Q3
Q2
R6
10k
5V
Doubling the circuit in Figure 1 and using an exclusive-OR circuit results in a window discriminator.
VOUT
Q1
Q2
Q3
fRL
fRH
fIN
Figure 3
The output of the exclusive-OR circuit in Figure
2 is high only when the input frequency is
between defined limits.
shorter than tW, the next pulse arrives before the one-shot completes its cycle and
returns to its initial state. The one-shots
output is high, and the rising edge of the
input pulse sets the flip-flop high. A high
flip-flop output indicates that the inputpulse frequency, fIN, is higher than fR.
Doubling the circuit in Figure 1 implements frequency discrimination with a
window characteristic (Figure 2). Two
pairs of R and C values determine the
lower and upper reference frequencies.
An exclusive-OR circuit takes the outputs

of the upper and lower flip-flops. The exclusive ORs output is high when fIN is between fRL and fRH. When fIN is outside the
frequency band fRL to fRH the exclusive
ORs output is low. Figure 3 shows the frequency-discrimination characteristic.
With R and C values as in Figure 2, and
the use of a 74LS123 one-shot, fRL16
kHz, and fRH46 kHz. Other types of
one-shots could produce different results.
Circuit forms novel floating current source

S Casans, AE Navarro, and D Ramirez, University of Valencia, Burjassot, Spain
igure 1 shows a polarVCC
ization circuit applicable
to ISFET (ion-sensitive
I0
REFERENCE
field-effect-transistor) sensors.
ELECTRODE
ISFET
ISFETs are solid-state chemical
SENSOR
+
sensors that measure the pH
TL082A
value of a solution in biomedD

RX
ical and environmental applicaS
+
tions, for example. The circuit
VSG
TL082B
in Figure 1 is extremely simple;
it sets fixed-bias conditions for

ISFET sensors (VDSI0RX;
2I0
IDSI0). When a senF
i
g
u
r
e
1
sor needs characteriVCC
zation, you must modify the
bias conditions, thus increasing This circuit is a classic configuration for biasing ISFET sensors.
92 edn | May 1, 2003
the cost and the complexity of

the bias circuit. The low-cost
auxiliary module in Figure 2
implements a novel, voltagecontrolled floating current
source. The current range covers the interval 0 to 100 A.
You implement this module to
control the ISFET sensors bias
voltage, but you can apply it to
any sensor that needs bias of
100 A or lower. The floating
current source uses three operational amplifiers, all portions of a Texas Instruments
(www.ti.com) TL084. The curwww.edn.com
design
ideas
VCC
Figure 2
I0
ISFET
SENSOR
REFERENCE
ELECTRODE
I1
R0
+
TL082A
_
E1
_
RX
TL084A
+
VC
+
I2
R0
VR2
TL084B
+
VR1
I0
E2
_
R
VSG
TL082B
_
VCC
_
TL084C
+
This novel floating current source represents an improved way to bias ISFET sensors.
rent sources (I0) and the current mirrors

(E1 and E2)use the Burr-Brown
(www.ti.com) REF200. The REF200 has
two 100-A floating current sources (I0)
and one current mirror Ei (i1, 2). The
VR1 and VR2 voltages compensate the deviations arising from the operational
amplifiers offset voltages and the resistor tolerances. The VC voltage controls
the currents I1 and I2; therefore, in the

circuit in Figure 2, VC controls the sensor bias voltage VDS.
Figures 3 and 4 show the measured absolute errors occurring in the bias current
and voltage, respectively. The main advantages of this current source are that it
floats and that you can connect it to any
circuit without changing its operating
0.1
1.5
0.5
mode, because the currents I1 and I2 are

complementary. Therefore, if I1 diminishes, the I2 current increases in the same
proportion, and this action does not affect the other currents in the circuit. In
the ISFET-sensor case, changing I2 via VC
allows you to vary the bias voltage applied
to the sensor without changing the bias
current, IDS.
_ 0.5
_ 0.1
ERROR
(A)
ERROR
(mV)
_ 0.2
_ 1.5
_ 2.5
_ 0.3
_ 3.5
_ 0.4
10
20
Figure 3
30
40
50
60
70
80
IDS (A)
Very small measured errors appear in the ISFETs bias current.
94 edn | May 1, 2003
90
100
0.2
0.4
0.6
0.8
1.2
1.4
1.6
1.8
VDS (V)
Figure 4
Only a few millivolts of error appear over the full range of VDS.
www.edn.com
design
ideas
Circuit provides Class D motor control

John Guy, Maxim Integrated Products, Sunnyvale, CA
lass D audio amplifiers provide
L1
a dual benefit for battery-powered
VCC
portable devices. They enhance bat15 H
IC1
C1
tery life, and they produce much less
1 F
MAX4295
R
power dissipation than do their linear
16
1
1
GND
SS
GND
16.5k
15
2
L2
cousins. Those features make Class D amPVCC
PVCC
C3
14
3
OUT+
OUT
1 F
13
4
plifiers ideal candidates for controlling
15
H
PGND
PGND
12
5
C2
VCC
GND
1 R2
speed and direction in small electric mo11
6
1 F
25k
VCM
FS2
10
7
tors. The standard application
IN
FS1
9
8
Figure 1
R3
AOUT
SHDN
circuit for a Class D audio am3
100k
C4
R4
plifier, IC1, requires only slight modifica1 F
100k
tions. In place of the usual audio-signal
input is a variable dc voltage that potenC5
tiometer R2 generates. Resistor R1 biases
100 pF
the potentiometer to match the input
range of IC1. Full-counterclockwise ro- A Class D audio amplifier, IC1, helps implement this simple motor-speed controller.
tation of the potentiometer corresponds
to maximum-speed reverse rotation of produces maximum-speed forward rota- prises L1, L2, C1, and C2. But, unless the
the motor. Midscale on the potentiome- tion in the motor. The characteristics of control circuitry is near the motor,
ter corresponds to motor off, and full- a given motor may allow you to eliminate you should include the filter to reduce
clockwise rotation of the potentiometer the amplifiers output filter, which com- EMI.
96 edn | May 1, 2003
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ideas
Small, 915-MHz antenna beats monopole

Dave Cuthbert and Bob Casiano, Micron Technology, Boise, ID
VIA=0.5 IN.
915-MHz data-acquiproperties, you add pesition project reriodic RC loads beL = 1.25 IN.
quired a small antentween the transmisL = 0.500 IN.
na, but the available
sion-line elements. The
antennas lacked the necloads are the small
essary characteristics: efboxes in Figure 2, and
ficiency, compactness
each load comprises a
L = 1.25 IN.
that is, smaller than a
30 resistor in series
GND
standard 3-in. monowith a 78-fF capacitor.
Figure 1
polewith adequate
The capacitance of
bandwidth, and with
each RC load is equal
L = 0.570 IN.
amenability to modeling
to the difference beby inexpensive NEC-2 antween the transmis0.25
0.25 IN.
tenna software. (To learn
sion-line capacitances
GND
GND
GND
GND
more about NEC antenna
calculated with FR-4 as
software, go to www.nit SIGNAL
the dielectric and with
INPUT
tany-scientific.com/nec.)
vacuum as the dielecThe result of this design This 915-MHz antenna measures only 1.25 in. sq yet outperforms a standard 3-in.
tric. You calculate the
effort, called the Tab an- monopole.
resistance of each RC
tenna for its square shape
load using the pubhas the following characteristics:
perpendicular to a pc board;
lished FR-4 loss tangent of 0.02. The fol a square shape, 1.25 in. per side (0.1
enhanced suppression of second- lowing formulas determine the approxiwavelengths);
and third-harmonic radiation; and
mate RC values for the transmission-line
the ability to be constructed in FR-4
the ability to be mechanically trim- loads:
pc board;
mable to resonance.
276
2D
linear polarization;
The Tab antenna is a folded monopole
log10
,
Z0 =
d
Er
a 2-to-1 VSWR (voltage-standing- that you miniaturize by forming it into
wave-ratio) bandwidth of 46 MHz an inverted L with a downward bend at where D is the conductor spacing and d
(5% bandwidth);
the end (Figure 1). You can solder it per- is the conductor diameter.
the ability to be mounted parallel or pendicular to a pc board or build it as
t
Er
part of a pc board and place it at a
C = PROP _ VACUUM
.
Z0
corner. The folded section transforms the 12.5 radiation resistLOSS TANGENT
ance to 50 and provides secondR=
.
2 fC
harmonic suppression. Third-harmonic suppression comes from an
open stub near the base of the anSmall, 915-MHz antenna
Figure 2
tenna. Detailed NEC-2 modeling
beats monopole ............................................73
explores the sensitivity to changes
Digital signal controls
in the dimensions and optimized
sine generator ................................................74
harmonic suppression. Because
Transmitter accurately transfers
NEC models wire antennas in a vacvoltage input ..................................................76
uum and the Tab antenna is built on
FR-4, you must incorporate the diAbsolute-value circuit delivers
electric properties of the dielectric
high bandwidth ..............................................80
between the antenna elements into
the model.
in series
The square grids represent loads of 30
To incorporate the dielectric
with 78-fF capacitors.
www.edn.com
May 15, 2003 | edn 73
design
ideas
3.5
You calculate the RC load pamonopole with a 50 source

3
rameters for 915 MHz and place
driving both antennas.
them every 0.1 in. (approximateThe Tab antenna has 202.5
ly 5) along the line. You use the
mil-wide traces on opposite
2
following parameters in the calsides of 62-mil FR-4 and
culations:
mounting pads at three loca1.5
D62 mils,
tions to allow soldering the
1
d20 mils,
antenna securely to a larger
SIMULATED VSWR
0.5
effective Er (dielectric conboard. You tune the antenna
MEASURED VSWR
stant) of FR-43,
by trimming the open trans0
loss tangent0.02, and
mission line to provide an
900
920
940
960
860
880
FREQUENCY (MHz)
tPROP_VACUUM85 psec/in.
impedance minimum at
Figure 3
Table 1 shows the effective
2745 MHz and then trimparameters in air and in the FR-4
ming the antenna elements
The simulated VSWR figures of the Tab antenna agree closely with
medium. You use iterative modelto resonance at 915 MHz.
the measured results.
ing to determine the antenna diFigure 3 shows that the simmensions with the following design paThe folded section, functioning as a ulated 2-to-1 VSWR bandwidth is 41
rameters: The first vertical section and the shorted 180 transmission line at 1830 MHz, whereas the measured bandwidth
horizontal section must be of equal MHz, provides second-harmonic sup- is 46 MHz. Note that the required operlengths, the feedpoint impedance target is pression. And, although the optimum ating band is only 902 to 928 MHz. The
50, and the resonant frequency is 915 point for the short circuit is 1.75 in. from increased measured bandwidth arises
MHz. You meet these design criteria with the feedpoint, you can achieve second- from dielectric losses and indicates that
a simulated antenna height of 1.3 in. and harmonic suppresa total element length of 3.3 in. The actu- sion of 25 dB by plac- TABLE 2HARMONIC SUPPRESSION OF QUARTERWAVELENGTH MONOPOLE AND TAB ANTENNA
al element length of 3 in. stems from di- ing the short within
Frequency
Quarter-wavelength
Tab antenna
electric loading. You also shorten the ac- 10% of this point. The
(MHz)
monopole (dB)
(dB)
tual antenna height to 1.25 in. to location of the short
1830
7
25
compensate for the impedance increase has little effect at 915
2745
1
15
that the dielectric loss causes. Note that MHz. An open transthe modified NEC model accounts only mission line at the feedpoint that is 90 at the radiation efficiency is approximately
for the dielectric between the antenna el- 2745 MHz provides third-harmonic sup- 90%. The large bandwidth of the Tab anements.
pression. This line creates a near-short cir- tenna results in low sensitivity to envicuit at 2745 MHz and provides ronmental detuning. This design effort
TABLE 1ANTENNA PARAMETERS IN
harmonic suppression of 15 dB yields an antenna only 40% as tall as a
AIR AND IN FR-4 PC-BOARD MATERIAL when you trim it to within 5% of standard quarter-wavelength monopole,
)
Dielectric
Er
Z0 (
C (fF)
R
the optimum length. Table 2 com- yet having excellent radiation efficiency,
Air
1
219
39/0.1 in.
Infinite
pares the simulated harmonic extended bandwidth, and superior har
FR-4
3
126
117/0.1 in.
30
suppression of the Tab antenna monic suppression.

RC load
78
30
with that of a quarter-wavelength
Digital signal controls sine generator

Simon Bramble, Maxim Integrated Products, UK
he circuit of Figure 1 produces an
5V
0.1 F
0.1 F
accurate, variable-frequency sine
VOD SHDN
10k
IC1
wave for use as a general-purpose
1
8
MAX809
IC2
VOUT
2
reference signal. It includes an eighth-orOUT
IN
IC3
AT90S 6
1 F 10k
der elliptic, switched-capacitor lowpass
10-MHz
10k
2323
MAX7400
CRYSTAL
5
4
filter, IC3, which uses a 100CLK
Figure 1
COM
kHz square-wave clock signal
OS
GND
that microcontroller IC2 generates. (Any
other convenient square-wave source is
also acceptable.) The microcontroller receives its clock signal from a 10-MHz os- By removing harmonics from a square wave, this circuit generates an accurate and adjustable sinecillator module. A voltage supervisor, wave output.
74 edn | May 15, 2003
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design
ideas
LISTING 1ASSEMBLY CODE FOR SINE GENERATOR
IC1, ensures correct operation in the

event of a power failure. IC3 sets the filters cutoff frequency at one-hundredth
the clock frequency.
The eighth-order elliptic filters sharp
roll-off sharply reduces the harmonic
amplitudes in a 1-kHz square-wave input, thereby producing a nearly perfect
1-kHz sine wave at its output. Using divider-chain logic or a processor, you can
then create a digitally adjustable sinewave source by adjusting the clock and
input frequencies and maintain a ratio of
100-to-1 between them. To prevent clipping at the positive and negative peaks,
attenuate the input signal and superim-
pose it on a dc level of VCC/2. The result

for a 5V input is a 2.25V peak-to-peak
output. Listing 1 shows the assembly
code for the microcontroller this application uses. You can download the code
from the Web version of this Design Idea
at www.edn.com.
Transmitter accurately transfers voltage input

Clayton Grantham, National Semiconductor, Tucson, AZ
hen you connect remote senVOLTAGE-CONTROLLED
sors to a central process conCURRENT SOURCE
TWISTED-PAIR
VLOOP
VIN
WIRE
troller, a simple, robust, and comROUT
monly used interface is the 4- to 20-mA
LOOP SUPPLY
FIXED
0 TO
VOLTAGE
VERY
RIN
4 mA
16 mA
loop. The advantages of this current loop
INPUT
LARGE
include the simplicity of just two twistVIN
VLOOP
ed wires that share both power and sigRLOAD
nal, the loops high noise immuniFigure 1
ty in harsh environments, and the
de facto loop standard within the
process-control industry. Within this in- This ideal 4- to 20-mA current transmitter has one voltage-controlled current source and one fixed
terface scheme, a typical 24V battery current source.
76 edn | May 15, 2003
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design
ideas
IC5
LM2936-3V
IC1
LM7301
5
4
+
1
3 _
VOLTAGE
INPUT
0 TO 1.2V
1
1
R4
200
R2
75
0 TO
16 mA
IC4
LM37242.32V
2
3
3
RESET
IC2A
LMV358
C2
0.01 F
R1
1M
Q1
2SD601A
R9
26.7k
R5
100k
VIN
C1
0.01 F
R3
11
R6
100k
1
IC3
2 LM40511.225V
5
VCC
MR
GND
1,2
VLOOP
C4
0.01 F
R11
3.6k
R10
100k
7
IC2B
LMV358
Figure 2
3 V
1
REG +V
GND
R8
3.01k
R7
17.8k
C3
22 F
6
4- TO 20-mA
CURRENT LOOP
5
R12
3.6k
4 mA
VIN
VLOOP
This circuit transforms a 0 to 1.2V input voltage to a 4- to 20-mA output range.
(loop power source) connects through a

twisted-wire pair to a transconductance
amplifier (voltage-to-current converter)
that converts a sensorsfor example, a
pressure transducersoutput voltage
into a current that then gets transmitted
back through the twisted-wire pair to a
receiver (load resistor) at the processcontrol computer. An important criterion in this interface is that the current
transfer of sensor information must be
accurate. Figure 1 shows the transmitter
with one voltage-controlled current
source and one fixed-current source.
The fixed-current source is 4 mA, a
current that constitutes the power source
for the transmitter and the sensor electronics. This fixed current source must
have an output impedance greater than
20 M to keep the loop current independent of loop-supply variations. Similarly, current needs to be independent of
temperaturethat is, greater than 100
ppm/Cbecause the transmitter and
the sensor can be in harsh environments.
The voltage-controlled current source
has the same requirements as the fixedcurrent source and needs to convert the
input voltage signal linearly into a 0- to
16-mA current. Thus, it produces an ideal transconductance as the two-port network representation of a voltage-controlled current source. The total
loop-current equation is: Loop current4 mA(gm)VIN (for VIN1.2V,
gm13.3 mmho).
The transconductance circuit in Fig-
78 edn | May 15, 2003
ure 2 allows you to transmit current (4to 20-mA loop) with less than 1% total
error from 40 to 85C and over a 3.2
to 40V loop-voltage range. Many IC realizations of a current transmitter have
existed for years, but none operates at the
loop voltage of 3.2V. Also, these ICs are
becoming sensor-specific, whereas you
can modify and optimize the circuit in
Figure 2 for any sensor electronics or
loop-current variation (for example, a 1
to 5A loop) at low loop voltage. The total loop current is as follows: Loop current1.225V(R11/R10)/R3VIN /R2. The
circuit discussion starts with the realization of the fixed current source, IS. The
fixed 4-mA current all flows through R3.
The servo circuitry, including IC2 and IC3,
senses the 44-mV voltage drop across R3
and keeps it fixed. Note that the ground
current of all ICs also flows through R3;
thus, the 4-mA fixed-current setting includes ground-current errors. The dual
op amp, IC2 , is both an inverting gain
stage and an integrator stage. R10 and R11
set the inverting gain to 27.8V/V. The
noninverting-integrator components C1,
C2, R5, and R6 provide a comparison of the
44 mV across R3 (gained up to 1.225V)
to the shunt-reference voltage of IC3. The
output of IC2A adjusts the sum of the
current though R4 and any ground current from IC2, IC3, and IC4 to a value of
4 mA. IC4 acts as an analog power-on-reset circuit that holds off the start-up of
servo action until all the ICs have sufficient supply voltage. With the divider
ratio of R8 and R9 and the 2.32V option

of IC4, the start-up voltage equates to:
VSTART-UP2.32V(R8R9)/R92.7V.
This start-up value is higher than the
rated supplies of IC1 and IC2 and lower
than IC5s regulated output of 3V. R4 level-shifts the output of IC2A up from zero.
R7 biases IC3 into its specification range
to guarantee 0.1% tolerance and 50ppm/C temperature coefficient over the
40 to 85C range. The circuit discussion continues with the realization of the
voltage-controlled current-source. IC1,
Q1, and R2 are configured as a voltage-tocurrent converter. Thus, for a full-scale
range of 20 mA, 16 mA comes from the
voltage-to-current converter. With the
maximum VIN at 1.2V, R2 must be 75 to
produce 16 mA. IC1 must have a common- mode input range that goes beyond
its negative supply (less than 44 mV).
R1 is optional and prevents an open circuit on IC1s input. You can remove R1,
depending on the output impedance of
any input-sensor electronics. Note that R1
directly introduces an error in the fullscale loop-current.
At the heart of the circuit discussion is
the realization of an output impedance,
ROUT, greater than 20 M in Figure 1. The
low-dropout regulator, IC5, accomplishes this task by subregulating the supply to
IC1 and IC2. The good line regulation of
IC5 keeps the 3V output within 30 mV
over the input range of 3.2 to 40V. Additionally, IC5 requires as little as 200 mV
of overhead to properly regulate, and it
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design
ideas
can withstand more than 40V. This current-transmitter circuit is useful for both
low-loop-voltage designs, and its backward-compatible with higher loop-voltage implementations. Furthermore, IC5
has reverse-supply and surge protection.
Therefore, this circuit does not require an
additional diode within the loop, a common need with other ICs to prevent
accidental reverse-wiring damage. The
TO-252-package option simplifies the
thermal-design considerations. With a 1in.-sq-area pad for heat sinking, the
worst-case power dissipation calculation
would keep the junction temperature
within its rated 150C: TJ85C(20
mA)(40V)50C/W125C.
You could increase the VIN range of the
current-transmitter by scaling R2, as long
as you dont violate the common-mode
input range of IC1. IC1s VCM includes its
positive rail. So, to obtain a higher VCM,
you can increase the voltage option of
IC5. For example, use the LM2936-5V
and R2 equal to 312.5 for a 0 to 5V in-
put range. This configuration

0.50
would also require that the loop
supply be at least 5.2V. Note that
0.25
any sensor and other electronics
0.00
ERROR
can and should use the 3V subrails
(% OF 16mA)
that IC5 creates as long as the cur0.25
rent they demand does not exceed
3 mA. The 4-mA fixed-current cir0.50
cuitry adjusts for the
40
20
0
20
40
60
80
Figure 3
TEMPERATURE (C)
current demand. Figure
3 shows the total error on protoOn three prototype circuits of Figure 2, the total
type units over temperature.
error is well below 1% over temperature at 3.2V
The total error includes the offloop voltage.
set (4-mA) and full-scale (20-mA)
effects on the ideal loop current.
The tolerances of R2, R3, R7, and R8 error both influence the best nonlinearshould be within 0.1% with 50-ppm/C ity attainable: less than 0.01%. IC2s offtemperature coefficients. With IC5 subset error is in series with the 44-mV voltregulating the rails of IC1, IC2, and IC3, age across R3, producing an offset error
the power-supply-rejection-ratio error of 4 mA. Adjust R3 if you need to null
of these ICs does not generate a signifi- this error. Adjust R2 to fine-tune the fullcant error. In like manner, IC2s CMRR scale range of 20 mA. The op amps off(common-mode-rejection-ratio) error set-temperature-coefficient error is
does not generate a significant error. small compared with the 1% temperIC3s CMRR error and Q1s base-current ature-range budget.
Absolute-value circuit delivers high bandwidth

Ron Mancini, Texas Instruments, Bushnell, FL
ost absolute-value circuits have
limited bandwidth and high component count, and they require
several matched resistors. The circuit in
Figure 1 uses three fewer components
than most absolute-value circuits require, and only two of the resistors must
have 1% tolerance to obtain 1% accuracy. This circuits output voltage is an accurate representation of the absolute value of the input signal, and it is accurate
for input signals containing frequencies
as high as 10 MHz. Another advantage of
this circuit is that it has a positive-voltage output, thus saving an analog inverter in most applications. When the input voltage is positive, the negative
output voltage of IC1 cuts off the diode,
thereby preventing signal propagation
through IC1. Virtually no signal propagates through R2, because the resistor
connects to ac ground through the out-
80 edn | May 15, 2003
R1
R2
put of IC2. The only signal path is
10k
10k
through R3 to buffer IC2, and the output VIN
1%
1%
of the buffer is a positive voltage. When
5V
the input voltage is negative, the positive
_
R
3
output voltage of IC1 forward-biases the
IC1
5%
diode, thus providing an ac short circuit
TLC072
+
D1
for R3 to ground. IC2 is within IC1s feed5V
back loop, so the output voltage is posiSD103CCT-NO
tive because of IC1s configuration as an
inverting op amp.
+
VOUT
IC2
This design uses a dual op amp to minTLC072
_
imize parts count. Two op amps in
Figure 1
a feedback loop tend to be unstable. Select an op amp that has sufficient
This inexpensive absolute-value circuit has high
phase margin to prevent oscillation when
bandwidth.
the input voltage is negative. The circuits
dynamic range is from the op amps inhigh-frequency TLC072 op amp with a
put offset voltage to the maximum out- fast Schottky-barrier diode. You can use
put voltage. This dynamic range is from higher frequency op amps to obtain bet1 mV to 4.1V for the TLC072 with 5V ter bandwidth results, but you must take
power supplies. The excellent bandwidth care in the op-amp selection to avoid osperformance results from combining the cillation or reduced dynamic range.
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design
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Microcontroller directs
supply sequencing and control
Joe DiBartolomeo, Texas Instruments, Dallas, TX
TO PIN 59
ith the proliferation of

TPS72518
2
4
dual-voltage architecTHREE
VIN
VOUT
1.8V
D CELLS
tures and multiprocesEN
GND RESET
1 F
4.5V
100k
sor boards, even simple appli1
3
5
TO PIN 14
MSP450
cations can require several
100k
processor voltage rails.
TO PIN 17
F
i
g
u
r
e
1
With each processor
TO PIN 60
having its own power-up and
TPS72525
MSP430FI49
-down requirements, power2
4
PI.1
VIN
VOUT
rail sequencing and control can
13
2.5V
PI.2
14
become a complex task. The
EN
GND RESET
1 F
PI.3
15
100k
1
3
5
PI.5
challenge for power-supply deTO
17
PIN 15
PI.6
AS CLOSE AS
18
signers is to consider each
100k
PI.7
POSSIBLE TO
19
processors timing and voltage
OUTPUT
PIN 4
TO PIN 18
PG.0
requirements and assimilate
59
PG.1
TO PIN 61
60
these into a total system, ensurPG.2
61
V
ing that the final design meets
100k
2
4
VIN
VOUT
3.3V
PI.0
the requirements of all proces12
EN
GND
FB
1
F
SHUTDOWN
sors.
FOR EXTERNAL
1
3
5
TO
Failure to properly power
HOST
PIN 13
processors can lead to problems
10k
PI.4
10
SYSTEM RESET
that range from the fairly beTO PIN 19
100k
nign, such as a reduction in
MTBF, to the catastrophic, such
as latch-up. Given the variety of An ultra-low-power microcontroller controls a systems power-supply sequencing.
available processors and the application challenges you expect when de- ty. The MSP430 is a good fit for such an voltage rails. The MSP430 monitors a conveloping a power-sequencing and -con- application (Figure 1). The high-per- trol variable to determine when to activate
trol scheme, use of a microcontroller is formance, low-cost 16-bit RISC proces- each rail. For power-sequencing applicadesirable because of its programmabili- sor has several high-quality analog pe- tions, the two most commonly controlled
ripherals and a JTAG interface.
variables are time and voltage. When time
Controlling
power
supplies
that
have
is the control variable, the controller enMicrocontroller directs supply
enable pins, such as those on most brick ables the first rail. At a specific time theresequencing and control................................73
dc/dc converters and low-dropout regula- after, it enables the next rail. Some time afCircuit provides leading-edge
tors, is simply a matter of using a GPIO ter that, it enables the next rail, and so on
blanking............................................................74
(general-purpose I/O) line. If the power until it has enabled all rails.
supply has no enable function, an inline
The MSP430 provides the timing-seMOSFETs reduce crosstalk effects
switch, normally a MOSFET, can control quence and the -control signals to turn
on analog switches........................................78
the power supply, either with a GPIO or on the power supplies. If voltage is the
Grounded resistor tunes oscillator ............78
PWM signal. The circuit in Figure 1 uses control variable, then the controller actiObtain higher voltage
the TPS725xx family of low-dropout reg- vates the first voltage rail and monitors
from a buck regulator ..................................80
ulators to provide 3.3, 2.5, and 1.8V from its rise via an ADC. When the first voltan input dc source. These regulators have age rail reaches a specific voltage level,
an enable pin and a reset function.You can the controller enables the next voltage
easily expand this circuit to any number of rail and monitors its rise until it reaches
www.edn.com
May 29, 2003 | edn 73
design
ideas
a specified voltage level. At this point, the

controller enables the next voltage rail
and monitors it. This process continues
until the controller has enabled all voltage rails. When using voltage as the control variable, the controller can use either
a GPIO or a PWM signal as the enable
signal, depending on whether the design
requires rail tracking. You can also use
a combination of voltage and timing
control.
In Figure 1, each low-dropout regulator connects to two MSP430 linesone
for enabling and the other for monitoring. When time is the control variable, the
monitoring takes place via Port 1 (GPIO);
when voltage is the control variable the
monitoring occurs via Port 6 (ADC). The
MSP430 also provides a system reset and
has an input for power-down. The code
is fairly simple and does not require much
programming experience. When time is
the control variable, the first thing to do
is initialize the MSP430 and setup the
port and timer; this operation takes five
lines of code (see Listing 1, which is available with the Web version of this Design
Idea at www.edn.com). The next operation is to load the capture-and-compare
register zero (CCR0) with the first timing
interval and start the timer. When CCR0s
value is equal to the timers value, the first
voltage rail becomes enabled. CCR0 is
then loaded with the next time interval,

and the timer resets and restarts. When
CCR0 is equal to the timer value, the second voltage rail becomes enabled. This
operation repeats until all rails become
enabled.
Once all rails are enabled, a delay loop
enters the picture to ensure that the reset
pins on the low-dropout regulators have
time to come up. The TPS725xx family
has an open-drain, 100-msec reset function. Once the delay is complete, the
MSP430 checks each regulators reset line
to ensure that all rails are up. If all rails are
up, the MSP430 issues a system reset.
When voltage is the control variable, only
five lines of code are necessary to initialize the MSP430 (Listing 2, which is available with the Web version of this Design
Idea at www.edn.com). The next operation is to load registers R9, R10, and R11
with values that represent 3.3, 2.5, and
1.8V, based on a 3V ADC reference. The
first rail becomes enabled, and its output
voltage undergoes monitoring until it is
within specification, at which point the
next rail is enabled and monitored. This
operation repeats until all three rails become enabled. Once all the rails are enabled, the delay loop for regulator reset
activates, and the system reset occurs.
Once the MSP430 turns on all the voltage rails and applies the system reset, it
enters the monitor mode. It continually

checks the low-dropout regulators output voltage, via the reset or output pins,
depending on whether time or voltage is
the control variable. If a fault occurs, the
MSP430 enters an error routine. The
most obvious fault would be the loss of
a voltage rail, but other faults, such as
overvoltage and undervoltage, are also
amenable to monitoring. The actions
that the error routine takes depend on the
application. The simplest actions would
be to power down all rails, but programmability gives you complete control. One
final function is the powering down of
the voltage rails. An external signal, likely from the main processor, signals the
MSP430 to power down the processor
rails. In this example the power-down sequencing is just the opposite of the power-up sequence, but you can define any
sequence. One addition to the powerdown sequence could be to turn on dummy loads to discharge the output filter
capacitors. This design uses the TPS725xx low-dropout regulators because
they offer fast transient response and stability with any output capacitor. However, some applications may require large
output capacitors to maintain stability
and transient response. In these cases, the
ability to discharge these filter capacitors
improves MTBF.
Circuit provides leading-edge blanking

Michael OLoughlin, Texas Instruments, Dallas, TX
n isolated switch-mode power supplies using peak-current-mode control, generally the current-sense resistor senses the current on the primary side
of the power converter. Figure 1 shows a
typical circuit, in which R2 is the currentsense resistor that monitors the current.
The current-sense signal goes to the input of the PWM comparatorin this
case, the PWM comparators input
(ISENSE) of the controller IC. R3 and C1
provide an RC delay in an attempt to remove some of the leading-edge spikes on
the current-sense signal. Sometimes, the
RC delay circuit is insufficient for removing the false noise signals at the input of the PWM comparator. This Design
Idea shows how to suppress the false triggering signals caused by parasitic LC (in-
74 edn | May 29, 2003
ductance and capacitance),

T1
causing LC tanking and
false-peak current triggering
to the peak-current-limit
comparator.
The RC delay circuit in
R1
Q1
Figure 1 works for most apGATE DRIVE
plications in suppressing
voltage spikes that may falseUCC38517
ly trip the peak-limit-curR3
ISENSE
rent comparator. However,
some applications require a
leading-edge blanking cirR2
C1
cuit to suppress false
triggering. Figure 2
Figure 1
shows the typical current-sense signal that appears across R2. The leading- In this classic PWM-controller configuration, R2 is the sending
edge spike at time T1 occurs resistor for the output current.
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design
ideas
when the gate drive switches from low to

high and the parasitic capacitance from
the gate to the source of Q1 is charging.
Depending on the values of R1 and R2, a
large-enough leading-edge voltage spike
could falsely trigger the PWM comparator at the ISENSE pin. This problem is common in isolated dc/dc power converters.
To remove false triggering from the PWM
comparator, it is desirable to blank out the
leading-edge spikes that appear on the
current-sense signal. You can suppress
these leading-edge spikes by adding four
additional components to the circuit in
Figure 1. Figure 3 shows the extra cir-
must select R3 to provide

some current-limiting
protection for transistor
Q2. R4 must supply sufficient base drive, IB, current
to Q2. You select R5 such
T1
that its current is 10% of
the base-drive curFigure 2
rent. You choose the
value of C2 to keep transistor Q2 saturated for two RC time constants. You can use the following equations to calculate the resistor and
capacitor sizes:
R4 =
VGATEVBE
,
IB
R5 =
VGATEVBE
IB /10
C2 =
TBLANK
,
2(R 4 + R 5 )
GATE DRIVE
ISENSE
R4
and
C2
Q2
R5
Figure 3
Transistor Q2 suppresses (blanks) leading-edge
spikes that could falsely trigger a PWM comparator.
cuitry necessary to provide leading-edge

blanking. The gate drive from the PWM
circuit activates the leading-edge blanking circuit. Transistor Q2 suppresses the
leading-edge current-signal spike. Components R4, C2, and R5 set up the amount
of time the leading edge of the currentsense signal is suppressed from the PWM
comparator.
Selecting the components for the leading-edge blanking circuit is simple. You
select Q2 with sufficiently low saturation
voltage, VSAT, to suppress the leading edge
of the current-sense signal. You select R4
and R5 to drive transistor Q2 into saturation. You then select C2 to set up the timing for the circuit. To select transistor Q2,
the maximum collector-to-emitter voltage, VCE, must be less than the gate-drive
voltage. The transistor saturation voltage,
VSAT, must be low enough to suppress the
voltage spike at the PWM comparators
input. For most applications, you can get
away with using a 2N2222 transistor. You
76 edn | May 29, 2003
The leading-edge spike in this waveform could

falsely trigger the PWM comparator in Figure 1.
After you add the leading-edge blanking circuit to the power module, it clamps
the leading-edge voltage spikes and allows
the converter to operate correctly. Figure
5 shows the current-sense waveform.
Leading-edge noise spikes on the currentsense signal can cause instabilities in peakcurrent-mode-control power-supply designs. Usually, you can resolve these issues
with an RC filter at the input of the peakcurrent-limit comparator. In some instances, the noise disturbance caused by
parasitic capacitance and gate-drive current can cause the PWM comparator to
trip falsely. In these instances, the supply
requires a leading-edge blanking circuit
similar to this one.
where VGATE is the maximum gate-drive

voltage of the PWM comparator, and
TBLANK is the amount of leading-edge
blanking time required.
Another power-supply design has current-sense spikes
so large that the module
Figure 4
will not regulate. This design requires the implementation of the leading-edge
blanking circuit in Figure 2.
The design, a 200-kHz flyback
converter, requires a leadingedge blanking time, TBLANK,
time of 200 nsec. The leadingedge blanking circuit requires
a maximum base current, IB,
Without leading-edge suppression, the spikes turn off Q1
of 42 mA. The IB specificain Figure 1.
tions require R4 to be 275
and R5 to be 200. To attain
the 200-nsec delay, C2 needs to
be approximately 390 pF.
Figure 5
Q2, a 2N2222 current-suppression transistor, requires a
current-limiting resistor, R3,
of roughly 1 k. The PWM
comparators input, ISENSE, has
a peak threshold of 1.5V. Figure 4 shows the current-sense
signal of the flyback converter before the addition of the
suppression circuit. The waveform shows that leading-edge
After adding the blanking circuit of Figure 3, the converter
spikes turn off switch Q1.
works normally.
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design
ideas
MOSFETs reduce crosstalk effects

on analog switches
Stanley Chen, Global Mixed-Mode Technology, Taipei, Taiwan
ome cost-effective analog
12
X0
multiplexer/demultiplexer ICs,
16
AUDIO CH1
13
1k
VCC
X1
C1
2
CH1L IN
such as the CD4053 and
Y0
1 F
1k
1
CH1R IN
Y1
CD4066, find frequent use as signal
14
1k
IC1
X
5
AUDIO CH2
AUDIO OUT
Z0 CD4053
15
distributors. These digitally con3
Y
CH2L IN
Z1
1k
AUDIO L OUT
trolled analog switches have low on4
6
CH2R IN
Z
INH
AUDIO R OUT
11
resistance. However, with
A
Figure 1
10
all channels in the same
B
9
C
Q2
package, crosstalk can be annoying
7
8
VEE
GND
2N3904
and unavoidable.
10k
5V
Figure 1 provides a cost-effective
CH SELECT
CH1
and viable method of solving this
10k
problem. By simply adding some nQ2
Q4
Q5
Q3
CH2
channel MOSFETs, such as the
2N7002
2N7002
2N7002
2N7002
2N7002 or 2N7000, the crosstalk effect becomes negligible. When the
Channel Select signal is high, the
CD4053s input pins A, B, and C assume a level of nearly 0V. This operation selects Channel 1. Therefore, the
Y output connects to Y0 and Z to Z0. By using a few low-cost MOSFETs, you can drastically reduce crosstalk effects in an analog multiplexer.
Meanwhile, the Channel Select signal
turns on Q4 and Q5, thereby drastically at- nal is set low, YY1 and ZZ1, and Q2 crosstalk decreases by more than 40 dB.
tenuating the Channel 2 signal at Y1 and and Q3 turn on to attenuate the crosstalk Add to that the analog switchs internal
Z1. The crosstalk effect simultaneously effect. For the 2N7002, the RDS(ON) resist- rejection ratio, and the total crosstalk redecreases. When the Channel Select sig- ance is several ohms; therefore, the jection could be as high as 80 dB.
Grounded resistor tunes oscillator

Vladimir Tepin, Taganrog, Russia
o vary the frequency of any sineSW
wave oscillator, you should use a pair
C2
of ganged variable resistors, and you
1 nF
IC1
IC2
should thoroughly match their characOUTPUT
teristics over the entire variation range to
LT1361
satisfy the oscillators balancing condiC1
tions. This restriction leads to problems
10 nF
in the tuning range and high cost, thereR3
by limiting the range of applications. The
R1
sine-wave oscillator in Figure 1 is free of
R2 4.9k
1k
the cited disadvantage. You can tune it
over a wide frequency range using only
variable resistor R1. The oscillator
Figure 1
requires no balancing, so no
matching problems arise. The variable In this sine-wave oscillator, the output frequenresistor connects to ground, an advanta- cy is dependent only on the value of the
geous fact in many applications. Like grounded resistor R1.
78 edn | May 29, 2003
most classic sine-wave RC oscillators, the

implementation comprises an operational amplifier, IC2, with two feedback
loops. One loop is a frequency-independent, positive-feedback loop using
two fixed resistors, R2 and R3, in this example. The other loop is frequency-dependent. This loop uses capacitors C1 and
C2; variable resistor R1; and a single-pole,
double-throw analog switch, IC1, driven
by a periodic sequence of square-wave
pulses applied to the SW input.
Assuming a switching frequency,
FS1/T, much higher than the oscillation
frequency and assuming that the pulse
width, , is half the switching period
(0.5T), the approximate voltage transwww.edn.com
design
ideas
fer function of the frequency-dependent

feedback loop is:
H(s) =
cillation condition does not depend on

R1. It thus becomes obvious that controlling grounded resistor R1 results only
in the variation of the oscillation frequency and does not affect the condition
for oscillation. This situation means that
you can tune this oscillator over a wide
range of frequencies, preserving the output waveform.
PSpice simulations prove the possibility of tuning the oscillation frequency
over three decades (20 Hz to 20 kHz) by
varying R1 from 1.2 M to 1.2 k. This
s2 + s 0d1 + 02
,
s 2 + s 0d 0 + 0 2
where 01/2RC1C2 is the oscillation
frequency, d0C1/C22C2/C1, and
d12C2/C1. Using this function and
assuming the transfer coefficient of the
positive-feedback circuit to be
R2/(R2R3), you obtain the oscillation
condition in the form d1/d2
2C2/C1/(2C2/C1C1/C2). The os-
design uses an LT1361 (www.linear.com)

for IC2, R21 k, R34.9 k, C110 nF,
C21 nF, and FS500 kHz. The outputvoltage amplitude is 3.2 to 3.3V. The total harmonic distortion in the 0- to 100kHz band does not exceed 3%. Its useful
to note that, because the oscillation frequency is proportional to the conductance of the variable resistor (G11/R1),
you can use the oscillator as a linear, wideband conductance-to-frequency or resistance-to-period converter.
Obtain higher voltage from a buck regulator

Ajmal Godil, Micrel Semiconductor, San Diego, CA
everal semiconductor vendors
current-mode buck controllers have
input-voltage ranges of 30 to 36V
but have output-voltage ranges from the
reference voltage to approximately 6V.
This output-voltage constraint arises

from the common-mode-voltage limitation of the current-sense amplifier. In
real-world applications, the power-supply designer must be able to generate
high output voltage for printers, servers,

routers, networking, and test equipment. Using a conventional buck regulator to generate higher voltages is a
challenge. The circuit in Figure 1 meets
VIN 27V
C1
22 F
D1
SD103BWS
R1
100k
C4
0.1 F
C2
22 F
IC1
MIC2182
1
HSD 16
SS
2 PWM
VSW 15
3
COMP
BST 14
4 SGND
LSD 13
5 SYNC
PGND 12
6
VDD 11
EN/UVLO
10
7 FB
VIN
8
VOUT 9
CSH
C10
100 pF
C5
1 nF
Q1
SI4800DY
C3
0.1 F
Q2
SI4800DY
R2
40m
VOUT
20V AT 2.5A
D2
B140
R3
16.2k
C6
0.1 F
C7
47 F
R4
100
R5
10k
L1
10 H
C8
47 F
R6
1.05k
C9
4.7 F
Q3
1
Figure 1
MMBT3906
R7
91
5
3
IC2A +
MIC6211
_ 4
2
R8
100
R9
1k
You can generate 20V output using a standard, current-mode buck regulator.
80 edn | May 29, 2003
www.edn.com
design
ideas
the challenge by using an external op

current through R8 is 400 A
98
amp, a small-signal pnp transistor,
((20.0420)/100), which is also
96
and a low-output-voltage buck reguthe current through R9 and R4
94
(via Q3). This current generates
lator to deliver 20V output voltage
a voltage drop of 40 mV across
from a 27V input supply for load cur92
R4 (400 A100). The conrents as high as 2.5A. You can easily
EFFICIENCY
90
(%)
trollers VOUT pin connects to
program the circuit to provide highthe internal 5V regulator
er load currents by merely lowering
88
(VDD) and R4; the other side of
the sense resistor, R2. IC1, the con86
troller in Figure 1 is the MIC2182,
R4 connects to the CSH pin. The
0
0.5
1
1.5
2
2.5
3
voltage on the VOUT pin is 5V,
and IC2, the operational amplifier, is
ILOAD (A)
the MIC6211. Resistors R3 and R6
and the voltage on the CSH pin
F
i
g
u
r
e
2
program the output voltage as
is 5.04V. The voltage difference
follows: VOUT20VVFB(1R3/R6).
between these two pins is exactThis curve shows the efficiency of the regulator in Figure 1.
CSH (Pin 8) and VOUT (Pin 9) of
ly the voltage drop across R2.
the buck controller normally connect voltage drop across R2 from 20V down to The simple circuit in Figure 1 allows you
across the sense resistor, R2, for output 5V, which is within the input common- to achieve greater than 95% efficiency for
voltages as high as 6V. The controller as- mode range of the internal current-sense load currents as high as 2.5A with
serts current limit when it senses ap- amplifier of the buck regulator. You can VOUT20V, using a conventional lowproximately 100 mV across these two readily understand the circuit operation output-voltage, current-mode buck regpins. In the case of VOUT20V, the oper- by assuming a voltage drop of 40 mV ulator. Figure 2 shows the efficiency of
ational amplifier and Q3 level-shift the across R2 for a load current of 1A. The the regulator.
82 edn | May 29, 2003
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design
ideas
Light a white LED from half a cell

hether you use them as indicators or to provide illumination,
LEDs are hard to beat in efficiency, reliability, and cost. White LEDs are
rapidly gaining popularity as sources of illumination, as in LCD backlights, but
with forward voltages typically ranging
from 3 to 5V, operating them from a single cell presents obvious difficulties. This
design exploits the ultralow operating
voltage of a single-gate Schmitt inverter,
such as the Texas Instruments (www.
ti.com) SN74AUC1G14 or the Fairchild
(www.fairchildsemi.com) NC7SP14 (Figure 1). When you first apply battery power, Schottky diode D1 conducts, and the
familiar Schmitt-trigger astable multivibrator starts to oscillate at a frequency determined by timing components C2 and
R1. When IC1s output goes high, transistor Q1 turns on, and current begins to
ramp up in inductor L1. The maximum,
or peak, level of inductor current is
IL(PEAK)(VBATTVCE(SAT))tON/L1, where
VBATT is the applied battery voltage,VCE(SAT)
is Q1s saturation voltage, and tON is the
duration of the high-level pulse at the
Schmitt triggers output. If Q1s saturation
voltage is, for example, less than 50 mV,

you can ignore VCE(SAT) and simplify the
expression to IL(PEAK)VBATTtON/L1.
At the end of tON, when the inverter
output goes low, Q1 turns off, and the
voltage across L1 reverses polarity. The
resulting flyback voltage immediately
raises Q1s collector voltage above VBATT
and forward-biases the LED and D2,
which appear in series. This action illuminates the LED with a maximum forward current equal to IL(PEAK) and raises
IC1s supply voltage, VBOOT, to a diode
drop above VBATT. D1 is now reverse-biased and remains so for as long as the
circuit continues to oscillate. The resulting bootstrapped supply voltage
for IC1 ensures that the astable multivibrator continues to operate even when
VBATT falls to very low levels. You should
choose values for C2 and R1 to produce
a time constant of microseconds, thereby allowing a small inductance value for
L1. For example, a test circuit using values of C268 pF, R139 k, and L147
H produces an operating frequency of
approximately 150 kHz at VBATT1V.
The resulting value of tON3 sec leads
Light a white LED from half a cell ............87

LED driver delivers
constant luminosity ......................................88
Get more power
with a boosted triode ....................................90
White-LED driver touts
high efficiency ................................................92
to a peak inductor current of approximately 65 mA and produces excellent

brightness in the white LED. Even with
VBATT as low as 500 mV, the corresponding peak current of 33 mA produces
reasonable LED intensity.
The inductance value should be as low
as possible to maintain a high peak current and, hence, adequate LED brightness at the lowest supply voltage. However, L1 should not be too small, or the
peak current could exceed the LEDs
maximum current rating when VBATT is
at a maximum. Remember that the inductor should be adequately rated to en-
VBATT
VBATT
Figure 1
D1
10k
D2
L1
Q2
D2
LED
SINGLE
CELL
1.5V
NOMINAL
IL
VBOOT
D3
R1
C1
10 F
C3
1 nF
5
2
C2
C1
10 F
4
IC1
3
SN74AUC1G14
OR NC7SP14
VBOOT
VAUX
Q1
R2
2.2k
C4
GND
(a)
NOTES: D1, AND D3 ARE BAT42s OR SIMILAR.

D2 IS A 1N4148 OR SIMILAR.
TO PIN 5,
IC1
GND
(b)
This circuit produces dazzling intensity in a white LED from very low battery voltages (a). A modification allows even lower battery voltages (b).
www.edn.com
June 12, 2003 | edn 87
design
ideas
sure it does not saturate at the highest

value of peak current. Switching transistor Q1 should have very low saturation voltage to minimize losses and produce the highest possible peak current.
The addition of D3 and C4 enables the
circuit to generate an auxiliary supply
voltage, VAUX, which you can use to drive
low-power circuitry without adversely
affecting the LEDs intensity. With a battery voltage of 1V, the test circuit produces good light intensity in the white
LED and delivers almost 1.5 mA at 4.7V
to the auxiliary load. Even at VBATT500
mV, the circuit delivers 340 A into a
10-k load and maintains reasonable

LED brightness. Note that IC1 cannot
take power from the auxiliary rail, because VAUX can easily exceed the maximum voltage rating of the two suggested device types.
The minimum start-up voltage depends largely on the device you use for
D1. Tests using a high-quality Schottky
diode produce a minimum power-up
voltage of just 800 mV. You can further
reduce this level by replacing D1 with pnp
transistor Q2 (Figure 1b). This modification allows the test circuit to start up at
just 650 mV at room temperature. Note,
however, that Q2s collector-base junction

becomes forward-biased under quiescent
conditions, which results in wasted power in its base-bias resistor. Despite its simplicity, the circuit can produce spectacular results with high-brightness LEDs.
The Luxeon range of LEDs from Lumileds (www.lumileds.com) allows the
circuit to demonstrate its prowess. With
L1 reduced to 10 H and VBATT1V, the
circuit generates a peak current of 220
mA in a Luxeon LXHL-PW01 white LED,
resulting in dazzling light intensity.
LED driver delivers constant luminosity

Israel Schleicher, Bakersfield, CA
At first glance, IAVE dehe circuit in Figure 1 is
L
similar in principle to
pends strongly on VIN. But
R1
close examination of the
that of a previous Design
10k
R2
C
logarithmic term reveals
Idea (Reference 1) but offers
2.2k
D2
that, with a proper selection
improved, more reproducible
R3
LED
of VB, the logarithmic term
performance. The output
4.7k 1N4148
VIN
can become a sharply decurrent is almost constant
VD
clining function of VIN. The
over an input-voltage range of
Q2
D1
logarithmic term thus fully
1.2 to 1.5V and is insensitive
2N2222
Q1
compensates for the term
to variations of transistor
1N4148
2N2222
VB
VIN2 in the expression. That
gain. Transistors Q1 and Q2
form an astable
compensation is precisely
Figure 1
flip-flop. R1 and C
the purpose of the diode,
NOTE:
define the on-time of Q2.
D1, in series with the base of
WHITE LED REQUIRES R3 AND D2.
During that time, Q1 is off,
Q1. The circuit drives a
and the voltage at the base of This circuit delivers virtually constant luminosity for a white or a yelhigh-brightness yellow or
Q1 and the current in induc- low LED.
white LED. Table 1 shows
tor L ramp up. When the voltthe proper component seage at the base of Q1 reaches approxi- tively. When the current through the LED lection for both colors. Table 1 also shows
mately 0.6V, Q1 turns on, and Q2 turns falls to zero, the voltage at the collector of some measured results at VIN1.35V. Beoff. This switching causes flyback action Q2 falls sharply, and this circuit condition cause the voltage across the white LED
in inductor L. The voltage across the in- triggers the next cycle. Assuming the jus- falls from 3.9 to 3.1V during flyback, caductor reverses, and the energy stored in tifiable approximation that the saturation pacitor C subtracts current from the
the inductor transfers to the LED in the voltage of Q2 is close to 0V and that the amount available to the base of Q1. This
form of a down-ramping pulse of cur- LEDs forward voltage, VD, is constant, subtraction might retrigger the circuit
rent. During flyback time, voltage across you can easily derive the expression for before the current in L falls to zero. The
the average dc current through the LED: addition of R3 and D2 solves this problem.
the LED is approximately constant.
During flyback, the current that flows
The voltage for yellow and white LEDs
V + VDVB
V2 R C
I AVE = IN 1 log e IN
.
through R3 compensates for the current
is approximately 1.9 and 3.5V, respec2 VDL
VINVB
withdrawn through C.
TABLE 1COMPONENT SELECTION FOR YELLOW OR WHITE LED

LED
Yellow
White
L (mH) C (pF)
1
2
470
1800
88 edn | June 12, 2003
D1
Current drain LED current Frequency

(mA)
(mA)
(kHz)
0.1
1N4003
5.6
3.3
40
0.2
1N752
12.4
3.7
15
Power-conversion
efficiency (%)
83
78
Reference
1.Nell, Susanne, Voltage-to-current
converter drives white LEDs, EDN, June
27, 2002, pg 84.
www.edn.com
design
ideas
Get more power with a boosted triode

Dave Cuthbert, Boise, ID
his Design Idea is a reprint of an
earlier one that contained errors in
graphics (Reference 1). Even though
6L6 beam-power tubes have been around
for 66 years, they are still quite popular
for use in electric-guitar amplifiers, and
its cousin, the 6CA7 (EL34) power pentode, is a favorite among audiophiles. The
developers of these tubes designed them
for pentode-mode operation, and they
deliver maximum audio power in this
mode. On the other hand, many audiophiles prefer triode-mode operation and,
until now, had to be content with a 50%
reduction in output power. This reduction means that they require larger power supplies and twice as many expensive
tubes to obtain pentode power from a triode amplifier. Figures 1a, 1b, and 1c
show the 6L6 connected as a pentode, a
400V
TABLE 1PENTODE, TRIODE, AND BOOSTED-TRIODE PARAMETERS

Amplifier
Pentode
Triode
Boosted triode
DC plate
current (mA)
75
75
75
Grid bias
(V)
14
32
44
true triode, and a boosted triode, respectively. The boosted-triode configuration allows pentodes to produce pentodelike power while operating in a
true-triode mode. To understand the operation of the boosted triode, its useful
to review some vacuum-tube theory. The
6L6 is a beam-power tube and has cathode, control-grid, screen-grid, suppressor-grid, and plate electrodes. The suppressor grid is actually a virtual
suppressor grid provided by two beamforming plates, but you can treat the 6L6
400V
Grid swing
(V)
22
64
88
Output power
(W)
11
6
10
beam-power tube as a pentode. You can

think of a pentode as an n-channel JFET
with the following electrode functions:
Thermionic cathode: source of electrons (corresponds to the JFET source);
Control grid: controls the cathode
current; operated at a negative potential
relative to the cathode (corresponds to
the JFET gate);
Screen grid: electrostatically screens
the control grid from the plate, thereby
reducing the effect that the plate voltage
has on the cathode current; operates at a
400V
Figure 1
6L6
6L6
1 F
6L6
1 F
1 F
100V
47k
47k
250V
47k
14V
32V
(a)
44V
(c)
(b)
A pentode (a) can deliver much more power than a triode (b), unless you use a boosted-triode configuration (c).
250
0
2.5
5
7.5
10
12.5
15
17.5
20
22.5
25
LOAD
LINE
200
PLATE
CURRENT
(mA)
150
100
50
100
200
300
400
500
600
700
800
300
0
10
250
20
200
30
40
PLATE 150
CURRENT
(mA) 100
50
60
70
50
80
90
LOAD
LINE
0
50
0
PLATE VOLTAGE (V)
Figure 2
The load lines for a pentode show that the plate

can draw 150 mA at a plate voltage of only 50V.
90 edn | June 12, 2003
100
200
300
400
500
600
700
800
PLATE VOLTAGE (V)
Figure 3
A pure triode needs 200V plate voltage to

draw 150 mA.
www.edn.com
design
ideas
positive potential relative to the cathode;

1.5k
100V DC
Suppressor grid: prevents secondary
TRIAD N-48X
1N4007
20W
40 mA
electrons from leaving the plate and trav+
(PD=3W)
2SC4953 WITH HEAT SINK
eling to the screen grid; operates at the
120V AC
120V AC 22O F
OR SIMILAR
250V
cathode potential; and
1N5378B
Plate: collects the electrons (corresponds to the JFET drain).
Figure 2 shows the pentodes characA 100V screen-grid power supply transforms a normal triode into a boosted
teristic curves for control-grid voltFigure 4
triode.
ages of 0 to 25V and a screen-grid
voltage of 250V. Note the idealized load 3 shows how the triode curves differ from 100V, rather than 200V as with the pureline and that the tube can draw a plate the pentode curves. The curves represent triode-mode circuit. You can obtain sigcurrent of 150 mA at a plate voltage of control-grid voltages of 0 to 90V. Note nificantly higher power with boosted-trionly 50V. High voltage gain, high plate the load line and that, in triode mode, the ode amplification and still maintain the
impedance, and high output power char- plate cannot draw 150 mA at a plate volt- characteristics of triode amplification. In
acterize pentode-mode amplification. By age lower than 200V. This fact greatly lim- Spice simulations of three single-ended
connecting the screen grid directly to the its amplifier efficiency and power output. Class A audio amplifiers using MicroCapplate, you can operate the tube in triode However, in spite of the limited output 7 evaluation software (www.spectrummode. Low voltage gain and low output power, some people still prefer triode soft.com), the control-grid bias for a quiimpedance characterize this mode. Figure mode because they claim that it produces escent plate current is 75 mA, and the ac
a superior-sounding grid signal is just short of amplifier clip300
amplifier.
ping. The transformer ratios provide a
0
10
For the boosted-tri- plate-load impedance of 5 k for the pen250
20
ode circuit in Figure 1c, tode and 3 k for both the triode and the
200
30
you simply add a 100V boosted triode. Table 1 details the param40
PLATE 150
screen-to-plate power eters.
50
CURRENT
(mA) 100
60
supply (Figure 4) to the
70
standard triode-ampli- Reference
50
80
1. Cuthbert, Dave, Get more power
fier circuit. This ad90
0
with
a boosted triode, EDN, April 3,
dition
shifts
the
triode
LOAD
LINE
50
characteristic curves 2003, pg 72.
0
100
200
300
400
500
600
700
800
100V to the left (Figure
PLATE VOLTAGE (V)
5). Note the load line
With a boosted triode, the plate can draw 150 mA and that the plate can
Figure 5
now draw 150 mA at a
with a plate voltage of 100V versus 200V for a
plate voltage of only
pure triode.
White-LED driver touts high efficiency

Dimitry Goder, Sipex Corp, San Jose, CA
hite LEDs, the most recent addition to the LCD backlight, find
common use in providing backlight for color LCDs. Thanks to their size
and white-light output, they appear in
small, portable devices with color displays,
such as PDAs and cellular phones. Like
other LEDs, a white LED needs a constantcurrent sourcetypically, on the order of
15 to 20 mA. The forward voltage of a
white LED is approximately 3.5V. Most
products use multiple LEDs to provide adequate backlight for a display. Because the
LEDs brightness depends on its forward
current, these multiple diodes commonly
92 edn | June 12, 2003
connect in series to ensure that the same

current flows through each of them. You
need approximately 14V to forward-bias
four series-connected LEDs, starting from
the nominal operating voltage, 2.7 to 4.2V,
of a single-cell lithium-ion battery. Boost
regulators usually provide this operating
voltage. A current-sense resistor, which
you insert in series with the LEDs, closes
the feedback loop. However, it is important to minimize the voltage drop across
this resistor to increase efficiency. Currently available integrated boost regulators
commonly use a 1.24V bandgap voltage as
the feedback reference, which results in
1.24V loss across the current-sense resistor, a loss that represents approximately
7% loss in efficiency. Figure 1 shows an interesting LED-drive circuit.
You use the SP6682, a standard, regulated charge-pump circuit, in an unusual manner to control the external switch,
Q1. This IC incorporates an internal 500kHz oscillator, which would normally
drive charge-pump capacitors to double
the input voltage. The circuit in Figure 1
uses no charge-pump capacitors. Instead,
the oscillator output appears on Pin 7
and drives Q1 on and off. Q1, L1, D1, and
C1 function as a conventional boost regwww.edn.com
design
ideas
ulator, which builds up voltage across C1.

When this voltage exceeds the sum of the
diodes forward drop, current starts to
flow. The circuit senses current across R1
and compares it with a 0.3V reference
voltage inside the chip. This circuit pro-
vides efficiencies as high as 87%, a figure

that exceeds that of any integrated boost
regulator. Several factors are responsible
for the increased efficiency. First, the chip
integrates the 0.3V reference voltage,
which is significantly lower than the typVIN
2.7 TO 4.2V
Figure 1
L1
4.7 H
D1
3
VIN
C2N
NO CONNECT
NO CONNECT
NO CONNECT
NO CONNECT
PWM IN
10
C1
1 F
Q1
Si1304
2
1
SP6682
ENABLE
VFB
8
5
R1
15
This circuit uses a charge-pump IC to provide power to a series string of LEDs.
94 edn | June 12, 2003
ical 1.24V. This reference voltage appears

in series with the LEDs and therefore
constitutes an efficiency loss proportional to the value of the reference. Second, a discrete MOSFET provides low
on-resistance and high switching speed,
parameters superior to those of any integrated switch.
Q1 is a low-cost device that comes in a
tiny SOT-23 package. Also, the excellent
drive capability of the charge-pump IC
ensures low switching losses. By changing the type of the MOSFET you use, you
can make a trade-off between desired efficiency and cost. The breakdown voltage
of the MOSFET limits the maximum
output voltage; you can adjust the voltage to drive a system with as many LEDs
as you need. (Larger displays use eight to
12 LEDs.) For dimming purposes, applying a PWM signal to the Enable pin
causes the regulator to shut down and
restart. This function allows you to precisely control LED brightness.
www.edn.com
design
ideas
Gate-drive method extends supplys input range

John Betten and Robert Kollman, Texas Instruments, Dallas, TX
ndustrial and telecom applications often require a nonisolated, lowvoltage supply from a high-voltage input. IC manufacturers have responded to
that need with the application of highvoltage processes and offer control ICs
that work to 50V and higher. That voltage is sometimes insufficient, and you
need further design techniques to extend
the input voltage. The buck converter in
Figure 1 represents one such technique.
In addition to allowing circuit operation
over a wide input-voltage range, the
technique reduces power dissipation, because the control circuit does not operate
directly from VIN. The circuit uses a linear regulator and a source-switched driver to buffer a control IC from a line whose
voltage is as high as 110V. When you apply the input voltage, current flows
through resistor R2 and zener diode D2,
clamping the gate voltage of FET Q1 to
9.1V. C2 reaches a voltage of approximately 6V, which is equal to Q1s gate
voltage minus its typical turn-on threshold of 3V. FET Q1 now acts as a crude linear regulator and allows the control circuit to become active.
The source-switched driver of Q2, Q4,
and Q5 then comes into play to allow the
supply to come into regulation. The
TL5001s open-collector output switches
to a low state to turn on the main power
switch, Q3. With the gate of FET Q5 also
held at 9.1V and the output pin of the
TL5001 low, current flows through Q5s
Gate-driven method extends

supplys input range......................................99
Active-clamp/reset-PWM IC
becomes more versatile ............................100
Circuit provides
hiccup-current limiting................................102
Microcontroller provides
SRAM battery backup ................................104
Positive regulator makes
dual negative-output converter................106
Analog switch frees stuck I2C bus ............108
J1
VIN
20 TO 110V DC
GND
1
2
R2
40.2k
0.5W
Q1
SI2320DS
Q2
MMBT3904
Figure 1
C4
R3
0.047 F 7.15k
L1
1 mH
VCC
DTC
OUT 1
Q5
SI2320DS
R4
402
IC1
FB TL5001AID
7 RT
R6
30.1k
Q3
IRFR6215
3
D1
BAS16
3 COMP
4
R5
44.2k
2
1
Q4
MMBT5401
C2
0.1 F
C3
470 pF
C1
0.1 F
200V
R1
1k
SCP
C5
0.01 F
GND
FREQUENCY200 kHz
C7
1 F
D2
9.1V
BZX84C9V1LT1

D3
C6
MURS120T3
100 F
16V
1
2
J2
12V, 0.2A
GND
R7
4.99k
R8
2.74k
C8
0.01 F
A buck converter uses switched-source gate drive to generate high output voltages.
www.edn.com
June 26, 2003 | edn 99
design
ideas
drain-to-source pins. The amount of

drain current that flows is equal to:
(9.1VQ5s turn-on thresholdIC1s Pin
1 saturation voltage)/R4. In this example,
this current is nominally approximately
12 mA. Because most of this current
flows through R1, the value of R1 sets the
voltage amplitude used for the gate drive
of Q3. With a value of 1 k for R1, the
voltage across it is 12V. Transistors Q2 and
Q4 form an npn/pnp pair to quickly
switch gate-drive current into and out of
Q3. The base-emitter junction of Q4 conducts when a voltage drop exists across
R1. This conduction quickly pulls down
the gate of Q3 from VIN to approximately
11.2V (12VVBE). Because Q3 is a p-
channel FET, pulling the gate to 11.2V

lower than the source turns it on. When
current is not flowing in R1, the base of
Q2 pulls up to VIN, a voltage that forwardbiases its base-emitter junction.
The gate of Q3 quickly charges to nearVIN potential, thereby turning off Q3. This
drive circuit is fast, because none of the
transistors operates in a saturated mode;
therefore, Q3 can attain 0.5-sec turn-on
time. This speed means that the circuit
can achieve reasonably high operating
frequencies with the low duty cycles you
encounter in a high-voltage input. You
can scale this gate-drive circuit for higher or lower input voltages by the proper
selection of the drain-source (or collec-
tor-emitter) ratings of Q1, Q3, Q4, and Q5.

All must have voltage ratings greater than
the input voltage, and all, except for Q1,
should also be able to switch at high
speeds. The addition of diode D1 offers
two advantages. It allows the control circuit to operate after start-up from the
output voltage, rather than the input
voltage. This method is more efficient,
inasmuch as the input voltage is relatively high. A bias-power savings of approximately sevenfold is the result. Also,
adding D1 pulls the source pin of Q1 to
approximately 11.2V, thus Q1 turns off.
All bias power to the controller now
comes from the output voltage, and Q1
no longer dissipates power.
Active-clamp/reset-PWM IC becomes more versatile

Gowripathi and M Sindhu, ITI Ltd, Bangalore, India
he UCC3580 (www.ti.com), IC1 in
Figure 1, is an active-clamp/resetPWM IC that has all the requisites of
a power-supply IC except for current
limit. You can use the shutdown pin (16)
for this purpose (see the UCC3580 data
L1
sheet). But when the shutdown pin activates, the soft-start capacitor normally
connected to Pin 15 discharges, and the
converter starts again, resulting in hiccup
mode. Poor dynamic response ensues because of this circuit behavior. The prob-
lem becomes especially serious when you

hot-plug a load card, with typically 100F decoupling across the converters output, into the motherboard. You can avoid
this problem by not using the shutdown
pin for current limiting. Instead, use the
T2
T1
R1
VIN
D1
SYNCHRONOUS
RECTIFIER
C3
C2
C1
VOUT
5V
Q2
V
D3
D2
V
R4
2.7k
Q1
Figure 1
LM358
+
C5
0.1
F
R6
100
3
14
UCC3580
IC1
R7
510k
R3
10k
C6
0.1 F
R5
10k
D5
R2
0.1
D4
12V
ZENER
C4
10 F
12
D6
8
D7
V
This circuit does not use the shutdown pin of the PWM IC; instead, it relies on the error amplifiers output to provide current limit.
100 edn | June 26, 2003
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design
ideas
error amplifiers output pin, Pin 12. Q1 is

the main switch, T1 is the main transformer, and C1 is the bulk capacitor. Q2,
D3, and D4 provide power (V) for IC1
during start-up and current limit. D1 and
C2 rectify and filter the voltage from the
auxiliary winding of T2 to power the control circuit during normal operation. R2
senses the current in the main switch, Q1.
The LM358 op amp provides current
limit. Diode D6 isolates the op amp and
Pin 12 of IC1 during normal operation.
According to the data sheet of UCC3580,
the error amplifiers output should pull
down to 0.3V or lower for 0% duty cycle.
This condition forces you to use a negative supply (V) for the op amp to obtain
rated performance. As Figure 1 shows, the
same supply voltage (V) serves for the
PWM IC and the op amp. You can obtain

the negative supply voltage (V) for the
op amp from another winding on T2.
Even though the voltages that T2 generates decrease in foldback condition, the op
amp continues to obtain V from Q2. A
negative voltage (V) from T2 is adequate
for proper operation of the op amp. The
Schottky diode, D7, from Pin 12 to ground
protects the error amplifiers output from
large negative voltages.
The inverting input of the op amp
senses the peak pulse voltage across R2.
Diode D5 helps C5 to charge to peak voltage (peak detection), and R3 helps to discharge C5 when the peak voltage across R2
decreases. Use a slow diode for D5. The
reference voltage at the noninverting input has two componentsfirst, from the
fixed 5V reference (Pin 14) of IC1; second, from the voltage generated by the T2
winding. This voltage decreases with output voltage, and voltage foldback occurs
at the noninverting input. The 50-mV
component from the fixed 5V reference
is necessary for start-up. As the current
limit starts, the output voltage starts to
decrease, and the noninverting-input
voltage also decreases, causing foldback.
With this circuit, if the current limit starts
at an output current of 10A, the output
short-circuit current is 2A. The output
recovers even with minimal current hysteresis. The positive voltage that the T2
winding generates decreases from 13V
just before current limit to 3V at short
circuit. This circuit does not influence the
transient response of the converter.
Circuit provides hiccup-current limiting

CH How and KP Basu, Multimedia University, Cyberjaya, Malaysia
urrent-limit protection is an
essential feature for power-supply
systems. The three major types of
current-limit-protection mechanisms
are constant, foldback, and hiccup. Hiccup current limit performs the best of
the three types; however, the implementation is rather complex. In this scheme,
upon detection of an overcurrent event,
the whole power supply shuts down for
an interval before it tries to power itself
up again. The cycle repeats until the

overcurrent fault disappears. With such
operation, the dissipation in the power
supply itself is minimal. You can incorporate the circuit in Figure 1a into the
PWM circuit of a switch-mode power
supply to implement the hiccup feature.
Figure 1b represents a typical shuntvoltage regulator to regulate the VCC that
powers the PWM controller.
Most PWM controllers have an un-
VCC
CLAMP
12k
200k
110k
Q1
2N2222A
dervoltage-protection feature, in which

the internal circuitry shuts down whenever its VCC drops below a certain threshold. For example, assume that the circuit
in Figure 1a works with a UCC3570
PWM controller. In this chip, an excessive
current that causes the Count pin to exceed 4V or the ILIM pin to exceed 0.6V
sets the shutdown latch. This action then
forces the PWM controllers output to go
low and discharge the soft-start capaci-
IC1
TL431
Q2
2N2907A
D2
1N4148
R1
R2
11k
10
C1
100 F
100
VAUX
D1
1N4148
510
CLAMP
Q3
2N2222A
Figure 1
SS
600
(a)
C3
0.1 F
C2
1 F
D3
1N4148
600
BD677A
Q4
VCC
DZ
12V
1 F
TO SOFT-START
PIN OF THE PWM IC
(b)
You can incorporate hiccup circuitry (a) into your PWM-control scheme, using a typical shunt regulator (b) to regulate the supply voltage to the PWM chip.
102 edn | June 26, 2003
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design
ideas
tor, C2. The discharge current of C2 causes Q3 and, hence, Q2 to turn on for a short
interval to charge the timing capacitor,
C1. The moment the voltage across C1
builds up, Q1 turns on and activates IC1
to overwrite the VCC voltage, which DZ
initially set to a voltagein this case,
7.02Vlow enough to turn off the PWM
controller (Figure 1b). With this action,
the controller becomes temporary disabled, and the shutdown latch resets.
After C2 completely discharges, Q3 and
Q2 switch off, and the charge stored in C1
continuously supplies the base drive
needed to hold Q1 on through R1. The
PWM controller then stays in sleep mode
for the fixed interval, tSLEEP, until the discharge current of C1 can no longer keep
Q1 on. You can estimate this sleep-time
interval (Figure 2) by using the following
equation:
t SLEEP
IIC1
R1 = VC1(0)VBEQ1 e
h FEQ1
where IIC1 is the forward current of IC1

(10.7 mA with VAUX12.5V), VC1(0) is
the initial voltage stored in C1 (5.05V),
R1C1 (1.1 sec), hFEQ1 is the dc current
gain of Q1 (170 from test results), and
tSLEEP is the sleep time

for the PWM IC (2
sec).
Note that, according
to the 2N2222A data
sheet, dc current gain
can be 75 to 300.
Therefore, to obtain a
better prediction from
the above equation, it is
advisable to determine
the dc gain through
simple testing. To solve
A scope display shows the relevant waveforms during
the equation, you
Figure 2
hiccup operation. Trace 1 is the VCC output voltage of
must first determine VC1(0). This the shunt regulator, Trace 2 is the soft-start voltage of the PWM conquantity depends on troller, Trace C is the collector-emitter voltage of Q3, and Trace B is
several factors. First, it the voltage across timing capacitor C1.
depends on the PWM
IC. The IC can discharge the soft-start caAfter time period tSLEEP elapses, C1
pacitor either linearly (constant-current should have discharged to a low enough
sink) or exponentially (RC discharge). voltage to turn off Q1, thereby allowing
Knowing this fact, you can work out the VCC to climb back to its normal value,
turn-on time, tON, of Q3 and Q2 by plug- thus enabling the PWM controller. The
ging tON and VCC into the standard RC- soft-start capacitor then charges up
charging equation with the time constant again. The output pulse gradually starts
of 1R2C1. In Figure 1a, because to generate after the soft-start voltage
2.31tON51, you can approximate reaches the internal threshold. This
VC1(0) by using VC1(0)VIC1VBEQ4 sleep-reboot-detect cycle repeats until
VCEQ2VD1.
the fault disappears.
Microcontroller provides SRAM battery backup

Dave Bordui, Cypress Semiconductor, Orlando, FL
o maintain content in
ing, the CPU in many inthe event of power loss,
stances powers up and runs
MICROCONTROLLERmany designs that include
if you apply power only to
I/O-PORT INPUTS
VCC
SRAM require a dedicated dean I/O pin. With this fact in
CHIP ENABLE
POWER-SUPPLY INPUT
vice that can automatically
mind, you can create an
LOW-POWER SRAM
switch from a standard power
automatic voltage switch
BATTERY INPUT
supply to battery operation.
by connecting the main
GND
MICROCONTROLLER
Microcontrollers seldom find
power-supply rail and a secuse in power-switchondary battery backup to
Figure 1
ing applications. Betwo separate I/O pins of the
OPTIONAL STATUS SIGNALS
cause microcontrollers typimicrocontroller. The miBATTERY OK
cally operate from the primary
crocontroller can then have
POWER SUPPLY OK
VCC
GND
power supply, they stop exefirmware that drives a third
cution if that supply drops,
I/O to a logic-high (source)
thereby making it impossible
mode or otherwise source
to perform the switching op- A microcontroller can power up and run even if its VCC pin is floating.
current to an output pin.
eration. However, by using a
This output then provides
characteristic of many microcontrollers, ure 1). Many microcontrollers have in- the uninterrupted power to the external
you can perform this switching function ternal protection diodes on their I/O low- power SRAM device.
without interruption to the SRAM (Fig- pins. Therefore, if the VCC pin is left floatWhen the VCC rail is present, the mi-
104 edn | June 26, 2003
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design
ideas
crocontroller draws current from the VCC

pin and operates normally. If the VCC rail
drops below the battery-input voltage,
the microcontroller automatically draws
current from the battery instead. Although this scenario requires no
firmware whatsoever, many microcontrollers can run firmware and continue
execution throughout this power-supply
transition. Continuing the microcontrollers firmware execution allows other
firmware-based functions, such as deassertion of SRAM chip enable, batteryand rail-health indication, and analogto-digital conversion. When you use this
technique, you must take care to ensure
that the entire design draws less current
than the forward-bias-current rating of
the protection diode. Also, the external
SRAM circuit must draw no more current than the microcontrollers output
can source. This stipulation remains true
whether the VCC rail or the battery provides power. It is also important to realize that, because the protection diodes are
sourcing the power, a slight voltage drop
exists on the microcontrollers uninterrupted-power-supply output. This voltage drop is equivalent to the one that the
microcontrollers manufacturer specifies.
You should consider this drop when you
select the battery, VCC rail, and externalSRAM voltage requirements.
Positive regulator makes

dual negative-output converter
ome systems, such as optical netCMDSH-3
works, require more than one negVIN
5V
ative voltage. A common procedure
0.22 F
L1
is to boost the main negative supply of
CDRH6D28-3R0
5V to 10V and then reduce it with a
BOOST
VSW
linear regulator to 9V. The 5V itself
VIN
comes from a positive supply, typically 5
SYNC
or 12V. Independently creating each of
IC1
LT1765EFE-5 FB
the two negative voltages requires the use
COUT
B220A
10 F
SHDN
of two switching-regulator ICs. Howev6.3V
er, a simpler approach uses only one stepVC
GND
X5R
down switching regulator and creates
10 F
CERAMIC
CIN
both a negative output with low ripple
16V
X5R CERAMIC
current and a second output with twice
1800 pF
the voltage. The circuit in Figure 1 is a
positive-to-dual-negative dc/dc convert2.4k
100 pF
er that converts 5V to both 5V and
10V, using a positive buck regulator.
This configuration is not a usual appliCCOUP
COUT2
cation circuit of a positive buck-regula4.7F
L2
10 F VOUT
tor IC, which you would typically find in
16V
CDRH6D28
6.3V 5V
single-output step-down applications.
X5R
33 H
X5R
However, by rearranging the connections
CERAMIC
to ground and VOUT, the dc/dc conFigure 1
verter becomes a common posiB130A
tive-to-negative converter.
You can use a positive buck regulator to configure a
VOUT2
The circuit features an additional neg- dual, negative-output dc/dc converter.
10V
ative-output stage with twice the voltage
of the first output by using a second in- ures less than 3 mm high and delivers tors and all-ceramic coupling, input, and
ductor, a catch diode, and an output ca- high load current (Figure 2). You can re- output capacitors, thanks to both its 1.25pacitor. The circuit includes a coupling place the two inductors with a single 1- MHz switching frequency and its 3A oncapacitor, CCOUP, for energy transfer to to-1 transformer, but even at the high board power switch.
the second winding and offers regulation 1.25-MHz switching frequencies, it may
Figure 2 shows the output capability
of the secondary output without feed- be difficult to find a less-than-5-mm- for the circuit in Figure 1. The load curback. The use of two inductors, as op- high transformer that can do the job. The rent on one output determines the maxposed to one transformer, can provide a LT1765 buck regulator provides high cur- imum available load current on the othflexible circuit layout. This circuit meas- rent capabilities even with small induc- er. At maximum output current, the peak
106 edn | June 26, 2003
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design
ideas
600
monitors VOUT, but the low-im- voltage, an excellent rating for a singlepedance ceramic coupling ca- feedback, dual-output converter. Figure
500
pacitor with an extremely high 3 shows typical efficiency curves for varrms current rating keeps VOUT2 ious values of the load current on VOUT2.
400
MAXIMUM VOUT2
well-regulated. As load
LOAD CURRENT 300
conditions change on
80
(mA)
both VOUT and VOUT2,
200
VOUT2s regulation be76
comes
slightly compro100
mised over different load
72
conditions. VOUT2 can be0
0
200 400
600 800 1000 1200
EFFICIENCY
come unregulated if the
(%)
Figure 2
VOUT LOAD CURRENT (mA)
68
load current on VOUT2 beVOUT2 LOAD CURRENT=400 mA
comes extremely small. A
The circuit delivers high maximum currents available from
VOUT2 LOAD CURRENT=300 mA
64
VOUT2 LOAD CURRENT=200 mA
preload of 5 mA on VOUT2
the two outputs in the circuit of Figure 1.
VOUT2 LOAD CURREN =100 mA
is necessary to maintain
60
switch current (the sum of the peak in- regulation if the load current falls
0
200
400
600
800
1000
ductor currents) is equal to 3A. Forcing below 5 mA. Zero load current on
VOUT LOAD CURRENT (mA)
the output current higher than the max- VOUT does not cause the conFigure 3
imum value can cause the output voltage verter to lose regulation.
on both lines to collapse and lose regula- Cross-regulation typically stays The circuit in Figure 1 has high conversion efficiency
tion. The single feedback signal directly within 1% of the typical output for various values of load current.
Analog switch frees stuck I2C bus

Bob Marshall, Philips Semiconductor, Morgan Hill, CA
he dual-channel PCA9540 I2C
3.3V
multiplexer often breaks up an I2C or
2.7 TO 5.5V
RESET
Y
SM bus or allows you to use devices
2.7 TO 5.5V
with the same addresses on the same bus.
E 74LVC1G66
When the PCA9540 initially powers up,
Z
VDD
it comes up in a state in which both chanVDD
nels are deselected. The I2C- or SM-bus
SD0
SDA
SDA
CHANNEL 0
master can then address the control regIC2
SC0
SCL
SCL
MASTER
ister in the PCA9540 to select either
2.7 TO 5.5V
Channel 0 or Channel 1, connecting the
PCA9540
master to the appropriate channel. The
2
I C bus can then address downstream devices on the selected channel. If a failure
SD1
CHANNEL 1
occurs in one of the downstream
SC1
VSS
F
i
g
u
r
e
1
2
channels, such that the I C bus is
stuck at high or low, the I2C-bus master
could become disabled. Because the
PCA9540 has a power-on-reset function To free up a stuck I2C bus, this circuit controls the supply voltage to force a hardware reset.
that initializes the multiplexer with all
channels disconnected, this feature can
When the enable pin of the 74LVC1G66 uses the PCA9540, but you can use the
free the bus. In some applications, how- goes low, the supply voltage disconnects 74LVC1G66, with a typical on-resistance
ever, powering down the entire system from the multiplexer, thereby freeing up of approximately 6, to selectively control
may be impractical. One way to avoid the I2C bus. The I2C master or any other the power for any device that has a powerpowering down the entire system is to in- system controller can generate this hard- on-reset function. Its size and wide operstall a low-on-resistance analog switch in ware reset. The 74LVC1G66 is available in ating-voltage range also make it practical
series with the power-supply line of the a 2-mm2 package, so the circuit takes up lit- to selectively power down sections of any
tle additional board space. This example circuit in power-sensitive applications.
multiplexer (Figure 1).
108 edn | June 26, 2003
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design
ideas
DDS device produces sawtooth waveform

Niamh Collins, Analog Devices, Limerick, Ireland
amp or sawtooth waveforms are
useful for a broad range of applications, including automatic-test
equipment, benchtest equipment, and
actuator control. Discrete components
typically set the waveform frequency. Unfortunately, drift in these component
values over time and temperature limits
the accuracy of the output frequency.
AD9834
Figure 1
90
IOUT
PSELECT
AD9833
INTERFACE
SIGNALS
CONSTANT
PHASE
MSB
IOUT
Two DDS chips provide a convenient way to

generate sawtooth waveforms.
Also, changing the frequency requires

that you use a different set of components. This Design Idea describes a flexible implementation of a sawtooth waveform generator (Figure 1) using two
DDS (direct-digital-synthesis) devices.
The frequency of the sawtooth is digitally programmable, so the design requires
no external components to set the frequency. A DDS device, a programmable
waveform generator, can deliver sine,
square, and triangular (up/down ramp)
waveforms. You can digitally implement
changes in phase or frequency by loading
onboard registers. Using the phase registers, the DDS chip can generate two linear up/down ramps of the same frequency but with a 90 offset. The up ramp of
one occurs at the same time as the down
ramp of the other. Selecting a phase register causes the signal from that register
to go to the output. A sawtooth waveform
occurs when the only the up ramp of
VDD
DDS device produces

sawtooth waveform ......................................77
Circuit makes universal
VCSEL driver ....................................................78
Circuit level-shifts ac signals........................80
Interface a serial 12-bit ADC to a PC ........82
Safety device uses GMR sensor..................84
each signal is directed to the output. The

AD9833 delivers the MSB of the phase
register, thus producing a digital signal at
the frequency of the up/down ramp. This
signal connects to the PSELECT pin on
the AD9834, which controls switching
between the phase registers.
Latency in the devices means that you
see the effect of switching between the
phase registers on the output only after
VDD
VDD
0.1 F
10 F
0.1 F
DIGITAL
CONTROLLER
MCLK2_CNTRL
MCLK_CNTRL
CLK_N
SCLK
SDATA
FSYNC
4
6
5
CAP DVDD AVDD
0.1 F
MCLK2_CNTRL
MCLK_CNTRL
SCLK
SDATA
FSYNC
6
FSYNCB 8
VDD
CAP
VDD
VDD
SCLK
SDATA
COMP
SCLK
14
SDATA
13
FSYNC
15
0.1 F
11
VOUT
DVDD
5
CRYSTAL
OSCILLATOR
MCLK_CNTRL
10 nF
FSYNC
RESET
SLEEP
FS ADJUST
12
1 6.8k
IOUTB
AD9834
AD9833
0.1 F
SDATA
FSYNC
0.1 F
COMP 3
2
REFOUT
SCLK
10
10
9
MCLK
DGND AGND
4
9
IOUTB
20
IOUT
PSELECT
FSELECT
IOUT
19
VIN 17
200
200
DGND
SIGN BIT OUT
8
Figure 2
MCLK2_CNTRL
16
MCLK
DGND AGND
7
18
This circuit delivers positive- and negative-going sawtooth waveforms.

www.edn.com
July 10, 2003 | edn 77
design
ideas
seven MCLK (master clock)

the selection of the triangular
cycles. Controlling the MCLK
waveform as the output wave600
OUTPUT
signals of both devices so that
form, and you should set PINVOLTAGE
AT IOUT
one MCLK is inactive for a
SW to 1, so that the pin con(V)
number of clock cycles can
trols
phase-register-select
30
overcome this inherfunction. And, for the
TIME
Figure 3
ent latency. Figure 2 ilAD9833, you should set the
lustrates how the two devices
OPBITEN bit to 1 to enable
600
OUTPUT
connect. The connections to
the digital output. You should
VOLTAGE
the interfaces of the two deset the DIV2 bit to 1 so that
AT IOUTB
(V)
vices combine so that they can
the digital output is not di30
accept programs from the
vided by 2, and set the
TIME
same digital controller. The
SLEEP12 bit to 1 because the
AD9833 is connected such that The up ramp of the upper waveforms occurs at the same time as the
DAC is not being used. For the
FSYNC is active high; the down ramp of the bottom waveform.
system to implement the sawAD9834 is connected such that
tooth, there must be an offset
FSYNC is active low. In this way, the conbetween the times when the MCLKs of
FWORD
fSAWTOOTH =
fMCLK ,
troller has to control only three signals inboth devices begin to run. You calculate
227
stead of six. The AD9834 is configured so
the offset as follows:
that the frequency and phase are con- where FWORD is the frequency word loaded
trolled via the pins. This configuration al- in both devices.

228
4 7 .
The AD9834 phase switches between OFFSET = ROUND
lows the digital output from the AD9833
FWORD
to control phase-register selection by sim- 0 and /2. Following instructions in the

ply connecting it to the PSELECT line. ICs data sheet, you should therefore load
Two analog outputs from the AD9834, Phase Register 0 with 0 and Phase RegIf, for example, Offset10, then the
IOUT and IOUTB, deliver complemen- ister 1 with 0x800 (which corresponds to MCLK of the AD9834 should run for 10
a 90 phase shift). The AD9833s phase cycles before the MCLK of the AD9833
tary sawtooth waveforms (Figure 3).
A RESET (Pin 11) signal initializes the is always set to /2, so you should there- starts running. From then on, the ICs
devices. This initialization can occur in fore load Phase Register 0 with 0x800. should be synchronous. A negative value
the same way for both devices, using the Once the MCLK of the AD9833 begins of Offset indicates that the MCLK of the
control register. This operation requires to run and after seven MCLKs of laten- AD9833 should start running first.
a control word with the RESET bit set to cy, the output of the AD9833 changes beThis Design Idea provides a flexible
1. The frequency and phase registers of cause of the /2 phase shift in Phase Reg- method for generating a sawtooth waveboth devices are then ready to load with ister 0. You can deactivate RESET form. The frequency is digitally programdata. Because of the switching involved in through the control register once the reg- mable, and the design requires no external
creating the sawtooth waveform, its fre- isters are loaded with data. In the same components to change the frequency. The
quency is twice that of an equivalent tri- control word to the AD9834, you should frequency does not change with composet the MODE bit to 1, which results in nent drift over time or temperature.
angular waveform:
Circuit makes universal VCSEL driver

Andrzej Wolczko, Institute of Electronics AGH, Krakow, Poland
CSELs (vertical-cavity surfaceemitting lasers) are commercially
available infrared semiconductor
lasers with 850 nm. Short-cavitylength, high-quality Bragg mirrors impart properties to VCSELs that differ
from those that earlier Fabrey-Perot
lasers impart. The emission characteristicsoptical power, P, versus diode currentshows threshold and operating
currents of approximately 3 and 13 mA,
respectively, for the Lasermate TSCM85A416 VCSEL. Such values are typi-
78 edn | July 10, 2003
cal for this type of laser (Figure 1). The

current characteristics are nearly independent of temperature. Thanks to their
P
low operating current, effective coupling
(60 W/DIV)
to multimode fibers, high-speed switching, and low priceabout one-third
that of a Fabrey-Perot laserVCSELs
may replace LED light sources in short
IVCSEL
I TH
fiber-optic links. The MC10EP89
(2 mA/DIV)
ECL coaxial VCSEL driver allows
Figure 1
the circuit to switch current with
less-than-1-nsec rise and fall times (Fig- A VCSEL has threshold and operating currents
ure 2). The IC delivers a voltage swing of of approximately 3 and 13 mA, respectively.
www.edn.com
design
ideas
with resistor RL for OR/NOR gate works as an asymmetriproper operation of the cal/symmetrical ECL converter. The
VDRIVE
MC10EP01
ECL
IC. You can optimize the lasers good thermal properties elimiINPUT
MC10EP89
RM
values of RM and RP for nate the need to provide a complicated
120
RL
each type and character- stabilization loop for the optical power.
50
150
RP
istic (individual emis- The entire circuit is dc-coupled and op300
300
VCSEL
sion parameters) of the erates with constant optical power am5V
VCSEL you select. Be- plitude for each binary code, and the circause of the dynamic re- cuit is insensitive to bit patterns. A
Figure 2
sistance of the laser, the slow-start circuit is unnecessary. BeThis universal VCSEL driver allows you optimize the circuit for
voltage drop across the cause of the operating speed, you must
any type of laser diode.
junction varies from ap- carefully design the pc board according
proximately 1.9 to 2.2V to high-frequency rules: Keep connec1.6V minimum to a 75 load (Figure 3). within the full current range. Therefore, tions as short as possible, use surfaceThe 120 resistor, RM, limits the am- you should consider this variation when mount components, and carefully perplitude of the pulse current, and RP de- you calculate RM and RP. In turning off form decoupling, for example. You must
termines the initial polarization current the optical power of the VCSEL, you ob- ground the metal case of the laser and
of the laser. For RP, the laser practi- serve some residual emission (tail) in the isolate it from the chip.
cally switches off during the low state of optical-pulse response
100
the driver. You must load the MC10EP89 (Figure 4). If the current
falls to zero (RP), the
RP
80
tail is shorter and small0
1300
er, but the optical-pow
60
1
er amplitude also deP
(ARBITRARY
creases.
VDRIVE (V)
UNITS)
2
The oscillogram rep40
resents the response of a
3
155-Mbps laser (Figure
20
4). VCSELs for 622 and
4
1250 Mbps are
1 nSEC/DIV
0
Figure 4
also available
Figure 3
1 nSEC/DIV
from Lasermate. The

The driver in Figure 1 switches 1.6V into 75
MC10EP89 needs symThese curves show the VCSELs response with RP open and
with less-than-1-nsec rise and fall times.
.
metrical drive; the input
RP1300
Circuit level-shifts ac signals

Ron Mancini, Texas Instruments, Bushnell, FL
C signals can emanate from many
sources, and many of these sources
are incompatible with the most popular interface voltages, such as TTL. A
temptation always exists to capacitively
couple the ac signals because capacitive
coupling strips off the dc level. Capacitive
coupling sometimes doesnt work, because the coupled signals voltage swings
around ground, so you have to add dc
offset to make the coupled signal compatible with the interface voltage. Also,
the coupled signal contains a dc content,
VDC, which varies with pulse width, and
the dc variation interferes with the inter-
80 edn | July 10, 2003
face voltage when the signal swing is

large. This circuit completes the signal
interface by measuring the dc offset,
adding appropriate compensation to the
capacitively coupled signal and adding
an adjustable-dc- level feature (Figure
1). R1 and C2 form a lowpass filter
(f3dB0.312 Hz) that measures the dc
content of the input signal. The transfer
equation is the following:
V R + VREF (R1 + R 2 )
VA = IN 3

(R 2 + R 3 )(R1C2s + 1) + R1
RF + RG
.
RG
C1
2 F
VIN
VOUT
R1
5.1k
7.5V
+
C2
100 F
R2
5.1k
TLCO7X
7.5V
VREF
R3
10k
R4
10k
VA
RF
10k
RG
10k
Figure 1
This circuit is a universal level shifter for ac signals; it accommodates any interface standard.
www.edn.com
design
ideas
When R1R2R3 and RFRG, VDC

transfers to the output signal, VA, because
it is multiplied by 1/2(2)1 or a gain of
one. The output voltage for the same resistor values contains VREF; thus, the output signal is level-shifted by the voltage,
VREF, not VREF plus the VDC. When the input signals duty cycle changes, rather
than the output voltages changing with
duty cycle, the op amp keeps the outputvoltage level constant. The gain for the
VDC must be one, so that it cancels the

voltage shift after ac-coupling. The gain
for the reference voltage can be greater
than one; for example if R1R23R3 and
RF3RG, the dc content is 1/4(4)1, and
the reference-voltage gain is 3/4(4)3.
VREF can be positive or negative, so you
can obtain TTL, CMOS, or ECL logic levels with this circuit. The time constant
formed by C1 and R4 must be large
enough to pass the lowest frequency sig-
nal without distortion. The value of R4 is

not critical, as long as the op amp can
drive R4 without losing too much signal
swing. In some cases, you can size R4 to
present the driving-point impedance you
need to eliminate near-end reflections.
The circuit easily couples 400-MHz data
as configured, but the data rate depends
on the time constant formed by R4 and
the input impedance of the driven circuit.
Interface a serial 12-bit ADC to a PC

DS Oberoi and Harinder Dhingra, GCET, Jammu, India
ver the years, IC man5V
ufacturers have devised
various ways of effecting
interfaces and paying special
C3
C2
attention to reducing the num10 F
0.1 F
ber of ICs interface-I/O pins.
The MAX187 is one such de1
vice, a 12-bit A/D converter.
VDD
You can create an interface to
3
SCLK 8
SHDN
this ADC using serial datacommunications techniques.
IC1
Analog-to-digital conversion
7
MAX187
and data transfer from MAXCS
187 require only three digitalI/O lines. You can create a sim2
6
VIN
ple interface between the
DOUT
AIN
MAX187 and a PC using the
computers Centronics printREF
GND
er port (Figure 1). You enable
4
5
or disable the MAX187 by setting the SHDN pin (Pin 3) to
C1
high or low level, respectively.
4.7 F
If you leave this pin open, then
the internal reference
Figure 1
(4.096V) becomes disabled, and you must apply an
external voltage reference to Its easy to effect an interface of a 12-bit serial ADC to a PC.
REF (Pin 4). Otherwise, this
pin connects to a 4.7-F bypass capaci- cycles. The analog-to-digital conversion
tor, C1. The digital data from the starts when the ADCs CS pin (Pin 7) goes
MAX187 transfers to the processing unit low. This pin must remain in the low state
one bit at a time by using an external until the complete cycle of conversion and
clock at SCLK (Pin 8).
subsequent serial-data transfer has taken
A complete data transfer requires 13 place. A change of state in the DOUT pin
external clock pulses. The first clock from low to high level indicates the EOC
pulses falling edge latches the first data bit (end-of-conversion) status. Then, serial
(the MSB) at the DOUT pin (Pin 6). The 12-bit data is available for transfer. Softoutput data bit changes at the falling edge ware controls the MAX187s operation.
of the next external clock, and you can The software should be able to generate
read the serial data bits until the appear- all the control signals for successful conance of the falling edge of the next clock version and also should be able to detect
82 edn | July 10, 2003
the EOC status. It should also

be able to generate 13 external
clock pulses to read serial 12-bit
P1
data and convert it into paral13
lel data.
25
12
The software for the MAX24
187s
operation is in Turbo
11
C, Version 3.0 (which you
23
10
can download from the Web
22
version of this Design Idea at
9
www.edn.com). In the code,
21
8
Port defines the Centronics
20
port of the PC to which the
7
MAX187 interfaces. Write Port
19
6
defines the port for initiating
18
the analog-to-digital conver5
sion and generating the external
17
4
clock pulses. Read Port defines
16
the port for reading the EOC
3
and serial data from the ADC.
15
2
After pulling CS and SCLK low,
14
the EOC loop checks for the
1
EOC status. If a valid EOC does
not appear, this loop remains
operational. As soon as a valid
EOC appears, the first of the 13
clock cycles appears, which
latches the first data bit (MSB).
After this action, the routine calls a subroutine (get_adc()). The subroutine generates the rest of the external clock cycles
to read the 12 bits of serial data. The function also converts the received serial data
into parallel data (adc_val). It converts by
multiplying the previous data by two by
shifting adc val to the left by one bit and
adding one to the parallel data if the serial bits value is one. Once the parallel data
is available, the function returns the value and displays it on the screen.
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design
ideas
Safety device uses GMR sensor

J Pelegri-Sebastia and D Ramirez-Munoz, University of Valencia, Spain
his Design Idea presents a differential safety device to prevent risks arising from current leakages in household applications. The proposed circuit
uses a new method for differential current sensing (Figure 1). The method entails the use of Helmholtz coils and a
magnetic sensor based on the GMR (giant-magnetoresistive) effect. The AC00401 magnetic sensor from NVE (www.
nve.com) uses GMR technology (Reference 1). Two Helmholtz coils carry the
households input current. If no differential current between phase and ground
exists at the center of the coils, then the
magnetic field is uniform and null. But,
in the presence of an unbalanced magnetic field, corresponding to a leakage
current to ground, a differential magnetic field appears at the center of the
Helmholtz coils (Reference 2).

Thus, the sensors output is a
nonzero voltage that the cirFigure 2
cuit in Figure 1 amplifies
and compares with a preset
reference voltage. The reference voltage corresponds to
the highest allowable leakage
currentgenerally, approximately 30 mA.
The sensors output, a differential voltage, connects via
a highpass filter to an INA118
instrumentation amplifier, a The sensors output (Channel 4) is zero because the difdevice with high common- ferential line current is zero.
mode rejection (Reference 3). This stage a half-wave rectifier and a lowpass filter
converts the sensors differential signal and becomes a dc signal. If this signal is
from a Wheatstone-bridge arrangement greater than VREF1, then the MOC3041
to a unipolar output with an appropri- optotriac turns off, thereby interrupting
ate gain figure. This output goes through the power to the household appliance.
220k
VCC
8
5V
GMR
SENSOR
GND V
4
FILTER
100 nF
V+ 5
1
3
7
+
2
8
1
100 nF
1M
VCC
VCC
50
10k
IC1
INA118
6
3 +
3.3k
8
J1
100 nF
VREF1
VREF2
100-kHz
FILTER
VCC
500k
SEN
IC1B
8
5
OPA2234
+
7
6
IN4148
4
REFERENCE VCC
VOLTAGE
VREF1
IC1A
OPA2234
1
1M
J2
SEN+
HALF-WAVE
RECTIFIER
AND FILTER
100
10 F
3k
J2
2
VREF2
VOUT
LM4040
2.5V
J3
1
2
VCC
VOUT2
COMPARATOR
1
3.3k
VCC
VREF1
1.3k
5 6 8
2 +
1k
VOUT
4 1
Figure 1
VCC
820
10k
2.5k
7
IC4
LM311
3
2
S1
1 ID
2 OD
T1 6
T2 4
MOC3041
J5
RELEASE
Q1
2N2905
1
10M
8.7k
RELEASE
SWITCH
J4
This circuit uses a GMR sensor to detect and disable dangerous differential line currents.
84 edn | July 10, 2003
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design
ideas
Figures 2 and 3 depict two scenarios. The

Channel 1 trace represents the line current; Channel 2 shows the current circulating through the line; and Channel 4
represents the sensors output, which is
proportional to the difference between
line and ground currents. In Figure 2, the
sensors output is zero because the cur-
Figure 3
rent difference is null. Figure

3 shows a ground current that
generates a nonzero magnetic field in the sensor. In Figure
4, the ground current is
greater than 30 mA. The comparator changes state, activating the optotriac (Channel 1)
and turning on the
relay (Channel 2, 20
mA/division).
Channel 3 shows
the live current, and
Channel 4 shows the
sensors output (1
mV/division).
A ground current generates a nonzero magnetic field in

the sensor (Channel 4).
86 edn | July 10, 2003
Figure 4
The ground current exceeds 30 mA. An optotriac and a

relay disconnect power to the household appliance.
References
1. Daugton, JM,Giant magnetoresistive in narrow stripes,
IEEE Transactions on Magnetics, 1992.
2. Smith, CH, and RW Schneider,Low magnetic field sensing
with GMR sensors, Sensors magazine,

September 1999.
3. Casas, O, and R Pallas, Basics of
analog differential filters, IEEE Transactions on Instrumentation and Measurement, 1996.
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design
ideas
Clip extracts signal from phone line

Maxwell Strange, Fulton, MD
sing a capacitive-couput sees and reduces the cirTOTAL
CCOUPLING
CSTRAY
pled clip, you can pick
cuits noise by the square root
AMPLIFIER RIN
up the signal from a
of the signal attenuation. The
C1
+
twisted-pair or -wire telenoise reduction accrues from
TO POSTAMPLIFIER
C4
R
VS
OP
phone line or from other unreducing the needed input reC3
(CABLE
AMP
SIGNAL)
C5
R
shielded analog lines withsistance. Therefore, you gen
out piercing the insulation.
erally dont need the compliC2
No line test can detect the
cation of an insulated bootclips presence, and it leaves
strapped shield. You can folVCM
no evidence of havlow the amplifier with a nearFigure 1
60 Hz+HARMONICS
ing been attached. It
by or remotely located postneeds no ground return. You In this equivalent circuit, you should maximize the coupling capacitances, C1 amplifier for more gain and
can fasten the small, insulat- and C2, and minimize the stray capacitances, C3, C4, and C5.
bandpass filtering to optied pickup plates to the opmize the signal-to-noise perposing jaws of an alligator clip for quick interference, typically comprising 60-Hz formance. A telephone signal has a bandand easy attachment. Balanced lines from signals and their harmonics from power- width of approximately 300 Hz to 3 or 4
the plates connect to the inputs of a high- line fields. The cable should have good kHz. A sharp highpass cutoff at 300 Hz
impedance differential amplifier (Figure electrical symmetry and low total capac- effectively rejects power-line noise pick1). For this scheme to have satisfactory itance between conductors and to the up. A simple, two-pole, Sallen-Key Butsignal-to-noise and frequency-response shield. Thus, the amplifier must be near terworth filter works well. You can trim it
parameters, the clip, connecting cable, the clip. The amplifier should have high to provide some high-frequency peaking
and amplifier must m be attached paral- input resistance, low current noise, and to obtain the most intelligible signal.
lel to the signal wire and must be as long adequate common-mode rejection.
A multiple-pad pickup scheme improves noise rejection (Figure 2). The cirB
+
cuits arrangement is such that evenA
C
numbered pads on one side and
RGAIN
odd-numbered pads on the other side
R
pick up equal noise that produces oppo
OUTPUT
site-phase outputs from op amps A and
PHONE LINE
C
+
CLIP
B. Op amp C then sums the signals and
R
PADS
A
rejects the noise. The desired difference
+
B
signal, however, appears in-phase at the
D
outputs of A and B, so both op amps con-
Figure 2
A multiple-pad approach produces cancellation of equal noise that the opposed pad pairs pick up.
as is conveniently possiblean inch or

moreand preferably slightly curved to
maximize the coupling capacitance. (For
a twisted-conductor line, the plates
should not be longer than the twist
wavelength to avoid signal cancellation.) You should orient the clip for the
cleanest signal output.
The clip, its connecting cable, and the
amplifier must be shielded to minimize
www.edn.com
The clips coupling capacitance and

stray capacitance and the amplifiers input resistance determine the low-frequency cutoff of the detected signal. Stray
capacitances in the clip and in its connecting cable to the shield are generally
much larger than the coupling capacitance. Thus, voltage-divider action reduces the signal, but the stray component
adds to the capacitance the amplifiers in-
Clip extracts signal from phone line ..........81

Circuit produces variable frequency,
duty cycle ........................................................82
Active-feedback IC serves as currentsensing instrumentation amplifier ............86
Create secondary colors
from multicolored LEDs................................88
July 24, 2003 | edn 81
design
ideas
SHIELD AND
POWER GROUND
OP-AMP
POWER
10M
SHIELD
3.3M
3.3M
IC1A
+
1 F
R
1 F
150k
IC2A
OP-AMP
+POWER
9V
R
0.0015 F
+
3.3M
B
IC1B
_
_
10M
INPUT FROM
MULTISEGMENT
PICKUP
C
IC2D
+
IC2C
10M
3.3M
10k
_
+
1 F
0.01 0.01
F
F
150k
220k
IC1C
3.3k
150 pF
R
150k
X
OUTPUT
Figure 3
+
3.3M
D
IC1D
_
IC2B
_
150k
NOTES:
IC1 AND IC2 ARE QUAD JFET OP AMPS.
CAPACITORS ARE 20% CERAMIC.
3.3M
10M
This amplifier, using the multiple-pad approach effectively reduces power-line-related noise pickup.
tribute equally to the output. You can

make a segmented pickup from pieces of
two-sided pc board with the solid-copper
side serving as a shield.You can solder the
shield side of the pieces to a suitable alligator clip. Alternatively, for longer term
use, you can simply tape them onto the
cable. You can use any even number of
pads. the more you use, the better, but
eight on each side are sufficient.
The amplifier of Figure 3 uses two
quad J-FET or BiFET op amps. Thanks to
stray capacitance on the input lines of the

test model, a relatively low input resistance of 3.3 M is sufficient. Input noise
is mostly the Johnson noise of the 10-M
feedback resistors. Power-line noise pickup is usually the bigger problem. The
output stages incorporate some highpass
filtering to reject noise below 300 Hz. The
output level depends on many factors but
is approximately 50 mV. A postamplifier
(not shown) can provide more equalization, filtering, and gain if necessary, as
well as manual or automatic level control.

Tests of models of both design approaches use readily available components and show perfectly clear telephone
speech through a small speaker in the
postamplifier box. The multiple-pad
pickup system produces noticeably lower noise, and clip orientation is less critical.
Circuit produces variable frequency, duty cycle

Mark Reed, Texas Instruments, Dallas, TX
his Design Idea shows a simple,
low-cost circuit that produces a highly accurate variable-frequency and
variable-duty-cycle output (Figure 1).
Further, the duty cycle and frequency are
independent of each other (excluding 0
and 100% duty cycle). The method derives its accuracy and stability from the
fact that the output is based on a crystal
oscillator and divisions of the oscillators
frequency. The design uses only six de-
82 edn | July 24, 2003
vices. IC1, a 74HC393 binary ripple

counter, has as its input is the oscillators
output frequency. The outputs are the oscillator frequency divided by two, four,
eight, 16, 32, 64, 128, and 256. IC5B is cascaded with IC1 to divide the oscillator frequency further by 512, 1024, 2048, and
4096. In this circuit, the divide-by-128 is
the largest division it uses. You could,
with a simple wiring change, substitute
an unused divider to obtain a different
output-frequency range. The eight inputs

of IC2, a 74HC151 eight-line-to-one-line
multiplexer, connect to the oscillators
frequency divided by one, two, four,
eight, 16, 32, 64, and 128. Note that the
oscillators output connects directly to an
input of IC2. This connection allows selecting the oscillators frequency divided
by one. IC2 connects one of the eight frequencies to the input of IC3.
IC3, a 74HC4017 decade counter, diwww.edn.com
design
ideas
5V
SET
FREQUENCY
SET_FREQ_C
SET_FREQ_B
SET_FREQ_A
Y1
1
EN
VCC 8
GND OUT
4
DGND
IC1A
74HC393N
QA
1
CLK
QB
QC
2
CLR QD
3
4
5
6
DGND
IC1B
74HC393N
QA
13
CLK
QB
QC
12
CLR QD
Figure 1
11
10
9
8
/1
/2
/4
/8
/16
/32
/64
/128
11
10
9
8
11
10
9
4
3
2
1
15
14
13
12
7
A
B
C
D0
D1
D2
D3
D4
D5
D6
D7
G
IC3
74HC4017N
Y 5
14
13
W 6
15
CLK
CI
RST
DGND
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q9
CO
GENERATOR
OUTPUT
3
4
5
6
DGND
DGND
/256
DGND
IC5A
74HC393N
QA
13
CLK
QB
QC
12
CLR QD
IC2
74HC151N
SET_DUTY_C
SET
SET_DUTY_B DUTY CYCLE
SET_DUTY_A
IC4
IC5B
74HC151N
74HC393N
11
A
QA
START OF 1
10
B
PULSE
CLK
QB
9
3
C
QC
4
2 10%
END OF
D0
3
4 20%
QD
PULSE 2
D1
Y 5
CLR
2
7 30%
D2
1
10 40%
D3
15
1 50%
W 6
D4
14
5 60%
D5
13
6 70%
D6
12 D7
9 80%
11
7
G
12
/512
/1024
/2048
/4096
OSCILLATOR
FREQUENCY
DIVIDE BY
DUTY CYCLE (%)
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
10
20
40
80
160
320
640
1280
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
10
20
30
40
50
60
70
80
DGND
This circuit produces waveforms of variable frequency and duty cycle. Further, the frequency and duty cycle are independent of each other.
IC5A is a binary ripple counter that

vides the frequency from IC2s output by wiring change. If you want to select 0%
10. Therefore, the maximum output fre- duty cycle, connect an input to IC4. If you serves as a set-reset latch. The start-ofquency for this design is the oscillator fre- select 0% duty cycle, the generators out- pulse signal sets the latch. The end-ofquency divided by 10. Each of the decod- put is low. IC4 connects one of eight end- pulse signal resets the latch. The output
ed decade counters 10 outputs goes high of-pulse signals to IC5.
of IC5 is the variable-frequency and variable-duty-cycle output of the
for one clock cycle only (Figure
signal generator. For example,
2). Using the 10 outputs, a freEND-OF-PULSE
END-OF-PULSE 50% DUTY CYCLE
if the oscillators frequency is 4
quencys period divides
40% DUTY CYCLE
Figure 2
END-OF-PULSE
MHz and IC2s C B A inputs
into 10 equal intervals.You
END-OF-PULSE
60% DUTY CYCLE
30% DUTY CYCLE
END-OF-PULSE
are 0 1 0, then the generator
can use these 10 equal intervals
END-OF-PULSE
70% DUTY CYCLE
20% DUTY CYCLE
delivers 100 kHz. If IC4s C B A
to generate duty cycles of 10, 20,
END-OF-PULSE
END-OF-PULSE
80% DUTY CYCLE
inputs are 0 0 1, then the gen30, 40, 50, 60, 70, 80, and 90%.
10% DUTY CYCLE
END-OF-PULSE
erators output exhibits 20%
For this circuit, the outputs of
START-OF-PULSE
90% DUTY CYCLE
duty cycle. If you need to select
IC3, Q1 through Q8, yield the
IC3
end-of-pulse signals for duty cyfrom more than eight freCLK
cles of 10 through 80%, respecquencies, use a larger multiQ0
tively. The start-of-pulse signal is
plexer than IC2. Cascade more
Q1
or different types of dividers to
Q9s negative edge, which occurs
Q2
achieve your frequency needs.
at the same time as Q0s positive
Q3
You can use a 74HC390 to obedge. Therefore, you can use Q9
Q4
tain division by five, 10, 50,
as start-of-pulse low true, and
Q5
100, and so on. If you need
the end-of-pulse signals are high
Q6
other duty cycles, cascade
true. The eight inputs of IC4, an
Q7
eight-line-to-one-line multi74HC4017s to divide the peQ8
plexer, connect to eight of the
riod by the desired number of
nine end-of-pulse outputs from
intervals. Finally, if you need
Q9
IC3. This circuit omits the 90%
to select from more than eight
duty cycle. You can include the The end-of-pulse signals from IC4 determine the duty cycle of the
duty cycles, use a larger mul90% duty cycle with a simple output waveform.
tiplexer than IC4.
84 edn | July 24, 2003
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design
ideas
Active-feedback IC serves as
current-sensing instrumentation amplifier
Jonathan Pearson, Analog Devices, Wilmington, MA
igh-speed current
must extend to high fresensing presents a dequencies. Figure 1 shows
AD8129/30
signer with some sighow high-speed active
A
+
+
nificant challenges. Most
feedback amplifiers, such
ISENSE
gm
RSENSE VSENSE
techniques for sensing curas the AD8129 and ADIOUT

rent involve measuring the
8130 differential receivers,
1
+
B
differential voltage the curare ideal for these highVOUT
+
gm
rent produces as it flows
speed instrumentation
through a sense element,
amp applications. The
such as a resistor or a
AD8129 requires a miniFigure 1
Hall-effect device. The
mum closed-loop voltage
RF
differential voltage across
gain of 10 for stability,
the sense element is generwhereas the AD8130 is
RG
ally small and is often riding
unity-gain-stable.
on a common-mode voltage
Active-feedback amplithat is considerably larger
fier operation differs
than the differential voltage An active-feedback amplifier is ideal for current-sensing applications.
from that of traditional
itself. Accurate amplificaop amps; it provides a
tion of the differential voltage requires a fiers have these features and often serve beneficial separation between the sigdifferential amplifier with high input im- for low-frequency current sensing, but nal input and the feedback network.
pedance, high CMR (common-mode re- they perform poorly at high speeds. Figure 1 shows a high-level block diajection); wide input-common-mode High-speed current sensing requires the gram of an active-feedback amplifier in
voltage range; and high, well-defined kind of performance that instrumenta- a typical closed-loop configuration.
gain. Traditional instrumentation ampli- tion amps provide, but their abilities High-speed current sensing uses a resistor as the sense element. The input
stages are high-impedance, high-CMR,
NETWORK-ANALYZER Tx
wideband, high-gain transconductance
50
amplifiers with closely matched transAD8129
conductance parameters. The output
+
currents of the transconductance amgm
1
plifiers undergo summing, and the

50
1
voltage at the summing node is
buffered to provide a low-impedance
+
gm
output. Applying negative feedback
50
around amplifier B drives VOUT to a level that forces the input voltage of amFigure 2
plifier B to equal the negative value of
301
the input voltage at amplifier A, because the current from amplifier A
15.8
equals the negative value of the current
from amplifier B, and the gm values are
closely matched. From the foregoing
NETWORK-ANALYZER Rx
100-MHz, THREE-POLE BUTTERWORTH
discussion, you can express the closedLOWPASS FILTER
loop voltage gain for the ideal case as:
150 nH
VOUT/VIN1RF/RGAV.
33
pF
33
pF
50
Measurement sensitivity in volts per
amp is expressed as:VOUT/ISENSEAVRSENSE.
Minimizing the values of RF and RG also
minimizes resistor and output-voltage
noise arising from input-referred current
This test circuit produces flat frequency response to 10 MHz.
86 edn | July 24, 2003
www.edn.com
design
ideas
noise. Because of the small sense resistance and high measurement frequencies,
you must minimize parasitic effects in the
input circuitry to avoid measurement errors. Parasitic trace inductance in series
with the sense element is of particular
concern, because it causes the impedance
across the amplifiers input to increase
with increasing frequency, producing a
spurious increase in output voltage at
high frequencies. Figure 2 illustrates a
test circuit with RSENSE1 and AV20,
which equates to a measurement sensitivity of 20V/A. The three-pole lowpass
filter produces a defined bandwidth and
attenuates spurious responses at the amplifiers output arising from input signals
at frequencies outside the desired measurement bandwidth. The test circuits frequency response in Figure 3 shows that
the expected differential-to-single-ended
gain of 20/101, or 14 dB, is flat to
Figure 3
approximately 10 MHz and is down
by 3 dB at 62 MHz. Figure 3 demonstrates the effectiveness of the high CMR
of active-feedback amplifiers. The common-mode signal at the amplifiers input
is approximately 50 times greater than The test circuit in Figure 2 exhibits accurate
the differential signal across the sense re- differential gain in the presence of large common-mode signals.
sistor.
Create secondary colors from multicolored LEDs

Claude Haridge, Stittsville, ON, Canada
LED 4
t is well-known that simultaneousTRILEDCA
LED 3
LED 1
LED 2
BILED
ly mixing two primary-color light
V
BILEDCA
BILEDCA
CC
R5
sources, such as red and green, creates
RC
A
VCC
VCC
R1
R
4 RC
R3
RC
GC
a secondary color, such as yellow. This
A
A
A RC
R6
CA
CA
GC
CA
mixing process commonly occurs in triB
R2
GC
GC
color LEDs. One disadvantage of this
B
B
R7
B
BC
method of generating a yellow color is
C
that the LED must use twice the curNOTES:
Figure 1
CA=COMMON ANODE.
rent because both the red and the
CC=COMMON CATHODE.
green LEDs must be on. In battery-powered circuits, the LED indicators operat- All these LED configurations can produce secondary colors, either by current control or
ing current may be a significant fraction duty-cycle control.
of the supply current, so using the same
f>40 Hz
current to generate both primary and
5V
secondary colors is advantageous. The
A
0V
operating-current savings may be signif5V
icant in telecom-line-card applications
B
0V
involving thousands of line cards or
LEDs OFF
RED LED ON
GREEN LED ON
YELLOW
large-panel RGB LED displays. This Design Idea proposes a sequencing method
to generate balanced secondary colors
5V
A
from bicolor, tricolor, and RGB LEDs, us0V
ing only one LEDs operating cur5V
Figure 2
B
rent. Advantages include lower pow0V
er dissipation and more uniform in- The waveforms at the top generate yellow
tGREEN
tRED
tensities between primary and secondary from green and red; the same result ensues
t<25 mSEC
colors. Using the sequencing method also from duty-cycle control (bottom right).
allows a bicolor LED to now produce
three colors and keep a simpler pc-board mary colors flash sequentially and quick- complete within approximately 25 msec
layout using two rather than three pins. ly enough from one point, humans see or less to produce a solid secondary colIn addition, you can also produce white them as overlapping in time, and the or or white light. In testing for an upper
light with RGB LEDs using the sequenc- brain interprets them to appear as sec- limit, you can use flash rates to 1 MHz to
ing method.
ondary colors or even white, depending produce this effect without degrading
The method uses the property of im- on the color components. Experimenta- secondary colors. Thus, you can use any
ages to persist in the human eye for sev- tion with two or three primary-color convenient clock source higher than 40
eral tens of milliseconds. If different pri- LEDs shows that the flash sequence must Hz to create secondary colors. Note that
88 edn | July 24, 2003
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design
ideas
the primary-color LEDs must be physi- mon-anode or -cathode configuration both bicolor and tricolor LEDs.
cally close together, such as on a semi- and 50% duty cycle, the correction is
Using a sequenced bicolor LED to
conductor chip, for the eye to properly easy to effect by adjusting the current- generate three colors has packaging admix the light. Diffused lenses also allow limiting resistors. Alternatively, you can vantages, particularly when you vertia wider viewing angle. These combina- use one current-limiting resistor and cally stack several LEDs. Previously,
tions are commercially availstacked, tricolor LEDs needTABLE 1SECONDARY COLORS FROM RGB LEDs ed to use a through-hole asable as bicolor, tricolor, and
Red
Green
Blue
Emitted color
Notes
RGB LEDs.
sembly, because the middle
0
0
0
None
Figure 1 shows the various
lead would be inaccessible if
1
0
0
Red
LED-circuit configurations,
the devices were surface0
1
0
Green
and Figure 2 shows the timing
mounted. Because the bi0
0
1
Blue
to generate all three colors
color LED has only two
1
1
0
Yellow
Red/green sequenced
from bicolor and tricolor
pins, you can vertically stack
0
1
1
Cyan
Green/blue sequenced
LEDs, although using only one
several of them and bend
1
0
1
Magenta
Blue/red sequenced
LEDs operating current. Note
out the leads for surface
1
1
1
White
Red/green/blue sequenced
that the driver for the bicolor
mounting. The generation
LED must be able to sink and source cur- then vary the duty cycle to provide the of secondary colors can also extend to
rent. You may have to provide color bal- necessary color balance. For two-leaded, RGB LEDs (Table 1). You can achieve
ance between the primary-color LEDs to bicolor LEDs, it is easier to adjust the color balancing by adjusting the curensure that the secondary colors appear duty cycle to produce the correct sec- rent-limiting resistors or the duty cycle.
properly. The LEDs have different effi- ondary color than to use additional cir- You can program three pins from a miciencies and intensities as the human eye cuitry. The waveforms at the bottom of crocontrollers port to sequence through
sees them, and these parameters need Figure 2 illustrate duty-cycle control to the various primary-color combinacorrecting. For tricolor LEDs in a com- achieve secondary-color balance for tions.
90 edn | July 24, 2003
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design
ideas
Make noise with a PIC

Peter Guettler, APS Software Engineering GmbH, Cologne, Germany
uilding a stable noise generator
for audio-frequency purposes requires only a few components. The
circuit in Figure 1 relies on linear-feedback shift registers and some simple software. An eight-pin Microchip (www.
microchip.com) PIC12C508 controller
(IC2) with a short program generates
pseudorandom noise at its output pin,
GP0. A single controller is sufficient for
simple applications. To obtain Gaussiandistributed noise, you can use a number
of identical PIC controllers in parallel in
a true realization of the central-limit theorem. (The central-limit theorem states
that the sum of an infinite number of
noise sources has Gaussian distribution,
regardless of the individual noise distribution of each generator.) Using an infinite number of noise generators is impractical, but 10 to 16 are sufficient in
most cases. And, because the smallest

member of the PIC family is an inexpensive chip with low current consumption,
the circuit is easy to realize.
All noise generators run the same program (Listing 1 on the Web version of
this Design Idea at www.edn.com). Perfectionists might program each PIC with
an individual initial value for the shift
register, but, because all controllers run
uncorrelated with their own internal oscillators and start out of reset at different times, this measure is unnecessary.
Op amp IC1A sums and level-shifts the
noise signals. Summing resistors R1 and
R2 must have a value of 10 k times the
number of noise generators you use. The
output signal of IC1A feeds a 3-dB/octave filter to obtain pink noise. Buffer IC1B
decouples the filter and provides low output impedance. The signal amplitude is
5V
approximately 400 mV p-p with a flat

spectral distribution of 20 Hz to 20 kHz.
Closing S1 or applying a low level at pin
GP4 immediately stops all noise generators and freezes the prevailing signal amplitude. You can download the PIC software from the Web version of this Design
Idea at www.edn.com.
Make noise with a PIC ..................................77
Circuit provides linear
resistance-to-time conversion ....................78
PC-configurable RLC resonator yields
single-output filter..........................................82
Single IC provides gains
of 10 and 10 ..............................................86
5V
10k
1
VDD
GP5/CIN
GP4/COUT
GP3/MC
IC2
GP2
PIC12C508P
GP1
8
VSS
GP0
2
3
4
5
6
7
R1
nR
R
5V
5V
ADDITIONAL
PICs
10k
1
GP5/CIN
GP4/COUT
GP3/MC
IC3
GP2
PIC12C508P
GP1
8
GP0
VSS
VDD
6 _
2 _
2
3
4
5
6
7
IC1A
TL072P
3 +
0.1 F
DISABLE
220
VOUT
PINK NOISE
400 mV P-P
300
1k
5V
3.3k
nR
S1
4
3k
R2
IC1B
TL072P
5 +
6.8k
1 F 0.27 F
47 nF
47 nF
33 nF
1
NOISE
GENERATORS
Figure 1
www.edn.com
SUMMING AMPLIFIER
3-dB/OCTAVE FILTER
OUTPUT BUFFER
This simple circuit generates Gaussian-distributed noise for audio applications.

August 7, 2003 | edn 77
design
ideas
Circuit provides linear

resistance-to-time conversion
S Kaliyugavaradan and D Arul Raj, Anna University, Chennai, India
esistance-based transducers, such
as strain gauges and piezoresistive
devices, find common use in the
measurement of several physical parameters. For applications in which digital
processors or microcontrollers serve for
data acquisition and signal processing,
the transducers response must assume a
form suitable for conversion to digital
format. It is desirable to convert the resistance change of such sensors into a
proportional frequency or a time interval
so that you can easily obtain an output
in digital form, using a counter/timer.
The circuit of Figure1 linearly converts
the sensor resistance, RS, into a proportional time period. The circuit is essentially a relaxation oscillator, comprising a
current source, a bridge amplifier, a comparator, and a flip-flop. The current, IS,
divides in the paths of R1 and R2 as if the
two resistors were connected in parallel.
Assuming ideal op amps, the circuit functions as an oscillator when RX (R4RS) is
greater than R1R3/R2.
The circuit produces waveforms at the
input and output of the comparator, IC2
(Figure 2). T1 and T2 are the time intervals
for which the comparators output assumes levels VS1 and VS2, respectively.
The output voltage from IC2, with its lev-
els changed via a zener-diode

circuit, serves as clock input to
a D flip-flop. From the 7474
VS1
flip-flop, you obtain a squarewave output that is high and
COMPARATOR
t
low alternately for a time peOUTPUT VOLTAGE 0
T1T2
T1
riod T4C(R2RXR1R3)/R1.
This equation indicates that
VS2
the circuit converts a change
in sensor resistance into a
proportional time period
T with sensitivity
Figure 2
T/RS4C(R2/R1).
The following salient features
of Figure 1 merit mention:
kIS
The sensor is grounded;
you can easily vary the conCOMPARATOR
t
INPUT VOLTAGE 0
version sensitivity by varying
T1
T1T2
either R1 or R2.
You can adjust the offset
kIS
value, T0 (about which
changes in T occur because
of a change in the sensors
resistance), by changing These waveforms represent the input and output of
either R3 or R4 without af- comparator IC2.
fecting the conversion sensi Thanks to the current source, the
tivity.
The offset voltages of the op amps al- output is largely insensitive to noise voltter T1 and T2 in opposite ways, such that ages in the line of the current source and
their overall effect on T(T1T2) is not ap- to changes that occur in VS1 and VS2.
preciable.
Consider the example of converting a
OFFSET ADJUST
R3
D2
D1
34.3k
SENSITIVITY
ADJUST
IS
65.4k
R1
6
4
OUTPUT
7474
3 +
LF 411
V0UT
VCC
15V
IC1
2k
2 _
IC2
LF411
R5
Q
3
CLK
10k
D4
R4
1k
RX
Figure 1
1 F
2 _
D3
FF
VCC
15V
R2
IN5287
VEE
15V
RS
(SENSOR)
Pt 100)
VEE
15V
5V
ZENER
NOTE: D1, D2, D3, AND D4 ARE IN4002s.
This simple circuit converts a resistance reading to a time period.
78 edn | August 7, 2003
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design
ideas
Pt-100 (platinum RTD) sensor in the

range of 119.4 to 138.51, which corresponds to a temperature range of 50 to
100C, into time periods of 10 to 12.5
msec. The design is simple. Because the
current through the sensor is a fraction
of IS, IS should be low enough to keep the
self-heating error to an acceptably low
level. This design uses an IN5287 current

regulator; it provides an IS of approximately 0.33 mA and has a dynamic impedance better than 1.35 M. For a better current source, you could use a circuit
based on a voltage-regulator IC. In the
next step, with suitable and practical fixed
values for R1 and C, you adjust R2 until
you obtain the needed sensitivity: 130.82

sec/. Following this step, with a fixed
R4, you adjust R3 to obtain the offset required in the output (T). Figure 1 shows
the values of components for this example. The resistors all have 1% tolerance
and 0.25W rating, and C is a polycarbonate capacitor.
PC-configurable RLC resonator yields

single-output filter
Saurav Gupta, New Delhi, India
OUTPUT
his Design Idea presTRANSCONDUCTANCE
S5
ents a versatile filter cirAMPLIFIER
D6 TO D9
S6
cuit for low-powerS7
consumption instrumenPC
VOUT
D2 TO D5
PORT
S8
tation that you can proR
gram from your PC using
the parallel port. The cirD2
cuit uses analog switches
1k
S1
and latches instead of digiD3
R
tal potentiometers for the
1
2.2k
S2
D4
digital control (figures 1
10k
S3
and 2). By running simple
C1
D5
VIN
100k
S4
software code on the PC,
10V
R
you can configure a single
robust design to work as a
_
lowpass, highpass, or bandR2
+
pass filter, and you can also
select the desired center fre10V
10V
quency, 0 (Listing 1). UnR3
like a similarly controllable
design (Reference 1), this
LP
C2
design is a single-outFigure 1
10V
put-at-a-time filter.
PCMany power-sensitive sys- A PC-configurable filter uses a synthesized
R5
PROGRAMMABLE
tems do not require simul- inductor and analog switches to determine
INDUCTOR
taneous-filter functions.
filter type and center frequency.
The design exploits the
fact that a series RLC resonator can pro- Figure 1, the inductor, LP, is implement- upon the state of switches S1 through S4
vide various filter functions with its ele- ed as a PC-controlled synthesized induc- (determined by PC-port data bits D2
ments. Because the design is based on an tor. The value of the inductor is through D5). The expression for the freRLC section, it is trivial to convert the de- LPC2RPR3R5/R2. Here, RP can assume quency is 0(R2/C1RPR3R5)1/2. You can
sign into a PC-controlled resonator. In any of 15 possible values, depending thus effectively select 15 frequency values.
(This design uses 12 values of practical
interest.) Data bits D6 through D9 from
TABLE 1REPRESENTATIVE PORT SETTINGS AND FILTER PARAMETERS
the PCs parallel port set the state of anaPort setting
Filter type/center
Hex output
log switches S5 through S8. The state of
frequency
D9
D8
D7
D6
D5
D4
D3
D2
from PC
Lowpass/9.93 kHz
0
0
1
1
0
1
0
0
X34
the switches determines the type of filHighpass/22.9 kHz
1
0
1
0
0
1
1
0
XA6
ter.
Bandpass/3.16 kHz
0
1
0
1
1
0
0
0
X58
Figure 3 shows the software-generated
Bandpass/37.3 kHz
0
1
0
1
0
1
1
1
X57
display for the circuit. This design uses a
82 edn | August 7, 2003
www.edn.com
design
ideas
1k
14
15
16
17
18
19
20
21
22
23
24
25
1
2
3
4
5
6
7
8
9
10
11
12
13
OC
1D
2D
3D
4D
5D
6D
7D
8D
GND
VCC
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
EN
74573
100k
IN1
D1
S1
V
GND
S4
D4
IN4
IN2
D2
S2
V
NC
S3
D3
IN3
2.2k
10k
DG308
C1
0.1 F
IN1
D1
S1
V
GND
S4
D4
IN4
IN2
D2
S2
V
NC
S3
D3
IN3
R2
100k
R3
100
C2
0.1 F
R5
1k
R1
4.7k
1/2
OPA2241
VIN
DG308
50
Figure 2
You must take the finite on-resistance value of
the analog switches into account in determining
the center frequency of the filter.
1/2
OPA2241
50
500
V+
V+
IN+ IOUT
Z+
V+
NC
ISET
Z
V
IN
NC
V
V
VOUT
500
MAX436
9.93-kHz bandpass filter for demonstration and testing. Increasing the number
of analog switches can provide a wider
range. Moreover, you could use additional switches for gain programmability. The 74573 latch provides the interface
to the PC. Table 1 shows the port/switch
settings for a few frequency and filtertype selections. Note that the analog
switches (DG308) have a finite operating
on-resistance of approximately about
110; you must take this resistance into
account when you calculate the center
frequency. For precision instrumentation, other switches are available with
operating on-resistances as low as 30 to
50. You can download Listing 1 from
the Web version of this Design Idea at
www.edn.com.
Figure 3
This user-friendly configuration screen allows you to determine filter type and
frequency.
84 edn | August 7, 2003
Reference
1. Gupta, Saurav, and Tejinder Singh,
PC-based configurable filter uses no
digital potentiometers, EDN, Jan 23,
2003, pg 76.
www.edn.com
design
ideas
Single IC provides gains of 10 and 10

Moshe Gerstenhaber and Charles Kitchin, Analog Devices, Wilmington, MA
eal-world data-acquisition systems require amplifying weak signals to match the full-scale input
range of an A/D converter. Unfortunately, when you configure them as gain
blocks, most common amplifiers have
both gain errors and offset drift. The typical two-resistor gain-setting arrangement found in many op-amp circuits has
serious accuracy and drift limitations.
With standard 1% resistors, the circuit
gain can be off by as much as 2%. Also,
the gain can vary with temperature, because each resistor drifts differently. You
can use monolithic resistor networks for
precise gain setting, but these components are expensive and consume valuable pc-board space. The circuits of figures 1 and 2 offer improved performance
and lower cost; they are also smaller. The
86 edn | August 7, 2003
single-SOIC approach
15V
is the smallest
0.1 F
Figure 1
available for this
7 VS
function, and the circuits
4
10k
require no external components. Figure 1 shows
AD628
8 100k
10k
IN
an AD628 precision gain
VOUT
A1
+IN
5
A2
+IN
block connected to pro1 100k
IN
vide a voltage gain of 10.
10k
The gain block itself
VREF 3
RG 6
comprises two internal
VG 2
amplifiers: a gain-of-0.1
0.1 F
difference amplifier, A1,
VIN
followed by an uncom15V
mitted buffer amplifier, This circuit has a precise gain of 10 and uses no external
A2. You can configure it components.
to provide different gains
by strapping or grounding the appropri- nects between the VREF pin (Pin 3) and
ground, instead of to the op amps inputs.
ate pins.
For a gain of 10, the input signal con- With the input tied to the VREF pin, the
www.edn.com
design
ideas
voltage at the noninverting input of

A1 equals VIN(100 k/110 k), or
VIN(10/11). The inverting input of A2
(Pin 6) is grounded; therefore, feedback
from the output of A2 forces the noninverting input of A2 to be 0V. The output
of A1 must then also be at 0V. The voltage on the inverting input of A1 must be
equal to the voltage on the noninverting
input of A1, so both equal VIN(10/11).
Thus, the output voltage of A2, VOUT,
equals
VOUT = VIN
10 100k
1 +
11
10k
10
11 = 10 VIN ,
11
providing a precise gain of 10 with no external components.
The companion circuit of Figure 2
provides a gain of 10. This time, the input connects between the inverting input
of A2 (Pin 6) and ground. Operation is
similar to that of Figure 1, but A2 now in= VIN
88 edn | August 7, 2003
15V
verts the input signal

0.1 F
Figure 2
by 180. With the
VREF pin grounded, the
7 VS
4
noninverting input of A1
10k
is at 0V, so feedback
AD628
8 100k
forces the inverting input
10k
IN
VOUT
A1
+IN
5
of A1 to 0V as well. BeA2
+IN
1 100k
IN
cause A1 operates at a
10k
gain of 0.1, the output of
A2 necessary to force the
VREF 3
RG 6
VG 2
inverting input of A1 to
0.1 F
0V is 10VIN. The two
connections exhibit difVIN
15V
ferent input impedances.
When you drive the VREF This companion circuit to the one in Figure 1 delivers
input (Pin 3) for a gain of an accurate gain of 10.
10, the input impedance
to ground is 110 k; it is approximately efficient lower than 5 ppm/C. The 350 G when you drive the noninverting dB bandwidth is approximately 110 kHz
input of A2 (Pin 6) for a gain of 10. All with a 10-mV input and 95 kHz with a
resistors are internal to the gain block, so 100-mV input. Although 15V supplies
both accuracy and drift are excellent. are appropriate, you may operate these
These circuits have gain accuracy better circuits with dual supplies from 2.25V
than 0.1%, with a gain temperature co- to 18V.
www.edn.com
design
ideas
Video multiplexer uses high-speed op amps

Bruce Carter, Texas Instruments, Dallas, TX
ideo multiplexers route
nance or sync pulses. This feaV
video from several
ture enables the op amp to op4
sources to a single chanerate as a video multiplexer.
1 THS4227
6
SD
1IN
75
nel. Low-end consumer prodThe multiplexer in Figure 1
7
V
5
+
REFERENCE
ucts use CMOS analog switchshows a three-position, single75
8
13
es and multiplexers, such as
pole rotary switch. This switch
the 4066 and 4051. Unfortucould be a break-beforeV
nately, these devices have a semakeor an electronic switch1.3k
1.3k
ries on-resistance that ranges
ing system, perhaps with an
from approximately 100 to 1
intelligent infrared interface.
2
14
SD
+
2IN
75
k, a resistance that is not
To test the quality of signals
16
15
constant with video level and
passed through the video
75
THS4227
that appears in series with the
multiplexer, this design uses
1.3k
signal. The traditional way of
the Lucasfilm THX (www.thx.
1.3k
solving this problem is by
com) test patterns on one
buffering the analog-switch
video input and a high-quali3
12
outputs with transistor stages.
ty NTSC program source on
SD
+
75
3IN
10
11
With this approach, the charanother input. When the con
75
THS4227
acteristics of the CMOS
trast/picture test goes through
Figure 1
1.3k
switch and the buffer
the video multiplexer as the
1.3k
stage degrade video performactive source, the presence of
ance. However, if you forget High-speed video op amps make ideal video multiplexers, devoid of video
the op amp as a buffer has no
the multiplexing action for a distortion or other artifacts.
effect on black and white levmoment and consider just the
els. No bleeding or blooming
buffer-amplifier function, you will see that nance shifts. Figure 1 shows a configura- occurs. Any crosstalk results in a visible
a better approach exists. It must present tion using high-speed op amps in a video- brightening of the center of the picture in
high enough input impedance to the multiplexing application.
the video-program source, but none ocswitch that a 1-k switch resistance is inHigh-speed op amps have plenty of curs. You set the brightness level with the
consequential and that variation in resist- bandwidth for video applications. By us- video multiplexer, not in the circuit. Then,
ance of the switch with IRE (Institute of ing an op amp that has 20 or more times you insert the video buffer into the signal
Radio Engineers) level produces no lumi- the video bandwidth, roll-off and phase path. Youll find that brightness level does
shift at 6 MHz are negligible. An op amp not change. The brightness setup test is
has high input impedance in the nonin- also an ideal way to test for crosstalk beVideo multiplexer uses
verting mode. You can terminate it for tween two video channels. Crosstalk
high-speed op amps ....................................87
75 input impedance by connecting a would show up on the black background
Single resistor tunes lowpass filter ............88
simple resistor. Two equal resistors create as a ghost image of the program mateSimple circuit provides
a gain of two in the noninverting config- rial on the inactive channel; however, none
precision ADC interface ................................88
uration. The gain compensates for a 75 occurs. No color shifts appear in the
back-termination resistor on the op amps SMPTE (Society of Motion Picture and
Buck regulator operates
output. The overall stage gain is therefore Television Engineers) bars with or withwithout a dedicated clock ............................90
one. Now, consider the multiplexing func- out the video multiplexer in the signal
LED driver combines
tion. Some video op amps have a power- chain. The color-bar patterns would also
high speed, precision ....................................94
down feature. This feature allows dis- produce color shifts in the other channel
abling the output of the op amp, if crosstalk were a factor. Human skin is
Filament transformer adjusts
producing a 0V (0 IRE) black level on its the toughest color to get right, and any
line voltage ......................................................96
output. Its output can therefore connect change in skin tone arising from color
in parallel with the outputs of other op crosstalk is apparent. No flesh-tone color
amps, because it contributes no lumi- shifts occur in the test.
CC
OUT
CC
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August 21, 2003 | edn 87
design
ideas
Single resistor tunes lowpass filter

Vladimir Tepin, State Radioengineering University, Taganrog, Russia
ny tunable, second-order, active
RC-filter section requires at least two
thoroughly matched variable resistors. But the lowpass implementation in
Figure 1 provides for wide-range cutofffrequency control using only a single
variable resistor, R. In addition to the resistor, this filter comprises an operational
amplifier, IC2, which serves as a unitygain buffer; two capacitors, C1 and C2;
and a single-pole, double-throw analog
switch, IC1, driven by a periodic sequence
of square-wave switching pulses applied
to the SW input. Thanks to the high-fre-
quency periodic switching, you can simultaneously control the

Figure 1
time constants of both C1
and C2 in their recharging processes using only R. The approximate voltagetransfer function of the filter, assuming
that the switching frequency is much
higher than the filters cutoff frequency,
is:
H(s) =
1
2
s s
+ Q + 1
P
P
where P1/(RC1C2(1) is the

pole frequency; Q
(1)C1/C2 is the
quality
factor; is
0
the online time ratio
(duty cycle);
is the
20
pulse width; and T is the
1.2
M
120
k
12
k
1.2
k
dB
switching period.
40
Obviously, controlling
R results only in varia60
tions of pole frequency
10 Hz
100 Hz
1 kHz
10 kHz
100 kHz
and does not affect the
CUTOFF FREQUENCY
Figure 2
quality factor. So, you
can tune this filter over a
By varying one resistor, you can adjust the cutoff frequency over
wide frequency range,
20 Hz to 20 kHz.
R
C1
IC2
IC1
IN
OUT
C2
SW
This second-order lowpass filter uses a single

resistor to control cutoff frequency.
preserving its passband gain and ripple.

You can achieve a stable value of by using a binary counter. A high-resolution,
digitally programmable potentiometer is
probably the most appropriate choice for
R in this filter. Figure 2 shows the filters
frequency response, simulated in PSpice.
This design tunes the cutoff frequency
over 20 Hz to 20 kHz by varying the resistor value from 1.2 M to 1.2 k, with
C110 nF, C21 nF, 0.5, and a
switching frequency of 500 kHz. Using
this method, you can also implement a
high-order lowpass filter by cascading
second-order sections or by joining them
to multiple-feedback structures.
Simple circuit provides precision ADC interface

Moshe Gerstenhaber and Charles Kitchin, Analog Devices, Wilmington, MA
15V
eal-world measurement requires
C1
0.1 F
the extraction of weak signals
0.1 F
F
i
g
u
r
e
1
from noisy sources. High com4
7
mon-mode voltages are often present
VS
CFILTER
10k
even in differential measurements. The
DIFFERENTIAL
INPUT
usual approach to this problem is to use
AD628
SIGNAL
100k
_
IN
10k
an op amp or an instrumentation ampli8
VOUT
VIN
+ IN
A1
100k
TO ADC
fier and then perform some type of low5
+ IN
A2
1
VOUT
_ IN
pass-filtering to reduce the background
VCM
noise level. The problems with this tra10k
ditional approach are that a discrete opamp circuit has poor common-mode reRG
VS
VREF
jection, and its input voltage range is
2
C2
3
6
0.1 F
always lower than the power-supply voltage. When you use a differential signal
RG
RF
15V
source with an instrumentation-amplifier circuit, using a monolithic IC can An instrumentation-amplifier IC provides precision drive and lowpass filtering for an ADC input.
88 edn | August 21, 2003
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design
ideas
greatly improve commoncreates the second pole.

mode rejection. However, a TABLE 1COMPONENT VALUES FOR 10V P-P FULL-SCALE This time constant comINPUT FOR A TWO-POLE LOWPASS FILTER
standard instrumentation
prises capacitor C2 across
3-dB corner
amplifier cannot handle
resistor RF. Note that this
frequency
second pole provides a
sources greater than the
200 Hz
1 kHz
5 kHz
10 kHz
more rapid roll-off of frepower-supply voltage or sigCapacitor C2
0.01 F
0.002 F
390 pF
220 pF
quencies above its RC
nals riding on high comCapacitor C1
0.047 F
0.01 F
0.002 F
0.001 F
corner frequency (1/
mon-mode voltages. InstruNote: Output is 5V p-p; RF=49.9 k, and RG=12.4 k.
(2
RC)) than does a sinmentation amplifiers using
a single external gain resistor TABLE 2COMPONENT VALUES FOR 20V P-P FULL-SCALE gle-pole lowpass filter.
However, as the input frealso suffer from gain drift. In
INPUT FOR A TWO-POLE LOWPASS FILTER
quency increases, the gain
addition, lowpass filtering
3-dB corner
of amplifier A2 eventualrequires the use of a separate
frequency
ly drops to unity and does
op amp along with several
200 Hz
1 kHz
5 kHz
10 kHz
Capacitor C2
0.02 F
0.0039 F
820 pF
390 pF
not decrease. So, the ratio
external components. This
Capacitor C1
0.047 F
0.01 F
0.002 F
0.001 F
of RF/RG sets the voltage
approach uses up valuable
Note: Output is 5V p-p, RF=24.3 k, and RG=16.2 k.
gain of amplifier A2 at
board space. The circuit of
frequencies below its 3Figure 1 overcomes all of
dB corner and unity gain at higher frethese performance limitations on one
8
quencies.
SOIC.
Figure 2 is a graph of the filters outAn AD628 precision-gain-block IC is
put versus frequency using components
configured as a differential-input ampli1
to provide a 200-Hz, 3-dB corner frefier and a two-pole lowpass filter. This
OUTPUT
VOLTAGE
quency. Note the sharp roll-off between
circuit can extract weak signals riding on
P-P (V)
the corner frequency and approximatecommon-mode voltages as high as
0.10
ly 10 times the corner frequency. Above
120V. The precision-gain block directRF =49.9k; RG =12.4k.
this point, the second pole starts to bely drives an ADC. A separate VREF pin is
C1 = 0.047 F; C2 =0.01 F.
available for offsetting the AD628 output
come less effective, and the rate of atten0.01
10
100
1k
10k
signal so that it is centered in the miduation is close to that of a single-pole reFREQUENCY (Hz)
dle of the ADCs input range. Alsponse. Tables 1 and 2 provide typical
Figure 2
though Figure 1 indicates 15V, the
component values for various 3-dB
circuit can operate with 2.25 to 18V The frequency response of the two-pole filter
corner frequencies and two full-scale indual supplies. The VREF pin can also al- in the circuit of Figure 1 shows a sharp roll-off
put ranges. The values are rounded off to
low single-supply operation; for this between the corner frequency and approximatch standard resistor and capacitor
purpose, you simply bias VREF at VS/2. mately 10 times the corner frequency.
values. Capacitors C1 and C2 must be
The gain block has two internal amplihigh-Q, low-drift units; avoid low-grade
fiers: A1 and A2. Pin 3 connects to function of the internal 10-k resistor at disc ceramics. High-quality NP0 ceramground, thus operating amplifier A1 at the output of A1, and an external capacic, Mylar, or polyester-film capacitors ofa gain of 0.1. The output of A1 directly itor, C1. The gain of A2 is a function of fer the best drift characteristics and setdrives the positive input of amplifier A2. external resistors RF and RG. An external tling time.
The first pole of the lowpass filter is a RC time constant in the feedback of A2
Buck regulator operates without a dedicated clock

Robert Bell, National Semiconductor, Phoenix, AZ
ost switching regulators rely
on a dedicated clock oscillator to
determine the switching frequency of operation. A dedicated oscillator
circuit within the power controller usually generates the clock signal. A class of
hysteretic switching regulators can actually operate at a relatively fixed frequency without a clock, even with changing
90 edn | August 21, 2003
input-line and output-loading conditions. Figure 1 shows a simplified buck

regulator operating in continuous-conduction mode. (The inductor current always remains positive.) The output voltage, VOUT, is equal to DVIN, where D is the
duty-cycle ratio of buck switch Q1 and
VIN is the input voltage. The duty cycle,
D, at fixed-frequency operation is TON/TS,
where TON is the on-time of Q1 and TS is

the switching-frequency period, 1/FS.
Some rearranging and substitution leads
to the expression DVOUT/VINTON/
(1/FS)TONFS.
Now, look at a regulator circuit, which,
rather than using a fixed clock and a
PWM, uses a circuit that turns on Q1 for
a time, TON, thats inversely proportional
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design
ideas
to the input voltage, VIN. Figure 2 shows

a regulator based on this principle. This
regulator does not contain a clock oscillator, yet it remains at a fixed operating
frequency even while the input voltage
varies from 14 to 75V. The two main regulation blocks within this regulator are
the on-timer and the regulation comparator. The
comparator monitors
the output voltage. If the
output voltage is lower
DTS
than the target value, the
TS
comparator enables the
I(Q1)
output switch, Q1, for a
period of time that the
on-timer determines.
The time period of the
I(D1)
on-timer is TONKRON/
VIN, where K is a constant
(1.3 1010), R is a
configuration resisFigure 1
tor, and VIN is the input voltage. If you now substitute TON in
the previous buck-regulator equations,
an interesting result occurs: VOUT/VIN
FSKRON/VIN. If you solve for FS, you obtain FSVOUT/KRON. Because VOUT remains regulated and the K and RON terms
are constants, the switching frequency

also remains constant.
The constant-frequency relationship
holds true provided that the inductor
current remains continuous. At lighter
loading, the current in the inductor becomes discontinuous. (The inductor
cause switching losses greatly decrease at

lower switching frequencies. You derive
the switching frequency in discontinuous mode as follows: The peak inductor
current IPVINTON/LVINKRON/LVIN
KRON/L, where L is the output-inductor
value. The output power is POUTVOUT2/
R OUT LI P 2 F/2FK 2 R ON 2 /L.
Solving for F: F(VOUT2L)/
VIN
(ROUTK2RON2). As you can see,
the switching frequency varies
IL
inversely with the output resistance, ROUT.
Q1
Fixed-frequency operation
without an oscillator offers a
VOUT
low-cost, easy-to-implement
L1
step-down regulator. You
C1
D1
neednt worry about any
VOUTDVIN
loop-compensation or stability issues. The transient response is fast because the cirIn a typical buck regulator, the output is the switching duty
cuit has no bandwidth-limcycle times the input.
iting feedback components.
current is zero for some portion of the Depending on the inductor value and
switching cycle.) At the onset of discon- loading, the operating frequency remains
tinuous operation, the switching fre- constant for most of the output-power
quency begins to decrease. This reduc- range. A desirable reduction in operating
tion is a desirable feature to maintain frequency occurs at low loading levels.
high efficiency as the load decreases, be-
7V SERIES
REGULATOR
14 TO 75V
VCC
LM5007
VIN
SD
UNDERVOLTAGE
LOCKOUT
ON-TIMER
1 F
THERMAL
SHUTDOWN
0.1 F
START
200k
6
SD/
RON
RON COMPLETE
OVERVOLTAGE
COMPARATOR
SHUTDOWN
2.875V
Figure 2
RCL
4
RTN
DRIVER
0.01 F
100 F
LEVEL
SHIFT
SET
S
Q
R Q
CLR
FB
FB
RCL
VIN
COMPLETE
100k
BST 2
UNDER- SD
VOLTAGE
LOCKOUT
REGULATION
COMPARATOR
2.5V
START
300-nSECMINIMUM
OFF-TIMER
COMPLETE
START
CURRENT-LIMIT
OFF-TIMER
10V
SW 1
BUCKSWITCH
CURRENT
SENSE
3k
D1
1k
15 F
0.5A
In this buck regulator, the switching frequency remains constant over a wide range of input voltages.
92 edn | August 21, 2003
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design
ideas
LED driver combines high speed, precision

Richard Cappels, Mesa, AZ
pplications such as turbidity meas- sults from the large differential voltage holds the base of Q3 low enough to enurement and densitometry require across the bases. Similar to the case of Q2, sure that all the collector current from Q2
cleanly pulsed light sources with sta- the collector current in Q4, when it is con- passes through Q4 and the LED. When
ble amplitudes. The LED driver in Figure ducting, is a high and stable percentage the input signal swings positive again, the
1 illuminates retinal neurons in a biolog- of the emitter current. The constant load energy stored in C3 develops a reverse
ical experiment that has similar require- the emitters of Q3 and Q4 present to the bias across Q1s emitter-base junction to
ments. For a given LED at a given current, current source enables the current source quickly deplete the stored charge, resultthe intensity is stable, so switching a sta- to operate continuously, allowing the use ing in a rapid turn-off. Make sure that
you dont exceed the power rating of Q4.
ble current is a simple and effective way of a low-bandwidth op amp.
Q1 is a common-base amplifier con- Take the current and collector-to-emitter
to obtain the needed function. The circuit provides current pulses to the LED nected in a manner essentially the same voltage into account. Using transistors in
with rise and fall times lower than 500 as a TTL-input stage with the exception TO-92 packages and an LED that drops
nsec and overshoot lower than 7%. You of C3, the 1000-pF capacitor across base 2V at 50 mA, the circuit in Figure 1 opcan make the current computer-pro- resistor R4. When the input signal is erates at temperatures greater than 55C
grammable by replacing the poten- greater than 2V, the base of Q1 remains with a jumper in place of R12. If you need
tiometer with a DAC. The circuit comat 2.5V, and the collector of Q1 rises higher currents or use smaller transistor
prises an adjustable, regulated current enough to ensure that Q4 and the LED packages, you may find it necessary to use
source (IC1 and Q2), an overdriven dif- conduct no current. When the input is a finite resistor for R12 to lower the dissiferential amplifier (Q3 and Q4) acting as below 0.4V, Q1s emitter voltage is low pation in Q4 to a safe level.
a switch, and a level shifter (Q1) to shift enough and the base current through R4
the TTL input signal to levels needed to is high enough to saturate Q1. This action
drive the differential pair.
Voltage at the wiper of R6
R12
results in an equal voltage
0
across R9 because of feed12V INPUT
(SEE
back to the op amp. Because
5V TO
+
TEXT)
CIRCUIT
C1
IC1
D3
D4
transistor Q2 has a high al+
100 F
7805
C2
1N916
LED
pha, most of the emitter cur10 F
POWERSUPPLY
rent that produces the voltRETURN
age across R9 comes from the
5V
5V
5V
5V
collector of Q2. Because al5V
pha varies little with temQ3
Q4
R10
R3
2N4401
perature, this current re2N4401
330
OFF
2.2k
mains stable. Transistors Q3
>2V
R1
C3
D1
and Q4 constitute a differen1k
1000 pF
1N916
Q1
ON
tial pair. Depending on
2N4401
<0.4V
which transistor is conductR2
+
10
R11
ing, the emitter of one or the
C5
R4
330
330
F
10k
other sources current to the
TTL INPUT
5V
D2
collector of Q1. When the
1N916
R5
base of Q3 becomes several
100k
hundred millivolts more
R7
R6
positive than the base of
+
330
F
i
g
u
r
e
1
10k
Q2
Q4, current from Q2
LM324
2N4401
_
shunts to the 5V power supC4
R8
ply. No current flows
0.1 F
4.7k
through Q4, so the LED is
R9
off. When the base of Q3 is
10
less positive than that of Q4,
current from Q2 passes
through the LED. The all-ornothing switching action re- This circuit delivers a stable, precision dose of current to an LED.
94 edn | August 21, 2003
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design
ideas
Filament transformer adjusts line voltage

EE Barnes, Cochranville, PA
he problem: I couldnt use my
Heathkit oscilloscope in a house I
lived in during the 1960s because my
lab was too far from the power-line input
to the house, and the line drop through
Figure 1
the house was substantial. Depending on the time of day, the screen
would shrink to perhaps half the normal
display size. I checked the line voltage,
and it was down to just approximately
120V
INPUT
CENTER
TAP
12.6V CENTER-TAPPED
FILAMENT
TRANSFORMER
12.6 V
120+12.6V
OUTPUT
You can use a small, inexpensive filament transformer to buck or boost the ac-line voltage.
100V. I lacked the funds to buy a highwattage Variac to deal with the problem.
The solution: I had a couple of 12.6V
filament transformers, rated at 3 or 4A. I
simply connected one of these in my lab,
with the primary winding across the ac
line (Figure 1). Then, I connected the
secondary winding such that one side
connected to the ac line, and the other
side provided the new, boosted ac line.
Because the transformer had a center tap,
I could adjust the line voltage in 6.3V
steps. The beauty of this approach is that
the transformer handles only the incremental power from the slight boost in
voltage. And the technique uses less space
and is less expensive than using a Variac.
Note that, by changing the polarity of
the filament transformers output, you
can decrease rather than increase the ac
output. This fact could come in handy in
situations in which the line voltage is too
high, causing incandescent-lamp burnout. Reduction in lamp life is a function
of approximately the 13th power of the
overvoltage (Reference 1). For the long,
skinny, and expensive European incandescent lamps that some bathrooms use
as a vertical light source, the lamp-life reduction can be significant. You can buck,
or subtract, the line voltage to increase
the lamps life. Even at nominal line voltage, you can use the method to drop the
voltage to an expensive or particularly inaccessible incandescent lamp.
Reference
1. Fink, Donald and Christiansen,
Donald, Electronic Engineers Handbook,
1975, McGraw-Hill, pg 11-6.
96 edn | August 21, 2003
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design
ideas
Seven-segment LCD uses two-wire interface

Hans Krobath, EEC, Nesconset, NY
ou can connect seven-segment
LCDs using only a two-wire interface (Figure 1). The two-wire interface may be at the field-effect, directdrive LCD or at a serial interface (such as
I2C) that uses an eight-pin microcontroller. The design in Figure 1 uses an Atmel (www.atmel.com) ATtiny12 microcontroller, IC1. VCC can range from 2.7 to
5.5V. Each digit receives drive from an 8bit 74HC164 shift register, which provides seven outputs for each of the segments and one output for a decimal point
or a colon. The data input to the shift register drives the LCDs common terminal.
Software for the eight-pin microcontroller generates the required symmetrical ac square wave between the segments
and the common terminal (Listing 1,
which you can find at the Web version of
this Design Idea at www.edn.com). This
generation entails shifting the seven-segment data and decimal points to the appropriate outputs and setting the shiftregister-input/LCD-common-terminal
to low at a less-than 1-msec rate. A delay
VCC
TO
INTO
IC1
ATTINY12
8
VCC
7
PB2
6
PB1
5
PB0
1
RST
2
PB3
3
PB4
4
GND
a two-byte binary integer, which converts

to decimal for display. A third byte in the
protocol indicates any decimal points or
colons. This data format allows the easiest interface from binary measurement or
calculation. A second protocol accepts
four bytes that directly control the segments and decimal points, allowing the
display of a variety of characters and
symbols possible on a seven-segment display. You can download the source code
and hex object file for the ATtiny12 from
www.edn.com. The code provides a
two-wire I2C interface for a four-digit
Lumex (www.lumex.com) LCD-S401C52TR display.
Seven-segment LCD uses
two-wire interface ..........................................89
Open-collector output provides
fail-safe operation..........................................90
Low-battery indicator uses fleapower ......90
Indicator has electronic lens ....................92
Thermal switches provide
circuit disconnect............................................98
VCC
C1
0.1 F
SRDA
SRCL
of 16 msec followed by shifting the same

data complemented, as well as the complement of the LCD common terminal
with another 16-msec delay, provides the
second half of the required ac waveform.
Because field-effect LCDs takes tens of
milliseconds to respond, the rapid datashifting and display-common changing
does not affect the displayed image. You
can use the two 16-msec delays per cycle
for application processing.
Directly driving the segments allows
the display of not only the numbers zero
to nine, but also any combination of segments and decimal points. You can use
the eight-pin ATtiny12 with a built-in, 1MHz clock oscillator to produce the described two-wire signal and to provide a
two-wire I2C application interface. The
dedicated use of the microcontroller for
display control and its I2C interface frees
the application hardware and software
from timing and resource restrictions.
The implemented I2C interface operates
at 0 to 40 kbps and is bit-synchronous.
One data protocol allows for the input of
Buck-boost regulator suits

battery operation ........................................100
R1
10k

BACKLIGHT CONTROL
SCK
DSD
VCC
IC2
1 2 74HC164 8
A B
CLK
9
CLR
QA QB QC QD QE QF QG QH
3 4 5 6 10 11 12 13
VCC
IC3
1 2 74HC164 8
A B
CLK
VCC
9
CLR
3 4 5 6 10 11 12 13
IC4
1 2 74HC164 8
A B
CLK
9
CLR
3 4 5 6 10 11 12 13
VCC
IC5
9
1 2 74HC164 8
A B
CLR
CLK
3 4 5 6 10 11 12 13
Figure 1
A minuscule 8-bit microcontroller
lets you use a two-wire interface to
drive a seven-segment LCD.
www.edn.com
37 36 5 6 7 34 35 8
32 31 9 10 11 29 30 12
27 26 13 14 15 24 25 16
23 22 17 18 19 20 21 28
1G 1F 1E 1D 1C 1B 1A 1DP
2G 2F 2E 2D 2C 2B 2A 2DP
3G 3F 3E 3D 3C 3B 3A 3DP
4G 4F 4E 4D 4C 4B 4A COL
IC6
LCD40
CM2
CM1
40
1
September 4, 2003 | edn 89
design
ideas
Open-collector output provides fail-safe operation

Susanne Nell, Breitenfurt, Austria
24V
t is common practice to use digital
open-collector outputs for control
2
units in industrial applications. Using
J1 OUTPUT
1
these outputs, you can switch loads, such
as relays, lamps, solenoids, and heaters.
One possible problem inherent to this
FROM CONTROL LOGIC
OR MICROCONTROLLER R
type of output stage is a short circuit
4
2
1.2k
from the output to the supply voltage (of1
Q1
3 IC1
D2
ten, 24V). This condition can destroy the
BD139
1N4004
R3
output transistor if it lacks protection.
100
D1
R2
The simplest approach to solving this
BAT85
10k
problem is to use a fuse. This method has
Q2
a disadvantage, however: You have to reBC548
place the fuse after it blows. A
Figure 1
C1
R1
PTC (resettable) fuse is often too
47 F
2.2k
slow to protect the transistor under the
short-circuit condition. Another possibility is to use a current source as the This circuit provides fail-safe protection of an open-collector output stage.
switching element. This approach is safe
and simple, but it produces heat during ground. If a short circuit exists on the the Schottky diode, D1, is forward-biased
the error condition. If the power rating output J1 or if the impedance of the load and thus discharges C1 and switches off
and the cooling of the transistor are inis lower than specified, the voltage on the Q2. If the steering output from the conadequate, the transistor fails because of collector of Q1 rises because too little trol logic again switches to the high state,
thermal overload. The circuit in Figure base-current feed comes from the control Q2 stays in the switched-off condition
1 shows another simple approach to the logic (via R4) to saturate Q1. If the collec- during the charging of C1. If the output
fail-safe protection of such switching de- tor voltage of Q1 reaches the switching of Q1 is not overloaded, Q1 saturates
voltage on the base of Q2, Q2 turns on, again and stays switched on. If the output
vices.
The principal function of the circuit is and Q1 switches off. You can adjust this has a short circuit to the supply or it is
to switch off the transistor if the voltage switching point with the R1-R2 voltage di- overloaded, then Q1 switches on only
on the collector is higher than a prede- vider. Now, the voltage on the collector of during the charging of C1; after this time,
termined value. Under normal switching Q1 rises to 24V, and the output stays in Q2 switches off Q1. The maximum load
conditions, transistor Q1 should saturate the switched-off condition. To reset the current depends on the value of R4, the
when it turns on with a voltage lower circuit, you must switch the steering out- output voltage from the control logic,
than 0.2V between the collector of Q1 and put from the control logic to low. Now, and the current gain of Q1.
Low-battery indicator uses fleapower

Yongping Xia, Navcom Technology, Redondo Beach, CA
t is always desirable to use a lowbattery indicator that consumes as little power as possible. For a 9V, 450mAhr alkaline battery, a 50-A lowbattery indicator can by itself run the battery down in a little more than a year. Battery-powered devices that need to run
continuously for a long time require battery indicators that consume minimal
power. The circuit in Figure 1, designed
for a 9V battery, uses extra-low power.
When the battery is at full charge (9V),
90 edn | September 4, 2003
the circuit draws 1.4-A current. At the

indication-threshold voltage, 6.5V, the
circuit draws 1 A. Assume that the average operating current is 1.2 A. The
circuit uses 42 mAhr in a four-year period, less than 10% of the batterys rated
energy. A red LED, D2, flashes periodically when the battery voltage drops below
6.5V. IC1, an LTC1540, is a nanopower
comparator with a built-in 1.18V reference. A battery-voltage divider comprising R1and R2, and a positive-feedback
network, R3, feed the positive input of the

comparator. The positive feedback generates hysteresis in the comparator. The
negative input of the comparator receives
bias from the reference voltage, through
the R4-C1 delay circuit.
During normal operation, the voltage
at the positive input is approximately
1.62V when the battery is at 9V. The output of the comparator is at a high state,
such that no current flows through D1
and D2. When the battery voltage drops
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design
ideas
R5
2.2k
below 6.5V, the voltage at the positive input drops below the reference voltage at
D1
R6
1N4148
20k
the negative input. The output of IC1
switches from high to low, thereby lightR3
20M
ing the LED, D2. The switching
R1
D2
Figure 1
changes the voltage at the positive
20M
LED
7
input to 0.58V and causes C1 to discharge
V+
through D1 and R6. Because the value of
3
+
R6 is much smaller than that of R4, the
IC1
8
LTC1540
voltage at the negative input drops
4
_
9V
quickly, according to the time constant
R4
5 HYST
that C1 and R6 set. Once the voltage at the
10M
6 REF
negative input falls below 0.58V, the
R2
comparator switches back to a high state.
2.2M
GND
C1
This change sets the voltage at the posi2
1
0.33 F
tive input to 1.18V, turns off the LED,
and reverse-biases D1, so the reference
charges C1 through R4. When the voltage at the negative input again reaches This fleapower low-battery indicator draws just 1.2-A operating current.
1.18V, the cycle repeats. The LEDs ontime is a function of C1 and R6, and the times are 20 msec and 10 sec, respective- 1.8V)/2.2 k2.1 mA. The average LED
off-time is a function of C1 and R4. With ly, at 6.5V threshold voltage. At this point, current is (20 msec2.1 mA)/10 sec4.2
the values in Figure 1, the on- and off- the LEDs on-state current is (6.5V A.
Indicator has electronic lens

Abel Raynus, Armatron International Inc, Melrose, MA
he method for implementing an extended-scale meter described in an
PW
earlier Design Idea had a conceptual
IOIP
PERIOD
error: The meter impedance must change
R
5 MC68HRC908JK1
continuously, not discretely as expressed
3
IP
OSC
(Reference 1). You could achieve the deC
IQ
sired result by using a digital potenTIME
tiometer controlled by an input voltage
PW
PWM RV
ADC
via an appropriate interface. But this apPB7 PD4
PERIOD
19
6
proach is probably too sophisticated. Fig2
ure 1 shows an alternative approach that
VIN
A
needs only a small and inexpensive microcontroller. The method exploits the
fact that a dc meter measures
Figure 1
the average value of a PWM signal: IAVGIPEAK(TPULSEWIDTH)/(TPERIOD).
An inexpensive microcontroller allows you to expand any portion of the scale of a linear meter.
Therefore, you can control the current
through the meter by changing the pulse and d denotes the expansion of the upper 8-bit hex equivalent. The microcontroller
width of the PWM signal. The PWM- end of the scale. The curves with high program (Listing 1 at the Web version of
generating software determines the law slopes in the graph of Figure 2 corre- this Design Idea at www.edn.com) reads
that governs the change in current in the spond to expanded scales. You can create the hex value and finds a corresponding
meter. In the process of creating this soft- the scale patterns by choosing the thresh- pulse width from a table in its memory.
ware, you can choose expansion of any old voltages (breakpoints) and slopes. Finally, the routine generates the PWM
The circuit resembles an electronic lens signal with the given pulse width. Figure
part of the scale (Figure 2).
The transfer function, a, represents a attached to the meter, which magnifies 3 shows the software flow chart for the
linear meter response; b denotes expan- any chosen part of the scale. The ADC in process.
sion of the beginning of the scale; c indi- the microcontroller of Figure 1 transAs an example of the method, calculate
cates expansion of the middle of the scale; forms the measured input voltage into its the scale expansion of a 100-A dc me-
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design
ideas
A
ter with a measured-voltage range of 0 to

50
40
60
30
70
5V. You need to magnify the portion of
20
80
100
2 VOLTS 3
10
90
the input from 2 to 3V, from 20 to 70%,
1
4
a
100
90
0
leaving 10% at the beginning and 20% at
A
0
5
80
50
the end of the scale (Figure 2, character40
60
30
70
a
70
20
80
istic c). Table 1 shows the steps of the calc
VOLTS
10
90
b
1
60
b
2
culations, which you execute as follows:
0
3 100
CURRENT
45
1. Choose a number (N) and the val50
0
(A)
A
.
ues of the measured input voltages, VIN
50
40
d
40
60
30
70
These parameters depend on the desired
20
80
30
VOLTS
10
90
3
accuracy of the meter scale. As an examc
0
100
20
4
2
1
5
ple, assume voltages with increments of
A
0
10
50
40
60
0.5V for the low slope (Figure 2) and
30
70
20
80
0
0.1V for the high slope (Table 1, column
VOLTS
10
90
0
1
2
3
4
5
d
0
100
2). Therefore, N19.
VIN
34
2
5
01
2. Calculate the 8-bit ADCs
Figure 2
digital output, NIN, for the seBy selecting slopes and breakpoints, you can expand the bottom (b), the middle (c), or the top (d)
lected input voltages (column 3): NIN
portions of a linear meters response.
(256/5)VIN51.2VIN.
3. Transform NIN from decimal to microcontrollers time intervals is a func- ponents R20 k and C10 pF should
hexadecimal format (column 4). The er- tion of the accuracy of its oscillator fre- yield a frequency of approximately 4.5
rors arising from the 8-bit quantization quency, which for the MC68HRC908K1 MHz. The measured frequency is 5.75
are insignificant for an analog indicator. depends on the external RC circuit. The MHz. With the timer/counter prescaler
4. Choose the PWM period, T. This data sheet for the IC recommends a tol- set at 64, the timer-clock period is 44.5
value depends on the rapidity of the in- erance of 1% or less for these components sec. Hence, you can calculate the numput-voltage change and should be rela- to obtain a clock tolerance of 10% or bet- ber of timer cycles for any time interval as
tively short to prevent needle chatter. As- ter. But it is difficult to find a 10-pF1% Nt(t in milliseconds)/(44.5103)
sume T10 msec for easy Table 1 capacitor, so this design uses a less ex- 22.5(t in milliseconds). Thus, for T10
calculations.
pensive 5% capacitor and measures the msec, N10225 or NHEX$E1.
6. Determine the duty cycle () of the
5. Calculate the number of timer cycles oscillation frequency. According to the
for the PWM period. The accuracy of any microcontroller manual, the timing com- PWM signal for each chosen input voltage, VIN, as well as the scale-expansion
pattern (column 5); (IV/IMAX)100%.
RESET
You could either read the current value directly from the diagram in Figure 2 (charINITIALIZATION
acteristic c) or calculate it for three linear
parts of the scale with the following equaMAIN
tion: IVITiSi(VINVTi), where IV is the
current
for the given input voltage VIN, ITi
CLEAR X-REGISTER
is the current for the threshold voltage VTi
CONVERT VIN TO
(i{1,2,3}), and Si is the slope of each linHEX FORMAT BY ADC
ear portion of the scale in Figure 2 (characteristic c). The expressions for the three
START
piecewise-linear segments are as follows:
COMPARE VIN WITH VX
10
VT1 = 0; IT1 = 0; S1 =
= 5 A / V.
FROM THE C MEMORY
2
DOES IT
MATCH?
ARE ALL VX
CHECKED?
COMPARE VIN WITH
THE NEXT VX
YES
YES
YES
VINV0?
SET PWX
FROM MEMORY
GENERATE PWM
SIGNAL
Figure 3
This flow chart shows the steps in the scale-expansion process.
STOP GENERATING
PWM
VT 2 = 2 V ; IT 2 = 10 A;
80 10
S2 =
= 70 A / V.
32
VT 3 = 3V ; IT 3 = 80 A;
100 80
S3 =
= 10 A / V.
53
7. Determine the pulse width of the
PWM signal: PWT (column 6).
8. Calculate the number of timer cycles, NOUT, for this pulse width by using
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design
ideas
the equation for Nt and transform the

number into hexadecimal format
(columns 7 and 8).
9. Enter NIN and NOUT Listing 1.
You can use any microcontroller with
a PWM function and built-in ADC. The
one in Figure 1 has a 12-channel, 8-bit
ADC and the capability to generate a
PWM signal. This microcontroller has 15
I/O pins, which are necessary for executing other functions. If your application
needs only to effect the meter-scale expansion, then the eight-pin 68HC908QT2 is probably a better choice. This microcontroller has a built-in oscillator and
costs less than $1.You can download Listing 1 from the Web version of this Design
Idea at www.edn.com.
Reference
1. Raynus, Abel,Expanded-scale indicator revisited, EDN, Aug 8, 2002, pg
112.T
TABLE 1EXAMPLE OF MIDSCALE EXPANSION

1
x
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
2
VIN
(V)
0.04
0.5
1
1.5
2
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
3
3.5
4
4.5
5
3
NIN
2
25.6
51.2
76.8
102.4
107.5
112.6
117.8
122.9
128
133.1
138.2
143.3
148.5
153.6
179.2
204.8
230.4
250.9
4
NIN
(hexadecimal)
$2
$1A
$33
$4D
$66
$6C
$71
$76
$7B
$80
$85
$8A
$8F
$94
$9A
$B3
$CD
$E6
$FB
(%)
0
2.5
5
7.5
10
17
24
31
38
45
52
59
66
73
80
85
90
95
99
6
Pulse width
(msec)
0
0.25
0.5
0.75
1
1.7
2.4
3.1
3.8
4.5
5.2
5.9
6.6
7.3
8
8.5
9
9.5
9.9
7
NOUT
0
5.6
11.2
16.87
22.5
38.25
54
69.75
85.5
101.25
117
132.75
148.5
164.25
180
191.25
202.5
213.75
222.75
8
NOUT
(hexadecimal)
$0
$6
$0b
$11
$16
$26
$36
$46
$55
$65
$75
$85
$95
$A4
$B4
$BF
$CB
$D6
$DF
Thermal switches provide circuit disconnect

Mark Cherry, Maxim Integrated Products, Sunnyvale, CA
single temperature sensor can blow the fuse. You must take precau- cause the SCR to turn on. Once trigprovide an interrupt to a micro- tions to ensure that the SCR does not gered, the SCR cannot turn off, and the
controller when the measured tem- trigger on a false gate pulse. Power-sup- fuse blows. A small RC filter, R3 and C3,
perature goes out of range. You need ply transients can cause a false high sig- suppresses any gate transients that
multiple temperature sensors when you nal at the output of the OR gate and would otherwise turn on the SCR.
have to monitor more than one hot
TO CIRCUIT
spot. A microcontroller implements the
proper protective action when one of
6
5
the temperature monitors detects an
C1
0.1 F
VCC OUTSET
overtemperature condition. It is some3
OUT
times easier and more cost-effective to
IC1
simply disconnect the offending circuit
MAX6510
5V
SET
1
from the power supply without involvPOWER
R1
D1
SUPPLY
HYST GND
13.7k
ing a microcontroller. A simple therEC103A
4 2
R
mal-protection circuit (Figure 1) in3
10k
cludes two temperature switches, IC1
and IC2, with active-high outputs. TemIC3
C3
perature thresholds for these switches
74HC32
0.033 F
6
5
C
2
depend on resistors R1 and R2, and the
VCC OUTSET
0.1 F
3
switch outputs connect to the inputs of
OUT
IC2
a dual-input OR gate, IC3. OR gates
MAX6510
with more than two inputs are available
SET
1
R2
if you need more than two temHYST GND
13.7k
Figure 1
perature switches. When excessive
4 2
temperature drives either input high,
the OR gates output switches high,
causing an SCR (silicon-controlled rectifier) to crowbar the power supply and This thermal-protection circuit includes a crowbar device, D1, driven by thermal switches IC1 and IC2.
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design
ideas
Buck-boost regulator suits battery operation

Kahou Wong, On Semiconductor, Phoenix, AZ
buck/boost converter can
32.1V to an output of 14.1V.
INPUT
OUTPUT
step a voltage up or down. Such
The MC33166/7 has a 40V maxMC33166/7
a converter is appropriate for
imum
switch rating, and it can acCOMP
V
battery-powered applications. One
commodate 95% duty cycle, so its
IN
GROUND
application derives a regulated
adequate for the application. To
SWITCH
14.1V at 1A from 12V solar panels
implement synchronous rectificaFB
with 9 to 18V variation. In this type
tion for better efficiency, the design
of battery application, efficiency is
uses an additional transformer
5V
an important factor; hence, this dewinding and a MOSFET. The auxsign uses an inexpensive synchroiliary winding provides bias voltnous-rectifier-based MC33166/7
age to turn on the MOSFET when
circuit. It is difficult to find a
the switching-node polarity turns
Figure 1
buck-boost controller in the
negative. Note that the synchromarket. It is even more difficult to
nous rectifier is an important facfind an inexpensive one with an in- This inexpensive buck-boost controller uses synchronous recti- tor in the efficiency of this circuit,
tegrated high-current switch. One fication for high efficiency.
because the input-to-output ratio
way to build a buck-boost convertis approximately 1-to-1. So, the
er is to use a buck regulator with an in- and a resistor pair divides the 14.1V out- duty cycle is approximately 50%, which
ternal switch, such as the MC33166/7 put voltage to 5V for connection to the FB means that the MOSFET conducts for
(Figure 1). The negative-polarity output pin of the IC. So, the IC effectively regu- half the switching-frequency period.
voltage connects to the ICs ground pin, lates an input of VINVOUT1814.1
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design
ideas
Dual comparator thermally

protects lithium-ion battery
Mike Hess, Maxim Integrated Products, Sunnyvale, CA
ost manufacturers recommend
that you dont change lithium-ion
batteries at temperatures lower
than 0C or higher than 50C. You can
monitor both thresholds by adding a
thermistor and dual (window) comparator to a lithium-ion battery charger (Figure 1). Set the low-temperature trip point
at 2.5C and the high-temperature trip
point at 47.5C. A precision voltage reference is unnecessary, because the comparators resistor network is ratiometric,
so variations on the supply voltage, VBUS,
do not affect the trip thresholds. By driving the chargers enable input, EN, the
comparators open-drain outputs ensure
that charging is inhibited when the battery temperature is out of range. As an alternative, you can substitute a dual comparator with push-pull CMOS outputs,
such as the MAX9032, if you also add a

tiny, SOT-323 dual diode (the dashed
lines in Figure 1). The dual comparator
and the MAX9032 are available in SOT23 packages, and both offer built-in hysteresis of 2 or 4 mV, respectively.
IC2 is a single-cell lithium-ion battery
charger that can derive its power directly
from a USB port or from an external supply as high as 6.5V. The 0.5% accuracy of
its battery-regulation voltage allows maximum usage of the batterys capacity. The
chargers internal FET delivers as much as
500 mA of charging current, and you can
configure its SELV input for charging a 4.1
or 4.2V battery. The SELI input sets the
charge current to either 100 or 500 mA,
and an open-drain output, CHG, indicates
the charge status. For near-dead batteries,
a preconditioning capability soft-starts the
cell before charging. Other safety features

include continuous monitoring of voltage
and current and initial checking for fault
conditions before charging.
Dual comparator thermally
protects lithium-ion battery..........................91
Lowpass filter discriminates
step input from noise ....................................92
Voltage-to-current converter
makes a flexible current reference ............96
Circuit forms single-pulse
voltage multiplier ..........................................98
Feedback circuit eliminates
CCD-driver delay mismatch......................100
VBUS
Figure 1
BATT
0.1 F
4.7 F
10k
1%
13k
1%
SELV
IC2
MAX1811
270
+
OUTA
19.1k
1%
10k AT 25oC
HOT (47.5oC): 3.97k
COLD (2.5oC): 28.7k
INB+
500 mA
SELI
INA _
100 mA
OUTA
+
OUTB
10k
CHG
OPEN-DRAIN
OUTPUTS
IC1
LMX393
BATTERY PACK
NTC THERMISTOR
(SUCH AS FENWAL
ELECTRONICS
140-103LAG-RB1)
+ SINGLE
LI-ION
BATTERY
2.2 F
100k
VCC
INA+
IN
EN
EN
GND
GND
OUTB
INB _
18k
1%
GND
DUAL SCHOTTKY
DIODE, SOT-323
CMSSH-3A
NOTE:
YOU SHOULD ADD THE DUAL SCHOTTKY DIODE
IF YOU SUBSTITUTE A CMOS-OUTPUT DUAL
COMPARATOR, SUCH AS THE MAX9032.
While charging a lithium battery from a USB port, this circuit provides thermal protection for the battery.
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ideas
Lowpass filter discriminates step input from noise

Eric Desrochers, Aircuity Inc, Newton, MA
umerous applications exist in industry, particularly with control
systems, in which it is desirable to
remove all but the lowest frequency components from a signal to effectively yield
a dc voltage. This voltage may, for example, serve as a setpoint to a PID controller
in a process-control or an HVAC application, in which the cable that is carrying
the analog signal is exposed to a wide
spectrum of noise, including low-frequency noise components from various
sources. These sources could include
variable-speed drives, ballasts, transients
from switching gear, and motors. In
many cases, noise reduction using a conventional lowpass filter can create adverse
effects in the response time of the system,
even if you use a multipole filter. As an alternative, the circuit of Figure 1 is ideally suited to provide extensive noise reduction for applications such as these
without impairing a systems ability to
track rapid changes in signal level. The
concept involves a lowpass filter with a
slewing mechanism that has significant
performance advantages over other nonlinear-lowpass-circuit topologies, given
its ability to discriminate step changes in
signals from noise.
The basic operation of the circuit is to

momentarily increase the corner frequency of the lowpass filter formed by R6
and C3, using an analog switch, IC1, upon
detection of a step change in signal, allowing VOUT to track VIN with little delay.
IC1 has an on-resistance of about 100,
so when it closes across R6, the corner frequency of the circuit changes from 0.016
Hz to approximately 160 Hz, which is
ample bandwidth for the target applications for this circuit. IC2B, along with R4,
R5, and C2, operates as an error amplifier with a corner frequency of
fCERR1/2R5C21.59 Hz. The amplifier generates an error signal, VERR, that
IC2A measures in reference to VOUT. IC2A
acts as a floating window comparator
that places the lowpass filter into slew
mode when VERR exceeds the predetermined threshold that zener diode D3 establishes. For values of VERR that are
greater than VOUT, diode D2 conducts,
causing the noninverting input of IC2A to
track this signal. IC2A compares the signal to a threshold voltage of approximately VOUT5.2V at its inverting input.
When a negative-step change (VIN
VOUT) to the input, VIN, is of sufficient
amplitude such that VERR becomes ap-
12V
12V
IN/OUT
proximately 5.7V (accounting for the

barrier potential of D2), IC2As output
switches high. This action activates IC1,
causing a short circuit across R6, thus allowing VOUT to track VIN.
For values of VERR below VOUT, the action is similar, except that the inverting input of IC2A tracks VERR through D3 and D4,
and the comparators output toggles high
at the point at which VERR is approximately 5.2V below VOUT. Although the
asymmetry in the window comparators
performance is not of great significance,
you could realize improved symmetry by
replacing D2 with a Schottky diode, which
has a lower barrier potential. The comparators trip points, along with the dc
gain of the error-amplifier stage (IC2B)
determined by the ratio R5/R4establish
the upper and lower deadband of Figure
1. With the values shown in Figure 1 the
circuit triggers to slew in response to negative-step changes in VIN as small as
0.260V and positive-step changes that are
as small as 0.285V. You can realize better
sensitivity by reducing the zener voltage
of D3 or by increasing the ratio R5/R4 and
ensuring that the error-amplifier stage
provides adequate roll-off. The roll-off
must ensure that noise levels that may ex12V
OUT/IN
CONT
VDD
VSS
D1
1N914
R1
10k
C1
0.1 F
IC1
TC4S66F
IC2A
TL074
_
R3
10k
12V
C2
0.01 F
R4
500k
R5
10M
VIN
R6
1M
FC=0.016 Hz
+
Figure 1
This unique lowpass-filter design provides
good noise reduction and retains the ability to track rapid changes in signal level.
C3
10 F
TANTALUM
IC2B
TL074
D2
1N914
4.7V
D4
1N914
D3
1N5230
R2
10k
D5
1N914
VERR
VOUT
+
_
IC2C
TL074
www.edn.com
design
ideas
ist in a given application cannot trigger

the circuit into slew mode.
Another important parameter to consider when choosing component values
for the error- amplifier stage is the step
response of that circuit, because

VOUT
it directly impacts the overall
settling time of the lowpass filter
when it encounters step
VIN
Figure 3
changes in signal. To be conservative, choose values
for R5 and C2 such that
three times the RC time
VOUT
constant they form is
well within the settling
time desired for the lowFigure 2
pass filter. For example,
VIN
with R510 M and This ac-coupled view illustrates more than 65 dB of
C20.01 F, 30.3 sec. attenuation at 30 Hz.
This case represents the approx- lustrates the response of the lowpass-filimate worst-case delay to the re- ter design to a 600-mV step change in VIN.
sponse to a step change in VIN The graphic also illustrates the circuits
that is outside the deadband of significant filtering capabilities on a sethe circuit. In practice, however, vere, 30-Hz, 640-mV p-p noise compothe delay is much smaller for step nent superimposed on the signal. An acchanges in VIN that are larger in coupled view of the filters performance
The circuit in Figure 1 has good step response, even
magnitude, given the first-order at steady state illustrates more than 65 dB
with a nasty 640-mV p-p, 30-Hz noise term superimnature of this circuit. Figure 2 il- of attenuation at 30 Hz (Figure 3).
posed on the input.
Voltage-to-current converter makes

a flexible current reference
Art Kay, Texas Instruments, Tucson, AZ
of IC1 and IC2, respectively, IB2 is the input-bias current of IC2, and AIC2 is the
gain of IC2.
This second equation is useful in understanding error sources and, conse R 2 VOS1
R1VOS2
R1VOS1
+
+
+ IB2 ,
quently, can aid in selecting the compoR1R 3

R1R 3 A IC 2
R1R 3 A IC 2
nents that are best suited to an

ERROR TERM
application. For example, for a nanowhere VOS1 and VOS2 are the offset voltages ampere current reference, you should
consider the error that the inR2
R1
strumentation amplifiers bias
1k
1k
IN
current generates. The example in
C1
Figure 1 uses the INA121P FET15V
0.01 F
input instrumentation amplifier
15V
to minimize the input-bias cur0.01 F
rent. A milliampere reference, on
7 V+
0.01 F
the other hand, would focus more
3
6
7 V+
on the input offset voltage of the
2 + IC1
3 +
OPA277P
IN
8 +
instrumentation amplifier. In
R3
6
RG
1 RG OUT
4 V
IC2
10M
2 IN
general, you can neglect the error
5 INA121P
0.01 F
VREF
that the offset voltage of the op
4 V
15V
LOAD
amp generates if you use a preci0.01 F
sion, low-offset amplifier. HowNOTES: AIC2=1+ 50 k
15V
RG
ever, resistor-mismatch and inIS THE GAIN FOR THE INA121P.
IN THIS EXAMPLE, RG =, SO GAIN AIC2=1.
strumentation-amplifier gain
errors are inevitable, regardless of
This current reference delivers an output
Figure 1
the application.
thats a linear function of the input voltage.
he voltage-to-current converter
in Figure 1 can both source and sink
current. The circuit is more flexible
than some traditional current references
that require different topologies for current sourcing and sinking. Also, you can
easily adjust the value of the current reference by simply adjusting the circuits
input voltage. Performing a simple nodal
analysis generates the following
equation:
V
IOUT =
R 2 VIN
.
R1R 3 A IC 2
You typically set R1 equal to R2.

The output current is a function
of R3 and the gain of the instrumentation amplifier. Note that
capacitor C1 stabilizes the circuit.
In this example, R310 M, and
the instrumentation amplifiers
gain is unity. Varying the input,
VIN, by 10V yields a currentoutput range of 1 A. Performing a more detailed nodal
analysis on the circuit in Figure 1
yields the following equation:
R 2 VIN
IOUT =
+
R1R 3 A IC 2
CURRENT TERM
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design
ideas
Circuit forms single-pulse voltage multiplier

Richard Cappels, Mesa, AZ
5V
t is sometimes necessary for a microcontroller to generate a pulse
whose voltage is higher than the powR1
R2
R4
er-supply voltage of the microcontroller.
1k
56k
56k
The circuit in Figure 1 allows
Figure 1
D1
D2
you to generate 14V pulses from
1N916
1N916
a 5V power supply. An adaptation of the
2N2907
2N2907
circuit provides a 5 to 12V programming
Q2
+
+
Q1
C1
C2
MICROpulse for programming the fuse bits in
14V
100 F
100 F
CONTROLLER
Atmel (www.atmel.com) microcontrollers (Figure 2). The approach is ecoR3
R5
56k
56k
0V
nomical, in that it combines the voltagemultiplier and pulse-amplifier functions.
Moreover, the technique benefits from
5V
the absence of noise that would arise
from a continuously running switching
0V
power supply. In Figure 1, when the microcontrollers output is low, C1 and C2 This simple circuit provides single pulses of 14V from a 5V power supply.
charge in parallel to nearly 5V. When the
microcontroller switches to 5V, it effec5V
tively makes the capacitors appear in series with the 5V pulse, resulting in a pulse
approaching three times the power-supD2
R1
R2
R3
ply voltage at the output. C1 charges
1N916
1k
100k
100k
through D1, and R1 limits the
Figure 2
D1
charging current from the miC2
+
1N916
crocontrollers output to a few mil2N2907
100 F
12V
liamperes. C2 charges through D2 and R3.
+
C1
MICRODuring the output pulse, C1 must sup100 F
R4
CONTROLLER
ply the base current for Q1 and Q2, as well
5V
150k
as the load current. Because the voltage
drop across the diodes decreases as cur5V
rent through them diminishes, after a
0V
charging time of several time constants,
the diode drop is only a couple of hundred millivolts. Therefore, pulses of nearly three times the power-supply voltage
are possible. When the pulses are contin- This variation on the circuit of Figure 1 supplies fuse-programming pulses for Atmel ATV
uous or when they occur within a couple microcontrollers.
of time constants of power application,
the series combination of C1 and the outdiode drops of approximately 1.5V sub- acceptable for some applications.
tract from the output. Additional losses
The circuit in Figure 2 provides a 5 to put of the microcontroller. You get no
can arise from voltage drops across the re- 12V programming pulse for Atmel ATV free lunch with this circuit. If the pulse
sistance of the microcontroller and satu- microcontrollers for the couple of hun- initiation occurs before R3 and R4 suffiration losses in the transistors.You can re- dred milliseconds the ICs require. Be- ciently charge C2 (60 k
100 F6
duce the saturation losses by reducing the cause the output during the time the mi- sec), the voltage is lower than intended.
values of R2 and R4, but be aware that re- crocontrollers output is low needs to be You can reduce the charge time of the
ducing these values increases the droop 5V, you omit the second transistor and circuit by reducing the values of the carate of the output pulse. For some appli- take the output directly from the cathode pacitors. C2 has the most effect because
cations, you could omit D1 and replace D2 of D2. Because the output voltage needs of the high-resistance charging path.
with a resistor, but the result would to go to only 12V, C2 charges from a volt- However, reducing the capacitor values
be longer charging and faster discharging age divider. C2 charges to only 2V, which makes the output pulse droop more
for the capacitors. These trade-offs are then appears in series with the 10V from quickly.
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design
ideas
Feedback circuit eliminates CCD-driver

delay mismatch
Mike Wong, Intersil-Elantec, Milpitas, CA
VCC
n a CCD (charge-coupled device),
packets of charges shift across the array. The transistor array, also called a
C1
bucket-brigade shift register, receives
0.1 F
R1
drive from a dual-phase clock signal.
5k
Dual-phase clock signals comprise two
IC1B
VIN
VOUT
synchronized clock signals that are 180
R3
R4
R2
out of phase. High peak-output-current
50
5k
5k
CCD drivers can buffer the logic-level
EL7212
clock signals and turn them into highvoltage and high-peak-current signals to
C2
R5
R6
R7
drive the heavily capacitive gates of the
0.1 F
50
5k
5k
R8
many CCD transistors. Because of the
3
4
VIN
VOUT
IC1B
speed mismatch of CCD-drivers n- and
5k
VCC
p-channel FETs, the turn-on and -off
D2
D1
C3
7
R9
delay times are poorly matched. Figure
0.1 F
5k
1 shows the outputs of one such current
R10
CCD driver, Intersils EL7212 (www.
5k
elantec.com), with a dual-phase input
clock. The overlap in the output stems
from the turn-on and -off delay misR11
C4
IC2A
IC2B
5k
0.1 F
matches of the EL7212.
EL5220
In a low-resolution system with a
lower clock frequency, the delay mismatch is an insignificant part of the
clock period. As CCD scan rate inFigure 2
creases, the mismatch becomes a
large part of the clock period. You need
This circuit can correct the mismatch in turn-on and -off delays in a CCD-driver IC.
a new approach to correct the CCDdriver delay mismatch. Figure 2 shows
a circuit that uses amplifiers to sense the C2 is 1/2VCC. Amplifiers IC2A and IC2B the amplifiers shuts off, and the errordelay mismatch and correct it. Because compare voltage on C2 with the 1/2VCC correction loop deactivates to prevent
VOUT and VOUT are 180 out of phase, if reference voltage and adjust the voltage output oscillation with no inputs.
their turn-on and -off times coincide between R3 and R6. IC2A provides the
perfectly, the voltage between R4, R7, and phase inversion, and IC2B is the high-dcgain error-correction amplifier. The
output of the error amplifier drives R3
and R6, which shift the voltage offset of
the incoming clock signal. When the offset-voltage level of the input clock signal shifts, the time at which the CCD
driver is triggered also shifts. IC2A and
IC2B guarantee that the proper offset
voltage goes to the input clock signals so
that the delay mismatch cancels. D1 and
D2 rectify the input clock signals and
create
the supply voltage to the
In
a
CCD
driver,
a
mismatch
may
After the circuit in Figure 2 does
Figure 1
Figure 3
IC2A and IC2B amplifiers. When the
occur in the turn-on and -off
its job, the turn-on and -off waveinput signals are removed, the power to
delay times.
forms line up nicely.
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design
ideas
Simple emulator speeds testing

Navdhish Gupta, Chicago, IL
esigning and testing embedded
hardware can be frustrating if you
have to rely on somebody elses perhaps-unready firmware to test your hardware. Often, hardware is ready for testing before debugging and system firmware are available from software developers. Microprocessor emulators are solutions but are often expensive, hard to
use, and sometimes inappropriate for use
by hardware developers, who often just
need to read and configure registers on
devices on their boards. If you are not
primarily concerned with your processors bus performance and need simple
read and write access to registers on chips
on your board to configure and test hardware, then building a simple processorbus emulator, such as the one in Figure
1, may be an attractive option. The simple emulator shown uses an easy-to-use
Basic Stamp microcontroller (www.
parallax.com) on a carrier board and a
small CPLD to emulate a 16-bit ISAlike I/O bus. Figure 2 shows the timing
parameters for the bus (Figure 2a shows
write-cycle timing; Figure 2b shows readcycle timing). Note that the bus emulator
runs much slower than a normal
processor bus but is useful to read and
configure registers that you need to test
hardware. This design uses the 16-bit
PC
BS2
PROGRAMMING
CABLE
GND
DTR
TX
RX
SERIAL
COM
PORT
5 4 2 3 DSR 6
DB9
ISP
EMULATEDPROCESSOR
BUS HEADER
7 RTS
CPLD (LATTICE ISPMACH 4128V)

SA[15:0]
AO ....... A15
BASIC STAMP 2
S1
1
2
3
4
TX
RX
ATN
GND
Figure 1
21 VDD
23 GND
22 RES L
P0
P1
P2
P3
P4
P5
P6
P7
P8
P9
P10
P11
P12
P13
P14
P15
16-BIT SREG
5 ADDPIN
6 ADDCLK
7 DATAPINO
8 DATACLKO
9 DATAPINI
10 DATACLKI
11
12
13
14 LATCHENB
15 DIR
16
17
18
19
20
DO0 ... DO15

DI0
16-BIT SREG
D015
DIO ... DI15
D0
.
.
.
.
.
D15
DATA
LE
16-BIT SREG
IOR
BASIC STAMP 2
CARRIER BOARD
IOW
BALE
ENDIR
VOL_REG
3.3V
5V
A simple emulator uses a Basic Stamp microcontroller and a small CPLD.

www.edn.com
Simple emulator speeds testing ................67

Software snippet provides
improved subset-sum algorithm................68
IC removes nonlinear
temperature effects........................................70
Motor controller
uses fleapower................................................72
ISA-like bus mainly for illustrative purposes; you could emulate almost any
processor bus with a similar setup.
The simple emulator consists of two
parts, the hardware (Figure 1) and the
Basic Stamp firmware (Listing 1, which
you can download from the Web version
of this Design Idea at www.edn.com).
You must connect the emulator itself to
a 5V power supply and a PC with a keyboard, monitor, and serial port, and you
load any simple terminal-emulator software, such as Hyper Term. The serial programming cable you use to program the
Basic Stamp also communicates with the
terminal-emulator software by inserting
a switch, S1, that lets you disconnect or
connect the DTR/ATN connection.
When the switch is closed, you can program the Basic Stamp, and, when it is
open, you can use the terminal-emulator
software to communicate with the Basic
Stamp. You enter commands on the keyboard, and the results appear on the
monitor. The emulator connects to the
board and devices to test and configure,
such as a custom FPGA, through the
boards normal processor bus. (You need
to either socket the original processor or
provide a test port on the board.) You
tristate the original processor or remove
it from the board to use the emulator.
The Basic Stamp firmware emulates
processor-bus cycles by changing the appropriate control signals on its pins. The
design
ideas
ADDCLK
CPLD uses shift registers to interface the
ADDPIN
serial address and data into and out of
SA[15:0]
the Basic Stamp to the emulated 16-bit
parallel address- and data-bus signals.
DATACLKO
The CPLD also conditions the control
DATAPINO
WRDATA[15:0]
signals from the Basic Stamp to the emulator header by performing logicBALE
threshold conversion through CPLD I/O
DIR
buffers. Listing 2, also availFigure 2
IOW
able from the Web version of
this Design Idea at www.edn.com, shows
ENDIR
the Verilog code for the CPLD. Note that,
LATCHENB
although the control signals IOW, IOR,
BALE, and ENDIR come from the basic
(a)
code firmware and the Basic Stamp pins
ADDCLK
and are conditioned through the CPLD;
ADDPIN
they could come directly from a simple
SA[15:0]
finite-state machine in the CPLD if your
BALE
design requires more realistic bus timing.
ENDIR
The Lattice (www.latticesemi.com) ispIOR
MACH 4128V CPLD is a 5V-tolerant device whose inputs you can safely drive
LATCHENB
with voltages as high as 5.5V. It also supDATACLKI
ports as many as 64 I/O lines and is
WRDATA[15:0]
in-system-programmable through the
IEEE-standard 1532 interface. These feaDATAPINI
tures make the CPLD a good choice for
DIR
use in the hardware implementation of
(b)
the logic needed in the emulator.
SERIAL ADD SHIFTED INTO ADD-SHIFT REG

PARALLEL SYSTEM ADD VALID
SERIAL DAT SHIFTED INTO DAT-SHIFT REG

HI-Z
DATA VALID
SERIAL ADD-SHIFTED INTO ADD-SHIFT REG

PARALLEL SYSTEM ADD VALID
LATCHED IN SR
RDATA SERIALLY SHIFTED INTO STAMP
The simple emulator uses Basic Stamp signals for write-cycle timing (a) and read-cycle timing (b).
Software snippet provides

improved subset-sum algorithm
Ivan Basov, Brandeis University, Waltham, MA
he subset-sum problem is one
of the most frequently occurring
NP (nondeterministic, polynomialtime)-complete) problems. It asks
whether a subset of numbers in a set of
positive integers adds up exactly to a given value. A relaxed version of the problem tries to identify a subset of numbers
that adds up to a maximum value no
greater than a given value. This problem
arises in transportation, network design,
scheduling, logistics systems, robotics,
and many other areas. The problem permits you to develop and illustrate the
power of different algorithmic tools. The
problem is as follows:
Given a set of positive integer values
W[1], W[2], ...W[m] and an integer n.0,
does a subset of the values add up to exactly n?

A well-known pseudo-polynomial algorithm (Reference 1) defines a table:
T[ij], 1im and 1jn, to be
T[ij]true if and only if a subset of
W[1],...W[i] sums to exactly j. The algorithm uses O(mn) time to fill in a table
that uses O(mn) space. Table 1 with
n13 shows the true entries and leaves
the false ones blank. This Design Idea
proposes an improved algorithm that
uses O(mn) time to fill in an array that
uses only O(n) space:
SubsetSum(W, m, n)
1. Define a bit array A[j], 1 j n.
2. Initialize the array to zeros.
3. A[0]:1.
4. for i:1 to m do.

5. for j:n to 0 do.
6. if A[j]1 then A[j1W[i]]:1.
7. return A[n].
You can easily prove that the returned
value is 1 if and only if a subset of the
weights adds up to exactly n. The proof is
analogous to the one of the original
O(mn)-space algorithm. The following
routine implements the above algorithm
in C++. It just shifts a bit map m times by
W[j] bits and applies a bitwise OR operation with the bit map from the previous
step.
int SubsetSum(int W[], int m, int n)
{
bit_vector x1;
for(i1; i <m; i++) x |x<<W[i];
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design
ideas
return (x>>n) &1;

}
The bit_vector class overloads bitwise
operators and behaves as an (n+1) bits
integer (with bits ranging from 0 to n).
Now, consider a low-density subset-sum
problem, the case in which the above algorithms produce a bunch of zeros and
only a few ones in the bit array. You use a
dynamically growing linked list and
waste no space for empty elements:
SubsetSumLD(W, m, n)
1. Define, a linked list with only one element with value 0 and with the
Head being equal to the Tail.
2. for i:1 to m do.
3. for Element :Head to Tail do.
4. if Element.value+W[i] n.
5. Insert(Element.value+W[i]).
6. if Head.valuen.
TABLE 1SUBSET-SUM ARRAY

i/j
W[1]=1
W[2]=9
W[3]=5
W[4]=3
W[5]=8
0
T
T
T
T
T
1
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
7. return 1.
8. else.
9. return 0.
The function Insert(value) inserts the
value into the list in descending sorted
order. The function does nothing if an element with the same value already exists.
The disadvantage of the subset-sum algorithm is that it solves only a decision
a yes-or-no problemand doesnt allow
restoring the partition itself. To overcome
this disadvantage, you can use an array of
integers instead of an array of bits and
10
11
12
13
T
T
T
T
T
T
T
T
T
T
T
T
T
T
store the number of ones in the corresponding element. This solution requires
O(n log(m)) space, and the array represents the sum of the rows of the table
T[ij] of the original O(mn)-space algorithm.
Reference
1. Garey, Michael R and Johnson,
David S, A Guide to the Theory of NP
Completeness, Freeman, San Francisco,
CA, 1979.
IC removes nonlinear temperature effects

Kevin Schemansky, Maxim Integrated Products, Howell, MI
common technique for removing
5V
nonlinear temperature-related effects from a dc voltage is to incorporate a temperature sensor that a miR1
croprocessor samples via an A/D con10k
V1
verter. The processor determinesby
9
7
IN
VDDF VDD
mathematical calculation or a temperaR2
2
6
V1
OUT
INP
ture-indexed look-up tablethe
383k
OUT
F
i
g
u
r
e
1
amount of adjustment is necessary
4
INM
at a given temperature and delivers the
IC1
resulting value via a D/A converter.
MAX1452
Though effective, that approach incurs
1 ISRC
design effort, cost, and multiple ICs. An
UNLOCK 10
alternative technique uses a single IC in
5
BDR
UNUSED SECOND
DIO 11
TO ONE-WIRE I/O
an unorthodox fashion (Figure 1). The
TEMPERATURE-COMPENSATED V
R
VSS
3
chip, intended as a low-cost interface to
5k
a Wheatstone bridge, normally provides
3
precision analog-signal processing along
with digitally programmable compensation of gain, offset, and temperature ef- IC1 introduces nonlinear temperature compensation to the analog voltage, V1.
fects. Much of its capability remains unused in this application, but its size and EEPROM, read/write accessible via the boundaries of 69 to 184C are outpre-engineered internal circuitry can one-wire asynchronous DIO pin, pro- side the ICs operating range of 40 to
readily add nonlinear temperature com- vides the user with two independent tem- 125C, the IC can compensate for brief
perature-indexed look-up tables. (This temperature excursions outside its norpensation to a design.
IC1 contains a bandgap temperature design uses only one.) For the table in mal operating range.
sensor whose output is digitized by an 8- use, an 8-bit temperature register indexThe Figure 1 circuit removes temperbit A/D converter, producing a digital es which of 176 16-bit stored values is ature-variable nonlinear offsets from the
representation of die temperature with applied to an internal 16-bit D/A con- analog voltage, V1IN. First, you program
1.45/bit resolution. An internal 768-byte verter. Because the temperature-indexing IC1 for its minimum gain, 39V/V, so the
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design
ideas
R1/R2 attenuation provides an overall

gain of unity. (The internal PGA provides
a gain range of 39 to 264V/V.) Next, program the internal coarse-offset DAC with
0000 binary and the offset-TC DAC with
0000hex, to ensure that they have no ef-
fect on the V1 input voltage. To generate

a compensated output (Pin 2), the output stage adds in the temperature-indexed value of a third DAC (the offset
DAC), whose 16-bit resolution achieves
adjustments as fine as 74 V. After cal-
culating coefficients for the offset DAC,

you program them into the IC via the
DIO pin. The equation for output
voltage is V1OUT39(V1IN/39)
VDD(offset-DAC value/65,536)(offsetDAC sign).
Motor controller uses fleapower

simple, permanent-magnet dc motor is an essential element in a variety of products, such as toys, servo
mechanisms, valve actuators, robots, and
automotive electronics. In many of these
applications, the motor must rotate in a
given direction until the mechanism
reaches the end of travel, at which point
the motor must automatically stop. Although you can use microswitches to
stop the motor at the end of travel, their
size, weight, and cost can be prohibitive,
particularly in low-cost, portable items.
The circuit in Figure 1 implements a lowcost, micropower, latching motor controller that uses current sensing rather
than switches to stop the motor. The design is optimized for a supply voltage of
3 to 9V, making it well-suited to batterypowered applications. To understand

how the circuit works, assume that crosscoupled flip-flops IC1A and IC1B are both
in a reset state, such that the D input of
each one is high. Because both Q outputs
are low, the H-bridge transistors, Q1 to
Q4, are all off, and the motor is idle.
A momentary closure of the Forward
switch latches the Q output of IC1A high
and turns on MOSFET Q2. This action,
in turn, provides bias for Q3, causing the
motor to run in the forward direction.
The circuit is now latched, and, because
IC1Bs D input is now low, any closure of
the Reverse pushbutton has no effect on
the H-bridge, and the motor continues
running in the clockwise direction. IC2
contains a comparator and a bandgap

reference-voltage (nominally 1.182V)
output at the Reference terminal (Pin 6).
The motors armature current generates
a sense voltage, VSENSE , across currentsense resistor RSENSE. The comparator
compares VSENSE at the IN input to a
reference voltage, which R5 and R6 set, at
the IN pin. Under normal running
conditions, VSENSE is lower than the voltage at the IN input, and the comparators output at Pin 8 is low. However,
when the mechanism hits an end stop at
the limit of travel, the motors armature
current increases rapidly, causing a corresponding rise in VSENSE. The comparator detects this increase, and the comparators output goes high, thus resetting
TO VDD
(PIN 14) IC1
C1
100 nF
D1
D3
Q3
Q1
ON/OFF
R2
150
Q4
Q2
FORWARD
5
+
BATTERY
SUPPLY
VB
6
SET
R3
150
MOTOR
D2
D IC Q
1A
3
4013B
2
Q
RESET
4
D4
13
R4
RF
100k VSENSE 100k
D5
IC2
MAX931 OR
LTC1440
7
V+
C2
100 nF
3 IN+
4 IN
12
8
SET
REVERSE
9
Q
D
IC1B 11
Q
RESET
10
OUT 8
R1
100k
RSENSE
CF
100 nF
Figure 1
R6
R5
TO VSS
(PIN 7) IC1
R8
100k
5 HYST
6 REF
1.18V NOMINAL
R7
100k
V
2
GND
1
OV
This latching motor controller uses current sensing, rather than switches, to stop the motor.
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design
ideas
TO VDD
(PIN 14) IC1
Figure 2
TO VDD
(PIN 14) IC3
8
IC3C 9
1
2 IC3A
ON/OFF
4001B
5
6 IC3B
TO Q2
GATE
TO Q4 11
GATE
12
IC3D 13
10
0V
0V
FORWARD
6
SET
5
1
D
Q
IC1A
3
4013B
Q 2
RESET
4
+
BATTERY
SUPPLY
VB
R1
100k
TO VSS
(PIN 7) IC1
13
12
FROM COMPARATOR
OUTPUT, PIN 8, IC2
TO VSS
(PIN 7) IC3
8
SET
Q
IC1B
Q
RESET
10
REVERSE
9
D
11
R8
100k
0V
This addition to the circuit in Figure 1 yields a nonlatching controller, in which the motor runs only when the associated switch is closed.
flip-flop IC1A. Transistors Q2 and Q3 now

turn off, and the motor stops running.
Because IC1Bs D input is now high,
closing the Reverse switch latches IC1Bs
Q output high. This action turns on Q4
and Q1 in the opposite arm of the Hbridge, such that the motor now runs in
the counterclockwise, reverse direction.
IC1As D input is now low, thereby disabling the Forward pushbutton, and the
motor continues to run in the reverse direction until the mechanism hits the opposite end stop. Once again, the comparator detects the increase in armature
current, and the comparator resets IC1B
and turns off the motor. The motors cutoff threshold is a function of RSENSE, R5,
and R6, and the bandgap voltage at the
REF pin. RSENSE should be in the region of
a few ohms to ensure that VSENSE is also
small when the motor is running under
normal loading conditions. Keeping
VSENSE low makes practically all of the
supply voltage available to the motor and
ensures that the gate-source voltage of Q2
and Q4 is as large as possible. You should
choose values greater than 300 k for R5
and R6 to minimize the loading on the
REF pin. In noisy environments, it may
be necessary to decouple the IN pin.
Filter components RF and CF serve a
dual purpose. They are necessary to
smooth the relatively lumpy voltage appearing across RSENSE and are also essential to prevent the motors in-rush cur-
rent at turn-on from tripping the comparator. Values of 100 k and 100 nF
should be adequate, but some experimentation may be necessary to determine the best time constant for your application. Reset components C2, D5, and
R7 ensure that the comparators output is
high at power-up. You should select all
transistors in the H-bridge to produce
minimal saturation voltage when the devices conduct the maximum motor current. Choose low-VCE(SAT) devices for Q1
and Q3, and make sure that MOSFETs Q2
and Q4 can receive full enhancement at
the minimum operating voltage. Depending on the type of MOSFETs you
use, you may need to add a resistor in series with each gate to prevent spurious
oscillation.
You should select resistors R2 and R3 to
provide adequate base drive for Q1 and
Q3 at the lowest supply voltage. Depending on the application, it may be possible to replace Q1 and Q3 with p-channel
MOSFETs, in which case R2 and R3 can be
fairly large. Freewheeling diodes D1 to D4
are necessary to commutate the currents
generated by the motors back-EMF at
turn-off. You may require capacitor C1 to
suppress any noise that the motors
brushes produce. The circuits quiescent,
motor-idle current drain is extremely
low, making it ideally suited to batterypowered applications. Measurements on
a breadboard circuit operating from a 9V
supply voltage reveal a quiescent current

of just 9.5 A. You can adapt the circuit
to produce a nonlatching version in
which the motor runs in the forward or
the reverse direction only while the associated switch is closed. However, this approach is not simply a matter of gating
the comparators output with each
switch; that action merely causes the motor to hiccup at the cutoff point. Instead,
you must again latch the comparators
output and add some extra logic in the
form of a quad NOR gate. Figure 2 shows
the arrangement, in which NOR gates
IC3B and IC3D control the H-bridge, and
the comparator controls the flip-flops reset pins as in Figure 1.
The motor runs in the forward direction only while you depress the Forward
button; releasing the pushbutton stops
the motor. While the switch is closed, IC3A
holds IC1Bs D input low, thereby ensuring that the Reverse switch can have no
effect on the motor while the Forward
switch is closed. Once you release the Forward switch, you can use the Reverse
switch to reverse the motors rotation.
Again, the motor runs only while you depress the pushbutton. You can see from
the symmetry of the circuit that closing
the Reverse switch locks out any operation of the Forward switch. When the
mechanism hits an end stop in either direction, the comparator resets the relevant flip-flop and shuts off the motor.
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design
ideas
DDS circuit generates precise PWM waveforms

Colm Slattery, Analog Devices, Limerick, Ireland
ulse-width moduVDD
lation is a simple
way to modulate,
LOWPASS
or change, a square wave.
3V
MCLK
FILTER
In its basic form, the
duty cycle of the square
AD9833
SCLK
DDS
AD8611
wave changes according
ACTUATOR
SDATA
R1
R
to some input. The duty
L
FSYNC
cycle is the ratio of high
R2
and low times in the
square wave. A waveVDD
form with a 50% duty
cycle would be
Figure 1
OPTICAL
high for 50% of
FIBERS
DAC
the time and low for 50%
8052
A DDS circuit combines with a comparaADC
of the time, and a waveform with a 10% duty tor and a microcontroller with an interADC824
cycle would be high for nal DAC and ADC to generate high-reso10% and low for 90%. lution PWM outputs.
Many applications exist
for PWM, including motor control, ser- ly program the frequency without chang- mum frequency is 266 Hz. The resolution
vo control, light dimming, switching ing component values, and fine-frequen- at 200 kHz drops to approximately 6 bits.
power supplies, and even some audio cy tuning is difficult. Another problem Thus, the ADC832 is the ideal low-cost
amplifiers. In applications such as MEMS with this method is that accurate control approach for low-frequency, high-reso(micro-electromechanical-system) mir- of the duty cycle is difficult.You could use lution applications but not for a highror-actuator control, a feedback system a digital potentiometer in place of the frequency, high-resolution application.
needs to regulate the PWM. A circuit mechanical one, but this replacement remonitors and controls the PWM output sults in a more costly design. A second DDS IMPLEMENTATION
Applications requiring high-resolution
and varies the duty cycle according to the method for generating PWM waveforms
requirements of the application. The out- uses an ADC824 MicroConverter. In frequency tuning and pulse-width-modput frequency tunes the actuator, and the addition to providing two PWM outputs, ulation tuning in real time can use a DDS
duty cycle sets the actuators speed. The it also integrates ADCs, DACs, an 8052- (direct digital synthesizer) to provide a
feedback loop controls the threshold lev- compatible microcontroller, and flash high-accuracy sawtooth waveform with
el. This Design Idea describes a high-fre- memory. You can configure the PWM fine-frequency resolution across a large
quency, high-resolution PWM with feed- with resolution as high as 16 bits. How- bandwidth. You can then use this signal
back control. First, it might be useful to ever, the programmed frequency affects as the input to a comparator in either
the resolution of the PWM. The frediscuss some PWM theory.
quency and resolution of the PWM are as
DDS circuit generates
ALTERNATIVE ARCHITECTURES
follows: FPWM16.777 MHz/N, where N
precise PWM waveforms ............................85
Traditional PWMs use two op amps to is the resolution in bits.
High-CMRR instrumentation amp works
An internal PLL derives the 16.77generate a sawtooth waveform, a potenwith low supply voltages ............................88
tiometer to generate a dc reference, and MHz reference clock from a 32-kHz crysa comparator to generate the PWM out- tal. This reference clock samples the outUse a DAC to vary LVDT excitation ..........92
put. The advantage of this type of design put of the PWM. As stated, N, the
is that the circuit is practical and inex- number of bits, is the resolution of the
pensive. Unfortunately, you cannot easi- PWM. For 16-bit resolution the maxi-
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October 2, 2003 | edn 85
design
ideas
open- or closed-loop applications. Figure 1 shows an easy method of generatAMPLITUDE/SINED/A

PHASE ACCUMULATOR
CONVERSION ALGORITHM
CONVERTER
ing programmable square waves with
programmable duty cycles. The AD9833
DDS drives a programmable triangular
TUNING WORD SPECIFIES
wave into one input of the AD8611 comOUTPUT FREQUENCY AS A
FRACTION
OF REFERENCEparator and controls the frequency of the
CLOCK FREQUENCY.
output waveform. The feedback loop
from the actuator controls the threshold
DIGITAL DOMAIN
level of the comparator. The
F
i
g
u
r
e
2
AD8611 is a single 4-nsec comparator with a latch function and comple- A DDS circuit includes a numerical-controlled oscillator employing a 28-bit phase accumulator, a
mentary output. The input signal from sine ROM, and a 10-bit D/A converter on a single chip.
the DDS connects directly to the inverting input of the comparator. The output
feeds back to the noninverting input given a reference interval (clock period), the phase and master-clock frequency.
through R1 and R2. The ratio of R1 to you can determine the phase rotation for The phase accumulator provides the 28bit linear phase. The sine ROM stores the
R1R2 establishes the width of the hys- that period:
amplitude coefficients of the output sine
teresis window with VDAC setting the cenPhasesdt;
wave in digital format. The DAC converts
ter of the window or the average switchPhase/dt;
the sine wave to its analog domain. If you
ing voltage. The output switches low
f(PhasefMCLK)/2,
when the input voltage is greater than VHI where dt is the reciprocal of fMCLK, the bypass the sine ROM, the part delivers
and does not switch high again until the master clock. You can generate output triangular waveforms instead of sinufrequencies using this formula, knowing soidal waveforms. You program the deinput voltage is lower than VLO,
as the following expressions
vice by writing to the freshow: VHI(V+1.5 VVDAC)
quency registers. The
(R1/(R1R2))VDAC, and VLO
analog output from the
SAWTOOTH CONTROLS
VDAC(R2/(R1R2)), where V is
part is then fOUT(fMCLK/
PERIOD OF OUTPUT
the positive supply voltage to
228)(frequency-register
SQUARE WAVE;
OUTPUTS AT 1 MHz.
the comparator and VDAC is the
word).
level that the DAC sets. The
The DDS outputs have
AD8611 can accept a 100-MHz
28-bit resolution, so effecsignal with 400-mV p-p levels
tive frequency steps on
(a)
and can also accept input sigthe order of 0.1 Hz are posnals in the tens of millivolts.
sible to a maximum of apThe AD9833 can provide sinuproximately 10 MHz. Two
soidal- and triangular-wave
phase registers provide 12outputs using the DDS archibit phase resolution. These
tecture. It includes a numeriregisters phase-shift the sigOUTPUT SQUARE
cal-controlled oscillator emnal by PSHIFT(2/4096)
WAVE RESPONDS
TO THRESHOLD
(phase-register word). A
ploying a 28-bit phase accumuCHANGES.
25-MHz crystal oscillator
lator, a sine ROM, and a 10-bit
provides the master referD/A converter on a single chip
(b)
ence clock for the DDS. The
(Figure 2).
output stage of the DDS is a
You typically think of sine
voltage-output DAC with a
waves in terms of their magnitypical swing of 0.7V p-p
tude expression: a(t)=sin(vt).
into an internal 200 resisHowever, these waveforms are
tor. Adding load resistor RL
nonlinear and are difficult to
reduces the peak-to-peak
generate. On the other hand,
output voltage, thus allowthe angular information is lining you to tune the peak-toear in nature. That is, the phase
peak output of the DDS to
angle rotates through a fixed
the input range of the comangle for each unit in time.
(c)
parator. A filter stage generKnowing that the phase of
Applying different thresholds to the comparator
Figure 3
ally appears on the output
a sine wave is linear and
in the circuit of Figure 1 has these effects.
86 edn | October 2, 2003
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design
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of the DDS. The purpose of this stage is

to filter feedthrough from the reference
clock, images, and higher frequencies and
to bandlimit the signals under consideration.
Figure 3 shows typical output plots
from the AD8611 comparator in Figure
1. The input signal from the DDS is a triangle wave set to 1 MHz. Each plot shows
the PWM output for various threshold

voltages. In the closed-loop circuit of Figure 1, you can tune the output of the
PWM to 12-bit accuracy. You have access
to many possible ways of providing
pulse-width modulation; the approach
depends on the application. For low-resolution applications, traditional methods
using op amps and potentiometers are
acceptable and inexpensive. For low-frequency, high-resolution applications, the

ADC832 provides a one-chip approach
with added features for free. For high-resolution, high-frequency applications requiring fine-frequency tuning, you can
combine a DDS and a comparator to generate precise, high-frequency PWM
waveforms.
High-CMRR instrumentation amp works

with low supply voltages
Dobromir Dobrev, Jet Electronics, Sofia, Bulgaria
In Figure 1a, VA, VB, VC, and VD are the
two differential amplifiers inputs, and AD
is the gain. The time constant 2R3C defines the highpass cutoff frequency. Figure 1b shows the detailed circuit. The input stage comprises op amps A1, A2, A3,
and A4. A1 and A2 are the main gain stages.
Because their inverting and noninverting
inputs are at the same potential, the inVOUT = A D (VAVB + VCVD ) =
put voltages supply the R3 resistors. The
2sR 3C
buffers A3 and A4, along with the R2 reAD
.
sistors, produce an amplification factor,
1 + 2sR 3C
1R3/R2, for the current in R3, because R2
VIN ()
and R3 connect to equal
potentials. This circuit
+
R4
VA
A1
structure is the heart of
_
the design. The voltage
R1
on capacitor C has no ac
component, and A1 and
R3
VA
A2 each amplifies oneR2
+
+
1
VIN ()
R4
R4
VB
half of the differentialR3
AD
A3
VB
input ac signal. C filters
_
_
+
the input dc compoVOUT
VOUT
A5
+
nent, which appears at
C
C
_
the A3 and A4 outputs.
VC
_
+
The
second stage is a
R
R
VC
4
4
AD
R3
A4
unity-gain,
four-input
VD
+
_
1
VIN ()
adder-subtracter stage.
R2
R3
It implements the above
equation, where AD is
1R1/(R2||R1). AssumR1
(a)
_
R4
ing R3
R2, AD1
A2
+
VD
R1/R2.
Figure 1
VIN ()
Another possible implementation for the
(b)
second stage could use
Capacitor
C ac-decouples the simplified amplifier circuit
(a)
(b)(a); the detailed circuit (b) uses gain stages and an adder-subtwo differential-chantracter stage.
nel ADCs, producing a
odern battery-cell voltages of 3
to 3.6V require circuits that offer
efficient low-voltage operation.
This Design Idea proposes an ac-coupled
instrumentation-amplifier design that
features high CMRR (common-moderejection ratio), wide dc input-voltage
tolerance, and a first-order highpass
characteristic. Most of these features stem
from a high-gain first-stage design. The
circuit uses popular-value and -tolerance
components. Figure 1a shows the sim-
plified amplifier circuit. The general

principle is that the capacitor, C, and the
R3 resistors buffer and ac-couple the input signal. The second stage comprises
two differential amplifiers, AD. Each of
them amplifies half the differential input
signal. A summing operation yields the
following expression for VOUT:
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design
ideas
3V
R7
10k
VIN (+)
R4
100k
+
IC1A
MCP607
_
D1
BAV99
C2
6.8 nF
C4
680 pF
R5
2M
R1
200k
+
C1
10 F
R3
1.6M
R8
1M
IC3B
MCP607
_
R2
1k
R4
100k
+
IC2A
MCP607
_
R4
100k
REFERENCE
C3
1 F
IC3A
MCP607
_
VOUT
R4
100k
_
R4
100k
IC2B
MCP607
+
R3
1.6M
Figure 2
R2
1k
C4
680 pF
C2
6.8 nF
_
VIN ()
R7
10k
D1
BAV99
IC1B
MCP607
+
R1
200k
R4
100k
This high-CMRR instrumentation amplifier operates from extremely low supply voltages.
digitized VOUT, ready for microcomputer processing. If a 5V supply is available, it is possible to obtain VOUT by using two difference amplifiers on one
chip, such as the INA2134. You can calculate the minimum CMRR as:
A D(14)
A D5
=
A CM(14) A CM5
AD
1.5A D
=
,
4 /(1 + R 4 / 2R 4 )
4
CMRR =
where AD(1-4) is the differential gain of

amplifiers A1 through A4, ACM(1-4) is the
common-mode gain of these amplifiers,
AD5 is the differential gain of amplifier
A5, and ACM5 is the common-mode gain
of A5. is the tolerance of the R4 resistors in the circuit. A very important parameter is the op amps input offset voltage, especially for A3 and A4. The A1 and
A2 offsets do not contribute to error, because they add to the input signals dc
component, which capacitor C cancels.
The maximum output-voltage error attributable to op-amp offset voltage is:
R
VMAX = ( VIOA 3MAX + VIOA 4MAX ) 1 + 1 +
R2
3VIOA 5MAX 2A D VIOA 34 MAX ,
where VIOMAX are the maximum offset

voltages of the corresponding op amps.
In selecting op amps, you should note the
following: A3, A4, and A5 should be lowoffset and high-CMRR types, and A1 and
A2 should have high open-loop gain,
CMRR, and gain-bandwidth products.
Figure 2 shows a practical amplifier circuit. The power supply is one 3V lithium
battery. You can use several op-amp
types, such as MCP607s or OPA2336s.
Because of the input common-mode
voltage range, you set the signal ground
to one-third of the supply voltage. The D1
diodes prevent the circuit from latching
up. The R7-C4 networks provide RF-noise
filtering at the inputs. You derive the networks values from the following consideration: With R7C4(R1||R2||R3)C2
R2C2, the high-frequency zero in the amplifiers transfer function cancels:
VOUT
2sC3R 3
=
VIN (+)VIN (1 + sC4R 4 )(1 + 2sC3R 3
R1 1 + sC2 (R1 R 2 R
.
1 + R R
1 + sC2R1
2
3
A D (s) =
The circuit has the following advantages:

The first stage ensures the overall
gain, thus providing high CMRR
without the use of high-precision
resistors in the second stage.
By connecting the low-frequencydetermining RC network to the inverting inputs of the op-amp pair
that amplifies the input signal, the
circuit needs no additional input
buffers.
The circuit delivers a standard, firstorder highpass characteristic, using
passive components with popular
values and tolerances.
The differential-input range is as
high as 2V, using a 3V supply.
The circuit consumes low supply
current and power: approximately
120 A, 0.4 mW.
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design
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Use a DAC to vary LVDT excitation

Anthony Di Tommaso and Ljubisa Milojevic, ABB Inc, Natrona Heights, PA
VDTs (linear variable differential
PRIMARY
SECONDARY
transformers) are electromechanical
measuring devices that convert the
3
position of a magnetic core into electrical signals. You generate these signals via
1
excitation on the primary side. The re4
sults on the secondary sidetypically,
5
two secondary windingsdepend on the 2
position of the core (Figure 1). The excitation typically ranges in ampli6
Figure 1
tude from 1 to 10V and in frequency from 1 to 10 kHz, depending on
the type of LVDT you employ. Tradi- An LVDT is an electromechanical measuring
tionally, for one circuit to provide such device that converts the position of a magnetic
variability in frequency and amplitude, core into electrical signals.
you can use either an LC tank with adjustable components or a sine-wave gen- than the LC-tank circuit. The circuit in
erator under microcontroller control. It Figure 2 presents an alternative.
can be difficult to achieve precision over
Rather than using a sinusoidal signal to
time and temperature with the LC-tank excite the LVDT, a triangular wave comes
circuit because of variations in passive from the integration of a square-wave
components. You also must manually output provided by a microcontroller
perform calibration. You can more easi- timer. With the use of a current-output
ly obtain precision over time and tem- DAC, such as the AD7564 from Analog
perature through the use of a microcon- Devices (www.analog.com), you can cretroller-controlled sine-wave-generator ate a circuit that provides an alternative at
chip, and calibration can be automatic, a lower cost than that of a sine-wave-genbut the method incurs a greater expense erator chip and with greater ease of mod-
VCC
3
SDIN
CLK
RESET
GAIN_DAC_LD
FSIN
SDOUT1
15
SDIN
16
12
13
14
11
20
24
R3
10k
TIMER
OUT
R2
11k
5
9
2
7
IC2B
AD712
Vcc
R1
11k
R4
10k
3V
VCC
VDD/REFA
CLKIN
IOUT1A
CLR
IOUT2A
LDAC
VREFB
FSIN
IOUT1B
SDOUT
IOUT2B
RFBA
21
22
23
25
28
IC1
AD7564
RFBB
NC
RFBC
RFBD
IOUT2C
IOUT2D
VREFD
VREFC
IOUT1C
18
A0
17
A1
19
IOUT1D
26
10
C1
470 pF
4
8
VDD
VDD
DG AG
ND ND
1 27
Q1
MMBT2222A
4
2
3
Figure 2
This circuit uses a triangular wave from a DAC
to excite an LVDT.
IC2A
AD712
Q2
MMBT2907
8
VDD
3
VDD
ification than with an LC-tank circuit. Beginning with the microcontroller, the frequency of the excitation wave depends on
the configuration of the microcontrollers
timer. You can configure a free-running
timer, for example, to toggle the output
based on the comparison match of a preset count. You base the count on the desired frequency output and the timers internal clock rate. You then adjust the
output of the microcontrollers timer to
remove offset. You need to eliminate as
much offset in the signal as possible because such offset adversely affects the
transformation process.You can use an op
amp to remove the offset because the offset is constantin this case, half the voltage that powers the microcontroller. In
general, you should choose an op amp
with low offset and low bias, not only for
the difference stage, but also later.
Once you center it about common, the
signal becomes a triangular wave. The integrator you use is basically a single-pole,
lowpass filter with a configurable (via the
DAC) corner frequency. The corner frequency you choose guarantees that integration of the excitation signal occurs. To
accommodate variability in
frequency and amplitude,
the DAC provides an easy
interface. With two channels of the AD7564, the circuit can emulate variable
resistors for the feed-forward and the feedback of
the integrating op amp.
(The other two channels
could serve for the demodulation gain of each LVDT
secondary.) You can use
these resistors to form the
corner frequency for the
lossy integrator and to establish the gain through the
circuit, ensuring that the
signal is integrated and that
the amplitude of the excitaLVDT
PRIMARY
tion signal is appropriate
INPUT
for the LVDT.
You need to make several calculations in advance
to determine the configurawww.edn.com
design
ideas
TIMER OUTPUT
tion of the DAC and the establishment

PRIMARY INPUT
of the resistances. According to the data
sheet, the resistance of the R-2R ladder in
SECONDARY 1
the Analog Devices AD7564 DAC is typOUTPUT
ically 9.5 k . You can calculate the feedSECONDARY 2
back resistance using the following forOUTPUT
mula: RFB1/(2fDC), where fD is the
desired corner frequency of the integrator and C is the value of the capacitor you
use. You can then assemble the data word
Although what appears on the secondary side differs from the excitation signal,
for that effective resistance accordFigure 3
it is sufficient because of the inherent filtering properties of the LVDT.
(40969500)/R
,
where
ingly: NFB
FB
NFB is the digital word loaded into the
DAC. The feed-forward resistance of the other components.
put of each secondary side generally
integrator circuit is then RIRFB/(gain
You have some flexibility in the type of transforms into a constant root-meanfactor), where the gain factor depends on excitation signal the circuit uses because square or mean-absolute-deviation valthe desired output amplitude. The data it is common practice to calibrate an ue. In the situation of two secondary
word for that effective resistance becomes LVDT. Figure 3 illustrates the output of coils, a comparison between those values
NI(RFB/RI)NFB or NI(gain factor) the excitation circuit and the results on occurs. As long as you excite both coils
NFB. In most cases, you may need to use the secondary side of the LVDT. Al- in the same mannerwhich is guaranadditional drive current from the output though what appears on the secondary teed because only one primary coil exof the lossy integrator to drive the pri- side differs from the excitation signal, it istsand the output signal is of sufficient
mary coil of the LVDT. This approach is sufficient because of the inherent fil- resolution, then a triangular wave can exmay entail the addition of transistors and tering properties of the LVDT. The out- cite such an LVDT.
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design
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High-fidelity triangle-wave generator

consumes only 6 A
Glen Brisebois, Linear Technology Corp, Milpitas, CA
deal triangle waves involve infinite
d2V/dt2, so high-fidelity triangle waves
entail very high bandwidths. MicroR2
power circuits have fairly low bandwidth,
+
so generating good triangle waves with
C1
such circuitry becomes problematic. The
_
circuits of Figure 1 show two methods of
generating triangle waves. The solitarycomparator circuit uses a relaxation-oscillator approach with the triangle approximation assuming an RC (expoTRIANGLE
(a)
nential) nature (Figure 1a). When you
need better linearity, adding an integrator improves the triangle approxiFigure 1
mation (Figure 1b). Both circuits
TC7S14F
R4
536k
1.5V
10 nF
R3
1M
1.5V

OP AMP
R1
100k
R2
1M
COMPARATOR

1.5V
LTC1542
A simple CMOS inverter provides high-bandwidth current assist, improving the waveform
drastically with minimal impact on supply current.
www.edn.com
R3
1M
COMPARATOR
_
OP AMP
R1
TRIANGLE
+
R2
R1
100k
R3
1.5V
SQUARE
COMPARATOR
_
(b)
SQUARE
1.5V
These popular methods of generating triangle waves have drawbacks, especially when your design
requires low-power operation.
1.5V
Figure 2
C1
10 nF
R1
include a hysteretic-feedback path, as well

as an RC or integrator feedback path
comprising R3 and C1. The hystereticfeedback path keeps changing the direction of the RC integrator and setting the
new target voltage, and the RC integrator
sets the rate of change toward the new
target. These circuits are robust and find
wide usage.
The problem arises when you simultaneously require ultralow power consumption and relatively high-frequency
operation. This scenario makes phenomenal demands on the micropower op
amp. Consider that, every time the comparator reverses direction, it slams an instantaneous current into or out of the op
amps output through the two feedback
paths. This situation would be acceptable,
except that the amount of current it
slams is greater than the op amps total
supply current. The result is a disastrouslooking waveform with enormous glitches stemming from the fact that the op
amp cannot provide the instantaneous
output-switch current demands. You can
gain some improvement by increasing

the resistor values and reducing the capacitor values. However, the improvements are only incremental, and the circuit becomes noisier and more
susceptible to interference.
High-fidelity triangle-wave
generator consumes only 6 A..................81
High-current driver
serves home-power-line modems ............82
Circuit forms fast, portable
light pulser ......................................................84
3V supply delivers
12V p-p to piezo speaker..............................86
Code provides adjustable
differential drive for robots ..........................88
Microcontroller produces
analog output ................................................88
Single transistor provides
short-circuit protection ..................................90
design
ideas
But take heart; a simple and inexpensive solution is at hand. Why not let a
CMOS inverter provide the instantaneous current and let the op amp simply
provide the precision linearizing current?
Figure 2 shows the method. The circuit

is identical to that of Figure 1b, except
that the op amp need not provide the instantaneous switch current. Instead of
the drastic change in output-current po-
larity at the triangle peaks, the op amps

output current slowly crosses zero at
midsupply. In the improved waveform,
the total supply current at 280-Hz operating frequency is 6.2 A.
High-current driver
serves home-power-line modems
Ryan Metivier, Analog Devices, Wilmington, MA
ome-based power-line
networking signals are
RG
RF
0.1 F
0.1 F
similar to xDSL (digital205
412
subscriber-line) signals in that

49.9
they both typically employ a
form of OFDM (orthogonal
frequency-division multiplexing). Both applications require high output current,
5
6
8
7
wide bandwidth, and good
VS
IN2
OUT2
VMID
linearity. This Design Idea de_
scribes a simple line-driver
circuit, designed with an
xDSL driver, to drive high+
POWER
33
speed data over a home powLINE
FROM
DAC/MODEM
AD8391
er line. Figure 1 shows the
AD8391 current-feedback
+
amplifier connected in a negative-feedback circuit to drive
_
wideband, discrete multitonebased signals through
Figure 1
VS
OUT1
PWDN
INI
home power lines.
3
4
1
The advantage of current
2
feedback is that it allows you
the flexibility of increasing the
0.1 F
10 F
gain beyond unity without beRF
RG
ing limited by the gain-band205
412
width product. The AD8391

0.1 F
0.1 F
has 60-MHz bandwidth,
49.9
600V/sec slew rate and 250mA output-drive-current ca5V
PD
pability, making it ideal for
driving home power lines.
An xDSL driver uses current-feedback technology to make an efficient home-power-line driver.
The circuit in Figure 1 op1
erates with a 5V supply, has a voltage gain with a peak-to-average ratio of 4V/V. The
.
fCL =
of 2(RF/RG), and drives a 33 load. feedback resistor, RF, and the gain resis R IN R IN
2C PR F 1 +
+
The 33 load emulates the worst-case tor, RG, maximize circuit bandwidth and
RF
R G
impedance of a home power-line net- stability. For this circuit, an acceptable

CP, the internal capacitance, sets the
work, which can vary greatly from home bandwidth is approximately 30 MHz.
to home. The driver is transformer-cou- The following equation shows the rela- corner frequency of the open-loop tranpled to the power line. The amplitude of tionship between closed-loop bandwidth simpedance function, and RIN is the inthe output signal is 2.8V p-p into the dif- (fCL), RG, and RF for current-feedback am- put impedance of the inverting terminal
of each amplifier. (Figure 1 does not
ferential power line (hot and neutral) plifiers.
www.edn.com
design
ideas
AMPLITUDE
(10 dB/DIV)
START 3 MHZ
Figure 2
1.9 MHZ
STOP 22 MHZ
Figure 3
FREQUENCY
The output spectrum of the power-line driver in Figure 1 shows that the
worst-case empty-tone distortion is 35 dBc.
show CP and RIN.) It is important to note

that RF dominates the expression, thus
controlling the closed-loop bandwidth.
The 49.9 resistors on the inputs of the
circuit terminate the signal source. You
should adjust these values based on each
application. The four 0.1-F capacitors
1V
100 nSEC
This plot represents the time-domain characteristic of the

power-line driver.
provide ac coupling on the input and

output lines. The test signal is a composite waveform constructed from the sum
of 75 sinusoids of pseudorandom phase.
Each tone in the test waveform may have
one of four phases to emulate QPSK
(quadrature phase-shift keying). The si-
nusoids are orthogonally spaced from 4

to 21 MHz, leaving the amateur-radio
bands empty. Figure 2 shows that the
worst-case empty-tone distortion is 35
dBc. This figure is adequate for most
practical power-line applications. Figure
3 shows the output in the time domain.
Circuit forms fast, portable light pulser

SK Kaul and IK Kaul, Bhabha Atomic Research Centre, Trombay, Mumbai, India
he absence of a
5V
5V
fast one-shot mul56k
22k
tivibrator in the
entire TTL family, as
0.1 F
well as the
Figure 1
low-voltage
swing and unwieldy
IC2
8
7
6
supply requirements
4
2
HLMP-CB-15
of ECL, drove us to exIC1
7555
ploit the fast transition
G2
G3
G1
1
3
times and low propa5
gation delays of F-seG4
ries gates. The applica0.1 F
74F00
tion called for the
implementation of a
compact, portable, fast This circuit provides fast light pulses in a blue LED.
light pulser for field
testing fast photomultipliers in gamma- less than 10 nsec, corresponding to three brightness of the LED, which is soldered
ray astronomy work. The use of only two gate delays. These pulses are ideally suit- to the edge of a small pc-board strip.
ICs helped to minimize the size and ed to pull low the cathode of a fast, blue Rechargeable batteries are clamped onto
power consumption (Figure 1). The HLMP-CB-15-type LED with the anode the other side of the pc board. Using a
normally high pulses at the output gate, clamped at 5V. The gate forces almost CMOS version of the timer, IC1, the cirG4, in IC2 have rise and fall times of ap- the entire 5V supply voltage across the cuit has a current drain of less than 4
proximately 2.5 nsec and a duration of LED. This high swing ensures optimum mA.
www.edn.com
design
ideas
3V supply delivers 12V p-p to piezo speaker

Royce Higashi and Tony Doy, Maxim Integrated Products, Sunnyvale, CA
ow-profile piezoelectric speakers can provide quality sound for
portable electronic devices, but they
require voltage swings greater than 8V p1 F 10k
p across the speaker element. Yet, most
AUDIO
portable devices include only a low-voltINPUT
age power source, and conventional amplifiers operating from batteries cannot
provide enough voltage swing to drive a
piezoelectric speaker. One approach to
this problem is to use IC1 in Figure 1,
which you can configure to drive a piezoelectric speaker with as much as
Figure 1
12V p-p and operate from a single
3V supply. IC1, a MAX4410, combines a This bridge-tied-load
stereo-headphone driver with an invert- configuration multiplies
ing charge pump that derives a negative the amplifiers voltage-
swing capability.
10k
OPTIONAL
RL NETWORK
INR _
13
10
OUTR
11
10k
100 H
INL
10
10k
_
OUTL
8
IC1
MAX4410
100
3V supply from the positive 3V supply. speaker appears to the amplifier as a caThus, providing the drive amplifiers with pacitor, the speakers impedance decreasan internal 3V supply allows each out- es as frequency increases, resulting in a
put of IC1 to swing 6V p-p. Configuring larger current draw from the amplifier.
1
IC1 as a BTL (bridge-tied load) driver IC1 remains stable with the speaker, but a
THD+N (%)
again doubles the maximum swing at the speaker with different characteristics
0.1
load to 12V p-p. In the BTL configura- might cause instability (Figure 4),. In that
f=10 kHz
tion, IC1s right channel serves as the case, you can isolate the speakers capaci0.01
master amplifier. It sets the gain of the tance from the amplifier by adding a simf=1 kHz
device, drives one side of the speaker, and ple inductor/resistor network in series
0.001
provides a signal to the left channel. If with the speaker (within the dotted lines
f=100 kHz
you configure IC1 as a unity-gain follow- on Figure 1). The network maintains sta0.0001
er, the left channel inverts the output of bility by maintaining a minimum high0
2
4
6
8
10
12
14
the right channel and drives the other leg frequency load of approximately 10 at
OUTPUT VOLTAGE
(V )
of the speaker. To ensure low distortion the ICs output.
and good matching,
Testing the circuit yields this
Figure 2
N versus output voltage
you should set the
THD
left-channel gain usfor the Figure 1 circuit.
ing precision resis1
tors.
VOUT=2VCC
We tested the circuit with a Panasonic
0.1
( w w w. p a n a s o n i c .
2V/DIV
OUTR
com) WM-R57A piTHD+N (%)
ezoelectric speaker,
yielding the THD
0.01
N (total-harmonicdistortion-plus noise)
curves (figures 2 and
3). Note that
0.001
20 SEC/DIV
10
100
1000
10000 100000
Figure 4
THDN inFREQUENCY (Hz)
Step response at the OUTR output of IC1 in Figure 1, which drives
creases as frequency
Figure 3
a WM-R57A piezoelectric speaker, shows that IC1 remains stable
Testing the circuit yields this
increases in both
N versus frequency for the Figure 1 circuit.
with the speaker.
THD
graphs. Because the
10
PP
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design
ideas
Code provides adjustable differential drive for robots

Alton Harkcom, EGO North America, Newnan, GA
ntelligently modify@ DRIVE
ing the motor-drive
DRIVE@ RATIO
commands to a robot
VECTOR
CALCULATION
can give you control finesse
* CALIBRATE
during competitions. Moving a joystick hard right, for
example, might have differDRIVE VECTOR
ent effects, depending on
*ENGAGE
the robots speed and di~ LEFT SPEED
rection. Software running
MOTOR#
LEFT
DIRECTION (2)
COMBINED
on an inexpensive microCOMBINED VECTOR
RATIO
VECTOR
controller (in this case, an
~ RIGHT SPEED
CALCULATION
CALCULATION
NEC (www.nec.com) PD7
# RIGHT DIRECTION (2)
8F9814) manages this control by calculating
Figure 1
separate drive and
ADJUST VECTOR
adjust vectors and then
combining the vectors and
NOTES: *=INTERRUPT.
calculating the appropriate
@=ADC INPUT.
ADJUSTMENT#=DIGITAL INPUT OR OUTPUT.
power ratio for two tread
@ADJUST
VECTOR
~=PWM OUTPUT.
&=COMMUNICATION DATA.
motors (Figure 1). This
CALCULATION
$=DATA-TABLE VALUES.
demonstration system uses
(0 TO 9)=NUMBER OF CONNECTIONS.
a simple treaded toy vehicle
to show how the ratio-drive An NEC microcontroller calculates the appropriate power ratios for two tread motors in a robot.
concept works and requires
no sensors in the vehicle. The microcon- the combined drive speed for the motors. culates the Left and Right motor vectors,
troller controls the tread motors with sim- Ratio variables (RatioRaw, RatioHI, Ra- another routine uses these vectors to
ple forward/reverse signals based on the tioMID, RatioLO, and Ratio) specify the drive the motors. If Right is greater than
calculated motor speeds and directions.
ratio of right-to-left motor balance. Ad- 1, for example, the drive routine enables
Listing 1, which you can download just variables (AdjustRaw, AdjustHI, Ad- a RightForward PWM signal and disables
from the Web version of this Design Idea justLO, and Adjust) specify the adjust- the reverse signal. For experimentation
at www.edn.com, shows the main routine ment value to the ratio value. The purposes, you can use a 1A quad half-H
for this application. It begins by initial- adjustment reduces the ratio value to bridge to route the speed and direction
izing all the signals and then calibrating better control left/right balance at par- signals to the motors. In actual competithem with the joystick at the idle position ticular speeds. Range-conversion vari- tions, you need a heavier duty motor con(MID) and each extreme (LO and HI). ables (RangedUpper, RangedLower, and troller because the motor-stall currents
The code uses several sets of variables. Ranged) rerange the ADC inputs to the can exceed 1A.
Drive variables (DriveRaw, DriveHI, desired 0 to 100% values for the motor
DriveMID, DriveLO, and Drive) specify speed and direction. After the code cal-
Microcontroller produces analog output

Abel Raynus, Armatron International, Melrose, MA
brushless dc motor needs several
voltage levels to control its speed: 0V
to stop the motor, 5V to run it at maximum speed, and some voltages between
these extremes to run it slower. When you
use such a motor in a system under microcontroller supervision, the microcontroller should generate all these voltages.
But a microcontroller is a digital device,

and it usually has no analog output. Several methods are available to overcome
this deficiency. For example, you could use
a DAC, a digitally programmable potentiometer, or some analog switches connected to resistor dividers. However, when
you need only a few intermediate voltage
levels, it would be more attractive to find

a method that uses microcontroller software. This Design Idea exploits the fact
that you can program a microcontrollers
I/O pins as either input or output. When
you program a pin as output, you set its
voltage level to high (5V) or low (0V).
When you program a pin as input, it has
www.edn.com
design
ideas
5V
VOUT (V)
0
1.25
2.5
R5
20k
3.33
MC68HRC908JK1
5
OSC
OUT 1
PB3
C1
10 pF
OUT 2
R1
300k
OUT 3
R2
100k
OUT 4
R3
49.9k
PB4
PB5
MODE
VO
PB6
IRQ
R4
100k
Figure 1
A microcontroller can generate analog outputs for motor-control purposes.
no effect on output voltage. Figure 1

shows a circuit example.
The circuit needs no external components, except for a few resistors. You can
set the output-voltage levels during the
main program execution or by an external interrupt. For testing purposes, using
an external interrupt is preferable (see
Listing 1 at www.edn.com). A pushbutton-mode switch triggers the external interrupt, the service routine of which consequently sets all the predetermined
voltages. This design uses 0, 1.25, 2.5,
3.33, and 5V levels. Resistors R1 to R4 determine the intermediate levels. The circuit uses the inexpensive, 8-bit MC68HRC908JK1 flash microcontroller
from Motorola (www.motorola.com),
but this method applies to almost any
kind of microcontroller. You can download the microcontroller software from
www.ednmag.com.
Single transistor provides short-circuit protection

n certain dc/dc4 TO 18V
12V
converter applicaVOUT
VIN
1 F
tions, on-chip, cycleX5R
CATCH
L1
25V CERAMIC DIODE
by-cycle current limit
CDRH5D28-150
may be insufficient proCCOUP
tection to prevent a failUPS140
ure during a short cirL2
cuit. A nonsynchronous
CFF
CDRH5D28-150
90.9k
boost converter pro47 pF
V
VIN
SW
vides a direct path from
the input to the short
FB
circuit through the inCOUT
FMMT3904
LT1961EMS8E
ductor and the catch
10 F
CIN
SHDN
diode. Regardless of
X5R
2.2 F
16V CERAMIC
current-limit protec6.8
nF
X5R
RSENSE
VC
10k
SYNC
tion in the IC, when a
25V CERAMIC
0.80
GND GND
short circuit exists in
100
6.8k
pF
the load, extremely
high currents that flow
through the load path
can damage the
Figure 1
catch diode, the inductor, and the IC. In a This 4 to 18V-input, 12V-output SEPIC has short-circuit protection.
SEPIC (single-ended,
primary-inductance-converter) circuit, load, no direct path exists for current to than the application-specific duty cycle,
the coupling capacitor breaks this path. flow from input to output. However, if the inductor and, thus, the switch curThus, when a short circuit exists in the the required minimum on-time is less rent can rapidly increase, causing IC fail-
www.edn.com
design
ideas
ure, input-supply overload, or both.

Even in certain buck-regulator applications, duty-cycle limitations sometimes
keep the switch on too long to maintain
control during an output short-circuit
condition, especially at very high input
900
800
700
600
SHORTCIRCUIT 500
CURRENT
(mA) 400
INPUT
OUTPUT
300
200
100
0
4
Figure 2
10
12
14
16
VIN (V)
The short-circuit input and output current

for the circuit of Figure 1 differ at different
voltages.
voltage with extremely high-frequency

1200
ICs. A single-transistor approach pro1000
tects the SEPIC circuit from short-circuit fault conditions by pulling down
800
the VC pin (the output of the error amCURRENT
(mA) 600
plifier) when the inductor current starts
to run away during an overload or short
400
circuit in the load (Figure 1).
Pulling the VC pin low forces the IC to
MAXIMUM LOAD CURRENT
200
IL1 PEAK CURRENT
stop switching, skipping minimum onIL2 PEAK CURRENT
time switch cycles, and allowing the cur0
0 2 4 6 8 10 12 14 16 18 20
rent in each inductor to ramp down.
INPUT VOLTAGE (V)
During a short circuit, the peak curF
i
g
u
r
e
3
rent in L1, which decreases because
of the limited number of switch cycles,
These curves show the maximum load current
and the peak current in L2 sum up to
under normal load conditions.
equal the peak current in the switch,
which is less than the 1.5A limit of the is equal to the load current and is a maxLT1961EMS8E. Figure 2 shows the imum of 600 mA under all load condishort-circuit input and output currents tions. If the sense resistor sees 800 mA, it
at different input voltages. Figure 3 knows that an overload condition has ocshows the maximum load current versus curred and tells the transistor to protect
input voltage. The average current in L2 the circuit.
www.edn.com
design
ideas
Scheme adds sequencing and

shutdown control to regulator
Said Jackson, Equator Technologies Inc, Campbell, CA
odern microprocessor- or FPGA-based circuits require separate
and independent power-supply
voltages for the core and the I/O circuits.
Some devices require stringent control of
the turn-on characteristics and sequencing of these multiple power supplies to
avoid internal parasitic current flows and
consequent latch-ups. Although regulators exist with specific soft-start and
shutdown inputs, it may be more cost-effective to use regulators that do not inherently provide these features and to
add these features with external discrete
devices. This Design Idea shows how to
use an inexpensive Linear Technology
(www.linear.com) LTC3701 dual switching regulator to provide a sequenced, and
Scheme adds sequencing and

shutdown control to regulator ....................89
standby-controlled, power supply for an

Equator Technologies (www.equator.
com) broadband-signal processor. You
can also adjust the circuit for FPGA or
generic microprocessor applications. The
features of the circuit in Figure 1 increase
the regulators stability beyond what you
can achieve with the standard Linear
Technology application-note circuit.
The LTC3701 switching regulator, IC1,
provides two independently adjustable
output voltages with very high voltage accuracy at a cost compatible with consumer-type applications. Because of cost
constraints, it does not provide the softstart or shutdown features present in other switching regulators. This design adds
three discrete transistors to the conven-
MathCAD functions perform

log interpolation ............................................90
Scheme improves on
ow-cost keyboard ..........................................94
ADC interface conditions
high-level signals............................................96
Two op amps provide
averaged absolute value..............................98
tional regulator circuitry to provide both

arbitrary power-on-sequencing control
and a simultaneous-shutdown feature.
Q3, Q4, and Q5 are inexpensive discrete
R1
R1
R1
R1
R1
KELVIN SENSING
Figure 1
C1
580 pF
0603
5V
VIN
VCORE
VIN
5V
R3
10k
8 7 65
C5
580 pF
R5
0603
10k
PACK4 3
C6
0603
47 pF
SENSE 1 SENSE 1+
VIN
ITH/RUN
VFB1
IC1 PGATE1
SGND LTC3701EGN
PLLLPF
PGND
PGOOD
PGATE2
VFB2
ITH/RUN2 EXTCLK/MODE
SENSE 2 SENSE 2+
SLEEP
Q3
2 BSN20
C7
580 pF
0603
R2
0.015
16
15
14
C4
22 F 10V
1210
13
12
10
9
C8
580 pF
0603
R7
0.015
C9
22 F
10V
1210
R9
33k
1
3
Q1
FAIRCHILD 2
FDC638P
Q5
BSN20
1%
R1
37.4k
0805
C3
220 F
6.3V
D1
ONMBRS
320T3
Q2
FAIRCHILD
FDC638P
R4
75k
0805
0.1%
3.3V
KELVIN SENSING
2.2 H
2.3A IRMS
COILCRAFT
DO1608C-222
2
6
5
1
Q4
2N3904- 1
SMD
VCORE
COILCRAFT
5 DO3316P-332
L1
6
3.3 H
2
5.4A IRMS
1
+
L2
4
3
37.4k = 1.20V VCORE.

47.5k = 1.30V VCORE.
66k = 1.50V VCORE.
93.1k = 1.80V VCORE.
160k = 2.50V VCORE.
5V
VIN
R6
10k
1 2 34
SLEEP
C2
47 pF
0603
1
2
3
4
7
11
5
6
8
=
=
=
=
=
D2
ONMBRS130T3
+
C10
220 F
6.3V
1%
R8
232k
0805
0.1%
R10
75k
0805
Adding a few transistors to a switching regulator adds power-sequencing and shutdown control to a power supply.
www.edn.com
design
ideas
IS STOPPED
devices that control the voltage ACQUISITION
voltage above approxi100k SAMPLES/SEC
on the regulators ITH/Run pins.
mately 1V. You may need
The ITH/Run pins of IC1 proto adjust the value of R9 if
vide an external compensation
your design requires core
to the internal feedback loops;
voltages below approxithey can also serve to shut
mately 1V.You can replace
down the device when you pull
Q3 and Q5 by potentially
cheaper industry-stanthem to ground. A microdard 2N2007 devices at
processors TTL/CMOS-comthe expense of slightly
patible input signal (Sleep)
higher capacitive loading
controls the power state of the
on the ITH/Run pins of
circuit. You can put the circuit
IC1. C2 and C6 are cominto shutdown mode by either
pensation capacitors that
letting the Sleep pin float high
the Linear Technology litor pulling it higher than ap1 500 mV/DIV
1.49V
Y
X
3 1V/DIV
75 mV
1 (1)=800 mV
349.96 SEC
erature does not mention
proximately 1.5V. Q3 then con2 (3)=5.880V
3.88004 mSEC
nects the ITH/Run1 pin to
but that are highly effec=6.680V
4.23000 mSEC
Figure 2
1/X= 236.406 Hz
ground, which causes the
tive in preventing subharVCORE core-voltage supply to The 3.3V supply turns on several milliseconds after VCORE attains an estabmonic oscillation arising
shut off. The VCORE voltage then lished level.
from dynamic current
drops toward ground, and Q4
loading on the outputs.
stops conducting when VCORE falls below proximately 0.8V. This action turns off Q5 (See the Linear Technology Web site for
approximately 0.8V. The gate of Q5 pulls and allows the ITH/Run2 pin voltage to information on subharmonic oscillato the 5V unregulated input voltage, and start rising. The 3.3V power supply thus tion.)
Q5 shorts the ITH/Run2 pin to ground, turns on. The combined effect of driving
The gate-drain-source capacitance of
which turns off the 3.3V regulator. The Q4 and Q5 from the VCORE voltage is that Q3 and Q5 also add to the stability of the
circuit is now in standby mode, and both the 3.3V I/O voltage always turns on only loop filter. Note that sequencing the turnafter the VCORE voltage attains an estab- on ramps of the power supplies also has
power supplies are off.
Pulling the Sleep pin lower than ap- lished level. The end result is to sequence the benefit of reducing the inrush current
proximately 0.8V turns on the power the power supplies over a period of 4 into the power supply by staggering this
current and preventing simultaneous
supply and sequences the voltages in the msec (Figure 2).
The circuit is symmetric, and changing current loading of the primary bypass cafollowing manner: Q3 stops conducting,
and the voltage on the ITH/Run1 pin can the base drive of Q4 and interchanging pacitors by both power supplies. The serise, thanks to internal current sources in the drain signals of Q3 and Q5 reverses the lected component values allow for more
IC1. The VCORE voltage regulator then sequencing order of the power supplies than 2A of current on the 3.3V line and
starts to operate, and VCORE rises to its set for chips that require the I/O voltage to more than 3.5A of current on the VCORE
voltage, 1.2V by default. Q4 starts con- rise before the core voltage. You can ad- line.
ducting as soon as VCORE rises above ap- just the value of R1 to generate any core
MathCAD functions perform log interpolation

James Bach, Delphi Delco Electronics Systems, Kokomo, IN
athCAD provides a number of
interpolation and curve-fitting
functions, so that, given a set of XY data points, you can estimate the Y value for any given X coordinate. Unfortunately, these functions work poorly with
data that is to be displayed in a nonlinear
(logarithmic) manner. Examples of these
functions are:
Log-Lin: phase/magnitude-versusfrequency (Bode plots);
Log-Log: impedance-versus-frequency (reactance plots); and
Lin-Log: impedance-versus-tem-
Figure 1
At X coordinates between data points, MathCADs linterp function creates a

bulging effect.
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design
ideas
perature (thermistor data).

Using the built-in linterp function,
MathCAD estimates and plots the data
(Figure 1). As you can see, at X coordinates between the original data points,
the linterp function creates a bulging
effect. The following trio of simple interpolation functions allows the correct
interpolation of nonlinear data on its appropriate scale. These routines function
by prewarping the incoming-data matrices before feeding them into the existing linterp function; for logarithmic Y-axis functions, you raise 10 to
the result of the linterp function to restore the values to the proper decade:
Figure 2
Using the LogLogInterp function, the bulges in Figure 1 disappear.
Using the newly created LogLogInterp

function, the straight-line data is displayed
(Figure 2).
Scheme improves on low-cost keyboard

Martin OHara, Telematica Systems Ltd, Cranfield, Bedfordshire, UK
ou can easily imRC
prove on a previous
MICROCONTROLLER
100
Design Idea to proS1
S2
S3
S4
S5
SX
duce a slightly simpler reC1
R
R
R
R
R
2
3
4
5
X
sistor arrangement with
47 nF
better timing balance be1k
1k
1k
1k
1k
R1
tween switches, using a
1k
Figure 1
single resistor value
(Reference 1, Figure 1).
The use of a single resistor
value, RS, in a series chain This simple keypad arrangement uses a single resistor value to select the switches.
for the switch resistors
gives the timing parameters a simpler rials cost. The timing balance between an SMD assembly with just two compoformat and should reduce bill-of-mate- switches should now also be more even. nent types: switch and resistor. In the
The improved balance eases original idea, in cases of multiple keys
extending the keyboard for being pressed, the timing is some odd
adding key inputs. The addi- multiple of parallel resistors and could
tional benefit of this arrange- accidentally represent a key that was not
ment is to make the circuit eas- selected. With the arrangement of Figier to adapt for faster or slower ure 1, the lowest order key dominates;
microprocessors, because you hence, the keypad has hard-wired prican easily adapt the circuit by ority setting and always results in a sechanging the single switch re- lected key timing, and no intermediate
sistor or capacitor values to al- timing period should occur.
ter the charge-discharge characteristics (Figure 2). It can Reference
1. Thevenin, Jean-Jacques,Novel idea
also make building the circuit
into a keypad housing easier, implements low-cost keyboard, EDN,
A 400-kHz square wave from the
Figure 2
especially if you use mem- April 3, 2003, pg 69.
microprocessor shows no key, key 1,
brane keys. The entire circuit is
and key 5 pressed.
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design
ideas
ADC interface conditions high-level signals

Moshe Gerstenhaber and Stephen Lee, Analog Devices, Wilmington, MA
esigners who build
5V
equipment for the
industrial market
VS
7
share a widespread probR3
AD628
10k
lem. At one extreme,
R4
they must build equip100k
IN
_
VB
V1
8
ment that supports
10k
R2
A1
+
10V bipolar voltages,
100k
OUT
+IN
+
A2
5V
1
5
often riding on a high
_
R1
AD628
common-mode level, a
10k
requirement enforced by
3
2
4 6
RG
VREF
VS CFILT
3.32k
30 years of legacy industrial equipment. At the
VR
C
AD7540
13.3k 3.32k
other extreme, the anaC
FILT
RG
VS
VREF
log signal needs condi5V
3
2
4 6
REFERENCE
tioning to match the fullR
R2
1
AD628
_
2.5V
scale range of a lowAD780
100k 10k
+IN
A2
+
5
VR
1
voltage, single-supply
10k
OUT
R4
A1
+
ADC. Designers need to
100k
-IN
_
VA
8
PRECISION
scale and level-shift sigV2
REFERENCE
nal levels throughout
R3
AD628
their system to
10k
F
i
g
u
r
e
1
7
accommodate
VS
the high voltage levels
5V
that sensor manufacturers dictate and the low This circuit attenuates and level-shifts a 10V differential signal while operating from a single 5V supply.
voltage levels that the
2 shows a 10V input signal
ADC dictates. Operating from a
50k SAMPLES/SEC HI RES
(top), the signals at the outsingle 5V supply, the circuit in
put of each AD628 (midthis Design Idea provides an indle), and the differential
terface of large bipolar inputs to
output (bottom). The bena single-supply, low-voltage, difefits of this configuration go
ferential-input ADC. The circuit
beyond simply interfacing
in Figure 1 comprises two difwith the ADC. The circuit
ference amplifiers, connected in
improves specifications such
antiphase. The differential outas common-mode-rejection
put, V1V2, is an attenuated version of the input signal:
ratio, offset voltage, drift,
V1V2(VAVB)/5.
and noise by a factor of 2
The difference amplibecause the errors of each
Figure 2
fiers reject the commonAD628 are not correlated.
mode voltage on inputs VA and
The output demonstrates
VB. The reference voltage, VR,
85-dB SNR (Figure 3). The
which the AD780 develops and
two AD628s interface with
10.0V
CH3
2.00V
M1 mSEC
CH1
2.4V
the ADC and the amplifier
an AD7450 12-bit, differen2V
2V
1.00 mSEC
share, sets the output commontial-input ADC. The ADmode voltage. A single capaci- The waveforms show a 10V input signal (top), the signals at the output
7450 easily rejects residual
tor, C, placed arcros the CFILT of each AD628 (middle), and the differential output (bottom).
common-mode signals at
pins, lowpass-filters the differthe output of the difference
ence signal, V1V2. The 3-dB pole fre- plifies the difference signal by 1.5. Thus, amplifiers. Figure 4 shows the commonquency is: fP1/(40,000C). A2 am- the total gain of this circuit is 3/10. Figure mode error at the output of the AD628.
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design
ideas
The topmost waveform is a 10V, common-mode input signal. The middle

waveform, measuring 150 V, is the
common-mode error measured, differentially, from the output of the two

AD628s. The bottom waveform, meas-
uring 80 V, is the resultant commonmode error.
INPUT
20V p-p
COMMON-MODE
ERROR OF
DIFFERENTIAL
OUTPUT
Figure 3
Figure 4
The circuit in Figure 1 has an 85-dBV SNR.
COMMON-MODE
ERROR OF
COMMON-MODE
OUTPUT
The common mode input (top) measures 20V p-p. The common-mode
error of the differential output (middle) is 200 V p-p. The error of the
common-mode output (bottom) is 80 V p-p.
Two op amps provide averaged absolute value

he circuit in Figure 1 is useful
C2
C1
when you need amplitude demodu470 nF
47 nF
lation or an averaged absolute-valVA
ue conversion. The circuit comprises two
R2
R3
R4
22k
220k
220k
stages, the first of which, IC1A, is a differential-output absolute-value convertR1
er. The second stage, IC1B, is a tradition20k
_
_
al
differential
amplifier.
The
VIN
IC1A
IC1B
D
1
VOUT
combination of the two stages performs
TL082
TL082
BAV99
+
+
single-ended absolute-value conversion
but only if R3R2. The C1 capacitors
integrate the current flow and yield avR2
R3
R4
22k
220k
220k
eraged voltages VA and VB. In addition,
the capacitors ensure low ac-impedance
points at nodes VA and VB when the outVB
put diodes are reverse-biased.
C2
C1
F
i
g
u
r
e
1
The additional C2 capacitors in
470 nF
47 nF
parallel with R4 resistors impart a second-order-lowpass-filter characteristic This single-ended, averaged absolute-value converter is useful for amplitude demodulation.
to the circuit and remove the remaining
ac signal. From a practical point of view, stants 1R2||R3C1 and 2R4C2 to be tages are that the circuit has equal delay
you can choose R3 to be five to 10 times equal. The circuit in Figure 1 is simple, for positive- and negative-going signals
higher than R2. The gain of the circuit is symmetrical, and cost-effective. It also and that it doesnt need matched
(R2||R3/R1)(R4/R3). In most applications, makes it easy to calculate and adjust the diodes.
you would choose the filter time con- gain using one resistor, R1. Other advan-
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design
ideas
Input filter prevents

instrumentation-amp RF-rectification errors
Charles Kitchin, Lew Counts, and Moshe Gerstenhaber, Analog Devices, Wilmington, MA
nstrumentation amplifiers serve
VS
in a variety of applications that need
0.01 F
0.33 F
RFI
FILTER
to extract a weak differential signal
from large common-mode noise or inC1A
terference. However, designers often
R1A 1000 pF
overlook the potential problem of RF
4.02k
G=1+ 49.4k
1
RG
rectification inside the instrumentation
8
+IN
+
amplifier. The amplifiers commonC2
mode rejection normally greatly reduces
2
7
AD8221
0.01 F
VOUT
RG
common-mode signals at an instrumen3
R1B
tation amplifiers input. Unfortunately,
4.02k
6 REFERENCE
_
5
IN
RF rectification still occurs, because even
C1B
4
the best instrumentation amplifiers have
1000 pF
virtually no common-mode rejection at
0.01 F
0.33 F
frequencies higher than 20 kHz. The amplifiers input stage may rectify a strong
RF signal and then appear as a dcVS
Figure 1
offset error. Once the input stage
rectifies the signal, no amount of low- This lowpass-filter circuit prevents RF-rectification errors in instrumentation amplifiers.
pass-filtering at the instrumentation
amplifiers output can remove the error. filter needs to remove as much RF ener- mismatch between the time constants of
Finally, if the RF interference is intermit- gy as possible from the input lines, pre- C1A/R1A and C1B/R1B unbalance the bridge
tent, measurement errors may go unde- serve the ac signals balance between and reduce high-frequency commontected. The best practical solution to this each line and ground (common), and mode rejection. Therefore, resistors R1A
problem is to provide RF attenuation maintain a high enough input impedance and R1B and capacitors C1A and C1B
ahead of the instrumentation amplifier over the measurement bandwidth to should always be equal. C2 connects
by using a differential lowpass filter. The avoid loading the signal source. Figure 1 across the bridge output so that C2 is efprovides a basic building block for a wide fectively in parallel with the series combination of C1A and C1B. Thus connectrange of differential RFI filters.
Input filter prevents instrumentation-amp
The component values are typical of ed, C2 effectively reduces any ac comRF-rectification errors ..................................101
those for the latest generation of instru- mon-mode-rejection errors from misWhite-LED driver backlights
mentation amplifiers, such as the AD- matching. For example, making C2 10
LCD and keypad ..........................................102
8221, which has a typical 3-dB band- times larger than C1 provides a 20-times
width of 1 MHz and a typical voltage reduction in common-mode-rejection
Microcontroller or DSP circuit
noise level of 7 nV/Hz. In addition to errors arising from C1A/C1B mismatch.
controls on/off function..............................104
RFI suppression, the filter also provides Note that the filter does not affect dc
Simple power supply fits
additional input-overload protection; re- common-mode rejection.
into small spaces ........................................108
The RFI filter has differential and comsistors R1A and R1B help isolate the inAmplifier and current source emulate
strumentation amplifiers input circuitry mon-mode bandwidths. The differential
instrumentation amplifier ..........................110
from the external signal source. Figure 2 bandwidth defines the frequency reHardware histogram speeds
shows a simplified version of the RFI cir- sponse of the filter with a differential inADC test..........................................................112
cuit. It reveals that the filter forms a put signal applied between the circuits
bridge circuit whose output appears two inputs, IN and IN. The sum of
across the instrumentation amplifiers in- the two equal-value input resistors, R1A
put pins. Because of this connection, any and R1B, and the differential capacitance,
www.edn.com
November 13, 2003 | edn 101
design
ideas
INSTRUMENTATION
which is C2 in parallel with the series
R1A
C1A
AMPLIFIER
combination of C1A and C1B, establish this
+IN
RC time constant. The 3-dB differenC2
VO
tial bandwidth of this filter is equal to IN
R1B
C1B
BWDIFF[1/(2R(2C2C1))]. The common-mode bandwidth defines
Figure 2
what a common-mode RF signal sees between the two inputs tied to- Capacitor C2 shunts C1A/C1B and reduces ac comgether and ground. C2 does not affect the mon-mode-rejection errors arising from combandwidth of the common-mode RF sig- ponent mismatch.
nal, because this capacitor connects between the two inputs, helping to keep amplifier, such as the AD627, with its
them at the same RF-signal level. There- low-input-stage operating current, is a
fore, the parallel impedance of the two RC good example. The simple expedient of
networks (R1A/C1A and R1B/C1B) to ground increasing the value of the two input resets common-mode bandwidth. The 3- sistors, R1A/R1B, that of capacitor C2, or
dB common-mode bandwidth is equal to both can provide further RF attenuation
at the expense of reduced signal bandBWCM1/(2R1C1).
Using the circuit of Figure 1, with a C2 width. Some steps for selecting RFI-filvalue of 0.01 F, the 3-dB differential- ter component values follow:
signal bandwidth is approximately 1900
1. Decide on the value of the two seHz. When operating at a gain of 5, the cir- ries resistors and ensure that the previous
cuit has measured dc-offset shift over a circuitry can adequately drive this imfrequency range of 10 Hz to 20 MHz of pedance. With typical values of 2 to 10
less than 6 V referred to the input. At k, these resistors should not contribute
unity gain, there is no measurable dc-off- more noise than that of the instrumenset shift. Some instrumentation ampli- tation amplifier itself. Using a pair of 2fiers are more prone to RF rectification k resistors adds Johnson noise of 8
than others and may need a more robust nV/Hz. This figure increases to 11
filter. A micropower instrumentation nV/Hz with 4-k resistors and 18
nV/Hz with 10-k resistors.

2. Select an appropriate value for capacitor C2, which sets the filters differential (signal) bandwidth. Set this value
as low as possible without attenuating the
input signal. A differential bandwidth of
10 times the highest signal frequency is
usually adequate.
3. Select values for capacitors C1A and
C1B, which set the common-mode bandwidth. For decent ac common-mode rejection, these capacitors should have values 10% or lower of the value of C2. The
common-mode bandwidth should always
be less than 10% of the instrumentation
amplifiers bandwidth at unity gain.
You should build the RFI filter using a
pc board with a ground plane on both
sides. All component leads should be as
short as possible. Resistors R1 and R2 can
be common 1% metal-film units. However, all three capacitors need to be reasonably high-Q, low-loss components.
Capacitors C1A and C1B need to be 5%tolerance devices to avoid degrading the
circuits common-mode rejection. Good
choices are the traditional 5% silver micas, miniature micas, or the new Panasonic 2% PPS film capacitors (Digi-key
part number PS1H102G-ND).
White-LED driver backlights LCD and keypad

Fabien Franc, Catalyst Semiconductor, Sunnyvale, CA
esigners widely use white LEDs
DISPLAY
ZETEX
to backlight color LCDs and keyZHCS400
pads in handheld devices, such as
cell phones, MP3 players, GPS navigators, and PDAs. Their spectrum
Figure 1
WHITE
and brightness represent nearSUMIDA
LEDs
ideal light sources. One possible configCLQ4D106R8
uration for a phone or a phone/PDA
6.8 H
IIN
combination is to have a group of three
SW
VIN
LEDs to light the display and six LEDs for
VIN
the keypad. Figure 1 shows a method for
RS
SHDN
3.4V
75
driving all the LEDs with a single driver
+
RSET GND LED
IC from Catalyst Semiconductor (www.
C1
4.7 F
catsemi.com), the CAT32. Power comes
15 mA
CAT32
OFF
R1
from a single lithium-ion battery cell. A
1.5k
FET switch can independently turn off
the group of six LEDs. The shutdown input, SHDN, on the CAT32 turns off all
the LEDs. LED brightness is a direct
function of the current running through A single IC boosts the battery voltage to drive a total of nine LEDs.
102 edn | November 13, 2003
KEYPAD
RS
75
RS
75
15 mA
ON
N-FET
www.edn.com
design
ideas
90
the LED, and typical values are 10
expression for efficiency is as
to 20 mA for white LEDs.
follows:
85
Figure 2
The CAT32 regulates a
80
constant current through the
connected
to
LED pin. Resistor R1
EFFICIENCY (%) 75
the RSET pin adjusts the LED
70
current.
The driver is a step-up con65
verter using an inductor to boost
where VLED is the voltage across
60
the LED, ILED is the LED current,
the voltage, such as that from a
3.8
4
4.2
3
3.2
3.4
3.6
RS is the series resistor, and IIN is
lithium-ion battery, and bias
INPUT VOLTAGE (V)
the current from the input supmultiple LEDs in series. The RS
resistors in series with the LEDs This curve shows the efficiency of the circuit in Figure 1 for 15ply. The efficiency is approxibalance out the current between mA LED current and 3 to 4.2V battery voltage.
mately 84% for a 3.6V supply. If
the groups of LEDs. The LED foryou now consider only the powward voltage, typically around 3.5V, ex- keypad. You define efficiency as the ratio er the LEDs dissipate, excluding all the
periences some variation from one LED of the power dissipated in the LEDs, in- other losses, the following formula gives
to the other for a given bias current, and cluding the power in the series resistors the net efficiency (approximately 75%
the series resistors also compensate for but not including the loss in the Schottky with a 3.6V supply):
that situation. By using series resistors diode, to the total input power. Figure 2
with values of 75, a current of approx- shows the efficiency of the circuit for a
imately 15 mA flows in all LEDs. The dis- load of 15-mA current in the LEDs and
play uses Nichia (www.nichia.com) for supply voltage ranging from 3 and
NSCW335 side-view LEDs, and top-view 4.2V, corresponding to the charge-disNichia NSCW100 LEDs backlight the charge cycle of lithium-ion batteries. The
Microcontroller or DSP circuit

controls on/off function
Dirk Gehrke, Texas Instruments, Freising, Germany, and Frans Ravn, ChemoMetec A/S, Alleroed, Denmark
n many applications, a single on/off
button switches the power supply on
or off. Usually, the system switches off
regardless of the processing function or
workload the microcontroller or DSP circuit is currently handling. The small circuit in Figure 1 is intended to make the
microcontroller or DSP circuit the master over this on/off function. The circuit
allows the microcontroller or DSP circuit
to take ownership over the on/off function. Thus, the system can do whatever
has to be done, such as processing data,
storing data, and so forth, before it issues
the command to shut down the supply.
Figure 2 shows the timing diagram. The
switch connects directly to the dc supply
or battery, though the end application is
disconnected from the supply. Thus, all
the capacitors discharge. The most difficult task is to get the two D flip-flops in
Figure 1 into the desired off configuration.
The inverter, IC1B, in Figure 1 resets the
D flip-flop, IC2B, via the diode, D4. The
RC network comprising R10, R11, and C4,

connected to the input of the inverter,
IC1B, generates a delay time of approximately 4.7 msec. This interval ensures
that this D flip-flop is released from reset after a delay time of approximately 4.7
msec. When the delay time has passed, reset-input pin R of IC2B changes from high
to low potential because R7 connects to
ground. At the same time, output Q of
IC2B switches to low level, and Q switches to high level. The D input node of IC2B
changes as well from high to low potential because it connects to the output pin,
Q. The RC network comprising R1 and
C3, in conjunction with the inverter, IC1A,
generates a delay of approximately 47
msec. This delayed output connects to
the set pin of the D flip-flop, IC2A. The
set pin holds high for 47 msec before it
goes low. The RC network, comprising
R1and C3, along with the inverter, IC1A,
generate a 47-msec delay. The delayed
output connects to the set pin of the D
flip-flop, IC2A. The set pin holds high for
47 msec before it goes low.

After the set pin falls to a low level, the
D flip-flop, IC2A, changes its output levels at Q to high and Q to low, and feedback from Q connects to the D input. The
high level at Q (SHTDN), connected to
the enable pin of the dc/dc converter or
low-dropout regulator, keeps the system
off. The D flip-flop, IC2A, is now in an off
condition. From this point on, both D
flip-flops are in a known state. The DSP
I/O pin is low during this initialization,
because the DSP circuit receives no power. R15 ensures a low level during the power-up sequence at the DSP I/O pin. The
SHTDN, after its initialization phase, assumes an active-high level. If you connect
it to the enable pin of the system dc/dc
converter or low-dropout regulator, it
keeps the system in an off condition.
IC1Bs input changes its level from high to
low when you press the pushbutton, because the switch shorts the pullup resistor at the pushbutton node to ground.
IC1Bs output changes its level accordingwww.edn.com
design
ideas
VDD
VDD
IC1A
CD40106B
R1
470k
C3
100 nF
D3
1N4148
R8
1M
Q 1
S
5
D IC2A
3
>CLK
4
2
R
Q
SHTDN
VDD
IC1B
CD40106B
CD4013B
D1
1N4148
4
R14
100k
Q1
BC547
R2
10k
12
D4
1N4148
IC2B
CD4013B
R
ON/OFF
PUSHBUTTON
3.3 OR 5V
VDD
CLK
13
3.3V
R10
100k
R11
470k
C4
10 nF
10
11
R7
100k
D2
1N4148
C6
10 nF
R4
100k
Q2
BC547
R15
470k
DSP
I/O
IC1C
5
R9
100
R13
10k
R5
10k
R16
10k
Q4
BC547
D9
8
S
R3
470k
R6
10k
R12
100k
Q3
BC547
C5
100 nF
IC1D
CD40106B
8
11
IC1E
CD40106B
10
13
IC1F
CD40106B
12
Figure 1
This circuit generates a delay between the DSP circuits or microcontrollers off command and system
shutdown.
button, the DSP I/O pin assumes a low flip-flop IC2B changes, via D4, to reset
ly from low to high for that period.
The CLK input of D flip-flop IC2A trig- level. The DSP circuit or microcontroller mode, so that the toggle signal valid at
gers via R14 and D1, and output Q changes should now detect this input change and CLK has no impact on the output status.
its status from low to high. This state en- generate an interrupt. This interrupt You now release the on/off pushbutton.
ables the low-dropout regulator or dc/dc should initiate a shutdown procedure. D D flip-flop IC2B releases from reset after
converter to start operation. The 3.3 or
5V connected to R2 supplies transistor Q1
VDD
6 TO 15V
to change the logic level at the CLK input
of D flip-flop IC2A. This action ensures
t
that the system disregards glitches when
PRESSED BUTTON
you press the on/off pushbutton. The
PUSH_BUTTON
DSP I/O pin of the circuit connects to
one of the DSP circuits or microcont
trollers I/O pins. You should configure
the I/O pin of the DSP circuit or micro5V
controller as an input pin after power-up
3.3V
and reset release. As long as you press the
t
on/off pushbutton, transistor Q2 remains
I/O PIN
I/O PIN CONFIGURES
CONFIGURES
on, driving the DSP circuits I/O pin low.
AS OUTPUT PIN.
AS INPUT PIN.
I/O PIN
You should program the DSP circuit or
3.3V
microcontroller such that the DSP circuit
t
stops executing code before you release
CONTROLLER
the button, and the DSP I/O pin changes
CONTROLLER
CONTROLLER HAS TIME CONFIGURES THE I/O
ACKNOWLEDGMENT:
TO STOP ALL TASKS
PIN AS THE OUTPUT
its level from low to high. D flip-flop IC2B
USER WANTS TO
BEFORE POWERING
PIN AND DRIVES THE
again resets via D4, but this reset
POWER DOWN APPLICATION. DOWN THE SUPPLY.
PIN LOW.
Figure 2
does not alter the output because
the application is running.
This timing diagram shows that the DSP circuit or microcontroller takes ownership over the sysWhen you again press the on/off push- tems on/off function to allow time for performing crucial tasks.
www.edn.com
design
ideas
approximately 4.7 msec, and Q2 and Q4

change levels and maintain a low signal
at the CLK pin before the reset delay time
passes. The microcontroller or DSP circuit sees a high signal at the I/O pin after
this time-out and can start the shutdown
procedure.
The DSP circuit or microcontroller
now has the time to store any critical

data. You must program the microcontrollers or DSP circuits I/O pin as an
output pin set low. Q4 loses its drive voltage, and the CLK pin of D flip-flop IC2B
changes its status from low to high. D
flip-flop IC2A changes its output status via
the output, Q, and D3. Q and Q change
the status of the SHTDN pin to low level, and the system shuts down. At the
same time, D flip-flop IC2B resets via Q3
and the comparator IC1C. This reset
brings D flip-flop IC2B to the initial state
described above before you first pressed
the on/off pushbutton.
Simple power supply fits into small spaces

Raymond Zheng, Linear Technology, Milpitas, CA
he demand for negative-voltage
1
power supplies is increasing with
VIN
4.5 TO 6V
the popularity of applications for
portable devices. It can be expensive and
relatively complicated to generate a negative supply from a positive input source,
especially when the design requires both
positive and negative outputs. FigFigure 1
ure 1 shows a simple and cost-effective solution that combines a voltage
inverter and a voltage doubler in a single charge-pump circuit. It produces a
regulated 5V output and an unregulated 10V output from a 5 to 6V input.
The circuit requires only five small, ce-
1 VIN
CIN
10 F
ON
6
OFF
VOUT
LTC1983ES6-5
SHDN
GND
2
5
VOUT1
5V
COUT1 I
OUT
10 F 100
mA MAXIMUM
C 4
C
CFLY
2.2 F
CBOOST
2.2 F
D1
D2
VOUT2
2VIN
COUT2 IOUT2
10 F 50 mA
NOTES: CIN, COUT1, COUT2: TAIYO YUDEN JMK316BJ106ML.

CFLY: TAIYO YUDEN LMK212BJ225MG.
CBOOST: TAIYO YUDEN EMK316BJ225ML.
12
10
ROUT
()
This circuit combines a regulated inverter and a voltage doubler.
VIN5V
8
6
4
2
0
0
50
IOUT (mA)
Figure 2
100
This graphic shows ROUT versus IOUT for the circuit in Figure 1.
86
84
EFFICIENCY 82
(%)
80
78
10.5
Figure 3
30.2
IOUT1 OR IOUT2
(mA)
50
This curve shows efficiency versus either output current.
ramic, surface-mount capacitors and two

4.5
diodes in addition to the charge-pump
4.6
VOUT1
IC in an SOT-23 package.
4.7
(V)
From a 6V input, the inductorless
IOUT250 mA
4.8
dc/dc inverter can deliver 100 mA at a
VIN6V
4.9
regulated 5V (5%), and the voltage
5
doubler can provide 50 mA at 10.5V with
5.1
60
0
80 100
40
20
7% variation. The inverters outputvoltage regulation follows the relaIOUT1 (mA)
Figure 4
tionship (VIN5)(IOUTROUT);
you can determine the values of ROUT and This curve shows output-voltage regulation
IOUT for VIN5V from the graph in Fig- versus output current.
ure 2. (The ROUT and IOUT values for other VIN values are available in the LTC- VOUT22VIN2VD, where VD is the for1983s data sheet.) If the variables dont ward voltage drop across the diodes. Figmeet this inequality condition, the part ure 3 shows the efficiency of the circuit,
runs in open-loop mode and acts as a which exceeds 81% and peaks at approxlow-output-impedance inverter in which imately 85%. Figure 4 shows the invertthe output voltage is VOUT1 ers output-voltage regulation versus in[VIN(IOUTROUT)].You can define the verter output current. The IC includes
output voltage of the voltage doubler as short-circuit and thermal protection.
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design
ideas
Amplifier and current source emulate

instrumentation amplifier
he classic three- or
two-op-amp instrumentation-amplifier circuits are standard
G1
ways to amplify a smallIA
ZG/2
TWISTED
amplitude differential
+
A
PAIR
signal contaminated
OUT
A2
with high common
VG
mode noise. In some apIB
ZFB
plications, the signal
B
ZG/2
source is floating with
high-series-output impedance and thus
Figure 1
requires an approA1
priate high-input-im+
pedance amplifier. This A voltage-controlled current source and
Design Idea proposes an an inverting amplifier emulate an instrualternative approach us- mentation amplifier.
ing a simplified amplifier circuit (Figure 1). The basic principle bining a virtual-ground transimpedance addition, the voltage at input B is at viris to sense the current in the amplifier inamplifier (A1) with a voltage-controlled tual-ground potential.
A practical circuit is a two-electrode
put B (IB) and inject a current of the same current source (G1). Thus, G1 balances the
value in the amplifier input A (IA), by com- common- mode interference currents. In biosignal amplifier for electrocardiogram
signals (Figure 2). IC2B
is the transimpedance
25k
25k
amplifier. The feedback capacitor, CFB,
ensures circuit stabiliIC1
ty. The INA134 differINA134
25k
ence amplifier, IC1, and
the op amp, IC2A, make
300k
25k
up a high-quality, bidirectional voltage-conIN (+)
trolled current source.
+
You could use many
IC2A
TL072
similar ICs, such as
_
INA132, 133, 152, 154,
24k
105, or AMP03, for IC1.
+
2 F
IC3A
+
The
remaining part of
CFB
OUT
TL072
IC3B
_
the
circuit
comprises
TL072
24k
15 nF
_
33 pF
two conventional non39k
15 nF
10
nF
1.5M
inverting stages. The
300k
proposed circuit can be
1k
IN ()
1k
useful in many two_
wire or two-electrode
IC2B
TL072
applications, in which
+
you need to maintain
Figure 2
high amplifier inputThis biosignal amplifier has the high input impedance that medical applications require.
impedance values.
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design
ideas
Hardware histogram speeds ADC test

Tony Zizzo Jr, Texas Instruments, Tucson, AZ
ccumulating enough samples to FIFO memory is to collect data at the the memory holds a look-up table of all
effectively and accurately measure lin- speed of the DUT (device under test), be- practical bin counts. Rather than use an
earity errors in pipeline converters at cause, with all the data-swapping that oc- adder or a counter to implement the
production test and minimizing test time curs during the histogram routine, the bin-count function, which would reare difficult enough. Add to that multiple cycle is slower than the DUT. But it also quire an extra IC, this circuit implesites, multiple channels, and the expense reduces switching noise in the test circuit ments data1 by storing each look-up
of multiple custom-instrument resources by keeping the outputs and the other de- entry in the address whose value is one
during periods of low capital expenditure, vices quiet during the initial acquisi- less than the value stored at that locaand engineers must
think creatively to inB[0]
2 D[0]
1
crease throughput withB[1]
4 D[1]
3
B[2]
6 D[2]
5
out sacrificing yield.
B[3]
8 D[3]
7
B[4]
10 D[4]
9
Many test approaches are
B[5] 11
12 D[5]
beginning to rely more
B[6] 13
14 D[6]
B[7] 15
16 D[7]
on FPGAs. These ICs
B[8] 17
18 D[8]
high speeds and flexible
B[9] 19
20 D[9]
B[10] 21
22 D[10]
usage lend them well to
B[11] 23
24 D[11]
B[12] 25
26 D[12]
ATE (automated-testD[13] 27
28 D[13]
D[0-15]
Q[0-15] A[0-15]
B[0-15]
equipment) shortfall
B[14] 29
30 D[14]
D[0-17]
A[0-15]
Q[0-17]
B[0-15]
D[15]
B[15] 31
32
workarounds and pare
IC3
VDD 33
34 WCLK
WCLK 80 IC1
REG RECEIVER
down final test time,
GND 35 P2A
36 GND P1B
FIFO
SN74LVTH16543
CONNECTOR
VDD
VDD 37 CONNECTOR
38
SN74V293
which could add up to
GND 39 QSE-020-01-L-D-A
40 GND QSE-020-01-L-D-A
MRS FF RCLK REN OE
LEAB OEAB OEBA LEBA
thousands of dollars in
78 75 62 61 59
2/27 1/28 29/56 30/55
savings, depending on
A[16]
IC2
B[16] 2
1 MRS
time saved and volume.
SRAM
LEBA 4
FF
3
CYC1011CV33
But development of
OEBA 6
5 RCLK
OEAB 8
7 REN
D[0-15]
FPGA designs can be
LEAR 10
OE
9
D[0-15]
OE
41
GND 12
OE_R
11
time-consuming and exVDD 14
13 WE_R
WE 17
pensive; outsourced deGND 16
15 GND
A[0-16]
VDD 18
17 VDD
signs can cost more than
A[0-15]
GND 20
19 GND
$100,000, depending on
VDD 22
21 VDD
GND 24
23 GND
complexity. Also, the
VDD 26
25 VDD
GND 28
27 GND
hardware-histogram caVDD 30
29 VDD
pability of many ATE
GND 32
31 GND
VDD 34
VDD
33
systems is expensive, and
GND 36 P2B
35 GND P1A
you must multiplex it to
VDD 38 CONNECTOR
37 VDD CONNECTOR
GND 40 QSE-020-01-L-D-A
39 GND QSE-020-01-L-D-A
multiple sites, which reduces its time-saving
effectiveness. This
Figure 1
Design Idea presA hardware-based histogram system for testing ADCs uses off-the-shelf components.
ents a simple, discrete
hardware-histogram circuit module (Figure 1), which uses off- tion. And, because many high-speed con- tion, not including bit 16. Address-bit
the-shelf components, requires no soft- verters require low-jitter sources, the use 16 keeps the bin counts and look-up
ware, is easy to debug, and is easy to of the FIFO memory eliminates the need table in different columns. When each
multiply to many sites and channels.
to synchronize the test head with exter- sample routes from the FIFO memory
The circuit of Figure 1 shows how you nal sources by using the system clock to to the address bits, the FIFO memorys
can configure a FIFO memory, a static run the rest of the circuit.
output becomes disabled as the bin
SRAM, and a bus register to generate fast
The SRAM stores each bin count in count for that code appears on the bus.
hardware histograms for linearity tests the address whose value is equal to the The bus registers bus-hold function
and still allow straight data acquisition code being accumulated. The memory conveniently holds the current bin
for other tests. The main purpose of the is generally underused, because part of count on the address lines while the
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design
ideas
SRAMs address-bit 16 is toggled to acOE

cess the count look-up table, and the
bin count1 appears on the bus. The
RCLK
bus register latches in the new bin
SAMPLE
SAMPLE
SAMPLE
QN
count while the FIFO memory reWE
asserts the sample data.
The SRAM then accesses the bin count
OE
(address-bit 16 reset) in write mode
A16
when the bus register reasserts the new
AN/DN
bin count with the FIFO memory disN
N
N+1 N+1
N+1
N
N
abled. This cycle plays out until the hisOEBA
togram is complete and the data is read
LEAB
through the bus register to the test head.
Figure 2 shows the timing scheme. AlLEBA
though the FIFO memory has a depth of
only 64 kbytes, note that the FIFO mem0 nSEC
10 nSEC
20 nSEC
30 nSEC
40 nSEC
50 nSEC
60 nSEC
70 nSEC
ory can be filled multiple times and the
histogram can be updated multiple times
until the SRAM is cleared. You enFigure 2
This graphic shows the histogram cycle timing for the circuit in Figure 1.
counter no overflow, regardless of
bus width, as long as no bin count exceeds 16,383. The look-up table can be when the handler is binning. This circuit channels, because you can simply plug the
written before any device is tested, and the is particularly useful when your applica- inexpensive module into other sites or
bin counts can be reset between tests tion requires multiple sites or multiple channels and operate it in parallel.
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ideas
The best of
design ideas
it out at:
8 Check
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Circuit controls microneedle etching

Stephen Woodward, Marine Sciences, Chapel Hill, NC
t its invention roughly two decades ago, STM (scanning tunneling
microscopy) created a sensation because it was the first technology to make
atomic-scale-resolution imaging a routine procedure. An essential requirement
for the practical application of STM is
some means for the reproducible fabrication of supersharp, atomic-scale needle
tips. One way to make the tips is to etch
them from short pieces of platinum wire
in a calcium-chloride electrolyte bath.
Applying an ac voltage between the electrolyte and the wire generates a chemical
reaction accompanied by vigorous fizzing
at the surface of the liquid. This reaction
etches the platinum, causing the wire to
neck down and eventually break into two
pieces. If the etching current turns off

within milliseconds of the wires breaking, then the point of separation remains
supersharp. This sharp point is suitable
for use as a high-quality STM tip. Swift
interruption of the current, however, is
essential to tip sharpness, because only
a few milliseconds of overetch suffice to
dull and ruin the tip. The circuit in Figure 1 achieves precision etch-termination by using relay-actuated etch turnoff based on the sudden drop in etch
current that occurs when the wire parts.
Precision sensing and full-wave rectification of the etch current is critical to
circuit operation; the circuit achieves this
precision by using an unusual differential-input rectifier.
Precision, full-wave rectification of

low-level ac signals to a dc format is a
common signal-processing function;
many classic rectifier topologies accomCircuit controls
microneedle etching......................................87
Circuit removes
relay-contact bounce ....................................88
Log-ratio amplifier has
six-decade dynamic range ..........................90
VCXO makes inexpensive
dual-clock reference ......................................92
60 Hz AC
FROM VARIAC
OUT/IN
4
1N4004
FULL-WAVE
PRECISION RECTIFIER
RELAY: RS275-248
15V
12V AC
120V AC
+
STOP
START
1N914
~40 mA
470 F
25V
I
G
1N914
Figure 1
D1
IC1A
0.3
5W
R1
13
3k
12
IC1B
C1
47 F
10V
12V
COMPARATOR
10k*
IC1D
RUN
Q2
2N3906
+
5
FILTER
14
THRESHOLD
SET: 0 TO 100
10k
0.39
F
10k
O
5.6k
7
D2
+
Q3
2N4401
Q1
2N3906
10
+
R2
453*
12V
+ 100 F
C2
6V
7812
820
390k
IC1C
3
1N914
100k
100k*
0.22 F
10-TURN
+ DIAL
11
NOTES:
1
ALL OP-AMPS ARE 4 LM324s.
* = 1% METAL FILM.
ETCH
CURRENT
This etch-control circuit produces supersharp microneedles by terminating the etching process at precisely the right time.
www.edn.com
November 27, 2003 | edn 87
design
ideas
plish this function. But the accuracy of

typical precision rectifiers depends on the
precise matching of resistor ratios. Moreover, op-amp input-offset voltages limit
the accuracy of these standard circuits.
The offset error generally limits sensitivity to input spans no smaller than some
hundreds of millivolts. The converter in
this design avoids these faults and adds a
number of new and useful features. The
differential ac signal to be rectified goes
to the noninverting inputs of op amps
IC1A and IC1B (Figure 1). Rectification
proceeds as follows: Consider a signal excursion,VIN, that drives IC1As input more
positive than IC1Bs. Amplifier IC1A responds by driving diode D1 into conduction, thereby forcing R2 to track the in-
put. Amplifier IC1B responds with a negative output excursion, forcing transistor
Q2 to conduct sufficiently to cause the inverting input of IC1A and the bottom end
of R1 to track. Q2s emitter current, and,
therefore, collector current is then I
VIN/R2VR1/R2; Q2 is a high-alpha transistor.
The respective roles of the amplifiers
reverse for input excursions of the opposite polarity, with D2 and Q2 conducting.
The match of Q1 and Q2 alpha values,
which is typically 0.3% or better, is the
only limit on rectification symmetry.
This precision rectifier is therefore
unique in that neither rectification symmetry nor common-mode rejection,
which exceeds 60 dB, depends on resistor
matching. Meanwhile, C2 affords ac coupling, which eliminates offset-voltage-related errors. Operation of the rest of the
etch controller is straightforward. IC1C
implements a unity-gain, two-pole Butterworth lowpass filter for good ripple attenuation without excessive time delay.
Etching begins when you push the Start
pushbutton. The etch-current comparator, IC1D, then drives Q3 to keep the relay
energized until the etch current drops below the level set by the Threshold Set potentiometer. IC1Ds output then drops
low, turning Q3 off, opening the relay, and
terminating the etch. The result is a serviceable, atomically sharp scan tip almost
every time.
Circuit removes relay-contact bounce

John Guy, Maxim Integrated Products, Sunnyvale, CA
dvances in semiconductor technology have allowed ICs to replace
many mechanical relays, but relays
still dominate in high-current circuits
that must stand off high voltages of arbitrary polarity. Contact bounce in those
drives the relay closed, and that relay closure connects the input of the hot-swap
circuitry to the power supply: 28V, in this
10V/DIV
case. The hot-swap controller, IC1, keeps
the p-channel MOSFET, Q1, off for a
minimum of 150 msec after the input
supply reaches a valid level.
Q1
FROM
That delay allows ample time
TO SYSTEM
MTD20P06
K1
POWER SUPPLY
POWER LOAD
for contact bounce in the re4
28V
5A/DIV
3
lay to subside. After the 150OUT
100 SEC/DIV
1
msec delay, IC1 drives
2
The mechanical relay, K1, by
Figure 2
the MOSFET gate such
itself exhibits contact bounce
that the output voltage slews on closure as shown.
R1
DRIVE
1
2
3
at 9V/msec. This controlled
CIRCUIT
100k
VS GATE DRAIN
ramp rate minimizes the in6
rush current, thereby reducON
5
PGOOD
ing stress on the power sup4
GND
ply, the relay, and capacitors
IC1
Figure 1
downstream from the hotMAX5902
10V/DIV
swap controller.
GND
GND
An example of relay contact bounce shows three
A hot-swap controller IC and external MOSFET removes conbounces with an inrush-curtact bounce from relay K1.
rent peak of almost 30A
relays, however, can prove troublesome to (Figure 2). The top trace is output volt- 500 mA/DIV
1 mSEC/DIV
downstream circuitry. One approach to age at 10V/division, the lower trace is incontact bounce combines a relay with a put current at 5A/division, and the
The Figure 1 circuit removes
Figure 3
hot-swap controller. Such controllers are output load is 54 in parallel with
relay-contact bounce and
increasingly popular as the means for 100 F. Use of the Figure 1 circuit under reduces inrush current.
switching system components without these conditions yields a better picture
shutting down the system power. In Fig- (Figure 3). The delayed rise in output current shows much less variation, peakure 1, a relay contact replaces the pin of voltage is clearly visible, with no hiccups ing under 1.5A before settling to a steadya mechanical connector. The drive circuit arising from contact bounce. The input state value of 500 mA.
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design
ideas
Log-ratio amplifier has six-decade dynamic range

Reza Moghimi, Analog Devices, San Jose, CA
ou need optical-power monitoring to guarantee overall system performance in fiber-optic communication systems. Logarithmic-signal processing can maintain precise measurements over a wide dynamic range. The
wide-dynamic-range signal undergoes
compression, and the use of a lower resolution measurement system then saves
cost. As an example of this technique,
consider a photodiode with responsivity
of 0.5A/W that converts light energy to a
current of 100 nA to 1 mA. With a fourdecade dynamic range and 1% error, the
required measurement resolution is
0.01104, or 1 ppm. This measurement
requires a 20-bit ADC. Instead, you can
compress this input to a 0 to 4V range using a log-ratio amplifier and then use a
10-bit ADC, substantially reducing the
system cost. Programming the reference
current allows shifting the output voltage
to the desired level. You can customize
and use the circuit in Figure 1 in applications involving unusual combinations
of dynamic range; input signal, such as
voltage or current; polarity; and scaling;

or operations such as log products and
ratios. Log-ratio amplifiers find applications in wide-dynamic-range ratiometric
measurements, which measure an unknown signal against a variable-current
reference. The transfer function of the
circuit in Figure 1 is:
where K is the output scale factor, IIN is

the current that the photodiode generates, VT is a temperature-dependent term
(typically, 26 mV at 25C and proportional to absolute temperature), and IREF
is the reference current. VOUT0 when
IINIREF. For proper operation, IIN/IREF
should always be greater than 0. The output of the log-ratio circuit can be positive, negative, or bipolar, depending on
the ratio of IIN/IREF. The 4V full-scale in-
put range of the ADC sets the 4-mA fullscale input-current range. Programming
IREF to a value of 40 to 600 A places the
output in the middle of the measurement
range.
The components give an output-scale
factor of 1. This circuit has an output
defined over a range of 4.5 decades of
signal current, IIN, and 1.5 decades of reference current, IREF (limited by the loaddriving capability of the reference for a
total six-decade range. For most applications, you would use only a portion of the
entire six-decade range. By determining
the range of the expected input signals
and computing their ratios, you can use
the equations to predict the expected output-voltage range. You can assign IREF and
IIN to match device performance to the
current range, but you should observe
polarity.
A log amplifier generally depends on
the nonlinear transfer function of a transistor. The general transfer function of a
log amplifier is related to IS and VT, which
both depend on temperature. IS is the
50-k9 33-TURN DIGITAL AD5201 POTENTIOMETER

DIGITAL TRIM FROM 3600 TO 50,000
2
AD5201 W
VS
3
SLEEP
330 pF
5V
VCC
VCC
OUT
GND
B
A
4
REF191
2.048V
REFERENCE
3600
CS SDI CLK
SHDN
MAT02/AD
1 C1
C2 7
2 B1
B2 6
IIN
1/2 AD8626
V+
3 E1
IREF
VEE
5V
E2 5
R3
2.2k
V+
LARGE-AREA
PHOTODIODE
1/2 AD8626
330 pF
R1(T)
1k
R2
15.7k
VCC
10 F
BAND-WIRE
SERIAL
INTERFACE
TEMPERATURE
COMPENSATED
VRE
VIN
VD
SCL
AD7810
DOU
VIN
Figure 1
1 F
AGN
MICROPROCESSOR
CONV
This circuit is a programmable, temperature-compensated log-ratio amplifier.
www.edn.com
design
ideas
3V
4V
Figure 2
Figure 3
2V
3V
IREF=40 A; IIN=100 nA TO 4 mA.
IREF=570 A, IIN=100 nA TO 4 mA.

1V
2V
1V
10
30
V (V65:OUT)
100
300
1k
I (R86)/ I (V43)
VOUT has IREF programmed to full scale of 570 A.
transistors collector saturation current,

and VT is the transistors thermal voltage. To overcome this temperature dependency, this design uses a matched pair
of MAT02 transistors to cancel the IS
temperature drift and a temperaturesensitive resistive voltage divider to compensate for the temperature coefficient of
VT. The heart of the IREF generator is a
REF191. You adjust its output with an
AD5201 digital potentiometer. This
modification allows you to program the
3k
10k
0V
1
3
V (V65:OUT)
10
30
100k
300k
1k
I (R86)/ I (V43)
VOUT has IREF programmed to zero scale of 40 A.
reference current in 33 steps, from 40 to

600 A.
The combination of the REF191 and
the AD5201 provides a current source
that is stable with respect to time and
temperature. For higher resolution, you
can use the 1024-position AD5231. The
AD8626 is a dual precision-JFET-input
amplifier with true single-supply operation to 26V, low power consumption, and
rail-to-rail output swing, allowing a wide
dynamic range. Its output is stable with
capacitive loads in excess of 500 pF. Figures 2 and 3 show the transfer function
of the log-ratio amplifier at the input of
the ADC. The output is limited to 0 to 4V
to match the unipolar input-voltage
range of the AD7810 ADC.
Reference
1. Sheingold, Dan, Editor, Nonlinear
Circuits Handbook, Analog Devices,
ISBN: 0-916550-01-X.
VCXO makes inexpensive dual-clock reference

Said Jackson, Equator Technologies Inc, Campbell, CA
his Design Idea describes an inexpensive circuit to generate two extremely high-quality, crystal-clockreference-signals, one of which is a
PWM-controlled VCXO (voltage-controlled crystal oscillator) clock signal
(Figure 1). The design also includes circuitry to statically switch and hold the
VCXO at its nominal fixed frequency of
operation (equivalent to 50% PWM)
without requiring any external PWM
stimulus. Most digital audio/video microprocessor-based systems today require
several independent clocks with low jitter and the potential adjustability a
VCXO provides. The described circuit replaces two expensive monolithic VCXO
and crystal oscillators at a fraction of
their cost and provides much higher
quality output signals than the monolithic solutions can generate, especially at
the control limits of the VCXO (100%
deviation). The circuit generates signals
with higher stability, much lower jitter,
lower operating voltage (3.3 versus 5V)
and a wider VCXO pull range than comparable monolithic approaches at less
than one-third of their cost.
You can use the circuit in a wide variety of applications; the indicated component values make it a perfect fit for a
digital audio/video system, such as a digital video recorder, digital camera, or settop box. The circuit is well-suited to single-chip, media-processing applications
that require adjustability, low cost, and
low-jitter performance, such as systems
based on Equators (www.equator.com)
broadband-signal processors. These
types of systems generally require a fixed
frequency, such as 25 or 33 MHz, for the
processor subsystem (Ethernet, PCI bus,
for example) and an adjustable 27-MHz
reference clock for the audio/video reference subsystem. A PLL system generally
controls the 27-MHz reference clock.
(This PLL is usually implemented in software with PWM outputs from the microprocessor controlling the 27-MHz
clocks deviation.) This approach guar-
antees a correct synchronization of the

audio and the video data streams to each
other and the broadcast source. The clock
requires 50-ppm adjustability, and the
circuit in Figure 1 provides more than
70 ppm. The circuit suits high-volume
manufacturing, the highest quality signal
(lowest jitter), and the lowest production
cost.
The design incorporates several novel
circuit features, such as both overtoneand harmonic-crystal operation, use of
inexpensive voltage-controlled capacitors
(varactor diodes), a single 3.3V powersupply operating voltage, and a selectable
50%-duty-cycle, 27-MHz-operation,
fixed-frequency mode. The fixed-frequency mode allows operation at 27
MHz without the PLL-PWM circuits
having to provide a 50% duty cycle, potentially freeing up hardware and software resources in the microprocessor that
usually generates the PWM signal. This
mode is usually invoked when the audio/video signals are generated internalwww.edn.com
design
ideas
32-MHz,
THIRD-OVERTONE
FOXSD/320-20
Y1
1
2
C2
10 pF
C3
10 pF
R3
560 1
AUDIO/VIDEO VCXO
EPCOS B82494-A1472-K
L1
47 H
R5
1M
R1
1M
C1
1000 pF
IC1A
74LVC04
IC3B
74LVC04
R6
56
REF_27 MHz
IC1B
74LVC04
REF_32 MHz
IC3A
74LVC04
R7
560
3.3V
TSSOP14
74LVC00APWDH
5
6
4 IC2B
Figure 1
TSSOP14
74LVC00APWDH
32 MHz 2
3
1 IC2A
14
9
10 IC2C
C4
22 F
10V
12
FIXED_VS_
VCXO_SELECT
13
PWM
SIGNAL
TSSOP14
74LVC00APWDH
14
IC2D
R8
3.3k
C8
0.01 F
R9
3.3k
CONTROL
VOLTAGE
C6
R10
0.01 F 47k
C9
1 F
11
TSSOP14
74LVC00APWDH
PWM_INPUT
PWM FROM
PLL PHASE
COMPARATOR
Y2
1
20-PPM, 18 pF-LOAD,
27-MHz CRYSTAL SMD
CITIZEN
HCM49-27.000MDDUT
2
14
14
C5
0.1 F
R4
3.3
D1
BB133
PHILIPS
C7
0.01 F
R11
47k
C11
0.01 F
D2
BB133
PHILIPS
C10
3.3 pF
PWM MULTIPLEXER
This circuit, ideal for A/V applications, generates two high-quality clock-reference signals.
ly to the system, such as when playing

back from a hard drive, and audio/video
synchronization to an external source is
unnecessary.
The circuit includes IC1, a 32-MHz,
PCI-based fixed-frequency reference
clock; IC2, a PWM multiplexer; and IC3,
a 27-MHz VCXO clock. A Fox (www.fox
online.com) 32-MHz, third-overtone
crystal serves to generate both the PCI
reference clock and the 50%-duty-cycle
reference for the fixed-frequency mode.
A third-overtone, 32-MHz part is less expensive and more mechanically robust
than a 33-MHz, fundamental-mode
crystal at the expense of running the PCI
clock slightly slower. The tank circuit
around inductor L1 and capacitors C1 and
C3 prevent the crystal from oscillating at
its fundamental mode of approximately
11 MHz. This tank circuit works by creating an LC series-resonant circuit between L1 and C3 that has natural resonance at approximately 24 MHz, which
is approximately 75% of the desired 32MHz frequency. Note that C1 is large
enough to have no effect on this tank circuits resonance frequency; it merely acts
as a dc blocker for inductor L1. One thing
to avoid is to connect this tank circuit to
the input side of inverter IC1A. Connecting it to the input side of IC1A could potentially create a resonant RC circuit with
resistor R1 and capacitor C1 acting as the
RC components. This circuit could oscillate at less than 1 kHz, a frequency at
which L1 would effectively be a short circuit, and crystal Y1 would be an open circuit. Placing C1 and L1 on the output side
of IC1A prevents this spurious-oscillation
mode.
By tuning L1 and C3, you can adjust the
circuit to oscillate at a frequency higher
than the third overtone. Oscillation at the
fifth, seventh, or even ninth overtone is
possible and is limited only by the performance of IC1A and the parasitic capacitance. The 32-MHz PCI referenceclock output also serves as a 50%duty-cycle reference for the VCXO when
the VCXO is operating in its fixed-frequency, 27-MHz mode. Multiplexer IC2
selects either this 32-MHz, 50% PWM
clock signal or the PWM clock signal
from a PLL phase comparator (usually
implemented in the microprocessor and
not shown in the schematic) to set the
VCXO to its fixed-frequency mode. The
advantage of using the PCI clock for this
feature is that traditional circuits would
have to generate an analog one-half-VDD

voltage and use an analog multiplexer to
set the VCXO at its nominal frequency.
Thus, this design avoids the necessity of
using accurate and expensive analog circuitry and also generates a reference signal with much higher immunity to temperature, for example, than analog
approaches could provide.
Digital multiplexer IC2 forwards one
of two PWM signals to the VCXO based
on the state of the fixed-versus-VCXO selected input signal. The PWM-input signal serves as the PWM reference input to
the VCXO if the select pin is high, and the
design uses the 50%-duty-cycle PWM
signal from the PCI clock circuit if the select pin is low. The design uses a 74LVC00
chip as a multiplexer because of its ready
availability and low cost. IC2C buffers the
PWM signal, and the cascaded RC filter
comprising R8, R9, C8, and C9 then lowpass-filters the signal. The analog-voltage
stability of the VCXO control voltage at
the output of this RC filter depends on
the quality of the VDD supply to IC2C. IC2
receives its 3.3V power through an RC filter: R4 with C4 and C5. IC2 with R8, R9, C8,
and C9 thus form a highly accurate D/A
converter.
www.edn.com
design
ideas
The VCXOs lowpass filter uses a cascaded design, because stray 32-MHz
noise could pass across the small parasitic capacitance inherent in R8 into the
analog VCXO-control voltage. Cascading also has the advantage of filtering
noise with 12 dB of attenuation per octave for frequencies greater than 5 kHz,
thus creating a noise-free VCXO control
voltage. The 27-MHz audio/video VCXO
circuit uses a fundamental-mode crystal that varactor diodes D1 and D2 load
with adjustable capacitance. These backbiased diodes junction capacitance depends highly on the bias voltage. Larger bias voltages lower their capacitance,
thus lowering the load across the crystal
and increasing its oscillation frequency.
Diodes D1 and D2 find use in many
tuners and are widely available. Capacitors C6 and C7 again function as dc
blockers.
The adjustment range of the VCXO is
approximately 27 MHz2 kHz, which

calculates to approximately 74 ppm.
The circuit is stable with very low jitter
throughout its entire 0 to 100% VCXOadjustment range. You can use the VCXO
subcircuit by itself to generate a spreadspectrum clock for EMI compliance. You
drive the VCXO voltage or PWM duty cycle from 0V (0%) to 3.3V (100%) with a
triangular-shaped drive signal. The frequency of the triangular wave must be
below the PWM RC filters cutoff frequency of 24 Hz to be effective. The oscillator circuits jitter depends on the
power-supply quality of IC1, IC2, and IC3
and on the noise inside these chips. To
avoid crosstalk between 32 MHz and 27
MHz, the design uses two chips. Implementing buffers IC1B and IC3B with separate chips, thus separating the powersupply loading from the sensitive buffers,
IC1A and IC3A, could further reduce jitter.
With independent clock buffers and a
low-noise power supply, this circuit has

exhibited a maximum cycle-to-cycle jitter of less than the 60-psec limitation of
the HP54720D oscilloscope that measures it. This figure betters the jitter characteristics of popular crystal oscillators
and VCXO chips available for consumer
applications. It also does not suffer from
unstable operation at its adjustment
margins (operating at 100% deviation), as designers commonly encounter
with monolithic components. Another
added benefit is that it achieves its 74ppm adjustment range with only a single
3.3V power supply, whereas monolithic
approaches usually require a 5V power
supply and control voltage. Finally, it offers all this performance at a total price
of less than $1.40 in large quantities by
using only commonly available, off-theshelf components. This figure compares
to $3 to $6 parts cost with monolithic approaches.
www.edn.com
design
ideas
Rechargeable flashlight obsoletes lantern battery

Fran Huffart, Linear Technology, Milpitas, CA
his Design Idea dethe probability of the
scribes a high-intensity,
lamps failure at turn-on.
FIVE- OR SIX-CELL
rechargeable flashlight
The soft-start circuit
MAGLITE
system that you can build
consists of an n-channel
KRYPTON LAMP
TO
from a 6V lantern-type
MOSFET in series with
680k
CHARGER
+
flashlight. The rechargeable
the lamp, which ramps
ON
battery comprises four 2V,
the lamp voltage up at a
IRLR024
2.5-Ahr (ampere-hour) SLA
controlled rate to reduce
OFF
IRFR024
(sealed lead-acid) cells, simthe inrush current. A
10k
+
ilar in size to a stangate-to-source capacitor
4.7 F
Figure 1
dard D-sized batcontrols the ramp speed.
tery. SLA cells are especially
The lamp turns on in apFOUR SEALED-LEAD-ACID
well-suited to powering
proximately 2 sec. Figure
CELLS 2V, 2.5 AHR EACH
flashlights because of their
2 shows the dramatic relow self-discharge rate.
duction in lamp inrush
This soft-start circuit reduces inrush current, thereby prolonging lamp life.
NiCd (nickel-cadmium) or
current when you use
NiMH (nickel-metal-hydride) cells can line cells the flashlight uses.) The lamps the soft-start circuit.
lose as much as 1% of their charge per operating voltage is approximately 1.25V
The charger is a 200-kHz step-down
day, compared with less than 0.2% per per cell, which makes the lamp voltage of switching regulator using current-limitday for SLA cells. SLA cells are also easy a six-cell lamp equal to 7.5V. This design ed constant voltage to charge the battery
to charge and can withstand abuse. The uses a six-cell lamp for this flashlight, al- (Figure 3). When a discharged battery
flashlight in this design uses a krypton though you could also use a five-cell, connects to the charger, the charge cycle
high-intensity lamp. Maglite (www. 6.25V lamp. A five-cell lamp provides ap- starts in a 1A constant-current mode. As
maglite.com) makes this lamp as a re- proximately 30% more light output but the battery accepts charge, the battery voltplacement lamp for its line of flashlights. has a shorter lamp life. To increase lamp age increases until it reaches the proThe lamps are extremely bright; have a life, this flashlight includes the soft-start grammed charge voltage of 2.5V/cell (10V
standard miniature-flange-base, built-in circuit in Figure 1.
total).At this point, the charge cycle enters
lens; and are available in five- or six-cell
Incandescent lamps inherently draw constant-voltage mode. During constantversions. (Manufacturers typically rate large start-up currents because of the fil- voltage mode, the charge current drops exflashlight lamps by the number of alka- aments relatively low resistance when it ponentially. When the charge current
is cold. A tungsten fila- reaches approximately 10% (100 mA) of
ments resistance is typi- the programmed current, the charge voltcally 10 times lower when age drops to a float voltage of 2.35V/cell
Figure 2
LAMP CURRENT
FIVE-CELL LAMP
cold than it is when at
800 mA AT 8V=6.4W
10
normal operating temperNO
ature. When the full batRechargeable flashlight obsoletes
LAMP
8
SOFT START
INRUSH
tery
voltage
suddenly
hits
1 mSEC/DIV
lantern battery ................................................83
CURRENT
6
a cold filament, the inrush
(A)
WITH
Single cell flashes white LED ......................84
SOFT START
current is typically 10
4
100 mSEC/DIV
Hot-swap controller handles
times the normal operat2
dual polarity ....................................................88
ing current, and this instant is when a lamp is
0
Temperature monitor measures
likely to fail. Adding a softthree thermal zones ......................................90
start circuit nearly elimiLAMP TURN-ON TIME (1 OR 100 mSEC/DIV)
nates this large inrush curWhats Up section at www.edn.com.
Using the soft-start circuit in Figure 1 provides a dramatic
rent, allowing for a higher
decrease in inrush current.
power lamp and reducing
www.edn.com
December 11, 2003 | edn 83
design
ideas
VIN
FROM AC WALL
ADAPTER
13 TO 24V
D1
23
10 F
24
Figure 3
21
28-PIN SSOP
VCC
PROG
SW
20
1 F
D2
SENSE
VC
BAT
22
0.33 F
STATUS INDICATOR
BRIGHT: CHARGE
DIM: FLOAT
FLASHING: NO BATTERY
OUT: NO INPUT POWER
7
LED
10k
82k
Q1
10
FLASHLIGHT
VBAT
19
CAP
FOUR CELLS
8V LEAD-ACID
FLAG
VFB
232k
1%
22 F
0.022 F
(SEE NOTE)
820
15 H
LT1571-1
4.99k
1N4148
0.68 F
3k
LED
LED
LED
LED
VCC
300
PROGRAM CHARGE
CURRENT (5k FOR 1A)
BOOST
976k
1%
100k
Q2
12k
82.5k
1%
VBAT IS 10V FOR CHARGE

CURRENTS GREATER THAN
100 mA AND 9.4V FOR
CHARGE CURRENTS LESS
THAN 100 mA.
NOTES:
GROUND PINS 1, 2, 3, 11, 12, 13, 14, 15, 16, 17, 18, 25, 26, 27, AND 28 TO GENEROUS
AMOUNTS OF PC-BOARD COPPER FOR BEST THERMAL AND ELECTRICAL PERFORMANCE.
Q1 AND Q2 ARE VN2222s, OR 2N7002s.
D1 AND D2 ARE 1A ,30V SCHOTTKY DIODES.
This battery charger uses current-limited constant voltage to charge the lead-acid cells in the flashlight.
(9.4V total). This dual-voltage approach

provides a faster charge and also provides
an LED indication when the battery is
nearly fully charged. The charger keeps the
battery at this float voltage, thus keeping
the battery in a fully charged condition.
You can leave the charger indefinitely connected to the battery without damage to
the battery, although battery damage can
result if it is fully dischargedwhen the
battery voltage is less than 1.8V/celleither through use or self-discharge. The
FLAG pin is an open-collector output that
indicates when the charge current has

dropped to approximately 10% of the full
programmed charge current.
A wall adapter with an output from
13V, 1A to 26V, 0.5A provides power to
the charger. This design uses all surfacemount components to reduce the overall size of the charger. The pc-board layout should include wide ground traces
that expand to larger copper areas to
minimize the possibility of overheating
the IC. The flashlight housing features a
3- to 4-in. reflector and has a handle on
top; it is readily available from Radio

Shack (www.radioshack.com) and other
electronics outlets. The light is designed
for a 6V lantern battery, but this design
replaces the lantern battery with four Dsized, SLA cells. The cells leave enough
room for the soft-start circuitry. Other
modifications include replacing the
switch with a high-quality SPDT switch
and soldering all the connections for increased reliability. A dc power jack connects the flashlight to the charger.
Single cell flashes white LED

any portable appliances and other products that must operate from
a single cell are restricted to working at very low voltages. It is thus difficult
to drive white LEDs that typically have a
forward voltage of 3 to 5V. The ability to
flash the LED with a supply voltage as low
as 1V presents additional complications.
The circuit in the Figure 1 provides a dis-
84 edn | December 11, 2003
crete approach to these problems and allows a white LED to flash at a rate set by
an RC time constant. Components Q1,
Q2, R3, R4, and R5 form a simple Schmitt
trigger that, together with R1, R2, and C1,
controls the flashing of the LED. Q4, Q5,
L1, and associated components form a
voltage booster that steps up the singlecell voltage, VS, to a level high enough to
drive the LED. Transistor Q3 functions as

a switch that gates the booster on and off
at a rate determined by the Schmitt-trigger section.
To understand how the booster section
works, assume that Q3 is fully on, such
that Q4s emitter is roughly at the batterysupply voltage, VS. Q4 and R8 provide bias
for Q5, which turns on and sinks current,
www.edn.com
design
ideas
IL, through inductor L1. The inductor With the values of R3 and R5 in Figure 1, R2 have values of approximately 1 M
current ramps up at a rate determined VB2 is approximately 800 to 900 mV when each and C1 has a value of 1 F or greater,
mainly by VS and the value of L1; during VS1V. This voltage produces approxi- a rate of less than one flash per second is
this time, LED1 and series diode D1 are re- mately 300 to 400 mV across R4, resulting possible. Remember, however, that R1 and
verse-biased. The current continues to in a collector current of at least 15 A in R2 form a voltage divider that sets Q1s
ramp up until it reaches a peak value, Q2 with R420 k. Q2s collector current base voltage, VB1; therefore, R2 must be
ILPEAK. Q5 can sustain no further increase, provides base drive for Q3, which satu- sufficiently larger than R1 to ensure that
and the voltage across the inductor at this rates, turning on the booster section and VB1 can cross the Schmitt triggers upper
point reverses polarity. The resulting fly- illuminating LED1. When LED1 is for- threshold voltage as C1 charges. With this
back voltage raises LED1s anode to a ward-biased, C4 charges to a positive volt- fact in mind, you can with some trial and
positive voltage higher than VS, sufficient age, VP, roughly one diode drop above VS. error fairly easily find the optimum valto forward-bias LED1
and signal diode D1.
VP
The flyback voltage is
VS
also coupled through
R6
C3 and R10 to Q4s base,
1M
thus causing Q4 and,
Q3
D1
hence, Q5 to turn off
L1
R3
1N4148
rapidly.
220
H
100k
The inductor current now circulates
Q4
around L1, LED1, and
IL
C3
R10
D1, and, as the energy
R1
LED1
100 pF
1k
WHITE
stored in L1 decays, the
+
VB1
VB2
LED
current ramps down to SINGLE CELL
Q2
Q1
1.5V NOMINAL
C4
zero. At this point, the
R7
R8
10 nF
100k
510
inductor voltage again
R2
Q5
reverses polarity and
C2
+
R9
C1
1 nF
R4
R5
the negative-going
10k
Figure 1
20k
750k
change is coupled
0V
through C3, rapidly
turning on Q4 and, in
turn, Q5. Current again
begins to ramp up in This circuit provides boosted voltage and flashes a white LED from a single cell.
L1, and the process repeats. The booster section oscillates at a Timing capacitor C1 now charges via R1 ues of R1, R2, and C1 necessary for a givrate determined by several factors. The at a rate determined mainly by the val- en flash rate.
The value of VP significantly influences
important factors determining the rate of ues of VP , R1, R2, and C1. Provided that
oscillation include the values of VS , L1, you carefully choose the ratio of R1 to R2, the charging and discharging of C1, and
and R8; the forward-current gain of Q5; Q1s base voltage, VB1, eventually exceeds VPs value hence varies according to the
and the forward voltage of LED1. With the quiescent level of VB2 (roughly equal prevailing battery supply voltage, VS.
the component values in the figure, the to the Schmitt triggers upper threshold However, changes in VB2, which also
oscillation frequency is typically 50 to 200 voltage, VTU), causing Q1 to turn on and varies with VS, somewhat balances this
kHz. On each cycle, a pulse of current Q2 to turn off. At this point, Q3 also turns dependence. Nevertheless, the flash rate
with a peak value equal to ILPEAK flows off, thereby disabling the booster section and duty cycle do vary somewhat as the
through LED1 and, because this scenario and turning off LED1.
battery voltage falls. For example, with
occurs thousands of times every second,
With LED1 off, VP rapidly decays, and R12.2 M, R210 M, and C11 F,
C1 begins to discharge at a rate deter- the test circuits flash rate at VS1.5V is
LED1 appears to be continuously on.
The low-frequency oscillator formed mined mainly by the values of R2 and C1 approximately 0.52 Hz with a duty cycle
around the Schmitt trigger turns the and by Q1s base current. The LED re- of 66%. With a VS of 1V, the flash rate inbooster section on and off at a low rate. mains off until VB2 has fallen below the creases to approximately 0.75 Hz but
To understand how this works, assume Schmitt triggers lower threshold voltage, with a lower duty cycle of 44%. The
that Q1 is off and Q2 is on. Provided that VTL, at which point Q1 turns off, Q2 turns Schmitt-trigger thresholds, VLT and VTU ,
Q2 has reasonably large forward-current on, and the booster section again acti- are typically approximately 0.7V and
gain, you can ignore the effects of its base vates, illuminating LED1. Provided that 1.2V at VS1.5V, falling to approximatecurrent and say that VS and the R3-R5 R1, R2, and C1 are large enough, LED1 can ly 0.6V and 0.8V when VS is 1V.
The LEDs intensity is proportional to
voltage divider set Q2s base voltage, VB2. flash at a low rate. For example, if R1 and
www.edn.com
design
ideas
its average forward current and is thus determined by the peak inductor current, IL, and by the duration of the current
PEAK
pulse through the LED. Provided that L1
is properly rated such that it does not saturate, the peak current depends largely on
the maximum collector current that Q5
can sustain. For a given supply voltage,
this figure depends primarily on Q5s forward-current gain, and on the value of R8
that you can select to give optimum LED
brightness at the lowest supply voltage.
Experiment with different values of R8 to
get the best intensity for a given LED type.
Take care, however, that the peak current
does not exceed the LEDs maximum current rating when VS is at a maximum. The
actual value of L1 is not critical, but values in the range 100 to 330 H should
provide good performance and reasonable efficiency. The transistor types in the
circuit are not critical; the test circuit
works well with general-purpose, smallsignal devices having medium to high
current gain. If possible, select low-saturation types for Q3, Q4, and Q5. C2 is not
essential to circuit operation but helps to
decouple any switching noise at Q2s base.
C4 acts as a charge reservoir and ensures that R1 can charge C1 from a stable
voltage source (VP) when LED1 is on. Because the charging current is likely to be
low, C4 can be fairly small; a value of 10
nF should be adequate. Note that C4 must
connect to the junction of D1 and LED1 as
shown, rather than being charged, via a
rectifying diode, from the flyback voltage
at Q5s collector. The reasons for this
caveat are, first, that this approach ensures that VP is only a diode drop above
VS, thereby minimizing the value of R1
necessary for a given C1 charging current.
Also, and more important, this approach
places the forward voltage of the LED in
the path from VS through L1 and R1 to
Q1s base. Because the forward voltage of
a white LED is usually at least 3V, this
connection prevents Q1 from being
turned on via this route, which could

otherwise cause the circuit to lock in the
off state.
At first sight, it might appear that you
can turn the booster section on and off
by gating current to Q4s base, thus obviating the need for Q3. However, under
certain conditions, once you activate the
booster section, the feedback to Q4s base
via C3 and R10 is sufficient to maintain oscillation without feeding any dc bias to
Q4s base. Therefore, the only reliable way
to gate the booster on and off is via Q3,
as shown. The test circuit starts up and
operates with VS as low as 0.9V, although
the LED is dim at this voltage. The LEDs
intensity is good at VS1.5V (equivalent
to a fully charged alkaline cell) and remains acceptable with VS as low as 1V.
The circuit should find applications in
toys, security devices, miniature beacons,
and any other products that must provide
a flashing visual indication while operating from a single cell.
Hot-swap controller handles dual polarity

Dan Meeks, Texas Instruments, Manchester, NH
Q1A
Si4936DY
ome applications require a hot5VIN
swap controller, a circuit-breaker
8
1
7
function, or both for dual-polarity,
C1
dc-input power-supply rails. In some
1 F
C3
10V
hot-swap cases, the requirement is based
R1
100 pF
28.7k
only on inrush-current considerations.
1%
Control of the inrush current is necesR2
sary to eliminate connector stress and
Q2
910k
IC1
2N3906
TPS2331ID
glitching of the power-supply rails. OthQ3
1
14
2N3906
GATE
DISCH
er applications may have issues when one
2
13
R4
DGND ENABLE
of the supplies fails for some reason. A
3
12
2k
TIMER PWRGD
C4, 0.1 F 4
1%
good example is a bias supply for a galli11
VREG
FAULT
5
10
um-arsenide FET amplifier. If you reVSENSE
ISET
6
9
move the negative gate bias, then you
AGND
AGND
R5
7
8
5VIN
10.7k
ISENSE
IN
must also remove the positive drain sup1%
ply; otherwise, the device may destroy itself because of the resulting high
Figure 1
drain current. You can meet both
these requirements by using a singleR6
1M
5
channel, hot-swap controller.
3
6
The circuit in Figure 1 uses a TPS2331,
5VIN
C5
IC1, in a floating arrangement. The cir1 F
Q1B
10V
cuit references the ICs ground to the
Si4936DY
negative input voltage. If the voltage on
the positive rail is too low or the voltage This circuit is a dual-polarity voltage sequencer for low-voltage applications.
5VOUT
C2
CBULK
5VIN
R3
10k
5VOUT
C6
CBULK
www.edn.com
design
ideas
Q1A
Si4936DY
on the negative rail is too high, the cir5V IN
8
5V OUT
cuit cannot attain the 1.225V threshold
1
7
at the VSENSE pin, and the IC turns off. The
C1
C2
1 F
VSENSE pin incorporates approximately 30
C3
CBULK
10V
100 pF
mV of hysteresis to ensure a clean turnR1
5V IN
on with no chatter.
When both supplies are beyond their
R2
R3
respective thresholds, IC1 turns on, pro910k
IC1
R4
10k
TPS2331ID
Q2
viding a controlled-slew-rate ramp-up
1
14
2N3906
GATE
DISCH
of the two FETs. Note that the circuit
2
13
DGND ENABLE
uses only n-channel FETs, which have
3
12
TIMER PWRGD
C4
4
11
lower on-resistance for a given size and
VREG
FAULT
0.1 F 5
10
cost than p-channel devices. To turn on
ISET
VSENSE
6
9
AGND
AGND
Q1A on, the TPS2331 has a built-in
7
8
IN
I
SENSE
charge pump that generates a voltage
5V IN
above the positive rail, thus enhancing
the FET. As the gate voltage builds, Q3
acts as a linear level translator, so
R6
Figure 2
that Q1B also ramps on. The turn1M
5
3
on speed is a function of the TPS2331s
12V OUT
6
14-A output current and the value of 12V IN
C5
1 F
C6
C3. The design uses the FETs based on
Q1B
10V
CBULK
Si4936DY
the maximum resistance allowed in the
dc path and the FETs power-dissipation
NOTE: SELECT R1 AND R4 TO SET THRESHOLD.
figures. You can use virtually any size
FET, depending on the current you want This variation on Figure 1s circuit can handle higher voltages.
to control. Take care that the total voltage span across the TPS2331 does not Figure 2 shows such an application, in handle the higher voltage. This circuit
exceed the maximum rating of 15V. If which 5V and 12V are the input sup- also allows you to use a positive input
IC1 does not float between the input plies. The main requirement is that the voltage as high as IC1s maximum ratrails, the negative input may be larger. level-shifting transistor, Q3, be able to ing of 15V.
Temperature monitor measures three thermal zones

Susan Pratt, Analog Devices, Limerick, Ireland
VCC
ou can use an ADT7461 singlechannel temperature monitor; an
ADG708 low-voltage, low-leakage
D+ ALERT
TO HOST
CMOS 8-to-1 multiplexer; and three
2N3906
2N3906
2N3906
standard 2N3906 pnp transistors to
measure the temperature of three sepaADT7461
ADG708
rate remote thermal zones (Figure 1).
S1
Multiplexers have resistance, RON, assoS2
SDA
D
D
ciated with them; the channel matching
S3
TO HOST
SCL
S4
and flatness of this resistance normally
result in a varying temperature offset.
A2 A1 A0
This system uses the ADT7461
Figure 1
temperature monitor, which
MULTIPLEXER CONTROL
can automatically cancel resistances in This system measures the temperature of three remote thermal zones.
series with the external temperature sensors, allowing its use as a multichannel no effect. Resistance associated with the from the ADT7461. The design requires
temperature monitor. The resistance au- pc-board tracks and connectors also can- no user calibration, so the ADT7461 can
tomatically cancels out, so RON flatness cels out, allowing you to place the re- connect directly to the multiplexer. The
and channel-to-channel variations have mote-temperature sensors some distance ADT7461 digital temperature monitor
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design
ideas
200
ADDRESS CHANGED HERE
can measure the temperature of an external sensor with 1C accuracy. The

remote sensor can be a monolithic or a
discrete transistor and normally connects
to the D and D pins on the
ADT7461. In addition to the remote-sensor-measurement channel, the ADT7561
has an on-chip sensor.
The diode-connected transistors have
emitters that connect and
Figure
then connect to the D input of the ADT7461, and each of the
base-collector junctions connects to a
separate multiplexer input (S1 to S3).You
connect the selected remote transistor to
the D input on the ADT7461 by addressing the multiplexer, which address
bits A2, A1, and A0 digitally control. The
ADT7461 then measures the temperature of whichever transistor is connected
through the multiplexer. The ADT7461
measures the temperature of the selected
sensor without interference from the
other transistors. Figure 2 shows the re-
150
ADDRESS=010
100
TEMPERATURE
(C)
ADDRESS=000
50
ADDRESS=001
0
IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII
18
35
52
69
86 103 120 137 154 171 188 205 222 239 256 273 290
50
2
100
REMOTE TEMPERATURE
LOCAL TEMPERATURE
The system in Figure 1 measures ambient (address 000), cold (address 001), and hot (address 010)
temperatures.
sults of measuring the temperature of

three remote temperature sensors. The
sensor at address 000 is at room temperature, the sensor at address 001 is at a low
temperature, and the sensor at address
010 is at a high temperature. When you
select no external sensor, the open-circuit flag in the ADT7461 register activates, and the Alert interrupt output as-
serts. You can expand the system to include as many external temperature sensors as your design requires. The limiting
factor on the number of external sensors
is the time available to measure all temperature sensors. If your design requires
two-wire serial control of the multiplexer, you can use an ADG728 in place of the
ADG708.
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design
ideas
Two DDS ICs implement amplitude-shift keying

Noel McNamara, Analog Devices, Limerick, Ireland
any communications systems,
including RFID systems and cable
modems, use AM (amplitude
modulation). This Design Idea shows
how two DDS (direct-digitalFigure
synthesis) devices can implement AM and ASK (amplitude-shift keying) over a range of frequencies. The
AD9834 complete 50-MHz DDS IC (Figure 1) has a current output, so you can
easily sum the outputs of two or more of
them by connecting them to a common
termination resistor. Each AD9834 has
two internal phase registers, P0 and P1,
and two internal frequency registers, F0
and F1 (not shown). With each AD9834
generating a sine wave at the same frequency, the amplitude of the summed
signal depends on the phase of each signal. You can achieve four preset amplitude levelsor any on-the-fly levelby
summing the outputs of two AD9834s.
Table 1 shows two AD9834s, IC1 and
IC2, configured to give four output levels. P0A is phase register 0 for IC1, P1A is
phase register 1 for IC1, and so on. You
can select the desired output level with
either the PSEL pins or with the PSEL
bits in the control register. Figure 2
shows the waveforms at the RTERM summing junction for the phases used in
Table 1. You can achieve any signal level
from 0V to a full-scale voltage of approximately 600 mV by programming
the phase registers with the appropriate
Two DDS ICs implement

amplitude-shift keying ..................................57
VCO produces positive and
negative output frequencies........................58
16-bit adjustable reference uses
8-bit digital potentiometers ........................62
www.edn.com
6.8k RSET
FSADJUST
PSEL
FSYNC
FSEL
SCLK
IC1
AD9834
SDATA
IOUTA
IOUTB
MCLK
RESET
100
6.8k RSET
FSADJUST
RESET
MCLK
SCLK
SDATA
IC2
AD9834
IOUTB
FSYNC
PSEL
SUM OF SIGNALS
FROM BOTH
AD9834s
IOUTA
FSEL
100
RTERM
100
You can use two DDS chips to implement amplitude modulation and amplitude-shift keying.
values. Both devices use the same MCLK

(master clock), and you need to synchronize them to get the correct signal
levels at the RTERM output. You achieve
synchronization by simultaneously applying a Reset signal to both parts after
programming both parts with the correct phase and frequency. You can accomplish the synchronization by applying a positive pulse to the Reset pins, or
you can implement a software synchronization by setting the reset bit in the
control register to one, stopping MCLK,
setting the reset bit in the control register to zero, and then starting MCLK. Ei-
ther method ensures that both parts simultaneously exit the reset state.
You can easily implement 100% AM
with a single AD9834 by toggling the Reset pin or the reset bit in the control register. When the part is in reset, the DACs
output is at midscale. The predetermined
sine wave is available at IOUT when the
DDS exits reset. To calculate the magnitude of the sum of the two signals from
the AD9834s, represent each signal as a
rotating vector (Figure 3). You can easily calculate the magnitude and phase of
the resulting summed vector as follows:
If the length of each vector is 1, then:
December 25, 2003 | edn 57
design
ideas
TABLE 1THE PHASE-REGISTER CONTENTS YIELD FOUR OUTPUT LEVELS FROM THE CIRCUIT IN FIGURE 1
P0
P1
P0
P1
Device
number
A
A
B
B
Phase-register
values ()
45
95
180
210
P0AP0B(45180)
P0AP1B(45210)
P1AP0B(95180)
P1AP1B(95210)
95+80
0.765SIN(2f105)
(SUM OF VECTORS A AND B)
Figure 3
95+210
45+180
Output level with RTERM

and RSET6.8 k
(mV)
100
223
128
435
350
Normalized level
of summed signal
0.765
0.426
1.47
1.191
45+210
BSIN
(2f180)
350 mV
233 mV
y3
y2
x2
y1
x3
ASIN
(2f45)
x1
300 mV
Figure 2
GND
The waveforms at the RTERM summing junction use the phases in Table 1.
x1 Cos(45)0.707: y1
Sin(45)0.707;
x2Cos(180)1.00: y2
Sin(180)0;
x3x1x20.293: y3y1y2
0.707;
Magnitude of resulting vector:
(x3)2(y3)20.765;
Phase of summed vector: 112.5
(180Tan1(y3/x3)).
The maximum output-voltage level

that any one AD9834 can develop across
the 100 termination resistor with
RSET6.8 k is 320 mV p-p. Therefore,
the voltage level this example achieves is
320 mV0.765244.8 mV. This example shows that the phase of the resulting
summed vector depends on the phase of
two input vectors and may result in a
phase discontinuity as the phases of the
You can calculate the magnitude of the summed

signals from the DDS chips by representing
each signal as a rotating vector.
input vector change. To avoid phase discontinuity at the transition, you can set
the resultant phase, P3, to a fixed angle,
say 180p2360p1.
Sin(2fp1)Sin(2fp2)2Cos
(0.5(p1p2))Sin(2f(p1p2)/2).
Desired amplitude: A2Cos [0.5(p1
p2)]; p1p2 2Cos1(A/2).
Resultant phase: P3(p2p2)/2.
Therefore, p1180Cos1(A/2), and
p2180Cos1(A/2) gives amplitude A
with no phase shift at the transition.
VCO produces positive and

negative output frequencies
Henry Walmsley, Farnborough, UK
he circuit in Figure 1 is a quadrature-output VCO that provides both
positive and negative output frequencies, depending on the polarity of
the control-voltage input. The circuit
provides a function that designers traditionally implement in analog music-effects units, such as Bode/Moog frequency shifters. Bode/Moog shifters use
fixed-beat-frequency oscillators at 20
kHz and variable sine oscillators that go
higher and lower than 20 kHz. Both oscillators feed into mixers. The circuit in
this design reduces the number of oscil-
lators to one and uses no mixers (Figure

1). As a result, the output has fewer spurious harmonics and unharmonically related frequency products, resulting in a
cleaner output overall.
The two lower transconductance amplifiers, IC4A and IC4B, form a standard,
double-integrator bandpass/lowpass filter. The lower amplifiers are active for
positive control voltages, and the upper
amplifiers, IC3A and IC3B, are effectively
turned off for lack of bias current. The
upper amplifiers thus play no part in the
circuit when the control voltage is posi-
tive. The TL072 op amps, IC2A and IC2B,

are merely buffers to enable an easier
choice of resistor values for IC4Bs input
and to avoid excessive loading of the integrator capacitors. The resistor values set
the Q (quality factor) to exceed unity.
Positive feedback from the bandpass output to the noninverting input makes the
filter oscillate. Adjusting the R3 trimmer
allows you to adjust the output amplitude
and lets you set the drive to the diodes at
a level that ensures oscillation but minimizes distortion. This fairly standard
configuration yields quadrature outputs
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design
ideas
Figure 1
R1
5k
15V
1k
47 pF
CV
1
3
2
4
7
10k
3.3k
10k
15V
8
IC1A
OPA2277
2
4
15V
1k
11
ABC V+
IN+ IC
5
3A
O
DI
LM13700
8
IN
BO
BI V
11
16
14
15
13
10
22k
ABC V+
IN+ IC
3B O 12
DI
LM13700
9
IN
BI V BO
BC559
15V
15V 100k
22k
15V
1k
1k
1k
1N4148
GND GND
22k
R2
1N4148
100k
1k
1N4148
10k
10k
15V
15V
10k
47 pF
1k
15V
BC559
5 +
8
IC1B
OPA2277
4
1
3
2
4
7
10k
15V
11
ABC V+
IN+ IC4A
5
DI LM13700 O
8
IN
BO
BI V
6
NOTES:
CONTROL-VOLTAGE INPUT: 10V TO +10V
FOR APPROXIMATELY 10 TO +10-kHz OUTPUT,
DEPENDING ON CAPACITOR VALUES C1 AND C2.
SET CV INPUT TO 1V AND ADJUST R3 FOR
2VPP OUTPUT.
SET CV INPUT TO 1V AND ADJUST R2 FOR
2VPP OUTPUT.
ADJUST R1 SO THAT THE OUTPUT FREQUENCY IS
THE SAME FOR EQUAL-MAGNITUDE POSITIVE AND
NEGATIVE CONTROL VOLTAGES.
22k
3 +
8
IC2A
1
TL072
2
4
16
14
15
13
10
ABC V+
IN+ IC
4B O 12
DI
LM13700
9
IN
BO
BI V
6
15V
15V
1N4148
11
1k
15V
22k
1k
R3
100k
C1
1k
8.2 nF
1k
5 +
8
IC2B
7
TL072
6
4
15V
15V
OUTPUT
90 0
100k
1k
15V
C2
8.2 nF
OUTPUT
0 90
22k
1N4148
1N4148
This quadrature-output VCO produces both positive and negative output frequencies.
from the two buffers with the highest distortion product approximately 40 dB
down from the fundamental.
For negative control voltages, the upper transconductance amplifiers, IC3A
and IC3B, receive bias current, and the
lower amplifiers shut off. The upper
amplifiers work in exactly the same way
as the lower ones, but they cross-connect to the inputs and integrator capacitors. In this way, the in-phase and
quadrature outputs are reversed for
negative control voltages, thus creating
a smooth transition to what you can
consider a negative frequency. In operation, when viewing the outputs on
an X-Y trace, the circular rotation of the
dot becomes slower as you adjust the

control voltage near zero and then perfectly reverses direction as the control
voltage goes negative. This transition
occurs without any unwanted crossing
of the circle or drifting off beyond the
circle.
The two current sources, IC1A and IC1B,
are fairly self-explanatory; the upper
source operates for negative control voltages and vice versa. The R1 gain trimmer
on the upper source allows you to adjust
the oscillator such that a given negative
control voltage yields the same frequency as does the equal-magnitude positive
control voltage. This trim compensates
for differences in transconductance of
the two separate dual-amplifier packages.

The diodes across the current-source op
amps avoid heavy saturation when the
respective source turns off. You trim the
R2 potentiometer to obtain equal amplitudes from the upper and the lower sections. The circuit in Figure 1 uses standard, inexpensive, multiple-sourced
components. It requires only minimal
(and easy) trimming, with no interacting
trims. A 0V control input results in a
guaranteed 0-Hz output, dependent only
on well-controlled op-amp offsets. With
the Bode/Moog system, you must make
a front-panel adjustment to zero-beat
two oscillators running at 20 kHz.
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design
ideas
16-bit adjustable reference uses

8-bit digital potentiometers
Bonnie Baker, Tucson, AZ
t may be easy to find a precision voltV
(R )
age reference for your application;
V1 AND V2= REF XB
STAGE ONE
(RXA+RXB)
however, a programmable precision
reference is another matter. The circuit in
VREF=4.096V
STAGE TWO
Figure 1 yields a precision reference with
_
IC4A
an LSB of 62.5 V. The circuit is a 16-bit
RA
IC3A
V1
+
DAC using three 8-bit digital poten_
RB
IC2A
tiometers and three CMOS op amps.
IC5A
V4
RA
Each digital potentiometer operates as an
+
VREF
8-bit multiplying DAC. On the left side of
V3
RB
_
Figure 1, two digital potentiometers, IC3A
NOTES:
IC4B
RA
and IC3B, span across VREF to ground, and
[(V1)(R2B)+(V2)(R2A)]
IC3B
V2
.
V3=V4=
+
(R2A+R2B)
the wiper outputs are connected to the
RB
IC1=PIC16F876.
noninverting inputs of two amplifiers,
IC3=IC2=MCP42010.
IC4A and IC4B. In this configuration, the
DUAL DIGITAL 10-k POTENTIOMETERS.
IC1
inputs to the amplifiers have high im3
3
IC4=IC5=MCP6022.
SPI
SPI
DUAL 10-MHz, SINGLE-SUPPLY OP AMPS.
pedance levels, thus isolating
Figure 1
VREF=MCP1541, 4.096V PRECISION
the digital potentiometers from
VOLTAGE REFERENCE.
the rest of the circuit. The microcontroller, IC1, programs digital poten- You can design a precision 16-bit DAC by using three digital potentiometers and three op amps.
tiometers IC3A and IC3B through its SPI
port. If VREF is equal to 4.096V, the LSB tentiometer. If VREF is 4.096V, you can in 0.2%. Given the size of the voltage
at the outputs of IC4A and IC4B is 16 mV. program IC3A and IC3B such that the out- across the third digital potentiometer,
To make this circuit perform as a 16- put difference of op amps IC4A and IC4B the LSB of the complete circuit from left
bit DAC, a third digital potentiometer, is 16 mV. You can achieve high accuracy to right is 62.5 V (VREF/216). Table 1
IC2A, spans across the outputs of the two with this circuit by using a dual digital shows the critical device specifications
amplifiers, IC4A and IC4B. The pro- potentiometer for IC3A and IC3B. With to obtain optimum performance with
grammed setting of IC3A and IC3B sets the dual structure, the resistances of this circuit.
the voltage across this third digital po- these two devices match typically with-
TABLE 1DEVICE SPECIFICATIONS FOR OPTIMUM PERFORMANCE

Device
Digital potentiometers
(IC2, IC3) (MCP42010)
Operational amplifiers
(IC4, IC5) (MCP6022)
Number of bits
Nominal resistance
(potentiometer element)
Specification
8 bits
10 k (typical)
Differential nonlinearity
1 LSB (maximum)
Voltage-noise density
(for half the resistive element)
9 nV/Hz at 1 kHz (typical)
Input bias current (IB)
1 pA at 25C (maximum)
Input offset voltage
500 V (maximum)
Voltage-noise density
8.7 nV/Hz at 10 kHz (typical)
Purpose
Determines the overall LSB and resolution of the circuit.
Achieve better noise performance by using lower resistance
potentiometers. The trade-off for low-noise potentiometers is
higher current consumption.
Good differential linearity ensures that the circuit exhibits no
missing codes.
If the noise contribution of these devices is too high, it reduces
the possibility of achieving 16-bit, noise-free performance.
Selecting lower resistance elements can reduce the
potentiometer noise.
Higher input bias current causes a dc error across the
potentiometer. CMOS amplifiers are, therefore, good choices.
A difference in amplifier offset error between IC4A and IC4B
could compromise the differential linearity to the overall system;
50 V is considerably lower than 1 LSB in Stage 1 of the circuit.
If the noise contribution of these devices is too high, it reduces
the possibility of achieving 16-bit, noise-free performance.
Selecting lower noise amplifiers can reduce overall system noise.
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What is the circuit tracer designed to do?

What is the circuit tracer designed to do?

How does the circuit tracer work?

How does the circuit tracer work?

design

Edited by Bill Travis

Design makes handy audible circuit tracer

he circuit tracer in Figure 1 is a

Design makes handy audible

Is this the best Design Idea in this

RADIO SHACK 273-073

January 9, 2003 | edn 71

Design a visible optical link

Hot-swap structure offers improved redundancy

72 edn | January 9, 2003

causes VOUT to dip (Figure 2). Figure 2a

tive. The configuration in Figure 3 adds

74 edn | January 9, 2003

rect voltage drop across D1.2, no current

Is this the best Design Idea in this

Embedded processor directly drives LCD

76 edn | January 9, 2003

VDD VDD VDD VDD

com). Figure 4a shows a display with

11A general-purpose MC68HC908GP32 drives a two

78 edn | January 9, 2003

This modification of an LCD has only two backplanes.

Edited by Bill Travis

Fleapower flasher draws less than 50 A

January 23, 2003 | edn 75

PC-based configurable filter

This user-friendly screen helps you configure the desired filter.

IN4 IN3 IN2 IN1

IN4 IN3 IN2 IN1

IN1 IN2 IN3 IN4

76 edn | January 23, 2003

based on a two-integrator configuration, provides simultaneous

TABLE 1DATA BITS FOR Q SELECTION

log-filter section. The software

LISTING 1C PROGRAM FOR PC-CONFIGURABLE FILTER

78 edn | January 23, 2003

ding to pins D6 through D9 control

TABLE 2DATA BITS FOR CENTERFREQUENCY SELECTION

mately 150, which the design takes into

use better switches having on-resistances of approximately 35.

Is this the best Design Idea in this

Frequency source feeds entire lab

80 edn | January 23, 2003

Circuit sequences supplies for FPGAs

core and the I/O interfaces. FPGAs and

82 edn | January 23, 2003

imize the voltage difference between the

84 edn | January 23, 2003

tor that contains two 30-m MOSFETs.

Edited by Bill Travis

Oscillating output improves system security

Oscillating output improves

A dynamic-variable signal drives the output relay in this circuit.

square-wave signal of a frequency that

11A general-purpose MC68HC908GP32 drives a two