EDN Design Ideas 2002

design
ideas
Edited by Bill Travis
Log amp uses capacitor-charging law

Jayashree Raghuraman and Ajoy Raman, Aeronautical Development Establishment,
Bangalore, India
he novel logarithmic amplifier in
VCC
Figure 1 relies on the expo15V
Figure 1
nential charging characteristics of a simple RC circuit. The expression
for the time, T, required for a capacitor,
1k
C, to reach a voltage (VIN2VK) from 0V,
1
14
DIS1
when charged through a resistor, R, with
VCC
1N914C
2
6.8k
an applied voltage of VIN, is VIN2VK
13
TH1
DIS2
2T/RC
5VIN(12e
), where VK is a fixed volt12
3
CV1
TH2
age. The expression for T reduces to
11
4
0.01
RES1 LM556C CV2
0.1 mF
T5RCln(VIN/VK), clearly showing an in10
220
5
mF
OUT1
RES2
herent logarithmic characteristic. The
6
V
CC
9
TRI1
circuit in Figure 1 demonstrates this
OUT2
15V
7
8
GND
characteristic, using a 556 timer. With the
TRI2
values shown, the first stage of the 556
1k
R2
timer is a standard astable circuit operDC
ating at a frequency of approximately 1
100k
kHz. The output of this stage acts as the
trigger for the second stage. The second
stage operates as a modified monostable
circuit. In this modified configuration,
the RC combination, R1 and C1, charges A simple 556 timer depends on RC charging to form a logarithmic amplifier.
from an external voltage, VIN, instead of
VCC. The control-voltage pin, CV2, has
the value VIN minus one diode
LINEAR FIT OF
Figure 2
7
EXPERIMENTAL DATA
drop, VK.
The monostable pulse width, T, then
6.5
depends on the time required for capac6
itor C1 to charge to VIN 2VK through R1
INPUT
VOLTAGE
R1
9.1k
C1
0.02 mF
OUTPUT
VOLTAGE
C2
1 mF
5.5
Log amp uses capacitorcharging law....................................................71
OUTPUT VOLTAGE (V)
5
4.5
EXPERIMENTAL DATA
Extend the timing capabilities of a PC ......72
Optocoupler simplifies
power-line monitoring ..................................76
3.5
Improved amplifier drives

differential-input ADCs..................................80
Circuit forms dc-motor switch
with brake ........................................................82
3
2.5
2
10
20
INPUT VOLTAGE (V)
The circuit of Figure 1 produces a distinct logarithmic output.

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January 10, 2002 | edn 71
design
ideas
with the applied voltage VIN.

The output of the second stage,
filtered through R2 and C2, depends on the first stages
astable frequency; the supply
voltage, VCC; and the monostable pulse width, T. Because
VCC and the astable frequency
are constant, VOUT is proportional to T. Table 1 tabulates
the experimental results, and
Figure 2 shows graphical results. The circuit operation is
limited to an input range of 2.5
TABLE 1OUTPUT VERSUS INPUT VOLTAGE

Input voltage Output voltage Input voltage
2.5
3.324
8
3
3.667
8.5
3.5
3.954
9
4
4.227
9.5
4.5
4.506
10
5
4.705
10.5
5.5
4.956
11
6
5.151
11.5
6.5
5.315
12
7
5.444
12.5
7.5
5.615
13
Output voltage
5.782
5.861
5.886
5.945
6.098
6.187
6.204
6.312
6.371
6.378
6.476
to 13V to satisfy the internal biasing requirements of the second stage of the 556. The diode
drop,VK, is not strictly constant,
because it varies with current.
In spite of these limitations,
Table 1 and Figure 2 clearly
show a distinct logarithmic
characteristic.
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Extend the timing capabilities of a PC

Martin Connors, Athabasca University, Athabasca, AB, Canada
ven when you use the internal timing registers and under DOS,
Figure 1
4
a PC cannot easily measure
time intervals with better time resolution
than a millisecond. Measuring long in100k
500
tervals with even this precision is a waste
10
3
1 A2
A1 18
of many CPU cycles. A microcontroller is
11
LD271
well-suited for this task; you can easily inC
2 A3
A0 17
LED
tegrate a PIC with a PC to extend the tim22 pF
OPT805SL
3 A4
OSC1 16
ing precision into the microsecond range
E
22 pF
for periods from tens of microseconds to
5
4 MCLR
OSC2 15
more than 24 hours. The flash-program4.0000 MHz
mable PIC16F84 microcontroller from
6
5 VSS
VDD 14
Microchip Technology (www.micro
chip.com) is an inexpensive and widely
B
C OPT805SL
BOTTOM
used device. The precision timer in FigVIEW
PIC16F84
E
ure 1 requires only the IC, two capacitors,
18 TO 25V
and a crystal and accepts direct input of
timing data to a PC via the parallel port.
The PIC16F84 draws only 2 mA and can
operate from an output pin in the parallel port without a battery. You can as- This zero-power photogate allows you to use a PC to generate precise timing intervals.
semble the circuit on a small pc board
with a male DB-25 connector glued or two basic parts. The first part waits for a crystal, most instructions take 1 msec, so
soldered to one end for connection to the signal and starts a loop that checks the the timing loop is 5 msec long. You can
parallel port, LPT1. In this example, the continuing presence of the signal and in- run newer PIC16F84s with a 20-MHz
timing signal occurs when you block a crements 32 timing bits while the signal clock, so, in principle, the timing loop can
photogate comprising a paired LED and is present. The second part transmits 32 be 1 msec long. Port A of the PIC serves
a phototransistor.
bits of timing information to an external for the timing signal on bit 3 and for
Listing 1 represents the timing appli- device, using one data-output line and communication. A minor coding change
cation implemented, which comprises two handshaking lines. With a 4-MHz allows you to use positive or negative log-
72 edn | January 10, 2002
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ideas
ic levels. If the timing signal is present at

the start of the program, an error flag
arises, with an output of 4 bytes of 0xFF.
A similar error occurs if the signal is present long enough (roughly a day) to cause
overflow of the counter. DATO (data output) occurs through bit 0. The routine
uses two handshake lines: VALID on bit
1 from the PIC to signal the presence of
valid data on the DATO line and SEND
from the PC to bit 2, signifying that the
PC is ready to receive data. This robust
transmission method does not depend
on timing characteristics in a critical way.
Listing 2 (pg 76) shows sample C code
for Borland Turbo C for DOS with a simple timing conversion that doesnt take
account of the overhead of byte overflow.

After the PIC times an event, it waits for
the PC to signal that it wants to download data. The transmission protocol for
transmitting 1 bit of data is as follows: PC
SEND is low, and the PIC polls it. PIC
VALID is initially low; the PC raises
SEND and polls VALID. In response, the
PIC puts DATA on the line. The PIC than
raises VALID and polls SEND; in response, the PC reads DATA. The PC then
lowers SEND, and the PIC lowers VALID.
This operation repeats for 32 bits, starting with the lowest bit of the lowest byte
and proceeding to the highest bit of the
highest (fourth) byte. Although this
transmission method is inefficient, it is
robust, and the polling timing is unimportant. The efficiency matters little, because the method involves little data
transfer. By referring to the listings, you
can step through the process to see how
the transfer takes place. Listing 2 includes a test routine that allows you to
supply a signal from the PC to test the
circuits operation. You can download
listings 1 and 2 from the Web version of
this article at EDNs Web site, www.edn
mag.com.
Is this the best Design Idea in this

issue? Vote at www.ednmag.com.
LISTING 1ZERO-POWER PHOTOGATE-ASSEMBLY PROGRAM
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LISTING 2PHOTOGATE-SUPPORT PROGRAM
Optocoupler simplifies power-line monitoring

Alfredo del Rio and Ana Cao y Paz, University of Vigo, Spain
he use of a linear optocoupler
Resistor R adds a dc offset curTABLE 1OUTPUT OFFSET-VOLTAGE DRIFT rent to allow2for both polarities in
and a capacitor-based power
TIL300 (88C)
VOUT (V)
TIL300 (88C)
VOUT (V)
supply yields a simple, yet preVIN. The match between the two
17.5
2.496
37.5
2.506
photodiodes in the IL300, IC2, encise power-line-monitoring system.
20
2.497
40
2.507
sures that IP2 is closely proportionThe circuit in Figure 1 converts the
22.5
2.498
42.5
2.509
al to IP1. The output stage converts
110V-ac power-line voltage to an ac
25
2.5
45
2.51
IP2 to a voltage level isolated from
output voltage centered at 2.5V, cov27.5
2.501
47.5
2.512
the power line. Variable resistor
ering 0 to 5V. The circuit isolates the
30
2.503
50
2.513
VR2 trims the overall gain, and VR1
output signal from the power line.
32.5
2.504
52.5
2.515
adjusts the output-voltage offset,
You can connect the output directly
35
2.505
which is nominally 2.5V. You can
to an A/D converter. For other powtest this circuit using simulation
er-line voltages, simply change the
value of R1. For a power-line voltage of vides a stabilized 5V-dc voltage and a the model in Listing 1 for IC2. Typical
220V ac, use a value of 470 kV for R1. The 3.3V dc reference. The TLC2272 op amp, values for K1 and K2 (optical transfer rainput stage is a nonisolated block that IC1, and the TLC2272 linear optocoupler, tios) are approximately 0.007. The globuses the neutral line as a ground refer- IC3, form a feedback amplifier in which al optical transfer ratio is K35K2/K1. Afence. This block receives power from a the IP1 current is proportional to the inter performing the simulation, you can
build and test a prototype. The power
capacitor-based power supply that pro- put voltage, VIN.
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ideas
supply for the isolated block provides 5V

dc and a 3.3V reference from an
Figure 2
available voltage of 7 to 10V. You
ADC
IMONITOR
do not need the regulated 5V if that voltDATA-PROCESSING
OUTPUT
110V AC
age is already available in your system.
SYSTEM
VMONITOR
ADC
An important goal in this design is to
obtain a stable dc voltage at the output.
This property is crucial for dc measurements of VIN. Even if you suppose the ac By adding two ADCs and a microcontroller, you can measure power-line voltage and current
power line to be free of dc voltage, some parameters.
types of loads drain dc currents, thereby
introducing a small dc voltage because of
verter, one LSB is equivalent to 0.5V in
LISTING 1SIMULATION MODEL
voltage drops in the ac lines. Thermal
the 110V power line. You can add a Halldrifts in the output voltage stem princieffect sensor to the circuit for current
pally from drifts in K3. In tests of the promeasurements. The LTS series from LEM
totype, the K3 temperature coefficient
(www.lemusa.com) is suitable for this
was 470 ppm/8C. Table 1 shows VOUT at
purpose, because these devices operate
different temperatures. The TLC2272 op
from a single 5V supply and provide a
amp has rail-to-rail output, yielding a
2.5V-centered output. Figure 2 shows a
wide output-voltage range, and low quisystem that integrates voltage and curescent current, simplifying the capacitor- block, IC1, cannot be halves of the same rent measurements. The processor combased power supply. Because the chip; otherwise, youd lose the isolation. putes true-rms voltages and currents, apThe main specifications of the circuit parent and active power, and power
TLC2272 is a dual device, you can connect the unused half as a voltage follow- are 5300V-ac-rms galvanic isolation, factor.
er. When you monitor a three-phase 0.08% linearity, 470-ppm/8C thermal
power line, youd use one and one-half shifts in VOUT, 28 phase shift at 50 Hz, and
TLC2272s. Note that the op amps in the dc to 1-kHz bandwidth at 23 dB. If you Is this the best Design Idea in this
isolated block, IC3, and the nonisolated connect the output to a 10-bit A/D con- issue? Vote at www.ednmag.com.
IC4
5V
100 470 pF
1 kV
IC5
3.3V
47 mF
47 mF
9.1V
100 mF
VR1
3
470k
1k
IC1
4
IF
1
2
IC2
IC7
3.3V
330 mF
+
2
R2
330k
R1
240k
IC6
5V
7 TO 10V
DC
33 mF
VR2
350k
500k
3 +
8
1
IC3
VIN
110V AC
2.4k
100 pF
IP1
1k
Figure 1
NONISOLATED BLOCK
47 mF
VOUT
IP2
ISOLATED BLOCK
NOTES:
IC1 AND IC3=TLC2272.
IC2=IL300.
IC4 AND IC6=TC55 RP 500201.
IC5 AND IC7=TC55 RP 330291.
An isolated optocoupler circuit allows you to make dc measurements of the power-line voltage.
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Improved amplifier drives differential-input ADCs

Stephan Goldstein, Analog Devices, Wilmington, MA
tors. Furthermore, the comDCs with differential
mon-mode reference input
inputs are be+
+IN
Figure 1
could require several milcoming increas2
liamperes of drive, depending
ingly popular. This popularion the resistor values and
ty isnt surprising, because
REF
voltages involved. However,
differential inputs in the ADC
RF
+
the circuit does the job, and
offer several advantages: good
RG
VOUT
you can build it by using a
common-mode noise rejec2
RF
high-quality quad op amp
tion, a doubling of the availand a handful of resistors.
able dynamic range without
Figure 2b shows a more effidoubling the supply voltage,
2
2RF
cient and elegant approach,
and cancellation of even-orGAIN=1+
RG
+
2IN
using only the four resistors
der harmonics that accrue
required in the original outwith a single-ended input.
put stage. In this circuit, a
But the differential input The classic three-op-amp instrumentation amplifier does not provide difmodern, fully differential op
structure doesnt eliminate ferential outputs.
amp, such as the AD8138, rethe frequent need for additional gain between the signal source and reference terminal), so its a poor match places IC3 and IC4 in Figure 2a. The amplifiers two outputs swing symmetricalthe ADC. A frequently used gain stage is for a differential-input ADC.
the classic, three-op-amp instrumentaFigure 2 shows two easy ways to cre- ly about its high-impedance, commontion amplifier (Figure 1). This popular ate a differential-input instrumentation mode reference input. The differential
circuit offers excellent common-mode amplifier. In Figure 2a, IC4 and its asso- outputs provide a clean, simple interface
rejection and high input impedance. The ciated feedback resistors are connected in to a differential-input ADC.
circuit also has an output-reference parallel with the original output ampli(ground-sense) terminal, allowing you to fier but with inverted polarity relative to
reference the output voltage to a voltage the original circuit. The two outputs toother than ground. However, this circuit gether provide the desired function, but Is this the best Design Idea in this
has a single-ended output (relative to the the circuit requires many matched resis- issue? Vote at www.ednmag.com.
Figure 2
2
IC3
+
AD8021
+IN
+
IC1
2
+IN
2
2VOUT
2VOUT
RF
RF
RG
REF
RG
REF
AD8138
2
+
RF
RF
2IN
2
IC2
+
4RF
GAIN=2+
RG
+
IC4
2
AD8021
2
2IN
(a)
+VOUT
+VOUT
GAIN=2+
4RF
RG
(b)
The four-op-amp instrumentation amplifier (a) provides differential outputs but requires many matched resistors. A differential-output op amp (b)
reduces the IC count in Figure 2a to three.
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Circuit forms dc-motor switch with brake

JB Guiot, DCS AG, Allschwil, Switzerland
ontrolling a small dc motor
VCC
without speed control sounds like a
S1
trivial task; a switch or a relay
D2
Q1
R1
should suffice. However, several problems accompany this approach.
A
Figure 1
For one, the switch, because of
D1
R2
the inductive load and the low starting reQ2
MOTOR
sistance of the motor, tends to wear out
prematurely (with all the related sparks
D3
R3
and EMI problems). Second, when you
cut the power, the motor continues to rotate for a certain time, depending on its This circuit provides both motor-drive and
initial speed and inertia. The circuit in braking functions.
Figure 1 can be useful for designs that
dont need precise control of speed and circuit. This circuit is similar to the outstopping position but can benefit from put circuit of TTL gates. D3 protects Q2
enhanced deceleration. The circuit com- from inductive surges. When S1 closes, Q1
prises two parts. Q1 plays the role of the turns on, and the voltage at Point A goes
switch. D2 protects Q2 against inductive high (near VCC). The voltage at the base
surges. Resistor R2 keeps Q1 off as long as of Q2 is higher than the voltage at the
switch S1 is open. R1 limits the base cur- emitter, because of the voltage drop in D1.
rent of Q1 when S1 is closed. S1 can be a If you open S1 while the motor is runmanual switch, a relay contact, an opto- ning, Q1 turns off. The voltage at Point A
coupler, or a transistor. If you close S1, Q1 is near zero. The self-induced, back-EMF
turns on, and the motor runs.
voltage from the motor sees a short cirQ2, D1, and R3 constitute the braking cuit in Q2, whose emitter is more positive
than its base and thus conducts. Shortcircuiting the motor results in braking it.
The higher the speed of the motor, the
stronger the braking effect.
You should mount the circuit of Q2 as
near as possible to the motor to reduce
the series resistance of the wiring. This
parasitic resistance limits the braking
current and, thus, the deceleration. The
circuit of Q1 can be remote. The dividing line between the two circuits is at
Point A. This design mounts the circuit
on the tool-changer motors of small machine tools, and it has worked perfectly
for years. The values of the components
are not critical. The transistors should
preferably be Darlington pairs and, like
the diodes, should be types commensurate with the power-supply voltage and
the motor current. (Also, dont forget the
high inductance of the motor.) The components in Figure 1, for example, are
suitable for a 24V, 3.5A motor.
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Autoreferencing circuit nulls out sensor errors

Chuck Wojslaw, Catalyst Semiconductor, Sunnyvale, CA
he autoreferencing circuit in Fig- 0.95VmVSENSEm1.05V. The 100-mV, 200- memory, first make OSC low and then
ure 1 nulls out the error of a sensor, mV, and 1V references for the circuit bring CS from low to high. If power dissuch as a pressure transducer, at its come from a 2.5V reference, stepped appears and is later restored, the potenreference levelfor example, at ambient down by a resistive divider and buffered tiometer goes to the corrected value
pressure. The circuit is an analog-digital- by voltage followers. IC2A implements a stored in nonvolatile memory. The measfeedback control system that uses a digi- square-wave oscillator whose frequency ured error in the system is less than 1 mV,
tally programmable potentiometer to is approximately equal to 1/RCin this but better performing amplifiers, a highprovide the variability. The circuit in Fig- case, 10 kHz. You program the autoref- er resolution potentiometer, and more
ure 1 is designed to accommodate a pres- erencing circuit using the logic-input sig- accurate resistors can reduce the error to
sure transducer with a nominal 1V650- nals OSC and CS. The circuit becomes the low-microvolt region. This circuit
mV output at ambient pressure and disabled when OSC is low and CS is high. uses three ICs and a handful of discrete
provide a voltage of 1V61 mV. Amplifi- When the circuit is disabled, VOUT is at its parts and is an alternative, low-cost aper IC1A is a summing/difference circuit last corrected value.
proach to more complex autoreferencing
whose inputs are the sensors output voltThe circuit becomes enabled and cor- circuits using DACs, ADCs, and microage, VSENSE; a voltage shift, VSHIFT, of 100 rects the output voltage for a new sensor processors.
mV; and a correction voltage, VCORR. IC1B or different set of conditions when OSC
functions as a comparator, comparing is high and CS is low. To store the curthe output voltage of the summing am- rent wiper setting of the digitally pro- Is this the best Design Idea in this
plifier with the ideal output voltage of the grammable potentiometer in nonvolatile issue? Vote at www.ednmag.com.
sensor, 1V. The logic output of the comparator sets the direction for inVREF
6
2
Figure 1
1V
crementing or decrementing the
IC2A
IC
7
1B
1 74HC 132
2M6064
potentiometers wiper, whose buffered
4
5
+
OSC
20k
wiper voltage provides the correction
5V
voltage, VCORR.
10k
200 mV
The potentiometer is a Catalyst 30-tap
digitally programmable potentiometer
U/O
0.01 mF
+
499k
VCORR 499k
INC
with an increment/decrement interface.
2
5V
CS
The correction voltage varies from 0
CS
2
to 200 mV and subtracts from the shift4
2
5V
ed sensor voltage. Mathematically,
CAT 5112
IC1A
1
VOUT
2M6064
IC2
1V51 mV
VOUT5(VSENSE 1VSHIFT)2VCORR, where
3
2.49k
+
11
0mVCORRm 200 mV, VSHIFT5100 mV, and
SENSOR
Autoreferencing circuit
nulls out sensor errors ..................................85
Low-power keypad
consumes only 100 nA..................................86
Time-tag impulses
with zero-crossing circuit ..............................88
Circuit provides reference
for multiple ADCs ..........................................92
LM4040
1.5V
15V
30.1k
499k
499k
VSENSE
1V550 mV
1V
15.8k
VSHIFT
100 mV
2M6064
200 mV
2k
+
IC1C
2
100 mV
2k
+
IC1D
2
Publish your Design Idea in EDN. See the

Whats Up section at www.ednmag.com.
This autoreferencing circuit nulls out output errors at a sensors reference (ambient) condition.
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January 2 4, 2002 | edn 85
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ideas
Low-power keypad consumes only 100 nA

Mike Mitchell, Texas Instruments, Dallas, TX
ften in the use of products with
keypads, one or more keys become
stuck or are being pressed. For example, a cell phone in the bottom of a
purse or in a hip pocket could have one
or more of its keys inadvertently pressed
and held down for a considerable period.
Depending on the circuit design and implementation of the keypad interface, this
condition could cause excess current to
flow, thereby draining the batteries in
portable equipment. The circuit in Figure 1 is a keypad interface that solves this
problem by using an ultralow-power microcontroller. The circuit typically consumes 100 nA while awaiting a key press
and consumes a maximum of only 2 mA
if all keys are stuck or held down. An
added bonus of the circuit is that it requires no crystal.
The circuit uses the MSP430, IC1, because it offers low power consumption,
individually configurable I/O pins with
interrupt on rising or falling edges, and

wake-up time of less than 6 msec. In normal mode, port pins P3.0 to P3.3 drive
the rows high. The columns connect to
port pins P1.0 to P1.2, configured as inputs with interrupts enabled and set to
interrupt on a rising edge. The pulldown
resistors hold the inputs low in the inactive state. The MSP430 then goes into
low-power Mode 4, in which the microcontroller draws 100 nA. This state continues indefinitely until you depress a key.
The circuit is completely interrupt-driven with no need for polling. When you
depress a key, the column associated with
that key receives a rising edge, thereby
waking the MSP430. The timer for the
delay uses the internal digitally controlled
oscillator of the MSP430, an RC-type oscillator. The digitally controlled oscillator
is subject to tolerances, so you use a debounce delay to yield a worst-case minimum delay of 25 msec. That figure trans-
VCC
1
100k
Figure 1
TEST
P1.7/TA2/TDO/TDI
2 V
P1.6/TA1/TDI
CC
3 P2.5/R
P1.5TA0/TMS
OSC
4 V
P1.4/SMCLK/TCK
SS
5 XOUT
P1.3/TA2
6 XIN
P1.2/TA1
IC
7
1
P1.1/TA0
RST/NMI
8 P2.0ACLK
P1.0/TACLK
9 P2.1INCLK
P2.4/CA1/TA2
10
P2.2/CAOUT/TA0 P2.3/CA0/TA1
11
P3.0/STE0
P3.7
12
P3.1/SIMO0
P3.6
13 P3.2/SOMI0
P3.5/URXD0
14
P3.3/UCLK0
P3.4/UTXD0
28
27
26
25
24
23
22
21
20
19
18
17
16
15
4.7M
324-KEY KEYPAD
1N4148
1N4148
1N4148
1N4148
This keypad interface draws only 100 nA in standby mode and avoids stuck-key problems.
86 edn | January 2 4, 2002
4.7M
lates to a worst-case maximum delay of

approximately 86 msec and a typical delay of approximately 40 msec. This range
is eminently usable for keypad-debouncing purposes. After the debounce delay,
the circuit scans the keypad to determine
which key you depressed.
After you depress a key, the MSP430
goes into a wait-for-release mode, in
which it drives only the necessary row for
the key you depressed. (Other rows
switch low.) The microcontroller reconfigures the P1.x I/O to interrupt on a
falling edge, and it again goes into lowpower Mode 4 and waits for the release of
the key. Again, the circuit needs no
polling at this point. The detection of the
key release is completely interrupt-driven, allowing the MSP430 to stay asleep
while the key is held, thereby reducing
current consumption. Once you release
the key, the circuit again executes the debounce-delay routine. After the debounce delay, the circuit again
scans the keypad to determine
whether any other keys are being held. If so, the wait-for-release mode continues. When all
the keys are released, the
MSP430 reverts to wait-forpress mode. During the waitfor release mode, only one row
of the keypad goes high, thereby
limiting the maximum current
consumption to the condition
in which all three keys on a sin4.7M
gle row are pressed. For a 3V system, this condition equates to
approximately 2 mA. Any other
key press does not result in increased current consumption,
because the corresponding row
is not in a high state. You can
download the software for the
microcontroller from the Web
version of this article at
www.ednmag.com.
Is this the best Design Idea
in this issue? Vote at www.
ednmag.com.
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Time-tag impulses with zero-crossing circuit

Elio Rossi, Itesre-CNR, Bologna, Italy
constant-fraction discriminator usually performs the time-tag0.2V, 5 mSEC
ging of impulsive events, which
have a peaking time of the signal ampli20 mVRMS
tude. The implementation of
Figure 1
this technique requires a delay in the input signal of approximately
the same amount as the signals rise
time. You can attain this delay by using
0.1V, 5 mSEC
a coaxial cable of an appropriate length.
For many applications, in which the rise
time for impulsive events is 1 to 10 msec,
you must consider alternative solutions,
because of the length of the cable youd
require. Figure 1 shows the typical output from a spectroscopic amplifier, A spectroscopic amplifier produces differentiated signals (lower traces) in response to input
where the presence of a large amount of impulses (upper traces).
detector noise with Gaussian distribution is a limiting factor for system per- the walking time arising from the am- noise around the zero-crossing line.
formance in amplitude and timing res- plitude variation of the signals. You can
In Figure 2, an arming discriminator
olution. The time-tagging of such pulses eliminate the walking time by differen- with a fixed threshold of 100 mV
is subject to two well-known types of er- tiating the signal and detecting the zero (53VRMS(NOISE)) enables the IC1, a MAXrors: the jitter related to the noise and crossings. The jitter is related to the 941 zero-crossing discriminator, via the
330 pF
Figure 2
0.1 mF
+
47k
10k
5 +
3.3k
23V
0.1 mF
10k
10k
2
IC3A
2
1
2 MAX942
1k
100 pF
33k
C2
18k
10k
10 mF 5V, 1 mA
CI
2T
1
CX
RC
7
Q
IC2A
1
2 HC4538
+T
10k
0.1V
1k
10k
2 MAX942
+
1
IC3B
2
2
4
16
0.1 mF 1N4148
13
+
C1
0 TO 10V
1k
11
4
3 2
1
IC1
7
2 MAX941
5
+
6
1k
15
14
0.1 mF
INPUT
100 pF
5.6k
12
0.1 mF
RC
CX
CI
2T
IC2B
1
2 HC4538
+T
Q
Q
DIGITAL
OUTPUT
9
10
0.5 mSEC
8
ENABLE/LATCH
A discriminator and a zero-crossing detector eliminates walking-time error for impulsive events.
88 edn | January 2 4, 2002
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design
ideas
first half of IC2, an HC4538 resettable monostable multivibrator.

Figure 3
The propagation delay in these
ICs allows enabling the zero-crossing discriminator when the differentiated signal
is well over the baseline noise for the full
range of the input signal. The positivegoing output pulse from IC3, a MAX941,
corresponding to the zero-crossing time,
reaches the output with a fixed length of
0.5 msec, set by the second monostable For 200-mV input, Trace A is the output from the arming discriminator, Trace 1 is the Enable signal
multivibrator. This second multivibrator for the MAX941, and Trace 2 is the signal output.
resets the first and latches the MAX941 at
the high output level until a new
Figure 4
trigger arrives from the arming
discriminator. In this way, you avoid spurious triggers at the beginnings and ends
of input pulses. The upper-threshold discriminator output, with a minimum output length of 5 msec, serves to veto the
0.5-msec output and works even for highly saturated input signals. Because of the
input configuration of the MAX942, it is For a 10V input, Trace A is the output from the lower level discriminator, Trace 1 is the Enable signecessary to reduce the upper threshold nal for the MAX941, and Trace 2 is the output from the upper level discriminator.
level to less than 2.8V. Figures 3 and 4
show the timing sequences for 0.2V and
6000
10V input signals, respectively.
Figure 5
SHAPING TIME: 3 mSEC
You can obtain the same results
5000
9.915 nSEC/CHANNEL
using many different implementations of
the circuit, depending on the ICs avail4000
able off the shelf. For example, you can
substitute the MAX941 with a common
COUNT 3000
discriminator and a CMOS analog
2000
switch to commutate the threshold from
IN 1V
a positive voltage to ground. A single flipIN 0.5V
1000
flop then completes the circuit. This deIN 0.2V
sign uses an amplification stage with
0
back-to-back limiting diodes in front of
700
800
900
1000
1100
1200
the zero-crossing discriminator. Table 1
CHANNEL
shows the results, with comparisons to
the shaping-time value of 3 msec. You These jitter histograms are for input signals of 0.2, 0.5, and 1V.
measure the walking time and jitter using a pulse generator, preamplifier, shap- 5 shows just three of the many his- Is this the best Design Idea in this
ing amplifier, time-to-amplitude con- tograms used to calculate the walking issue? Vote at www.ednmag.com.
verter, and multichannel analyzer. Figure time and jitter results.
TABLE 1MEASUREMENT RESULTS AT 1 kHz AND WITH 20 mV RMS OF NOISE

Shaping
time
msec)
(m
1
3
6
3
Peak
time
msec)
(m
2
6
12
6
C1
(nF)
0.47
1
2.2
1
90 edn | January 2 4, 2002
C2
(nF)
0.33
1
2.2
1
Jitter
s (m
msec)
s (m
msec)
s (m
msec)
Amplifier
0.1VIN1
0.249
0.594
1.608
0.664
0.2VIN
0.145
0.395
0.939
0.417
0.5VIN
0.06
0.156
0.372
0.161
1VIN
0.029
0.081
0.195
0.081
2VIN
0.015
0.042
0.096
0.042
5VIN
0.009
0.017
0.04
0.017
10VIN
0.006
0.009
0.021
0.009
Walk
0.06 msec
0.2 msec2
1.1 msec2
0.47 msec3
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Circuit provides reference for multiple ADCs

Ron Gatzke and Tanja Hofner, Maxim Integrated Products, Sunnyvale, CA
he achievable accuracy for systems with multiple ADCs depends
directly on the reference voltages applied to the ADCs. Medical-ultrasoundimaging systems, for example, commonly include a large number of ADCs in the
systems beam-former electronics, with
the ADCs usually organized in groups of
16, 24, 32, and so on. To obtain maximum
beam accuracy, you must minimize errors in the ADC path. Poor accuracy of
the reference voltages of the individual
ADCs degrades the overall system accuracy. Another source of degradation is the
distributed load, which comprises many
individual resistive and capacitive loads.
Several approaches are available to provide the reference voltage for such ADC
arrays:
Individual on-chip references.
Though this approach offers a convenient local connection to each
ADC, it can result in relatively poor
matching among the converters.

A single external reference voltage
applied to all ADC reference inputs.
Such a configuration allows you to
engineer an external reference voltage of arbitrary accuracy but incurs
errors from the small variations
among the internal ladders of the
ADCs.
An external reference directly driving the ADCs reference-ladder taps.
This option delivers maximum gain
accuracy by directly controlling the
reference voltage applied to each
ADC ladder. However, it requires
driving the relatively low resistance
of the ladders. Moreover, some
ADCs do not allow access to that internal bias point.
ADC ACCURACY
In many applications, gain and noise
level have a major effect on ADC accu-
racy. The gain of an ADC is in effect the

slope of its transfer function, which relates analog inputs to the allowable range
of digital-output codes. One way to
quantify gain is to measure the full-scale
input range, which is a direct function of
the reference-voltage level. For medicalultrasound-imaging systems, variations
in the full-scale ranges of the ADCs can
cause errors in beam formation. The
variations also affect the ADCs clipping
pointan effect that may be important
is certain signal-demodulation schemes.
An ADCs noise level determines its usable dynamic range. This dynamic range
should be as great as possible. The reference-noise component of ADC noise can
be additive or multiplicative. Local bypass capacitors on the individual ADCs
can easily filter additive noise. Multiplicative noise, on the other hand, is more
insidious. For ultrasound applications,
reference noise in the audio-frequency
3V
0.1 mF
2.048V
3V
NC
29
REFOUT
31
0.1 mF
32
0.1 mF
1
1
IC1
3
REFIN
REFP
ADC 1
REFN
2
2
16.2k
1 mF
10-Hz LOWPASS
FILTER
3
4
IC2
2
COM
162
0.1 mF
0.1 mF
0.1 mF
100 mF
0.1 mF
10-Hz LOWPASS
FILTER
2.2 mF
10V
Figure 1
NC
29
REFOUT
31
32
0.1 mF
1
2
0.1 mF
0.1 mF
REFIN
REFP
ADC N
REFN
COM
0.1 mF
For ultrasound applications, a single, low-noise reference circuit can drive as many as 1000 ADCs.
92 edn | January 2 4, 2002
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design
ideas
spectrum can modulate large stationary signals in the RF spectrum. Such signals arise from stationary tissue in the ultrasound target.
Audio modulation produces sidebands
in the RF signal that a Doppler detector
can demodulate, producing audio tones.
To estimate the amount of audio noise
tolerable in an ultrasound application,
assume a nearly full-scale RF signal applied to a 10-bit ADC such as the
MAX1448. The devices dynamic range of
almost 60 dB equates to a noise floor of
260 dBFS (relative to full scale). You can
normalize that noise level to a 1-Hz
bandwidth. The Nyquist bandwidth for
an 80-MHz sampling rate is 40 MHz. The
correction factor is =40 MHz576 dB,
which places the ADCs noise floor at
260 dBFS276 dBFS52136 dBFS. Because a conservative design requires the
reference-voltage noise to be at least 20
dB lower (2156 dBFS), a 2V reference requires an extremely low noise level of 33

nV p-p (approximately 8 nV/=Hz).
A multiple-ADC array may require a
more accurate reference voltage than the
one internal to each converter. The reference voltage internal to MAX144x converters, for example, has an accuracy of
61%. The following two circuits are reference designs for such arrays. They feature a single, common low-frequency
noise filter, and they offer high-frequency noise suppression via local decoupling
capacitors connected to individual
ADCs.
and thus eliminate the need for any circuit modification. Moreover, the high
input impedance of REFIN (even of
multiple REFIN terminals connected in
parallel) results in only a small load-current drain. Figure 1 shows a precision
source, such as the MAX6062, that generates an external dc level of 2.048V and
exhibits a noise-voltage density of 150
nV/=Hz. The output of the IC passes
through a one-pole lowpass filter
with 10-Hz cutoff frequency to op amp
IC2, which buffers the reference. The
buffered reference voltage then passes
through a second 10-Hz lowpass filter.
IC2 exhibits a low offset voltage for high
gain accuracy and a low noise level. The
passive 10-Hz filter following the buffer
attenuates noise produced in the voltage-reference IC and buffer stage. The
filtered noise density, which decreases
with frequency, meets the noise levels re-
SINGLE EXTERNAL REFERENCE

Multiple-converter systems based on
the MAX144x family are well-suited for
use with a common reference voltage.
You can the REFIN pin of these converters to an external reference source
3V
0.1 mF
29
NC
31
IC1
32
2V AT 8 mA
2 21.5k
3 +
2
1
1
IC2A
2
47
2
11
10 mF
6V
1.47k
21.5k
Figure 2
REFIN
ADC 1
3V
2V
REFOUT
REFP
REFN
COM
330 mF
6V
0.1 mF
0.1 mF
0.1 mF
3V
1.5V
0.1 mF
1.5V AT 0 mA
5
6
1 mF
4
+
IC2B
2
11
47
10 mF
6V
1.47k
21.5k
330 mF
6V
NC
3V
3V
1V
0.1 mF
10
21.5k
21.5k
2.2 mF
10V
31
1V AT 28 mA
4
+
IC2C
2
29
11
REFIN
ADC 2
47
10 mF
6V
1.47k
REFOUT
32
1
330 mF
6V
2
0.1 mF
0.1 mF
REFP
REFN
COM
0.1 mF
For ultrasound applications, a precision, low-noise reference circuit can drive as many as 32 ADCs.
94 edn | January 2 4, 2002
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design
ideas
quired for precision-ADC operation.

Converters of the MAX144x family
specify a typical gain error of 64.4%
(better than 60.5 dB). This performance
is better than the gain tolerance of all
other building blocks in the signal path
of an ultrasound receiver. Note that the
circuit in Figure 1 ensures proper power-up/power-down sequencing, because
all active parts receive their power from
the same supply-voltage rail. This approach yields excellent gain matching
and an extremely low noise level with
minimal circuitry. The circuit should
prove adequate in many applications
that require multiple gain-matched
ADCs.
PRECISION EXTERNAL REFERENCE
For applications requiring more stringent gain matching, the MAX144x family fills the bill. In Figure 2, connecting
each REFIN to analog ground disables
the internal reference of each device. You
can thus directly drive the internal refer-
96 edn | January 2 4, 2002
ence ladders from a set of external reference sources. These voltages can have an
arbitrarily tight tolerance; the ADCs typically track them within 0.1%. ADCs of
this family have 4-kV resistance across
the ladders reference connection, so its
easy for the reference source to drive the
load, even with many ADCs connected in
parallel. IC1 generates a dc level of
2.500V, followed by a 10-Hz lowpass filter and a precision voltage divider. The
buffered outputs of this divider provide
2, 1.5, and 1V, with an accuracy that depends on the tolerances of the divider resistors. The quad op amp IC2, selected for
its low noise and dc offset, buffers the
three voltages.
The individual voltage followers connect to 10-Hz lowpass filters, which filter
both the reference-voltage and bufferamplifier noise to a level of 3 nV/=Hz.
The 2 and 1V reference voltages set the
differential full-scale range of the associated ADCs at 2V p-p. The 2 and 1V
buffers drive the ADCs internal ladder
resistances between them. The load is 4

kV divided by the number of ADCs in
the circuit. As an example, 32 ADCs draw
8 mA from the supplies, a load current
that is well within the capability of IC2.
The gain accuracy of the configuration in
Figure 2 can be almost arbitrarily tight,
depending on the accuracy grade of IC1
and the tolerances of the resistors in the
voltage divider. The gain matching of the
ADCs in such a configuration is typically 0.1%. With a noise level below 3
nV/=Hz at 100 Hz, this circuit provides
exemplary performance. As in Figure 1,
the common power supply for all active
components removes any concern about
power-supply sequencing.

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Motor-control scheme yields

four positions with two outputs
Jean-Bernard Guiot, DCS AG, Allschwil, Switzerland
igure 1 shows how to position a
mechanical device into four discrete
positions but with only two free outputs and one free input from the control
system. The position depends on a set of

cams and four corresponding limit
switches. The 24V-dc motor comes with
a worm gear. Darlington transistors Q3 to
Q6 and resistors R7 to R12 form an Hbridge that drives the dc motor, M.
Diodes D3 to D6 protect these transistors
from inductive spikes. The outputs of the
controller (not shown), connected to the
Control 1 and Control 2 inputs, have
open-collector structures that connect
Control 1, Control 2, or both to ground
upon activation. If you activate neither
Control 1 nor Control 2, Q3 and Q5 conduct, receiving base current through R7
and D1 and R10 and D2, respectively. This
action short-circuits (brakes) the motor.
In this case, Q4 and Q6 are turned off. Optocouplers IC1 and IC2 are on, thereby
short-circuiting the limit switches, MA
and MB.
Motor-control scheme yields

four positions with two outputs ..................99
Single switch controls
digital potentiometer ..................................100
Versatile power-supply load
uses light bulbs ............................................102
Two-transistor circuit replaces IC..............104
Digital current source
is nonvolatile ................................................106
Closing the loop deepens notches ..........108
Hints and kinks for USB coding................108
Activating only one control input (for

example, Control 1), if the cam does not
push open the corresponding limit
switch, EA, causes Q3 to switch off and Q4
to switch on with R8 limiting the base
current. Thus, the motor rotates until the
cam pushes open limit switch EA (Position 1 in Figure 2). The limit switch, MA,
has no influence because optocoupler IC1
short-circuits MA when Control 2 is in a
high state. A similar, symmetrical operation occurs if you activate (ground) Control 2. In this case, the motor rotates to
push open limit switch EB (Position 4).
To bring the motor to one of the middle
positionssay, Position 2you use the
following procedure:
1. With Control 2 high (not connected), activate (ground) Control 1. The
motor rotates until it pushes open
limit switch EA. The bases of Q3
VCC
R7
R1
Figure 1
R4
Q3
Q5
D1
R2
D3
D2
D5
R10
R5
Q1
Q2
R8
MA
R9
F1
R12
R11
MB
R3
R6
IC2
IC1
R13
IC2
EA
EB
IC3
IC1
CONTROL 1
NOTES:
D1, D2: 1N4148
D3 TO D6: 1N4937
R1, R2, R4, R5, R9, R12: 10 kV, 0.25W
R7, R8, R10, R11: 3.3 kV , 0.25W
R3, R6, R13: 1.5 kV, 0.6W
Q4
D4
D6
Q6
CONTROL 2
Q1, Q2: 2N2222, 2N3904...

Q3, Q5: BDX33C
Q4, Q6: BDX34C
IC1 TO IC3: PC814, H11AA1, SFH6206-2...
This simple circuit provides four-position motor control with two inputs.
www.ednmag.com
February 7, 2002 | edn 99
design
ideas
through Q6 are all high.

EA
2. Activate (ground) Control 2. The
MA
bases of Q5 and Q6 switch low. (MB
MB
and EB are closed.) The motor rotates
in reverse until MA closes. At this
EB
time, all bases are low. Q4 and Q6
POSITION 1
POSITION 2
POSITION 3
POSITION 4
short-circuit the motor to
Figure 2
ground, thereby braking it to
a stop.
First activating Control 2 and then Cams operate the limit switches in Figure 1, producing four discrete positions.
Control 1 brings the motor to Position
3, the edge of cam MB. Otocoupler IC3 re- current conditions, such as a stalled mo- and the motor current. (Dont forget the
mains on as long as the motor receives tor. You can mount the circuit in Figure high inductance of the motor.) The comvoltage. The output of IC3 connects to a 1 on small machine tools, such as a work- ponents in Figure 1 accommodate a 24Vfeedback input of the controller. Thus, piece changer. The values of the compo- dc, 2.5A motor.
you can control whether the motor is ro- nents are not critical. The transistors are
tating or stopped through this input. F1, preferably Darlington types and, like the
a polymer-based resettable fuse, protects diodes, should have adequate ratings to Is this the best Design Idea in this
the motor and the circuit against over- accommodate the power-supply voltage issue? Select at www.ednmag.com.
Single switch controls digital potentiometer

Chuck Wojslaw and Gary M Craig, Catalyst Semiconductor, Sunnyvale, CA
he control of electronic potenDPDT
MOMENTARY
tiometers in most todays
CONTACT
F
i
g
u
r
e
1
applications comes from
5V
100k
5V
controller-generated signals. However, a
significant number of applications exist
U/D
that require adjustments using manual,
IC1A
INC
front-panel controls. The circuit in FigMOMENTARY
S1A
ure 1 uses one IC, one switch, and 10 disCS
OFF
IC1B
MOMENTARY
crete components. It implements the interface of a single DPDT, momen100k
5V
CAT5114
tary-contact rocker switch to a DPP (dig10k
100k
S1B
itally programmable potentiometer). The
5V
74HC132
IC1D
Catalyst DPP has a three-wire increIC1C
ment/decrement interface. The tradi10k
100k
tional way to implement the front-panel
5V
controls for potentiometers with this
C
R
1 mF
1 mF
4.7 mF
100k
type of interface is to use two single-pole,
single-throw switches. Switch S1 reduces
the front-panel hardware by half. The ac- A single switch is all you need to control a digitally programmable potentiometer.
tion of the switch is natural for the control of increment-up/increment-down driving the INC input of the DPP. The depress the rocker switch, the clock freeclock output of IC1D drives INC. The runs at a frequency of approximately
potentiometers.
IC1A and IC1B, which implement an R- clock becomes enabled when you depress 1/R1C1.
S flip-flop, control the potentiometers the rocker switch either up or down. The
wiper directionup or down. The out- RC networks at the inputs of IC1C deput of the flip-flop reflects the up/down bounce the switches. If you momentariposition of S1. The potentiometers wiper ly depress the rocker switch, the clock Is this the best Design Idea in this
advances on the falling edge of the signal generates one pulse. If you continuously issue? Select at www.ednmag.com.
100 edn | February 7, 2002
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Versatile power-supply load uses light bulbs

William Sloot, Computron Display Systems, Mount Prospect, IL
mprovising loads for bench-testing
and designing power supplies is often
a frustrating and sometimes hazardous experience. When you push large
power resistors to their limit, they tend
to burn benches and melt solder connections. Many electronic loads are on
the market but are usually expensive and
of laboratory-type precision and often
represent overkill for the average designer. Incandescent light bulbs make excellent loads, able to handle large
amounts of power. Moreover, they come
in small packages and require no heat
sinks. Furthermore, because they light
up, you obtain instant feedback, rather
like an analog versus a digital meter. The
drawback is that the resistance of an incandescent lamp changes dramatically
with the power input. The power into the
load must therefore be controllable over
a broad range, if the bulb is to be a use-
ful current sink. A simple approach to

this control problem is to pulse-widthmodulate a power MOSFET in series
with the load. This design uses a fourrail, 100W supply with outputs of 5, 12,
and 615V. For these voltage and power
levels, 50W, 12V bulbs provide a suitable
load. This application required three
bulbs connected in parallel (Figure 1).
Many automotive-supply dealers offer
50W, 12V bulbs.
Because these bulbs screw into an ordinary 115V light socket, you can create
a virtually unlimited combination of
loads. The use of old-fashioned porcelain-type sockets wired in parallel allows
you connect any number of bulbs in the
load circuit. The circuit in Figure 1 addresses supplies of 1 to 24V output levels,
of positive or negative polarity, with power levels as high as 150W. You can use the
same basic approach to load higher volt-
age supplies by using 115V light bulbs

and appropriately sizing the power
MOSFET and other components. The
circuit uses a standard PWM 3843 IC,
IC1, in open-loop mode. Potentiometer
VR1 controls the duty cycle over its full
range. The frequency is not critical and is
approximately 37 kHz with the values
shown in Figure 1. A small, modular
plug-in transformer provides power, but
you can use any source of approximately
18V dc at 50 mA.
T1 provides isolated drive to the power MOSFET, Q1. The transformer allows
you to load negative as well as positive
sources. The various components in the
gate circuit provide efficient drive to Q1
over a broad range of duty cycles. The L1
choke isolates the input from the switching pulses in Q1. You could use either an
analog or a digital current readout. This
design uses an LED readout salvaged
ON/OFF
2
12V AC
115 AC
50W
12V
1N4148
+
Figure 1
50W
12V
50W
12V
L1
50 mH, 5A
+ 1000 mF
25V
TO POSITIVE
INPUT
100 mF
25V
47.5W
+
10
T1
COILCRAFT
0.22 mF
0.22 mF
SD 250-1
Q1
IRF3710
4.7 nF
1N4148
10k
+
2N4401
7
IC1
3843
2
3
2N4402
180
4.7k
20V
470 mF
35V
47
1.2k
TO CURRENT METER
4.7 nF
R1
SELECT
VR1
1k, 10 TURN
470
TO NEGATIVE INPUT
Incandescent light bulbs provide convenient loads for testing power supplies.
www.ednmag.com
design
ideas
from an old power supply. You must size

the current resistor, R1, for the power dissipation and the requirements of the
current meter. In this application, three
metal-oxide, 0.1V, 2W resistors connected in series met the requirements
(maximum current of 4A). You must fas-
ten Q1 to a heat sink adequate for the application. The circuit in Figure 1 uses an
Aavid (www.aavid.com) 530101B00100.
This heat sink is a U-shaped radiator
measuring approximately 1.753175 in.
on each side. Applications requiring
higher currents could use two MOSFETs
in parallel. The gate-drive scheme shown

has enough power to drive two
MOSFETs.

issue? Select at www.ednmag.com.
Two-transistor circuit replaces IC

Jim Hagerman, Hagerman Technology, Honolulu, HI
inear Technologys recently intro5V
3.3V
duced LTC4300 chip buffers I2C
10k
10k
clock and data lines to and from a
SCL
SCL*
hot-swappable card. This task is difficult
because the IC must work bidiFigure 1
rectionally, meaning that you can
simultaneously and actively drive both
ENABLE
sides. However, as is sometimes the case,
10k
you can replace a complicated circuit by
a simple one without much loss of per- This circuit is an I2C-compatible, hot-swappable
formance. For example, transistors and translator/buffer.
resistors replace the entire IC (Figure 1).
The circuit handles only the clock signal and drop the VCE voltage to approxior only the data signal. Two npn transis- mately 0.1V, thereby pulling the other
tors, connected head-to-head, form the side low.
The circuit acts like an efficient diode.
heart of the circuit. I2C signals come from
open-collector or open-drain outputs, so With Enable low, the hot-swappable side
can only pull down (sink current). When has no effect on the signal, with or withEnable is high, a low-going SCL signal out power applied. The two-transistor
drives the emitter of one of the transis- circuit offers the additional benefit of acttors as a common-base amplifier. The 10- ing as a level translator between two logkV resistor in the base circuit provides ic levels. This example shows a bufferenough current to saturate the transistor translation between a 3.3V system and a
5V card. For proper operation, the Enable

line must not go higher than the lower of
the two supply voltages. Figures 2a and b
show operation at 100 kHz. Some edge
glitches and overshoot, stemming from
transistor-junction capacitance, are evident in the 3.3V signal, but these slight
defects should be tolerable in many lowcost applications. References 1 and 2
treat similar level-translation circuits.
References
1. Hagerman, Jim, Two transistors
form bidirectional level translator,
EDN, Nov 7, 1996, pg 114.
2. Poon, CC, and Edward Chui, Lowvoltage interface circuits translate 1.8V to
5V, EDN, Nov 5, 1998, pg 119.

(a)
Figure 2
(b)
The 5V side (a) and the 3.3V side (b) drive operation with the circuit.
www.ednmag.com
design
ideas
Digital current source is nonvolatile

Stephen Woodward, University of North Carolina, Chapel Hill
igitally
programmable
current sources that
Figure 1
V1 (OPTIONAL)
feature automatic
2.5 TO 6V
trimming and retain the setting
despite power-down cycles are
W2
useful in applications such as RFLT
IN
OUT
and laser-communications driv317
W1
ers. The circuit in Figure 1, for example, is particularly suited for
ADJUST
8
R1
setting the drive current for the
VR
1.24
CAT5512-00
1.25V
optical pump in widely tunable
DPP
3
H
VCSELs (vertical-cavity surfaceVR
2
emitting lasers). These lasers are
W
5
U/D
suitable in systems using wave12P
R2
DIGITAL
1
length-agile DWDM fiber-optic
1.24
INC
PROGRAM
P
INTERFACE
communication links. The circuit
100k
7
in Figure 1 delivers a stable drive
L
6
CS
current that derives its control
VR
from DPP (digitally programmed
.
JL4
(R1+(11P)R2)
potentiometer), a Catalyst Semiconductor (www.catsemi.com)
4
CAT5512. For the circuit values
LOAD
(EG, LASER DIODE)
shown, you can set the output
current to 500 mA to 1A; howevV
er, you can alter this span over a
NOTES: IMAX= R ,
R1
wide range by the judicious selecVR
IMIN=
(R2<<100k),
tion of sense resistors R1 and R2.
R1+R2
IMAX R1+R2
The unique features of the
V
V
=
, R1= R , AND R24 R 1R1 .
IMIN
IMIN
IMAX
R1
CAT5512 make possible the low
component count (two chips and
two resistors). The device combines a 5-bit-resolution, 100-kV This digitally programmable current source is suitable for driving VCSELs in communications equipment.
DPP, a nonvolatile EEPROM for
long-term storage of the DPP setting, and design equations are R151.25V/IMAX, and dropout voltage (approximately 2V) and
the voltage drop across the R11R2 series
a unity-gain analog-wiper-buffer ampli- R251.25V/IMIN2R1.
Note that the R2 equation is an ap- resistance: VMAX5V+ 1 2V2IMAX(R11
fier. The DPP provides a complete digital interface of the LT317 precision regu- proximation, based on the assumption R2). In the circuit in Figure 1, this voltage
lator chip to the R1, R2 split that R2 is much lower than 100 kV, the is V+ 1 4.5V. This arithmetic leads to a
current-sense-resistor network. The re- parallel DPP resistance. The full expres- VMAX of only 500 mV if you use the W1
option and V+ = 5V. This compliance
sult is a robust, precision programmable sion for R2 is:
current source with 5-bit resolution over R251/(1/((1.25V/IMIN)2R1)21/100 kV). figure may be insufficient for some apYou exert control of the DPP setting plications. If, by contrast, you choose the
a flexible IMIN to IMAX range. The basis of
circuit operation is the fact that the LT317 pand storage of the setting in non- W2 option and V+ is greater than 7.5V
regulator generates the current necessary volatile EEPROMvia the three-wire (not necessarily regulated), VMAX increasto maintain a constant 1.25V across the digital interface, as described in the es to a much more adequate 2.5V.
effective sense resistance: R11(12p)R2, CAT5512 data sheet. The load-voltagewhere p is the DPP setting: 0, 0.032, compliance limit is a function of the W1
0.064, 0.097, ..., 0.98, 1. In this way, and W2 V+ supply jumpers, connected to
I151.25V/(R11(12p)R2) over the range the LT317. The maximum output voltage
of IMIN51.25V/(R11R2) for p50 to is the difference between the LT317s in- Is this the best Design Idea in this
IMAX51.25V/R1 for p51. The pertinent put voltage and the sum of the LT317s issue? Select at www.ednmag.com.
www.ednmag.com
design
ideas
Closing the loop deepens notches

Tom Napier, North Wales, PA
otch filters reby differential-input,
R2
move a sincurrent-output multiR4
Figure 1
C1
C2
gle unwantpliers (for example,
ed frequency from an
the Harris HA2547)
HP
_
R5
BP
_
IC1
LP
input signal. They are also
creates the tunable
R6
R1
_
+
IC2
a vital component of VIN
notch filter in Figure
IC3
+
+
pulse-shaping networks,
2. The time constants
VN
such as time-averaging filT1 and T2 are the
R7
R
NOTCH
8
NOTES: R14R24R4, R74R84R9,
products of the values
ters. You can tune a stateT14R5C1, T24R6C2, AND
R9
VN
_
1`s2T1T2
of the integrating cavariable filter over a wide
INPUT
1
4
.
VIN
IC4
1` R2 sT2`s2T1T2
pacitors and the mulrange by changing the
R3
+
tipliers transimpedtime constants of its inteR3
ances. In Figures 1
grating amplifiers (referand 2, R3 controls the
ences 1, 2, and 3). Textwidth of the notch.
books focus on its high- Changing connections makes the depth of the notch depend only on the gain of the
pass, bandpass, and low- integrating amplifiers.
References
pass outputs, but they
1. Napier, Tom,
sometimes fail to
R3
VN
Multipliers
implenote that subtractFigure 2
R2
NOTCH
T1
ment tunable filters,
ing the bandpass
R1
T2
_
VIN
BP
EDN, March 16, 1992,
output from the input sig_
IC1
_
IC4
pg 131.
nal creates a notch filter.
+
+
_
IC2
_
IC5
2. Siu, Chris, DeThe attenuation of such
+
+
IC3
LP
sign innovations proan open-loop notch filter
+
vide for voltage-tunis limited by how well the
able, state-variable
components match; typi1`s2T1T2
VN
.
4
NOTE: R14R2, AND 1
VIN
1` R1 sT2`s2T1T2
active filters for megacally, its approximately 40
R3
hertz ranges, EDN,
dB. Figure 1 shows a stanSept 28, 1995, pg 117.
dard state-variable filter Replacing two resistors by multiplier ICs results in a tunable notch filter.
3. Napier, Tom,
with an amplifier, IC4,
added to invert the bandpass output. You R9 and to take the notch output from the Take tunable lowpass filters to new
can implement a notch filter by adding a output of IC4. Closing the loop around heights, EDN, Jan 15, 1998, pg 145.
further amplifier to sum the input signal the notch filter makes the depth of the
notch depend only on the gain of the in- Is this the best Design Idea in this
and the output of IC4.
An alternative is to move the input to tegrating amplifiers. Replacing R5 and R6 issue? Select at www.ednmag.com.
Hints and kinks for USB decoding

Bert Erickson, Fayetteville, NY
he USB is a serial data-transmission for USB were for 1.5 and 12 Mbps at lowsystem that uses cables to connect pe- and full-speed rates, respectively. These
ripheral equipment to
TABLE 1BINARY VERSUS DIFFERENTIAL-NRZI
PCs. All new computers
have two or more USB reBinary
Differential NRZI
ceptacles, and the predic11)
11)
11)
b(n1
b(n)
d(n1
d(n)
or
d(n1
0
0
1
0
0
tions are that they will re0
1
0
0
1
place most of the legacy
1
0
0
1
1
receptacles on older PCs.
1
1
1
1
0
The 1.0 and 1.1 standards
standards targeted low- and mediumspeed peripherals. The latest 2.0 standard
is for a 480-Mbps rate that will
CODE accommodate many highspeed devices along with the
previous low- and full-speed
d(n)
1
rates. At the PC-accessible USB
1
receptacle and at the peripher0
al, if it has a receptacle, the sig0
nal has the format of differenwww.ednmag.com
design
ideas
D S Q
d(n) DATA
tial-NRZI (nonreturn-to-zero-inverted)
CP
CLK
code. After conversion (with a simple cirC Q
(a)
cuit or test probes) of this differential to
b(n)
single-ended signal, the signal
D S Q
Figure 1
becomes a waveform that asCLK
CP
C Q
sumes the voltage levels used to recognize
(b)
b(n) DATA
d(n)
ones and zeros in computer code.
In this NRZI waveform, a transition
between the d(n21) and d(n) bits de- Simple circuits perform NRZI-to-binary (a) and
codes to a binary b(n)50 data bit. No binary-to-NRZI (b) conversion.
transition decodes to a binary b(n)51
bit. However, when you display the d(n) volve some computer statements and
waveform on an oscilloscope of a logic logic circuits that provide a different way
analyzer, it is difficult for an observer to to effect the conversion.
decode it back to the originating binary
Table 1 shows all the combinations
waveform, or vice versa. In this situation, that can exist in NRZI encoding. For the
you may doubt your judgment and turn differential-NRZI-d(n)-to-binary-b(n)
to dedicated test equipment to make the code conversion, the following observaconversion. Much of the human problem tions apply:
occurs because NRZI decoding depends
The conversion is independent of
on knowledge of the previous and cur- b(n21).
rent input bits to determine a value for
If d(n21)d(n), then b(n)50.
the current output bit. In the encoding
If d(n21)5d(n), then b(n)51.
descriptions in most textbooks and tech Or, simply, b(n)5d(n) XOR NOT
nical articles, the transitions receive pass- d(n21).
ing mention, and the material presents a
You can perform the conversion by uspair of waveforms with little or no elab- ing an XOR gate and a 74LS74 D-type,
oration. The following suggestions in- positive-edge-triggered flip-flop (Figure
1a). The flip-flops Set and Clear terminals connect to VCC, and you do not need
to reset either one. For the binary b(n)
to differential NRZI d(n) conversion, we
offer the following observations:
The conversion is not independent
of d(n21).
d(n)5d(n21) unless
b(n21)50 AND b(n)50, then
d(n)5NOT d(n21), or
b(n21)51 AND b(n)50, then
d(n)5NOT d(n21).
You can perform the conversion by using an XOR gate and a 74LS74 D-type
positive-edge-triggered flip-flop (Figure
1b). The flip-flops Set and Clear terminals connect to VCC after you use them to
set d(n) to its proper initial value. For all
input-data sequences that keep repeating, you must select the last and first bits
to produce the first output bit. You can
download a computer program that
confirms the decoding from the Web version of this article at www.ednmag.com.
www.ednmag.com
design
ideas
Circuit controls intensity of reflex optical sights

Stephen Woodward, University of North Carolina, Chapel Hill, NC
popular category of aiming/
pointing aids is the reflex, or
Figure 1
IL
red-dot, sight. This system
SIGHT
finds use in such diverse applications as
LED
100
astronomy, archery, and shooting. In the
R2
reflex sight, light from an internal
LIGHT
sourcetypically a high-intensity red
SHIELD
LEDreflects from a curved, transparQ1
AMBIENT
LIGHT
L14Q1
ent optical (reflex) element through
+
9V
which you view the target. The result of
500 mAHR
IP
this geometry is that the image of the
NC
LED (the red dot) appears superimposed
Q2
CCW
CW
Q3
on the target image, thus indicating the
2N3904
2N3904
100k
point of aim. When you correctly adjust
R1
the aiming point of the telescope, bow, or
NOTE:
PHOTODECTOR'S
gun, the target and LED images coincide.
RATIO ADJUSTMENT
FIELD OF VIEW IS SIMILAR TO
The reflex sight offers several advantages
THAT OF THE REFLEX SIGHT'S.
over competing pointing technologies,
such as telescopic and open sights. These
benefits include rapid and intuitive tar- This simple circuit automatically adjusts red-dot intensity in reflex optical sights.
get acquisition, noncritical eye positioning, and a wide field of view.
possible. For this reason, most reflex mm objective reflex sight. The light shield
For best sight performance, the inten- sights require manual adjustment of the mimics the field of view of the sight, so
sity of the red-dot light source must at source intensity. Although this adjust- the light that Q1 samples represents the
least roughly match the illumination lev- ment is effective enough, the time and at- target intensity visible through the sight.
el of the target. Otherwise, if the source is tention needed to optimize intensity with Proper adjustment of R1 results in good
too dim, the aim-point dot loses itself in a manual control detracts from the fast compensation of dot intensity for a wide
the brightness of the target. If too bright, and intuitive target-acquisition capabili- range of both incandescent and natural
the dot flares, and its apparent size in- ties of the red dot. The circuit in Figure light. The circuit effectively maintains a
creases, obscuring the point of aim and 1 uses phototransistor Q1 to sense target constant angular dot diameter of 4 minmaking precise pointing difficult or im- brightness and automatically adjust the utes of arc under outdoor ambient lightLED output. The circuit maintains near- ing ranging from dark overcast to full
constant dot size over a wide range of sunlight. The circuit also delivers similar
Circuit controls intensity
ambient-light levels.
performance under indoor incandescentof reflex optical sights ..................................85
Potentiometer R1 divides Q1s pho- lighting conditions. Compensation with
Indicator features expanded scale ............86
tocurrent, IP, between the LED driver, Q2, fluorescent lamps, however, is less satisand the bias transistor, Q3 (connected as factory because of the absence of an ad16-bit ADC provides
a diode). The adjustment of R1 therefore equate near-infrared component in the
19-bit resolution..............................................88
determines
the ratio between drive cur- spectrum of these light sources. You
Microcontroller emulates
,
and
ambient (target) intensity could probably fix this shortcoming by
rent,
I
L
numerically controlled oscillator ................92
over the range of 1 to B, where B is the beta using a suitable visible-light filter in front
Method simplifies testing
of Q2 (greater than 100). The prototype of of Q1.
high-Q devices................................................94
the intensity-control circuit was packaged
in a small plastic enclosure attached to the
side of a Compasseco Inc (www.com Is this the best Design Idea in this
passeco.com) Tech Force model 90 30- issue? Select at www.ednmag.com.
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February 21, 2002 | edn 85
design
ideas
Indicator features expanded scale

Abel Raynus, Armatron International, Melrose, MA
5
est equipment for a production line
ACCEPTABLE
should be user-friendly (read
RANGE
Figure 1
(GREEN ZONE)
idiot-proof ) and should of4.75
fer minimal test time. In many cases, the
MEASURED DEVIATION
test fixture must give an operator only
VOLTAGE (V)
one answer: pass or fail. Usually, two inMEDIUM VALUE
dicators assume this role: green for pass
and red for fail. In most applications, a
sensor transforms the tested parameter to
a voltage; the test fixture must measure
this voltage and display the result. Sometimes, an operator needs to observe the
TRANSIENT
STEADY-STATE PROCESS
PROCESS
dynamics of the tested parameter to verTIME
ify that the results are inside the permit- Its desirable to observe deviations in values inside the acceptable green zone.
ted green zone. For
V2, the diode, D1 does not conduct, and
example, when evalumA
the voltmeter comprises the microamating a regulated
Figure 2
50
60
40
meter and resistor, R1. When the tested
systems behav70
30
20
80
voltage surpasses the threshold V2, the
ior, the operator is of3
2
10
90
V
1
4
diode conducts, and resistor R2 connects
ten interested in meas100
0
4.75
in parallel with R1. The voltmeters imuring the parameters
5
0
pedance decreases, thereby expanding the
deviation and estimatmeasurement scale. You can calculate the
ing its average value
values of resistors R1, R2, and R3 as folafter the process
lows:
reaches steady state
The voltage at the beginning of the
(Figure 1). In this situ- Its difficult to discern deviations from the norm when the green
tested zone, 4.75V, should consume
ation, using an analog zone represents only 10% of full-scale.
10% of the scale, with a corresponmeter with marked
ding current of 10 mA. Hence, nered and green
mA
Figure 3
glecting the internal meter impedzones is prefer50
60
40
70
30
ance, R1 equates to 4.75V/10 mA, or
able to using a digital
20
80
475 kV.
or bar-graph LED dis10
90
After the measured voltage exceeds

play.
V
0
100
4.75
the threshold level, 4.75V, the voltAssume that the
5
meter impedance equates to R1,25
range of the tested
(524.75)V/(100210) mA, or 2.8
voltage is 4.75 to 5V.
kV.
To make a voltmeter Expanding the green zone to 90% of full-scale makes readings much
Hence, (R1R1,2)/(R12R1,2)5(4753
with maximum 5V easier.
2.8)/(47522.8)52.8 kV, and R35
reading by using a
VCC
R2(VCC/V221)52.8 (5/4.7521)5
100-mA dc meter, you would use
5V
Figure 4
147V.
a series resistor of 50 kV. The meR3
ter scale is linear, and the tested voltage
100 mA
D1
147
zone represents only 5% of full-scale
(Figure 2). It is difficult for an operator
R1
R2
to observe the meter reading inside such
VTEST
V2
475k
2.8k
a narrow zone. It would be desirable to
expand the test zone to, say, 90% of fullscale (Figure 3). The circuit in Figure 4
does just that. When the tested voltage, This simple circuit expands the acceptable test
VTEST, is lower than the threshold voltage, results to 90% of full-scale.
www.ednmag.com
design
ideas
16-bit ADC provides 19-bit resolution

Alain Guery and Charles Kitchin, Analog Devices, Wilmington, MA
any data-acquisition systems
10
1000
require both high accuracy
Figure 1
11
and a fast acquisition rate.
These attributes allow the system to de12
tect small data signals and to group more
sensor channels into the same system.
13
100
With more channels, the system can be
14
smaller, less expensive, and less powerconsuming. Long-distance optical com15
munications and medical equipment,
ACCURACY
ACCURACY
DATA-ACQUISITION-SYSTEM
(PPM OF POINT)
(BITS)
such as CT scanners, can benefit from a
SPECIFICATION
16
107
PPM
OF
POINT61.9
PPM
fast and accurate data-acquisition system.
10
17
Optical power systems, such as laser
pumps, need to constantly monitor their
18
power levels. In such systems, the incoming laser-power range and the laser
19
control-loop response time are such that
1
20
the system needs a dynamic range of 90
0.000001 0.00001 0.0001 0.001
0.01
0.1
1
10
100
dB or more and a sampling rate of 1M
INPUT VOLTAGE
sample/sec. In CT scanners, 16- to 22-bit
(% OF FULL SCALE)
resolution is necessary for the data-acquisition system to process the large dy- Using a programmable-gain amplifier ahead of an ADC increases the accuracy of a 16-bit ADC to 19
namic range of the X-rays through vari- bits.
ous body tissues. A large
5V
number of photodeF
i
g
u
r
e
2
2.5V
tectors (more data-ac5k
30k
quisition channels) and high
825
data accuracy improve the
5
2
COMPLATCH
+
image resolution.
IC1
7
AD8561
These two examples show
3
100
the need for relative accura84.5
590
6
4
cy, as opposed to absolute acIC3
curacy. Although its imporADG749
tant to be able to detect a
10-nW change in an optical
5
1
GAIN
power of 1 mW, it is almost
2
irrelevant to see the same 102 IC6
CHANNEL
3
R1
6
IN1
AD8021
4
nW difference between 1
IN2
7
3
15
5 IN
+
D
+
3
mW and 1.00001 mW. HowC1
5
6 IN
5
27 nF
13
+
ever the ADCs accuracy apIN6
10 pF
12 IN
IC4
7
pears under the integral11 IN ADG758
8
CALIBRATION
590
10
nonlinearity specification as
43
19 A
IN+
0
an absolute error. For the best
IC2
18 A
1
AD7677
17
relative accuracy, a classic soA2
IN2
1
REF
lution is to use a program5V
39
EN
37
mable-gain amplifier in front
590
REF
2.5V
of an accurate ADC. The
2
2 IC7
+
R2
6
1 mF
AD8021
AD7677 ADC specifies 615VCM
3
15
+
ppm of full-scale nonlinear+
1.25V
C2
5
+
27 nF
ity (61 LSB at the 16-bit lev10 pF
el). A programmable-gain
amplifier ahead of this converter must be able to settle This system provides 19-bit accuracy by combining a programmable-gain amplifier with a 16-bit ADC.
www.ednmag.com
design
ideas
quickly enough with the same resolution

and speed as the ADC. It also
Figure 3
must have the lowest noise possible, because the amplifier sets the SNR
of the data-acquisition system. To meet
these challenges, the amplifier in this design uses an AD8021, an op amp combing speed, accuracy, and fast settling time.
The noise density of the AD8021 is only
2 nV/=Hz. Figure 1 shows how the gain
settings of the programmable-gain amplifier divide the specified accuracy of the
ADC. The system reaches 19-bit accuracy when the input level is low.
Relative accuracy is normally specified
as parts per million of reading plus or minus the absolute minimum error. The cir- This plot shows the differential nonlinearity of a data-acquisition system for all possible ADC
cuit in Figure 2 can achieve a relative ac- codes.
curacy of 107 ppm61.9-ppm
work to provide different gains to a
maximum error. Analog multiplexmaximum of 25. The analog switch,
er IC4 combines many lower bandwidth channels to take advantage of
IC3, controls the gain setting. The high
gain-bandwidth product of the ADthe 1M-sample/sec sampling rate of
8021 op amp provides more than
the ADC. Because the programmaenough bandwidth, so its compensable-gain amplifier presents a high intion capacitor remains the same for all
put impedance to the multiplexer,
gains. Amplifier IC7 generates the difyou can cascade the multiFigure 4
ferential signal for the ADC. The setplexer, thus increasing the
tling times of the comparator and the
number of channels. The multiplexamplifier and the acquisition time of
er also provides a simple way to cal- The dime shows the relative size of the complete datathe ADC are all significantly less than
ibrate the offset and gain errors at acquisition system.
the ADCs full conversion period of 1
each gain setting by applying a calibration-reference voltage to one of the time of 7 nsec. It integrates a latch signal msec. The RC noise filters at the two ADC
multiplexers input ports. You need to that holds the gain constant during the inputs, R1/C1 and R2/C2, use this extra
calibrate only at power-up or when op- time the amplifier settles and the ADC time. These filters limit the noise banderating conditions, such as temperature, acquires the signal. The usual program- width of the programmable-gain amplichange. The amplification chain com- mable-gain-amplifier configuration re- fier, which is the main noise source of the
prises the multiplexer, the comparator, quires the user to predict the amplifiers data-acquisition system when IC7 operand the amplifier on one side and the gain setting before applying the signal at ates at a gain of 21.
Figure 3 shows the circuits nonlinearADC on the other side. The successive- the input. The programmable-gain amapproximation structure of the AD7677 plifier in Figure 2 has an autorange fea- ity. The photo shows a maximum nonADC allows the individual sections in the ture that selects the most appropriate linearity of 0.44 LSB and a minimum of
amplification chain to work simultane- programmable-gain amplifier gain to 20.37 LSB for the highest gain setting,
ously. While the ADC converts one sam- maximize accuracy without incurring which poses the most difficult challenge.
ple, the comparator/amplifier can settle saturation or clipping. The comparator This nonlinearity corresponds to a typithe following channel. Therefore, the incorporates hysteresis to reduce gain- cal error of 60.9 ppm. At a gain of 8, outdata-acquisition system can operate at setting change when signals are close to put noise is 85 mV rms. If desired, you can
the limits of an individual gain range. further reduce the noise by using softthe ADCs maximum sampling rate.
Shortly after the analog multiplexer The circuit automatically boosts the ADC ware averaging. Figure 4 shows the comsettles, the fast comparator, IC1, applies accuracy to 19 bits while maintaining a plete data-acquisition system assembled
the appropriate gain setting. The com- full-speed sampling rate of 1M sam- using the AD7677 evaluation board. The
parators thresholds are such that the ample/sec.
pc-board area measures 15330 mm.
plifier does not saturate or clip the sigIC6 amplifies the multiplexer signal usnal after amplification by IC6 and IC7. ing one of two possible gain settings: 1 Is this the best Design Idea in this
The AD8561 comparator has a response or 8. You can modify the feedback net- issue? Select at www.ednmag.com.
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design
ideas
Microcontroller emulates
numerically controlled oscillator
Tom Napier, North Wales, PA
icrocontrollers commonly add
intelligence or digital functions to
products, but they can also provide
a variety of analog signals. An 18-pin PIC
16C54 microcontroller, combined with
an inexpensive, 8-bit DAC and a simple

lowpass filter, can generate sine waves
from dc to approximately 50 kHz with a
tuning resolution of 24 bits. The accuracy and stability of the output is as good
as that of the crystal driving the microcontroller. You can connect a binary data
signal to one or more PIC ports to apply FSK (frequency-shift-keying), BPSK
(binary-phase-shift-keying), or QPSK
5V
5V
5V
Figure 1
5V
0.047
mF
14
4
VCC
FREQUENCYCONTROL
INPUTS
0.047
mF
5
RTCC
16 OSC1
15
OSC2
B7
13
12
B6
11
B5
10
16C54 B4
9
2
B3
A3
8
1
B2
A2
18
7
B1
A1
17
6
B0
A0
5 D7
6 D6
7 D5
V+
0.047
mF
15
6 _
6.8k
REF1
IO
4.7 mH
1.5 mH
TL082
5 +
4
8 D4
9 D3
10 D2
11 D1
12 D0
1 LC
14
REF+
0.047
mF
3.3k
3.3k
13
MCLR
20 MHz
GND
DAC08
6800 pF
IO
V1
COMP
16
1.1k
100
0.047
mF
2200 pF
SINE
OUTPUT
15V
1k
0.047mF
15V
An inexpensive microcontroller and DAC emulate a numerically controlled oscillator.
LISTING 116C54 NUMERICALLY CONTROLLED OSCILLATOR-EMULATION ROUTINE
www.ednmag.com
design
ideas
(quadrature-phase-shift-keying) modulation to the output. Figure 1 shows the

emulation scheme, and Listing 1 controls
the operation of the microcontroller. The
16C54s firmware emulates a 24-bit numerically controlled oscillator. A fixedlength loop continuously adds the contents of one set of registers (the frequency
control) to another set (the phase accumulator). The phase accumulator increments at a rate proportional to the desired output frequency and wraps around
once per output cycle.
With a 24-bit accumulator, the output
frequency is f3N/[67108864(L12)],
where f is the clock frequency, N is the
tuning control number, and L is the number of instructions in the loop. (The loop
period is two instruction times longer
than the instruction count, L.) For example, if the PICs clock crystals frequency is 16.777 MHz, and the loop has
30 instructions, you can set any frequency to approximately 40 kHz in steps of
1/128 Hz. Once per loop, the highest byte
of the phase accumulator selects an out-
put sample from a 65-element look-up

table, which contains one quadrant of a
sine wave. To create the other three quadrants, bit 6 determines whether to read
the table forward or backward, and bit 7
specifies the output sign. An exclusiveOR operation on bit 7 with a port bit generates BPSK operation. An exclusive-OR
operation on both bits 6 and 7 with port
bits generates QPSK modulation. The result goes to the DAC via the PICs 8-bit
output port. A 50-kHz lowpass filter then
converts the DACs output into a smooth
sine wave.
You can preset the output frequency or
load it serially via two pins of the PICs 4bit port. You obtain FSK by using an input bit to select which of two frequencycontrol registers to use. If the two
frequencies have a large common multiple, as in minimum-shift keying, the accumulator can be shorter, leading to a
higher output frequency for a given clock
input. Without modulation, the firmware
loop can be as short as 26 instruction
times (Listing 1). You can insert nonop-
eration instructions to make the looprepetition rate a convenient submultiple

of the crystal frequency. For example, a
31-instruction loop and a 20-MHz crystal yield a scale factor close to 104
steps/Hz.
The code takes advantage of a quirk in
the 16C54s operation: If two addresses
exist on the return stack, the first copies
endlessly into the second every time the
routine pops the second. The initialization code puts two copies of the loopstart address into the return stack, causing all subsequent RETLW instructions
to jump to the start of the loop. Indexing into the look-up table with a calculated GOTO instruction both supplies an
output sample and executes a jump to
restart the loop. This procedure is much
faster than executing a CALL, a GOTO, a
RETLW, and a further GOTO. You can
download Listing 1 from the Web version
of this article at www.ednmag.com.
Method simplifies testing high-Q devices

Alan Victor, IBM Microelectronics, Research Triangle Park, NC
he design of low-phase-noise oscillators requires careful atFigure
tention to resonator unloaded Q. In the construction of a
low-phase-noise, high-frequency oscillator, the goal is to achieve an unloaded-Q
figure greater than 400 in a reasonable
package. Also, you need to monitor the
effect of the package and pc-board
arrangement. Shielding, inappropriate
grounding, and some construction techniques can degrade unloaded Q. Q meters; various bridges, such as Maxwell and
Hayes; and both vector and scalar impedance analyzers are useful but inconvenient-to-use test instruments. You
must carefully set up test fixturing and
calibration that duplicates the final environment to obtain reasonable agreement with the final measured results. A
simple test set uses nothing more than
RG
50
TABLE 1NOTCH DEPTH

VERSUS SERIES RESISTANCE
1
C1
13 pF
VIN
L
450 nH
RL
50
RF
VOLTMETER
RS
A simple test set allows you to determine the

unloaded Q of an inductor.
the voltage-divider relation with the device under test embedded as a series trap
network (Figure 1). You can measure the
inductors value, or calculate it from
known equations based on the inductors
form factor, such as solenoid, toroid, helical, or flat spiral. You use the inductors
value to select C1, a variable, air-dielectric
high-Q capacitor. At resonance, the im-
V)
RS (V
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
Notch depth (dB)

247.993
242.007
2-38.52
236.055
234.151
232.602
231.297
230.171
229.181
228.299
pedance of the inductor-capacitor combination goes to zero, so the effective load

is the series resistance RS in parallel with
the 50V termination resistance.
You use an RF generator and voltmeter
to read the depth of the notch the trap
creates. This attenuation depth is a function of the remaining finite-series resistwww.ednmag.com
design
ideas
ance of the resonator. Table 1

225
shows the notch attenuation for RS
227.5
ranging from 0.1 to
Figure 2
230
1V. These values assume 50V source and termination
232.5
impedance and the component
235
values shown in Figure 1. Un237.5
NOTCH
loaded Q equates to XL/RS, where
DEPTH
240
(dB)
XL is the reactance of the inductor,
and RS is the equivalent series re242.5
sistance. Figure 2 shows the notch
245
attenuation as a function of the
247.5
equivalent series resistance. In ad250
dition, a crosscheck is available:
0.1
You can the 3-dB bandwidth of
EQUIVALENT SERIES RESISTANCE (RS)
the notch and calculate unloaded
Q from f0 divided by the band- The notch depth of the circuit in Figure 1 at resonance is
width. Finally, as a sanity check, inversely related to the equivalent series resistance of the
you can readily reduce the un- inductor.
loaded Q to a known value by inserting a series resistance in the trap cir- Delron rod with careful construction lets
cuit. The reduction in unloaded Q you achieve unloaded Q near 500 at 70
should correlate with added resistance MHz. The measurement technique unvalue. Any variations you notice in these veils issues with shielding, namely the resimple experiments are usually the result duction in Q from the effect of the shield
of subtle factors. One factor in particular on the solenoid coil. The details of the
is a component operating near its self- measurement are as follows:
resonant frequency. In the test case of
Assume an inductor with known L and
Figure 1, six-gauge wire on a 0.75-in. XL at a frequency of interest f0. The in-
ductor shall resonate in a seriestuned (trap) configuration, driven from a 50V generator and terminated in a 50V shunt. An RF
voltmeter placed across the shunt
reads notch depth in decibels.
From Figure 2, you can determine the unloaded Q from the
expression Q5XL/RS. For example, a solenoid inductor measuring 0.75 in. in diameter and
wound with five turns of sixgauge wire has a measured inductance of 460 nH at 65 MHz.
1
The inductor series-resonates at
65 MHz with a 13-pF capacitor.
You set the signal generator at 65
MHz and use a variable, air-dielectric capacitor to fine-tune the
notch at 65 MHz. The measured
notch depth is 36 dB. RS is 0.4V, and the
unloaded Q is 469. You can readily notice
changes in the depth of the notch with
fine variations in coil position relative to
conducting surfaces.
www.ednmag.com
design
ideas
Frequent Design Ideas author

takes home annual award
EDN is pleased to announce that Stephen Woodwards design entry is the grand-prize winner of EDNs 2001
Design Ideas competition. Woodward will receive a $1500 check for his July 5 entry, Quickly discharge powersupply capacitors, which we present again below in case you missed it the first time. Woodward is a frequent EDN
contributor and previously won the annual award for his first submission to EDN in 1974.
The Design Ideas section is among the most popular features in EDN, because it embodies the traditional engineering challenge: An individual sees a well-defined and bounded problem; applies a mix of hardware, software, and
algorithms; and produces an innovative solution to that problem. In many cases, the problem is unique or requires
a solution that is complex and costly.
According to Woodward, Theres nothing quite like the satisfaction that comes from seeing your name in print
attached to something that others find a useful idea. Ive done over a hundred of these bite-sized articles, and the
pleasure has never faded. The ideas that form the basis for my Design Ideas come from two basic sources. Some I
develop specifically for publication. Others come from real-life applications. The circuit that won this year is one
of these. The rapid and safe discharge of large power-supply filters is a problem Ive been bothered by for years.
The topology in this years winning Design Idea is a solution I came up with only after long consideration. It has
served me well in dozens of designs.
We congratulate Woodward on his achievement.
Quickly discharge power-supply capacitors

perennial challenge in power- RB (Figure 1). The trouble with the RB
supply design is the safe and speedy fix is that power continuously and
discharge, or dump, at turn-off of wastefully bleeds through RB, not only
the large amount of energy stored in the when its desirable during a capacitor
postrectification filter capacitors. This energy, CV2/2,
1:1
can usually reach
S1
Figure 1
tens of joules. If you
let the capacitors self-disNC
charge, dangerous voltages
CVS2 ~
can persist on unloaded
= 50J
NC
2
120V AC
electrolytic filter capacitors
for hours or even days.
These charged capacitors
+ 4400 F
can pose a significant hazard
RB
200V
to service personnel or even
to the equipment itself. The
standard and obvious solution to this problem is the
traditional bleeder resistor, A bleeder resistor ensures safety but wastes much power.
www.ednmag.com
dump, but also constantly when the

power supply is on. The resulting energy hemorrhage is sometimes far from
negligible.
Figure 1 offers an illustration of the problem, taken from the power supply
of a pulse generator. The
CV2/2 energy stored at the
nominal 150V operating
voltage is 15024400 F/2,
or approximately 50J. Suppose that you choose the RB
fix for this supply and opt
1k
to achieve 90% discharge
V=150V
25W
of the 4400-F capacitor
within 10 sec after turning
off the supply. You then
have to select RB to provide
a constant RC time no
March 7, 2002 | edn 121
design
ideas
longer than 10/ln(10), or 4.3 sec. RB,

therefore, equals 4.3 sec/4400 F,
TURN-OFF
Figure 2
DISCHARGE PATH
S1
or approximately 1 k. The re1:1
sulting continuous power dissipated in
R1
RB is 1502/1 k, or approximately 23W.
This figure represents an undesirable
power-dissipation penalty in a low-duty120V AC
R2
cycle pulse-generator application. This
waste dominates all energy consumption
and heat production in what is otherwise
a low-average-power circuit. This sce+ 4400 F
V=150V
nario is an unavoidable drawback of
200V
C
bleeder resistors. Whenever you apply
the 10%-in-10-sec safety criterion, the
downside is the inevitable dissipation of
almost half the CV2/2 energy during each
Otherwise unused switch contacts can dump energy while not wasting power.
second the circuit is under power.
Figure 2 shows a much more selective ro power-on energy waste. Use the fol- ensure quick disposal of the stored enand thrifty fix for the energy-dump lowing four criteria to optimally select ergy.
problem. The otherwise-unused off- R1, R2, and S1:
S1 must have a break-before-make
The peak discharge current, V/(R1 architecture that ensures breaking both
throw contacts of the dpdt on/off power
switch create a filter-capacitor-discharge R2), should not exceed S1s contact rat- connections to the ac mains before making either discharge connection and vice
path that exists only when you need it: ing.
The pulse-handling capability of R1 versa. Otherwise, a hazardous groundwhen the supply is turned off. When the
switch moves to the off position, it es- and R2 should be adequate to handle the fault condition may occur at on/off trantablishes a discharge path through resis- CV2/2 thermal impulse. A 3W rating for sitions.
tors R1 and R2 and the power trans- R1 and R2 is adequate for this 50J examformers primary winding. The result is ple.
an almost arbitrarily rapid dump of the
The discharge time constant, Is this the best Design Idea in this
stored energy while the circuit suffers ze- (R1R2)C, should be short enough to issue? Select at www.ednmag.com.
High-side current sensor has period output

Greg Sutterlin, Maxim Integrated Products, Wexford, PA
Quickly discharge power-supply
capacitors ......................................................121
High-side current sensor
has period output ........................................122
Absolute-value comparator
touts accuracy, size......................................124
Programmable oscillator uses
digital potentiometers ................................128
Time-delay relay reduces
inrush current................................................130
Optimize linear-sensor
resolution ......................................................132
122 edn | March 7, 2002
ou use high-side current monitoring in many battery-powered products that require accurate monitoring of load current, charger current, or
both. In applications for nonportable designs, high-side-current monitoring
serves as a power-supply watchdog that
can flag a failure in downstream devices.
The monitoring can also eliminate hazardous conditions by preventing powersupply overloads. Further, high-side-current monitoring of motor/servo circuits
can produce useful feedback in control
applications. These applications require
a device that converts high-side current
directly to a digital signal (Figure 1). IC1
is a low-cost, high-side-current-sense
amplifier that converts high-side current
to a proportional, ground-referenced
voltage. Its two internal comparators
(latching and nonlatching) implement a
voltage-to-pulse converter that produces
an output pulse width proportional to
the measured current.
IC1s Out pin charges C1 via R1. When
C1s voltage reaches 0.6V, Comparator1
latches in the high-impedance state. The
time required to charge C1 to 0.6V is proportional to the measured current. Comparator2, in conjunction with the Reset
pin, initiates the conversion and removes
the previously existing charge on C1. The
Reset and CIN2 pins, tied together and
connected to a TTL-compatible microcontroller output, CTRL, control the
conversion process. Normally, CTRL is
www.ednmag.com
design
ideas
RSENSE
CTRL 5V
0 TO 20V
Figure 1
RS+
VCC
10k
TO
MICROCONTROLLER
INPUT
COMPARATOR1 OUT

RESET
4
CIN2
R1
COUT1 5V
C1
VTHRESH
+
6
GND
3
CIN1
COMPARATOR2

GND
5
IC1
MAX4374
The duration of a negative-going pulse at COUT1 is proportional to the current flowing through
RSENSE.
high. The microcontroller starts a conversion by pulsing CTRL low, discharging C1 and clearing the latch in comparator1 (COUT1 goes low.) The microcontroller now measures the time from
the CTRL transition to the low-to-high
transition at COUT1 (Figure 2). The period begins at the low-to-high transition of
CTRL and ends at the low-to-high transition of COUT1. As a function of the current levels of interest, you select R1 and
C1 values to create pulse durations in the
TPULSE
Figure 2
COUT2
1.5 SEC TYPICAL
GND
LOAD
RS
8 COUT1
VTHRESH
CTRL
10
5V
tens of milliseconds. As a result, the Out

settling time of 20 sec and the comparator propagation delays of 4 sec
have negligible effects on the measurement accuracy.
To derive an expression for the output
pulse width, start with the relationship
for an RC-charging circuit: VTHRESH
Out(1e TPULSE/R1C1). For the Out-pin
voltage, substitute the expression ILOAD
RSENSEAV and solve for ILOAD: ILOAD
VTHRESH/[RSENSEAV(1eTPULSE/R1C1)],
These waveforms illustrate the operation of the

circuit in Figure 1.
where ILOADmeasured current in amperes, VTHRESHcomparator threshold

0.6V, RSENSEcurrent-sense resistor in
ohms, AVgain of IC1, and TPULSEtime
to charge C1 to VTHRESH in seconds.
For example, selecting R11 M,
C10.1 F, RSENSE0.075, and AV20
produces a TPULSE measurement of 0.022
sec in response to a 2A current. Thus, given a microcontroller timer port, an external interrupt, or simply an available
microcontroller input, IC1, and two external passive components implement
high-side-current-to-digital conversion
without the need for a discrete A/D converter.
Absolute-value comparator touts accuracy, size

Teno Cipri, Engineering Expressions Consulting, Sunnyvale, CA
typical window comparator uses
two comparators and a single
5V
Figure 1
op amp to determine
+
whether a voltage is inside or outside a
IC2A
VREF
IC
boundary region. Figure 1 shows a typiLM319
1
VREF

AD548
cal implementation. IC1 is an inverting op
+
amp with a gain of 1. VREF and VREF
create the window limits. When VIN becomes more positive than VREF, the out+ IC
2B
put of IC2A goes low. When VIN becomes
LM319
V

IN
more negative than VREF, the output of
IC2B goes low. If VIN is lower than VREF and
greater than VREF, both outputs of IC2
5V
remain high. The LM319 and AD548
come in 14- and eight-pin DIPs, respec- This traditional window-comparator circuit suffers from limited input range.
124 edn | March 7, 2002
5V
www.ednmag.com
design
ideas
VREF
tively. The LM319 accommodates sepaR2
rate input and output power supR1
Figure 2
plies. The input supply can be
2k
R3
2k
15V referenced to analog ground, and
5V
1k
the output can use a logic supply refer15V
D1
enced to logic ground. The circuits input
R4
_
limit is 2.5V because of the maximum
+ IC
VIN
R5
V1
2
IC1A
_
1k
differential-input limit of the LM319. If
LM1458
LM311
V2
IC1B
_
1k
+
D
LM1458
2
you think the input will exceed a 5V
+
differential voltage between VREF and VIN
or VREF and VIN, then you must incor15V
porate a clamping network with many
additional discrete components. The cir- An absolute-value comparator circuit offers a wide input range and improved dc performance.
cuit in Figure 2 overcomes
symmetrical for positive and negthese limitations.
ative voltages. The following
To increase the maximum
expressions define V2: V2
differential-input voltage, you
|VIN|VIN(2VIN) for posican use an LM311, but it is
tive inputs, and V2VIN for
available only in eight-pin
negative inputs.
packages, so the circuit would
The dual comparators of Figrequire three eight-pin packure 1 can have slightly different
ages. To reduce the chip count,
thresholds. You can select the
the circuit in Figure 2 uses an
dual op amps in Figure 2 for inabsolute-value amplifier drivput offsets below 1 mV; doing so
ing a single LM311 comparaallows the circuit in Figure 2 to
tor, IC2. Although at first glance
EDN02022di-28412
the circuit in Figure 1 may look
improved dc performance.
Heather offer
simpler than the one in Figure
Another advantage of the circuit
2, you can save pc-board area
in Figure 2 is the fact that you
and improve performance by
need change only R2 to set the
gain of the circuit. Most comusing a dual amplifier in a sinparators have offset voltages of
gle eight-pin DIP and an
Channel A is the rectified (absolute-value) output of
several millivolts, so scaling up
LM311, also in an
Figure 3
IC1B; Channel B is the output of the comparator.
the input voltage improves accueight-pin DIP. In Figracy by increasing the signal/offure 2, when the absolute value
of VIN exceeds VREF, the output of com- clamped to the forward voltage of D1. Be- set ratio. The circuit in Figure 1 would
parator IC2 goes low. When VIN is posi- cause the inverting input of IC1A and IC1B require the addition of another op amp
tive, IC1A inverts the signal, and the volt- are both at virtual ground, no current to achieve this goal. The simulation in
age at R5 is equal to VIN. The current flows through R3 and R5. With IC1A ef- Figure 3 shows the circuit response.
flowing through R5 is 2 times that flow- fectively out of the circuit, IC1Bs gain is Channel A is the output of IC1B. Chaning through R1, and the output of IC1B is 1, and the output voltage is positive. nel B is the output of the comparator
equal to VIN. When VIN is negative, D2 The inverting-input voltage of IC2 is al- with VREF set at 1V. Marker 1 corresponds
blocks the output of IC1A, which is ways at a positive value. This circuit is to the 1V threshold, and Marker 2 corresponds to logic low at the output of the
VREF
comparator. The circuit in Figure 4 is anR1
R2
other variation of the circuit that uses a
2k
2k
R3
single 5V supply. It works for input sig5V
Figure 4
1k
5V
nals of 0 to 5V and VREF of 2.5 and 5V.
The 0 and 5V inputs result in the maxiD1
R4
mum value of 5V at the output of IC1B.
_
VIN
D2
+
R5
IC1A
With VIN at 2.5V, the output of IC1B asIC2
1k
_
LM1458
LM311
IC1B
1k
sumes the minimum value of 2.5V.
_
+
LM1458
+
2.5V
You can modify the circuit in Figure 2 to work with a single supply.
126 edn | March 7, 2002

www.ednmag.com
design
ideas
Programmable oscillator uses digital potentiometers

Alan Li, Analog Devices, San Jose, CA
igital potentiometers are versaADJUST TO SAME
tile devices; you can use them
SETTINGS FOR
Figure 1
R
FREQUENCY
C
in many filtering and waveVP
10k
A
B
TUNING
form-generation applications. This DeB
2.2 nF
sign Idea describes an oscillator in which
W
W
2.2 nF R
C
setting the resistance of two digital po2.5V
10k
tentiometers independently programs
V+
+
A
the oscillation amplitude and frequency.
VO
AD8510
Figure 1 shows a typical diode-stabilized
_
V
Wien-bridge oscillator that generates ac2.5V
curate sine waves from 10 to 200 kHz. In
R2A
this classic oscillator circuit, the Wien
VN
NOTES:
D1
R AND R= AD5232.
2.1k
network comprising R, R, C, and C,
R2B
R2B=AD5231.
provides positive feedback, and R1 and R2
B 100k A
1N4148
provide negative feedback. R2 is the parallel combination of R2A and R2B in series
R1
W
1k
D2
with RDIODE. To establish sustainable osAMPLITUDE CONTROL
cillation, the phase shift of the loop
should be 0 when the loop gain is unity.
In this circuit, you can determine the This Wien-bridge oscillator uses digital potentiometers to provide independent settings of ampliloop gain, A(j )
(j ) by multiplying the tude and frequency.
amplifier gain by the transfer function
VP/VO. With RR and CC, the loop
gain is
R=8 k
1 + R 2 / R1
A(s)(s) =
.
f=8.8 kHz
(1)
3 + sRC + 1 / sRC
Substituting sj and rearranging the real and imaginary

terms yields
A(j)(j) =
Figure 2
R=4 k
f=17.2 kHz
1 + R 2 / R1
. (2)
3 + j(RC1 / RC)
You define the phase angle of the loop

gain as
Im A(j)(j)
0 = tan1
.
Re A(j)(j)
(3)
You force the imaginary term to zero

to set the phase shift to 0. As a result, the
oscillation frequency becomes
0 =
1
1
or f 0 =
,
RC
2 RC
(4)
where R is the programmable resistance:

R=
256D
R AB .
256
(5)
D is the decimal equivalent of the digital

code programmed in the AD5232, and
128 edn | March 7, 2002
R=450
f=100 kHz
These three frequencies reflect three digital-potentiometer settings.
RAB is its end-to-end resistance. To sustain oscillation, the bridge must be in balance. If the positive feedback is too great,
the oscillation amplitude increases until
the amplifier saturates. If the negative
feedback is too great, the oscillation amplitude damps out. As Equation 2 shows,
the attenuation of the loop is 3 at resonance. Thus, setting R2/R12 balances
the bridge. In practice, you should set
R2/R1 slightly higher than 2 to ensure that

the oscillation can start. The alternating
turn-on of the diodes makes R2/R1 momentarily smaller than 2, thereby stabilizing the oscillation. In addition, R2B can
independently tune the amplitude, because 2/3(VO)IDR2BVD.
You can short-circuit R2B, which yields
an oscillation amplitude of approximately 0.6V. VO, ID, and VD are interwww.ednmag.com
design
ideas
dependent variables. With proper selection of R2B, the circuit can reach equilibrium such that VO converges. However,
R2B should not be large enough to saturate the output. In this circuit, R2B is a
separate 100-k digital potentiometer.
As the resistance varies from the minimum value to 35 k, the oscillation amplitude varies from 0.6 to 2.3V. Using 2.2 nF for C and C, and a 10-k dual
digital potentiometer with R and R set
to 8, 4, and 0.7 k, you can tune the os-
cillation frequency to 8.8, 17.6, and 100

kHz, respectively (Figure 2). The frequency error is 3%. Higher frequencies
are achievable with increased error; at
200 kHz, the error becomes 6%. Two
cautionary notes are in order: In frequency-dependent applications, you
should be aware that the bandwidth of
the digital potentiometer is a function of
the programmed resistance. You must
therefore take care not to violate the
bandwidth limitations. In addition, the
frequency tuning requires that you adjust

R and R to the same setting. If you adjust the two channels one at a time, an
unacceptable intermediate state may occur. If this problem is an issue, you can
use separate devices in daisy-chain mode,
enabling you to simultaneously program
the parts to the same setting.
Time-delay relay reduces inrush current

P Seshanna, Assumption University, Bangkok, Thailand
transformer switching onto a
NORMALLY OPEN RELAY CONTACT
line can sometimes cause a circuit
FUSE
breaker to trip or a fuse to blow. This
L
LOAD
phenomenon occurs even if the transR1
220V
(TRANSFORMER/
50 Hz
former presents no load, such as when
CAPACITOR)
N
the secondary is open. The problem arises because of the heavy magnetizing inTIME-DELAY RELAY
1M
rush current in the transformer.
R2
F
i
g
u
r
e
1
50
The amplitude of the current depends on the instant on the ac waveform
C2
D4
D1
1.22 F
at which the transformer becomes ener400V
gized. The inrush current is at its maxi
+
DZ
mum value if the transformer becomes
2k
D2 +
D3
C1
15V
energized when the ac waveform goes
3000 F
LED
NOTES:
50V
RELAY IS VIVA JZX-2P.
through its zero-crossing point. A simiCOIL IS 12V DC.
lar situation exists when a capacitor in
D1 TO D4 ARE 1N4007s.
a power-factor-improvement bank
switches onto the line. In this case, the in- A time-delay-relay circuit can eliminate annoying circuit-breaker trips and blown fuses.
rush current is at its maximum when the
ac waveform goes through its peak value. Normally, a mechanical conFigure 2
12
tactor effects the switching with10
out any control of the instant of
switching. The inrush current dies down
8
RELAY-COIL
exponentially to the normal operating
VOLTAGE
6
(V)
value of the load within a few cycles. If
4
the breaker trips from the initial inrush
current, you close the breaker to re-en2
ergize the circuit and hope for the best.
You can limit inrush current by inserting
0
0.2
0.4
0.6
0.8
1
1.2
1.4
a series resistor, R1, during switching and
TIME
(SEC)
then shorting this resistor after the tranOnly
after
330
msec
does
the
time-delay
relay
short-circuit
the resistor in series with the load.
sient period (Figure 1).
130 edn | March 7, 2002
www.ednmag.com
design
ideas
Lately, designers have been inserting

negative-temperature-coefficient thermistors in series with some loads, such as
switch-mode power supplies. This device
presents a high resistance at the instant
of switching, thus limiting the inrush
current. After a few cycles, the resistance
of the thermistor drops to a low value, allowing normal operation of the load. In
contrast, the circuit in Figure 1 physically inserts a resistor in series with the load
to limit the inrush current and then
short-circuits the resistor after a time delay. You can adapt the circuit to any size
load by suitably selecting the series resistor and the relay-contact rating. A drawback of negative-temperature-coefficient
thermistors is their limited joule heat-absorption capacity. The circuit in Figure 1
works directly from the ac line to which
the load drawing inrush current is connected.
The steady-state dc-current requirement of the relay coil determines the values of the other circuit components. You
select capacitor C2 such that the average
value of the rectified current, IAVE, is equal
to the current the relay coil requires. The
coil resistance should be smaller than the
capacitive reactance of C2 at line frequency. Under these conditions, the av-
erage rectified current is approximately

IAVEV(2fC2)/1.11, where V is the rms
value of the line voltage (220V), f is the
line frequency (50 Hz), and C2 is the required capacitor value. Once you know
the relay current, you can select capacitor C2 and the bridge diodes. The value
of capacitor C1 determines the delay
time.
The voltage across C1 rises exponentially with a time constant, RLC1 (Figure 2). If you know the relays pickup
voltage and its coil resistance, RL, you can
choose the required value for C1. It is easy
to see that when you close the main
switch, the circuit simultaneously energizes the load drawing inrush current
and the time-delay relay. A constant average-current source drives the capacitor/relay combination, and the dc voltage
rises exponentially. When this voltage
reaches the pickup voltage of the relay,
the relays normally open contact across
the series resistor closes, thereby shortcircuiting the resistor. When you open
the main switch, the voltage across the relay coil drops, again exponentially. When
this voltage reaches the dropout voltage
of the relay, the contact opens. The resistor is again in series with the load and
ready for the next switching operation.
The pickup voltage of the 12V relay in the

test is approximately 6V, and the contactclosure time is 330 msec, as the dashed
line in Figure 2 shows.
The important design considerations
are as follows:
The normal operating voltage of the
relay must be less than 10% and must be
lower than the ac-line voltage.
C2 determines the average operating
current through the relay.
The relays contact rating must be
adequate to meet the load-current requirement. The relay in Figure 1 is small
and has 12V-dc coil rating and 220V-ac,
5A contact rating. The measured coil resistance is approximately 160.
The function of the 50 resistor, R2, in
Figure 1 is to limit the switch-on surge
current into the time-delay-relay circuit.
The zener diode, DZ, limits the voltage
rise across C1 to 15V in the event of a relay-coil open circuit. You can use the circuit in Figure 1 in the laboratory for energizing a 220V, 1-kVA transformer for
use in experiments.

Optimize linear-sensor resolution

Steve Woodward, University of North Carolina, Chapel Hill, NC
wide variety of sensors and
transducers of physical phenomena
work via the mechanism of variable
resistance. These devices sense temperature, light, pressure, humidity, conductivity, and force, for example. Such sensors measure the physical parameter of
interest by reading out the inherent parameter-sensitive resistance or conductance. All resistive sensors share the need
for interface circuitry that provides a suitable source of excitation current and appropriate gain and offset of the resulting
parameter-dependent voltage. The circuit in Figure 1 and the design equations
provide a universal solution for an application-specific, optimum-resolution, ra-
132 edn | March 7, 2002
tiometric interface of almost any resistive

sensor. The technique works with any
unipolar ADC with an externally accessible full-scale reference. When you configure it properly, the interface circuit selectively maps the range of interest of
sensor output resistance (RMIN to RMAX)
onto the full-scale span of the ADC. The
circuit thus optimally uses available resolution that might otherwise be wasted
on sensor resistances that lie outside the
range of a given application.
The circuit works as follows: R1 sources
the sensor excitation/bias current, IB. The
op amp boosts and offsets the resulting
sensor voltage, IBRT, as a function of the
R1-R2-R3 network. When RTRMIN,
VOUT0V, and, when RTRMAX, VOUT

VREF. Thus, RT(VOUT/VREF)(RMAX
RMIN)RMIN. Positive feedback via R4
cancels the effect of voltage variation
across R1 and thus maintains constantcurrent excitation of the sensor throughout the RMIN to RMAX range. You select R1
through R4 as follows: First, select a value for IB. Sometimes, sensor limitations
determine an appropriate value for IB.
Self-heating errors, for example, may limit the maximum excitation current you
can apply to temperature sensors such as
thermistors and RTDs. But if the given
sensor is indifferent to the magnitude of
IB, then youll obtain optimum tolerance
of op-amp offset and gain errors with
www.ednmag.com
design
ideas
IBVREF/(RMAX+RMIN). With IB known,

you can compute the required gain:
GVREF/(RMAXRMIN). Then,
R1(ZRMAX)(11/G).
R2ZR1.
R3(G1)(R1R2/Z).
R4GR1, where ZVREF/IB.

For a practical example of how this circuit can be handy in a real application,
consider a system in which you use a
100 platinum RTD to sense temperatures in the range of 25 to 50C with 0.1
VREF
2.5V
R1
2390
Figure 1
R1
2390
R4
VOUT=VREF
618k
RTRMIN
.
RMAXRMIN
RMINRTRMAX.
A
IB
RT=
VOUT(RMAXRMIN)
R3
1 mA
RT
100
R2
110
27.1k
PRTD
NOTES:
RMIN=109.73 (25C).
RMAX=119.40 (50C).
VREF
+RMIN.
IB=SENSOR REQUIREMENTS,
OR
VREF
.
(RMIN+RMAX)
V=IB(RMAXRMIN); G=
R1=(ZRMAX) 1+ 1 .
G
VREF
VREF
.
; Z=
V
IB
resolution. The corresponding resistance

range is 109.73 to 119.4. The 0.39/
C temperature coefficient would require
at least 12 bits of conversion resolution
without scale expansion. But you can
make an 8-bit ADC suffice using the circuit in Figure 1 with the values shown.
The calculations are as follows: IB1 mA
limits self-heating power to an acceptable
120 W. Assuming VREF2.5V, Z
2.5V/1 mA2500. G2.5/9.67/1 mA
258.5. It therefore follows that
R 1 (2500119.4)(11/258.5)
2390.
R225002390110.
R 3 (257.5)(2390110/2500)
27,100.
R4258.52390618,000.
RT9.67(VOUT/VREF)109.73.
R2=ZR1
R3=(G1)
R1R2
.
Z
R4=GR1.
This circuit allows you to optimize resolution for sensors using resistive elements.
134 edn | March 7, 2002

www.ednmag.com
design
ideas
Circuit adds programmability to sensor amplifier

he pressure-sensor amplifier circuit of Figure 1 offers a numFigure 1
ber of advantages over the
traditional approach using the classic
three-op-amp instrumentation amplifiVREF
er. The circuit can operate from a single
supply and uses only two op amps and
1% resistors. If the reference voltage,
SENSOR
VREF, is 0V, the transducer gain for the
circuit is
R + R4
VOUT = VS+ 3
R3
R2
R1
R4
IC1
+
VCC
R3
VOUT
IC2
+
VS
VS
This circuit is a good sensor amplifier but suffers from a lack of variability.
R + R 2 R 4
.
VS 1
R 1 R 3
To ensure equal gain for the two
R4
R3
R2
R1
(1p1)R p1R
p1R (1p1)R
ground-referenced voltages makFigure 2
VREF
ing up the differential sensor voltL
H
W H
W L
5V
age, you must impose the following con100k
100k
dition:
U/D
R1 + R 2 R 3 + R 4
.
=
R1
R4
This restriction complicates the design
and makes it difficult to add variability to
the circuit. The circuit in Figure 2 has the
same advantageous topology as the orig-
INC
CS
IC2
IC1
5V
VOUT
+
VCC
VS
SENSOR
VS+
Circuit adds programmability

to sensor amplifier ........................................93
CAT5113/5114
Add CAD functions

to Microsoft Office..........................................94
An improved circuit features programmability and fewer components.
Single IC forms pseudorandomnoise source ....................................................98
inal circuit, but it adds variability and tiometers are identical, the end-to-end
programmability to the gain, simplifies resistances are the same, thus meeting the
the design expressions, and reduces the (R1R2)(R3R4) requirement. If you
component count. Two ganged Catalyst reverse the wiper-to-low and wiper-todigitally programmable potentiometers high resistances for IC1 and IC2, R1 and R4
EDN0203di28572
replace resistors R1 through R4. The po- are equal. If you mathematically model
Heather
tentiometers wiper-to-low and wiper-tothe wiper-to-low and wiper-to-high rehigh resistances establish the voltage sistances as (1p1)RPOT and (p1)RPOT, the
gains of IC1 and IC2. Because the poten- gain expression becomes
LED dimmer uses only two lines..............100

Circuit generates fan-speed control ........102
www.ednmag.com
March 21, 2002 | edn 93
design
ideas
VOUT =
VS+VS
, FOR 0 p1 1.
1p1
The factor p1 models the relative position of the wiper as it moves from one
end (p10) of the potentiometer to the
other end (p11). The number of values
p1 can assume is a function of the num-
ber of taps on the potentiometer. The

sensor gain is inversely proportional to
(1p1), is pseudo-logarithmic, and
varies from less than unity to 31 for a 32tap potentiometer, such as the CAT5114,
and to 99 for a 100-tap potentiometer,
such as the CAT5113. The voltage, VREF,
represents a programmable offset voltage
for the signal-conditioning circuit. You

can easily implement the reference voltage by using a digitally programmable
potentiometer configured as a programmable voltage divider.
Add CAD functions to Microsoft Office

Alexander Bell, Infosoft International, Rego Park, NY
icrosoft Word has excellent
drawing capabilities.You could use
it effectively to perform some CAD
tasks, such as schematic entry. Word is by
far the most popular text processor on
the market, and it would seem desirable
for technical writers to be able to create
a single integrated document file combining both text and graphics in an editable format. Of course, many thirdparty drawing or CAD packages are available, but most of them cost a significant
sum. Also, the use of third-party software
components could raise licensing issues.
Moreover, in a shared development situation, you could face a document-interchangeability problem. Some of your
coworkers may lose the ability to perform
schematic editing if the third-party component is not installed on their computTo display this dialogue box, click on
ers. This Design Idea provides
Figure 1
the Draw button in the Drawing
a great deal of flexibility, beToolbar,
shown
in Figure 2.
cause anyone who has Word can create
and modify drawings using standard
Word features.
You can add some
convenience features
that can ease the schematic-entry process within Word. The first step is
to create an Electronic
Components Symbol Library and add it to the
Clip Gallery. You can use
those clips with Word or
any other Microsoft Office application. These
applications supCreate the component symbol by using Drawing
port drawing basiFigure 2
Toolbar objects and then group them.
cally in the same
94 edn | March 21, 2002
way, with their built-in AutoShapes and

Clip Art collection. In addition, you can
use Clip Gallery with other graphics editors that support object linking and embedding. You can even use Clip Gallery as
a stand-alone program. (For more information, refer to Microsoft Help for the
Clip Gallery and related topics.) The task
of creating the components library comprises several steps.
First, open a new file and then adjust
the grid-line settings. You can reduce
Horizontal Spacing and Vertical Spacing to 0.02 in. for good resolution. Make
the gridlines visible by checking the box,
Display gridlines on screen (Figure 1).
To make the Drawing Grid dialogue box
pop up, use the Drawing Toolbar button,
labeled Draw in Figure 2. Set the scale
to its maximum: 500%. Save the file as a
Template by using the Save As option
and choosing Save as Type: Document
Template with extension .dot (for example, MyCad.dot) in the Word Templates default folder and then close the
file. Now, when you open the new file
for drawing, use this template as follows: Go to the File menu item, click
the New subitem, and then choose
the MyCad template. Note that the
grid lines are not printable objects;
they are visible only on the screen.You
could type the text, draw the schematic, and then turn the grid lines off in
the final document.
The next step is to create the symbol and add it to the Library. Use
Drawing Toolbar objects via the corresponding buttons (Figure 2). After
you have finished the drawing, select
www.ednmag.com
design
ideas
Figure 3
You can use the Clip Gallery with many Microsoft

Office applications and even in stand-alone
mode.
all of its constituent parts by pressing the

Shift key and holding it down while
making the selection and then rightclick the mouse on the pop-up menu, select the Grouping item, and click
Group. Now, Word treats the created
component symbol as Clip or Auto
Shape Object, which you can move, resize, and format as a whole image. To edit
a part of the symbol image, you should
first ungroup it, make the necessary
changes, and then group it again. To add
symbols to the Library, you should first
create a new category in the Clip Gallery,
which serves as a container for your
graphic images and then copy and paste
the symbols into the Gallery. The procedure is as follows:
1. Open the Clip Gallery by clicking on
the icon Insert Clip Art located at
the Drawing toolbar.
2. Click on the New Category icon
(Figure 3) and type the name (for
example, MyCad) for your Library
when prompted, then click OK.
3. Check to see whether the new MyCad category icon appears in the
Clip Gallery window (Figure 4) and then click on
the icon to open it.
4. Select the component you
want to add to the Library
and copy it to the clipboard (the shortcut for
the Copy command is
Ctrl-C).
5. Paste the component to
the MyCad Category
(the shortcut for the
Paste command is CtrlV). Type the name
for the symbol
Figure 5
when prompted
96 edn | March 21, 2002
Figure 4
Add the new category, MyCad, which serves as your

Components Library.
and then click OK.

6. Repeat steps 2 to 5 for any components you want to add.
Figure 5 shows a variety of symbols in
the MyCad Category. The usage of the
Components Library is straightforward
and similar to the usage of built-in Clips.
To insert the symbol image into you document, you could use the Clip Gallerys
standard Import Clips feature or the
Drag-and-Drop option, depending on
your personal preference. The Clip
Gallery has a Help utility you can use to
obtain more information. You could further improve ease of use by adding
macros to automate the most common
tasks, such as resizing, rotating, or flipping objects or adding labels, for example. You can assign the macros to shortcuts (certain key combinations).
However, only qualified users, who have
extensive experience dealing with
VBA/macros, should attempt these operations. Also, you must be aware of the
security issues associated with the use of
macros in the applications:
Some macros can perform poten-
tially dangerous and harmful actions, and some of them may contain viruses. Use the macros at your
sole risk without warranty of any
kind.
When using the Clip Gallery in a
shared-development environment,
and also with regard to network-installation or distribution issues, refer to the licensing/legal information, Legal restrictions for using
clips provided in the Clip Gallery
in the in the Help menu and the Microsoft Office End-User Legal
Agreement, because certain restrictions could apply.
You can download several sample
macros from the Web version of this article at www.ednmag.com. You can use
them to Add Label to the selected graphic component, to resize the component
or to rotate it 45 clockwise.You can store
macros in the Macro Module that you
add to the default Normal.dot template,
thus affecting all opened documents. Alternatively, you can store the macros in
the Template Macro Module within the
MyCad.dot file. In this case, the
macros are available only for
opened documents based on
the MyCad template file. For
more information on creating
and storing template files, refer
to the Microsoft online Help
features.
After adding the components to the Clip Gallery, you can

use them in the same way youd use built-in Clips.

in this issue? Select at www.
ednmag.com.
www.ednmag.com
design
ideas
Single IC forms pseudorandom-noise source

Steve Ploss, Veridian, Dayton, OH
rying to find a single IC noise
source can be frustrating. NaFigure 1
tional Semiconductor once
OUTPUT
made such a noise source for audio apBITS
plications, but its now hard to find. This
BITS
BITS
BIT 0
1 AND 2
BIT 3
17 TO 23
4 TO 16
CARRY
situation leaves the designer with several
D
Q
D
Q
choices, most of which involve using sevQ
D
Q
Q
Q
D
D
D
eral ICs. You can take the analog approach of using a lot of gain to amplify
diode-avalanche noise, or you can design
a linear-feedback-shift-register pseudorandom-noise source using multiple The shift registers length in this pseudorandom-noise generator is effectively 25 bits.
CMOS ICs. Alternatively, you
2.5 TO 5.5V
could use a single-chip microconits internal 4-MHz oscillator. The
troller, such as Microchips
shift registers length is efFigure 2
12C508. The classic approach to
fectively 25 bits, three bytes
generating a pseudorandomplus a carry bit. For a maximal1 V
VSS 8
DD
noise sequence is to model the linlength sequence such as this, the
edn02031di28611
ear-feedback-shift register in softpattern does not repeat itself for 5
2
7
GP5/OSC1/CLKIN
Heather
OUTPUT
GP0
ware. The method involves testing
minutes and 35 sec. If you desire
12C508A
and XORing together multiple
higher bit rates, you can simply
3
6
bits to provide the single-bit feeduse a 20-MHz part with a crystal
GP4/OSC2
GP1
back into the shift register. One
to obtain an output rate of 500
4
problem with this approach is that
kHz. Another trick for increasing
GP3/MCLR/VPP GP2/TOCKI 5
it doesnt yield the highest possithe rate is to use a part with an 8ble bit rate. The approach in Figbit output port and use that port
ure 1 is more optimum for using The connections for the 12C508 microcontroller are exceedingly
in place of the Hibyte register.
the lowest number of machine cy- simple.
Then, the commands movf Hicles per loop.
byte,W and movwf GPIO are
The approach is similar to the one that ing 1 shows the assembly code for the unnecessary. The result is a loop time of
CRC bit-shift algorithms take. These al- complete noise source. The entire loop eight instruction cycles and a 25% ingorithms test only a single bit but XOR takes only 10 instruction cycles. You can crease in output rate. Be sure to configmultiple bits in parallel. A microcon- download Listing 1 from the Web version ure the port pins as all outputs.
troller quickly accomplishes the task. The of this Design Idea at www.ednmag.com.
bit-test and XOR operations require only The circuit in Figure 2 produces an out- Is this the best Design Idea in this
three instruction cycles to complete. List- put rate of 100 kHz for the 12C508 with issue? Select at www.ednmag.com.
LISTING 112C508 ASSEMBLY

CODE FOR PSEUDORANDOM-NOISE GENERATOR
edn02031di28612
Heather
98 edn | March 21, 2002
www.ednmag.com
design
ideas
LED dimmer uses only two lines

Jerry Wasinger, WallyWare Inc, Norcross, GA
he circuit in Figure 1 provides 32
steps of brightness control
Figure 1
from 0 to 100%for a backlight or instrument panel, using just two
general-purpose-microprocessor signals.
STEP
In addition, the circuit requires little
CLOCK
board space, because it uses only three
DIRECTION
SOT-23s and one Max package. Although Figure 1 shows the circuit driving white LEDs, the load could also be a
dc motor or an incandescent lamp. The
basis of the circuit is a modified Schmitttrigger relaxation oscillator (Figure 2).
The output of IC1 is high when
5V
1
2
3
4
INC
U/D
H
GND
VDD
D1
WHITE LED
8
5V
DD1
CS 7
6
L
W
R2
75
D2
WHITE LED
R1
75
5V
IC1
MAX5160
5V
2
1
IC2
NC7S14
4
5
2
R3
1k
Q1
ZXM61N02FTA
3
BAT54S
C1
0.01 F
V V V
H = CkR P ln CC D N ,
By controlling the duty cycle of a Schmitt trigger, you obtain 32 steps of brightness in an LED
VCCVDVP
display.
where k is the wiper position, VCC is the
100
supply voltage, VD is the diode voltage,
and VN and VP are the threshold
2
1 IC
Figure 2
1
DUTY
voltages of the Schmitt trigger.
CYCLE 50
The output of IC1 is low when
(%)
SCHMITT TRIGGER
V V
L = C(1k)R P ln D P .
VDVN
The period and duty cycle are

TLH, and DC100H/T, where DC
is duty cycle. Initial inspection of the
foregoing equations may make the substitutions to solve for the duty cycle appear to be a tedious, algebraic exercise.
But, when you substitute VCC, VD, VN, and
VP into the two logarithmic terms, their
results are close in value. So, you can simplify the expanded solution to the dutycycle equation to
kR P
DC = 100
=
(1k)R P + kR P
100
kR P
= 100k.
RP
Based on the above considerations, you

can see that the duty cycle of the circuit
is not only linear, but also independent of
the selected components. The component selection affects only the center fre-
100 edn | March 21, 2002
D1
10
15
20
25
30
35
TAP POSITION
POTENTIOMETER
D2
(1k)RP
kRP
The duty cycle of the

Schmitt trigger is a linear function of the potentiometers tap position.
Figure 3
940
920
The MAX5160 digital potentiometer controls the

duty cycle of the Schmitt trigger.
FREQUENCY 900
(Hz)
880
860
quency of oscillation. An approximate

equation for the operating frequency is
f1.75/(CRP). This circuit uses a
MAX5160 digital potentiometer that has
a full-scale resistance of 200 k in combination with a 10-nF capacitor. This
combination results in an operating frequency of approximately 875 Hz. Note
that slight mismatches of the two logarithmic terms cause the frequency to vary
slightly as you adjust the duty cycle. Figure 3 shows a plot of duty cycle versus the
840
0
10
15
20
25
30
35
TAP POSITION
Frequency also varies

with the tap position,
but with no effect on performance.
Figure 4
potentiometers tap position; Figure 4

shows the variation in the oscillation frequency with tap position.
www.ednmag.com
design
ideas
Circuit generates fan-speed control

Jim Christensen, Maxim Integrated Products, Sunnyvale, CA
an noise is becoming a significant
14
issue as electronic equipFigure 2
ment increasingly enters the
12
C
office and the home. Noise is propor10
tional to fan speed, and the airflow
hence, fan speednecessary for cooling
B
8
is less at low ambient temperatures. Be6.86
VOLTAGE (V)
6
cause ambient temperature is lower
than the upper design point most of the
4
time, a fan can run slower, making it
2
easier on the ears. Fan-control circuits
A
range from simple switches that boost
0
the speed from low to high, to digital,
0
5
10
15
20
25
30
35
40
45
proportional speed-control designs.
TEMPERATURE
High/low-speed switches are inexpen(C)
sive, but the sound of sudden speed
changes can be annoying. Digitally con- These curves illustrate voltage output versus temperature for the circuit in Figure 1.
trolled fans perform well, but the circuitry is costly, and the system must in- any desired linear relationship between
Curve A in Figure 2 represents the outclude a serial bus. As an alternative, the fan voltage and temperature (Figure put of a MAX6605 analog temperature
consider a low-cost, self-contained ana- 2, curves B and C). We plotted meas- sensor versus temperature in degrees Cellog circuit for fan-speed control (Figure ured data points against the desired sius: VSENSOR0.0119 V/C0.744V.
Curve B relates the fan voltage to tem1). You can easily adjust the circuit for voltage in Figure 2.
Figure 1
12V
FAN
12V
4.9k
10 F
Si9424DY
5V
VREF
1 MAX6003 2
3
R1
301k
R4
20.5
4 MAX6605
0.1 F
R3
27k
1 nF
TO REDUCE
THE OFFSET
1 nF
TO INCREASE
THE OFFSET
R5
169k
5V
3
2
MAX4402
VREF
1
+
MAX4402
2N2222
6
2N2222
1k
R2
3.16k
1k
390 pF
390 pF
R6
100k
This circuit delivers a continuous and linear fan-control voltage that is proportional to temperature.
102 edn | March 21, 2002
www.ednmag.com
design
ideas
perature and combines a minimum

floor voltage of 8V with a sloping line:
VFAN0.114V/CT6.86V, where T is
the system temperature. The floor voltage ensures fan rotation at low temperatures. Above 10C, the voltage increases
with a slope of 0.114V/C until it reaches full value at 45C. Simply amplifying
the MAX6605s output does not provide
the 8V floor voltage. Moreover, the gain
(9.580.114/0.0119) needed to obtain
the fan-voltage slope is not the same gain
(9.226.86/0.744) needed to obtain the
y-intercept point.
To transform Curve A into Curve B,
you must subtract a voltage offset from
the temperature sensors output and then
multiply the result by a constant. The circuit in Figure 1 performs this operation.
You connect the dotted line labeled To
reduce the offset. One op amp creates the
sloped line, and the second op amp creates the floor voltage. The op amps outputs connect to transistors in such a way
that the op amp demanding a higher
104 edn | March 21, 2002
output voltage dominates. The following

equations allow you to determine resistor values:
For the condition in which R2R1,
R1any reasonable value; R2R1
(A V V TEMP0 V Y-INTB )/[(A V 1)(V REF
and
R3R2
VTEMP0VY-INTB/AV)];
(AV1), where AV0.114/0.0119
9.58the ratio of the desired slope in
volts per degrees Celsius to that of the
sensor; VTEMP00.744Vthe temperature-sensor voltage at 0C; VY-INTB
6.86Vthe y-intercept indicated by
the desired (extrapolated) temperature
curve; and VREF3Vthe reference
voltage.
Thus, choosing R1301 k lets you
calculate R23.158 k and R327.09
k. The closest 1% values are 3.16 and 27
k, respectively. The following equation
lets you calculate the floor voltage:
R5R6(VFLOORVREF)/(VREF), where R6
equals any reasonable value. VFLOOR8V,
the desired minimum output voltage.
Thus, choosing R6100 k lets you cal-
culate R5169 k. In some cases, the required offset gain is greater than the required slope gain, so you must increase
the temperature sensors natural offset.
For a desired temperature, Curve C, expressed as VFAN(0.114 V/C)(T)8.5V,
the gain (slope) of AV9.58 is the same
as for Curve B, but the required offset
gain is (8.5/0.744)11.42 is greater. You
therefore use the To increase the offset
version of the circuit in Figure 1. The following equation applies in such cases:
R 4 R 1 ( V Y-INTC /A V V TEMP0 )/( V REF
VINTC/AV)20.41 k, where VY-INTC
8.5V is the intersection of the desired
temperature curve with the y-axis. For
R1301 k, the closest 1% value for R4 is
20.5 k.

www.ednmag.com
design
ideas
Make a simple ramp generator for stepper motors

Richard Brien, GSI Lumonics, Wilmington, MA
S1
tepper motors are synchronous
motors that step at the pulse
COMPUTER
VCC
Figure 1
rate of the driving signal. For
R1
the motor to move quickly, the stepping
15k
RAMPGENERATOR
VCC
rate must be fast. However, because of
C1
COMPONENTS
3 F
motor and load inertia, the motor often
UCN
100k
cannot go from 0 rpm to the desired
5804
4
8
number of revolutions per minute in one
VCC
7 DISC RESET
3
step. Therefore, most stepper motors reSTEP
OUT
100k
555D
DIR
ceive their drive from a pulse chain that
2 TRIG
5
CTRL
6 THR
starts out slowly and then increases in rate
GND
C2
C2
until the motor reaches the desired rate.
1 C
10 nF
2
10 nF
10 nF
To stop the motor, the drive signal must
not abruptly stop; it must gradually decrease or ramp down to zero. Micro- This circuit generates a pseudo-trapezoidal motion-control profile for controlling stepper motors.
processors can easily generate the needed ramp-up and then ramp-down normal circuit, but instead receives its all the components in the timing string.
This final frequency is lower than the fresignals, often called a trapezoidal profile, power through a pushbutton switch.
When you push the button, capacitor quency the circuit would adopt, if C1 and
but in any circuit without a microprocesC1 starts charging up to a point at which R1 were not in the string. When you resor, this ramp is difficult to generate.
The 555-based bistable circuit in Fig- C2 can start charging. As C1 charges, the lease the pushbutton, the 555 does not
ure 1 can easily generate a pseudo-trape- output frequency of the 555 starts off immediately stop running but ramps
zoidal move profile. Note that the timing slowly and gradually increases to a fre- down in frequency until it finally stops
string of R1 and associated components quency or pulse rate thats a function of (Figures 2a and 2b). The ramp frequendoes not connect to VCC, as it would in a
cies generated do not follow a
linear profile, but neither do
PULSE
those in most microprocessorRATE
Make a simple ramp generator
driven circuits. The ramp-fre0
for stepper motors ........................................77
quency profile of the circuit
START
SLOW
RUN
should resemble that of Figure
(a)
TIME
Remote humidity sensor
2a, depending on the
needs no battery ............................................78
Figure 2
component values.
Power source is insensitive
You can operate this circuit
to load changes..............................................80
with a simple pushbutton. This
concept opens a world of manEncrypted routines impede
ual control to stepper motors.
hackers, protect licenses ..............................82
SLOW
SLOW
RUN
Usually, stepper motors do not
TIME
Capacitor improves efficiency
(b)
(PULSE RATE)
use manual control, because of
in CPU supply..................................................86
the difficulty of generating a
trapezoidal frequency profile in
The move profile from the circuit in Figure 1 is roughly
hardware. With this circuit, you
trapezoidal (a); the step-rate profile exhibits low frequencan use low-torque, low-revolucies at ramp-up and -down (b).
www.ednmag.com
April 4, 2002 | edn 77
design
ideas
tions-per-minute stepper motors in systems in which you formerly needFigure 3

ed dc gearbox motors. By changing the pushbutton to a dpdt switch, you
can make a stepper motor run clockwise
and then counterclockwise without microprocessor control (Figure 3). These
concepts also apply to stepper-motorbased linear actuators. You could also replace the pushbutton with a control signal from a computer or a controller, thus
allowing stepper motors to take their
drive from controllers that do not have a
built-in ramp-generating function.
5V
R1
DOWN
16
15
14
13
12
11
C1
R
4
7 DISC RESET
2
6
8
VCC
OUT
555
TRIG
THR
CTRL
GND
UCN5804B
VDD
OUTB
OE
KBD
OUTD
DIR
GND
GND
GND
GND
2
3
4
5
STEP OUTC 6
10 STEP KAC 7
8
9
1PH
OUTA
5V
C2

MANUAL
CONTROL
UP
FROM
COMPUTER
5
C
1
C
By changing the pushbutton in Figure 1 to a dpdt switch, you can make a stepper motor run clockwise and then counterclockwise without microprocessor control.
Remote humidity sensor needs no battery

Shyam Tiwari, Sensors Technology Private Ltd, Gwalior, India
R4
sing ac-line power sources and
47
D1
batteries for remote humidVCC
1N914B
Figure 1
R6
ity sensors is undesirable beQ2
CONTROL 4.7k
cause these sources can be troublesome if
2N2905
INPUT
VCC
R5
14
R2
you mount them in inaccessible points,
f-OUTPUT
R1
4.7k
4.7k
2
IC1
1M
edn02032di28723
1
such as smokestacks, cold-storage cham74HC14
C2
Q1
R
Heather
3
bers, or darkrooms, where maintenance
100 F
2N2222
+
4.7k
7
10V
is difficult and inconvenient. Figure 1
LOW
shows a simple way to remove the power
GROUND
LEAKAGE
C1
source from the humidity-sensor circuit.
10 TO 1000m
160 TO 200 pF
SHIELDED SIGNAL CABLE
The circuit uses a 160- to 200-pF, capac0 TO 100%
REMOTE
itor-type HS1101 humidity sensor from
f-OUTPUT
HUMIDITY SENSOR
Humirel for the circuit. IC1 forms a clasCONTROL INPUT
sic oscillator of time constant R1C1. The
center frequency is 5 to 10 kHz, depending on the value of R1. The circuit charges Eschew troublesome power sources for remote humidity sensors by using this simple scheme.
the 100-F, low-leakage capacitor, C2,
through the diode, D1, directly from the sistor Q1. Transistor Q2 supplies enough the circuit at several humidity points.You
output line of the sensor oscillator, IC1. current to charge C2 through R4. The can find more details about the HS1101
C2 becomes the power source for IC1.
HS1101 sensor measures approximately sensor at www.humirel.com or www.
When you make measurements, you 160 pF at 0% relative humidity and 200 sensorstechnology.tripod.com/humidity.
stop charging C2 for a short time by re- pF at 100% relative humidity. Therefore, html.
moving the Control Input signal (0V for frequency decreases with increasing relacharging and VCC or floating for meas- tive humidity. Although the sensor has a
urement). You then measure the fre- linear response within 5% of full-scale Is this the best Design Idea in this
quency of the signal at the output of tran- range over 1 to 25C, you should calibrate issue? Select at www.ednmag.com.
78 edn | April 4, 2002
www.ednmag.com
design
ideas
Power source is insensitive to load changes

Ken Yang, Maxim Integrated Products, Sunnyvale, CA
or the heating and cooling ele1.2
ments common in industrial
Figure 2
VCC=VPP=15V, VEE=15V
systems, resistance is not a
fixed quantity. These elements include
1
such devices as positive-temperature-coVPC=1V
efficient heaters and thermoelectric coolers. Their resistance can change more
0.8
than 100% during operation, and the result is a change in power dissipation for
LOAD
POWER
elements receiving drive from a fixed
(W) 0.6
voltage or current source. Worse, excessive power can damage the heating or the
VPC=0.5V
cooling element. Driving the element
0.4
with a fixed and regulated power driver
overcomes these problems (Figure 1).
The circuit is analogous to a voltage or a
0.2
current source but delivers fixed power
1
10
100
levels that are independent of the load reLOAD RESISTANCE
sistance. A feedback loop senses load
()
power and automatically adjusts the output voltage to maintain the desired pow- Power delivery to the load is nearly independent of load resistance.
1000
VPP
5 TO 16V
VCC
Figure 1
7
3
Q1
+
10 F
2N3055 WITH
HEAT SINK OR
EQUIVALENT
6
IC6
2
MAX427
4
RSENSE
+
1 F
VEE
RS+
POWER CONTROL
VPC
10k
3k
3k
27k
3k
1
IC5
2
MAX427
4
VEE C1
100k
MAX427 4 2
6
IC4
+ 3
7
T1
TEST POINT VEE
RLOAD
IC2
MAX4372H
0.1 F
OUT
GND
+ 3
10 F
RS
VCC
VCC
0.1
7
10k
6
4
10
10k
11
14
OUT
IC3
2
2
3
MAX427
1 nF
15k
2k
1
RY
20k
RX
20k
J2
2
1
1
10k
13
12k
13k
10k
2
3
X+
VEE
10k
J1
12
2
33k
VCC
ROUT
10k
Y+ 4
IC1
MC1495
OUT+
Y
VEE
39k
7.5k
5k
RSCALE
15k
VEE
2k
This regulated power source delivers fixed power to a varying load.
80 edn | April 4, 2002
www.ednmag.com
design
ideas
er level. The circuit measures the output

current with a current sensor, IC2 and
then determines the output power by
multiplying the current by the voltage
with the use of a four-quadrant analogvoltage multiplier, IC1 and IC3.
Because the multipliers output is inverted, you add a unity-gain-inverting
stage, IC4, to reinvert the output-power
signal. Op amp IC5 then compares output power to the reference power, VPC input, and integrates any difference between them. The integrator provides an
automatic power adjustment by increasing or reducing the output voltage until
output power equals reference power. IC6
and Q1 form a voltage follower that drives
the load. The following formula sets output power: VPC10PRSENSE, where P is the
desired output power in watts, RSENSE is
the sensing resistor in ohms, and VPC is
the reference-power input in volts. If, for
example, the desired load power is 1W,

and RSENSE0.1, then set VPC to 1V.
Curves for load power versus load resistance for 0.5 and 1W loads show that
power delivered to the load changes less
than 7% for a change of 10,000% (two
decades) in load resistance (Figure 2). If
you define load regulation as the change
in output power divided by the output
power, then for a load change of 6 to 40
at 1W, the load regulation is 2%. For
the circuit to work properly, you must
calibrate the analog multiplier as Motorolas MC1495 data sheet delineates.
You repeat that calibration procedure below for convenience. Remove jumpers J1
and J2 for the calibration.
1. X-input offset adjustment: Connect
a 1-kHz, 5V p-p sine wave to the Y
input. Connect the X input to
ground. Using an oscilloscope to
monitor test point T1, adjust RX for

an ac null (zero amplitude) in the
sine wave.
2. Y-input offset adjustment: Connect
a 1-kHz, 5V p-p sine wave to the X
input. Connect the Y input to
ground. Using an oscilloscope to
monitor test point T1, adjust RY for
an ac null (zero amplitude) in the
sine wave.
3. Output-offset adjustment: Connect
the X and Y inputs to ground. Adjust
ROUT until the dc voltage at T1 is 0V
dc.
4. Scale-factor (gain) adjustment:
Connect the X and Y inputs to 10V
dc. Adjust RSCALE until the dc voltage
at T1 is 10V dc. Repeat steps 1
through 4 as necessary.
Encrypted routines impede hackers,

protect licenses
Lawrence Arendt, Oak Bluff, MB, Canada
he use of public-key-encrypted algorithms within licensed applications can prevent hackers from
cracking the licensed algorithms. Moreover, you can use them to disable licensed
features that a user doesnt purchase. Licensing schemes eventually arrive at
some critical decision point at which an
algorithm decides whether the user is entitled to run that application. If not, the
algorithm usually generates a console
message or a message box to notify the
user of his or her ineligibility. Then, the
application terminates or continues in a
feature-limited mode. The decision code
generally resolves to one of the following
(or similar) commands in assembly code:
Jump/Branch if not equal (for example, JNE, BNE)
Jump/Branch if equal (for example, JE,
BEQ).
Typically, a hacker searches a disas-
82 edn | April 4, 2002
sembled listing for the termination message, finds the routine that displays the
message, and then traces backward
through the calling sequence until he locates the decision code. Often, changing
a single hex byte in a binary image of the
executable code completely bypasses the
decision logic. Or changing the byte can
reverse the decision logic. (The new copy
runs only if it does not have a license.) The
edited file can then generate a new .exe
file. For example, you could replace the
hex code for a JNE with a JMP (jump always) or a JE. To thwart hackers,
1. Select the code, CPT, consisting of a
single routine or a block of contiguous routines, that implements the licensing scheme.
2. Compile the application, linking in
temporary code CEN that generates
a CRC of the associated object bytes
and then compress and encrypt the
associated object bytes. Then, dump

the output CCT to a file formatted for
direct pasting into a C/C file.
This file serves to initialize a const
char array called EncryptedRoutines.
3. Now, insert runtime code, CDE, that
copies the contents of EncryptedRoutines to a buffer and then decrypts and decompresses the contents. Also, remove the original
unencrypted code, CPT, and the temporary code, CEN.
4. Finally, recompile the application to
link in CDE and CCT and to exclude
CEN and CPT.
When the application starts up, it executes code CDE, which copies the encrypted bytes from the EncryptedRoutines
array into a dynamically created buffer. It
then decrypts the buffers contents using
a public key, K2, which the vendor provides, followed by decompression. The
www.ednmag.com
design
ideas
routine computes a CRC of the decrypted block. If this CRC matches the original CRC, the application then constructs
a pointer to a decrypted entry-point
function and uses the pointer to execute
that function. CRCs that differ from each
other indicate the use of the wrong public key, and the application terminates,
because executing the still-encrypted
code could be catastrophic. As a result,
any system calls made from within the
encrypted code do not show up in any
disassembled listing. A hacker can detect
them only if he or she is willing to acquire
and use an emulator and trace through
the execution.
Compression of the code to be encryptedbefore encryptionprevents
the hacker from simply replacing the encrypted bytes with the decrypted bytes.
Now, even if the hacker recovers the decrypted bytes, he cannot subvert or
change the licensing logic and then encrypt and replace the existing encrypted
bytes, because he does know the private
key, K1. You should also encrypt all messages that the encrypted routines use.
Most compilers for Windows/DOS generate position-independent code that results in relative calls: Jumps and Branches. When the system compiles and links
the original application, the compiler assumes that all code executes from code
space. Subroutine calls compile into PCrelative call instructions with the correct
displacements. However, the decrypted
routines run out of dynamically allocated data memory, so the displacements are
all wrong.
The solution is to force all subroutine
calls from the decrypted routines to be
made to absolute addresses. However, the
absolute addresses of all linked functions
depend on the compiler and the options
used, the order of the linked libraries, and
the size of the user code, which will change
because of Steps 2 to 4. Three solutions
to these problems are:
1. If necessary, pad the code with dummy instructions, such that the size of
CPTCEN equals the size of
CDECCT.
2. Link all subroutines called from
within the decrypted code to fixed,
user-specified addresses that will not

change because of Steps 2 to 4.
3. Use an encrypted table of absoluteruntime-function addresses.
You can use the same concepts to protect code that implements a licensed feature. If you enter the correct public key,
the decrypted code is usable. If you enter the wrong public key, the decrypted
code remains encrypted, rendering that
function unusable. You should use a
unique private/public key pair for each
licensed feature. Listing 1 shows Borland
5.02 code fragments that illustrate the
concept of running decrypted code from
dynamically allocated memory. You can
download Listing 1 from the Web version of this article at www.ednmag.com.
The programmer can decide the implementation details of the CRC generation,
compression, and private/public key
algorithms.

LISTING 1ROUTINE FOR GENERATING ENCRYPTED CODE
84 edn | April 4, 2002
www.ednmag.com
design
ideas
Capacitor improves efficiency in CPU supply

Masami Muranaka, Maxim Integrated Products, Tokyo, Japan
igh efficiency is important for
the dc/dc buck converters that supply high currents in notebook PCs.
This efficiency extends battery life and
minimizes temperature rise. A low-dissipation synchronous rectifier using an
external MOSET provides this high efficiency. Synchronous rectifiers require
special attention, however. Poor designs
allow shoot-through current when the
high- and low-side MOSFETs conduct simultaneously. Some designers believe
that providing enough dead time between the turn-off of one MOSFET and
the turn-on of the other can eliminate
this problem, but using dead time is inadequate in some applications. Figure 1
illustrates a step-down power supply in
which a step-down controller, the
MAX1718, provides the CPUs core supply. Recent CPU cores require a 1 to 2V
supply rail at more than 20A of input
current. The input-voltage range, on the
other hand, is 7 to 20V. This scenario dictates a low duty cycle for the high-side
MOSFET.
Obtaining high efficiency with a low
duty cycle requires different types of
MOSFETs for the high- and low-side devices, Q1 and Q2, respectively. Q1 requires
high switching speed even if its on-resistance is relatively high, but Q2 requires
low on-resistance even if its switch speed
is relatively low. This combination of parameters allows no possibility of shootthrough current when Q2 turns on, because Q1s fast turn-off occurs first.
Because Q2s turn-off is slow, however,
you must allow enough dead time before
Q1 turns on. The MAX1718 solves this
problem by monitoring Q2s gate voltage,
thereby ensuring that Q1 turns on only
after Q2 shuts completely off.
Now, consider a third condition leading to the possibility of shoot-through
5V INPUT
20
Figure 1
0.22 F
VCC
VDD
SKP/SDN
V+
CMPSH-3
SHUTDOWN
25V
510 F
TON
BST
VCC
D0
Q1
DH
D1
0.68 H
LX
D2
SUMIDA
CEP125#4712-T011
QGD
100k
D3
Q2
D4
DL
MAX1718
ZMODE
OUTPUT
0.6 TO
1.75V
0.004
0.1 F
100k
MULTIPLEXER
CONTROL
BATTERY
7 TO 24V
6270 F
2V
CENTRAL
SEMICONDUCTOR
CMSH5-40
QGS
GND
SUS
REF
SUSPENDINPUT
DECODER
FB
WHEN QGD IS LARGE,
AN ADDITIONAL
CAPACITOR CAN
IMPROVE EFFICIENCY
S0
S1
NEG
62k
TIME
4.75k
47 F
5V
POS
CC
511k
0.22 F
REF
VGATE
24.9k
ILIM
100k
POWER-GOOD
OUTPUT
OVP
27.4k
A buck-regulator IC drives external power MOSFETs to form a CPU-core power supply.
86 edn | April 4, 2002
www.ednmag.com
design
ideas
90
current: a rise in Q2s gate voltage when

Q1 turns on because of high dV/dt
Figure 2
at Terminal LX. That condition
can appear even with sufficient dead
time, because it involves high current
flow into Terminal DL through Q2s gatedrain capacitance, QGD. The MAX1718s
ample current-sinking ability at DL
EFFICIENCY
solves this problem. Sometimes, howev(%)
er, if Q2s gate-drain capacitance is large,
the trace from DL is long, or both, you
can eliminate the shoot-through current
by adding a capacitor of several thousand
picofarads between the gate and the
source of Q2. Figure 2 shows that the addition of a 4700-pF capacitor improves
the high-current efficiency of the circuit
in Figure 1 by a considerable margin.
However, note that using a too-large gatesource capacitor, QGS, can increase the
drivers losses.

88 edn | April 4, 2002
WITH 4700-pF
CAPACITOR
80
WITHOUT
CAPACITOR
70
60
50
0.1
10
100
LOAD CURRENT (A)

NOTES:
BLACK LINE REPRESENTS TWO PA2701s.
RED LINE REPRESENTS TWO PA2700s.
VIN=20V; VOUT=1.3V.
The addition of a capacitor increases high-current efficiency by approximately 3%.
www.ednmag.com
design
ideas
IR distance ranger covers 1 to 20 cm

Paul Florian, McKinney, TX
ommercially available IR distance rangers typically hanFigure 1
dle a 3- to 30-in. detection
distance. Many times, it is necessary to
determine smaller distances. The circuit
in Figure 1 is useful for measuring small
distances to reflective surfaces. Its measurement range is from less than 1 cm to
5V
approximately 20 cm for a flat, white surface. The output of the circuit is an active-high pulse at connector P1. A 12msec pulse corresponds to the minimum
measurable distance; the output frequency is approximately 25 Hz. If the circuit detects no reflection, then the output
at connector P1 remains high. IC1A is a 0.1mA current source. The source charges
C1 and produces a linear voltage ramp.
Every 40 msec, the output of IC2 switches low and discharges C1 through D1. IC1B
and Q1 buffer the voltage on C1. Q1 ramps
the current through the IR LED from 0 to
60 mA. IC3 is a synchronous-detection
photo IC. IC3s output switches low when
the IC detects a reflection from D2.
When the reflection distance is small,
not much current through the IR LED is
IR distance ranger covers

1 to 20 cm........................................................65
Digital volume control
has log taper ..................................................66
Tricks improve on
Excel LCD initialization..................................68
Unidirectional counters accumulate
bidirectional pulses........................................72
Circuit forms UPS for USB devices ............74
Circuit forms high-frequency
polarity clamp ................................................76
www.ednmag.com
5V
1
56k
RSET
2
TRIG
IC2 THRE 6
NE555
CONT 5
3
OUT
8
VCC
7
D1
1N4148
10k
GND
DIS
10k
100k
2 _
IC1A
3+
47k
8
5 +
IC1B
6 _
4
Q1
2N3904
4.7k
+ C1
1 F
C2 +
1 F
15
5V
IR LED
5V
D2
3
10k
OUT
P1
VOUT
5V
CATHODE
4
IC3
VCC
S6846
C3
0.1 F
GND
GND
NOTES:
IC1: TEXAS INSTRUMENTS TLV2252IP.
IC2: NATIONAL SEMICONDUCTOR LM555CN.
IC3: HAMMAMATSU S6846.
D2: LUMEX OED-EL-1L2.
This circuit detects distances considerably lower than commercial IR rangers.
necessary to trigger the photo IC, and the

pulse-width output is short. When the reflection distance is greater, it takes more
current through D2 to trigger IC3, and the
pulse-width output is greater. The maximum pulse width is always less than 40
msec. The duration of the output pulse
also depends on the color of the reflecting surface and the alignment of D2 and
IC3. D2 and IC3 are spaced 0.5 in. apart.
A piece of heat-shrink tubing shields the
sides of D2. To align the circuit, leave
some extra lead length when you mount
D2 and IC3. Next, make small bends in the

positions of these components while
monitoring the output pulse width to
achieve the minimum pulse width for a
given distance to a reflective surface. With
careful adjustment, a detection range of
20 cm is possible to a flat, white surface.
The detection distances for nonwhite
surfaces are lower.

April 11, 2002 | edn 65
design
ideas
Digital volume control has log taper

Doug Farrar, Los Altos, CA
igital potentiometers provide a
compact and convenient way to attenuate audio-amplifier signals.
However, most such potentiometers suffer from at least one flaw: a nonlogarithmic step increment. To avoid this prob-
lem, a user must usually step the potentiometer in a nonlinear sequence to simulate a logarithmic taper. For this reason,
the potentiometer needs many taps, and
you need software help to complete the
design. The circuit in Figure 1 is a low-
6 dB
3 dB
R1
16.5k
1%
1 F
R2
4.02k
1%
0 dB
R3
4.22k
1%
3 dB 6 dB
9 dB 12 dB
R4
4.22k
1%
R5
4.02k
1%
R6
3.57k
1%
12
R7
3.01k
1%
cost, digitally attenuated audio amplifier

that does not use a digital potentiometer. The circuit attenuates the signal in
logarithmic steps, by using an inexpensive 8-to-1 analog switch as its potentiometer. The resistor string, R1 through
VCC
2.7 TO 5.5V
dB
R8
10k
1%
R9
0
AUDIO IN
VOLUME V
1
BITS
V0
15
14
13
16
S2
VCC
10 S1
VSS
S1
S0
IC2
VEE
74HC4051
11
S7
S0
S6
S5
S4
S2
S3
EN
6
0.1 F
Figure 1
6
VCC
SHTDN
100 pF
4
_
IC1
LM4882
+
4
V2
100 F
BYPASS
0.1 F
GND
GND
This circuit sets audio gain logarithmically in 3-dB steps.
Figure 2
12
VOLUME BITS
V2 V1 V0
VCC
GATES:
74HC132
Q3
2N3906
IC4B
1 nF
10k
IC4D
1 nF
10k
IC4A
330k
10k
0.47 F
S1
UP
IC4C
330k
330k
0.47 F
S2
DOWN
330k
330k
Q1
2N3904
9
10
Q3
IC3
P2
Q2 74HC193
1
2
P1
Q1
15
3
P0
Q0
330k
10k
RST
VCC
330k
Q2
2N3904
14
P3
7
330k
330k
13
CY BW
330k
DN
UP
220k
LD
11
330k
0.47 F
Up/down pushbutton switches step the gain in the circuit of Figure 1.
66 edn | April 11, 2002
www.ednmag.com
design
ideas
R8, sets the gain of power amplifier IC1.

Analog multiplexer IC2 selects one of the
eight tap voltages and applies it to IC1s
inverting feedback node. Because only
one bias current flows through the nonlinear switches, the topology introduces
no measurable distortion.
The amplifier changes gain in 3-dB
steps, starting from a high of 6 dB, then
decreasing to 3 dB, 0 dB,...12 dB, and
finally dB (in other words,mute or
off ) as you step the volume bits V2 to
V0 from 7 to 0. If you dont want to turn
off the amplifier at the minimum-volume setting, you could change resistor R9
to a finite value for whatever end-atten-
uation level you desire. The assumption

in Figure 1 is that your system has a way
to generate the 3-bit volume codes. For
those applications that do not have these
bits available, you can use the circuit in
Figure 2 to generate them. Pushing
switches S1 and S2 clocks up/down counter IC3 up and down, respectively. Transistors Q1 and Q2 decode the counters
zero state and disable the down clock
when the count reaches zero. In this fashion, the circuit limits the counter to a value of 0 to 7. Once you attain a maximum
or minimum volume, further pushes on
the up and down switches, respectively,
have no effect on the volume setting un-
til you go in the opposite volume direction. Standby-current consumption of

the logic is almost entirely a function of
the resistors you use for Q1 to Q3, because
the logic chips use almost no power. You
can set a nonzero power-up volume by
using IC3s load (LD) pin when you first
apply power. In Figure 2, the counter
powers up at a 4 volume, rather than
0 (muted). 74HCXX logic operates
over 2 to 7V, but the power amplifier, IC1,
uses 2.7 to 5.5V. Therefore, IC1 sets the
operating-voltage range.
Tricks improve on Excel LCD initialization

Aubrey Kagan, Weidmller Ltd, Markham, ON, Canada
previous Design Idea on using Excel for LCD initialization relies on the user for cutting and pasting from Excel into an
editor (Reference 1). It appears that
it would take a minimum of six
keystrokes or mouse strokes from
one character to a new character to
perform this operation. This procedure does not allow for the addition of comments, which would be
advantageous in the maintenance
of the character set. Over a set of 64
characters, a user would take nearly 400 actions. The use of
Figure
macros would allow for the
reduction of these keystrokes or
mouse strokes and would probably improve the previous idea.
In using such macros, rather than copy
the numbers associated with characters
into the text editor, as the previous Design Idea suggests, you append each sequence of numbers to a text file. When
the character set is complete, you can
open the text file, massage it with findand-replace techniques, and then paste
68 edn | April 11, 2002
sociated with this character.

Creates a line consisting of a
leader, data separated by a delimiter, a comment symbol, and the
comment already entered.
Takes the file name from the
spreadsheet. If the file does not exist, the macro creates a file with the
line appended to it. Each time the
macro runs, it opens, adds to, and
closes the file.
Clears the entries in the LCD
matrix and sets the top-left cell of
the matrix as active, ready for the
This Excel configuration simplifies LCD-matrix
next character.
1
initialization.
All the parameters represent
data in the cells of the spreadsheet.
it as a whole into a target file. An added The file name is in cell A1. (The macro
benefit is that each sequence appears on appends the .txt.) Cell B26 has the
a single line rather than having a line for leader, B27 has the comment symbol, and
every row of the display. You can main- B28 has the delimiter between the numtain this original file for use in both high- bers in the file.You can use this data in aslevel and assembly programs if the need sembler or C or some other language, so
for repeating the process ever arises.
the listing generalizes. C would ignore
The macro in Listing 1 performs the the /* db */, and you could universally
following tasks:
replace it with db if you use an assem Prompts the user for a comment as- bler. Similarly, you could globally modiwww.ednmag.com
design
ideas
fy the comment notation, ;// (with a

space before the semicolon), in the text
file as well. The trailing comma of the line
of data is needed in C as part of a constant array but in assembler would generate an error. If youre using an assembler, the global search would look for the
sequence ;// and replace it with a space
and a semicolon. Because of the inconsistent way text editors deal with tabs, the
listing avoids using the tab character. By
modifying the cells, you can easily customize the format. You can implement
other changes by modifying the macro,
written in Visual Basic for Applications.
The following is a sample line from a file:
/* db */ 4 , 12 , 4 , 4 , 4 , 4 , 14 ,;//this is
a 1 on a 57 matrix.
A button on the spreadsheet allows you

to run the macro with a single click (Figure 1), so you need not switch from the
mouse to the keyboard to run the macro.
You can also run the macros from Ctrlkey combinations. (In Excel, you should
note that, to run a macro, you must have
completed data entry into a cell.) The
matrixs 1016-cell format is also generalized. You can alter this format by entering the number of columns in B3 and
the number of rows in B4 and clicking on
the Shade Matrix button. This action activates a second macro that shades out the
cells not in use. Clicking on the Update to
File button triggers a pop-up window requesting a comment. You need not enter
the comment symbol, because the macro
automatically enters it. The macro then

appends the line to the file. The unused
rows do not appear in the file. You can
download the Excel file in Listing 1 from
the Web version of this Design Idea at
www.endmag.com.
Reference
1. Bitti, Alberto, Excel offers painless
LCD initialization (EDN, Sept 20, 2001,
pg 98).

LISTING 1SAVE-CHARACTER EXCEL MACRO
70 edn | April 11, 2002
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design
ideas
Unidirectional counters accumulate

bidirectional pulses
uadrature-output increCLOCKWISE ROTATION
82C54
mental optical shaft encoders
ENCODER
PIN 16
OUTPUT
are popular in high-performPIN 14
CHANNEL A
ance, bidirectional rotation-sensing
PIN 15
applications. Available with resoluCHANNEL B
tion options extending beyond 2000
PIN 18
pulses/revolution, incremental en1

2048 REV=0.176
coders provide a fast, inexpensive,
COUNTERCLOCKWISE
ROTATION
and reliable way to digitally read out
82C54
PIN 16
CHANNEL A
bidirectional mechanical motion.
PIN 14
The encoders are fast, too; you can
CHANNEL B
PIN 15
usually operate them at 10,000 rpm
and faster. However, the interface
PIN 18
logic they need can sometimes be
somewhat problematic. Such
Figure 2
logic typically includes at
least one long-bit-length (for exam- These timing signals illustrate the operation of the
ple, 16-bit) bidirectional counter. Al- circuit in Figure 1.
though several handy peripheral
chips, such as the 8253, 8254, and 9511, that can provide the needed function,
are available that implement flexible uni- and hard-wired or programmable logic is
directional counting, bidirectional-count- a viable approach. Unfortunately, none of
er chips are relatively scarce. ASICs exist these alternatives is ideal from a cost or
pc-board-area standpoint. The configuration in Figure 1 combines the industry-standard 82C54 unidirectional
counter-timer peripheral chip with simple software to provide a convenient interface of quadrature encoders with the
ISA I/O bus. The technique digitizes bidirectional motion without tears.
As Figure 2 illustrates, the trick is to
use two unidirectional counters of the
three that the 82C54 contains. You use
one counter for each encoder-rotation
direction. One of the encoder quadrature-output signals, A, drives the gate
pins of both counters. This connection
selectively enables counting once every
encoder-output cycle. A couple of
Schmitt-trigger inverter stages phasesplit the other encoder output, B, into
two complementary signals. One phase
drives the trigger input of the clockwise
counter (82C54, Counter 1); the other
phase drives the trigger input of the
B3
B29
5V
+ 330 F
6.3V
B1
B10
B31
DB7
DB6
DB5
DB4
DB3
A3
DB2
DB1
DB0
A7
A8
A9
9
A
8
7
6
5
4
3
Figure 1
B13
LS645
2
19
A22
A23
A11
A25
A26
1
C2 18
A4
A5
A6
B14
A24
5V
4.7k
A2
A27
A30
A31
5V
11
12
13
14
15
16
17
4
5
6
7
8
18
E
C2CCW
C1CW
3,4
A9
5
A8
AEN
A6
12
A5
11
5
I0W
6
2
6
B
5
100 pF
10k
10k
4.7k
5
4
3
TO
ENCODER
100 pF
LISTING 1MBASIC LISTING FOR

MOTION-CONTROL ADAPTER
D0
A1 A0
RD W R
21 20 19 22
2
3
16
C1 15
14
G1
82C54
CS
A4
A1
A0
I0R
A7
G2
1 D7
2
3
23
1
6 9
8
13
10
1
13
12
11
10
9
This technique uses unidirectional counters to encode bidirectional encoder

signals.
72 edn | April 11, 2002
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design
ideas
counterclockwise counter (82C54,

Counter 2). The result is that only the
clockwise counter, Counter 1, is active
during the active B transition during
clockwise rotation, and only the counterclockwise counter, Counter 2, is active
during counterclockwise rotation.
Listing 1, written in MBasic, suffices to
periodically latch, read, and sum the

counter contents to produce a continuous 32-bit readout of encoder position.
You can download Listing 1 from the
Web version of this Design Idea at
www.ednmag.com. The technique can
easily accommodate pulse rates as high as
500 kHz. Passive RC filtering and
Schmitt-trigger signal conditioning provide robust rejection of noise pickup in

the encoder cabling. The design is thus
suited for typical industrial motion-sensing applications.
Build a UPS for USB devices

Mark Cherry and Jean-Claude Ailloud,
Maxim Integrated Products, Sunnyvale, CA, and France
ortable systems often include
circuitry that derives power
V
Figure 1
USB 2
from an external source,
POWER
such as USB. When the system disconVOUT
nects from the USB supply, a battery
V1 +
takes over and supplies current via a
V2>V1
BATTERYdc/dc converter. A diode-OR connection
ONBOARD
(Figure 1) offers the easiest way to ensure
PORTABLE
SYSTEM
that the supply voltage doesnt sag during this switchover to the battery. The
diodes forward voltage drop, however,
can reduce battery life and efficiency. The A diode-OR connection is effective but lossy.
single-cell, boost-converter circuit with
external PFET (Figure 2) is an improve- USB power supply has a diode-OR conment over the diode-OR connection. The nection to Q1s source. Setting the boost
PFET, Q1, coupled with IC1s internal converters output to 3.4V allows the
gain block, forms a linear regulator. The drain of Q1 to regulate to 3.3V. This con-
POWER
FROM PC
USB PORT
3.3V
560

1
R1
D3
figuration produces negligible loss in Q1.

The bus-supply voltage available to
USB devices ranges from 4.4 to 5.25V.
When you connect the bus, it forward-biases D1 and causes the boost converter to
idle. The converter continues to idle as
long as its output remains above the 3.4V
regulation point. The bus supply serves
the load and activates the current source
to charge the battery. Adjusting R1 allows
you to set the current-source output to
charge the nickel-metal-hydride cells at a
level one-tenth the batterys capacity. Disconnecting the circuit from the USB supply causes the boost converter to cease
idling and supply current to the load via
the battery. Figure 3 shows that the load
current suffers no interruption during a
switchover from USB to battery.
D1
D2
4.7 H
+
PORTABLE
SYSTEM'S
BATTERY PACK
LXP
LXN
100 F
220 F2
POUT
10
ON
Q1
3
47 F +
+
20k
180k
TO LOAD
NODE 1
(5V/DIV)
OUT
0.22 F
100k
REF
0.22 F
IC1
MAX1703
NODE 2
(2V/DIV)
NODE 3
(2V/DIV)
FB
AO
AIN
Figure 2
121k
CLK/SEL
PGND
200k
GND
200
mSEC/DIV
These waveforms (bottom trace, load

voltage) show that the load current suffers no interruption during a switchover from
USB to battery.
Figure 3
A boost-converter circuit is an improvement over the simple diode-OR connection.
74 edn | April 11, 2002
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design
ideas
Circuit forms high-frequency polarity clamp

Shyam Tiwari, Sensors Technology Private Ltd, Gwallor, India
ou need a negative signal clamp to
C1
protect an ADC against negative-go1 F
ing signals while measuring
Figure 1
the positive pulse shape of the sig5V
OUTPUT
R2
INPUT
nal by digitizing the waveform. In other
10k
R1
words, you must clamp negative signals
Q1
10k
2N2222
at 0V. The circuit in Figure 1 can clamp
A
7
2
IC
either positive or negative pulses to
1
6
MAX477EPA
ground. The circuit uses a fast MAXS1
3
477EPA amplifier to drive the Q1 or Q2
Q2
+
B
4
2N2905
to clamp signals of either positive or negative polarity. Q1 forces negative signals
to a 0V level; Q2 does the same for posi5V
tive signals. You use an spdt switch to
choose the transistor of interest. The circuit works over 1 kHz to 10 MHz. You This simple circuit clamps either positive or negative signals to ground.
can also make the clamp operate at frequencies as high as 100 MHz by replac- MAX477EPA buffer amplifier to drive the Is this the best Design Idea in this
ing C1with a 1-k, 0.5W resistor. How- 50 signal cable, because the circuits issue? Select at www.ednmag.com.
ever, the output would need another output impedance increases to 1 k.
edn02041di28901
Heather
76 edn | April 11, 2002
www.ednmag.com
design
ideas
Simple phototimer controls load

Abel Raynus, Armatron International, Melrose, MA
5V
HOURS
n industrial and home applications, the need

RESET
6
Figure 1
10k
10k
sometimes exists
NEUTRAL
1 MC68HC705KJ1 16
LD8-C322RI
RESET
IRQ
for a device that, after activation
CERAMIC
270 DOT
15
125V AC
2
by some physical effect, such as
RESONATOR
OSC1
PA0
4 MHz
270 G
light, temperature, or sound,
3
14
LINE
OSC2
PA1
switches a load on for a prede270 F
13
MICRO- PA2
termined time. The load, such as
CONTROLLER
270 E
12
PA3
20k
a lamp, motor, solenoid, or
20k
10k
NIGHT
270 D
11
heater, usually derives its power
PA4
DAY
270 C
LOAD
2
8
_
10
from the ac line. The phototimer
PA5
5
1
LM393
PB2
270
in Figure 1, based on an inex9
B
3
PA6
PHOTO
+
pensive MC68HC705KJ1 mi4
270 A
2
8
PA7
TRIAC
crocontroller, is a simple and inL2004F31
560
1
LOAD
3
10k
PHOTO
PB3
expensive way to satisfy this
4
need. A load switches on when it
7
becomes dark and stays on for
an interval that an operator sets When it becomes dark, this circuit turns the load on for a predetermined interval.
with the Hours pushbutton
switch. A seven-segment LED display
LISTING 1ROUTINE FOR PHOTOTIMER-LOAD CONTROLLER
shows the interval. The time value is a
function of the design objectives, the microcontroller software, and the displayinterface complexity. The design in Figure 1 is simple, because it needs only one
pushbutton switch and a single-digit display.
The heart of the design is the microcontroller software (Listing 1). The routine serves manual and automatic operating modes. The initialization process
sets the manual, or continual, mode. This
Simple phototimer controls load................93

Delay line upgrades
vintage scope..................................................94
Circuit reduces negative-voltage
stresses on control IC ....................................98
Track multisite temperatures
on your PC ....................................................100
(continued on pg 94)
www.ednmag.com
April 18, 2002 | edn 93
design
ideas
LISTING 1ROUTINE FOR PHOTOTIMER-LOAD CONTROLLER (CONTINUED)
setting means, that after a 30-sec delay,

the load switches on and stays on until
you press the Reset pushbutton. The 30sec delay allows you to change your mind
and choose an automatic mode. During
the manual mode, the display exhibits
C for continual. The dot on the display
lights every time the load is on, a useful
feature when the timer and the load are
far away from each other. By pressing the
Hours pushbutton, you change the manual mode to an automatic one. In the automatic mode, the display exhibits a time
delay in hours. When you press and hold
the pushbutton, the digits increment automatically from 1 to 9 every second.
This feature comes about by using counter modulo 9 in the external interruptservice routine (lines 85 to 92 in Listing
1). You can download the software associated with this circuit from the Web
version of this Design Idea at www.
ednmag.com.
After the time-delay setting elapses, the
microcontroller waits for nightin other words, for a high level on the Photo inputto switch on the load. During that
wait, the dot in the display blinks in 1-sec
intervals. When it becomes dark, the
LM393 voltage comparators output
switches high and triggers the program
to continue. The load switches on, and
the dot in the display stops blinking and
stays on. The display digit shows the
elapsed working time. When this time expires, the load and the dot in the display
switch off, and the display exhibits E.
You can stop the process at any time by
pressing the Reset pushbutton. Otherwise, the microcontroller automatically
repeats the entire sequence every night.
The circuit in Figure 1 is extremely flexible. The circuit can switch on the load
using any physical effect just by changing
the sensor on the comparator input. You
can also modify the software for different
time delays. As an example, you might
want to display two-digit hours and twodigit minutes. In this case, you should use
decoder/drivers, such as the CD4511 or
MM74HC138, to configure an interface
with the display.

94 edn | April 18, 2002
www.ednmag.com
design
ideas
Delay line upgrades vintage scope

Robert Houtman, Blaine, WA
TO EXTERNAL
intage triggeredmethods to obtain the
TO
TRIGGER
5V
TWO-STAGE
OSCILLOSCOPE
sweep oscilloscopes
two-stage, pole-zeroEQUALIZER
750-nSEC
470 pF
24 nF
find use in many apcancellation equalizer in
330
DELAY
7
3
75
+
VIN
CABLE
plications. However, they
Figure 1 (Reference 2).
AD8055
2
6
19
19
3.5
3.5
have no internal delay line,
This double-bridged-T
28 pF
1.1M
4
750
135
so they cant display the
filter corrects the cables
560
pulse that triggers the
phase and amplitude
290
140 H
2.8 H
sweep. Moreover, early labdistortion over a 105V
oratory scopes conMHz band.
Figure 1
tain delay lines havEach of these two filing insufficient delay to This circuit modifies vintage oscilloscopes having no internal delay line.
ters is basically a resisdisplay such pulses during
tive attenuator, but fast
a uniform portion of the sweep.
steps can bypass the attenuation durWith such oscilloscopes, the true
ing a time constant, . For short times,
pulse shape remains a mystery.
the equalizers input port sees a load
You can circumvent these limitaof only the 75 cable via the capacitions if you add an external delay
tor, which presents a short circuit at
line and equalizer. The scope can
high frequencies. The inductor presthen display the exact triggerents an open circuit at high frequenpoint trace. The instrument then
cies, so the resistors have no effect for
becomes easier to use, and the
short times. Eventually, as t surpasses
measurements become more
in the step response, the capacitor
trustworthy. For every additional
and inductor yield to the resistive atmicrosecond of equalized cable,
tenuator while presenting the 75
the scope can display a microsecload to the equalizers input. With
(a)
ond of pretrigger information.
only the first, 180-nsec filter, the
Figure 1 shows the components
step response becomes a more finely
you need to implement these imrounded waveform. With the second,
provements on a Philips PM3230
25-nsec filter, the step response is
10-MHz oscilloscope. The coma sharp step, limited only by the oscilponents are a wideband amplifiloscopes bandwidth. Each filter reer to restore the signal to its origsides in a reclaimed CATV signalinal level and provide a trigger; a
splitter box. You can connect these
750-nsec delay cable; and a pas75 constant-resistance filters at varsive, two-stage equalizer.
ious locations along the delay line
CATV cables, such as RG6U,
without incurring reflections. You can
RG59U, and others, are commontherefore use this arrangement to
ly available at garage sales and secfine-tune the passive components to
(b)
ond-hand stores. You connect the
eliminate residual reflections, using
75 cables with solid or
time-domain reflectometry.
The step response through the 750-nsec
Figure 2
foam dielectrics using stanThe AD8055-based amplifier has
cable (a) and the complete network, includdard CATV connectors to make ing the cable (b), differ.
greater-than-100-MHz bandwidth,
the 750-nsec delay line. A low-imfully adequate for the 10-MHz oscilpedance driver displays the bipolar step ror function, cerf(kl/t (Reference 1). loscope. Its input impedance is 1 M in
response of the delay line, as the eye pat- The time, t, refers to the start of the step parallel with 30 pF to match the oscillotern in Figure 2a shows. The delay line after traversing the cable of 160m length. scopes input and its low-capacitance
transmits approximately 65% of the sig- Computer evaluation of this function probes. Figure 2b shows the final eye patnal at audio frequencies, because of re- shows the constant to be k2.6 tern, using the amplifier, the two-stage
sistive losses. The losses increase at high- 107(sec)0.5/m for best agreement with equalizer, and the 750-nsec delay cable.
er radio frequencies, because of the skin the step response in Figure 2a. You can- This pattern is essentially identical to the
effect in the conductor. The theoretical not adequately correct this functional eye pattern that ensues using the oscilloform for the step response that the skin- form by using the usual single-bridged- scope without the circuit in Figure 1, exeffect loss causes is a complementary er- T filter. You therefore apply time-domain cept for the 750-nsec temporal shift. You
96 edn | April 18, 2002
www.ednmag.com
design
ideas
can see the benefit of the circuit in Figthat the circuit in Figure 1 corrects
ure 3. Trace A shows the original impulse
these phase shifts and amplitude
response of the oscilloscope without the A
variations. Trace B shows a short,
circuit. Trace A is merely an uninterestsymmetrical pulse with no tail, an
ing, featureless trace. For Trace B, the ineven function as similar as possible
put impulse passes through the amplifito the input impulse using this oser to the external-trigger input and then
cilloscope.
through the equalizer and delay cable to B
References
the oscilloscopes input. Because its delay
1. Nahman, NS, The measureis longer than the intrinsic delay of the
ment of baseband pulse risetimes of
oscilloscope in starting its sweep, a clean
less than 109 second, Proceedings
pulse of approximately 20 nsec appears
of
the IEEE, Volume 55, No. 6, June
on the display. You can now use the comTraces A and B show the impulse
1967, pg 855.
plete unit as a 10-MHz laboratory
Figure 3
response, respectively, without and with
2. Houtman, Hubert, 1-GHz
oscilloscope.
sampling oscilloscope front-end is
You can define an input impulse as an the delay network.
easily modified, Electronic Design,
even function composed purely of cosine
waves of zero phase. However, the cables sponse is thus no longer an even func- Sept 18, 2000, pg 175.
impulse response is simply the derivative tion, so its composite cosine waves have
of the waveform in Figure 2a and ac- evidently acquired various phase shifts Is this the best Design Idea in this
quires a long, slow tail. This impulse re- accruing to the cable. Figure 3 illustrates issue? Select at www.ednmag.com.
Circuit reduces negative-voltage stresses

on control IC
Michael Day, Texas Instruments Inc, Dallas, TX
n a synchronous, buck switching
power supply, the two FETS and the
output inductor meet at the phase
node (Figure 1). The phase node often
connects directly to the control IC. The
voltage on this node swings from the input voltage to some voltage lower than
ground. If the voltage goes too far below
ground, the ESD structures or other circuitry within the control IC can become
forward-biased, causing currents to
flow through the chips substrate.
These unwanted currents can cause erratic behavior and damage to the IC under certain circumstances. Although it is
impossible to keep the phase node from
going below ground, it is necessary to
keep the voltage at the control IC from
going so far negative that it adversely affects or damages the IC.
Trace A in Figure 2a shows the phasenode voltage waveform with VIN12V,
and VOUT3.5V at 8A. When the top FET
is on, the output current flows through
that FET and the inductor to the output.
During this time, the phase-node voltage
is equal to VIN. The bottom FET must re-
98 edn | April 18, 2002
VIN
TPS5103
VOUT
This classic buck regulator

suffers from excessive negative phase-node voltage.
Figure 1
main off until after the top FET fully

turns off. When the top FET turns off, the
current then flows from ground, through
the bottom FET, and through the output
inductor. Dead time is the time lag between turning off the top FET and turning on the bottom FET. During the dead
time, the current flows through the body
diode of the bottom FET, and the phasenode voltage is approximately 1V, depending on the current levels and the
FET parameters. When the bottom FET
turns on, the current flows through the
FET structure rather than through the

body diode. During this time, the voltage is a function of the output current
and the resistance of the FET.
During the dead time, the negative
voltage coupled with parasitic ringing
can apply a negative voltage that exceeds
the maximum voltage ratings of the control IC. Trace B in Figure 2b shows the
phase node when the top FET turns off.
The output current flows through the
body diode of the bottom FET, and the
voltage drop across the FET is 0.76V.
With the ringing in the circuit, the phasenode voltage can exceed 1V, a voltage
applied directly to the control IC. When
the bottom FET turns on, the voltage
drops to approximately 0.1V (8A
0.013). Adding a Schottky diode in parallel with the bottom FET helps, but a
Schottky diode is large and expensive and
has little effect on the voltage. Trace C in
Figure 2b shows the voltage that occurs
with the addition of a large D-Pak
MBRD835L Schottky diode. The diode
reduces the voltage to 0.6V. With ringing, the control IC sees 0.7V.
www.ednmag.com
design
ideas
D
C
B
D, C, B:
20 nSEC
200 mV
A:
1 SEC
5V
(a)
Figure 2
(b)
Expanding the dead-time waveforms (a) leads to three scenarios (b): the unadorned buck regulator (Trace B), adding a Schottky diode (Trace C), and
the simple solution in Figure 3 (Trace D).
VIN
TPS5103
OUT_U
VOUT
LL
OUT_D
GND
Moving one resistor and adding a

small Schottky diode minimizes
the phase-node voltage.
Figure 3
The circuit in Figure 3 is small and inexpensive and significantly reduces the
phase-node voltage at the control IC. The
gate-drive resistor moves from the gate to
the source of the top FET. Following the
current from the IC as it charges and discharges the gate capacitance of the top
FET shows that moving the resistor has
no effect on the circuit operation. An
SOT-23 or an SOD-123 Schottky diode
with a current rating of 0.5A connects to
the control IC. As you can see in Trace D
of Figure 2b, when the voltage across the
FETs body diode goes to 1V, the Schottky diode clamps the voltage on the IC
to approximately 0.3V. The full output
current flows through the FET, and the
gate-drive resistor limits the current
through the Schottky diode. This solution is small and inexpensive and prevents erratic operation or damage to the
power-supply control IC.

Track multisite temperatures on your PC

Clayton Grantham, National Semiconductor, Tucson, AZ
he low-cost circuit in Figure 1 allows you to track four remote temperatures with thermistor sensors
through the parallel port on your PC.
This four-zone thermometer instrument
has a temperature range of 40 to
90C and a resolution of better than
1C. You can calibrate its accuracy to
within 1C over a 0 to 50C span and
within 3C over a 40 to 90C span.
Thermistors are low-cost, passive, rugged
components, making them a good choice
for temperature sensing. The signal-conditioning hardware in Figure 1 performs
a simple voltage division to partially linearize the thermistors. Temperature data
in the form of thermistor voltages goes
into Excel macros, and software performs
100 edn | April 18, 2002
a fifth-order-equation fit using calibration coefficients to convert the data into

Celsius temperatures. This Design Idea
focuses on the electronics in Zone 1; the
other zones behave similarly. You can implement one, two, three, or all four zones
without software modification.
All components have low power (quiescent current) consumption to minimize LPT1 sourcing requirements. Four
LPT1 outputs at D0 (Zone 1), D2 (Zone
2), D4 (Zone 3), and D6 (Zone 4) power
this application. The hardware typically
requires less than 162 A of current per
zone. Parallel-port drivers within your
PC generally source at least 400 A. Supervisory circuit IC1 monitors the voltage from the LPT1 port. The reset output
signal of IC1 goes back to the parallel port

at S7 for software error-checking at initialization. The software ascertains that
the hardware is present and that the minimum voltage from D0 of the LPT1 port
is greater than approximately 4.65V. Most
PCs have a 5V parallel-port interface, but
a few have only 3.3V available. For 3.3V
PCs, you need to scale the voltage options
of the components you use.
IC2 is a voltage reference for both the
RT1-R7 voltage divider and the ADC, IC3.
Inasmuch as IC2 is common to the divider and the ADC, you obtain accurate
ratiometric analog-to-digital conversion,
and gain, offset, and thermistor-interchangeability errors are at a minimum.
The low temperature coefficient of IC2
www.ednmag.com
design
ideas
(grades are available with lower than 10

ppm/C) ensures that the circuit exhibits
high accuracy in the environments that a
portable PC encounters. You should also
select R4 and R7 with thermal performance in mind. A 0.1% tolerance, 25ppm/C metal-film resistor is a good
choice. If you intend to use the circuit in
a temperature-controlled lab, then you
can use less expensive components. RT1
operates in a zero-power resistance
mode, in which self-heating errors are
negligible. RT1 and R7 form a voltage divider that only slightly linearizes the exponential equation of the NTC thermistors negative-resistance-versus-temperature relationship: RTRT0exp[(T0T)/
IC1
LM3724
4.63V
S1
(TT0)]. The software performs further

curve fitting.
IC3 and IC4 (the ADC block) perform
the voltage-measurement function. IC4,
a rail-to-rail op amp, buffers the R6-C3
lowpass filter. The serial output of IC3
(D0) connects to the parallel port at S3.
The converted (8 bits) voltage representing the temperature data, sampled from
the divider voltage, goes to the parallel
port. C0 of the parallel port controls the
timing of IC3s clock input. C1 of the parallel port controls IC3s CS input; a negative-going front starts the conversion.
Resistors R1, R2, and R3 help provide the
logic interface between IC3 and the parallel port. Pulling the thermistor con-
nections either above the PCs 5V supply

level or below ground could result in
damage to the circuit, the PC, or both. R4
and R6 provide some protection. However, to be completely safe, you should
isolate the thermistors from any external
voltage potential. With no thermistor
connected, the temperature reading assumes the zero-voltage temperature,
which is 40C.
IC1 also has a manual reset that provides direct user control for external triggering. If you depress the momentary
switch, S1, and select the Trig button on
the user form, then the circuit performs
a temperature measurement. The hardware turns off when the user form clos-
IC2
LM4130
4.096V
5
VCC
MR
RESET
GND
1,2
R4, 10k
4
VREF 5
VIN
C1
GND
0.1 F
2
IC3
ADCV0831
R1, 10k
R2, 100
R3, 10k 6
CLK
V+
D0
VIN 3
2
GND
CS
ZONE 1
C2
0.1 F
IC4
LMC7111
2
3 R5, 100
+
5
RT1
100k
R6, 10k
C3
1000 pF
R7
100k
LM4130
4.096V
LPT1
14
15
16
17
18
19
20
21
22
23
C0
C1
D0
S3
D1
C2
D2
C3
D3
GND
GND
GND
GND
GND
GND
24
GND
25
GND
D4
1
2
10k
4
VREF 5
VIN
C4
GND
0.1 F
2
ZONE 2
0.1 F
3
4
5
6
7
D5
8
D6
9
D7
10
S6
11
S7
12
S5
13
S4
RT2
100k
ADCV0831
10k
100
10k
CLK
V+
VIN
D0
GND
CS
1
2
3
2
5
LMC7111
100
3
+
10k
1000 pF
100k
LM4130
4.096V
4
VIN
0.1 F
10k
10k
VREF 5
GND
2
RT3
100k
ADCV0831
4
100
10k
CLK
V+
VIN
D0
GND
CS
ZONE 3
0.1 F
1
2
3
2
5
LMC7111
100
3
10k
1000 pF
100k
LM4130
4.096V
10k
4
VREF 5
VIN
C10
GND
0.1 F
2
Figure 1
10k
100
10k
0.1 F
RT4
100k
ADCV0831
4
5
6
CLK
V+
D0
VIN 3
2
GND
CS
ZONE 4
2
5
LMC7111
100
3
+
10k
1000 pF
100k
This PC-based thermometer derives its power from the parallel port and uses thermistors to sense four temperature zones.
102 edn | April 18, 2002
www.ednmag.com
design
ideas
es. The program control resides in

cel are available for familiar usage.
Excel (running under Office 2000)
The macros in the .xls listing contain
macros that perform I/O through
the basic interface features for capthe LPT1 port of the PC. The proturing the signal-conditioned thergram uses a free file Input32.dll
mistor-sensor signals. Within Modto bit-wise-control the parallel
ule 1, the declaration of Input32.dll
ports digital I/O. The author of
needs to include its directory path.
the .dll file is Jonathan Titus, ediThe code for input/output of temtorial director of Test and Meaperature data is within the usersurement World. You load Quadform module.
Zone.xls with its macros, connect
The macros also include a softthe circuit of Figure 1 to the parware-calibration routine that steps
allel port, and then run the Conusers through a temperature-caliThe user form, which floats in front
trolPanel macro. A user form (Figbration sequence. With the thermisFigure 2
of an Excel spreadsheet, measures
ure 2) pops up, overlaying the
tor inside a calibrated oven, you
spreadsheet, and connects temper- the temperature of four thermistors connected to LPT1.
right-click on the user form to initiature-measurement actions with
ate calibration. The cal spreadsheet
the electronics. Your possible options us- zone temperature measurement when of Figure 2 stores the raw calibration
ing the user form are single-temperature you press the Update button on the user data. The FitChart chart plots this raw
measurement, multiple-temperature form. Measurement data links to the cells data and displays a fifth-order-polynomeasurements separated by user-defined from columns A to G (named data) in mial trend-line equation. The user-form
time intervals, linked measurements that the spreadsheet when you press the code uses the equations coefficients to
append the data to an Excel spreadsheet, Linked button. When you press the Loop scale and display the temperatures in the
and externally triggered single-tempera- button, the circuit samples measurement user form.
ture measurements. You can download data in user-defined intervals. S1 exterthe spreadsheet and the .dll file from the nally triggers measurement data if you
Web version of this Design Idea at press the Trig button. By using macros
within Excel, all the graphing, analysis, Is this the best Design Idea in this
www.ednmag.com.
The user form displays a single quad- and data-storage utilities common to Ex- issue? Select at www.ednmag.com.
104 edn | April 18, 2002
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design
ideas
Circuit allows high-speed clock multiplication

Lukasz Sliwczynski and Przemyslaw Krehlik, University of Mining and Metallurgy, Krakow, Poland
n theory, synchronous clock multiplication is an easy task. A simFigure 1
ple PLL with two digital dividersone inserted just after the VCO
C7
5V
TRANSFORMER T:
10 nF
(voltage-controlled oscillator) and the
FOUR TURNS PRIMARY
SIX TURNS SECONDARY
B
second one placed directly at the input of
ON FERRITE-RING CORE
C1
R1
VCC
VCC
the phase detectormay do the job. The
C
10
nF
IC2
270
DIN
6 7,10,18, 1,2,3,4,8,9,11,
XC9572XL
flexibility of such a configuration allows
13,14,15,16,27,28
26,20,21
125 MHz
8
SCO
OUT
23
for clock multiplication by any rational
R9
C2
R2
IC1
SCO
2k
3.3V
10
nF
100
number. However, a problem emerges if
GS9015A
22
DIN
5
R6
you want to multiply a high-frequency
R7
R8
330
330 C6
17
A
12
clock. Standard, integrated PLLs, such as
1.5k
10 nF
R4
the 74HC/HCT4046 and NE564, do not
LOOP
100 MHz
R3
2.7k
910
accommodate such fast clock signals;
R5
C4
C3
C5
theyre limited to frequencies lower than
10 nF 5.6 pF
10 nF 2k
approximately 60 MHz for the NE564.
Although you can implement almost all
PLL subcircuits by using fast programmable logic, such as CPLD or FPGA circuits from Xilinx (www.xilinx.com), a big
problem exists in providing the proper Using this simple circuit, you can easily and cheaply multiply high-frequency clock signals.
high-frequency VCO. Two obvious possibilities exist: Order the VCO from a
company specializing in high-frequency
circuits, or build it yourself. The
Figure 2
first approach can be costly; the
second requires specialized knowledge
and can be frustrating for an inexperienced designer. The circuit in Figure 1 offers yet another possibility.
Circuit allows
high-speed clock multiplication ..................77
Differential amp needs
no power source ............................................78
Printer port activates
CMOS switches ..............................................80
Circuit improves on
temperature measurement ........................80
Add voice commands
to your CAD system ......................................84
www.ednmag.com
3 nSEC
80 nSEC 12.5 (MHz)
This scope photo shows some key waveforms in the circuit of Figure 1.
The circuit is based on IC1, Gennum

Corps (www.gennum.com) GS9015A
clock-recovery IC, an ECL-based circuit
that can operate at frequencies to approximately 400 MHz. You normally use
such an IC to extract clock information
from a digital NRZ data stream with the
aid of an input divider. The clock-recovery circuitry is in principle a form of PLL

with a special type of digital phase comparator. The comparator allows for VCO
phase adjustment only when high-to-low
or low-to-high transitions are present in
the input signal. This property of the
May 2, 2002 | edn 77
design
ideas
clock-recovery circuit allows you to exploit it as a clock multiplier. If you apply

a signal with 50% duty cycle instead of a
normal NRZ data stream to the input of
the clock-recovery circuit, the circuit attempts to interpret the signal as a sequence of N consecutive zero and one
symbols and controls its VCO in such a
way as to produce a clock transition for
each symbol. The result is a multiplication of the input frequency by the factor
2N. You set the actual multiplication coefficient by setting the VCOs free-run
frequency close to the desired output
clock frequency. To avoid locking of the
clock-recovery circuit to some undesired
multiplication coefficient, you should

make the VCOs tuning range narrow.
This design is applied to a 4B5B encoder, which needs to derive a 125-MHz
clock from a 100-MHz master-clock signal; therefore, it needs a multiplication
factor of 5/4. To realize this operation,
you must first divide the 100-MHz clock
by 8 and then multiply the result by 10.
(Note that only even multiplication coefficients are possible using the concepts
in this Design Idea.) Figure 2 shows some
key waveforms the circuit produces. The
complete design implements the remaining part of the encoder with IC2, a
3.3V XC9572XL CPLD IC to match log-
ic levels. Resistor R3 and capacitors C3 and

C4 form the loop filter, and resistors R4
and R5 set the free-run frequency of the
VCO. The circuit in Figure 1 is simple
and easy to build. The only trimming it
requires is the initial setting of the VCOs
free-run frequency (close to 125 MHz).
You perform this trim by observing the
output waveform with an oscilloscope
and adjusting variable resistor R5 with R2
shorted.

Differential amp needs no power source

R4
10M
true-differential, power-sourcefree, high-input-impedance
Figure 1
C
amplifier with bipolar outC1
C3
S1
10 F
put would present distinct advantages in
0.1 F AMPLIFIER GAIN100
R3
A
100k
D
B
2
2
remote devices. Such an amplifier, with
V2
IC1 7
1N914B
6
S
MAXits bipolar output, would be a better
3 7614
R5
E
+
V1
4
choice than a unipolar, 4- to 20-mA deD1
10k
R1
1N914B
GROUND
100k
vice. It would also improve on commonR2
COAXIAL
10M
C2
C4
mode performance. In Figure 1, a MaxCABLE OF LOW
10 F
0.1 F
LEAKAGE
im MAX319 analog switch, IC2, feeds the
10V
DISC
CURRENT
power from the coaxial signal cable to the
charge-holding capacitors, C1 and C2.
The analog switch injects both positive4.5 TO 8V
1
8
and negative-polarity signals into the
SQUARE PULSES
charging circuit when its Control signal
7
8V
2
OUTPUT
C5
LOW-LEAKAGE
has a high (TTL) level. At the same time,
0.1 F
SAMPLE-ANDCONTROL (TTL)
6
3
the output uses a sample-and-hold caHOLD CAPACITOR
SENSE
CHARGE
pacitor to retain the last analog signal
8V
4
5 5V
IC2
during the charging cycle. Thus, the cirMAX319
cuit never loses the signal, as long as the
charging and sensing cycles maintain
A high-impedance differential amplifier is useful in remote locations, because it requires no local
timing within certain limits.
You can increase the values of C1 and power supply.
C2 if the sensing time is considerably
greater than the charging time. Switch S1 ance for IC1, a low-bias-current, low- plification with a range of 10 pA to 1
places the feedback resistor, R4, either in power MAX7614 amplifier. This amplifi- nA, using only R4 for the current-to-volta direct connection to the sample-and- er is an improved version of the ICL7611. age conversion.
hold capacitor, C5, or before R5 to form This amplifier circuit was useful for theran R5-C5 lowpass filter. In either case, R5 mocouple-signal amplification without
is a protective resistor during the charg- cold-junction correction. You can also Is this the best Design Idea in this
ing period, ensuring 10-k load resist- use it for bipolar, low-current signal am- issue? Select at www.ednmag.com.
78 edn | May 2, 2002
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design
ideas
Printer port activates CMOS switches

J Jayapandian, IGCAR, Tamil Nadu, India
VOLTAGE DOUBLER
he cost-effective design in Figure
1 provides control for CMOS
Figure 1
8
IN914
2
switches without the need for
LPTICL7660
an external power supply. Analog switch+
PORT
3
+
es such as those in the MAX4663 are idePINS
1 F
100
al for use in low-distortion applications.
2
They are preferable to electromechanical
100
VL
V
3
relays in automatic test equipment or
NC
S
2
other applications in which you need
SWITCH ENABLE
4
OUTPUT
NC
current switching. The CMOS switches
S
3
use lower power, consume less board
CURRENT INPUT
space, and are more reliable than electroS1 NO
SOURCE
mechanical relays. The MAX4663 quad
S4 NO
switch features 2.5 maximum on-re

sistance, 5-nA maximum leakage current
MAX4663
18
at 85C, and 56-dB off-state isolation at
V
GND
1 MHz. They also offer break-before25
make switching. The switches operate
MAX4663
from a 4.5 to 36V supply or from dual
LOGIC S1 AND S4 S2 AND S3
4.5 to 20V supplies.
ON
0
OFF
In Figure 1, the switches mount in and
OFF
ON
1
derive power from the PCs LPT port.
The design provides as much as 50 mA of The LPT port powers a current-reversal circuit, using CMOS analog switches.
current, with current-source compliance
as high as 10V. The circuit uses a simple have complementary pairs (normally switches. At the LPT port, the D0 and D1
voltage-doubler circuit, the negative- open and normally closed). This config- bits (pins 2 and 3) power the circuit in
voltage-converter ICL7660, for the sepa- uration simplifies the design, with single- Figure 1. Bit D2 (pin 4) sets the switchrate V supply and the VL logic supply. enable-bit operation (the switch-enable enable/disable function. For data word
The current source can supply as much inputs are shorted together as a single en- 0x03, bit D2 is low, enabling the normalas 200 mA at 10V. Figure 1 shows a cur- able). You can download a LabView Vir- ly open contacts; for data word 0x07, and
rent-reversal application in a low-tem- tual Instrument program from the Web D2 goes high, enabling the normally
perature-resistivity experiment. The de- version of this Design Idea at www.edn closed contacts.
sign draws only a few tens of mag.com. The program latches the LPT1
microamperes from the PCs parallel port at the address 0x378 with data for Is this the best Design Idea in this
edn02043di-28931
port. The MAX4663 CMOS switches forward and reverse operation of the issue? Select at www.ednmag.com.
Heather
Circuit improves on temperature measurement

Alexander Bell, Infosoft International Inc, Rego Park, NY
hen current pulses with a stable IHIGH/ILOW ratio modulate a
semiconductor junction, the ensuing voltage difference (for example,
VBE for a bipolar transistor) is a linear
function of the absolute (Kelvin) temperature, T. You can use this truism to
make accurate temperature measurements. Technical literature has thor-
80 edn | May 2, 2002
oughly covered the relationship (references 1 to 4) and has numerous implementations. This Design Idea suggests
some areas for improvement and design
variations on the basic idea. The principal equation describing the phenomenon
is as follows: V86.4Tln(IHIGH/
ILOW), expressed in microvolts. Setting the
current ratio IHIGH/ILOW 10 results in V
of approximately 200 V per degree. The

key issue in the practical implementation
of the idea is to switch current with a
highly stable IHIGH/ILOW ratio, which you
can do by using a number of discrete
components. This Design Idea suggests
a digitally controlled and integrated approach (Figure 1).
The current switching with a stable
www.ednmag.com
design
ideas
IHIGH/ILOW ratio, comes from a DAC with

current outputs. The typical DAC
VBE1
Figure 1
Q1
has two current outputsa direct
C1
I1 and a complementary I2. These outputs
I1
allow for simultaneous dual-channel
temperature measurements. The current
DAC
VBE2
+
C2
VIN
ratio IHIGH/ILOW is a function of the input
I2
digital code, DI; you could program this
DI
code using a microcontroller. ObviousQ2
ly, you can use the circuit for single-channel temperature measurements, by simply ignoring the second output. If you
need more than two channels, then use The DAC modulates transistors Q1 and Q2 with its two current outputs; VBE is a linear function of
additional DACs or use a multiphase absolute temperature.
DAC (Reference 5). The circuit in Figure
1 works as follows: The output
SIGNAL-PROCESSING MODULE
Figure 2
currents, I1 and I2, are functions of
the input digital code, DI, and the input
C1
AMPLIFIER/
IC1
CONDITIONER,
voltage, VIN:
MICROR-2R
TRACK-ANDADC
CONTROLLER
I1(VIN/REQ)(DI/2N), and
MULTIPLYING
HOLD
+
DAC
AMPLIFIER,
C2
I2(VIN/REQ)(2NDI)/2N,
MULTIPLEXER
VIN
IC2

where REQ is the equivalent transfer resistance of the DAC, and DI is the decimal equivalent of the input binary code.
The full measurement cycle consists of
two phases, switching codes from D1 to
D2. Assuming D1D2, then the current
ratio IHIGH/ILOW for output I1 is equal to The two op amps, IC1 and IC2, provide virtual grounds for both current outputs of the DAC.
D1/D2. The current ratio for the second
output I2 is equal to (2ND2)/(2ND1). should choose the proper value for VIN VBE measurements. You can implement
For a 10-bit DAC (N10), choosing (typically 2.5 to 10V). Alternatively, to that portion of the circuit by using an
D1931 and D293, the ratio IHIGH/ILOW obtain the desired IHIGH, you could use an amplifier/conditioner, a track-and-hold
on both outputs is 10.01, which is close additional series resistor, RS (not shown amplifier, and an ADC controlled by any
to the standard (references 3 and 4). in Figure 1), connected between the volt- general-purpose microcontroller. ReferFor an 8-bit DAC, these numbers are age source and the DAC input. The R-2R ences 3 and 4 offer hints on implemenD1233 and D223, which results in a ladder has an equivalent input resistance, tation.
ratio IHIGH/ILOW10.13 on both outputs. R, which does not change with the digiIts important that the ratio be substan- tal code. With the additional series resis- References
1. Belousov, Alexander, Temperature
tially immune to variations in the input tor, the equivalent transfer resistance bevoltage, VIN. Thus, any unregulated volt- comes RRS. Note that this series resistor Measurement Device, SU Author Cerage source is suitable for the circuit. The may be of almost any type, because its tificate 1599674, registered June 15, 1990.
source needs only short-term stability impact on the current ratios accuracy is
2. Belousov, Alexander, Temperature
during the measurement cycle. Besides, limited.
Measurement Device, SU Author Cermany modern DACs integrate on-chip
In a practical implementation, you tificate, registered May 1, 1991.
voltage references.
should take into consideration the finite
3. Steele, Jerry, Sense temperatures
You should note that other IHIGH/ILOW value of VBE on the DACs output, be- without Calibration, Electronic Design,
ratios are applicable. Moreover, in gen- cause its variation with temperature may6 13, 1998, pg 130.
eral, it is unnecessary to have the same could affect the accuracy of the measure4. Setton, Joel, Multichannel tempercurrent ratios for both outputs. Thus, you ment. If the DAC has internal current ature measurement system, Electronic
could set the sensitivity to different val- sources, you can use the circuit of Figure Design, July 10, 2000.
ues for the two channels. Higher ratios 1 as-is, because the VBE has a limited ef5. Belousov, Alexander, Multiphase
result in greater sensitivity, but self-heat- fect on the current ratio. In the case of us- DAC modifies R-2R lader, EDN, Jan 18,
ing effects impose certain limitations on ing an R-2R DAC, the circuit in Figure 2 1996, pg 87.
IHIGH, and noise levels set a lower limit on is more appropriate. The two op amps,
ILOW. Thus, 100 and 10 A are typical val- IC1 and IC2, maintain virtual grounds on
ues for general-purpose bipolar transis- both current outputs, thus preserving the
tors. As most general-purpose R-2R high accuracy of the current ratios. The Is this the best Design Idea in this
DACs have REQ of 10 to 100 k, you rest of the circuit in Figure 2 performs issue? Select at www.ednmag.com.
_
82 edn | May 2, 2002
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design
ideas
Add voice commands to your CAD system

he first time I activated the Language Bar (Speech Tools) in my Microsoft Word 2002 and started dictating this Design Idea, the on-screen title
displayed cat instead of CAD. By using the Add/Delete Words feature, Ive trained the system to
recognize the CAD acronym.
This was my first experience
with the MOSR (Microsoft Office Speech Recognition) tool,
which is part of the latest Microsoft Office XP package. Its
main operational modes are
dictation and voice command.
This Design Idea shows how to
add a practical VCI (voice-command interface) to the simple
CAD system inherent in MS
Word 2002 applications. Reference 1 described a simple version of such a CAD for
schematic entry.You can download some macros from
Figure 1
the Web version of this
Design Idea from www.ednmag.com. The macros, grouped and
stored in the MyCAD.dot file, extend
CAD functions:
Module mod_View contains
macros to set the drawing environment.
Module mod_Symbol contains
macros to perform operations on
Symbol objects.
The next level of CAD-system improvement is to add the custom VCI, enabling you to run macros via voice commands. Before use, the system prompts
you to use the Voice Training session,
which lasts approximately 15 minutes. As
you read the text on the screen, the system analyzes your verbal patterns to build
the Default Speech Profile. A longer session results in greater accuracy of speech
recognition. The Add/Delete Words feature enables the MOSR engine to recognize special terms and technical jargon.
Formatting the title provides a good example of practical use of the MS Word
2002 built-in Voice Commands, which
correspond to its Menu and Toolbars
buttons Text. First, I selected the whole
84 edn | May 2, 2002
sentence by saying select all, then I converted it to boldface by saying Bold.

Then I changed the font to Arial by saying font, and, when the drop-down
menu appeared, I pronounced Arial.
you downloaded to the appropriate modules. The screen should look like the
snapshot in Figure 1. From the Debug
menu item, select Complete Project,
and then close the Visual Basic Editor
window and save the file under the name MyCAD.dot
using the Save As menu
option. Add a custom toolbar by selecting from the
menu ToolsCustomize
ToolbarsNew. When a
prompt appears, type the
name for the new toolbar as
MyCAD Symbol Commands and make it available
to MyCAD.dot. Add toolbar buttons related to the
macros stored in MyCAD.
dot. For each button, edit the
button text; it defines the
Custom Voice Command.
The toolbars should finally
This Visual Basic Editor screen has the template file
look like the snapshot in
MyCAD.dot with two standard modules.
Figure 2. Save the file and
close MS Word 2002. You
Finally, I set the font size to 14 points by can consult Microsoft Office Help utility
saying font size and then 14, and I for more details on how to add custom
then underlined the title by saying un- toolbars and buttons.
derline. You can add custom VCI by folPut the file MyCAD.dot into the MS
lowing several steps:
Word or MS Office start-up directory.
First, start MS Word 2002 and open a Typically, the path is C:\Program
new file. Go to the Visual Basic Editor Files\Microsoft Office\Office10\Startup.
screen (shortcut: AltF11); add two Then, start MS Word 2002, enable the
standard modules, mod_View and macros in MyCAD.dot upon the system
mod_Symbol; and copy the macros prompt, open a new document, and test
TABLE 1VCI-TEST RESULTS (100 SAMPLES PER COMMAND)

Custom commands
Built-in commands:
menu and toolbarsbutton text
Voice commands
Grid lines
Add labels
Flip horizontal
Increase
Reduce
Rotate right
File
Edit
View
Insert
Tools
Help
Bold
Underline
Cancel
Correct execution Nonrecognized

100
0
100
0
100
0
100
0
100
0
99
1
100
99
99
100
100
98
95
100
100
0
1
1
0
0
2
4
0
0
Misinterpreted
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
www.ednmag.com
design
ideas
the VCI with both built-in and

custom voice commands. Its
advisable to use a set of highly phonetic, distinctive words
or phrases for VCI. If not, distortion and noise can lead to
misinterpretation of the voice
command by confusing it with
another voice command. I
tested the CAD with a VCI on
a PC clone with a 600-MHz
Athlon CPU. The system has
256 Mbytes of SDRAM-133
and runs Microsoft Office XP
Professional under the Windows 2000 operating system.
The voice-command execution delay is approximately 1 sec. For faster
Figure 2
execution, you can use
a faster CPU. For audio input,
this design uses an inexpensive multimedia microphone. Table 1 shows sample
test results for both built-in and custom
commands.
The accuracy increases to almost 100%
for the sample set of commands when
86 edn | May 2, 2002
A Microsoft Word 2002 display has a language bar and two

custom toolbars.
you use a Plantronics (www.plantron

ics.com) headset with noise-cancellation
features that comes with Microsofts
SideWinder game package. For more information on natural-language input
technology in Office XP, refer to Mi-
crosoft Guidelines on the

Web. The Web site has a link,
Hardware Guidelines for
Speech Technologies. Note
that, when you enable macros
in MS Word or other applications, some macros could
cause harmful actions, and
some may contain viruses.
You use the macros at your
sole risk without warranties.
To use the macros in the
mod_Symbol section, you
should uncheck the box Automatically create drawing
canvas when inserting AutoShapes. Go to the tabbed
Dialogue:ToolsOptions
General.
Reference
1. Bell, Alexander,Add CAD functions
to Microsoft Office, EDN, March 21,
2002, pg 94.
www.ednmag.com
design
ideas
Method provides self-timing

for synchronous rectifiers
Giampaolo Carli, SAE Power Co, Saint-Lazare, Quebec, PQ, Canada
ynchronous rectifiers are MOSPWM
PWM
MAIN
FETs, driven in such a way as
CONTROLLER
CONTROLLER
Figure 1
SWITCH
to perform a rectifying function. They often take the place of diodes in
+
FIXED
the output-rectification stage of switching
OR
MAIN
ADAPTIVE
SYNCHRONOUS
power converters, because of their lower
SWITCH
DELAY
VIN
RECTIFIER
on-state power loss. In power circuits, synchronous rectifiers are often complicated
+
to use because of timing issues. Some tech
niques attempt to predict the correct timVIN
ing by following the same drive signal that
ZERO-CROSS
SYNCHRONOUS
controls the main switching element of the
DETECTOR
RECTIFIER
circuit. Other techniques sense the current

(a)
(b)
in the FET in various ways and then act on
that information. Figures 1a and 1b show These topologies often exhibit a delayed turn-off of the synchronous rectifier, resulting in considersimplified representations of these alter- able reverse current. The current-reversal timing depends on loading conditions (a). The zero-cross
native techniques, applied to the forward/ current causes the rectifier to turn off too late (b).
buck topology. During the off-time of the
main switch, the rectifier conducts from
Unfortunately, if the signal from the connection of the rectifier. With some
source to drain. At the beginning of the control circuit appears at this time, the minor additional circuitry, this single
switching cycle, the main switch turns on synchronous rectifier turns off only af- component accomplishes by itself the
and begins driving current into the recti- ter various delays (especially, the MOS- two main functions necessary to elimifier. Eventually, the current in the rectifier FETs turn-off delay). Because a large nate the turn-off-delay problem.
falls to zero and begins to reverse, flowing di/dt is involved in the turn-off, the unThe first function is to determine the
from drain to source. This instant is the desirable consequence is that the rectifi- instant that the current falls close to zero.
optimum time to turn off the rectifier.
er turns off only when considerable re- At that time, the core comes out of satuverse current is flowing. If you use the ration and blocks voltage. This voltage
concept in Figure 1a with a fixed delay, also appears on the additional winding,
Method provides self-timing
the turn-off of the synchronous rectifier flagging to the sense circuit that it must
for synchronous rectifiers ............................99
rarely occurs at the optimum time, be- immediately turn off the MOSFET. The
Sampling peak detector
cause the current-reversal timing de- second function is to significantly slow
has shutdown feature ................................100
pends on loading conditions. Adaptive- the di/dt of the current during this cruCircuit provides bidirectional,
delay techniques that compensate for cial turn-off time. The saturable cores
variable-speed motor control ..................102
changes in delay with load are complex. operation allows wider tolerances in timThe concept in Figure 1b has similar ing and more flexibility in the design of
Software reset uses I2C I/O port ..............104
complications. The zero-cross current the synchronous-rectifier driver, resultSupply uses ac to generate 5V,
detector is often relatively slow, so, in ad- ing in far fewer and less expensive compower-on reset ............................................106
dition to the cited FET delays, it causes ponents. The core can be small, even for
Routine automates pattern/
the synchronous rectifier to turn off too high-power applications, and should be
sequence detection ....................................108
late. Figure 2 shows a simple way to mod- of nonsquare-loop ferrite material. Regify the concept in Figure 1b. In this case, ular power ferrite is much less expensive
you introduce a saturable core with an and lossy than its square-loop counteradditional sense winding in the drain parts. The nonsquare-loop material al-
www.ednmag.com
May 16, 2002 | edn 99
design
ideas
lows the core to come out of

saturation when
Figure 2
the current is
MAIN
PWM
SWITCH
CONTROLLER
still slightly positive in the
rectifier, thus giving a slight
+
advance warning.
Because of the nonlinear
SATURABLE
SENSE AND
response of the saturable
CORE
DRIVER
VIN
core, the secondary sense
winding has far fewer turns
SYNCHRONOUS
RECTIFIER
than the corresponding lin
ear sensor in Figure 1b and
virtually no loss in the sensing and clamping circuits A low-cost, saturable core in the drain circuit of the synchronous rectifier
for its secondary current. introduces a self-timing feature in the circuit.
These considerations improve response speed and reduce losses in the high-current outputs. Note that this
simple circuit is versatile; you
can apply it to various
switches and rectifiers in
most power-circuit topologies. The concept can even
improve on well-known softswitching techniques.
in this issue? Select at
www.ednmag.com.
Sampling peak detector has shutdown feature

ou face a serious problem in using
VDD
VDD
IN+
IN+
IC2
IC1
a slow ADC with a fast peak detec5V DC
INPUT
5V DC
1
6
1
6
MAX4231
MAX4231
tor. The circuit in Figure 1 allows a
slow ADC to measure a fast, sampled sigVSS
VSS
SHDN
SHDN
+
+
nal peak. The 100-MHz peak detector for
2V DC
2V DC
2
2
5
5
ultrasonic-pulse sampling uses a fast

D1
MAX4231 amplifier from Maxim (www.
1N4148
IN
IN
maxim-ic.com). This amplifier has a
3
4
3
4
OUTPUT
OUT
R1
C1
shutdown feature that facilitates power
10k
0.1 F
savings without losing the sampled inMEASURE
PEAK
formation. When the circuit samples a
DETECT
IC3
IC3
peak with a low-TTL-control input, the
4
1
3
2
CONTROL
74HC14
74HC14
output of the peak-detector amFigure 1
plifier shuts off, and the output
amplifier switches on to measure the output signal. This technique reduces pow- This circuit allows you to use a slow ADC to measure fast peaks and saves power to boot.
er consumption by nearly 50%, because
only one of the amplifiers is active at any
TABLE 1CIRCUIT FUNCTIONS AND AMPLIFIER MODES
given time. Table 1 shows the circuit
Function
Amplifier 1
Amplifier 2
Control input
functions and the amplifier modes as a
Signal-peak sampling
On
Off (shutdown)
TTL 0 (0V)
function of the control inputs status.
Peak measurement
Off (shutdown)
On
TTL 1 (2.4 to 5V)
The most important advantage of the
circuit is that it prevents sampling of an- interval, an impossible operation with a shown) without R1 to discharge the caother input peak before a measurement conventional peak-detecting circuit. You pacitor to ground before sampling a new
takes place. The first peak-detector am- select the R1 and C1 values for the desired input-signal peak.
plifierin shutdown modedoes not time constant to hold the peak and then
permit the reading to change. This fea- let it decay according to the RC time conture helps a slow ADC to monitor a high- stant. If peak decay is undesirable, then Is this the best Design Idea in this
speed sampled peak in a desired sampling you can use a transistor switch (not issue? Select at www.ednmag.com.
100 edn | May 16, 2002
www.ednmag.com
design
ideas
Circuit provides bidirectional,

variable-speed motor control
uring the development of systems that include small motors, a
simple, bidirectional motor controller with speed adjustment
Figure
may be helpful. Figure 1
shows such a controller. The circuit uses
everyday components whose tolerances
and ratings are unimportant as long as
they sustain the required voltage, current,
and power. The circuits advantages are
low cost, small size, flexibility, and ready
availability. You can assemble it in less
than an hour on a board measuring approximately 75100 mm; its height is
less than 12 mm. A transistor-based Hbridge allows two directions of rotation.
A chopper controls the upper arms of the
H-bridge, thereby enabling the speed adjustment. To start the rotation in one direction, you must connect one of the inputs (In CW or In CCW) to 0V. You can
do this through switches, transistors, or
open-collector TTL circuits, for example.
If both inputs are high (no command),
transistors Q2 and Q4 do not conduct,
and the motor stops. The motor receives
a slight braking action from the pulsing
Q1 and Q3 transistors.
If one input is low (connected to
0V)for example, In CW or In CCW
the corresponding transistor, Q2 or Q4,
conducts, with base current limited by R1
and R4. The pulse signal to the base of Q1
TON=160 SEC
TON=25 SEC
2
(a) TOFF=5 SEC
(b) TOFF=150 SEC
The position of the wiper on the speed-control

potentiometer determines the duty cycle of the
chopper circuit. When it is fully down, 0
(a); when it is fully up, 1 (b).
or Q3 short-circuits to 0V, thus shutting

off Q1 or Q3. On the opposite side, Q4 or
Q2 does not conduct, but Q3 or Q1 receives pulses from the chopper through
D2 or D1 and R6 or R5. Thus, Q3 or Q1 conducts each time transistor Q5 is on. The
chopper uses a 555 timer circuit, IC1,
connected as an astable multivibrator.
The zener diode, D7, and R10 limit IC1s
power-supply voltage to the maximum
allowable: 15V. The timing capacitor, C2,
charges through R11, the upper part of the
potentiometer R12, and zener diode D7.
The discharge takes place through the
lower part of R12. Using for the position
of R12s wiper (middle: 0.5; down:
0; up: 1), the charging time is
TON0.693C[R11R12(1)], and the
discharge time is TOFF0.693CR12.
The total time of one period of the
chopper is thus TONTOFF0.693C[R11

R12(1)]0.693C(R11R12). The
output signal on Pin 3 is a square wave
with nearly fixed frequency and adjustable duty cycle. In Figure 2a, the potentiometers wiper is fully down (0).
In Figure 2b, the wiper is fully up (1).
Q5 and Q6 adapt the voltage level to drive
the bases of Q1 and Q3, which conduct
only in the time when the output (Pin 3)
of the 555 is high (TON). This conduction
adjusts the rotational speed. Diodes D3 to
D6 protect the transistors Q1 to Q4 against
inductive voltage peaks. The fuse, F1,protects the whole circuit against overcurrent conditions. Capacitor C3 between
VCC and ground acts as a kind of energy
tank that filters out the current peaks.
The circuit was a help in determining
speeds or gear ratios to use during test
and adjustment of prototypes on small
machine tools. The transistors should
preferably be Darlington types, adapted
to the power-supply voltage and the motor current. (Dont forget the high inductance of the motor.) Select resistor R10
and the zener diode according to the
power-supply voltage, VCC.
R10
V DC
Figure 1
5.1k
D1
D3
Q1
R1
R2
5.1k
5.1k
Q3
F1
IN CW
D2
D5
D4
Q2
C3
1000 F
Q5
R6
R8
5.1k
R3
R4
5.1k
R9
IN
CCW
Q4
0V
R11
1k
8
IC1
Q6
D6
D7
5.1k
5.1k
470
R7
5.1k
R5
R12
10k
D8
5.1k
C1
10 nF
C2
22 nF
NOTES:
Q1, Q3=TIP142.
Q2, Q4=TIP147.
Q5=BC161, BC556, 2N3906.
Q6=BC160, BC546, 2N3904.
IC1=555 TIMER.
D3 TO D6=BYV26E.
D1, D2, D8=1N4148, 1N4007.
D7=15V, 0.4W ZENER.
You can set a motors rotational direction and speed using this simple circuit.
102 edn | May 16, 2002
www.ednmag.com
design
ideas
Software reset uses I2C I/O port

Bob Marshall, Philips Semiconductors, Sunnyvale, CA
ou can use the circuit in Figure
VDD
1 to allow the I2C or SMBus to conVDD
trol device resets in a system by usR R
D D
ing the PCA9554 I2C I/O-port IC. NorVDD
I/O0
mally, a reset function takes an active-low
SCL
I/O1
SCL
signal. On power-up of the PCA9554, the
I/O2
TO DEVICESDA
I/O3
SDA
IC sets all the I/O pins as inputs. The 4.7RESET PINS
A0 PCA9554 I/O4
k pull-down resistor on each I/O enI/O5
A1
sures that all the active-low reset pins are
I/O6
A2
initially in a low state during power-up.
I/O7
VSS
You can now program the I2C controller
4.7k 4.7k 4.7k 4.7k 4.7k 4.7k 4.7k 4.7k
to bring all or some of the external devices out of the reset condition.
Figure 1
Figure 2 shows additional details
of the I/O internal structure. The PCA9554 has four internal registers. Register This circuit allows the I2C or SMBus to control device resets in a system.
0 is the input-port register. Register 1
controls the output-port register. RegisOUTPUT-PORT
ter 2 is a polarity-inversion register, and
REGISTER DATA
VDD
CONFIGURATION
Register 3 is the configuration register. All
REGISTER
DATA FROM
the registers, except Register 2, are iniD
Q
SHIFT REGISTER
Q1
BIT
100k
tially set to all logic ones (high).
N
WRITE-CONC
Q
K
When you apply power to VDD, an inFIGURATION
TO DEVICEPULSE
I/ON
OUTPUT-PORT
RESET PINS
ternal power-on reset holds the
REGISTER
PCA9554 in its initial state until VDD
EXTERNAL
D
Q
Q2
4.7k
BIT
reaches approximately 1.5V. The powerN
WRITE
CK
Q
on condition sets all the I/O pins
PULSE
VSS
Figure 2
INPUT-PORT
as inputs, so Q1 and Q2 are off.
INPUT-PORTREGISTER
REGISTER
The IC has a 100-k internal pull-up reD
Q
DATA
BIT
sistor on each I/O pin. The 4.7-k exN
READ
CK
Q
ternal pull-down resistors hold all the atPULSE
POLARITYTO INT
tached devices in a reset state. The I2C
INVERSION
REGISTER
bus can now control which devices can
POLARITYREGISTER
D
Q
come out of the reset state. The I2C bus
BIT
DATA
WRITEN
uses unique addresses for slave devices
POLARITY
CK
Q
PULSE
on the bus. The PCA9554 uses an address, 0100xxx R/Wn, where xxx is the
level of A2, A1, and A0. To communicate The details of the I/O structure of the circuit in Figure 1 show four internal registers.
with the PCA9554, the bus master must
first send the device address, a command
00: Write 00 to the configuration reg- uration register. Another feature of the
byte that addresses one of the four inister, which sets all I/O as outputs; PCA9554 is that it remembers the last
ternal registers, and then the data. After
SP: Stop bit generated by the bus mas- command byte. Subsequent writes to the
each byte sent from the I2C master, the
configuration register require only a 2ter.
slave device automatically generates an
The default condition of the output byte operation, provided that no other
acknowledge signal on the I2C bus. The register is all logic ones (high). If you command register is addressed. For exmaster then sends the next byte. The want to bring devices out of the reset state ample, the following command sequence
command sequence to bring all the de- one at a time, simply change the pattern brings four devices out of reset (devices
vices out of reset at once is:
written in the configuration register. Any attached to I/O0 through I/O3) and then,
ST: Start bit generated by the master; bit left at logic one in the configuration on the subsequent write, brings the rest
40: Write to slave address (A0 to A2 register keeps the corresponding output of the four devices out of reset:
are all low in this example);
ST: Start bit generated by the master;
low (in reset). To place any device into re03: Write the next byte to the config- set, the I2C bus simply writes a logic one
40: Write to slave address (A0 to A2
into the corresponding bit in the configuration register;
are all low in this example);
104 edn | May 16, 2002
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design
ideas
03: Write the next byte to the configuration register;

F0: Set I/O0 through I/O3 as outputs;
SP: Stop bit generated by the master;
40: Write to slave address;
00: Set all I/O as outputs;
SP: Stop bit generated by the master.
If you want to control more than eight

devices, you can use the 16-bit I/O-port
PCA9555 IC. Using the A0 to A2 address
pins and the PCA9555, you can control
as many as 128 devices, using the I2C bus
or the SMBus.You can find additional information about the I2C bus, including
the bus specification, at www.semicon

ductors.philips.com/buses/i2c/support/.
For information about the SMBus, you
can go to www.smbus.org/specs/.
Supply uses ac to generate 5V, power-on reset

Greg Sutterlin, Maxim Integrated Products, Sunnyvale, CA
he need often arises for a
5V
D1
C1
low-cost logic supply for
R1
powering microcontrollers
and related circuitry in whiteSHUNT
goods products, such as indusIC1
trial controllers and sensors.
MAX6330L
+
VAC
C2
D2
RESET
RESET
These applications usually include 24 or 115V ac or
GND
Figure 1
higher levels of ac voltage
for conversion to 3.3 or 5V dc.
The simplest approach to generating low-current logic-supply This SOT-23 IC with low-cost external components prolevels is to apply the rectified and vides a combination of power-on reset and an efficient
filtered ac input to a high-input- logic supply.
voltage linear regulator. However, power dissipation in the regulator can rectify the ac voltage before applying it.
be considerable, even for modest load Typically, a capacitor follows the rectificurrents. A standard shunt regulator also er to hold the charge during off cycles.
dissipates notable amounts of power in The design in Figure 1 uses a simple halfthe limiting resistor. A switching regula- wave rectifier to save cost. C1 is the transtor minimizes power dissipation, but that fer capacitor, and C2 stores energy. D1 acts
type may be impractical for cost-sensitive as a half-wave rectifier, and D2 discharges
designs. As an alternative, consider the the transfer capacitor during negative cyac-coupled approach in Figure 1. The cir- cles. R1 limits surge current during the
cuit suits applications in which 24V ac is discharge of C1 and, if applicable, during
available. With proper safety precautions, high-voltage transient testing.
Several simplifications help to approxyou can apply the circuit to double-insulated white goods and other products imate the available output current. Asthat require a logic supply for control or sume 0V forward drops in the diodes and
0V shunt voltage in the IC regulator.
monitoring functions.
To transfer energy to the regulator with With, for example, a 60-Hz sinusoidal innegligible power loss, the circuit uses a put of 24V rms amplitude (VPEAK
coupling capacitor in conjunction with 33.94V), you calculate as follows:
an IC containing a shunt regulator and Peak current in C1 isIPEAK(C1)
power-on-reset circuitry. Available with C1(dVS/dt)C1[VPEAK(dsin(t)/dt)]
50-mA maximum output-current capa- C1[VPEAK(cost))]C1VPEAK.
Thus, with C13 F, 377.1 radibility in 3, 3,3, and 5V shunt-voltage versions, IC1 also includes a power-on-reset ans/sec, and VPEAK33.9V, IPEAK38.4
function. Because IC1 is an active shunt mA. The rms charge current (IRMS) in C1
versus a passive zener diode, you must is
106 edn | May 16, 2002
IRMS (C1 )=
2
;
1 / T T0 / 2 (C1 ()VPEAK cos(t)) dt
IPEAK (C1 )= C1 (VPEAK )d sin(t) / dt =

C1()VPEAK .
Thus, for T16.7 msec, IRMS19.1

mA. By adjusting the value of C1, you can
limit peak-current levels to the value of
maximum MAX6330 shunt current, 50
mA, and achieve an output of 20 mA or
so. The voltage rating of C1 must be able
to withstand the maximum input voltage. Because peak currents are limited to
IPEAK, practically any small-signal diode
can serve as the half-wave rectifier, D1. D2
discharges C1 during the negative portion
of the cycle. The current rating of D2 depends on the value of VPEAK and the selected value, 50, of surge-limiting resistor R1. The maximum reverse voltage
on D1 and D2 is (VSHUNTVDIODE). C2 acts
as a storage capacitor that maintains load
current during the negative portion of
the cycle. To calculate its value, use the
following approximation based on the allowable level of ripple voltage (VRIPPLE):
C2(ILOADT/2)/VRIPPLE. With VRIPPLE
150 mV, T/28.3 msec, and ILOAD10
mA, C2550 F.

www.ednmag.com
design
ideas
More on twotransistor circuit

In a recently published Design Idea,
Jim Hagerman proposes a two-transistor circuit that claims to replace the
LTC4300 hot-swappable, two-wire
LTC4300 bus buffer (Two-transistor
circuit replaces IC, EDN, Feb 7, 2002,
pg 104). I feel compelled to point out
that the LTC4300 offers numerous advantages over this circuit for both
buffering and hot-swapping the I2C
bus.
The NPNs in Hagermans circuit
provide no capacitive buffering between the card and the backplane,
which allows card capacitance to add
directly to backplane capacitance. The
LTC4300 isolates card capacitance
from the backplane capacitance, making it possible to meet the 400-pF
specification.
The LTC4300 further aids in meeting rise-time requirements by providing boost pull-up current circuits on
all four SDA and SCL pins. This feature allows users to choose weaker
pull-up resistors on the bus that reduce power consumption and increase noise margin while still meeting system rise-time requirements.
When hot-swapping the card, the
Hagerman solution immediately connects the card bus to the backplane
bus with no regard for the condition
of either node. The LTC4300 monitors the backplane side for a Stop Bit
or Bus Idle and the card side for logic-high states before connecting the
buffers. This approach ensures that no
data transaction is occurring during
the instant of connection.
Although I do not doubt the attractiveness of Hagermans idea, I felt
it was important for your readers to
appreciate the additional benefits of
the LTC4300.
Todd Nelson
Product Marketing Manager
Mixed Signal Business Unit
Linear Technology Corp
108 edn | May 16, 2002
Routine automates
pattern/sequence detection
K Venkatachalam, Murugesh Rajiah, and Vijayakrishnan
Rousseau, Tata Elxsi Limited, KR Puram, Bangalore, India
equence detection is
a common operation
in many communication and security systems.
Some good examples are
HDLC-flag identification
and signature analysis. As
the complexity of the system increases, designing
circuitry for sequence detection becomes tedious
and laborious. Using the
software tool in this Design
Idea, you can generate
HDL code in VHDL or
Verilog formats
These are the options available for the sequenceFigure 1
for both Mealy
detection method.
and Moore machines for
any sequence of arbitrary length. The tool can assume values of 0 to n1). Let the
additionally presents options for infer- n-bit sequence be represented as an array
ring the sequence-detector state machine of bits called SEQ. The index of the arin one of the popular encoding styles, ray ranges from 0 to n1. In the
such as one-hot, binary, and Gray. Let S0 pseudocode, the state machine generally
to Sn1 be the states of a Mealy machine switches from Sm to Sm1 on detecting
for n-bit sequence detection. The key to an input that matches the next bit in the
any state-machine design is to find the sequence. But this is not the case for the
next state transition, which is a function last state. For nonoverlapping sequence
of the input and the current state. Any detection, the state machine switches
state Sm (0mn1) indicates that the from the last state to the initial state (S0)
m bit of the n-bit sequence has been de- upon detecting the last bit of the setected so far.
quence. On the other hand, for an overThe state machine switches from Sm to lapping sequence detection, the state maSm1 on detecting an input that match- chine either stays in the last state or
es the next bit of the sequence. Other- switches to one of the previous states
wise, the state machine stays in the same upon detecting the last bit of the sestate or switches one of the previous quence. The routine determines the statestates. The state machines status depends machine behavior in the same way as it
on the currently received bit and the pre- determines the next state transition for
viously received bits. If this pattern of bits an input that doesnt match the next bit
matches the pattern of bits successfully of the sequence. Refer to the while loop
detected in any of the previous states, of the if and else blocks of the
then the state machine switches to that pseudocode.
state. Listing 1 is the pseudocode of the
For both overlapping and nonoverlapalgorithm for determining the next state ping sequence detection, the output
transition from any state Sm (where m switches high from the last state when the
www.ednmag.com
design
ideas
method detects the last bit of the sequence. You could generate a Moore machine by following the same concepts.
The only difference would be that the
number of states is one more than that of
a Mealy machine. Moreover, the output
depends only on the states and not on the
input, and it goes high only in the last
state where the sequence has been successfully detected. This tool can no doubt
help a designer to focus on high-level designs, rather than intricate design details.
You can extend the idea to detecting double sequences, such as start-of-frame and
end-of-frame sequences, and sequences
having more than one bit as inputs. You
can download Listing 1 and an executable file that creates a GUI (Figure 1)
for the sequence detection from the Web
version of this Design Idea at www.ednmag.com.
LISTING 1ROUTINE FOR DETECTING SEQUENCES

110 edn | May 16, 2002
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design
ideas
Digital potentiometer programs and stabilizes

voltage reference
perature stability of RPOT
he potentiometer portion of a
V+
mixed-signal, digitally programmahas adverse effects on the
ble potentiometer adds varitemperature coefficient of
R
Figure 1
ability to an analog circuit, and its
VOUT. The programmable
VOUT
voltage-reference circuit in
digital controls provide programmabiliR1
Figure 2 uses the potenty. You can use a digital potentiometer in
IC1
tiometer as a three-termitwo ways in an analog circuit. You can use
DIGITAL
nal device. For this circuit,
it as a two-terminal variable resistance, or
CONTROLS
IC2
rheostat, or as a three-terminal resistive
CAT5113
R2
divider. Although both ways bring vari
pR POT
ability to the analog circuit, the three-terVOUT = 1.25V 1 +
(
1
p)R POT
minal implementation usually brings

other important characteristics as well.
1
.
= 1.25V
For example, a programmable voltage In this circuit, the potentiometers temperature coefficient
1p
reference has two implementations. The adversely affects that of V .
OUT
This implementation
circuit in Figure 1 is a voltage reference
shifts
the temperature dewhose output, VOUT, depends on the
12V
1.25V reference of the shunt regpendence of VOUT on the
Figure 2
potentiometer from the
ulator, IC1, R1, and the program6.8k
5.5V
high temperature coeffimable resistance R2pRPOT. The value of
VOUT
p varies from 0 to 1; it represents the procient of RPOT to the potentiometers low ratiometric
portional setting of the wiper from one
R1
2
temperature coefficient of
end, 0, to the other, 1. For this circuit,
U/D
(1-p)R
POT
1
DIGITAL
INC
IC1
20 ppm/C. It also reduces
VOUT1.25V(1pRPOT/R1). As p varies CONTROLS
7
R2
LM4041C
CS
from 0 to 1, VOUT varies from 1.25V to
component count and cost
R
p POT
IC2
and increases programCAT5113
ming accuracy. The 15%
Digital potentiometer programs and
accuracy of RPOT is the
stabilizes voltage reference..........................81
dominant factor in the accuracy of VOUT in the cirAdd voice command
This circuit has low component count, low temperature coefficuit of Figure 1. In the cirto virtual instrumentation ............................82
cient, and enhanced programming accuracy.
cuit of Figure 2, the
Switch debouncer uses only one gate ......84
some maximum value established by R1 potentiometers 1% linearity is the domPower meter is 1% accurate ..................86
and the potentiometers end-to-end re- inant factor in the accuracy of VOUT. For
sistance, RPOT. The temperature coeffi- the values shown in Figure 2, the 100-tap
Circuit controls brightness
cient
of VOUT is proportional to those of CAT5113 digitally programmable potenof multiple displays........................................88
the LM4041CIZ regulators 1.25V refer- tiometer provides for a variable, temperDifference amplifier uses
ence, R1, and RPOT. The temperature co- ature-stable VOUT of 1.25 to 5.5V
digital potentiometers ..................................90
efficient of the reference voltage and a (0p0.77). The measured data correSwitching regulator forms
quality resistor are lower than 100 lates to better than 1% with the calculatconstant-current source................................92
ppm/C. However, the temperature co- ed values.
efficient of RPOT is not guaranteed and
can run in the hundreds of parts per mil- Is this the best Design Idea in this
lion per degrees Celsius. Thus, the tem- issue? Select at www.ednmag.com.
www.ednmag.com
May 30, 2002 | edn 81
design
ideas
Add voice command to virtual instrumentation

LANGUAGE TOOLBAR IN MS EXCEL 2002 IS SHOWN IN A
ebates still persist in the engiVOICE-COMMAND MODE. (THE USER ENTERED THE SPLIT
neering community about the relaCUSTOM COMMAND.)
tive merits of analog
TEMPORARY
CUSTOM TOOLBAR IS DYNAMICALLY
Figure 1
and digital controls of inCREATED ON THE FILE_OPEN EVENT.
strumentation. Meanwhile, a revolutionary new type of controlvoice-command controlis gaining acceptance in
many application areas (Reference 1).
This Design Idea focuses on the practical implementation of the Voice Commander voice-command interface in a
virtual-instrumentation project. The
beauty of the method lies in the fact that
a single Microsoft Excel file, vScope
VC.xls, encapsulates the entire voicecommand system. The Excel file comprises two worksheets, vScope and vScopeData; two standard code modules;
and a small portion of code in the This
Workbook code module. You can download the relevant software from the Web
version of this Design Idea at www.edn
mag.com. Using the terminology and the
concept of modern multitiered software
architecture, the voice-command method embraces the user-interface and the
business-logic layers.
This screen snapshot uses the time-domain mode with horizontal zoom and split-view on to see
The simulated-data layer is in the v- signal details at the beginning and end of the scale.
ScopeData worksheet. Column A contains the samples ordinal numbers (i1,
2, ...64), Column B contains simulated
signal-amplitude samples (Vsin(6.28
2i/64)0.5cos(6.2810i/64)), and
columns C and D contain calculated
complex-FFT and signal-amplitude spectra, respectively. By adding the actual data
source (signal samples captured by a
data-acquisition board or database query
for historical data analysis) and linking
it to Column B, you can expand the technique to a full-flavored virtual instrument or analytical tool with voice-command interface.
The vScope worksheet contains the
Chart Object (called Chart1 in the
downloadable macros), formatted to emulate the actual oscilloscope screen (Figure 1). A custom toolbar appears at the
top of the display, which contains
Figure 2
control buttons. The buttons are
associated with macros that execute when
you press the button or say the com- These signal-amplitude spectra correspond to a 64-point FFT with 32 spectral components.
82 edn | May 30, 2002
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design
ideas
mand, corresponding with

signal at the same time.
TABLE 1VOICE-COMMAND DESCRIPTIONS
buttons caption. Note that the
When you say,spectra, the
Voice command Description
voice-command feature is
signal-amplitude spectra
Go scope
Customize screen settings to maximize viewing area
available only in the latest Exscreen appears (Figure 2).
Reset Excel
Reset standard Excel screen settings
cel 2002 Office application.
You can use this technique
Time Domain
Time-domain mode
Table 1 shows the list of cuswith Excel 95, 97, and 2000,
Spectra
Show signal-amplitude spectra
tom commands. The Chart
but you must use the cusZoom H
Zoom horizontal axis
Object dynamically links via
tom toolbar instead of voice
Unzoom
Unzoom horizontal axis
macros to the simulated data
commands. Note that when
Split
Toggle split-screen mode on/off
in the vScopeData worksheet.
you enable macros in Excel
Smooth
Toggle line smoothing on/off
The Business Logic portion of
or other applications, some
Linear
Use linear scale (vertical axis)
the routine is programmed in
macros could perform poLog
Use logarithmic scale (vertical axis)
Grid lines
Turn major/minor gridlines on/off (three-state logic)
VBA (macros) and partially in
tentially dangerous and
End
Close file without saving and end the vScope session
Excel worksheet functions. It
harmful actions, and some
contains a 64-point FFT, based
may contain viruses. The
on the Excel add-in functions. To use this Command mode. In this mode, you can code for this Design Idea is on an as-is bafeature, install Analysis Tool-VBA from enter the command either by saying it or sis without warranty of any kind. The vthe Tools-Add-Ins menu item. You can by clicking the button on the toolbar. For Scope VC.xls file is for demo purpose
expand the business-logic and user-inter- example, by clicking on or saying go only, and commercial use of this file is
face layers by including different digital- scope, you can maximize the view by prohibited.
filtering and windowing techniques and temporarily removing some standard
by adding multiple channels, for example. screen components. You can restore the Reference
1. Bell, Alexander, Add voice comUpon opening the Demo file, a tem- components by clicking or by saying,reporary custom toolbar appears at the top set Excel. The Split command allows you mands to your CAD system, EDN, May
of the display (Figure 1). In Excel 2002, to open two pseudowindows with inde- 2, 2002, pg 77.
activate the speech tools: Go to the pendent horizontal scrolling. This feature
ToolsSpeechSpeech Recognition lets you see the rising and falling edges Is this the best Design Idea in this
menu item and then choose the Voice of the long, or horizontally zoomed, issue? Select at www.ednmag.com.
Switch debouncer uses only one gate

Steven Robertson, Anritsu Co, Morgan Hill, CA
5V
he circuit in Figure 1 produces a
single debounced pulse each
R2
Figure 1
time you press S1. Moreover,
D1 TO D3
1k
the circuit uses only logic power from the
VOUT
remote pull-up resistor, R2. You can use
1N4148
R1
the circuit to detect when a key is pressed
R3
VDD IC
100k
S1
1
10k
in a nonenergized device, such as a de7Z04
vice in a system thats just coming up
from standby. The circuit operates as follows: Assume that you have not yet
VSS
C1
pressed S1 and that C1 is in a charged
state. Under these conditions, R1 drives
100 nF
IC1 toward VSS (ground), causing the IC
to consume virtually no power. This ac- This switch-debouncer circuit consumes virtually no power.
tion allows VOUT to remain near 5V. However, when you press S1, C1 rapidly dis- ward VSS. Once C1 charges sufficiently, VOUT for improved compatibility with
charges and drives IC1 toward VDD. IC1 goes to VSS and stops drawing pow- CMOS logic.
Under these circumstances, IC1 conducts er. This action unloads VDD and causes
heavily, pulling VOUT near 0V until R1 VOUT to return to a high state. D1 to D3, Is this the best Design Idea in this
charges C1 enough to again drive IC1 to- in conjunction with R3, shifts the level of issue? Select at www.ednmag.com.
84 edn | May 30, 2002
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design
ideas
Power meter is 1% accurate

4
ower meters provide
X-input offset adjustment: Con3
an early warning
nect a 1-kHz, 5V p-p sinusoidal
Figure 2
2
of thermal oversignal to the Y input, and connect
1
load by monitoring power
the X input to ground. Using an
POWER0
MEASUREMENT
consumption in high-reliaoscilloscope to monitor the outERROR
1
bility systems. Power moniput, adjust RX for an ac null (zero
(%)
2
amplitude) in the sinusoidal sigtoring is especially suitable
3
nal.
for motor controllers, indus4
1
3
5
7
9
11
13
15
Y-input offset adjustment: Contrial heating systems, and
POWER (W)
NOTES:
nect a 1-kHz, 5V p-p sinusoidal
other systems in which the
VCC=15V; VEE=15V.
signal to the X input, and conload voltage and current are
RSENSE=0.1.
nect the Y input to ground. Usboth variable. The power meing an oscilloscope to monitor
ter/controller in Figure 1 The measured power is better than 1% accurate for power levthe output, adjust RY for an ac
uses the principle that pow- els of 3 to 14W.
null (zero amplitude) in the sier is the product of voltage
nusoidal signal.
The circuit in Figure 1 has a unity-gain
and current. The typical accuracy of the
Output-offset adjustment: Connect
circuit is better than 1%. A current sen- transfer function, in which the output
both X and Y inputs to ground. Adsor, IC2, measures output current, and a voltage is proportional to load power. For
four-quadrant analog-voltage multiplier, instance, the output voltage is 10V when
just ROUT until the dc output voltage
is 0V.
IC1 and IC3, generates the product of out- the load power is 10W. To change the
put voltage and current. An optional uni- transfer-function gain, change the sense
Scale factor (gain): Connect both X
ty-gain inverter, IC4, inverts the inverted resistor as follows: Gain10RSENSE. For
and Y inputs to 10V dc. Adjust
multiplier output. This power meter is the circuit in Figure 1, Figure 2 compares
RSCALE until the output voltage is
10V dc.
most accurate for multiplier inputs (J1 power-measurement error with load
and J2) of 3 to 15V. Select the current- power. Note that accuracy is better than
Repeat the preceding steps as necsense resistor as follows: RSENSE1/P, 1% for load power of 3 to 14W. For
essary.
where RSENSE is in ohms, and P is the out- proper operation, you must first calibrate
put power in watts. If power delivery to the analog multiplier according to the folthe load is 10W, for example, you would lowing procedure. Remover jumpers J1 (X Is this the best Design Idea in this
input) and J2 (Y input) before calibration. issue? Select at www.ednmag.com.
choose RSENSE0.1.
VPP
VCC
27k
3k
10k
6
OUTPUT
3k
_ 2
IC4
MAX427
+ 3
7
VEE
OPTIONAL INVERTER
6
10k
3
+
MAX427
IC3 _ 2
VEE
Figure 1
1
33k
MC1495
X
13
2
15k
3
2k
20k
1 RX
1
15k
10k
J2
VCC
2
10k 1
2
J1
10k
3
13k
3
RSCALE
5k
VEE
3
39k
VCC
Y 4
12k
10 F
10k
11
Y X V
8 12 7
0.1 F
IC1
2 OUT
ROUT
10k
7.5k
6 10
14 OUT
3k
5
1
OUT
RS
IC2
MAX4372H
RS
GND
RSENSE
0.1
10 F
VEE
20k
RY
2k
This power meter, whose output voltage is proportional to load power, achieves 1% accuracy.
86 edn | May 30, 2002
www.ednmag.com
RLOAD
design
ideas
Circuit controls brightness of multiple displays

Stephan Goldstein, Analog Devices, Wilmington, MA
recently needed to control nine
seven-segment displays for a microcontrollers serial port. The complication I faced was the need to provide a
continuous brightness adjustment for all
the digitsfrom completely dark to fully bright. I couldnt easily use the obvious
solution of a string of 74HC595 serial-toparallel converters driving the segments
through series resistors, because I would
have needed a variable power supply for
the displaysan inefficient and inelegant
approach. I considered using software to
control the duty cycle of the displays
drive signal, but as a long-time analogcircuits guy, I felt honor-bound to find a
way that wouldnt require writing any
more code. Besides, Id used up all the I/O
pins on my microcontroller, so a software
solution would have entailed changing
processors. Allegro Microsystems (www.
allegromicro.com) offers several parts for
driving common-anode displays. Each
includes a serial-data interface and an onchip control loop that sets equal on-currents for all the segments, using a single
resistor to ground. I selected the Allegro
A6275E (Figure 1), which neatly match-
7 10 14
CA CA CA CA CA
AAA
F
B
F
B
GGG
E
C
E
C
L DDD R
VDD
DPR G
8 12
2
3 SDI
CLK
4
LE
13
OEB
F
2
E
4
D C
A DPL
IC2
A6275E
DPR G
8 12
14
SDO
16
VDD
1
GND
15
REXT
VDD
7 10 14
CA CA CA CA CA
COMMON-ANODE
SEVEN-SEGMENT DISPLAYS
5 6 7 8 9 10 11 12
OU OU OU OU OU OU OU OU
T0 T1 T2 T3 T4 T5 T6 T7
2
SDI
3
CLK
4
LE
13
OEB
F
2
E
4
D C
9 11 13 1
A DPL
6
5 6 7 8 9 10 11 12
OU OU OU OU OU OU OU OU
T0 T1 T2 T3 T4 T5 T6 T7
IC3
A6275E
14
SDO
16
VDD
1
GND
15
REXT
VDD
C2
3
2
1
TO
ADDITIONAL
A6275E
DRIVERS
R5
3
+
IC1A
AD8542
2
R3
100k
R1
909
100k
VDD
R4
10k
9 11 13 1
0.1 F
8

VDD
SERIAL-BUS
CONTROL LINES
FROM CPU
Figure 1
Q1s drain goes to the ICs noninverting

input. The MOSFET adds an inversion
inside the main loop, so using the op
amps noninverting input as the feedback
point results in overall negative feedback.
C1 and R3 create the loops dominant
pole, and R2 isolates Q1s gate capacitance
to ensure that IC1B doesnt oscillate. Allegro cautions against excessive capacitance at the A6275s reference pin, so I
used R5 to isolate IC1As input capacitance
from this point. IC1 must have a rail-torail output, its input must operate down
to the negative rail, and it must operate
with a total supply span of 5V. Q1 needs
to have low on-resistance with 5V gate
drive. Using the STP30NE06L from ST
Microelectronics (www.stmicroelectron
ics.com) was probably overkill at 0.045,
but the price was right at less than $1. The
remaining components are noncritical.
You may want to experiment with different potentiometer tapers; in my case, an
audio taper gave a pleasing feel to the
brightness control.
es up one chip per display digit. Now, I

had to simultaneously vary nine resistors.
I cheated, of course. Instead of varying the resistors, I moved their apparent
ground point with a simple analog control circuit comprising a dual op amp, a
power MOSFET, and a few passive components. IC1A provides a buffered version
of the A6275s nominal 1.23V reference
voltage to the top of the potentiometer,
preventing the potentiometers loading
from affecting the segment currents of
the master A6275. IC1B drives Q1s gate
and forces Q1s drain voltage to be equal
to the voltage at the potentiometers
wiper. This action varies the voltage
across the 909 resistor between (almost) ground and the reference voltage
and yields a smooth intensity control
from maximum (20 mA for a 909 resistor) to zero. The slight variations in
A6275 reference voltages and the tolerances of the 909 resistors add to the
normal variations in intensity from digit to digit, but these variations were unnoticeable in my application.
One important point to note is the
connection of IC1B: The feedback from
8
IC1B
AD8542
6
R6
909
VARIABLE "GROUND" NODE
R2
1k
C1
Q1
STP30NE06L
NOTES:
PIN NUMBERS ARE FOR PANASONIC LN518OA SEVEN-SEGMENT DISPLAYS.
BYPASS CAPACITORS FOR IC2 AND IC3 NOT SHOWN.
1000 pF
An analog control loop provides an adjustable ground node to control the current flowing through the resistors that set the segment currents.
88 edn | May 30, 2002
www.ednmag.com
design
ideas
Difference amplifier uses digital potentiometers

Reza Moghimi, Analog Devices, San Jose, CA
V
CC
ou sometimes need to measure a
small signal in the presence of
Figure 1
a large common-mode signal.
IC1A
1
Traditional instrumentation amplifiers
2 AD5235
that use two or three op amps in their inV1
A
V+
3 +
ternal structure find common use in
W2
IC2
these applications. The circuit in Figure
B
AD8628
1 presents an alternative approach that is
2
useful when low cost and low drift are

V
important, but when you dont need
W1
high precision. The circuit uses IC1, a
V2
dual 1024-position AD5235 digital poA
B
tentiometer with nonvolatile memory. It
IC1B
1
2 AD5235
also uses IC2, an AD8628 autozero amplifier to form a difference amplifier with
a gain of 15. The programming capability of the AD5235 allows you to perform
gain setting and trimming in a single step. A low-cost difference amplifier uses digital potentiometers to set the gain.
Autozero amplifiers, such as the AD8628
and the AD855x family, are the best
choices in these types of applications.
They have high dc accuracy and
Figure 2
100
add negligible errors to the output. The long-term stability of the au90
tozero amplifiers eliminates the need for
80
repeated calibration. With a minimum
common-mode rejection ratio of 140 dB
70
COMMON-MODE
for the autozero amplifier, the resistor
REJECTION 60
match is the limiting factor in most cirRATIO
(dB) 50
cuits. The transfer function of the circuit
in Figure 1 is:
VOUT
R
= W1B2
R W 1A 2
R W1B2
1 + R
W 1A 2
V2V1 ,
1 + R W 2 A1

(1)
R W 2B1
where RAnBnnominal end-to-end resistance; RWnBnterminal resistance, W to B:

RWBRABD/2N; RWnAnterminal resistance, W to A:RWARABRWBRAB
(1D/2N); Ddecimal equivalent of the
binary word; and Nnumber of bits.
A special situation arises when
(RW1B2)/(RW1A2)=(RW2A1)/(RW2B1). The
transfer-function equation reduces to
VOUT
40
30
20
10
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
A plot for common-mode rejection ratio versus frequency for the circuit in Figure 1 yields a figure
of 98 dB.
ference of the two inputs times a gain factor that you can set to any desired gain,
including unity. Equation 2 holds true
because the same chip integrates all the
resistors; therefore, their values match
tightly. The low-frequency commonR
VOUT W1B2 (V 2 V1 ).
mode rejection ratio is approximately 98
R W1A 2
(2) dB (Figure 2). Because of the tight
You can see that the output is the dif- matching, the circuit can achieve a tem-
90 edn | May 30, 2002
perature coefficient of 15 ppm/C. Although the circuit has lower performance

than precision instrumentation amplifiers, it is adequate for many low-cost applications.
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Switching regulator forms constant-current source

Stefan Strozecki, Institute of Telecommunications, Bydgoszcz, Poland
4
FDB
any applications require curIC1
L1
LM2576
1
100 H
rent sources rather than voltage
7 TO 30V
VIN
2
OUT
+
sources. When you need a highC2 +
C1
1000 F
100
F
current source, using a linear regulator
GND ON/OFF
D1
1N5822
3
5
is inadvisable, because of the high power
dissipation in the series resistor.
Figure 1
To solve the wasted-power problem, you can use a switch-mode regulator. The circuit of Figure 1 uses IC1, an A switching voltage regulator forms a good
LM2576 adjustable regulator. It needs basis for a constant-current source.
only a few external elements and has an
adjustable sensing input, which you use er. The required gain depends on the outfor controlling the output current. Resis- put current you need: GVREF/VSC,
tor RSC is a current sensor. IC2A, one-half where G is gain, VREF is the voltage on the
of a TL082 op amp, operates as a differ- sensing input of the LM2576, and VSC is
ence amplifier. When R1R2R3R4, the the voltage across RSC. Note that
output voltage is proportional to the cur- VSCIOUTRSC, where IOUT is the output
rent flowing in RSC. Good common- current. For example, if IOUT2A and
mode rejection and a wide common- RSC0.12, then VSC0.24V. Typically,
mode voltage range are important, for the LM2576, VREF1.237V. So, you
because the amplifier works with large, can obtain the gain of the noninverting
amplifier from the gain equation:
changing common-mode signals.
The second half of the TL082 op amp, G5.15V/V. The overall gain of the nonIC2B, operates as a noninverting amplifi- inverting amplifier is G1R7/R6. If
92 edn | May 30, 2002
RSC
0.12
R2
100k
R1
100k 2
R3
100k
R4
100k
IOUT
LOAD
15V
IC2A
TL082
3+
4
R5
20k 5
15V
R6
24.1k
+
IC2B
TL082
6
R7
100k
R7100 k and G5.15, you can solve

for R6 (24.1 k). When you need a precise output current, you can replace the
fixed resistor, R6,with a series connection
of a fixed resistor and a potentiometer.
Tests showed that the output current is
practically constant with varying loads.
For example, the 2A output current
changed less than 1% for an output-voltage range of 0.3 to 15V.
edn020502di28971

Heather
www.ednmag.com
design
ideas
Optocouplers are handy for motor drive

igure 1a shows a latching circuit
based on an optocoupler, IC1. If the
off switch remains closed, pressing
R
R
the on switch powers the LED in the opR
tocoupler. Thus, the transistor in IC1
OUT
OUT
turns on. You can now release the on
IC2
IC2
switch, and the transistor remains on.
OUT
You must adapt the current-limiting resistor, R, to the power-supply voltage and
OFF
the optocouplers characteristics. To turn
ON
IC1
off this latch, press the off switch, thereON
by cutting the current path. The output
IC1
of this circuit comes directly from
ON
OFF
Figure 1
IC1
the collector of the transistor. If
you need an isolated output, you can use
OFF
the circuit in Figure 1b, which works
similarly to the circuit in Figure 1a. Fig(a)
(b)
(c)
ure 1c shows a similar circuit but with an
NO (normally open) switch for both the
off and on switches. Shorting the LED in Various optocoupler-latching circuits are suitable for motor control. In (a) and the isolated circuit
IC1 turns off the transistor in IC1. Thus, (b), simply pushing the on button turns on the circuit. In (c), you push both buttons simultaneously.
IC2 also turns off. Note that simultaneously pressing both the off and the on
buttons turns on the output. But
Figure 2
be aware that pressing the off butR
M
ton reduces the voltage across the circuit
Optocouplers are handy

for motor drive................................................93
Linear regulator=low-cost dc/dc
converter ..........................................................94
IC1
IC2
QOUT
ON
Make eight-channel measurements

through an LPT port ......................................96
Eliminate thermoelectric EMF
in low-ohm measurements..........................98
Parallel port controls arbitrarywaveform generator ..................................102
The Wien-bridge oscillator is reborn ......104
Optical sensor needs no tweaking..........106
Power-line outage flashes red alert ........108
www.ednmag.com
A notched cam controls a proximity switch, which determines the motors stop positions.
below the resistor by 1 to 2V; you must

consider this fact when you calculate the
value of R.
Figure 2 is a simplified schematic of an
application in which a motor must always
stop at a defined position. Simplified
means that it shows only the parts needed for illustrating the optocouplers role
and omits protection, correct polarization, and a braking circuit, for example.
IC1 is the latching optocoupler. IC2 is an
npn-transistor, NO proximity switch.
The proximity switch is on when metal
is near its sensing area. A cam with a
notch mounts on the motor axis. The
motor should stop when the notch passJune 13, 2002 | edn 93
design
ideas
es the sensing area of the proximity

switch. Closing the on switch turns on
transistor QOUT, thus allowing the motor
to rotate, regardless of the status of the
rest of the circuit. When you open the on
switch, two things can happen:
The notch is near the sensing area of
the proximity switch. IC1 and IC2
are both off, so QOUT receives no
base current. Therefore, the motor
does not rotate.
Metal is near the sensing area of the
proximity switch, turning on the
switch. The LED and, therefore, the
transistor, in IC1 are still both on.

Thus, the motor continues to rotate
until the notch nears the sensing
area of the proximity switch. At this
point, the motor ceases to rotate.
All circuits were tested using a PC814
optocoupler from Sharp (www.sharp.co.
jp). (The circuit in Figure 2 has been running for a few months on several machines.) Optocouplers, such as the 4N33,
with accessible transistor bases are more
difficult to use in this application. Of
course, these circuits cannot replace all
relays. But they are convenient and effec-
tive in applications in which the current

and voltage are in the range of optocouplers. (You can add some amplification
by adding some power Darlington transistors.) The main advantages of these
types of circuits are that they are lowpower, have no mechanical noise, have
no switch bounce, cost only about 50
cents, require no critical components,
and measure less than 610 mm.

low-cost dc/dc converter

Linear regulator
Susanne Nell, Breitenfurt, Austria
he circuit in Figure 1 is a good
choice if you need a power
Figure 1
supply with high efficiency
L1
and you dont want to use expensive
680 H
J2
J1
BD242
dc/dc-converter ICs. The heart of the cir1A
1
1
INPUT
Q1
cuit is IC1, the common, inexpensive
OUTPUT
24V DC
C2
+ C
+
D1
5V DC
1
LM7805 linear regulator. The external
R1
2
2
470 F
1N5817
47 F
47
switch is a pnp transistor; the circuit can
R3
easily source more than 1A output current. As an additional feature, the switch1
3
IN
OUT
IC1
ing circuit automatically turns off if the
LM7805/TO220
load draws no or only a few milliamperes
GND
of currents. Under these conditions, the
2
circuit works as a normal linear regulator. When you first apply input voltage,
R2
current flows through resistor R1 and
through the LM7805 to the output. Current also flows through the emitter-base You can use a linear regulator in a switching circuit to configure an inexpensive dc/dc converter.
junction of Q1 and turns on the transistor. The current through inductor L1 now current discharges C2. When the output put. For these higher voltages, you should
rises, and the output capacitor, C2, voltage drops a few millivolts below the add resistors R2 and R3. These resistors
charges. When the output reaches the rat- 5V output voltage of the LM7805, the add some hysteresis to the circuit, reduced output of the linear regulator (5V for LM7805 again starts sourcing current to ing the switching frequency. Typical valthe LM7805), the regulator switches off the load. This action switches on Q1, and ues are 2.2 and 2.2 k, respectively. With
the cycle starts again. Under light- or no- the circuit in Figure 1, you can attain efits output .
Now, transistor Q1 switches off, be- load conditions, all the output current ficiency approximately of 75% when you
cause the LM7805 cuts off Q1s base cur- flows through the LM7805, and Q1 always convert 24V to 12V. If you use a 5V regrent. When the switch turns off, the volt- stays off. You can adjust the switchers ulator, efficiency drops to 65%, but that
age across the inductor changes polarity, start current by selecting the value of R1. figure is still better than that of a pure linYou can also use this circuit for output ear regulator.
and current flows through diode D1. The
current delivers more charge to C2, until voltages greater than 5V. You can replace
all the energy stored in L1 transfers to C2. the LM7805 with an LM7812 or an Is this the best Design Idea in this
If a load is present at the output, the load LM7815 to obtain 12 or 15V at the out- issue? Select at www.ednmag.com.
94 edn | June 13, 2002
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design
ideas
Make eight-channel measurements

through an LPT port
J Jayapandian, IGCAR, Tamil Nadu, India
he circuit in Figure 1 represents a
LPT
simple and cost-effective way to obV+
V
PORT
GND
tain eight-channel analog-signal acNO1
D0
INPUT 1
quisition through a PCs LPT port. IC1, a
PIN 2
D1
A0
NO2
INPUT 2
3
12-bit, serial-output MAX187 ADC, opD2
A1
NO3
INPUT 3
4
NO4
D3
A2
erates from a single 5V supply and acINPUT 4
5
NO5
EN
100
D4
INPUT 5
cepts analog inputs of 0 to 5V. IC2, an
6
NO6
INPUT 6
D5
7
NO7
eight-channel MAX338 analog multiD6
INPUT 7
8
NO8
INPUT 8
plexer, also operates from a single 5V supIC2
ply. The circuit acquires eight analog in18 TO 25
GND
MAX338
COM
puts and displays eight independent
DRDY
10
digital readouts in a Microsoft Windows
IC1
DATA IN
15
environment. The MAX338 connects one
MAX187
SCLK
14
CS
of eight inputs to a common output
1
through the control of a 3-bit binary adDB-25
VOLTAGE DOUBLER
dress. The design requires no external
CONNECTOR
8
2
power supply; it instead derives power
1N914
V+
IC3
3
from the LPT ports data lines D4, D5,
ICL7660
+
+
1 F
and D6 (pins 6 to 8 on the DB-25
1 F
Figure 1
connector). The low-power design consumes less than 1-mA of operating current.You derive the positive supply, V, and the logic supply, VL, by using You can obtain eight-channel analog measurements through a PCs LPT port.
IC3, a simple, ICL7660-based voltagedoubler circuit. The ICL7660 is a negaADC. After receiving the MSB, the softtive-voltage converter. The bits D0
ware generates the serial-clock output
Figure 2
through D3 (pins 2 to 4 on the con(SCLK) through Pin 14 (Auto Line Feed
nector) provide the channel-selection
output) in the Control port (0x37A) and
function. The controlling software in this
then receives the remaining 11 bits from
CHANNEL 1
design uses National Instruments
the ADC. Upon reception of all 12 bits,
CHANNEL 2
(www.natinst.com) LabView Version 6.0
the CS input goes high to enable the ADC
graphics language. The software allows
to accommodate new data in its tristate
CHANNEL 3
for channel selection through the Data
output buffer. The sequence continues,
CHANNEL 4
port (0x378) and collects the ADCs seand the digital panel meter displays the
CHANNEL 5
rial data through one of the bits in the
acquired data. One input of the LPT port
LPT1 Status port (0x379). (The Status
(control port 0x37A, Pin 15) acquires the
CHANNEL 6
port uses Pin 15 on the connector, the
serial, 12-bit data. The controlling softCHANNEL 7
LPT ports Error input.) You can downware shifts most of the bits left, accordCHANNEL 8
load the LabView software from the Web
ing to the bit position, and some of the
version of this Design Idea at www.edn
bits right (because the serial data is in the
This front-panel view represents a LabView
mag.com.
fourth bit of the data in the status port
Once the ADC completes the conver- Virtual Instrument for an eight-channel ADC.
(0x379)). The software sets other bits to
sion, its Data Ready pin switches from
zero.
high to low. The DRDY output of the (0x379) on Pin 10 and sets the ADCs
Finally, a logical OR function of the 12
ADC connects to the LPTs port Pin 10 chip-select pin CS to low, through Pin 1 bytes/words delivers the 12-bit pattern of
on the connector (the Acknowledge in- (Data Strobe output) in the Control port the acquired signal. For example, the 12th
put). The controlling software senses the (0x37A). The routine then receives the bit (MSB) appears as the first bit for
DRDY signal through the Status port MSB (most-significant bit) from the transfer. This bit must be set as the 12th
96 edn | June 13, 2002
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design
ideas
position of the word; hence, the data received through the fourth bit, D3, must
shift left through seven positions to be assigned as an 11th bit, and so on. In this
sequence of data structuring, once the
fourth bit (LSB 4) of the 12-bit pattern
appears, it needs no shifting, because it is
an actual D3 bit. The third bit, D2, requires shifting in the right position by
one, and the D1 and D0 bits need rightshifting by two and three, respectively.
This method of shifting and finally performing a logical-OR operation delivers
the exact 12-bit data pattern from the serial data received through one line of the
parallel port.
D0 through D3 bits in the Data port
(0x378) enable the channel selection. For
each channel selection, the cited sequence of acquiring the data and conditioning it provides eight independent
digital readouts. The downloadable LabView Virtual Instrument program (newmulti_MAX187.vi) is a self-explanatory
graphics program for the data-acquisition process. In the program, a time de-
lay of 125 sec between SCLK and the serial-data read sets the data-transfer rate
at 4 kHz. This time delay allows the read
cycle to read exactly at the midpoint of
the data bit to avoid improper data reads.
You can reduce the time delay for faster
data acquisition. Figure 2 shows the
front-panel view of the LabView Virtual
Instrument.
Eliminate thermoelectric EMF

in low-ohm measurements
John Wynne, Analog Devices, Limerick, Ireland
hen two different-metal conAVDD
ductors connect together
Figure 1
EMF1
IOUT1
in a loop and one of the
IEXC1
junctions is at a higher temperature than
IEXC2
the other, an electrical current flows
IOUT2
R
LOW
through the loop. The magnitude of this
AIN1
current depends on the type of metals inEMF2
AIN2
volved and the temperature differential
of the junctions. When you open such a
MULTIloop, a thermoelectric voltage appears
PLEXER
AIN3
across the open ends. Again, the pheADR420
A
A
Q1
Q2
BUFFER
nomenon depends on the type of metals
AIN4
AND
involved and the temperature differential
PROGRAMMABLEGAIN
of the junctions. The junction of the two
AMPLIFIER
REFIN1(+)
metals forms a thermocouple, so the
IC1
thermoelectric voltage is a thermocouple
AD7719
RREF
PHASE 1
voltage.
REFIN1()
CURRENT FLOW
When you try to measure small voltAGND
ages or low impedances, thermal EMFs
(electromagnetic fields) are likely to
cause errors in the readings. A standard
way that digital-multimeter manufactur- In this configuration, the excitation current flows in RLOW from top to bottom.
ers deal with the problem is to initially
take one reading and then to reverse the inates the thermoelectric EMFs from the These EMFs would normally cause an erexcitation and take a second reading. Re- final result (Reference 1). Figure 1 shows ror if you were to take a single measureversing the current excitation through a IC1, an AD7719 ADC measuring a low- ment of RLOW.
However, you can program each of the
low-value resistor or thermocouple junc- value resistor, RLOW. The diagram also
tion reverses the polarity of the desired shows two thermoelectric EMFs, EMF1 AD7719s two current sources, IEXC1 and
signal but does not affect the polarity of and EMF2, representing summations of IEXC2, to appear at either of the package
the unwanted EMF voltages. Subse- all the thermoelectric EMFs on the way pins, IOUT1 and IOUT2. This feature allows
quently averaging the two readings elim- from and to the ADC and the resistor. you to reverse the excitation current
98 edn | June 13, 2002
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design
ideas
AVDD
through the low-value resistor. You can
EMF1
IOUT1
IEXC1
thus take two measurements and
Figure 2
eliminate the effects of EMF1 and
IEXC2
IOUT2
EMF2. To increase the excitation current
RLOW
and thereby increase the measurement
AIN1
EMF2
sensitivity, the two internal 200-A exAIN2
citation currents appear in parallel with
MULTIeach other. Thus, a single 400-A current
PLEXER
AIN3
source makes up the excitation current,
ADR420
A
A
Q1
Q2
BUFFER
IEXC, in this design. Transistors Q1 and Q2
AIN4
AND
steer the excitation current through the
PROGRAMMABLEGAIN
reference resistor, RREF, to ensure that the
AMPLIFIER
REFIN1(+)
same polarity reference voltage always
IC1
AD7719
RREF
appears, regardless of the excitation-curPHASE 2
REFIN1()
rent direction. Port pins P1 and P2 (not
CURRENT FLOW
AGND
shown) of the AD7719 drive the transistors in antiphase mode. A value of 6.8 k
for RREF is suitable and ensures a typical
In this configuration, the excitation current reverses, and flows from the bottom of RLOW to the top.
ratiometric reference voltage of 2.5V.
Figures 1 and 2 show the current flow
in each phase of a measurement. During EMFs: VDIFFVDIFF(PHASE1)VDIFF(PHASE2) 2.048V output, provides the known voltPhase 1, the excitation current flows out (IEXC)(RLOW).
age. It connects to the second pair of difFinally, you need to turn this ratio- ferential inputs, AIN3 and AIN4, and into
of IOUT1, through RLOW, and through RREF
via Q2 to ground. During Phase 2, the ex- metric measurement into an absolute the main 24-bit ADC channel.
citation current flows from IOUT2, one. You achieve this result by measuring
through RLOW, and through RREF via Q1 to a known voltage using the unknown ra- Reference
ground. During Phase 1, VDIFF(PHASE1) tiometric reference voltage. Taking a
1. Low Level Measurements, Fifth EdiVAIN1VAIN2VEMF1VEMF2(IEXC)(RLOW). reading of this known voltage but with tion, Keithley.
You now switch the current sources. Dur- an unknown reference allows you to ining Phase 2, VDIFF(PHASE2)VAIN1 fer the unknown reference value and,
VAIN2VEMF1VEMF2(IEXC)(RLOW). You hence, the absolute value of VDIFF on pins
now combine the two measurements in AIN1 and AIN2. An absolute voltage refer- Is this the best Design Idea in this
software to cancel the thermoelectric ence, such as an ADR420, supplying issue? Select at www.ednmag.com.
100 edn | June 13, 2002
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design
ideas
Parallel port controls

arbitrary-waveform generator
Art Kay, Texas Instruments Inc, Tucson, AZ
ou can use the parallel port of your
PC and a few additional
74HC374N
Figure 1
3
BIT 0
IC1 1Q 2
components to generate a
1D
4
5
BIT 1
2Q
2D
powerful, easy-to-use arbitrary-wave7
6
BIT 2
3Q
3D
9
8
form generator. By using a Visual Basic
BIT 3
4Q
4D
12
13
BIT 4
5Q
program with the circuit in Figure 1, you
5D
DB25M
15
14
BIT 5
6Q
6D
can generate any waveform (for example,
1
BIT 8
16
17
BIT 6
7Q
7D
2
BIT 0
19
18
BIT 7
sinusoid, triangle, amplitude- or fre8Q
8D
3
BIT 1
BIT 10
11 CK
4
quency-modulated, or exponential deBIT 2
1
OC
5
BIT 3
cay) by simply entering its characteristic
6
BIT 4
74HC374N
7
BIT 5
equation. For this circuit, the parallel port
74HC374N
IC5
3
3
2
BIT 0 BIT 0
8
IC6 1Q 2
BIT 6
1Q
1D
1D
connects to four latches (IC1, IC2, IC5, and
9
4
4
5
5
BIT 7
BIT 1 BIT 1
2Q
2Q
2D
2D
10
7
7
6
6
BIT 2 BIT 2
IC6). IC5 provides control signals, IC1 and
3Q
3Q
3D
3D
11
9
9
8
8
BIT 3 BIT 3
4Q
4Q
IC6 transfer data to the memory, and IC2
4D
4D
12
12
12
13
13 BIT 4 BIT 4
5Q
5Q
5D
5D
13
controls a VFC (voltage-to-frequency)
15
15
14
14 BIT 5 BIT 5
14
BIT 9
6Q
6Q
6D
6D
16
16
17
17 BIT 6 BIT 6
converter. During the load-waveform op15
7Q
7Q
7D
7D
19
19
18
18 BIT 7 BIT 7
16
BIT 10
8Q
8Q
8D
8D
eration, the waveform data transfers from
17
BIT 11
11 CK
CK 11 BIT 8 BIT 10
18
the parallel port via latches IC1 and IC6 to
1
1
OC
OC
19
the memory chips IC7 and IC10. The bi20
5V
C5, 0.1 F
21
nary counter, IC9, increments the memDGND
22
ory addresses in sequence to allow load23
50V, 10% 24
24
ing each memory location with a unique
VCC
25
8
9
A0
A0
D0
16-bit binary word. Each binary word
7
10
A1
A1
D1
corresponds to a waveform data point.
6 A2
11
A2
D2
13
DGND
5
A3
During the load-waveform operation, the
A3 DS122OAB100 D3
14
4
A4
IC
D4
A4
7
memorys configuration allows writing
15
3
A5
D5
A5
16
2
information to it (for example, ~OE1,
A6
A6
D6
17
1
A7
D7
A7
~WE0).
A8
23 A8
During the output-waveform opera22
A9
A9
IC9
19
tion, latches IC1 and IC6 disconnect from
A10
A10
2
9
A0
18
CT5
Q1
1 10
the bus, and the memory delivers the
CE
7
A1
3 IC11
CLK
20
CT6
Q2
A2
OE
6
stored data (for example, ~OE0,
CT7 21
Q3
74HC02N
WE
5
A3
GND
5
Q4
~WE1). For each accessed location,
2
3
A4
12
Q5
IC11
FOUT
6
one of the binary words stored during the
2
A5
Q6
74HC02N
5V
4
A6
11
load-waveform operation transfers to
Q7
C9, 0.1 F
RST
13
A7
Q8
IC8, a DAC7621. This transfer causes the
12
A8
10 11
9
50V, 10% 24
Q9
13
14
DAC to deliver one output point in the
A9
8 IC11
Q10
12 IC11
VCC
15 A10 A0
8
9
Q11
to
clock
waveform. The VFC causes IC9
A0
D0
1
74HC02N
74HC02N
7
10
Q12
A1
A1
D1
through all possible addresses. IC11 resets
6 A2
11
A2
D2
the counter when the memory sequences
13
5
A3
A3 DS122OAB100 D3
14
4
A4
through all possible addresses. When IC9
IC10
D4
A4
15
3
A5
D5
A5
resets to zero, the waveform begins to re16
2
A6
A6
D6
17
peat itself. Thus, each waveform com1
A7
D7
A7
A8
23 A8
prises 2048 data points. The number of
22
A9
A9
points, N, and the clock frequency, C,
19
A10
A10
18
CT5
control the frequency of the arbitrary
CE
CT6 20
waveform: fAWG1/NTC, where TC is the
OE
CT7 21
WE
GND
period of the clock frequency.
12
IC2, IC3, and IC4 form a circuit that adDGND
justs the clock frequency, C, via the par- With the aid of some Visual Basic software and a few ICs, a computers parallel port forms an
(text continued on pg 104)
102 edn | June 13, 2002
effective arbitrary-waveform generator.

www.ednmag.com
Figure 2
15V
TLC7226CN
IC3
74HC374N
IC2
3
4
7
8
3
4 13
5 14
6 17
7 18
11 11
1
BIT 0
BIT 1
BIT 2
BIT
BIT
BIT
BIT
BIT
BIT
1D
2D
3D
4D
5D
6D
7D
8D
CK
OC
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
2
5
6
9
12
15
16
19
14
13
12
11
10
9
8
7
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
15
WR
16
A0
19
A1
DGND
18
VDD
3
VSS
REF
5V
C6, 0.1 F
C1, 0.1 F
50V, 10%
15V
DGND
DGND
50V, 10%
DGND
REF_OUT
10
2
OUTA
1
OUTB
20
OUTC
19
OUTD
AGND
DGND
50V, 10%
C3, 0.1 F
VCC
VIN
1
IIN
6 C
OS
CT1
13
5
6
IC4
VFC110
EN
FOUT 8
5VREF 3
12
V
AGND
NC
7 GDND
IN_COM
VEE
FOUT
OUT
CMPR_IN
R1
4.99k
0.125W
1%
11
9
14
C4, 0.1 F
50V, 10%
DGND
15V
DGND AGND
DGND
AGND
28
D0
27
D1
26 D2
25 D3
24 D4
23 D5
22 D6
21 D7
20 D8
19 D9
18
D10
17
D11
16
D12
15
D13
DAC7621
IC8
14
D14
13
D15
AO 12
A1 11
WR 10
CLR 9
VEE () 8
VCC (+) 7
GAIN_ADJ 6
VREF_OUT 5
4
OFFSET_ADJ
3
VOUT
2
ACOM
1
DCOM
5V 15V 15V
DGND
C7, 0.1 F
50V, 10%
C8, 0.1 F
REF_OUT
50V, 10%
TP1
TP2
DGND
AGND
DGND
Depending on the points stored in memory, the circuit in

Figure 1 can generate virtually any waveform.
www.ednmag.com
June 13, 2002 | edn 103
design
ideas
allel port. The clock rate C controls the

frequency of the arbitrary waveform. The
output frequency of IC4, a VFC110 VFC,
is directly proportional to its input voltage. With a full-scale input of 10V, the
VFC110 delivers 4 MHz. IC3 provides a
voltage output of 0 to 10V, thus providing frequency control from near 0 Hz to
4 MHz. The voltage output of IC3 receives its programming via the parallel
port, thus allowing computer control of
the clock rate. Thus, the circuit provides
a frequency range of 7.6 Hz (1/(204864
sec)) to 125 kHz (1/(32250 nsec)).
Figure 2 shows various sample outputs
of the circuit. You can download the
software files associated with this Design

Idea from the Web version of the article
at www.ednmag.com.

The Wien-bridge oscillator is reborn

Michael Fisch, Agere Systems, Longmont, CO
n 1940, William Hewlett and David
Packard launched a product from a
garage. The product was a Wienbridge oscillator. It consisted of a singlepole highpass filter in series with a singlepole lowpass filter. To keep the gain
constant, the circuit used an incandescent
pilot light to provide AGC (automatic
gain control). As is true for all incandescent bulbs, the pilot light has nonlinear
resistance. When you turn on the circuit,
the cold lamps resistance is low, resulting
in high gain. As the gain increases, the resistance of the warming lamp increases.
Thus, the lamp provides an AGC function. The circuit has been in use for more
than 60 years and is still in use. The only
problem with the Wien-bridge oscillator
is that below unity gain it does not func-
to a value lower than unity. The 5.2V zener diode maintains the gain. The result is
that when the gain falls below unity, the
amplitude tries to decrease but cannot do
so, because the zener-diode voltage pulls
it back up. IC2, the LT1056AN amplifier
serves as a driver for the two LEDs, which
alternately turn on and off at the frequency of the oscillator. IC1, an
LT1012AN amplifier has very low offset
voltage. IC3, a high-voltage TI/BurrBrown (www.ti.com) amplifier, produces
the final output of 20 to 200V. The final
resulta major breakthroughis a
Wien-bridge sine-wave oscillator that
you can adjust below unity gain, and the
circuit still maintains its AGC.
tion. When working for a telephone company, I had to develop a 20-Hz, high-voltage sine-wave ringer circuit. The circuit
had to be adjustable from 20 to 200V pp. The most difficult part was that I had
to adjust the oscillators gain to a value
below unity.
The basic oscillator had to have gain
slightly greater than unity to make the
positive-feedback network oscillate. It
also needed an AGC loop to control the
greater-than-unity gain. So, I added a
third loop around the oscillator and
dubbed it a voltage-controlled, regulated-output feedback circuit. The end result (Figure 1) is a simple push-pull circuit. By adding D1, a zener diode, to
another feedback loop, I maintained the
amplitude even when I adjusted the gain
12V
Figure 1
12V
1
+ IC
2
LT10562 _ AN
5
4
3
5.62k
13k
12V
1k
2k
12V
1N759A
56k
1
8
IC1
LT10123 + AN
5
4
12V
2 _
1N914
D1
1N751A
Q1
2N2222
1 F
27k
OSCILLATOR
RUNNING
7.5k
270k
13k
2N2222
150V
2
6
4
IC3
3583JM
5 _
1k
1 F
LED
GREEN
LED
GREEN
Q2
12V
6.8k
750
6
1 F
6.8k
1
CASE
J1
1
VOUT
2
VOUT
150V
1k
14k
HIGH-VOLTAGE
AMPLIFIER
This Wien-bridge oscillator is, according to the author, the first oscillator that can function at gains below unity.
104 edn | June 13, 2002
www.ednmag.com
design
ideas
Optical sensor needs no tweaking

Ron Mancini, Texas Instruments, Bushnell, FL
he transfer gain of optical sensors
spans a 16-to-1 ratio because of variations in the LED, phototransistor,
ambient temperature, and optical path.
The wide transfer-gain variation complicates output-resistor selection in dc-coupled circuits. You must size the output resistor to prevent high transfer gains from
causing output-stage saturation, but low
transfer gains yield low output-voltage
swings with low-value resistors. You usually need to make adjustments to match
the dc output voltage to the transfer gain,
and reliable operation requires readjustment under extreme temperature and
dust conditions. The circuit in Figure 1
eliminates the need for adjustments. The
circuit uses dc-coupled feedback to control the current in the output resistor.
Hence, the output voltage is predictable
and constant.
The op amps input current and the
current in D3 is negligible, so I1I2, and
the output voltage is 2.7V when the phototransistor is on (light path unbroken).
The output voltage is 0V when the phototransistor is off (light path broken).
The op amps output-voltage swing accommodates the variation in transfer
gain. This output voltage assumes the value required to make the LED current
times the transfer gain equal to the phototransistors emitter current. The inputcurrent equation is as follows:
The range of transfer gain is 80 to 5:

5I3/I280. The op amps output-voltage range is limited, especially with the
high output-current requirement, thus
the design uses a TLC071 that can source
20 mA at 3.5V in this design:
V VREF
I1 CC
R1

53
100 A.
20 k
V
VD1
R 3MAX OUTMAX
I 3MAX
3.50.7
350 .
8 mA
When the light is blocked, the phototransistors emitter current goes to zero.
The input current, I1, cant flow into Q1
because it is off, so the op amp heads for
the positive rail. If the op amps output
stage saturates, the recovery time is unpredictable, so you insert the zener-diode
combination D2 and D3 to prevent saturation. As the op amps output voltage approaches 3.4V (VD2VD3), the diodes
clamp the output voltage, thus preventing saturation. R3270 so that it can
supply adequate LED current without incurring op-amp saturation. When this
circuit drives a saturated logic circuit, you
should buffer the output with a hysteresis gate or a comparator with hysteresis.
VREF
3V
R1
20k
+
TLC071
_
5V
IB
I1
I2
Q1
D2, 2.7V
1N5223
D1
R3
270
D3
1N4148
Figure 1
VOUT
R2
27k
EESG3
The op-amp feedback keeps the phototransistors current constant, so the circuit requires no
adjustments for transfer gain.
106 edn | June 13, 2002
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design
ideas
Power-line outage flashes red alert

Vasiliy Borodai, Zaporozhje, Ukraine
his Design Idea expands on a circuit in a previous one to configure a
power-outage detector with a flashing alarm (Figure 1, Reference 1). The
circuit plugs into a mains outlet and uses
trickle-charged nickel-cadmium batteries. The green-LED monitors the presence of line voltage. The BZV55-C4V3
zener diode, D1 protects the batteries
against overvoltage. Voltage bias from R6
RED LED
Figure 1
R3
1M
C1
330 nF
NiCd
+ BATTERY
3.6V
300 mAH
+
BC327
Q2
R1
220k
C2
10 F
Q2N2222A
OR
BC547
C3
0.47 F
D1
BZV55C4V3
R5
10 TO 47
Q1
PL1
1A BRIDGE OR
41N4007
R2
470
R4
20k
R6
1 TO 10k
GREEN LED
A green LED indicates normal power-line voltage; a flashing red LED denotes a power outage.
108 edn | June 13, 2002
and the green LED keeps Q1 off, so the

Q1-Q2 RC oscillator remains off. When a
power outage occurs, capacitor C2 discharges in approximately 2 to 3 seconds,
and the dc bias disappears. Now supplied
by the batteries, the RC oscillator starts,
and the red LED flashes at a rate of approximately 2 Hz. R3 and C3 set the flashing frequency. You can use an infrared
LED instead of the visible LED. The infrared LED couples with an infrared receiver to provide a convenient remote
alarm.
Reference
1.Terrade, J M, Free-line indicator
stops interruptions, EDN, Dec 7, 2000,
pg 187.

www.ednmag.com
design
ideas
Current-sensing scheme improves

PFC on/off sequences
Jol Turchi, On Semiconductor, Toulouse, France
FC (power-factor-correction)
VIN
D2
VOUT
preconverters typically use the stepD1
L1
up, or boost, configuration, because
this type of converter is relatively easy to
implement (Figure 1). However,
Figure 1
this topology requires the output
voltage to be higher than the input voltC1
Q1
CONTROLLER
age. When this condition is not the
casefor example, with on/off sequences
or under load conditionssome inrush
current flows through the boost inductor
and diode to abruptly charge the output
capacitor. For instance, before start-up, In this classic boost-converter topology, inrush curthe output capacitor discharges. When rents can unduly stress the power-MOSFET switch.
you plug in the PFC stage, the output capacitor attempts to charge resoFigure 2
nantly to twice VIN. During this
sequence, the current can largely exceed
(VOUTVIN)L1
the levels obtained during normal operVIN/L1
ation. Too often, these uncontrolled inrush currents make PFC-stage designers
nervous during on/off reliability tests.
Except for On Semiconductors (www.
TIME
Current-sensing scheme improves

PFC on/off sequences....................................81
Reset generator uses fleapower..............84
Voltage-to-current converter
drives white LEDs ..........................................84
Use time-domain analysis
of Zobel network ............................................86
Circuit improves further
on first-event detector ..................................88
Delay line has wide
duty-cycle range ............................................88
www.ednmag.com
D1 OFF
Q1 ON
D1 ON
Q1 OFF
TIME
Boost-converter operation occurs in two phases.
onsemi.com) MC33260, which monitors

the entire loop current, available controllers cannot detect this overcurrent
state. These controllers may turn on the
power switch while a huge and potentially destructive current flows through
the inductor.
In the boost structure of Figure 1, the
controller turns the power switch, Q1, on
and off to control the L1 inductor current. Figure 2 illustrates two phases:
Switch Q1 is on. The boost structures input voltage (VIN, the rectified ac-line voltage) appears
across the inductor, L1, which
charges linearly.
Switch Q1 is off. The diode, D1,
turns on and drives the inductor
current toward the output capacitor, C1. The inductor current
ramps down with a slope equal to
(VOUTVIN)/L1. VOUT must be
higher than VIN to properly discharge the inductor.
If VIN exceeds VOUT, an inrush current flows through L1 and D1 and
charges output capacitor C1. Designers generally place a diode, D2, between VIN and VOUT. This diode conducts a major part of the inrush
current, thus improving the safety of
the first power-switch turn-on. However, when the output voltage is in the
neighborhood of VIN, the current that
ramps up during this first switch-on
time generally cannot significantly decay during the off-time. As a consequence, the following turn-on operation may occur while the inductor is
still charged. Moreover, if VOUT needs
several switching cycles to significantly charge (for example, under heavy load
conditions), the power MOSFET faces a
succession of stressful turn-ons that may
jeopardize the circuits reliability.
When you cannot use the MC33260,
you can use the circuit in Figure 3 to improve the reliability of the PFC stage. You
can test this configuration using the
MC33262. Typically, the current-sense
resistor, R1 connects between the power
MOSFETs source and ground, and the
June 27, 2002 | edn 81
design
ideas
FUSE
MAINS
FILTER
AC LINE
S1
SWITCH FOR
ON/OFF TEST
VCC
14V
VOUT
AUXILIARY
VOUT
1
3 MC33262 6
Figure 3
Q1
C1
LOAD
R1
In this circuit, a modification in the placement of the current-sensing resistor increases the robustness of the PFC preconverter.
negative terminal of the output capacitor,

C1, connects to ground. As a result, R1
senses only the power-switch curFigure 4
rent. In the modified circuit of
Figure 3, the output capacitors charging
current also passes through R1. As a result, the sense resistor senses the entire inductor current. The MC33262 keeps the
power switch off as long as the sensed
current is higher than the setpoint that an
internal multiplier establishes. When the
sensed current is below this setpoint, the
MOSFET turns on upon core-reset detection. If detection is impossible, a 600sec watchdog timer reactivates the power switch. In the case of on/off sequences,
the core-reset information is generally
unavailable, and the MOSFET turns on
in the following cases:
600 sec after the preconverter No switching occurs when the input current is high; a 600-sec timer delays the power switchs
switches on, regardless of the in- turn-on.
ductor current, in the traditional application, or
fect, the losses are PMODIF1/6RSENSE
PMODIFPTYP
(%) 120 VAC . (2)
once the coil current measures low- (IPKMAX)2, where RSENSE is the current-sense
PTYP
VOUT 1.2 VAC
er than setpoint in the modified resistor (R1 in Figure 3), and IPKMAX is the
maximum inductor peak current (obFrom Equation 2, you can determine
application.
Figure 4 clearly shows that no switch- tained at the top of the sinusoid). In this that if VAC90V and VOUT400V, the dising takes place when the input current is application, you can compute the losses sipation increases by 36%. If VAC180V
and VOUT400V, the dissipation increashigh, as long as the current is higher than using the following equation:
es by 117%. The simple modification of
the setpoint. In Figure 3s example, the
PTYP
the sensing resistors location signifisituation is even better. In effect, the 600cantly increases the robustness of the
sec timer delays the power switchs turn
1
.
2
V
1
(I
)21 AC , (1) PFC preconverter during on/off tests at
R
on even after the current-sensing block al6 SENSE PKMAX
VOUT
the price of a reasonable increase of the

lows the turn-on, so the MOSFET finally
switches on when the inductor current is where VAC is the rms input voltage and power dissipation in the sensing resistor.
zero. You can see that the modified appli- VOUT is the output voltage. The relative
cation schematic increases the power dis- increase in dissipation then conforms to Is this the best Design Idea in this
sipated in the current-sense resistor. In ef- the following equation:
82 edn | June 27, 2002
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design
ideas
Reset generator uses fleapower

Philip Simpson, Maxim Integrated Products, Reading, UK
VCC
hen a processor-controlled
riod varies from 1.308 sec with a
VCC
VCC
10M
device must operate reliably,
4.5V supply to 1.306 sec with a 1.8V
D1
10M
RP
designers often choose to perisupply. Figure 2b shows details of
1N4148
270k
+
CP
odically reset the processor rather
the low-going reset pulse, which
RESET
MAX919
OUTPUT
than rely on a watchdog configuratakes the shape of the output of a
1 nF
10M
tion. In low-power systems, this perinormal relaxation oscillator. The reR1

odic-reset circuit can consume a large
set pulse is 100 sec wide at its 30%
C1
7.1M
part of the systems current budget or
point on the exponential
130 nF
Figure 1
may fail to operate at low voltages.
curve.
The circuit in Figure 1 generates a
The 350-nA supply current, the
low-going reset pulse of 100-sec du- This reset circuit consumes less than 1 A and delivers a
1.8 to 5.5V supply range, and the
ration. The circuit consumes less than 100-sec-wide reset pulse every 1.3 sec.
SOT-23 package make the MAX919
1-A operating current and operates
ideal for this application. Measurefrom 1.8 to 5V supplies with little varia- form by varying R1, C1, or both. You can ments for the circuit reveal lower than 1tion in the output period. The circuit is adjust the pulse width of the low-going A operating current. This low conan adaptation of a normal relaxation os- reset pulse by varying RP, CP, or both, or sumption would allow the circuit to
cillator. The circuit has a differentiator you can change the polarity by reposi- operate from a single AA lithium cell for
and diode clamp on the output to gen- tioning D1. Figure 2a shows the com- 250 years. With judicious component
erate the 100-sec low-going pulse. You parators output waveform, which has a choice, the circuit can generate periods
can adjust the period of the output wave- period of approximately 1.3 sec. The pe- from milliseconds to minutes. To ensure
good temperature stability, you should
use metal-film types for R1 and RP and
NP0 types for C1 and CP. Assuming a reset-logic threshold of 30% of the supply
1V/DIV
rail, you can use the following formulas
1V/DIV
to adjust the output pulse width and period: pulse width0.36RPCP, and period.4R1C1.
(a)
Figure 2
200 mSEC/DIV
(b)
100 SEC/DIV
The comparator in Figure 1 produces a square wave with a period of 1.3 sec (a); the
output differentiator yields a low-going pulse of 100-sec width at its 30% point (b).

Voltage-to-current converter drives white LEDs

ou sometimes need to drive a white
LED from one 1.5V battery. Unfortunately, the forward voltage of a
white LED is 3 to 4V. So, you would need
a dc/dc converter to drive the LED from
one battery. Using the simple circuit in
Figure 1, you can drive one white LED or
two series-connected green LEDs, using
84 edn | June 27, 2002
only a few components. The circuit is a

voltage-to-current converter, which converts the battery voltage to a current that
passes through the LED. You can adjust
this current and, thus, the brightness of
the LED, by varying resistor R3. If you
turn on switch S1, resistor R2 feeds base
current to transistor Q2. Q2 turns on, and
its collector current, via R3, turns on Q1.

Now, the current through inductor L1 increases. The slope of the increase is a
function of the value of L1 and the battery voltage. The current through L1 increases until it reaches a maximum value, which depends on the gain of Q1.
Because the value of R3 sets the base curwww.ednmag.com
design
ideas
Q1
rent drawn from Q1, Q1s colL1 flows through the LED. DifS1
BC558C
I =10 mA
lector current is also limited.
ferent forward voltages of the
2 DC
1
Once the current through L1
LEDs yield different on-times
ON/OFF
L1
R1
R2
reaches its maximum value,
(duty cycles) but the same
680
H
BATTERY
22k
R3
100k
the slope of the current
peak current through the LED.
1.5V
1k
through L1 changes. At that inWith the values shown in FigC1
stant, the voltage on L1 switchure 1, the circuit oscillates at a
Q2
BC548C
es to a negative polarfrequency of approximately 30
1 nF
IPEAK=20 mA
Figure 1
ity forced by the
kHz and delivers a 20-mA peak
D1
changed slope. This negative
current through the LED. The
LED
voltage traverses capacitor C1
duty cycle depends on the raand turns off Q2, which in turn
tio of the battery voltage to the
turns off Q1. The negative volt- You can eschew expensive dc/dc converters by using this inexpensive
forward voltage of the LED.
age on L1 increases until it circuit to drive a white LED from a single battery cell.
One advantage of this circuit is
reaches the forward voltage of
that it requires no series-limthe LED. The peak current through the LED. The brightness of an LED is a iting resistor for the LED. The peak curinductor L1 now flows through the LED linear function of the current through rent through the LED is a function of the
and decreases to zero. Now, Q2 switches the LED. So, adjusting the value of R3 also value of R3 and the gain of Q1.
on again, via the current through R2, and adjusts the brightness of the LED.
the cycle starts again. By adjusting reIt doesnt matter which LED you use;
sistor R3, you can set the peak current the forward voltage on the LED always Is this the best Design Idea in this
through L1 and the peak current through increases until the peak current through issue? Select at www.ednmag.com.
Use time-domain analysis of Zobel network

Nol Boutin, Universit de Sherbrooke, PQ, Canada
IC
IS
source to supply a step current, you
Zobel network is useful in
must add another branch that draws
making a reactive load appear as
a current, IC, such that it compensates
a pure resistance to a drivFigure 1
IL
L
C
L
for the slow-rising load current, IL.
ing source prone to stability
Adding the series R2C network meets
problems (Reference 1). A typical sitR2
R1
R1
that requirement. The current, IC,
uation is an audio power amplifier
(a)
(b)
flowing through that network is indriving a loudspeaker, modeled at first
stantaneously equal to V/R2 and then
approximation as an inductance and A first-approximation model of a loudspeaker is an
a series resistor (Figure 1a). The ad- inductance and a resistor in series (a); the addition of a decreases exponentially to zero with
a time constant 2R2C. For the sum
dition of a series R2C network in par- series RC network (b) makes the speaker look purely
allel with the series R1L network resistive to the driving source.
of the current, IL, flowing through the
forms a Zobel network (Figure 1b).
series R1L network and the current IC
If you select the proper values of R2 and way to arrive at the same result. More- flowing through the series R2C network
C, the driving source sees a purely resis- over, the method provides a better un- to yield a step current IS, R2 must equal R1
tive load. Reference 2 discusses the com- derstanding of the reasons why the driv- and 2 must equal 1. That is, R2R1 and
putation of the total impedance, ZL, of er sees a purely resistive load with a Zobel R2CL/R1.
the Zobel network:
network.
Without loss of generality, let the driv- References
2
1. Zobel, OJ,Distortion Correction in
ing source be an ideal V-volt step-funcL
R2
+ s R 2C + + 1
R1 s LC
Electrical
Circuits with Constant-Resistion
voltage
source.
If
the
load
were
pureR
R

1
1
,
ZL = 2
ly resistive, the source current, IS, would tance Networks, Bell Systems Technical
s (LC) + sC(R 2 + R1) + 1
also be a step function. In the absence of Journal, July 1982, pg 438.
2. Albean, D,Zobel network tames refrom which you find that the following the series R2C network, the current flows
conditions must prevail: R2R1 and only through the series R1L load, starting active loads, EDN, Dec 21, 1995, pg 82.
CL/R12. Designing the Zobel network from a zero value and exponentially inin the time domain, rather than in the creasing toward a final value. The time Is this the best Design Idea in this
transformed-s domain, yields an easier constant in this case is 1L/R1. For the issue? Select at www.ednmag.com.
86 edn | June 27, 2002
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design
ideas
Circuit improves further on first-event detector

Vasiliy Borodai, Zaporozhje, Ukraine
he circuits in Figure 1 have certain
advantages over those in a previous
Design Idea (Reference 1). The firstevent detector with autoreset (Figure 1a)
consists of N sets of monostable multivibrators, using 4001 logic circuits with
LEDs attached. After any player (1
through N) presses a pushbutton, the
corresponding monostable multivibrator switches on, and its associated LED
lights. The voltage at Point A changes to
a level of nearly 2V (the forward voltage

of the LED). After that instant, no other
player can change the situation by pressing a pushbutton, because, to switch, the
monostable multivibrators need a voltage exceeding 4V. After an interval of
0.5RC (nearly 15 sec for R1 M and
C33 F), the monostable multivibrator returns to its previous state, and the
circuit is ready for its next first-event detection. Figure 1b shows another first-
9V
33 F
2.5k
event detector with autoreset, using 4011

logic ICs. This circuit is a mirror image
of the circuit in Figure 1a and operates
similarly.
Reference
1. Arendt, Lawrence,Circuit improves
on first-event detection, EDN, Aug 16,
2001, pg 106.
9V
2.5k
1M
1M
14
PLAYER 1
Figure 1
47 F
IC1
A
1M
5
6 IC1
PLAYER 1
IC1A
33 F
47 F
1M
1M
8
PLAYER 2
IC1B
1M
IC1
10
12
13
IC1
PLAYER 2
11
IC1D
IC1C
1M
1M
33 F
47 F
1M
1M
PLAYER N
PLAYER N
IC1
IC1
ICN
1M
(a)
ICN
1M
(b)
Monostable multivibrators and LEDs form the heart of these first-event detectors with autoreset.
Delay line has wide duty-cycle range

John Guy, Maxim Integrated Products, Sunnyvale.CA
odays digital delay lines can
process pulses no shorter than their
delay times, and that restriction confines the devices to applications in which
the duty cycle remains near 50%. A limited range of available delays (2 to 100
nsec per tap) further limits their use.
Longer delay is available with one-shot
multivibrators of standard digital-logic
families, but those devices do not retain
duty-cycle information. As an example,
88 edn | June 27, 2002
a PWM control circuit (Figure 1) must

handle relatively long delays while retaining information about the input duty
cycle. The upper half of this dual-path,
precision one-shot works on the input
signals rising edge. The rising edge triggers the D flip-flop, IC3A, to drive IC4As
input low. IC4A has an open-drain output; the output therefore rises exponentially according to the single R1C1 time
constant. IC1A compares the output with
a dc voltage equal to 67% of VCC, producing a conveniently scaled delay equal

to R1C1.
The output of comparator IC1A drives
the set input of an RS latch (IC2B and
IC2C). It also feeds back to the input flipflop, thereby resetting the flip-flop in anticipation of the next rising edge. The
lower half of the circuit in Figure 1 works
in a similar fashion, but it triggers on the
inputs falling edge and drives the reset
www.ednmag.com
design
ideas
VCC
input of the RS latch. You can
test the circuit with a 100-kHz
VCC
4
input signal and a nominal deIC4A
2 D PRE Q 5
lay of 1 sec. When the input
R1
74HC05
IC3A
IC2A
10k
duty cycle varies from 10 to
74HCT74 6
74HCT00
1
2
INPUT
C
1
Q
3
3
90% (limits imposed by test
+
SIGNAL
IC2B
IC1A
CLR
2
1
C1
74HCT00
MAX907
equipment), the duty-cycle erVCC
100 pF
1
2 _
4
DELAYED
6
4
OUTPUT
ror is less than 0.1%.
5
SIGNAL
F
i
g
u
r
e
1
1k
You can obtain this
performance with unmatched
VCC
VCC
VCC
components. The circuit pro0.1 F
2k
0.1 F
0.1 F
duces accurate pulse widths for
VCC
14 10
pulses as narrow as 20 nsec. To
9
12
PRE
IC4B
14
IC2D
Q
D
9
8
5
ensure accuracy, the timing ca74HC05
IC3B
74HCT00
+
8
10k
IC1B
7
12
10
74HCT74
8 3
11
pacitors should be NP0 types
4
11
MAX907
IC2C
Q
C
6
13
7

74HCT00
with 5% tolerance, and the reCLR
4
0.1 F
100 pF
13
7
sistors should be 1% accurate.
The MAX907 comparator
from Maxim (www.maximic.com) provides the high in- Based on a precision dual comparator, this delay line generates accurate duty cycles.
put impedance, high precision,
and low propagation delay the circuit inclusion of a NAND gate connected as Is this the best Design Idea in this
requires. For most applications, 74- an inverter, IC2A, which enhances accu- issue? Select at www.ednmag.com.
HC/HCT logic is fast enough to mini- racy by equalizing the propagation delays
mize propagation-delay errors. Note the in each channel.
90 edn | June 27, 2002
www.ednmag.com
design
ideas
Improved frequency modulator uses negatron

ou can improve a capacitive-sensor
CAPACITIVE SENSOR
R3
R1
circuit with a modulator and an RF
4.7M
15k
transmitter (Reference 1) by modifying the modulator portion to obtain
VCC
CS
better accuracy. More improvements result from adding a negatron circuit, a
_
configuration that uses equivalent negaIC2
OUTPUT (f)
IC1
VCC
tive capacitance. Reference 2 gives some
TO
+
5V
TRANSMITTER
insight into the uses of negative impedR4
R5
R2
ance. The circuit in Figure 1 works with
1M
1M
12k
the RF transmitter of Reference 1 (Figure 2) as follows: The modulator uses op
R6
C1
1M
amp IC1 in a standard flip-flop configu120 pF
ration (with the addition of the bias resistor R4, because of single-supply operNOTE: OP AMPS=LTC1124s.
ation). The negatron portion of
Figure 1
the circuit uses op amp IC2. The
output frequency, f, of the modulator The modulator portion provides improved performance over the circuit in Reference 1; the negawithout the negatron is a function of the tron increases sensitivity and resolution.
time constant MR3CS. Thus, the frequency is a function of the physical valIC1A
ue of the input (for example, presIC1C
IC1B
74HC132
Figure 2
74HC132
74HC132
sure or humidity). The potential
ENABLE
ANTENNA
accuracy and stability of the modulator
28-CM-LONG
TO
in Figure 1 are greater than those of the
COPPER
R2
MODULATOR
modulator in Reference 1 because of the
1k
L2
L1
Improved frequency modulator

uses negatron..............................................97
C2
100 pF
Get buck-boost performance

from a boost regulator ................................98
C4
C3
22 pF
5 pF
NOTES:
L1 IS SIX TURNS OF 22-GAUGE WIRE WITH 5-MM DIAMETER.
L2 IS 18 TURNS OF 22-GAUGE WIRE WITH 5-MM INNER DIAMETER.
Circuit transmits ARINC

429 data ........................................................100
Circuit divides frequency
by N+1............................................................104
Maintain precise timing
with PCs speaker logic ..............................106
Voice feedback enhances
engineering calculator................................108
www.ednmag.com
This simple transmitter from Reference 1 allows you to remotely measure physical phenomena.
low input capacitance and temperature

coefficient of the LTC1124 op amp and
the high stability of the R4-R6 voltage
threshold.
Adding the negatron portion in Figure
1 increases the relative sensitivity of the
frequency modulator. The equivalent capacitance of the negatron is CN
C1(R2/R1). Assuming the physical value
of the input causes the change C (compared with the sensors initial capacitance, C0), the relative output-frequency
change without the negatron (for small
C) is f/f0C/C0. With the negatron
added, the equation is: f/f0C/(C0
C1(R2/R1)). The result is higher relative
sensitivity because of the reduction in the
denominator value. The value of CN is apJuly 11, 2002 | edn 97
design
ideas
proximately 100 pF for the circuit in

Figure 1. In other words, a given change
in the input value causes a greater relative-frequency deviation. Note that
adding the negatron changes the equivalent time constant: R3(CSC1(R2/R1)).
You can make value adjustments in R3 to
obtain the desired initial frequency, f0.
Also, note that the measured values of f0

and f may differ from the calculated
ones because of parasitics and the input
capacitance of the op amp.
IC, EDN, Nov 8, 2001, pg 116.

2. Belousov, Alexander, Negative impedance improves capacitive sensors,
EDN, March 30, 1995, pg 82.
References
1. Tiwari, Shyam, Low-cost relativehumidity transmitter uses single logic

Get buck-boost performance

from a boost regulator
Tom Gross, Linear Technology Corp, Milpitas, CA
he SEPIC (single-ended, primary-inductance-converter) topology is generally a good choice for voltage regulators that must produce an on output
voltage that falls in the middle of the input-voltage range, such as a 5V output
from a 2.7 to 6V input, The topology has
some disadvantages, however. The efficiency of a SEPIC circuit fares worse than
that of buck and boost regulators, and
SEPIC designs often involve the use of
large, complex magnetic components,

thereby complicating the design task.
Figure 1 shows a simple and efficient alternative topology. When the input voltage is lower than the output voltage, the
circuit operates as a normal boost regulator. The inductor, L1, stores energy
when switch Q1 is on and the boost diode,
D1, is reverse-biased. While D1 is off, the
output capacitor, C1, delivers the load
current. When Q1 turns off, L1 reverses its
D1
MBRM120
L1
10 H
VIN
2.7 TO 6V
LQN6C100
MURATA
MOTOROLA
VOUT
5V AT
500 mA
1 F
CERAMIC
+
47 F, 16V +
AVX TAJC
TANTALUM
0.1 F
CERAMIC
6
Figure 1
100 F, 10V
AVX TPSC
TANTALUM
Q1
Si9424
SILICONIX
10
SW
R1
220k
C1
100 F, 10V
AVX TPSC
TANTALUM
1M
VIN
1
polarity, thereby forward-biasing D1. L1

then charges C1 and delivers current to
the load. The inductor voltage adds to the
input voltage to generate the output voltage.
The low-battery comparator in IC1,
which usually checks battery levels, monitors the output voltage through its LBI
pin. IC1s internal comparator output
switches low (sinking current). This action turns the p-channel Q1 fully on, cre-
8
LBO
IC1
LT1308A
VC
FB
LBI
47k
SD
GND
2
7
R2
100
MMSD4148T1
MOTOROLA
330 pF
Q2
TPO610T
SILICONIX
274k
48.7k
VSHDN
100k
VIN
2.7 TO 6V
This circuit can both boost and step down the output voltage, depending on whether the input voltage is lower or higher than the output voltage.
98 edn | July 11, 2002
www.ednmag.com
design
ideas
ating a low-impedance path to the out90

put. When the input voltage is the
Figure 2
VIN=6V
same value as or greater than the
output voltage, the circuit functions like
85
VIN=5V
a linear regulator. In this case, the interVIN=4.2V
nal comparators output assumes a highimpedance state. The voltage at the gate
EFFICIENCY (%) 80
VIN=3.3V
of Q1 begins to pull up through R1, a 220k resistor, so Q1 begins to turn off. This
75
action forces the output voltage to deVIN=2.7V
crease, and the comparator eventually
again switches states from high to low
70
(sinking current). The comparators low
0
100
200
300
400
500
600
state causes the output voltage to rise
IOUT (mA)
again, and the cycle repeats. Thus, the circuit begins to operate as a linear regula- The efficiency of the circuit in Figure 1 depends on whether the circuit acts as a boost converter or
tor, with Q1 acting as the pass transistor. a linear regulator.
The circuit can also disconnect the input-to-output current path, unlike a thereby turning off the transistor. Hence, tor. When the input voltage exceeds the
conventional boost regulator. The shut- the shutdown operation disconnects the output voltage, the circuit operates as a
down signal connects to the gate of Q2, a input-to-output current path. Figure 2 linear regulator in which efficiency is aplogic-level, p-channel MOSFET, as well as shows how the efficiency of this linear- proximately VOUT/VIN.
to IC1s shutdown (SD) pin. When the boost regulator depends on its mode of
shutdown signal goes low, it turns off IC1 operation. When the input voltage is lowand turns on Q2. This action delivers VIN er than the output voltage, the efficiency Is this the best Design Idea in this
(via R2, a 100 resistor) to the gate of Q1, of the regulator is that of a boost regula- issue? Select at www.ednmag.com.
Circuit transmits ARINC 429 data

he ARINC (Aeronautical Radio Inc)
429 specification defines the air
transport industrys hardware and
protocol standards for the transfer of digital data between avionics systems. Circuitry that can implement elements of
the 429 spec is often an essential part of
control and sensor electronics intended
for the aviation environment. ASIC chips
for this purpose are commercially available, but they typically require nonstandard power supplies (for example,
15V) and wide parallel interfaces.
Therefore, its sometimes inconvenient to
accommodate them in 5V microcontroller-based designs. The circuit in Figure 1 serves the Tx (transmit/output)
portion of the 429 spec. The design implements a high-speed ARINC-429-compliant transmit function using a single 5V
100 edn | July 11, 2002
TABLE 1FORMAT OF SPI BITS

Byte
1
2
3
4
5
ARINC field
Label
LS data
Data
Parity+MS data
Spacer byte
7
L
N
N
OPB
0
6
L
N
N
SSM
0
5
L
N
N
SSM
0
SPI bit
4
L
N
N
N
0
3
L
N
N
N
0
2
L
N
N
N
0
1
L
SDI
N
N
0
0
L
SDI
N
N
0
LL = ARINC label (most-significant bit transmitted first)

SDI = ARINC source/destination identifier
NN = 19 data bits (may include SDI and SSM fields; transmit least-significant bit first)
SSM = ARINC sign/status matrix
OPB = Odd parity bit (makes total count of "1" bits in the 32-bit word odd)
supply rail and 74HC series chips.

The physical transmission medium for
the 429 standard is 78 shielded, twisted-pair cable that uses a complementary, differential bipolar RZ (return-tozero) waveform (Figure 2). The voltages
are the net differentials that the biphase
drive develops: For example, the differential is 10V when you drive the Data A
signal in Figure 1 to 5V and the Data B
signal to 5V. In addition to the signal
levels, a 429 system must closely control
the rise and fall times to conform to the
specification. This control limits both inwww.ednmag.com
design
ideas
tra-cable signal crosstalk

1.50.5 SEC 1.50.5 SEC
TRANSMIT
and EMI radiation that
C
D
might interfere with senHI 10V1V
sitive aircraft communication and navigaFigure 2
tion systems. The
operation of the trans5 SEC5%
NULL 0V0.5V
A
mitter in Figure 1 centers
around IC1, a 4-bit1610 SEC2.5%
B
word FIFO memory. The
serial ARINC bit stream
LOW 10V1V
comes from the microcontrollers synchronous
serial-peripheral interface
(SPI); the C input of IC1 The ARINC spec imposes rigid requirements on waveforms.
buffers the data stream. In
addition, the D input of IC1 serves as a of bits in the IC1 FIFO (indicated by
buffered ARINC-enabled bit (the micro- QR1) resets the ARINC RDY bit in IC3B
controllers J port, bit 2). When low, this and enables IC3A. If IC1s D bit (Pin 10)
bit disables the ARINC transmitter logic is also high, it gates the 100-kHz square
and permits other system peripherals to wave to the IC4 multiplexer. This action
causes the sequential gating of 5, 0, and
use the SPI hardware.
Bits A and B of IC1 go unused. The 5V onto the A/B data-output signals in
100-kHz ARINC high-speed baud rate ARINC-compatible waveforms. The LRC
comes from the 1-MHz reference sup- network at the output ensures compliplied to the IC3A divide-by-10 circuit. The ance with the 429 requirements for rise
100-kHz signal drives IC1s shift-out (SO) and fall times. The circuit must process
pin and the IC2 pulse gate. The presence five 8-bit SPI bytes to generate each 32-
IC3A
1
2 HC390
AN7
ARINC RDY
5V
13
16
SCK
19
HC13
1
9
4
5
6
SDO
PJ2
14
QR
SI
QA
OE
IC1
R HC40105
A
B
D
11
C
C
Q
D
D 10
9
HC088
IC2
Q
R
12
14
15
11
10
9
6
1
5
2
4
8
2.5V
NULL
2.5V
6.5V
LOW
13V
bit, 429-compliant output word. Table 1

shows the format of the SPI bits. The first
four bytes in Table 1 combine to form a
32-bit ARINC 429 word. The 32-bit
word, reading from right to left, starts
with byte 1 (again, reading from right to
left), then tacks on byte 2, and so on.

16
33 H
0
13
C
1
2
3
A
IC4
B
C HC4052
0
1
2
3
3
C
6
VSS
7
DATA
A
0.022 F
36
ARINC 429
OUTPUT
0.022 F
33 H
36
DATA
B
BAT5401CT
IN5817
5V
5V
B C D
0.1 F
100 kHz
1 MHz
6.5V
15
10
REFERENCE
HI
5V
16
12
SO
Figure 1
13V
5V
15
RECEIVE
QA
IC3B
1
2 HC390
8
5
10 F
+
AT 6V
VO
0.1 F
V+
IC5
LTC1046
OR MAX1680
LV
6
2
+
3
10 F AT 6V
G
3
This ARINC 429 transmitter operates from a single 5V supply and meets all timing requirements of the 429 spec.
102 edn | July 11, 2002
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design
ideas
Circuit divides frequency by N+1

Bert Erickson, Fayetteville, NY
igital frequency dividers usualCLK
ly use flip-flop stages that
9
Figure 1
connect the Q pin to the D
15
3
2 4
5 6
7 11
10 13
12 14
data-input pin of the following stage.
D0 Q0
D1 Q1
D2 Q2
D3 Q3
D4 Q4
D5 Q5
OUT
This configuration creates a binary waveform that you can feed back to the input.
1
You can divide any integer lower than 2N
2
with minimal stages, where N is the numIC1
5
3
ber of stages. These dividers can easily se74LS260
12
lect one frequency from 100 for a receiv13
er. However, as the applied clock rate
approaches the ratings of the devices, de1 divider displays no decoding spikes, even at high clock rates. The added NOR circuit
coding spikes appear. As a result, youd be This N
ill-advised to use the dominant pulse in ensures proper start-up.
such a waveform for clocks
or strobes. The diFigure 2
vider in Figure 1
uses a ring configuration,
CLK
and the stages connect Qto-D, without using the Q
Q0
output, to provide a binaQ1
ry sequence. Consequently,
the circuit can divide only
Q2
by N1, but it produces a
clean waveform at an apD0
plied clock rate thats subA
B
C
stantially higher than you
1 divider; note the propagation delay from the NOR gate in
can apply to conventional These waveforms illustrate the operation of the N
binary dividers using flip- Section C.
flops from the same
process families.
feedback lines, providing that you clock pulse rises. Then, with all Q outputs
If the last Q in a cascade of 74xx174 ground the corresponding input pins. low, D0 rises a short time later to allow
flip-flops connects to the D input, the You can take the output from any Q pin the sequence to repeat. D0s transfer can
loop becomes a shift-register ring count- and use an additional stage, such as Q5, take place only after the next clock pulse
er. Moreover, the circuit can operate at a for a buffer. Although the output of the rises. This factor creates an additional
clock rate higher than that of any other NOR gate resembles one of the Qs, you time slot to make the total N1. Section
configuration. Unfortunately, when you should not use it as an output.
C shows the propagation delay attributturn on the power or ground the reset
Figure 2 shows the timing diagram for able to the NOR gateapproximately 10
pin, all Q outputs go low and remain low the divider. Section A of the diagram nsec for most logic-circuit families and
when you apply the clock. To circumvent shows the state of D0 and the Q outputs less than 5 nsec for the F and S series. This
installing a preset circuit that must op- in the start-up condition before the first propagation delay is the only additional
erate at a high clock rate, you can place and second clock pulses arrive. Note that delay in the loop. A comparison of the
one NOR gate with its propagation de- when the power turns on or when the re- output waveforms with those from a
lay in the loop. This addition ensures that set pin connects to ground, the Q outputs 74xx90 divide-by-5 counter shows
the divider always starts and continues to are all low, and D0 is high. D0 then trans- prominent decoding spikes from this
function properly. Because this gate refers to Q0 on the rising edge of the first counter. The N1 divider had no spikes
ceives inputs from all stages at once, it clock pulse. Section B of the diagram and operates at a much faster clock rate.
features parallel carry and has the prop- shows the output for a repetitive seerties of a parallel-carry counter. For quence starting with Q0. Section C is an
simplicity, Figure 1 does not show the re- expanded representation of the end of Is this the best Design Idea in this
set line, and you can delete the broken the sequence. Note that Q2 falls after the issue? Select at www.ednmag.com.
104 edn | July 11, 2002
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Maintain precise timing with PCs speaker logic

DS Oberoi, CEDTI, and Harinder Dhingra, GCET, Jammu, India
recise timing control is paramount in data acquisition and
analysis and especially in digital-signal processing. The easiest way of maintaining timing control in a PC is to use
delay loops. The disadvantage of this implementation is that the delay loops
elapsed time depends on the systems operating frequency. Hence, a program
works accurately with a single operating
frequency, but you must modify it for
other frequencies. You can use add-on
cards to achieve timing control, but
theyre costly, and, for simple
operation, they remain underused. This Design Idea
explores another way to obtain timing control. You can
implement a stable delay
loop with the aid of the PCs
speaker logic. In PC/AT architecture, a 16-bit 8255
timer/counter IC is available,
and the ICs operating frequency of 1.1931817 MHz is
fixed across the entire range
of PC families. You can use
this fixed-frequency feature
to implement a delay loop.
In PC/AT architecture,
Counter 0 serves as a system
timer and to maintain the
time of day. Counter 1 generates pulses and serves as
the DRAM refresh-rate generator. The PC uses Counter
2 for sound generation
through the PCs speaker.
Only Counter 2 is available
for an implementation of the
delay loop. You can enable or
disable Counter 2 by setting
bit 0 of the 8255s Port B to
1 or 0, respectively. For our
purposes, Counter 2 operates as a rate generator (in
Mode 2 operation). In this
mode, the counter automatically decrements by one
count with every counter
clock pulse (1/1.1931817
106 edn | July 11, 2002
MHz0.838095 sec counter_count_

time). Hence, the total period that
Counter 2 can measure is approximately
54.92 msec (65,5360.838905 sec).
Listing 1 gives the details of implementing the delay loop. You can download
Listing 1 from the Web version of this
Design Idea at www.ednmag.com.
The software sets Counter 2 to operate in Mode 2 by setting the control-word
value to 0b4h and by writing this controlword data to the control-register port
(043h). A routine called delay_loop() ac-
LISTING 1DELAY-LOOP ROUTINE
tually implements the delay loop. The

routine first configures Counter 2 by
writing the control word in the control
register. Then, the program loads
Counter 2 with starting (ffffh) data at address 042h in a 2-byte operation. The
routine then enables the counter by setting bit 0 of the 8255s port B (in other
words, port 61h) to one. Once enabled,
Counter 2 automatically decrements by
one count every 0.8380958 sec. Before
calling the delay routine, the software
computes the total of Counter 2s count
required for the desired delay
(desired_delay_time).
A
while loop repeatedly reads
back Counter 2s data from its
input port (042h) in a 2-byte
operation.
The two bytes combine to
produce 16-bit data (counter_data). This data helps to
compute the elapsed counts
(count_elapsed); as soon as
the required count is reached,
the software exits this loop.
The routine disables Counter
2 by setting bit 0 of the 8255s
port B to 0 before returning
to the calling program. Thus,
it achieves the desired delay.
Because the count depends
on a fixed operating frequency across the entire PC family, you can use this method to
implement a precise and stable timing loop. You can
achieve delays of approximately 20 sec to 54.9 msec.
The software is in Turbo
C and assembly language
and was tested it in MS-DOS
mode on a 450-MHz Pentium II computer.

in this issue? Select at
www.ednmag.com.
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design
ideas
Voice feedback enhances engineering calculator

he screen shot in Figure 1 repreFormula Bar: User-Defined formula is entered into the
Cell B2
sents a Microsoft Excel 2002
Figure 1
worksheet designed to implement VFI (voice-feedback interface)
for an engineering calculator. The voiceinterface technique has both practical
and educational aspects. It automates the
common task of finding the values of two
resistors for a given ratio. It also demonstrates the latest advances in natural-language programming technology with an
example of the technologys actual imText-To-Speech
plementation in CAD/CAE systems. A
Toolbar
single user-defined function RR (resistor
ratio) encapsulates both the computation Cell A2 serves for data (ratio) entry; cell B2 contains the user-defined formula 5RR(A2). In automatengine and the VFI. The function uses ic calculation mode, every time you enter a new ratio value in A2, the system recalculates R1, R2,
VBA (Visual Basic for Applications) with and Relative Error.
the code placed in the standard code
module of Excel File (Listing 1). You can sheet from the Web version of this Design
The core search algorithm, which condownload Listing 1 and the Excel work- Idea at www.ednmag.com.
tains outer and inner loops, sequentially
LISTING 1CODE MODULE FOR VOICE FEEDBACK
108 edn | July 11, 2002
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design
ideas
tests each pair of values, R1

and R2, to find the best approximation of the target
ratio. In other words, the algorithm tries to minimize
the absolute error: (ABS
(R1/R2Ratio)). The values
of R1 and R2 come from the
E24 EIA-standard series,
but you can apply the same algorithm to
any other standard series, such as E48,
E96, or E192. The VFI sends the statusnotification message in a verbal form instead of showing the Message Box. The
VFI uses the built-in Excel 2002 Speech
Object with the following syntax:
Application.Speech.Speak
<String Variable or Constant>, True,
where <String Variable or Constant>
contains the actual spoken text, and the
second property is set to True for asynchronous mode. Listing 2 is an example
of voice-error notification in the case that
you enter non-numeric data as the ratio
(data-validation error message):
110 edn | July 11, 2002
(for example, A2 in Figure 1) for the ratio

(data-entry cell) and another cell (for example,
B2) to display the results.
Enter the formula
RR(A2) into cell B2.
Now, every time you enter a new ratio value into
cell A2, the system automatically calculates and displays R1, R2, and Relative Error, and sends the status voice notification. The notification is either OK to
confirm the successful completion of the
calculation or an error notification in the
case of a data-validation or computation
error. Note that some macros in Microsoft Office applications could result in
potentially dangerous and harmful actions, and some may contain viruses. You
use the macros at your own risk without
warranties of any kind.
LISTING 2VOICE-ERROR NOTIFICATION
Using the technique is simple. Open

Excel File, switch to the Visual Basic Editor window (press Alt-F11), add the
standard module, and paste the code
from Listing 1. From the Debug menu
item, choose Compile VBA Project, save
the file with any name, and close the Visual Basic Editor window. Make sure you
activate the text-to-speech tools (in the
menu: ToolsSpeechShow Text To
Speech Toolbar). Check whether you are
in automatic- or manual-calculation
mode (in the menu: ToolsOptions
Calculation). Set the mode to automatic; otherwise, youd have to use the F9 key
to force a new calculation every time you
enter a new ratio value. Choose any cell

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design
ideas
Simple circuit provides motor-feed control

ecause we needed a small grinding
machine, we modified an old
milling machine that lacked a control system. The table of the grinding machine needed only to move back and
forth with adjustable feed. Using an existing dc servoamplifier, a servo motor,
and limit switches, we devised the circuit
shown in Figure 1. Because the motor
had no tachometer, we used part of the
motor voltage as feedback. We reduced
the feedback voltage from the
Figure 1
motor to approximately 8V
by using the resistors R1 to R3. (Motor
voltage60V, maximum amplifier input10V, R1R233 k, and R310
k.) This feedback voltage feeds back to
the speed-command differential-voltage
input. You must be careful with the feedback-signal polarity to avoid an uncontrolled runaway of the motor. The actual
command voltage connects to the
tachometer input, which is not differential. Using the appropriate gain and control-loop adjustments available on most
drivers, you can obtain good motor response. This design uses the 15V the
SERVOAMPLIFIER
DIFFERENTIAL
INPUT
R3
R1
R2
SIGNAL
GAIN
MOTOR
OUT
LIMIT
LIMIT
TACHOMETER
GAIN
TACHOMETER
INPUT
15V
S1
MANUAL S
2
15V

0
AUTO
+
FEED
P1
+
C1
D1
K1
LS
LS+
D2
D3
K1
K1
A defunct milling machine served as the platform for this grinding-machine motor controller.
Simple circuit provides
motor-feed control ........................................81
Linear power driver works
from single supply ........................................82
Circuit performs high-speed
voltage-to-current, current-tocurrent conversion ........................................84
Chip recorder customizes
phone ringer....................................................88
Op amp linearizes
attenuator control response ........................90
Whats Up section at www.edn.com.
www.edn.com
driver supplies to power the control circuit. Switch S1 enables manual and automatic modes. For both modes, potentiometer P1 reduces the control voltage,
and C1 filters it. Two LEDs, D1 and D2,
show in which direction the axis moves.
This indication can be especially useful in
automatic mode if the potentiometer is
turned to its zero position. The driver becomes disabled in one direction when the
inputs Limit or Limit no longer connect to 15V; that is, when the limit switches LS or LS (located at each end of
travel) become activated. The following
describes the operation of the two modes:
In manual mode, the momentary

switch S2, selects 15V or 15V. If
you use two separate switches, take
care to avoid shorting both power
supplies together.
In automatic mode, the polarity of
the voltage depends on the setting of
relay K1. Upon power-up, K1 is off;
thus, a positive voltage goes to the
driver. The motor moves in the positive direction until limit switch
LS activates. At that instant, the
driver is disabled (for the positive
direction), and the relay, K1, energizes. K1 holds itself on through its
July 25, 2002 | edn 81
design
ideas
contact, diode D3, and the limit

switch, LS. You need the diode to
avoid feeding voltage to the Limit input through the activated LS
limit switch. The motor now runs in
the opposite direction until the limit switch LS activates. At that instant, the driver is disabled (for the
negative direction), and relay K1

turns off. The cycle begins anew.
The values of the components the circuit uses depend principally on the selected servoamplifier and motor, thus
Figure 1 shows no values. The machine
has worked satisfactorily in two shifts for
more than two years. During this period,
contrary to our expectations, we never

readjusted the servoamplifier.

issue? Select at www.edn.com.
Linear power driver works from single supply

Tom Gay, Darmstadt, Germany
n low-power, single-supply
VS
analog applications, it is
R8
Figure 1
10k
often desirable to main5V
Q2
tain precise control of voltages
IRF9Z24N
much greater than the positiveR7
100k
supply rail. The circuit in Figure 1
Q1
allows you to amplify the input
BC547
voltage, VIN, by a factor, A, which
C2
R3
D3
R6
resistors R1 and R2 set. The output
47 pF
10k
STPSD745
100k
R5
C3
VIN
voltage, VOUT, equals AVIN, where
2.2k
2.2 nF
AR2/(R1R2). The op amp re4
2 _
ceives its supply from a single 5V
R2
6
IC
VOUT
1
1.3k
source, and the discrete output
3 +
7
stage operates from a rectified
D2
1N4148
voltage, VS, from a power source
5V
D1
R1
that meets the requirements of the
C1
1N4148
9.1k
220
pF
application. When the circuit neiQ3
R4
IRFZ46N
ther sinks nor sources current, the
R9
10k
VS
op amps output settles to a voltD4
age higher than 1.9V (Q1 is comC4
7.5V
100 nF
pletely off) but lower than the
threshold voltage of the n-channel
FET, Q3, minus 1.2V (two diode
drops). When VIN rises from a given state, the op amps output volt- This simple circuit allows you to control voltages far in excess of the positive-supply rail.
age drops and gradually turns on
Q1. This action results in a voltage drop LT1013, and AD8551. All these op amps maintain the idle window in which
across R8, turning on Q2. This process deliver load currents as high as 5A at volt- both Q1 and Q3 are off. The op amps incontinues until the voltages at the op ages as high as VS40V. One important put-voltage range must include ground.
amps two inputs match. A decreasing VIN feature of the design is its insensitivity to D3 is necessary only in cases in which
causes the op amps output voltage to rise component tolerances. The values for R1 sources connect to the output. D3 preto the point at which Q3 conducts enough and R2 in Figure 1 yield A8. The value vents reverse current flow from the exto pull down VOUT. Capacitors C1, C2, and of R9 depends on VS. You could use a log- ternal source through Q2. Such a situaC3 are necessary to prevent oscillation.
ic-level FET, such as the IRLZ34N for Q3; tion can arise when the circuit serves in
The circuit, useful as a power driver for you can then omit the components D1, a battery-charger application.
pulse generators, offers rise and fall times D2, D4, R4, R9, and C4. In this case, the op
of less than 15 sec, virtually independ- amps output connects directly to the gate
ently of the supply voltage, VS. You can of Q3, and you must reduce the value of Is this the best Design Idea in this
test the design with op amps LMC7101, R6 to lower the base voltage of Q1 to issue? Select at www.edn.com.
82 edn | July 25, 2002
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design
ideas
Circuit performs high-speed voltage-to-current,

current-to-current conversion
Ali Mehmed, Nokia UK Ltd, Southwood, UK
he circuit in Figure 1 performs acC9
tive voltage-to-current conFigure 1
OPTIONAL
version or acts as a variablegain current mirror with high precision
R5
R3
R12
and bandwidth. A typical application is
402*
100*
220k
testing high-speed ICs or other devices
OPTIONAL
5V
that have inputs designed to be driven
INPUT
R2
10V
(BNC) VIN
100*
R4
from current-steering DACs to enable a
2 7
402*
7
2
6
modulated voltage source to control the

R1
6
3 +
devices. The circuit thus simplifies the
IC1
4
3
100
+
IC2
AD8055AR
testing of such devices in isolation, beC2
C1
4 AD8055AR
R13 5V
10
nF
10
nF
cause modulated voltage sources are
56
R14
200
readily available, but modulated current
R6
1k*
sources generally are not. A further use of
3V
the circuit could be for easy and precise
control of a current-controlled, variable10V
S
gain amplifier by using an adjustable dc
2
7
R15
G
6
voltage source at the input. Figure 1
1k
3
+
3V
shows the circuit configured as a voltageIC3
4
Q1
D
OPTIONAL
C
AD8055AR SST175
OUTPUT
3
to-current converter. The overall gain
10 nF
IOUT (SMA)
with the component values shown is 1
Q2
mA/V, but you can easily realize other
10V
R16
BSS83
D
gains by altering the component values.
1k
G
3 + 7
3V
6
Note that the output of the circuit can
SS
OPTIONAL
2
C4
both source and sink current.

IC4
4
10 nF
OP177GS
Starting at the input, VIN, because the
5V
S
C5
10V
input of amplifier IC1 is at virtual
10 pF
5V
POWER
ground, the parallel combination of R1
10V
SUPPLIES
R7
RV1
R9
and R2 provides a 50 termination for
10V
19.6k*
1k
1k*
the input signal. IC1 then inverts this signal with a gain of R3/R2. Amplifier IC2
C7
C6
10 pF
provides a gain of R5/R4 1 to the
10 nF
3V
REFERENCES
signal received from IC1, but its nonin3V
10V
R8
verting input is tied to the 3V reference.
R10
10k*
2
Therefore, its output and the top of the
7
3V
100
6V
6
current-sense resistor, R6, is offset by 6V
3 +
IC5
C8
4
with respect to ground when VIN is zero.
R11
OP177GS
+ 10 F
6.8k
The current source comprises amplifier
10V
IC3 and the p-channel JFET, Q1. The
NOTES:
choice of a JFET, rather than a bipolar
1. RESISTORS MARKED WITH * ARE 0.1% TOLERANCE.
transistor, ensures very high speed, zero
2. ALL OTHER RESISTORS ARE 1% TOLERANCE.
dc error, and almost perfect linearity in
3. DECOUPLING FOR ICs IS NOT SHOWN.
the output-current characteristic. The
JFET is an SST175 from Vishay/Siliconix
(www.vishay.com); it has a guaranteed This versatile circuit can serve either as a voltage-to-current converter or as a variable-gain current
IDSS current of 7 mA, high speed, and low mirror.
84 edn | July 25, 2002
www.edn.com
design
ideas
capacitance. Amplifier IC3 clamps the

VDD
voltage at the source of Q1 and the
Figure 2
RSENSE
bottom of R6 at 3V. With no signal
passes
a
constant
input, therefore, Q1
S
quiescent bias current of 3 mA into the
3-mA constant-current sink involving

IC4 and Q2. The output current of the
G
circuit, which comes from the drains of
+
Q1 and Q2, is zero. When VIN assumes a
D
VDDVIN(t)
VIN(t)
.
IOUT=
level VIN above ground, the voltage at
RSENSE
the top of R6 increases by the same
amount. So the current through R6 and,
thus, the output current, IOUT, increases This topology represents a traditional voltageby an amount VIN/R6, equivalent to 1 controlled current source.
mA/V.
This circuit differs from the tradition- sink obtains the balance of its current,
al precision current-source topology VIN/R6, from the load.
The 6V reference that fixes the bot(Figure 2) in that, the op amp in Figure
1 clamps the bottom end of the sense re- tom of R7 derives from amplifier IC5s apsistor at a constant voltage rather than be- plying a nominal gain of 2 to the 3V
ing varied in response to the input signal. reference. You should trim the 6V refInstead, the voltage at the top end, which erence by means of RV1, such that the outwould normally be connected to a fixed put current is zero in the absence of an
voltage, varies in response to the input input signal; the quiescent currents in Q1
signal. Furthermore, because Q1 is always and Q2 are then equal. Note that this sinconducting, its gate-voltage variations gle adjustment entirely calibrates the sigare typically less than 200 mV in response nal path, canceling out the effects of reto changes in VIN. The result is that no sistor tolerance, amplifier dc errors, and
nasty current spikes transfer to the out- any tolerance in the 3V references but
put via Q1s gate-channel capacitance not the effects of finite open-loop gain.
when VIN makes a step to or from zero. In To ensure maximum bandwidth in the
a traditional circuit, because there is no signal path, the amplifiers are AD8055current sink, the op amp must com- ARs from Analog Devices (www.anapletely turn off the FET when the output log.com). These amplifiers can tolerate
current must be zero. In doing so, the op a total supply voltage of only 10V, so you
amps output slews several volts to satu- must operate IC1 from a split 5V supration near its positive supply rail, trans- ply and IC2 and IC3 from a single-ended
ferring a high-amplitude current spike 10V supply, because their inputs are 3V
onto the output. A spike of the opposite above ground.
You can obtain optimum dc accuracy
polarity and similar magnitude is created when the op amp has to recover from and stability by using an OP177GS amsaturation and slew in the opposite di- plifier for IC4 and IC5 and a high-quality
reference IC, such as the AD780BR, for
rection to again turn on the FET.
The 3-mA constant-current sink com- generating the 3V reference. You generprises amplifier IC4 and n-channel ate the 3V reference by applying a fixed
MOSFET Q2. IC4 clamps the voltage at gain of 1 to the 3V, using an inverting
the top of current-sense resistor R7 at circuit similar to that used in Figure 1 for
3V. Because the voltage-reference cir- deriving the 6V reference. You should
cuit fixes the bottom of R7 at 6V, the use 0.1% tolerance resistors where
quiescent current through Q2 remains shown, and you can optionally include
steady at 3 mA, equal to the current R12 to provide 0.11% of additional gain
through Q1 when VIN is zero. When VIN to compensate for the finite open-loop
assumes a level VIN below ground, the gain of amplifiers IC1 and IC2. You can
voltage at the top of R6 decreases by the further optimize the dc stability by insame amount; the current through Q1 cluding R15 and R16, although the protothen falls below 3 mA; and the current type does not use these resistors. In tests,
86 edn | July 25, 2002
without C9, the bandwidth of the circuit

with a 1V peak-to-peak sinusoidal input
was 80 MHz when the circuit drove a resistive 100 load. The output rise and
fall times with the same load and a 1V,
2.5-nsec input step are just 5.5 and 4.8
nsec, respectively, with no overshoot, as
measured with a 500-MHz oscilloscope.
The typical output compliance ranged
from 1.7V to 2.8V. The maximum
undistorted output-current swing extended from +2.1 to 2.1 mA.
For optimum frequency response and
linearity, you should use the circuit to
drive a virtual-ground load; in other
words, you should use a high-bandwidth
op amp configured as an current-tovoltage converter. If you use any other
load, which must have low impedance in
any case, and it is partly capacitive, you
may need a small capacitor, C9, across R5
to optimize the overall transient response of the circuit at the expense of
some speed. You can also configure the
circuit to operate as a current-to-current
converter with an overall gain of 0.1
mA/mA by omitting R1, replacing R2 and
R13 with 0, and increasing the value of
R12 to 470 k. You can use this configuration, for example, to scale the outputs
from commercial current-steering DACs
that typically have full-scale outputs in
excess of those that ASIC inputs need.
Thus, you could test an ASIC with current-driven inputs by using such a circuit
between each input and each DAC output. Note that, in this configuration, amplifier IC1 is configured as a current-tovoltage converter with a gain of 0.1V/mA
and presents a virtual-ground to the
DAC outputs, a load that normally ensures optimum linearity performance
from the DACs. The circuit supports
both current-sourcing and current-sinking DACs, because the circuit can source
as well as sink current. For high-speed
operation, you may need a small capacitor across R3 to cancel the effect of the
DACs output capacitance and any stray
capacitance.

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design
ideas
Chip recorder customizes phone ringer

Don Schelle and Ted Salazar, Maxim Integrated Products, Sunnyvale, CA
ompanies usually purchase one
type of telephone for all
Figure 2
employees, which is understandable, especially if they obtain
50V/DIV
a discount for buying in quantity. One
ringer sound for everyone can pose a
problem, though, if the sound of a
ringing phone makes a dozen people
pause and look at their telephones.
Equally annoying is the absence of a visual message indicator. Obliging everyone who suspects they may have a mes-
sage to lift the handset and listen for

a special message tone is far from ideal. By placing a circuit in series with
the telephone, you can customize a
phone ringer without modifying the
phone (Figure 1). The heart of the
ringer is a chip-recorder IC, IC5,
which can play as much as 10 seconds
of telephone-quality recorded sound.
The ringer signal of a typical telephone

exceeds 200V p-p.
9V
BATTERY
0.1 F
+ 22 F
35V
1
CVH
IN
IC1
MAX1684EEE LX
2
AIN
15
0.47 F
6
VCC
D1
75V
220
VCC
4.7k
1W
D2
75V
VCC
VCC
OUT
5
4
0.01
F
CC
AGND
1 F
Figure 1
16
VCC
VCC
CTC IC4A
DM74LS221D (16)
1
2
3
LS1
13
4
17
18
19
OUT+
0.47
F
1 F
FS1
FS2
8
0.47
F
1 F
SHDN
14
47 H
VCC
OUT
6 VCM
16
SS
IC6
MAX4295
21
VCC
VCC
2.2k
VCC
22k
10k
47k
AOUT
15 PVCC
2
PVCC
0.1 F
IN
20
10
11
8
5
28
VCCA
TRA
TRB
CLR
VCC
16
GND
8
47 H
100k
RC COM
14
VCC
5 pF
VCC
15
1k
300k
7
FB
9
SYNC/PWM
11
STBY
CVL 4
1 F
300k
GND
2
8
5
12
BOOT
REF
ILIM/SS
VCC
S1
IC3
1
4
IN MAX- CLEAR
835EUK
0.1
F
VCC
D3
3
1k
IC2
H11AA1
10
0.1
F
100 F
10V
16
PGND
SHDN
VCC
13
LX
0.1
F
10 H
14
100 pF 0.47 F
14
15
VCC
VCCD
1
A0
A1 2
A2 3
A3 4
IC5
A4 5
ISD1110P
A5 6
VCC
MIC
A6 9
MIC REF
A7 10
25
1 nF
AGC
RECLED
27
ANA IN
REC
23
VCC
ANA OUT
PLAYL
24
PLAYE
SP+
26
SP
XCLK
VSSD
VSSA
0.1 F
12
13
VCC
1 F
PGND PGND GND GND

330 F
1 F 13
12
This circuit plays as much as 10 seconds of recorded sound in place of the ring from a telephone. It also indicates when someone has called.
88 edn | July 25, 2002
www.edn.com
design
ideas
A high-efficiency stepdown converter,

IC1, allows the circuitry to operFigure 3
ate from a supply voltage of 5 to
14V.
An optocoupler and associated frontend circuitry monitor the line, sensing
when the line receives a high-voltage
C2
1 nF
ringer signal (Figure 2). Zener diodes D1
and D2 prevent the on-hook voltage from
activating the optocoupler. Comparator
PLAYL
IC3 latches LED D3 on when a call is received, and a pushbutton switch, S1,
PLAYE
clears the comparator. The circuit shown
in Figure 3 records as much as 10 secRECORD
onds of sound in the chip recorders proprietary multilevel EEPROM. A switchmode, Class D audio amplifier, IC6,
maintains high efficiency and delivers
adequate power to an 8 speaker; even
a PC speaker will work.
VCC
ISD1110P
VCCO 28
VCCA 16
12
VSSO
VSSA 13
14
SP+
15
SP
20
ANA IN
R1
1k
C2
0.1 F
R2
C3
5.1k
21
23
0.1 F
ANA OUT
PLAYL
24 PLAYE
18
MIC REF
27 REC
17
C4
MIC
25
19
0.1 F
RECLED
AGC
26 XCLK
R5
C6
470k
4.7 F
16
SPEAKER
R3
10k
C1
220 F
ELECTRET
MICROPHONE
C5
0.1 F
R4
10k
Using the EEPROM internal to IC5 in Figure 1, this circuit records as much as 10 seconds of sound.
Op amp linearizes attenuator control response

Mike Irwin, Shawville, PQ, Canada
rofessional-audio equipment
15V
commonly uses Analog DeFigure 1
vices (www.analog.com)
7.5k
SSM2164
MASTER
R2
high-performance, quad-voltage-con1
GAIN CELL
100k
VREF
trolled SSM2164 attenuator. The control
G 2
15V
4
response is 30 dB/V, with 0V produc560
pF
100 pF
3
ing unity gain. Attenuation increases as
R1
500
100k
the applied control voltage increases in
2
VIN
IC1
the positive direction. The circuit in Fig1
GAIN-CONTROL
LF353A
VOLTAGE
ure 1 extends the range of applications
3
VOUT0.67log(VIN/VREF)
+
0 TO 15V
for this versatile chip by providing a sim100 pF
ple means of linearizing the control reR4
sponse. The result is an amplifier with
gain directly proportional to the control
R3
30k
6
30k
7
6
5
voltage. In addition, the circuit also funcAUDIO
G

IC2
7
IN
tions as a simple logarithm generator.
AUDIO
560 pF
LF353B
25V
P-P
OUT
SSM2164
5
You can use a single SSM2164 to make
25V P-P
+
MAXIMUM
SLAVE
500
MAXIMUM
two high-quality, linear voltage-conGAIN
CELL
trolled amplifiers using this method. The
four gain cells in the SSM2164 are tightly matched, current-in, current-out You can obtain both a gain-controlled output and a logarithmic output using this configuration.
transconductance multipliers. The conEach voltage-controlled amplifier uses arithmic voltage output in response to a
trol response of each gain cell is:
gain10(V/0.67). The cells are noninvert- two gain cells. A master cell in the feed- linear voltage input. This log voltage then
ing structures.
back loop of an op amp generates a log- goes to the control pin of the second
90 edn | July 25, 2002
www.edn.com
design
ideas
(matching) slave cell, which processes

the audio signal. Op amp IC1
Figure 2
maintains its inverting input at
virtual ground by servo-controlling the
gain of the master SSM2164 cell, which
connects to the negative reference voltage. The output of IC1 is a logarithmic
function of the input: VOUT
0.67log[(VINR2)/(VREFR1)]. VIN is the The lower trace is a 0 to 3V triangle wave,
gain-control voltage, and VREF is the neg- which you use to modulate the 10-kHz sine
ative reference voltage. VOUT then drives wave in the upper trace. Note the linear moduthe control pin of the slave cell. Substi- lation envelope.
tuting the expression for VOUT for V in
the expression for gain yields the follow- gain with the indicated component valing: gain(VINR2)/(VREFR1), which is the ues. The gain decreases smoothly to 70
desired linear response.
to 80 dB as the control voltage deOp amp IC2 converts the slave cells creases (Figure 2). The voltage-conoutput current to an audio voltage with trolled amplifier then shuts off coma gain of R4/R3. The overall expression for pletely (attenuation100 dB) when the
the gain is: gain(VINR2R4)/(VREFR1R3). control voltage drops to within a few milIf R1R2 and R3R4, the expression re- livolts of 0V. Negative voltages make the
duces to: gainVIN/VREF, and gain (in output of IC1 swing close to the positive
decibels)20log(VIN/VREF). Setting VIN to rail, but IC1 promptly comes off the rail
15V and VREF to 15V produces unity when the control voltage returns to the
92 edn | July 25, 2002
0 to 15V range. The circuit produces no

audible clicks and works well at lower
supply voltages, such as 5V.
For best performance, IC1 should be a
low-offset, low-input-current unit, and
IC2 should be a high-quality, low-noise
audio op amp. However, you can obtain
reasonably good performance with inexpensive op amps, such as the TL072 and
LF353. The prototype unit achieved a
control range of 75 to 80 dB, using an
OP-290 for IC1. The control-voltage
feedthrough on the audio output is minimal, varying 10 to 20 mV when you
sweep the gain through a 70-dB range.
The noise and distortion performance is
excellent, because the design uses the
gain cells in the standard configuration
in the SSM2164 data sheet.

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design
ideas
Where is the wiper?

Chuck Wojslaw and Dave Gillooly, Catalyst Semiconductor, Sunnyvale, CA
ou enjoy significant advantages
5V
when using DPPs (digitally
Figure 1
programmable potentiome8
3
ters) with increment/decrement serial in2
U/D
terfaces. Programming the serial interface
IC1
1
5
CAT5113/5114
is simple and fast, and you can adjust the
INC
6
potentiometer in real-time applications.
DB0 (LSB)
CS
DB1
The interface, however, provides no in7
4
DB2
formation about wiper position, and this
5V
DB3
information is important in some appliC1
cations. If, for example, you use the po1 nF
tentiometer to control a parameter in a
PE
15 10
15
10
closed-loop, real-time application, the
R1
1
1
1k
data reflecting the final wiper settings can
5
CI
6 Q1
6
4
IC2
DB4
be valuable in evaluating both the prod4
IC3
11 Q2
12
JAM1
DB5
uct performance and the circuit design.
CD4029BS
12
14
14 Q3
13
JAM2
DB6
The circuit in Figure 1 keeps a digital
13
2
2 Q4
3
JAM3
DB7 (FLAG)
record of the DPPs wiper position by us3
JAM4
ing two presettable CD4029 up/down
5
9
BUS
9
7
CO
CI
counters, IC2 and IC3. The counters monBIN/DEC
5V
itor the control signals INC and U/D of
PIN 16=VCC=5V
the DPP, IC1.
PIN 8=VSS=0V
During power-up, the wiper assumes
position (00)10, which it takes from pre- Two up/down counters keep track of a digitally programmable potentiometers wiper position.
viously programmed nonvolatile memory. Also during power-up, R1 and C1 dif- differentiated signal serves to preset the DPPs having as many as 256 taps. The
ferentiate the 5V power supply; this binary counters to (0000 0000)2. Thus, DPP does not wrap around when the
the DPP and the external IC2/IC3 coun- wiper advances to its upper or lower limters are at the same point after power-up. it. The counters, however, do wrap
Where is the wiper? ....................................107
The level-sensitive up/down signal es- around. To identify the case in which the
tablishes the direction of movement of digital counter is not in synch with the
PLD code creates
the DPPs wiper and the direction of the DPP, you can use the MSBs of the counPWM generators ..........................................108
count. The edge-sensitive INC signal ad- ters as flags. DB7 can serve as a flag for
Square-wave modulator has variable
vances both the wiper and the counter. the 32-tap CAT5114 and the 100-tap
frequency and pulse width ........................110
The INC pin of the DPP responds to neg- CAT5113. You can change the initial
Expanded-scale indicator revisited ..........112
ative-edge triggering, and the clock input count during power-up to something
of the counter responds to positive-edge other than zero by preprogramming the
Butterworth filter has adjustable
triggering. If the signal driving the INC DPP and setting high and low levels on
group delay ..................................................114
line is a pulse (a common occurrence), the JAM inputs of the digital counters to
Single transistor sequences
the two inputs are compatible.
the desired value.
multiple supplies ..........................................116
The Q outputs of the counters (DB0
to DB7) indicate in binary notation the
location of the wiper. You can use the Is this the best Design Idea in this
same circuit, using two counters, for issue? Select at www.edn.com.
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August 8, 2002 | edn 107
design
ideas
PLD code creates PWM generators

Clive Bolton, Bolton Engineering Inc, Melrose, MA
he PLD (programmable-logicdevice) code in Listing 1 creates
arbitrary-resolution, pulse-widthmodulated (PWM) generators. PWM
generators are useful as low-bandwidth
D/A converters in hardware of microprocessor-based systems. When you pass
it through a simple RC lowpass filter, a
PWM waveform becomes a voltage thats
approximately equal to the PWM duty
cycle times the supply voltage. In practical systems, the driving hardware is imperfect, so the minimum value is never
zero, and the maximum value never
equals the positive-voltage rail.
The software module in Listing 1 automatically generates the required hardware from two compile-time parameters:
PWM_WIDTH and AVALUE. PWM_
WIDTH sets the number of possible
steps in the PWM comparison. For example, 6 bits yields 26, or 64, steps.
AVALUE sets the value at which the
PWM initializes upon power-up or reset
(set to one-half scale in the example in
Listing 1).
The module has two major sections: a
holding register, which stores the PWM
value, and a counter, which generates the
PWM waveform. You can update the
holding register independently of the
PWM counter. The holding registers value automatically strobes into the PWM
counter when the counter overflows. The
module takes the CLOCK, ACLR, ENABLE, WRITE, and DATA[PWM_
WIDTH-1..0] inputs. CLOCK is the
master system clock; all signals other
than ACLR must be synchronous with
the clocks rising edge. ACLR initializes
the hardware to the power-up state and
loads AVALUE into the holding register.
When ENABLE0, the PWM output becomes 0 (off); when ENABLE1, the
PWM generator produces the PWM
waveform at the Q output. Asserting
WRITE for one clock cycle strobes the
data presented on DATA[PWM_
WIDTH-1..0] into the holding register.
The PLD code uses Alteras (www.
altera.com) AHDL high-level design language; you can directly compile the code
108 edn | August 8, 2002
LISTING 1AHDL CODE FOR PWM GENERATOR
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design
ideas
into any of Alteras PLDs. Using an

EP1K10TC100-3 PLD, a design with parameters set to the default values in Listing 1 operates as fast as 139 MHz. Although we wrote the code for Alteras

devices, you can readily translate the design structure and flow into VHDL or
Verilog. You can download Listing 1
from the Web version of this Design Idea
at www.edn.com.
Square-wave modulator has

variable frequency and pulse width
few years ago, I worked at a diskdrive company. We had a plating facility that required square waves to
drive the high-voltage plating operation.
The challenge was that the square waves
pulse width had to be variable, along with
the duty cycle. Also, the amplitude of the
pulses had to be adjustable. The circuit in
Figure 1 satisfies all these criteria. The
circuit delivers a unipolar (adjustable
from 0 to 12V) pulse with adjustable fre-
sions of the pulse train to ground. The

other half of the op amp, IC2B, serves as a
level shifter that allows amplitude control
over the range 0 to 12V. You can modulate the amplitude at low frequency by
varying the amplitude-control voltage.
quency and pulse width. The first half of

a dual, retriggerable monostable multivibrator, IC1A, generates the frequency of
the pulse train. The 100-k potentiometer, R1, along with R2 and C1, sets the adjustable frequency. R3, R4, and C2 set the
adjustable pulse width in the second section of the multivibrator, IC1B. The accoupled op amp, IC2A, running openloop, delivers a 12V pulse output. D1
and D2 clamp the negative-going excur-

5V
5V
R1
R2
100k 5.1k
FREQUENCY
ADJUST
14
C1
4.7 F
5V
CEXT
R4
5.1k
C2
4.7 F
15 REXT/CEXT
1
2.2k
R3
100k
IC1A
74LS123
CLR
Q 13
Q 4
PULSE-WIDTH
ADJUST
6
12V
CEXT
12V
7 REXT/CEXT
IC1B
9 A 74LS123
1 F
5
10
Q
B
12 X
11 CLR
Q
10k
4
6 _
2.2 F
IC2A
LT1057
5 +
8
10k
D2
1N4148
5V
D1
1N4148
X
1k
12V
2.2k
33O pF
7 1
3+
1N4148
12V
Figure 1
4 1N4148
2 _
0 TO 12V DC
AMPLITUDE CONTROL
IC2B
LT1057
7.5k
IC3
2 _
OPA627
VOUT
2
45
X
3 +
8
2.2 F
12V
This variable-frequency circuit allows amplitude modulation of its pulse-train output.
110 edn | August 8, 2002
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design
ideas
Expanded-scale indicator revisited

Abel Raynus, Armatron International Inc, Melrose, MA
A
he visualization aid that a previ50

40
60
30
ous Design Idea describes allows only
70
20
2
80
3
the expansion of the upper
VOLTS
10
1
F
i
g
u
r
e
1
4
90
end of the scale (Reference 1). But
0
100
what can you do if, according to your
0
5
project requirements, you need to expand
(a)
A
the middle region of the scale? Figure 1a
50
40
60
illustrates the challenge. A voltmeter
30
70
20
80
comprises a 100-A dc meter and a series
VOLTS
10
90
resistor. The voltage under test, VTEST,
2
3
0
1
100
ranges from 0 to 5V. The voltage changes
4
0
5
between 2 and 3V (the green zone) are
(b)
of interest. But at the same time, you cannot ignore the voltages from 0 to 2V and In a, the 2 to 3V green zone occupies only 20% of the scale; in b, this zone expands to 80%.
from 3 to 5V, and you need to be able to
R 4R 5
observe these voltages. With a linear scale, sistor values as follows:
VT 2
VCC .
the green zone consumes only 20% of the
R 3R 4R 5
2V
200 k;
R1
full-scale range. Your objective is to ex10 A
In this case,VCC5V,VT12V,VT23V;
pand this zone to 80%, leaving 10% at the
3 2 V
hence,
R3R5200 k, and R4100 k.
lower end and 10% at the upper end of
12.5 k;
R 1 R 2
the scale (Figure 1b). The circuit in Fig9010 A
Reference
ure 2 solves the problem. The window
R1 R1 R 2 200 12.5
1. Raynus, Abel, Indicator features
comparator, IC1, controls the variable

13
.
3
k

.
R2
R1R1 R 2 20012.5
impedance of the voltmeter. Analog
expanded scale EDN, Feb 21, 2002, pg
switches S1 and S2 provide a contact-log86.
You can calculate resistors R3, R4, and
ic AND function and put resistor R2 in
parallel with R1 only upon closure of both R5 from the equations for the threshold
switches. This closure occurs when VTEST voltages:
is between the threshold voltages VT1 and
R5
VCC ;
VT1
VT2 (Figure 3). You can calculate the reR 3R 4R 5
VO1
5V
Figure 3
Figure 2
R3
200k
VT2
+
_
R4
100k
A
R6
10k
R1
200k
R7
10k
VO2
S2 IS ACTIVATED
VT2
VO1
VT1 _
5V
R2
13.3k
S1
S2
IC2
CD4066
A window comparator and two analog switches collaborate to expand

the green zone in Figure 1.
112 edn | August 8, 2002
VTEST
VO2
IC1
LM393
R5
200k
VTEST
S1 IS ACTIVATED
VT1
100
90
80
70
SCALE
DIVISIONS 60
50
(A)
40
30
20
10
0
VTEST
R1
R1 R 2
R1
1
VTEST
Within the thresholds of the window comparator, R2 connects in parallel with

R1 to expand the scale of the voltmeter.
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ideas
Butterworth filter has adjustable group delay

William Stutz, Maxim Integrated Products, Sunnyvale, CA
he Sallen-Key realization of a
5.25-MHz, three-pole ButFigure 1
terworth filter has a gain of
100 pF
2V/V and can drive 75 back-terminatR1
ed coax with an overall gain of 1 (Figure
VCC
75
221
332
1). Used to reconstruct component-video
+
(Y, Pb, Pr) and RGB signals, this filter has
MAX4390
R2
75
_
an insertion loss greater than 20 db at
330 pF
R3
0
V
C
EE
1
13.5 MHz and greater than 40 db at 27
VCC
82 pF
MHz (Figure 2). Like the antialiasing fil604
0.1 F
604
ter before an ADC, this filter removes the
higher frequency replicas of a signal following a DAC. To preserve quality in the
0
NOTES:
video waveform, you should minimize
VEE
1. R3 IS THE 75 LOAD. REMOVE R3 IF YOU USE AN EXTERNAL LOAD.
group-delay variations in the filter and
2. ALL RESISTORS ARE 1%.
0.1 F
3. ALL CAPACITORS ARE 2%.
any group-delay differential between fil4. R2 IS FOR GROUP-DELAY ADJUSTMENT.
ters. That requirement mandates a means
for adjusting the filters group delay without affecting its bandwidth. In Figure 1, This three-pole Butterworth video-reconstruction filter has adjustable group delay.
the addition of R2 in series with C1 and R1
creates a lag-lead network.
Keeping the sum of R1 and R2 constant
and equal to the original R1 value pre0
serves bandwidth by preserving
Figure 2
the dominant-pole frequency. Increasing the R1 value, on the other hand,
introduces a lead term that lowers
dB 20
group delay by reducing the rate of
change in phase. For R20 and
R1332 in the circuit shown, the average group-delay variation over the filter
40
bandwidth is about 25 nsec. Raising R2 to
3 6 1
3 6 1
3 6 1
3 6 1
3 6 1
3 6 1
3
31.6 and lowering R1 to 301 decreas100 Hz
10 kHz
1 MHz
100 MHz
es the variation to approximately 15 nsec,
and setting R259 with R1274 The typical filter response for the circuit of Figure 1 is R1R2332.
decreases it to approximately 7 nsec. The
last case has a less-than 0.5-dB effect
on band-edge selectivity but does not
R1=332, R2=0
80
change the filters 3-dB bandwidth (Fig70
R1=301, R2=31.6
ure 3).
GROUP
DELAY
(nSEC)
60
5V
+
10 F
5V
10 F
+
R1=274, R2=59
50
40
Figure 3

114 edn | August 8, 2002
4
5
FREQUENCY (MHz)
Selected values of R1 and R2 allow control of group-delay variation over the filters passband.
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design
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Single transistor sequences multiple supplies

David Chen, Linear Technology Corp, Milpitas, CA
any DSP chips, microprocessors, only one pnp transistor to provide the
FPGAs, and ASICs require multi- necessary logic. Figure 2 shows a dual
INTVCC
VOUT1
ple power supplies that must de- power supply that uses the described cirR3
liver different voltages in a specific start- cuitry to sequence the outputs.
R1
up sequence. Out-of-sequence voltages
When VOUT1 is low,VOSENSE2, the voltage
Q1
can cause excessive input current, logic
INTVCC
R4
errors, or even device failure. To sequence
VOUT1
R
2
different supplies, a common
R3
Figure 1
approach is to regulate a lowR1
VOSENSE2
er voltage from a higher voltage using a
Q1
VOSENSE3
linear regulator. Another approach is to
R4
V
OSENSE4
Figure 2
use a series of Schottky diodes. Although
R2
simple in concept, these approaches can
VOSENSEN
be expensive and difficult to implement
VOSENSE2
in applications that require more than
You can obtain multiple-output sequencing by
two power supplies. Figure 1 shows a A simple one-transistor circuit synchronizes
adding ORing diodes.
simple, low-cost approach that requires two outputs.
VOSNS1B
SENSE1
S1
0
1000 pF
S1+
SENSE1+
0
0.1 F
10
VIN
22 F
50V
+
INTVCC
QVIN
TG1 4
30.1k
1%
FDS8936A
1M
30.1k
1%
0.22 F
20k
1%
RUNSS1
0.1 F
LTC1628
B
10k
20k
1%
2N3906
10.5k
1%
100 pF
20k
1%
VOSNS1
0.01
F
ITH1
0.01
F
SGND
ITH2
VOSNS2
330 pF
330 pF
100
pF
56 pF
56 pF
68k
68k
20k
1%
1
RUN/SS1
2
SENSE1+
3
SENSE1
4
VOSNS1
5
FREQSET
6
STBYMD
7
FCB
8
ITH1
9
SGND
10
3.3VOUT
11
ITH2
12
VOSNS2
13
SENSE2
14
SENSE2+
VIN
FLTCPL
TG1
SW1
BOOST1
BG1
EXTVCC
INTVCC
PGND
TG2
SW2
BOOST2
BG2
RUN/SS2
FDS8936A 7
2
BG1
27
26
25
10 F
6.3V
MBRM140
GND
TP3
1
CMDSH-3
10
EXTVCC
VIN
7
20
16
17
18
19
15
FDS8936A
10
1
0.1 F
BG2
S2+
FDS8936A
SENSE2+
SENSE2
VOSNS2B
S2
0
6.4 H
SW2
CMDSH-3
0
TG2 2
63.4k
Figure 3
150 F
6.3V
0.01
+
24
28
23
22
21
SW1
1000 pF
VOUT1
5V
4A
TP2
6.4 H
180 F
4V
0.01
+
VOUT2
3.3V
4A
+
10 F
6.3V
MBRM140
GND
3
TP6
X5
INTVCC
SIGNAL
GROUND
POWER
GROUND
1 F
4.7 F
10V
This dual-output supply uses the simple circuit in Figure 1.
116 edn | August 8, 2002
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design
ideas
feedback for VOUT2, goes high, and the

second supply,VOUT2, shuts off (Figure 3).
When VOUT1 approaches its nominal level, Q1 turns off. Q1 then relinquishes control of VOSENSE2, and VOUT2 resumes its normal start-up process. The process is
similar for power-down sequencing.
When VOUT1 is high, VOUT2 operates nor-
mally. When VOUT1 goes from high to low,

VOSENSE2 goes high and shuts off VOUT2.
More specifically, R3 and R4 set the clamping voltage for the VOSENSE2 pin when
VOUT1 is low, and R1 and R2 determine the
VOUT1 voltage level at which Q1 turns off.
In cases of multiple supplies, you need
only add ORing diodes at the collector of
Q1 (Figure 3). The design uses an

LTC1628 dual-output controller. You can
see the sequenced-output waveforms in
Figures 4a (at turn-on) and 4b (at turnoff).
Figure 4
VOUT1
VOSENSE2
VOUT2
(a)
(b)
These supply-voltage waveforms occur at turn-on (a) and turn-off (b).
118 edn | August 8, 2002
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design
ideas
GIC resonator has inherent amplitude control

Lutz von Wangenheim, University of Applied Sciences, Bremen, Germany
he circuit in Figure 1 is based on a
classic GIC (generalized impedance
VCC
SINGLE SUPPLY
converter). The sine-wave-oscillator
TO VCC
circuit has inherent amplitude
+
VOUT1
IC1
Figure 1
stabilization and normally op
RCC
erates from dual power supplies. How5k
VEE
ever, if you connect an additional resisPORT 1
kC
PORT 2
R
R
RN
R
tor, RCC, to VCC, you can operate the cirZ
ZIN2
IN1
1k
1k
1k
1k
cuit with one supply (with VEE0V). You
400 nF
25 nF
C/k
V
can adjust the oscillation frequency by
EE
R1 2.5k
(5k FOR
0.95k RCOMP
varying R1. RCOMP ensures oscillation and

SINGLE
IC2
VOUT2
does not affect the oscillation frequency.
SUPPLY)
+
The remaining passive components are
VCC
four equal-value resistors, R, and two capacitors, kC and C/k, where k is a scaling
factor. This modification of the classic
GIC structure incorporates an addition- A GIC-based resonator provides inherent amplitude control and low distortion.
al resistor, RN, between both inverting opamp inputs. The GIC topology has excel1
1 R N R COMP
1
f0 =
.
lent high-frequency properties and thus Z IN1 = 2C 2R jkC R R .
2C RR 0
finds extensive use in active-filter circuits.
For the circuit values in Figure 1, IC2
The GIC structure can simulate a
Note that, for RCOMPRN, the expresgrounded inductance or a grounded sion for ZIN1 represents the input imped- saturates, providing a clipped sinusoidal
FDNR (frequency-dependent negative ance of an ideal FDNR. The FDNR, to- signal at VOUT2. VOUT1 is a filtered version
gether with an ohmic shunt resistance of that signal. Thus, no extra circuitry is
resistance).
You can explain the function of the cir- from Port 1 to ground, forms a tuned cir- necessary for amplitude stabilization.
cuit by starting with the GIC input im- cuit with the inherent capability to oscil- However, the quality of the sinusoidal
pedance at either Port 1 or Port 2. A late. In reality, however, the oscillation signal at VOUT1 depends on the Q factor of
straightforward analysis of the circuit would die out because of parasitics aris- the resonator circuit, as the following
ing from lossy capacitors and imperfect equation states:
yields the input impedance at Port 1:
amplifiers. The circuit in Figure 1 comk RR 0
pensates for these losses by using the secGIC resonator has
.
Q=
ond portion of ZIN1, representing a negaR
NR COMP
inherent amplitude control..........................89
tive capacitance for RCOMPRN. In
Three parts provide tenfold increase
practice, you should choose RNR and a
For the values shown, a quality factor
in switcher current..........................................90
resistor ratio, RCOMP/R, close to unity (for Q100 results with a capacitance scaling
example, RCOMP/R0.95 to 0.98). If you factor k4, C100 nF, and (RN
IC maintains uniform bias
perform the analysis at Port 2 of the cir- RCOMP)50. VOUT1 provides a signal
for GaAs MESFETs..........................................92
cuit, the input impedance, ZIN2, repre- with a total harmonic distortion lower
Add gain to an absolute-value
sents an ideal inductance in series with a than 1% at f01 kHz. The peak-to-peak
amplifier ..........................................................94
negative resistor. Shunting this imped- amplitude of the sinusoidal signal is apUse a PIC for automatic
ance with a capacitor-resistor branch proximately 1V lower than the total supbaud-rate detection ......................................96
(C/k and RCOMP in Figure 1) creates a loss- ply-voltage span.
less LC tank circuit. This tank circuit can
Design low-duty-cycle timer circuits ..........98
oscillate if you satisfy the condition
RCOMPR. The circuit starts reliably and Is this the best Design Idea in this
oscillates at the following frequency:
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August 22, 2002 | edn 89
design
ideas
Three parts provide tenfold increase

in switcher current
Wayne Rewinkel, National Semiconductor, Sunnyvale, CA
ndustrial-control circuits often
derive their power from widely varying sources that can exceed the 40V
maximum rating of popular switching
ICs. This Design Idea presents a simple,
flexible, and inexpensive buck switcher
that converts an input voltage as high as
60V to 5V at several amps. The circuit is
unique in that it boosts current with almost no compromise in performance,
size, or cost. It should be of interest to
anyone who has ever searched for a simple step-down switcher with an output
current or input voltage exceeding that of
off-the-shelf devices. Such a search usually entails a far more complex and costly solution than the one this Design Idea
presents. National Semiconductors
(www.national.com) LM2594HV and
LM2597HV both feature 60V maximum
input, 150-kHz operation, 0.7A peak output, and on/off capability. The 2597 adds
soft start, delay, a power-good flag, and a
pin you can use to bootstrap most of its
bias current from VOUT. Although both
devices are single-chip switchers, you can
also use them as driver-controllers with
only slight modifications to their standard buck-regulator circuit configurations. Figure 1 shows the 2597HVM in a
typical 5V, 0.5A configuration that uses
all the ICs features. Figure 2 shows the
higher current configuration with only

three additional components to boost
output current to more than 6A.
As a bonus, the circuit in Figure 2 also
provides overcurrent and short-circuit
protection for Q1. The rugged self-protection features of the IC also apply to Q1,
provided that the transistor has sufficient
heat sinking; L1 stays out of saturation if
you select R1 properly. If the peak current
in R1 produces a voltage drop large
enough to cause Q1 to saturate, then the
IC experiences an overcurrent condition,
causing its internal protection modes either to disable the switch for the remainder of the pulse period or to skip pulses.
Q1 needs to be a fast switch to minimize
switching losses. The transistor also
needs to have minimal storage time to
avoid pulse skipping at low duty cycles.
Table 1 shows circuit performance at its
maximum input voltage, 60V, under a variety of output conditions. The table also
includes component values and ratings
necessary to select sources for L1, C1, and
C2.
Efficiency for test conditions of
VIN60V and IOUT2 to 6A measures
77% for VOUT5V and rises to 87% for
VOUT12V. Efficiency is highest for the
VIN range of 30 to 40V, where its peak is
2% higher than the values in Table 1.
Power dissipation is almost evenly divided among L1, D1, and Q1, so you should
space these components to avoid hot
spots and provide heat-sinking for as
much as 3W each at maximum current
and voltage. A good layout should include lots of ground plane and short,
wide traces on high-current paths. Output voltages other than 3.3, 5, and 12V
are also available by substituting the adjustable version of the 2597. This IC requires an added resistor pair from VOUT
to the FB pin to ground. Calculate resistor-divider values to set the FB pin at
1.23V for the desired output voltage. Although this design example uses the
LM2597HVM-5.0, you can easily apply
this current-boost technique using only
three additional parts to any of Nationals second-generation buck devices, effectively extending their output-current
capability more than tenfold. You need
not use HV devices for applications with
a maximum input voltage lower than
40V. The following seven steps provide a
simplified procedure to select component values for a wide range of operating conditions, including those that Table
1 lists:
1. Choose R1 to drop 1.5V at the inductors peak operating current of
IOUT20%. A higher current peak can
D44H8
R1
Figure 1
L1
Q1
VOUT
VIN
7
VIN
L1
VSWITCH 8
VIN
FB
PGOOD
5
CSS
ON/SS
DELAY
GND
VSWITCH 8
VIN
4
FB
VOUT
LM2597HVM5.0
VBIAS 3
C1
Figure 2
PGOOD
5
2
CD
D1
C2
LM2597HVM5.0
3
VBIAS
C1
R0
CSS
ON/SS
DELAY
GND
R2
R0
1
2
D1
C2
CD
This classic buck-regulator circuit efficiently steps down voltage.
90 edn | August 22, 2002
You can increase output current more than tenfold with the addition
of only three components.
www.edn.com
design
ideas
TABLE 1EFFICIENCY VERSUS OUTPUT VOLTAGE AND CURRENT

Efficiency
(%)
77
78
77
77
85
86
87
88
VIN
(V)
60
60
60
60
60
60
60
60
VOUT
(V)
5
5
5
5
12
12
12
12
IOUT
(A)
1
2
4
6
1
2
4
6
R1
)
(
1
0.5
0.33
0.22
1
0.5
0.33
0.22
R1
(W)
0.06
0.15
0.5
0.7
0.16
0.42
1.5
2
R2
)
(
4.7
4.7
4.7
4.7
4.7
4.7
4.7
4.7
force Q1 to saturate, causing the IC to deliver base current in excess of 0.7A to Q1.
This action triggers the ICs pulse-bypulse current limit and protects the IC,
Q1, and the load from further excessive
current. An output short circuit causes
the IC to reduce its clock frequency, protecting D1 and L1 from high continuous
peak current. The power dissipated in R1,
which can be a significant part of the total loss, subtracts from the dissipation in
Q1, allowing for a smaller heat-sink requirement. This dissipation is:
R1(IOUT)(IOUT)(VOUT/VIN).
2. Choose R2 to be small enough to
quickly turn off Q1 but not so small that
it diverts much needed drive current
away from Q1 and causes early current
limit. A value of 4.7 (the value that
Table 1 uses) is a good trade-off value for
most applications.
3. Choose Q1 to be a fast switch with
VCE rating greater than 60V and ICE rating of two times the desired current peak.
This ratio generally provides a high beta
over the working-current range. The
D44H8 works well to more than 6A output in a TO-220 package and more than
2A in an SOT-223 package.
Q1
D1
D4448 (V at A)
D4448 60/1
D4448 60/3
D4448 60/6
D4448 60/6
D4448 60/1
D4448 60/3
D4448 60/6
D4448 60/6
L1
H)
(
68
47
2
34=68
2
20=10
150
2
94=47
DMT2-79
DMT2-47
L1 ESR L1 LSAT C1
)
F)
(
(A)
(
0.13
1.2
100
0.086
2.4
220
0.065
4.8
470
0.056
7.2
680
0.25
1.2
100
0.17
2.4
220
0.07
4.8
470
0.04
7.2
680
4. Choose D1 to be a Schottky diode

rated for the maximum values of VIN and
IOUT. D1 dissipates much of the total power loss when VINVOUT, so look for a
diode rated at less than 0.5V forward
drop.
5. Choose L147 H/IOUT for
VOUT3.3V, 68 H /IOUT for VOUT5V
and 150 H/IOUT for VOUT12V.
Choose the nearest L1 value with a saturation and working current rating greater
than IOUT. Coilcrafts (www.coilcraft.
com) SMT DO5022 family works well for
output current to 1 or 2A, but you need
larger cores for currents greater than 3A.
You can tie these SMT inductors in series or in parallel to extend their use to 3
to 4A. Theyre also available in stackedcore versions for higher current use.
Through-hole inductors, such as Coilcrafts DMT2-xx family, are physically
larger but provide lower losses, especially for output current greater than 5A.
6. Choose C1 for ripple-current rating
and C2 for low ESR. A minimum capacitance value for C1C2/10100 F IOUT
works well at low current, but, as current
rises to several amps, you need larger values to meet ESR and ripple-current re-
C1 ESR
)
(
0.22
0.11
0.065
0.047
0.22
0.11
0.065
0.047
C2 RMS
(A)
0.5
1
1.8
2
0.6
1
1.7
2.4
C2
F)
(
100
220
470
680
100
220
470
680
C2 ESR C2 RMS
)
(
(A)
0.22
0.12
0.11
0.2
0.065
0.3
0.047
0.6
0.22
0.11
0.11
0.2
0.065
0.25
0.047
0.4
quirements. Ripple-current rating depends on several variables, but a conservative choice is half the maximum output current for C1 and one-fourth the
maximum output current for C2. High
ripple-current capability may require
paralleling several capacitors for C1. Select C2 to have ESR less than 0.1 / IOUT
to keep the VOUT peak-to-peak ripple less
than 50 mV. Choose capacitors by looking at those targeting high-temperature
use in switching power supplies with
published ESR and ripple current ratings.
Then, select a voltage rating higher by at
least 50% than the expected operating
voltage.
7. R0, CSS, and CD are optional. You can
leave these pins open if you dont intend
to use them. You can shut off the circuit
by pulling Pin 5 low and then turn it on
again with soft-start by allowing Pin 5 to
float high. Refer to the 2597 data-sheet
graphs for CSS and CD values necessary to
set the desired soft-start and power-good
flag delay times.

IC maintains uniform bias for GaAs MESFETs

he gate-turn-on threshold voltage for GaAs MESFETs (gallium-arsenide metal-semiconductor field-effect transistors) varies considerably from
part to part, even within a given lot. That
behavior makes biasing difficult, especially if you want to design the device into
a high-volume product. To overcome this
92 edn | August 22, 2002
drawback, you can introduce a current

sensor that monitors the bias current and
provides feedback to the gate input (Figure 1). IC1 combines a current sensor and
an error amplifier. Intended as a powercontrol IC for power amplifiers, it senses
the drain-source current, IDS, at the
source; compares and integrates the dif-
ference between voltage drops across

RSENSE and RG1; and feeds back an output
voltage to the MESFET gate. The feedback
adjusts IDS until the two voltage drops are
equal, thereby achieving uniform source
current, regardless of the MESFETs gatethreshold characteristics. The expression
for drain-source current is:
www.edn.com
design
ideas
VDD
CHOKE
IDS =
VPC R G1
.
4 R G3 R SENSE
RF OUT
RF IN
MESFET
Figure 1
Current through RG1 depends on a

voltage, VPC, with respect to the negative
supply, VEE, applied to the power-control
input at Pin 4. You can implement VPC
with a voltage divider, a reference, or a
variable-voltage source. Because the gate
voltage is negative with respect to the
source, you must modify IC1s supply
voltage to ensure a negative gate drive for
the MESFET: Connect the VCC pin to
ground and the ground pin to VEE. You
can easily modify this uniform-bias circuit for biasing bipolar transistors and
MOSFETs, as well.
0.1
RSENSE
1k
4 PC
RG2
1k
2
SR1
SR2
IC1
MAX4473
VPC
RG1
1k
1
7
OUT
3R
1 nF
VEE
R
_
3
VGND
SHDN
VCC
8
SR3
6
RG3
GND
5
VEE

VEE
A smart-bias IC ensures uniform bias for GaAs FETS in high-volume products.
Add gain to an absolute-value amplifier

he absolute-value amplifier is a
basic building block in test-andmeasurement and signal-processing
applications. The addition of a DPP (digitally programmable potentiometer) adds
another dimension, G (gain), to this key
circuit. Because the gain is programmable, you can use the circuit as an absolutevalue amplifier (G1) or an absolute-value attenuator (G1). The single-supply
circuit in Figure 1 comprises IC1, which

is an inverting amplifier for positive-polarity signals only, and IC2, the summing
amplifier. For the summing amplifier, R1
represents a programmable, variable resistance. This resistance is modeled as
pR2p(10 k), where p varies from 0 to
1/99 to 99/99 and represents the relative
wiper setting from one end of the potentiometer (0) to the other end (1). For in5V
8
Figure 1
U/D
INC
2
1
CAT5113
7
(W)
4
2k
5
6 R1
(L) 10k
10k
10k
VS
3
(H)
5V
13 _
12
IC1
LMC6064
+
14
1k
2.5V
Attenuate or amplify with this variable-gain absolute-value circuit.
94 edn | August 22, 2002
_
IC2
1
LMC6064
3
+
11
VOUT
put voltages above the reference, for example, VS2.5V and for voltages below
the reference, VS2.5V, VOUT2.5V
|p5VS|2.5V|GVS|.
The potentiometer, a Catalyst 5113,
has 100 taps and an increment/decrement interface. For this DPP, the circuit
gain varies from 5/99 to 5. The measured
accuracy of the circuit is approximately
1% for moderate values of gain (0.5 to 4)
and for a characterized end-to-end resistance, RPOT. During power-up, the
wiper goes to its stored value in nonvolatile memory. This stored value establishes the default value of the gain after power-up. The basic idea for this
absolute-value circuit came from Reference 1.
Reference
1. Cipri, Teno, Absolute-value comparator touts accuracy, size, EDN, March
7, 2002, pg 124.

www.edn.com
design
ideas
Use a PIC for automatic baud-rate detection

Ross Fosler, Microchip Technology, Chandler, AZ
utomatic baud-rate detection is
desirable in many applications. Mip
p
crochips (www.microchip.com)
standard USART module that the company embeds in most of its PIC
This bit stream is a general-case
Figure 1
For the baud-rate-detection
microcontrollers lends itself to a
signal typically appearing on the
Figure 2
scheme, this waveform represimple and easily implemented automat- RX pin of a PIC microcontroller.
sents an ideal control signal.
ic baud-detection scheme. The PIC18FXX2 data sheet defines the following in Figure 2 is an ideal control signal. You for an SPBRG value with the minimum
baud rate in bits per second:
take measurements from the rising edge, frequency of the next SPBRG. The value
and the pulse is symmetric. Figure 3 at which theyre equal is the border beFOSC
FOSC
(1) shows the simplified program flow for tween continuous and discontinuous op1; B =
X=
,
16 B
16(X + 1)
the baud-rate detection.
eration for any given input frequency.
where X is the value for the baud-rate
It is useful to know the valid frequen- The following two equations express this
generator and FOSC is the input clock fre- cy range for a baud rate, SPBRG value, equality and the continuity barrier:
quency.
and tolerable error. The following equa(EH + 1)(X)(B)(16) =
Figure 1 represents a general-case sig- tion defines error as follows:
(6)
nal typically seen on the RX pin of a PIC
(EL + 1)(X + 1)(16)(B).
BCB
(4)
E(BC ) =
,
microcontroller. The time, p, is the numB
ber of instruction cycles from the end of
(EL + 1)
(7)
X LOW =
.
the start bit to the beginning of the stop
where B is the desired baud rate and BC
+
(
E
H 1)(E L + 1)
bit. This definition allows you to relate is the calculated or actual baud rate. Subbaud rate, B, to the total time it takes for stituting Equation 1 for BC and using althe RX pin on the microcontroller to see gebra leads to the following result:
Thus, for any given frequency and a deeight bits of data. Eight is a convenient
fined error, the automatic baud-detection
FOSC = (E + 1)(X + 1)(16)(B). (5)
figure for a binary machine. Basically,
scheme always generates a good SPBRG
E is the error used to determine the value if it is above XLOW. Of course, you
8 FOSC
2F
(2) maximum and minimum frequencies for must select the frequency and baud rate
p=
; B = OSC .
such that SPBRG is less
a chosen baud rate and SPB 4
p
than or equal to 255, the
BRG value. For example, a
START
largest value that SPBRG
The term (FOSC/4) is the instruction good value for E would be
rate of a PIC microcontroller. The term 62%. Evaluating
supports. For example, for
Figure 3
8/B is the eight bit-times that the RX pin Equation 5 for
a 2% error, the lowest SPNO
RISING
sees. Relating the two baud-rate equa- the high and low limits of
BRG value before certain
EDGE?
tions,
clock frequencies become
error E yields a valid oscilYES
a problem is 25. A bootlator operating range. For
2F
FOSC
p
START TIMER
loader is an excellent exB = OSC =
; X = 1. (3) most SPBRG values, comp
16 (X + 1)
32
ample of an application
mon baud rates, and the
for this baud-rate-detecmost common clock freNO
RISING
EDGE?
The simplified result leads to a simple quencies, operating ranges
tion scheme. The simple
equation that you can easily implement overlap each other from
implementation uses minYES
on a PIC microcontroller. Count the to- one SPBRG to the next.
imal resources. It synchroSTOP TIMER
tal numbers of instruction cycles for eight Thus, the automatic baudnizes to a baud rate withbit-times. Divide the result by 32. (In oth- detection scheme synchroin one transmitted byte,
(TIMER/32)1
er words, shift the count right five times.) nizes with the source for
and you can most likely
Add a rounding bit. Then, decrement the most of the common consuccessfully synchronize it
LOAD SPBRG
value by one. Finally, load the SPBRG reg- ditions. However, some erto any standard baud rate,
ister with the result to synchronize the rors and clock frequencies
especially 9600 bps.
FINISHED
PIC microcontroller to the incoming never have a valid SPBRG
baud rate. It is important to select the (X) value.
This program-flow diagram
Is this the best Design
right control signal so that the microTo approach this prob- illustrates the principles of
Idea in this issue? Select at
controller samples the correct number of lem, you must compare the baud-rate-detection techwww.edn.com.
bits. For this implementation, the signal the maximum frequency nique.
96 edn | August 22, 2002
www.edn.com
design
ideas
Design low-duty-cycle timer circuits

Phil Rogers, Texas Instruments Inc, Rockwall, TX
esigning astable circuits using
VCC
0.1 F
the industry-standard 555 timer is
a straightforward process when
duty cycles are 50% or greater. However,
IC1
you must overcome the many pitfalls of
TLC555D
low-duty-cycle circuits to arrive at a de8
RA
VCC
sired result. Using only ideal components
4
3
VOUT
RESET
OUT
eases the design, but the components
7
DISCH
themselves are hard to obtain. Nonideal
6
THRES
RB
2
components get in the way of the easy5
TRIG
CTL
1
to-use standard equations and greatly
GND
multiply the tolerances. This Design Idea
C
0.1 F
uses the TLC555 CMOS timer. You can
use other versions of the popular 555
timer with appropriate variations in the
given parameters. For a stanThis classic 555-based timer is valid
Figure 1
dard, greater-than-50%only for duty cycles greater than 50%.
duty-cycle, low-frequency design (Figure
1), you would use the following design ure 2), required to implement the design.
Adding a bypass diode across RB allows
equations:
for designs with duty cycles lower than
t H = C (R A + R B ) ln(2);
50%. During the charging cycle, current
flows through RA and bypasses RB
t L = C R B ln(2);
through the diode. During discharge,
current flows through RB and the internal discharge transistor as usual. Because
(R A + R B )
DUTY CYCLE =
.
RB is now present only in the discharge
(R A + 2R B )
cycle, you can tailor the duty cycle to any
Charging current for the timing ca- desired point over the full range. Again,
pacitor flows through RA and RB until the using ideal components, the timing equacapacitor voltage reaches the upper tions are simple:
threshold voltage of 0.667VCC. The cat H = C R A ln(2);
pacitor then discharges through RB and
an internal transistor to the lower threshold voltage of 0.333VCC. Because RB is
t L = C R B ln(2);
present in both the charging and the discharging cycles, you cant implement
(R )
duty cycles lower than 50% in this conDUTY CYCLE = A .
(R B )
figuration. These idealized equations also
ignore several factors that slightly degrade the results for the higher range of
The factors you must consider in obduty cycles but greatly influence the retaining a design that agrees with calculasults of low-duty-cycle designs. These tions include the:
factors include propagation delays and
diode forward voltage,
the on-resistance of the internal dis propagation delays,
charge transistor. All these factors are
discharge-transistor on-resistance,
supply-voltage-dependent. Another fac ratio of RA to on-resistance, and
leakage resistance of the control-pin
tor for low-duty-cycle designs that does
capacitor.
not apply to high-duty-cycle designs is
Diode forward voltage depends on the
the effect of the RB bypass diode, D1 (Fig-
98 edn | August 22, 2002
current flowing through the diode. This

current can range from a few hundred
microamps to tens of milliamps. For a
fixed design, you can obtain this voltage
from manufacturers curves or actual
measurements you make by applying the
desired current through the diode. You
can also use the diode equation:
I = IS (eqV / kT1) .
Or, in terms of voltage:

VF =
I
1
ln 1 + =
I
0.026
S
I
38.46 ln1 + .
IS
This voltage subtracts from the charging voltage during the charging cycle and
affects the charge-ramp time. Propagation-delay times from the THRES
(threshold) and TRIG (trigger) inputs to
DISCH (discharge) add directly to the
period. These delays depend upon supply voltage. The formulas for the propagation delays (in nanoseconds) are:
T PHL 0.0162V CC 5 0.8207V CC 4
16.205V CC3155.62V CC231.88V CC
1558; TPLH0.0102VCC50.5044VCC4
9.6825VCC389.622VCC2401.04VCC
807.97.
Discharge-transistor on-resistance also
varies with supply voltage. This resistance
affects the discharge current. Also, when
you use low-value resistors for RA (for
low-duty-cycle designs), the combination of RA and the on-resistance yields a
voltage divider that affects the discharge
voltage. The on-resistance formula for resistance in ohms is:
RON59.135VCC0.8101.
Typically, youd place a small capacitor on the control pin that connects to the
upper internal-divider node. This capacitor has only a slight effect on the threshold-trigger voltages. The leakage resistance of the ceramic capacitor is approxwww.edn.com
design
ideas
imately 9 M. This value is high but still

accounts for approximately a 1.5% drop
in the trigger voltages because of the 80k divider resistors that the windowVCC
0.1 F
IC1
TLC555D
8
RA
VCC
4
RESET
7
D1
6
RB
2
1
OUT
VOUT
DISCH
THRES
TRIG
CTL
GND
0.1 F
Figure 2
The simple addition of a bypass diode makes
this timer circuit valid for low duty cycles.
100 edn | August 22, 2002
comparator circuit uses. When you take

all the cited parameters into account, the
design equations become considerably
more complicated:
These equations include all the known

parameters to obtain a nominal design
using the TLC555 timer. Tolerances in
each of the parameters cause additional
variations that you must consider. In addition, you must consider the effects of
tH = C R A
temperature variations. After you obtain
all this knowledge, the simple 555 timer

2 V CC
t
+
ln (3e PHL /(RON C ) )
(2 VCC3 VF ) presents a major math problem. Howev

er, thanks to modern computers, you can
t PHL ;
eliminate much of this tedious math using an Excel spreadsheet. It shows the results of calculations both with and without the bypass diode and includes the
t L = C (R B + R ON )
tolerancing parameters. You can downt
load the spreadsheet from the Web verln(3e PHL /(CR A ) ) 2.38
sion of this Design Idea at www.edn.com.
3R
ON
1
(R A + R ON )

+t .
1

PLH
2 3 R ON
(R + R )
ON
A
www.edn.com
design
ideas
High-side driver has fault protection

Carl Spearow, Tokyo Electron, Gilbert, AZ
igh-side drivers find common
24V
use in driving grounded soFigure 1
lenoid coils and other loads.
8
OFF
IN
Short-circuit protection for such drivers
5V
SHORT-CIRCUIT TEST
3 SHDN
is essential for avoiding damage from
1
OUT
IC1
wiring faults and other causes. Polymer
LP2951 (SO-8)
ON
fuses are generally too slow, and discrete
7 FB
1 F
current-limiting circuits are large and
30V
1
LOAD
GND
cumbersome. The circuit in Figure 1 uses
4
a small, low-dropout linear regulator as a
high-side switch and provides inherent
current limiting and thermal shutdown.
The regulator comes in an SO-8 package.
The zener diode provides transient pro- This simple high-side driver provides current limiting as well as transient protection.
tection, and the output capacitor ensures
stability of the circuit. The circuit can
drive a 24V load at 100 mA. These
Figure 2
are adequate specs for many solenoid valves, relay coils, and other moderate loads. During a short circuit, the regulator limits the current to 160 mA. This
current causes the die to overheat and enter a thermal-shutdown state. Upon removal of the short circuit, the device
cools down and resumes normal operaedn020822di298011
tion. The top trace in Figure 2 is the out-
Heather
High-side driver has fault protection ......103
Boost 3.3V to 5V with tiny
audio amplifier ............................................104
Add a signal-strength display
to an FM-receiver IC....................................106
Op amp linearizes response
of FET VCA ....................................................108
Convert voltage to potentiometerwiper setting ..................................................110
Make a DAC with a microcontrollers PWM timer ..............................110
www.edn.com
In the bottom trace, the output current limits itself to 160 mA during a short circuit.
put voltage during a 1.3-sec short circuit.

The bottom trace is the short-circuit current, which limits itself at less than 200
mA. Note that the regulator goes into
thermal shutdown after 500 msec, and
the IC then toggles on and off until removal of the short circuit.
September 5, 2002 | edn 103
design
ideas
Boost 3.3V to 5V with tiny audio amplifier

Wayne Rewinkel, National Semiconductor, Santa Clara, CA
D1
D3
his charge-pump circuit quietly
VIN
converts a 3.3V source to 5V
3.3V
6
+ C1
Figure 1
at 500 mA (figures 1 and 2).
150 F
VIN
8
16V
Nationals (www.national.com) LM48A2OUT
5
A1OUT
71LD power amplifier makes this design
C2
RH1
LM4871LD
RT
idea both possible and practical, thanks
150 F
300k
RS
10k
+ 16V
to its low output resistance, low cost,
0.6
A1+ 3
D2
D4
compact size, and high dissipation capa4
RH2
A1
CT
33k
bility. Its output resistance has an average
4.7 nF
2
COUT
value of 0.6: 0.5 to ground and 0.7
+ CIN
BP
150 F
150 F
CBP
SD
16V
to VIN. Because it is a CMOS IC, each outGND
16V
1 F
1
7
put can swing to its rail, limited only by
the resistance of the output transistor.
The leadless lead-frame package has a
NOTES:
1. D1 AND D2: MBRS12OT3.
footprint smaller than an SO-8 but pro2. C1 AND C2 ESR<11.
vides a JA of 56C/W when soldered to a
board with 1 sq in. of 1-oz copper ex- You can use a tiny audio amplifier to boost 3.3V to 5V with respectable current capability.
posed. This high thermal conductivity
couples with low output resistance to al- 50% duty cycle at a frequency approxi- 1 provide a circuit that can produce 5V at
low the 4871 to continuously deliver mated by the following equation:
R OUT = 2(R S + R DIODE + ESR + 1 / Cf )=
nearly 1A from each of its two outputs
1
4R TC T
2(0.6 + 0.15 + 0.11 + 0.07) = 1.9.
= 4 SEC +
,
while operating at its full rated ambient
R H1 + R H 2
f
temperature of 85C. Internal thermal
R
H2
0.5A from a 3.3V source at a conversion

shutdown protects the device from overf = 44 TO 53 kHz.
efficiency of 78%. If necessary, you can
loads, and a shutdown pin allows you to
You can calculate the output voltage obtain tighter regulation figures at slightpower down the device to less than 1 A.
Figure 2 shows the full circuit across COUT from the following equation: ly lower output current by adding a lowdropout linear regulator, such as the
schematic, including the equivalent in- VOUT = 2
ternal components. Amplifier IC1 is con(VINVDIODEIOUT R SIOUT (ESR)IOUT / Cf ) LP3961. At a 500-mA load it introduces
figured as an RC oscillator similar to a
a drop of only 150 mV. Its addition pro= 2(3.30.350.30.050.062) = 5.08 V ,
555 timer. RT charges CT to the voltage set
vides good line and load regulation over
by the resistor divider RH1 and RH2, caus- where IOUT is the average output current, the range IOUT0 to 500 mA (Figure 3).
ing the amplifier to switch states, aided by VDIODE is the diode voltage drop at IOUT, You can also use the circuits of figures 1
the positive feedback from the RH resis- RS is the source resistance of IC1 and IC2, and 3 to provide 3.3V at 500 mA from a
tors. The remaining internal feedback ESR is that of C1 and C2, and C is the val- 2.5V source.
and biasing resistors connected to IC2 ue of C1C2.
configure it as a simple inverter with bias
The following equation approximates
at mid-supply. The amplifier outputs the effective output resistance at the load: Is this the best Design Idea in this
switch rail-to-rail out of phase with a
Component values as shown in Figure issue? Select at www.edn.com.
D1
D3
D2
D4
VIN
3.3V
Figure 2
VOUT
Figure 3
3.3V
CIN
C1
RT
CT
A1
BP
CBP
COUT
A2OUT
A1OUT
40k
A1+ IC1
RH1
40k
C2
SD
IC2
+
100k
DOUBLER
CIRCUIT
VIN
VOUT
VOUT
5V, 5A
LP3961EMPX
1
SD
ERR GND
4
5
COUT
10 F
VIN
100k
RH2
This equivalent circuit shows the innards of the LM4871LD audio amplifier.
104 edn | September 5, 2002
You can tighten voltage-regulation specs in Figure 1s circuit by

adding a linear regulator.
www.edn.com
design
ideas
Add a signal-strength display to an FM-receiver IC

Jos Miguel-Lpez, RF Center Ltd, Barcelona, Spain
he Philips (www.semiconductors.
philips.com) TDA7000 integrates a
monaural FM-radio receiver from
the antenna connection to the audio output. External components include one
tunable LC circuit for the local oscillator,
a few capacitors, two resistors, and a potentiometer to control the variable-capacitance-diode tuning. The IC has an
FLL (frequency-locked-loop) structure.
The filtered output of the FM discriminator frequency-modulates the local oscillator to provide negative-feedback
modulation. The result is compression of
the signal at the output of the mixer.
Thus, the IF bandpass filter and the FM
discriminator deal with narrowband FM
signals. For a compression factor of K3,
the original FM bandwidth reduces to
R1
20k
5V
Figure 1
100 nF
10 nF
180 pF
4
15
220 pF
150 pF
R2
5k
R3
20k
9V
9V
IC2
3.3 nF
9
10
22 nF
1k
IC1
TDA7000
150
nF
11
2.2 nF
1/2
TL082
_
IC3
OK
1N4148
1k
13
LOW
14
20k
2.2 F
LEDs
IC4
TCA965
1
5V
GOOD
11
1/2
TL082
_
330 pF
10 nF
R4
220k
R5
4.7k
12
3.3 nF

18
8
7
5V
12 is dc-coupled to an amplifier, IC2.

Next, an envelope detector, IC3, yields a
dc voltage proportional to the receivedsignal strength. The Siemens (www.
siemens.com) TCA965 window discriminator, IC4, compares this envelope voltage with a voltage derived from R1, R2,
and R3 for the windows center (and R4
and R5 for the windows half-width).
Three LEDs show the result of the comparison (Low, OK, Good), but the display
is valid only if the tuning is correct. If its
correct, the voltage at IC1, Pin 1 reaches
its maximum value, and the LM311
comparator, IC5, enables the TCA965.
180/360 kHz. So, you need neither ceramic filters nor complex LC tank circuits to realize the IF filter. A simple active filter using op amps can fulfill the
task. The IC incorporates a correlation
muting system that suppresses interstation noise and spurious responses arising from detuning. The muting circuit
uses a second mixer. Its output is available at Pin 1; you can use it to drive a detuning indicator. You can add a signalstrength display to the TDA7000 using
the circuit in Figure 1.
You can obtain the information related to the intensity of the received signal
at the output of the IF filter (IC1, Pin 12).
You can easily process this voltage with
common op amps, because the IF signal
is centered on 70 kHz. The voltage at Pin
100k
4.7 nF
14
9V
330 pF
17
2
39 pF
13
16
+
1.8
nF
22k
12k
9V
TO AUDIO
AMPLIFIER
L1
IC5
LM311
_
10k
56 nH
BB809
10 nF
100k
10k
9V
IC6
7805
5V
10 F
10 nF
You can easily add a signal-strength indicator to the Philips TDA7000 FM-receiver IC.
www.edn.com
design
ideas
Op amp linearizes response of FET VCA

Mike Irwin, Shawville, PQ, Canada
ets find common use
VC
in VCAs (voltageFigure 1
O TO 5V
controlled ampliR6
15V
50k
fiers) and attenuators, in
R5
50k
which the FET serves as a vari5 +
C4
R1
able resistance. A control volt7
R7
10 nF
300k R
IC1B
2
age applied to the gate sets the
50k
FILM
6
1k
channel resistance and overall
R8
50k
circuit gain. You frequently
R3
2
2.2k
need to select individual FETs
VREF=50 mV
1
because of wide spreads in
IC1A
C2
VDS=50 mV
C3
+ 3
10 F
FET characteristics. The cir220 pF
NONPOLAR
ID
CERAMIC
cuit in Figure 1 uses a masterELECTROLYTIC
R4
slave servo technique with a
4.7k
R9
Q1A
D
D Q1B
matched-FET pair to impleR13
220k
470k
ment voltage-controlled vari2
G
G
C5
AUDIO OUT
IC
VGS
able gain. This gain is a linear
3 + 2 6
10 nF
6V P-P
IN6263
FILM
D1
function of the applied conS
S
SCHOTTKY
AUDIO IN
2N3958
trol voltage, VC. In contrast
6V P-P
DUAL FET
R
R
10
with variable-gain circuits us12
C1
R11
100k
470k
100 nF
150
ing a single FET as the gainFILM
control element, the circuit in
Figure 1 exhibits minimum
gain for VC0V and features a
linear increase in gain with in- This voltage-controlled amplifier has a dynamic range of 55 to 0 dB.
creasing VC. The self-biasing
in combination with R12, reduce distoroperation of the circuit also compensates
tion at higher signal levels. With the valfor unit-to-unit variations in the FET
ues shown, the gain increases linearly
characteristics, thereby making device sefrom 55 to 0 dB as VC varies from 0 to
lection less critical.
5V. The circuit accepts a 6V p-p input
The circuit maintains the drain voltsignal. Figure 2 shows the result of modage, VDS, of Q1A at a low value (VREF50
mV) to ensure that the FET operates in
ulating a 500-Hz sine wave with a 0 to 4V
the resistive region of its ID versus VDS
triangle wave.
characteristic curve. Op amp IC1A servos
For best performance, IC1 should be a
the VGS of Q1A to maintain VDS at VREF,
low-offset, low-input-current unit, such
while Q1A sinks the current from
as the OP-290. IC2 should be a high-gainA 0 to 4V triangle wave linearly
Figure 2
the Howland current source
bandwidth-product,
low-noise amplifier,
modulates the 500-Hz audio input.
IC1B. The sourced current is ID(mA)
such as the NE5534. You can successfulVC/R5(k), where VC is the control
ly use inexpensive units, such as the
voltage. The channel resistance, RD, in sets the gain: Gain1R9/RD1R9/ LF353 and LF351, at reduced gains. You
kilohms is then RDVREF/ID0.05/ID (VREFR5/VC).
can also operate the circuit from 5V
0.05R5/VC. The same VGS applies to Q1B
The maximum gain is 1R9/R0. R0 is supplies (with R1 changed to 100 k), usthrough R12. Because Q1 is a well- the minimum channel resistance for ing an OP-290 for IC1 and a TL031 for
matched monolithic dual FET, Q1A and VGS0V, approximately 450 for the IC2. The maximum supply current for
Q1B have identical channel resistance, RD. 2N3958. The minimum gain is unity, 5V operation is 0.33 mA, showing that
VGS varies from approximately 370 mV when the FET does not conduct (VGS low-power operation is possible.
(which D1 limits to prevent gate-source VPINCHOFF). The circuit attenuates the auconduction) to VP (approximately 1.7V dio-input signal level to lower than 10
for the 2N3958) as VC varies from 0 to 5V. mV p-p. This attenuation minimizes disIC2 is a variable-gain, noninverting am- tortion in the FET and also sets the clip- Is this the best Design Idea in this
plifier, in which the controlled RD of Q1B ping level at the output of IC2. R13 and C5, issue? Select at www.edn.com.
www.edn.com
design
ideas
Convert voltage to potentiometer-wiper setting

Chuck Wojslaw, Catalyst Semiconductor, Sunnyvale, CA, and
Chris Wojslaw, Conexant Systems, Newport Beach, CA
he circuit in Figure 1 con5V 6.8k
5V
verts an analog input
0.01 F
1%
Figure 1
,
to
a
provoltage, VIN
8
8
portional wiper setting of a DPP
100k
5
7
2 U/D
10k
(digitally programmable poten+
IC1
5V
3
0.1 F
IC5
VIN
3
LM33IA
tiometer). The potentiometers
1 CAT5114
0 TO 1V
+
IC4
INC
wiper setting, which varies from
1,6
7
VPULSES
CS
5
position 0 through 31, corre6
10k
4
2
sponds to the input voltage,
RS
100k
1 F
15k
which varies from 0 to 1V dc.
1%
1%
47
The CAT5114, IC5, is a 32-tap
5V
potentiometer with an increment/decrement interface. VIN
8
R1
280k
typically models the output volt10k
3
1%
VGATE
age of a sensor whose value sets
1%
7,6
IC2
IC3
a parameter of an analog circuit
LM555
2
5
in the signal-processing portion
C1
of a system. The basic principle
0.1 F
1
0.01 F
0.01 F
of the circuit is to convert the inCALIBRATE
VTRIG
(MIC)
put voltage to a number of pulses and let each pulse advance the
potentiometers wiper within a
certain period of time. IC1 is a You can convert an analog voltage to a wiper setting in a digitally programmable potentiometer.
voltage-to-frequency converter.
This circuit converts the 0 to 1V dc input sor-generated logic signal. The 31-msec up. When the DPP powers up, the IC revoltage to an output frequency, VPULSES, gating signal is chosen to correspond to calls wiper setting 00 from nonvolatile
that varies from 0 to 1 kHz.
the highest tap position of the poten- memory. When you depress the calibrate
This free-running oscillator advances tiometer at the highest frequency of the switch, the wiper increments from 00 to
the wiper of the potentiometer for only voltage-to-frequency converter. For a a setting corresponding to the input volt31 msec, established by VGATE and the 100-tap potentiometer, the gating signal age, VIN . You can use the three-terminal
AND function of IC4. VGATE is the output measures 99 msec for the same sensitivi- resistive network of the potentiometer to
of the one-shot multivibrator, IC2. The ty of the voltage-to-frequency converter. control the gain of an amplifier (shown
one-shot receives its trigger from a cali- You can trim the 15-k resistor, RS, to in broken lines in Figure 1), a parameter
brate switch or an external signal. The match the timing of the 331 converter to of a filter, or the coefficient of a mathehex inverters of IC3 debounce the cali- the pulse width of the 555.
matical operator.
brate switch. R1C1 differentiate the voltTap position 00 of the digitally conage-level shift generated by the switch to trolled potentiometer is stored in the
provide a nominal 100-sec trigger, DPPs nonvolatile memory and the po- Is this the best Design Idea in this
VTRIG, to IC2. VTRIG could also be a proces- tentiometers up/down control is set to issue? Select at www.edn.com.
Make a DAC with a microcontrollers PWM timer

Mike Mitchell, Texas Instruments Inc
any embedded-microcontroller
applications require generation of
analog signals. An integrated or
stand-alone DAC fills the role. However,
you can often use PWM signals for gen-
erating the required analog signals. You

can use PWM signals to create both dc
and ac analog signals. This Design Idea
shows how to use a PWM timer to simultaneously create a sinusoid, a ramp,
and a dc voltage. A PWM signal is a digital signal with fixed frequency but varying duty cycle. If the duty cycle of the
PWM signal varies with time and you filter the PWM signal, the output of the filwww.edn.com
design
ideas
ter is an analog signal (Figure 1). If you

the counter reaches the CCR0 value. This
MSP430
build a PWM DAC in this manner, its
scheme provides positive pulses equivaMICROCONTROLLER
resolution is equivalent to the resolution
lent to the value in CCRx on each reof the PWM signal you use to create the
spective output. If you use the timer in 8PWM
ANALOG
OUTPUT
FILTER
DAC. The PWM output signal requires
bit mode, the reset/set output mode is
a frequency that is equivalent to the upunavailable for the PWM outputs bedate rate of the DAC, because
cause the reset/set mode requires CCR0.
Figure 1
each change in PWM duty cycle
The timers clock rate is 2.048 MHz. Figis the equivalent of one DAC sample. The A PWM signal passing through a filter yields
ure 3 shows the sine and ramp wavefrequency the PWM timer requires de- and analog signal.
forms. The sine wave in this example uses
pends on the required PWM signal fre32 samples per cycle. The sample values
quency and the desired resolution. The giving the counter an effective 8-bit are in a table at the beginning of the prorequired frequency is FCLOCKFPWM2n, length.You can find this register and oth- gram. A pointer points to the next value
where FCLOCK is the required PWM-timer ers in a DAC demonstration program for in the sine table, so that, at the end of
frequency, FPWM is the PWM-signal fre- the MSP430 microcontroller. You can each PWM cycle, the new value of the
quency, and n is the desired DAC reso- download the program from the Web ver- sine wave is written to the capture/comlution in bits.
sion of this Design Idea at www.edn.com. pare register of the PWM timer.
Figure 2 depicts a circuit that delivers
CCR1 and output TB1 produce the
The ramp in this example does not rea 250-Hz sine wave, a 125-Hz ramp, and sine wave. CCR2 and TB2 generate the quire a table of data values. Rather, the
a dc signal. The desired sampling rate is ramp, and CCR3 and TB3 yield the dc ramp simply increments the duty cycle
8 kHz (32 samples for each sine-wave cy- value. For each output, the output mode for each cycle of the PWM signal until it
cle (16 oversampled), and 64 samples is the reset/set mode. In this mode, each reaches the maximum and then starts
for each ramp cycle (32 oversampled)). output resets when the counter reaches over at the minimum duty cycle. This
These figures result in a required PWM- the respective CCRx value and sets when gradual increase in PWM-signal duty cysignal frequency of 8 kHz and a
cle results in a ramp voltage
MSP430F149IPM VCC
required PWM clock frewhen the signal passes through
Figure 2
quency of 2.048 MHz. It is
a filter. You control the dc levDVCC
AVCC
R1
R2
usually best for the PWM signal
el by simply setting and not
2k
1M
frequency to be much higher than
changing the value of the
XIN P4.1/TB1
C1
C2
the desired bandwidth of the sigPWM-signal duty cycle. The dc
0.1 F
32,768 Hz
200 pF
nals to be produced. Generally, the
level is directly proportional to
XOUT/TCLK
2k
1M
higher the PWM frequency, the
the duty cycle of the PWM sigP4.2/TB2
lower the order of filter required
nal. Figure 2 shows the recon0.1 F
200 pF
DVSS
and the easier it is to build a suitstruction filters used for each
able filter. This design uses Timer
signal in this example. The fil330k
AVSS P4.3/TB3
B of the MSP430 in 16-bit mode
ter for the ac signals is a simDC
and in up mode, in which the
ple two-pole, stacked-RC filter,
0.05 F
counter counts up to the contents
which is simple and has no acof capture/compare register 0
tive components. This type of
(CCR0) and then restarts at zero. A microcontroller and some passive filters produce a sine wave, a
filter necessitates a higher samCCR0 is loaded with 255, thereby ramp, and a dc signal.
pling rate than would be re-
Figure 3
(a)
(b)
The microcontrollers PWM timer produces an ac signal (a) and a dc signal (b) of a sine wave and a ramp with 8-bit resolution.
www.edn.com
design
ideas
quired if the filter had a higher order.

starts the timer. Finally, the MSP430
RESET
With the type of filter shown in Figgoes into low-power mode
Figure 4
ure 2, you should use at least a 16
0 (LPM0) to conserve powDISABLE WATCHDOG
TIMER_B
oversampling rate.
er. The CPU wakes up to handle
TIMER, INITIALIZE I/O
CCIFGO
PORTS, AND SET UP
INCREMENT AN AND
The filter yields its best response
each CCIFG0 interrupt from the
INTERRUPT SINE-TABLE POINTER
CLOCK SYSTEM
AND MOVE NEW
when R2 R1. Also, setting the cutPWM timer and then re-enters
VALUE TO CCR1
off frequency too close to the bandLPM0. (See references 1, 2, and 3
CALL DELAY LOOP FOR
CRYSTAL STABILIZATION
width edge causes a fair amount of atfor more information on the DCO
tenuation. To reduce the amount of
and the MSP430 family.)
INCREMENT AN AND
CALL SOFTWARE
RAMP VALUE AND
attenuation in the filter, set the cutoff
FREQUENCY-LOCK LOOP
MOVE TO CCR2
FOR DCO STABILIZATION
References
frequency above the bandwidth edge
1. MSP430x13x/14x data sheet,
but much lower than the frequency of
SET UP TIMER_B AND
RETURN FROM
Texas
Instruments document SLASthe PWM signal. The filter for the dc
START PWM GENERATION
INTERRUPT
272.
value serves for charge storage rather
2. MSP430x1xx Family Users
than ac-signal filtering. Therefore, it
ENTER LPMO
Guide, Texas Instruments docuuses a simple, single-pole RC filter.
ment SLAU049.
Figure 4 shows the software flow for This software flow diagram shows how the PWM timer
3. Controlling the DCO of the
the DAC. After a reset, the routine generates the sine and ramp signals.
MSP430x11x, Texas Instruments
stops the watchdog timer, configures
the output ports, and sets up the clock
Next, the routine calls the calibration document SLAA074.
system. Next, the software calls a delay to routine to set the operating frequency to
allow the 32,768-Hz crystal to stabilize to 2.048 MHz. After the DCO calibration,
calibrate the DCO (digitally controlled the program sets up Timer_B, CCR1 and Is this the best Design Idea in this
oscillator).
CCR2 for PWM generation and then issue? Select at www.edn.com.
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design
ideas
Add current boost to a USB charger

Len Sherman, Maxim Integrated Products, Sunnyvale, CA
he popular USB interface can
charge a portable device while transferring data. But for high-capacity
470k
500 mA
4.5 TO 6.5V AC
batteries, the 500-mA output current of
100 mA
ADAPTER
USB hosts and powered hubs greatly ex(USB ONLY)
100k
(DOES NOT REQUIRE CURRENT LIMIT)
ON
OFF
tends the charging time. (Unpowered
USB hubs supply no more than
Figure 1
1N5817
100 mA.) Thus, a system that ac1N5817
1N4148
cepts charging power from an ac adapter
Q2
as well as the USB port is more conven2N3904
ient. Such a system can charge from a
IC1
MAX1811
notebook USB port when youre travelR1
SELV
CHG
20k
0.25
ing, yet can charge faster via the adapter
SELI
EN
R2
R
3
1 F
when youre at home or in the office. An
200
10
Q3
GND
FTZ789A
GND
external transistor current source adds
OR 2SB1427
USB
dual-input capability to a single-chip
(>200 AT 1A)
IN
POWER
BATT
+
lithium-cell charger (Figure 1). The chip,
Q1
4.7 F
LI+
4.7 F
FND304P
IC1, operates alone when you connect to
BATTERY
USB power and allows you to pin-program it for a maximum charging current
of either 500 or 100 mA. When you plug
in an ac adapter, which the 600-mA components set, the external-transistor cur- This battery charger delivers 100 or 500 mA (selectable) to a single lithium cell when USB power is
rent source, Q2 and Q3, turns on and sets connected and charges at 1100 mA (settable via R1 or R2) when ac power is present.
IC1s charging current to 500 mA. BeQ2 and Q3 form a current limiter for
cause IC1 and Q2 both charge the battery
IC1 also controls the prequalification
under that condition, the total charging the ac adapter. The limiter allows Q2 and current, which is the current level necesR1 to pass the additional 600 mA. When sary to safely recover deeply discharged
current is 1100 mA.
the voltage drop across R1 exceeds that cells at low battery voltage. The CHGoutacross R2, which R2 and R5 set, Q2 begins put assumes a high-impedance state durAdd current boost to a
to turn off. Q2 cancels VBE, enabling R1 to ing cell prequalification to ensure that the
USB charger..................................................103
more accurately set the maximum cur- external current source remains off, and
Transistor linearly digitizes airflow ..........104
rent. Voltage across R3 sets the reference that the prequalification current of apMake a truly linear RF-power detector ..106
voltage, and the output current limits proximately 50 mA comes only from IC1.
when the voltage drop on R1 matches the When you plug in the ac power, Q1 turns
Simple circuit provides 5V gate
voltage on R3. Q3 should have a beta high- off to prevent back-feeding the USB inbias from 48V..........................................108
er than 200 at 1A, so that IC1s CHG pin put. You install Q1 backward with the
Circuit provides laser-diode control ........110
can sink enough current to turn on Q3. drain connected to USB input side, so
High beta also minimizes error in the that USB power remains connected to the
One amplifier has two gain figures ........110
transistor current source. When IC1 IN pin (IC1 pin 4) via Q1s body diode,
Single switch controls digital
changes
from current mode to voltage even when Q1 is off.
potentiometer................................................112
mode at approximately 4.15V, IC1s CHG
Instrumentation amp makes noninverting
output turns off the transistor current
integrator........................................................114
source. IC1 remains on and finishes off
the taper to full charge. It also remains on
and continues to function when USB Is this the best Design Idea in this
power is gone and only ac power remains. issue? Select at www.edn.com.
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design
ideas
Transistor linearly digitizes airflow

sensitive and reliable way to
measure airflow is to take advantage
of the predictable relationship between heat dissipation and air speed. The
principle of thermal anemometry relies
on Kings Law, which dictates that the
power required to maintain a fixed differential between the surface of a heated
sensor and the ambient air temperature
increases as the square root of air speed.
The popular hot-wire anemometer exploits this principle, but it suffers from
the disadvantage of using a specialized
and fragile metallic filament, the hot
wire, as the airflow sensor. The circuit in
Figure 1 avoids this disadvantage by using a pair of robust and inexpensive transistors instead of a flimsy wire for airspeed sensing. The Q1/Q2 front end of the
circuit borrows from an earlier Design
Idea (Reference 1). Just as in the 1996 circuit, the circuit in Figure 1 works by con-
tinuously maintaining the condition

VQ1VQ2. To perform this task, the circuit
must keep Q1 approximately 50C hotter
than Q2.
VBE balance requires this temperature
difference, because Q1s collector current,
IQ1, is 100 times greater than that of Q2,
IQ2. If Q1 and Q2 were at the same temperature, this ratio would result in VQ1s
being greater than VQ2 by approximately
100 mV. Proper control of IQ1 establishes
differential heating that makes Q1 hotter
than Q2. The method thus exploits the
approximate 2-mV/C temperature coefficient of VBE to force VQ balance. The
resulting average, IQ1, proportional to the
average power dissipated in Q1, is the
heat-input measurement that forms the
basis for the thermal air-speed measurement. Calibration of the sensor begins
with adjustment of the R1 zero-adjust
trim. You adjust R1 such that, at zero air-
flow, VQ1VQ2 with no help from Q3.

Then, when moving air hits the transistors and increases the heat-loss rate, VQ1
increases and causes comparator IC1 to
release the reset on C1. C1 then charges
until IC2 turns on, generating a drive
pulse to Q1 through Q3.
The resulting squirt of collector current generates a pulse of heating in Q1,
driving the transistors temperature and
VBE back toward balance. Proper adjustment of R2 calibrates the magnitude of
the IQ1-induced heating pulses to establish an accurate correspondence between
pulse rate and air speed. Now, consider
measurement linearization. The squareroot relationship of Kings Law makes the
relationship between heat loss and air
speed nonlinear. You must iron the kinks
out of the air-speed-calibration curve.
You might achieve linearization in software, of course. However, depending on
5V
ZERO
10k
Figure 1
100 F
240k
R1
2k
Q3
2N3906
IQ1
Q7
2N3906
CALIBRATE
1k
5.1k
Q6
2N3904
2.2k
R2
12k
5k
2.2k
240k
300k
Q1
2N4401
2k
VQ1
3
2
AIRFLOW
5.1k
IC1
VQ2
5.1k
VC1
V3
5
IC2
LM393
4
C1
0.1 F
LM393
240k
1
F
82
W
ID
240k
Q2
2N4401
Q4
2N5087
Q5
2N5089
1M
5.1k
VC2
10k
1 F
Using a simple transistor as sensor, this circuit yields a digitized, linear measurement of air speed.
www.edn.com
design
ideas
the flexibility of the data system the

anemometer works with, a software correction is sometimes inconvenient. Another earlier Design Idea (Reference 2)
presented an analog solution to linearization. But if you want the advantages of a digital, pulse-mode output
that is, noise-free transmission over long
cable runsyou need a different fix.
The circuit in Figure 1 provides both
linearity and a digital output. The average heat the pulses deposit in Q1 is
H5VIFW, where I is the amplitude of the Q1 current pulses (adjusted
with R2), F is the output frequency, and

W is the pulse width. W is inversely proportional to ID, the discharge current that
ramps down VC1 and controls the ontime of IC2. Q4 and Q7 average the output
duty cycle to generate a control voltage
for Q5 and thus make W a function of F.
In fact, the feedback loop this arrangement establishes implicitly makes W
K/(WF), where K is a calibration constant determined by the component values. Therefore, W2K/F, and H5
IF/K/F. This expression yields
F(H/5I)2/K, making F the desired func-
tion of H2 and thus linearizing the relationship between frequency and air
speed.
References
1. Woodward, Steve,Self-heated transistor digitizes airflow, EDN, March 14,
1996, pg 86.
2. Woodward, Steve, Transistor and
FVCs make linear anemometer, EDN,
Sept 26, 1996, pg 72.
Make a truly linear RF-power detector

Victor Chang and Eamon Nash, Analog Devices, Wilmington, MA
3
odern high-performance trans- transmit QPSK (quadratureSQUARE WAVE

mitters require accurate monitor- phase-shift keying),
2.5
Figure 1
ing of RF power, because most cel- 16QAM (quadrature
3.01 dB (75.25 mV)
2
lular standards depend on strict power- amplitude modulation), and
transmission levels to maintain an effec- 64QAM, for example, and
OUTPUT
SINE WAVE
VOLTAGE 1.5
tive network. Regulation of transmitted- spread-spectrum systems such
(V)
signal strength also lets you build lower as CDMA and W-CDMA
1
cost systems. Figure 1 shows a waveform- (wide CDMA). A logarithmic
0.5
independent circuit that provides a lin- amplifier in an automaticear measurement of RF power. Sophisti- gain-control loop can regulate
0
80 70 60 50 40 30 20 10 0 10 20
cated modulation schemes, such as the gain of a variable-gain
INPUT POWER (dBm)
CDMA (code-division multiple access) power amplifier, but the outand TDMA (time-division multiple ac- put voltage is waveform-de- This circuit provides an output voltage that is linearly process) have obsoleted traditional ap- pendent, because the logarith- portional to the input power in watts.
proaches to RF power. Diodebased detectors have poor
mic amplifier does not re5V
temperature stability,
spond to the rms level of
Figure 2
C2
C3
and thermal detectors
the signal. For example,
0.01
F
100 pF
AD8361
1
6
have slow response times.
sine- and square-wave inVRMS
VPOS
2
Logarithmic amplifiers are
puts that have the same
5
C5
COMM
RFIN
VRFIN
1 nF
temperature-stable and have
rms voltage levels have difC
1
3
R1
4
FLTR
PWDN
100 pF
75
a high dynamic range, but
ferent logarithmic inter15V
they exhibit a waveform-decepts (Figure 2). You could
0.1
F
15V
pendent response. This reuse calibration factors to
1
+VS 8
X1
sponse causes the output to
correct this intercept dif2
7
2
+
X2
change with modulation type
ference in a multistandard
W 7
6
VOUT
AD707
5V
AD633
and, in the case of spreadsystem.
3 _
6
3
Y1
Z
4
R2
spectrum technology, chanAn alternative solution
0.1 F
R4
100
4 Y2
15V
nel loading.
(Figure 1) uses the
VS 5
100k
Power detection must be
AD8361, a high-frequency
R7
R6
R3
R5
1k
4k
waveform-independent in
true-power detector. Un15V
100
1k
systems that use multiple
like the logarithmic ampli5V
modulation schemes. These
fier, the AD8361 is an rmsinclude point-to-point sys- Log amps detect signals over a wide dynamic range, but are not rmsto-dc converter and,
tems that are configurable to responding.
therefore, responds to the
www.edn.com
design
ideas
input rms voltage. Hence, a sine

[G(R5R6R7)/R5]. This
100
4
wave, a square wave, or any othvalue is lower than the gain of
er input with the same rms level
10 that you would need to exVOUT:100 MHz
ERROR:100 MHz
produces the same dc output, alactly cancel the effect of the
10
2
lowing you to incorporate wavemultiplier scaling and allows
form-independent measurement
the circuit to have a wider dyVOUT (V) 1
0 ERROR (dB)
into a multimodulation system.
namic range, because the outWith the addition of a
put would saturate with a
VOUT:900 MHz
Figure 3
multiplier, the circuit
smaller input with a gain of
0
2
delivers an output voltage that is
10.You can easily adjust all cirERROR:900 MHz
proportional to the input power
cuit offsets with potentiome0
4
level in watts. You can easily adter R2. Figure 3 shows meas0.01
0.1
1
10
urements made with this
just gain and offset for this powPIN (mW)
power meter. The graphs plot
er meter with an op-amp circuit,
thus providing an output scaled The circuit in Figure 1 responds to rms signals, independent of wave- the output voltage and error
for input signals at frequencies
in volts per watt. A complex RF form.
of 100 and 900 MHz. The dewaveform feeds the input of the
AD8361.
pedance of the circuit. The AD633 mul- tector operates at frequencies as high as
The multiplier squares the dc output tiplier squares the rms output of the 2.7 GHz.
to produce a voltage proportional to the AD8361 and divides by 10. The AD707 Is this the best Design Idea in this
power dissipated in the 50 input im- provides a maximum gain of 6 issue? Select at www.edn.com.
Simple circuit provides 5V gate bias from 48V

Will Hadden, Maxim Integrated Products, Sunnyvale, CA
small and simple
VOUT
circuit derives 5V
5V, 2 mA
1
IN
MAXIMUM
+ MAX6138
from the 48V rail
C+ OUT
EXR50-T
that telecomm applicaC2
IC1
C3
MAX1683
3.3 F
tions typically
4.7 F
IC2
C1
2
C
0.1 F
use (Figure 1).
Figure 1
GND
Useful for gate
R
VIN
bias and other purposes,
8.2k
48V
the 5V supply delivers as
much as 5-mA output
current. A shunt refer- This small, simple circuit produces 5V at 5 mA from a 48V input.
ence, IC1, defines 5V as
ground reference for a charge pump, IC2. shunt reference.
The charge pump doubles this 5V differThe shunt reference sinks as much as
ence between system ground and charge- 15 mA and requires 60 A minimum to
pump ground to produce 5V with respect maintain regulation. Maximum IR is a
to the system ground. The shunt refer- function of the maximum input voltage.
ence maintains 5V across its terminals by To prevent excessive current in the shunt
regulating its own current, IS. IS is a func- reference with no load on the chargetion of the value of R. The current pump output, use the maximum input
through R, IR, is reasonably constant and voltage (48V10%52.8V) to calvaries only with the input voltage. IR, the culate the minimum value of R. The
sum of the charge-pump and shunt-ref- maximum reference sink current, 15 mA,
erence currents (IRICPIS), has maxi- plus the charge pumps no-load operatmum and minimum values set by the ing current, 230 A, equals the maxi-
mum IR value, 15.23 mA. Thus, RMIN

(VIN(MAX)VREF)/IR(MAX)3.14 k.
Choose the next-highest standard 1%
value, which is 3.16 k. You calculate the
guaranteed output current for the charge
pump at the minimum line voltage:
48V10%43.2V. The charge
pumps maximum input current is
ICP(VIN(MIN)VREF)/RISH(MIN)(43.2
5)/3.1690 A12 mA, where 90 A
is the minimum recommended operating current for the shunt reference. Assuming 90% efficiency in the charge
pump, the output current is IOUT
(ICP/2)0.9(12/2)0.95.4 mA. You
halve the charge-pump current, because
the output voltage is twice the input voltage. Be sure that R can handle the wattage
under no-load conditions. A 1W resistor
suffices in this example.

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design
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Circuit provides laser-diode control

aser diodes are sensitive to ESD,
rapid turn-on currents, and overvoltage conditions. To address those
problems, the simple laser-diode controller in Figure 1 has several functions.
The first part of the circuit comprises an
8.2V zener diode, D1 that forms the heart
of a constant-voltage source for the laser
diode. Next, IC1A, half of a dual FET-input op amp, forms an inverting integrator to slow the turn-on time. To turn on
the laser diode, IC1B, the other half of the
op-amp IC, triggers the base of Q2. This

transistor forms a constant-current
source for the laser diode. You can monitor the laser-diode supply voltage and
the sense-diode current and voltage. You
use these parameters as inputs to the differential amplifier, IC2A, the first half of
another dual FET-input op amp. When
an overvoltage condition occurs, the difference amplifier detects the condition,
and its output drives IC2B, configured as
an open-loop comparator. You set the
threshold by using the potentiometer, R1.

Zener diode D2 provides a constant-voltage source for that threshold setting.
When the voltage reaches the threshold,
the output triggers the base of Q1, which
instantly shuts down IC1B, which in turn
shuts down the laser diode.

12V
0.1 F
150
0.5W
1k
1k
D1
8.2V
CONSTANT-VOLTAGE SOURCE
10k
5 +
8
IC2B
LT1057
6 _
4
12V
SENSE
DIODE
LASER
DIODE
1k
1N914
1k
12V
3 +
IC2A
LT1057
2 _
4
87.5
1W
0.001 F
10k
1k
12V
12V
SPST
2 _
1M
8
IC1A
LT1057
3
+
4
SLOW TURN-ON
330
6 _
IC1B
LT1057
5
+
4
Q1
2N2222
499
Figure 1
REFERENCE SETPOINT
LASER-DIODE
PACKAGE
8
7
1k
Q2
2N2222
12V
330
56k
R1
100k
CONSTANT-CURRENT
SOURCE
10k
D2
8.2V
CONSTANT-VOLTAGE
SOURCE
SHUTDOWN CIRCUIT
Constant voltage and current and slow turn-on time are the keys to laser diodes survival.
One amplifier has two gain figures

he single-supply circuit in Figure
1 is an inverting amplifier with two
outputsone for positive output
voltages, VOUT(POS), and the other for negative output voltages, VOUT(NEG). Steering
diodes D1 and D2 split the amplifier, IC1,
output into the two output polarities relative to the 2.5V reference. The gain of
the inverting amplifier for each of the two
polarities features independent programming, using Catalysts (www.cat

semi.com) 100-tap, digitally programmable potentiometers DPP1 and DPP2.
You configure the potentiometers as variable resistances and model them as
(1p)RPOT, where p represents the proportional position of the wiper as it
moves from one end (p0) of the DPP
to the other end (p1). RPOT is the potentiometers end-to-end resistance. In

terms of p, the gains of the circuit are
If R1RPOT, the gain values can be less
(1p1)R POT1
VOUT(POS) =
VIN
R1
FOR 0 < VIN < 2.5V , and
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design
ideas
(1p2 )R POT 2
VOUT(NEG) =
VIN
R1
p1RPOT1
3
than one, one, or greater than one. For

the circuit values shown, you can
Figure 1
program the two gains from ap1
proximately /10 to 10. If you characterize
the potentiometer, the measured accuracy of the circuit is approximately 1%.
This implementation of the circuit uses
SERIAL
only six components and is appropriate
BUS
for signal-processing applications.

R1
1k
1%
FOR 2.5V < VIN < 5V.
VOUT(POS)
6
5V
D1
2
1
IC1
3 +
11
VIN
D2
2.5V
5V
5V
DPP1
CAT5113
4
DPP2
CAT5113
4
p2RPOT2
VOUT(NEG)
3
5
NOTES:
IC1= 1/ 4 LM6064.
RPOT1=RPOT2=10 k.
Using digitally programmable potentiometers, you can obtain two distinct gain figures from one
amplifier.
Single switch controls digital potentiometer

Jim Bach, Delphi Delco Electronics Systems, Kokomo, IN
his Design Idea is an evolution and
DPDT
MOMENTARY
simplification of another (Figure 1,
CONTACT
Reference 1). Replacing the three in100k
5V
verted-input NOR gates with their
Figure 1
logical equivalents, positive-input
NAND gates, makes these three gate
IC1A
symbols consistent with the fourth,
S1A
which was drawn as a positive-input
OFF
IC1B
NAND gate. The 74HC132s data sheet
describes the device as a quad, two-input
100k
5V
MOMENTARY
NAND gate with hysteresis.
10k
100k
S1B
As the earlier design also describes, you
5V
can activate the DPDT rocker switch, S1,
IC1C
to produce either a count-up or a
10k
100k
countdown effect at the digital poten5V
tiometer, CAT5114. Moving the switch
C
1 F
1 F
4.7 F
up causes S1A to ground the input of IC1A,
thus causing the NAND-gate flip-flop,
IC1A and IC1B, to switch high, thereby This is the original circuit, as published in Reference 1.
commanding the CAT5114 to count up.
At the same time, S1B causes the 1-F caTABLE 1SUMMARY OF SAVINGS
pacitor on IC1Cs upper input to discharge
Component
Figure 1 count
Figure 4 count
through a 10-k resistor. Eventually the
ICs
Two
Two
output of IC1C also switches high, thus
Resistors
Seven
Four
enabling the oscillator comprising IC1D.
, 100 k
)
)
Resistor values
Two (10 k
One (100 k
Similarly, moving the switch down causCapacitors
Three
Two
es S1B to ground the input of IC1B, thus
Capacitor values Two (1 F, 4.7 F)
Two (0.1 F, 4.7 F)
Switches
One DPDT
One SPDT
causing the NAND-gate flip-flop to
5V
U/D
INC
CS
CAT5114
74HC132
IC1D
R
100k
Savings
Zero
Three
One
One
One lower value and cheaper
Single-pole and cheaper
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design
ideas
DPDT
MOMENTARY
CONTACT
100k
Figure 3
5V
S1B
S1A
10k
1 F
OFF
10k
S1B
IC1C
You can simplify the oscillator-enable structure,

as shown.
10k
that the A and B sections are not crossconnected between operating the flipFigure 2
flop and the oscillator-enabling circuit.
You can rewire the interface structure as
You can restructure the switch-interface circuit
shown in Figure 2. This circuit uses S1A to
of Figure 1 as shown.
control the flip-flop, whereas S1B controls
the oscillator-enable
5V
SPDT
circuit. This step
100k
MOMENTARY
does nothing direct5V
CONTACT
IC1A
U/D
ly to reduce the parts
count of the circuit;
INC
S1
however, it does
CS
IC1B
OFF
make the subsequent step more ob100k
5V
74HC132
vious. The next step
IC1C
CAT5114
IC1D
100k
in the simplification
Figure 4
is to recognize that
0.1 F
R
the two RC net100k
works on the inputs
C
4.7 F
of IC1C both do the
same thing but in
This circuit uses fewer and cheaper components than the circuit in
opposite switch poFigure 1.
sitions. As far as IC1C
is concerned, either
switch low, thereby commanding the switch position performs the same funcCAT5114 to count down. At the same tion; that is, to debounce the switch contime, S1A causes the 1-F capacitor on tacts and eventually enable the oscillator.
IC1Cs lower input to discharge through Thus, you need only one RC network,
a 10-k resistor, thereby eventually en- and you can tie it to both of S1Bs active
positions (Figure 3). Moving the switch
abling the oscillator comprising IC1D.
The first step in simplifying this design in either direction discharges the 1-F
is to rearrange the connections of S1 so capacitor through the 10-k resistor,
1 F
eventually causing the output of IC1C to

switch high, thus enabling the oscillator.
When you release the switch, S1B goes to
the open, or off, state, and the 1-F capacitor recharges through the 100-k resistor, thus turning off the oscillator.
The last simplification step stems from
realizing that the sole purpose of IC1C and
the RC filter on its input is to generate a
high state whenever switch S1 is in either
of its active positions. True, the RC filter
does debounce the switch contacts; however, the actual switch- closure information available at S1B is also available at S1A.
Thus, you can simply use IC1C to directly monitor the S1A contacts.You can move
the RC filtering to the input of IC1D. This
step allows you to simplify S1, changing it
from a DPDT to a SPDT configuration,
which means you can use a cheaper
switch. Because the RC debounce filter
now connects to a low-impedance gate
output, IC1C, you can increase the R, thus
reducing the amount of C you need to
form the same time constant. Thus, you
can use smaller, cheaper capacitors. You
can also use the same resistor value, 100
k, in all four locations, eliminating the
need to inventory two resistor values. The
final circuit appears in Figure 4. Table 1
summarizes the savings in component
count and cost.
Reference
1. Wojslaw, Chuck,Single switch controls digital potentiometer, EDN, Feb 7,
2002, pg 100.
Instrumentation amp makes noninverting integrator

Glen Brisebois, Linear Technology Corp, Milpitas, CA
igure 1a shows the classic implementation of an integrator. The circuit has two properties that may be
undesirable in same applications: It necessarily inverts, and it requires a split-
supply or midsupply reference. Figure 1b

shows an implementation of an integrator that uses an LT1789 instrumentation
amplifier. This integrator does not invert,
and it works with a single supply. In ad-
dition, because it has a positive-only output swing, the integrator capacitor can be
a high-value, polarized electrolytic unit,
as shown. Most of the circuit operates as
a voltage-controlled current source. The
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design
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VS
LT1789 is a precision micropower

VS
t=0
3
instrumentation amplifier
7
VIN
+
R
1
Figure 1
8
10k
6
that can operate from 3 to
3
LT1789
7
+
1
C
REF
6
36V total-supply spans.
LT1636
2
IOUT
2
With a gain setting of 1, with
4
4
+
pins 1 and 8 open, the voltage beVS
+
C1
R2
tween the inputs also appears beR
100 F
10
VIN
tween the Output and Reference
pins. The Output pin connects to
+
t=0
one side of R1, and the voltage on
VS
the other side of R1 drives the Ref(a)
(b)
erence. The input voltage, VIN, appears across R1, causing the current-source action, with IOUT The classic integrator in a inverts and requires split supplies. The circuit in b is noninverting and works
VIN/R1. Dumping this current into with a single supply.
a capacitor produces the integrator action, with the time constant R1C1. range and micropower operation make adjustable ramp generators, and voltageThe LT1636 buffers the output voltage on the circuit suitable for battery-powered to-frequency converters.
C1, thereby eliminating the loading ef- systems. As a positive-output-only intefects of approximately 200 k of the grator, this circuit is not generally appliLT1789s Reference pin and any down- cable inside control loops. Suitable ap- Is this the best Design Idea in this
include
accumulators, issue? Select at www.edn.com.
stream circuitry. The wide, single-supply plications
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Passive circuit limits inrush current

Sunil Tiwari and Mangesh Borage, Centre for Advanced Technology, Indore, India
ou would normally limit the inrush current during start-up of a
rectifier circuit with a capacitor output filter by using the circuit in Figure 1.
You insert a high resistance in series with
the ac input or the dc output of the rectifier and then short-circuit the resistance
with a switch once the filter capacitor is
sufficiently charged. In this scheme, you
need an additional timer relay or sensing
circuit to control the closure or opening

of the switch. Moreover, the switch carries the full load current during normal
operation. As an alternative, the simple,
passive circuit in Figure 2 for inrush-current limiting uses commercially available
components and presents advantages in
size and cost. The resistance-switch
arrangement inserted in series with the
filter capacitor, instead of in the main
Figure 1
In this classic inrush-limiting circuit, the switch carries the full load current during normal operation.
Passive circuit limits inrush current............93
Transmitter senses triple
relative-humidity figures ..............................94
Latching light detector is frugal
with power and parts....................................96
High-speed peak detector uses
ECL comparator ............................................98
Simple FIFO provides data-width
conversion ....................................................100
Measure open-circuited cables
using a multimeter ......................................102
Circuit measures true-rms
and average value ......................................104
Electronic-potentiometer system
has pushbutton interface ..........................106
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power line, limits inrush current in this

circuit. The current rating of the switch
can therefore be much lower. A switch, S1,
short-circuits the charging resistor, R1.
This switch represents the contact of a
commercially available dc relay. The relay senses the voltage on capacitor C;
thus, the switch operates automatically.
R1 limits the peak inrush current and
also determines the start-up delay. The
Figure 2
In this inrush-limiting circuit, the current rating of the switch is considerably reduced.
Figure 3
The circuit in Figure 2 limits the inrush current to a

safe value of approximately 6A.
design
ideas
relays changeover contact either shortcircuits R1 when the capacitor is sufficiently charged or connects R2 across the
capacitor to speed its discharge in the off
condition. For jitter-free operation of the
relay, you need suitable hysteresis between closure and opening. Too little hysteresis results in malfunction of the circuit in the presence of momentary dips.
Too much hysteresis leaves the circuit
unprotected against heavy inrush currents upon reclosure of the relay. You can
incorporate suitable hysteresis by adding
zener diode DZ and resistor R3 in series
with the relay coil. The following equations describe the operation of the circuit
in Figure 2:
Dc pickup voltage:
(R C + R 3 )
+ VZ ;
RC
Dc dropout voltage:
VDCP = VCP
VD = IZ (R C + R 3 ) + VZ ;
and hysteresis:
VDCPVD = VCP
(R C + R 3 )
IZ (R C + R 3 ),
RC
where VCP is the relay-coil pickup voltage,

RC is the relay-coil resistance, VZ is the
zener-diode breakdown voltage, and IZ is
the zener-diode knee current.
Commercial-grade components have
variations in their parameters. These
variations can affect the dc pickup and

dropout voltages. For minimum sensitivity to variations in VCP, RC, and IZ, you
should make R3 as low as possible. Tolerances in VZ and R3 have an insignificant
effect on the circuit; however, IZ is temperature-dependent, and its effect on
dropout voltage is significant. Figure 3
shows the experimental results. The prototype uses the following component values: C2000 F (nonpolar), R136,
R24.7 k, R312 k, VZ110V, IZ3
mA, VCP65V, and RC10 k.
Transmitter senses triple relative-humidity figures

Shyam Tiwari, Sensors Technology Ltd, Gwalior, India
he circuit in Figure 1 is a triple, relative-humidity sensor and raFigure 1
dio transmitter. Sensors 1 and
2 form two gated oscillators with natural frequencies of 10 and 5 kHz, respectively, at relative humidity of 50%. The
gated oscillators use variable resistances
R2 and R3, respectively. Together, these
two oscillators generate FSK-modulated
outputs at output of IC1B, Pin 6. The oscillator for Sensor 3 causes switching of
the FSK signal at IC2B. IC2Bs natural frequency is 1 kHz at relative humidity of
50%. As the HS1101s capacitance
changes from 160 to 200 pF (180 pF at
relative humidity of 50%), the oscillator
frequencies change by approximately
20% for relative humidity of 0 to Using FSK modulation, you can generate three independent relative-humidity measurements with
100%). You can tune the RF generator, one circuit.
IC1A, to the desired frequency of 27 to100
MHz for FM transmission. The following
Sensor 2 signal is the bottom FSK generate the frequency from any other
represents various ways to monitor the
frequency, 5 kHz, on the carrier type of sensor. This frequency then besignals at the receiver end (not included
wave. It measures 5 Khz20% for comes available at the receiver without afin the design):
relative humidity of 0 to 100%.
fecting the relative-humidity signals from
Sensor 3 signal is the FSK-modulat The difference between the top and sensors 1 and 2. You can even use a TTLed signal at the receiver: 1 kHz20%
the bottom FSK modulating fre- based ASCII output to replace the Sensor
for relative humidity of 0 to 100%.
quencies provides the difference in 3 circuit to pass the ASCII data along with
Sensor 1 signal is the top FSK frethe relative-humidity signals.
relative-humidity signals.
quency, 10 kHz, on the carrier wave.
You can replace the Sensor 3 circuit
It measures 10 kHz20% for relative with any TTL oscillator circuit with a Is this the best Design Idea in this
humidity of 0 to 100%.
range of 100 Hz to 1 kHz. You can then issue? Select at www.edn.com.
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Latching light detector is frugal

with power and parts
Anthony Smith, Scitech, Biddenham, Bedfordshire, UK
his idea demonstrates three uses
for the humble LED. The circuit in
Figure 1a forms a simple light detector that latches and turns on an LED
when the ambient light exceeds a preset
limit determined by potentiometer P1.
LED D1 is both the indicator and the light
detector. All junction diodes exhibit some
degree of photosensitivity. Light-emitting diodes are photovoltaic in that they
generate a small voltage in response to

light with suitable spectral content. Provided that they have light loads, some
LEDs can generate more than 1V in adequate light conditions. The Q2-Q3 differential pair acts as a comparator. At low
light levels, the photovoltage that D1 generates is lower than Q3s base voltage, VB3,
and Q1 and Q2 are both off. When the
light falling on D1 exceeds the threshold
that P1 sets, Q2 begins to conduct, thereby biasing the second LED, D2, which acts
as a voltage reference (the third function
of an LED). Q1 now turns on, sourcing
current to D1, which illuminates.
Regenerative action around Q1 and Q2
ensures that the circuit makes a rapid
transition into the latched state. The circuit stays latched, and D1 remains illuminated even if the light level falls below
Figure 1
This circuit uses LEDs as both light-detecting and -indicating devices (a). A modification replaces the voltage-reference LED, D2, by a resistor (b).
Figure 2
This circuit avoids trip-point changes as a function of supply voltage (a). A modification works from slightly higher supply voltages (b).
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the trip point. You can reset the circuit by

short-circuiting D1. Because Q1 is off in
the unlatched state, D1s only load is R2
and Q2s base current. Provided that Q2
has adequate beta and R3 is fairly large,
the loading is negligible. You can use R2
and C1 to reduce D1s sensitivity and provide a degree of filtering. You may need
such filtering in noisy environments,
such as monitoring the light from fluorescent tubes. With adequate forward
current, most green LEDs drop approximately 1.7V, so, in the latched state, approximately 1V appears across R1. A value of approximately 330 sources 3 mA
into D1, providing adequate brightness.
For obvious reasons, you should not expose the voltage-reference LED, D2, to
light. If necessary, you can omit D2 by
modifying the circuit (Figure 1b). For
battery-powered applications, the values
of R4, R5, and P1 should be fairly large to
ensure minimal current drain in the unlatched condition. If you need a broad
threshold range, you should select the
values to provide a range of VB3 from approximately 0.6 to 1.4V.
You need to experiment to find the optimum LED to act as photodetector. Tests
on more than 50 LED color samples produced a range of unloaded output voltage varying from a low of 135 mV to
more than 1V in overcast sunshine. A
green LED with a clear lens produces almost 1.5V on a dull afternoon. The circuit can work from supply voltages as
low as 3.3V, guaranteeing operation from
three cells. In the off state, current drain
is minimal. The circuit in Figure 1a consumed just 88 A in the unlatched state.
Although simple and effective, the circuit
suffers the disadvantage that its trip
point varies with changes in supply voltage. Also, the trip points lower limit cannot be less than the 600 mV or so to bias
Q1 and Q2. The circuit in Figure 2a remedies these problems. The circuit uses
IC1s internal bandgap reference to generate a stable threshold. Because the
MAX921 (www.maxim-ic.com) comparators input-voltage range includes
the negative rail, you can set the trip
point at 0 to 1.18V (the value of the internal reference), thus allowing D1 to
work over a wider range of light levels.

Power requirements are minuscule.
The circuit operates from supplies as low
as 2.5V (the MAX921s minimum supply
voltage), and, in the off state, the only
current drain comes from P1 and IC1s
quiescent supply current. The prototypes
total off-state current was just 7.8 A.
You can use the comparators rail-to-rail
output voltage at VOUT as a digital signal
and feed it to other systems to indicate
light conditions. The comparator output
can source more than 10 mA with little
reduction in high-level voltage, thus allowing you to slightly simplify the circuit
(Figure 2b). However, in this version, you
must accommodate the voltage drop
across D2, so the minimum supply voltage becomes approximately 3V. Alternative devices you can consider for IC1 include the Linear Technology (www.
linear-tech.com) LTC1440 and the Telcom (www.telcom-semi.com) TC1031.

High-speed peak detector uses ECL comparator

Przemyslaw Krehlik and Lukasz Sliwczynski, Institute of Electronics, Krakow, Poland
rofessional electronics designers often use peak-detector circuit
sin such applications as amplitude
measurement, automatic gain control,
and data regeneration. You can
Figure 1
build a simple and fast peak detector from a serial diode and a shunt capacitor, but it suffers from serious inaccuracy that stems from the diodes
forward-voltage drop. On the other hand,
precise detectors based on op amps are
rather slow. They are therefore not wellsuited for measuring pulses of a few
nanoseconds duration. The circuit in
Figure 1 offers both good accuracy and
good dynamic performance. The main This circuit uses an ultrafast ECL-output comparator to measure the peak value of input signals.
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design
ideas
part of the detector is the ultrafast

MAX9690 (www.maxim-ic.com), ECLoutput comparator. Because
Figure 2
the circuit does not internally
pull down the output emitter follower,
you can use the circuit as a rectifier that
charges capacitor C1. The circuit amplifies and level-shifts the voltage from the
capacitor and feeds it back to the negative input of the comparator. When the
signal appears at the peak detectors input, capacitor C1 charges until the feedback voltage at the comparators negative
input becomes equal to the peak value of
the signal under measurement; thus, the
peak detection occurs. The second op The circuit in Figure 1 yields a dc value equal to the positive peak of the input signal.
amp forms an output buffer.
In this design, the measured peak volt- repetition frequency of approximately 1 tor. In this case, you should use the inage should be 0 to 2.5V. The detectors ac- MHz. To deal with pulses having a lower verting output of the comparator and
curacy depends on the pulse duration repetition rate, you should increase the also reconfigure the amplifier/shifter for
and duty cycle. For example, 1V rectan- values of C1 and C2 . That increase would, inverting operation. Figure 2 shows an
gular pulses having 3-nsec duration and however, result in longer settling time. example of the circuits operation. The
5% duty cycle produce 5%-low readings. Another important element is the dis- circuit correctly measures the peak valSimilar inaccuracy occurs for 10-nsec charging resistor, R1. A value of 100 k ue of the applied input signal, although
pulses having 0.1% duty cycle. The ac- for R1 is appropriate for operation with the input pulses are quite short and have
curacy is much better for longer pulse low-duty-cycle pulses, but you may need nearly triangular tips.
durations, greater duty cycles, or both. lower values for fast tracking with varyThe circuit measures pulses lasting for ing input-signal amplitudes. You can also Is this the best Design Idea in this
some tens of nanoseconds and having configure a minimum-value peak detec- issue? Select at www.edn.com.
Simple FIFO provides data-width conversion

David Lou, Ghent University, Ghent, Belgium
any designs require FIFO elastic write data ports. You can implement this an on-chip DLL (delay-locked-loop)
buffers to form a bridge between FIFO using a Xilinx (www.xilinx.com) macro, distributed memories, and simple
subsystems with different clock Spartan II Series FPGA. The method uses counter logic (Figure 2).
rates and access requirements. However,
in some applications, you need FIFO
buffers for data conversion. One
Figure 1
example is the case in which you
need to connect an 8-bit ADC to a 16-bit
data-bus microprocessor through a FIFO
buffer (Figure 1). Unfortunately, most
currently available FIFO buffers are unsuitable for this application. This Design
Idea describes how to implement a common clock (synchronous version) for an
FPGA-based FIFO for data-width con- This block diagram is an example of a system using a FIFO between an ADC and a microprocessor
version with different-width read and chip.
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design
ideas
The width of the input data of the

FIFO is 8 bits; however, the width of the
output data is 16 bits. You use only one
common clock for both read and write
actions. The trick is to use a clocked
DLL, which not only minimizes clock
skews, but also offers a double-frequency output clock. So, you can implement
a double data rate for the input data,
write_data_in. By monitoring a sample
of the DLL output clock, the
Figure
DLL can compensate for the
delay on the routing network, efficiently eliminating the delay from the external input port to the individual clock
loads within the device. Instead of using
block memory, this design employs distributed memory to hold the data in
FIFO. In fact, choosing block memory or
distributed memory depends on how important this FIFO is in your system. If it
ify the VHDL code. You can just use

some RAM macros to replace distributed memories. You can download the
VHDL code for the FIFO from the
www.ednmag.com. FIFOs commonly
use Gray-code counters or linearfeedback shift registers as read or write
counters. To minimize the logic size,
this design uses only two integers
ranging from 0 to 7 together with a
2
carry for the counters. When the read
and write counters are equal and the
carry is zero, the FIFO is empty. When
This FPGA uses an on-chip DLL, distributed memothe write counter plus one is equal to
ry, and simple counter logic.
the read counter and the carry is one,
is not critical, you may want to consider the FIFO is full.
using distributed memory.
You can put the memory anywhere
you like within the FPGA. If you insist on Is this the best Design Idea in this
using block memory, you can easily mod- issue? Select at www.edn.com.
Measure open-circuited cables using a multimeter

Ron Duffy, Agilent Technology, Colorado Springs, CO
ou can use a multimeter with capacitance-measurement capability
to measure the length of wire or cable to an open circuit. The capacitance of
a pair of wires (or a wire to a shield) is directly proportional to the length of the
wire. If you know the capacitance per foot
of wire, then you can calculate how far it
is to the open circuit. To determine the
capacitance per foot, take a trip to the
hardware store, use a known length of
wire, and measure the capacitance with
the multimeter. You must zero the multimeters capacitance function before
making any measurements. To zero the
meter, select the capacitance function
and separate the leads. Then, make the
measurement and simply divide the total
capacitance of the wire or cable by the total length to determine the capacitance
per foot. Once you have this figure, and
youre sure that the suspect wire or cable
carries no power or signals, you can
measure the capacitance, C. The wire
length in feet to the open circuit is C di-
TABLE 1CAPACITANCE CHARACTERISTICS OF COMMON WIRES AND CABLES

Total
capacitance
Type
(nF)
Twisted pair, 18 gauge
41
16-3 SJ
0.1
Category 3 phone, PVC
21.6
Category 3 phone, plenum 22.1
14-2 NMB
5.26
16-gauge speaker
0.98
18-gauge speaker
0.91
24-gauge speaker
1.69
20-gauge twin lead
0.68
RG-6
0.47
RG-8
RG-25
RG-59
Total
length
(ft)
1100
5
1000
1000
250
30
30
75
100
25
vided by the capacitance per foot.

The resolution depends on the range
and resolution of the multimeter. The
lowest range of a multimeter is usually 10
nF. The resolution in that range is 10 pF.
The multimeter steps up by a factor of 10
each time it changes range. The higher
ranges allow you to measure longer wires,
but, as Table 1 shows, the resolution de-
Capacitance
per ft
(pF)
37.3
20
21.6
22.1
21
32.7
30.3
22.5
6.8
18.8
29.5
50
21
Resolution
(in.)
32.2
6
55.56
54.3
5.7
3.67
3.96
5.33
17.65
6.38
4.07
2.4
5.71
Range
(ft)
2682.9
500
4629.6
4524.9
475.3
306.1
329.7
443.8
1470.6
531.9
339
200
476.2
creases by a factor of 10 for each higher

range. (Note the measurements on wires
longer than 1000 ft.) All but the last three
entries in Table 1 measure the lengths of
wire or cable and then calculate. The last
three entries are from a coaxial-cable
chart.
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design
ideas
Circuit measures true-rms and average value

Charles Kitchin and Lew Counts, Analog Devices, Wilmington, MA
he circuit in Figure 1 measures
both the true-rms value and the rectified average value of an ac signal.
This design uses two low-cost ICs in
SOIC packages and consumes only 180
A of quiescent current. Operating from
a single 5V supply, the circuit has an input dynamic range of less than 30 mV to
greater than 3V rms. Sine-wave
Figure 1
accuracy is good (Table 1), and
bandwidth is approximately 100 kHz, depending on input level. The circuit can
also measure a 1V rms, crest-factor-offive pulse train with lower than 1%-ofreading error. Most ac measurements use
rectified-average-value circuits. Although
these can be accurate if you calibrate their
scale factor to read the rms value of one
waveform, such as a sine wave, they exhibit large errors if you use them for other waveform types. In contrast, the rms
value of an ac signal is the amount of dc
required to produce an equivalent
amount of heat in the same load. Therefore, the rms value is independent of You can measure both true-rms and average-rectified values with this circuit.
waveform shape or duty cycle; its often
past the switch, keeping the capacitor
useful for measuring the power of a comTABLE 11-kHZ SINE-WAVE
charged and preventing any large surge
plex ac waveform.
ACCURACY
currents from flowing into or out of CAV
Average-responding and rms measwhen the switch is closed. The AD737JR
urements have traditionally used differVIN
VOUT rms
VOUT
(rectified average value)
drives the AD8541AR op amp with a
ent circuits. However, in some cases it
3
2.9999
2.6762
negative-flowing output current. The op
may be useful to know both the rms and
1
1.0027
0.8947
amp operates as a current-to-voltage
the rectified average value of an ac wave0.3
0.30201
0.2698
converter and also inverts the signal, proform. The ratio of rms to rectified aver0.1
0.10082
0.09947
viding an output voltage that swings
age value is one way to determine the
0.03
0.0296
0.02956
more positive with increasing input levcharacteristics of a waveform without acNote: VIN is in ac volts rms as monitored by
els. Resistor R5s value of 80.6 k matchtually seeing it on an oscilloscope. For exKeithley 191 in ac mode. Supply=5V dc.
es the effective input resistance of the
ample, the rms/average-value ratio is
0.707V/0.636V or 1.11 for a 1V peak normally 200 mV. You can greatly in- AD737 (R1R28 k), so that
undistorted sine wave, 1.0 for a symmet- crease this range by adding an external re- input/output scaling is 1-to-1. Resistor R3
rical square wave, 1.155 for a triangular sistancein this case, resistor R1 and and trimming potentiometer R4 cause a
wave, and 1.253 for Gaussian noise. An trimming potentiometer R2between current to flow from the supply to the op
AD737 rms-converter IC drives an the signal input and Pin 1. This addition amps summing junction. This action offAD8541AR micropower op amp (Figure has the added advantage of increasing the sets the op amps output, such that the
circuits output is approximately 0V with
1). Resistors R7 and R8 form a voltage di- circuits input impedance.
vider to allow operation from a single
The AD737JR measures the true-rms no voltage applied. Note that this circuit
supply voltage or battery. Capacitors C4 value when switch S1 connects its aver- has a maximum supply-voltage limit of
and C5 bypass any signal currents on VCC aging capacitor, CAV, to Pin 5. The aver- 5.5V; you can extend operation to 12V by
or VCC/2 to ground. The rms-converter aging capacitor performs the mean por- substituting an OP-196GS op amp for the
IC has two inputs: a high-impedance tion of the rms function. Removing CAV AD8541AR. Circuit calibration is easy:
(1012) input (at Pin 2) and an 8-k, by opening S1 converts the circuit to recAdjust trimming potentiometer R4 to
wide-dynamic-range input via Pin 1. The tified-average-value operation. Resistor mid-scale and set S1 for rms.
1. Apply a 2.000V rms, 1-kHz sinerms converters full-scale input range is R6 allows a small leakage current to flow
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design
ideas
wave input signal.

2. Adjust R2 until the circuits output
voltage is 2.000V dc.
3. Reduce the input to 100 mV rms
and adjust offset trimming potentiometer R4 for a reading of 100 mV
dc.
4. Repeat Step 2.
Because the dc-offset circuitry is ratiometric, it remains calibrated with modest
variations in supply voltage. The measured power-supply-rejection ratio of this
circuit over a 4.5 to 5.5V supply range is

approximately 61 dB. The measured errors versus crest factor for a 5V supply
and a 1V rms, 100-sec pulse are: crest
factor3, error0.67%; crest factor5,
error0.98%; and crest factor10, error4.7%. Some additional points to
consider: The peak rms value of a sine
wave is 0.707V peak, and the peak rectified-average value is 0.636V. This ratio of
0.707V-to-0.636V is equivalent to an 11%
scale-factor difference between the two
measurement methods. If you want this

circuit to accurately read the rms value
for sine waves in the rectified-averagevalue mode, S1 can be a two-pole switch.
The second pole can connect a 523-k,
1% resistor in parallel with R1 to increase
the scale factor in the average-value
mode. However, the true rectified-average value is more useful in most cases.
Electronic-potentiometer system
has pushbutton interface
Gene Warzecha and Roger Griswold, Maxim Integrated Products, Sunnyvale, CA
s systems grow smaller, it becomes increasingly attractive
Figure 1
to replace mechanical potentiometers with electronic potentiometers,
which are smaller and less expensive silicon equivalents. A common interface for
such devices comprises a Chip-Select, Increment and, Up/Down line. CS activates
the device and, on a rising edge of INC
steps the wiper in a direction that the These three ICs form a solid-state potentiometer.
U/D pin indicates. The simple circuit of
Figure 1 uses two pushbuttonsone for
up and one for downand a few tiny silicon devices to implement a debounced,
ESD-protected electronic-potenFigure 2
tiometer system. The normally
open pushbutton switches feed
into the MAX6817, an ESD-protected
switch debouncer in an SOT-23 package.
It has internal pullup resistors on the inputs and buffered, noninverting CMOS
outputs. In the absence of a switch clo- Closing either pushbutton in Figure 1 increments the potentiometers output in a direction that the
sure, the normally open switches hold the MAX5161s U/D input indicates.
MAX6817 outputs high. In turn, that
condition ensures a low state for the ac- 5161 is a 32-tap, linear-taper electronic isfies the setup requirement. The delay, tf,
tive-low, push-pull output of the potentiometer in an SOT-23 package is typically 10 to 30 sec (Figure 2). INC
MAX6308, an SC70 reset device with two with the standard INC-U/D interface. goes high again only after the reset timereset inputs that are independent of the (The electronic potentiometer pulls the out interval expires. For the MAX6308,
CS input high internally.) Its setup re- that interval (tRESET) is factory-preset with
VCC pin.
The reset device must have extra reset quirement is 50 nsec, meaning that the a value as short as 1 msec.
inputs rather than a manual-reset input, U/D signal must be stable for 50 nsec prebecause the glitch-immunity protection ceding a rising edge at the INC pin. The
of manual-reset inputs is not adequate to transient-filtering circuitry internal to Is this the best Design Idea in this
guarantee proper operation. The MAX- the MAX6308 introduces a delay that sat- issue? Select at www.edn.com.
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RF oscillator uses current-feedback op amp

Victor Koren, Tioga Technologies Ltd, Tel Aviv, Israel
V(ROSC)VINVVRES/2. The voltage at the
resonator tap is VRES/2, because the resonator capacitors are equal in value.
V(ROSC)VRESVRES/20.5V p-p. I(ROSC)
V(ROSC)/ROSC. I(RF)I(ROSC). The negative feedback nulls the amplifiers inverting-input current. VOUTV(RF)
VINVRFI(RF)VINV1000(0.5/33
0)12.51V p-p. If you need more voltage, you can add RGin this case,
100from the inverting input to
ground. I(RG)VINV/RG. Now, the current through RF is the sum of the currents
through ROSC and RG. So, VOUTV(RF)
VINVRFI(RF)VINV1000(0.5/33
01/100)112.51V p-p. Figure 4
shows the measured output voltage.
The LM6181s maximum output current is 100 mA, so it can easily drive a current of 63 mA p-p (6.3V/100) into
a total load of 100 (50 output-termination resistor and 50 load resistor).
The voltage across the 50 load is 3.15V
peak, or 2.23V rms, which is close to 20
dBm (100 mW). This power level can directly drive high-level diode double-balanced mixers, or it can drive a higher
power amplifier while delivering a clean
sinusoidal waveform. You can modify the
resonator circuit to accommodate differ-
current-feedback amplifier is a
well-known component
Figure 1
with many uses. Its basic
+
block diagram shows that its input stage
VP
is a voltage followerin practice, a sym1
VOUT
+
metrical emitter follower (Figure 1). The
IEZT
configuration samples the output cur
rent, converts it to voltage across a large
VN
IE
impedance, and amplifies it to the output
using a high-power, low-output-impedance amplifier. The idea is to use the amplifiers input stage as a voltage follower In a typical current feedback amplifier, the
in a basic Colpitts oscillator. This circuit input stage is a voltage follower.
uses the noninverting input of the current-feedback amplifier as the follower resistor ROSC to improve the linearity and
input and the inverting input of the am- define the feedback magnitude. The valplifier as the follower output. You use the ue of ROSC, 330, lets you obtain soft
output amplifier to obtain a relatively clipping operation of the diodes across
high-power buffered output. The circuit the resonator (VRES1V p-p, which is
in Figure 2 shows a basic Colpitts oscil- 0.5V peak across each diode). Figure 3
lator that uses the amplifiers input-volt- shows VRES, the measured voltage at the
age follower as the active element of the top of the resonator. RF is the amplifiers
feedback resistor; the amplifiers manuoscillator.
Take note of two aspects of this oscil- facturer recommends its value. This delator circuit: First, back-to-back diodes sign uses the LM6181 from National
connect across the resonator to limit the Semiconductor (www.national.com),
oscillations to a specific level, thus main- and the value of RF is 1 k.
It is easy to calculate the output volttaining the linearity of the voltage follower. Second, the voltage follower outage: VRES1V p-p, and VINVVRES1V pput connects to the resonator tap through p. The voltage-buffer gain is unity:
BAV99
12V
RF oscillator uses
current-feedback op amp ............................83
Simple tester checks LCDs............................84
Circuit drives mixed types
and quantities of LEDs..................................86
MOSFET serves as ultrafast
plate driver ......................................................88
Parallel port provides highresolution temperature sensing..................90
+
0.8 H
1 nF
1 nF
Figure 2
LM6181
100 nF
VRES
VINV
ROSC
330
100 nF
100 nF
VOUT
RTERM
50
RLOAD
50
12V
RF
1k
RG
100
This Colpitts oscillator uses a current-feedback amplifier to provide a clean sinusoidal output.
www.edn.com
October 3, 2002 | edn 83
design
ideas
ent tuning elements. You can use the circuit as a crystal oscillator by changing the
inductor to a crystal and changing the
resonator capacitors to an appropriate
Figure 3
value, such as 268 pF. You need a highvalue, such as 10-k, bias resistor from
the noninverting input to ground to provide bias current to this input.
This clean sinusoid is the signal at the top of the resonator, VRES, in Figure 1.
Figure 4

The Colpitts oscillator in Figure 2 produces a pure

sinusoidal output.
Simple tester checks LCDs

D Prabakaran, NL Polytechnic College, Tamil Nadu, India
anufacturers of electronic
4.5V
12
13
equipment use LCDs for calculaIC1F
R2
tors, watches, mini-videogames,
14
47k
4
3 IC
PROBE 1
and pagers, for example. In com1B
Figure 1
parison with LED-based displays,
11
10
IC1E
which consume power on the order of
C1
R1
tens of milliwatts, an LCD consumes only
10 F
220k
a few microwatts. The LCD thus saves
25V
9
8
IC1D
2
1
power by a factor of approximately 1000.
IC1A
R3
C2
47k
7
Checking an LED is as simple as checkPROBE 2
0.47 F
ing a semiconductor diode but, in the
5
6
IC1C
case of LCDs, involves some added complexity. An LCD requires an ac electric
field to excite the organic compound in
the display. Applying a dc voltage could This simple circuit tests LCDs by producing a biphase square wave with no dc component.
permanently damage the LCD. The circuit in Figure 1 is a simple configuration probes through 47-k series resistors, ment under test is operational, it will
to test the performance of an LCD. The which protect the IC in the event of short light up. If the LCD under test is a mulcircuit produces biphase square waves circuits. With the component values tiplexed type, then all segments, which
with negligible dc content. The circuit is shown in Figure 1, oscillator IC1A pro- are connected, will glow if they are operbased on a CD40106 hex Schmitt-trigger vides a square-wave frequency of ap- ational. Usually, the rightmost or leftmost
inverter. The circuit comprises an oscil- proximately 45 Hz. The circuit can oper- connection is the backplane of the LCD.
lator, IC1A; a phase splitter, IC1B; and a pair ate from 3 to 5V. To test any segment of If it is not, you have to find it by trial and
of buffer/drivers comprising IC1C/IC1D an LCD, touch the backplane using either error.
and IC1E/IC1F.
of the two test probes while touching the Is this the best Design Idea in this
The buffers and drivers connect to test segment with the other probe. If the seg- issue? Select at www.edn.com.
84 edn | October 3, 2002
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Circuit drives mixed types and quantities of LEDs

Mark Pearson, Maxim Integrated Products, Sunnyvale, CA
LED
LED
LED
LED
D1
L1
VCC
ortable systems often use
STRING
STRING
STRING
STRING
MBR0540T1
10 H
2.7 TO 5.5V
1
2
3
4
LEDs of different colors and
STANDARDSTANDARDQ5
in varying quantities of each
COLOR
COLOR
FDN337N
C2
LEDs
LEDs
C1
color. Some examples are white for
1 F
MAX1698
10 F
IC1
EXT
the display backlight, green for
VCC
D6 TO D8
NSPW500BS
REF
CS
keypad illumination, and red for
D
TO
D
3
5
D2
PGND
R1
ADJ
NSPW500BS
power. Typically, the LEDs derive
24V ZENER
500k
AGND
CMPZ5253B
MPQ3904
GND
MPQ3904
power from at least two power
MPQ3904
Q3
FB
Q2
SHDN
Q4
supplies: one for standard LEDs
MPQ3904
Q
1
(red and green) and one for white
LEDs. (White LEDs exhibit
Figure 1
a higher forward voltage.)
R2
The keypad and other indicator
LEDs have current-limiting resistors associated with them. To In this LED-driver circuit, a switching converter, IC1, and associated components lets you mix LED quantities
eliminate these resistors and drive and types.
groups of dissimilar LEDs from
LED
LED
LED
D1
L1
VCC
STRING
STRING
STRING
MBR0540T1
the same source, you can regulate the cur10 H
2.7 TO 5.5V
1
2
3
rent through multiple strings. Four
Q5
strings of varying LED types derive powFDN337N
C2
C1
1 F
er from a single power source (Figure 1).
MAX1698
10 F
IC1
EXT
VCC
The circuit mixes LEDs of different forREF
CS
ward-bias requirements, yet keeps the
D6 TO D8
D3 TO D5
D9 TO D11
D2
PGND
R1
ADJ
NSPW500BS NSPW500BS NSPW500BS
24V ZENER
500k
loads reasonably well-balanced through
AGND
CMPZ5253B
BALLAST
GND
R5
R6
use of a current mirror comprising tranRESISTORS
FB
SHDN
C
4
V
CC
sistors Q1 through Q4. It also eliminates
1 nF
the need for a separate current-limiting
R2 CURRENT-SENSE
MAX4040
ballast resistor on each LED or
RESISTOR
Figure 2
string of LEDs and provides a
R4
R3
common control point (IC1s ADJ pin)
65.8k
1M
for adjusting the LED intensities.
Transistors Q2 through Q4 mirror the
C3
1 nF
current in the diode-connected transistor, Q1. Note that the Q1 current-set string Modifying Figure 1 as shown reduces the overall power dissipation in a standard application.
(LEDs D3 through D5) should have an
equal or larger voltage than that of sub- Any power difference between the refer- proves efficiency by reducing the resistor
sequent LED strings. (If it doesnt, the ence string and a mirrored string dissi- values and their associated loss. Increascurrent-mirrored strings may have too pates in the current-mirror transistor for ing the gain of the current-sense signal by
little voltage overhead to function prop- that string: PMAX (transistor) approximately 16 allows an equivalent reerly.) You can easily meet that require- (VOUT300mVVLEDs)ILEDMAX. The duction in the value of R2 and the ballast
ment in the first string by placing either current-sense resistor value is R2300 resistors. A typical value for R2 is 15,
LEDs with larger forward voltage drops, mV/ILEDMAX, where ILEDMAX is the sum of which represents a loss of 18 mW: (20
such as the approximate 2.8 to 3.7V range currents from all the strings. (For a com- mA)215 for each of three resistors. If
of white LEDs, or more similar LEDs. prehensive circuit and parts list, refer to R2R5R60.931, then the resistor
Then, the circuit can easily accommodate Maxims MAX1698 (www.maxim-ic. power loss drops to 1.12 mW. The op
amp draws only 20 A maximum, which
the subsequent strings with lower voltage com) EvKit data sheet.)
When driving the same LEDs without represents a dissipation of 100 W.
burdens. The matched-transistor current
mirrors maintain a constant and equal the current mirror, you can reduce powcurrent in all LEDs, regardless of quan- er dissipation in the sense resistor and
tity and type. That configuration allows ballast resistors by substituting a mithe use of a single power supply and a sin- cropower op amp across the current- Is this the best Design Idea in this
gle point for adjusting LED brightness. sense resistor (Figure 2). That circuit im- issue? Select at www.edn.com.
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MOSFET serves as ultrafast plate driver

he circuit in Figure 1 provides a
20-MHz square wave across a set of
highly capacitive ion-deflection
plates in an experimental instrument. To
get the required deflection, the plate voltage must be 20 to 30V, much higher voltage than conventional logic or driver
families can provide. To minimize artifacts, the rise and fall times must be very
fast, with a minimum of overshoot and
ringing. Identical circuits, phased 180
apart, drive the plates. The driver uses a
Directed Energy (www.directedenergy.
com) DEIC420 high-speed MOSFET
gate driver to drive a 1000-pF capacitive
load from 0 to 25V in less than 5 nsec.
With smaller loads of a few hundred picofarads, the rise time decreases to approximately 3 nsec. Series resistors R1 and
R2 control the output rise and fall times,
allowing you to trade off the rise and fall
times against overshoot and ringing.
A high-speed Analog Devices (www.
analog.com) ADUM1100BR ferromagnetic signal isolator prevents system

ground loops by providing dielectric isolation for the input signal; you could also
use high-speed optocouplers. A low-power MC78L05CD regulator provides power for the signal-isolator output stage.
A snubber network, composed of a
thin-film, high-power resistor R3 in a TO220 package and high-quality NP0 capacitors C1 and C2, terminates the load
at the plates. You empirically determine
snubber values by observing the radiated field on an RF spectrum analyzer using a passive RF probe. You tune the
snubber network to reduce higher order
signal harmonics. Note that placing an
oscilloscope probe on the outputs significantly increases the observed higher order harmonics, indicating that adding the
probe to the circuit increases ringing and
overshoot. The DEIC420 is mounted in a
high-speed, high-power package that
minimizes lead inductance. The part requires multiple bypass capacitors at each
of its power pins. You should choose the
capacitors so that their self-resonant frequencies do not significantly overlap.
Having a full ground plane and using
high-speed and RF-signal-layout techniques are critical to the proper operation
of this circuit. The input must be wellisolated from the output. Double-pulsing, ringing, and even oscillation may occur if you dont strictly follow these
practices. The tracks or cabling between
the driver and the load should be impedance-controlled and should be as
short as possible. The DEIC420 requires
good heat-sinking when you operate it at
high speeds and high voltages. When operating at 20 MHz from a 25V supply, the
two drivers and snubber together dissipate 130W.
12 TO 25V POWER SUPPLY

1
2
0.22 F
2 50V
G1
G1
1
IC2
VI
V0
MC78LO5ACD
0.1 F
GND GND GND GND

2
3
6
7
5V ISOLATED SUPPLY
1
0.1 F
2 50V
0.1 F
G1
G1
1
2
DRIVE SIGNAL
G1
1
2
AXIAL WIDEBAND CHOKE, 2.5 TURNS

WB2-2.5T
G1
1
1
0.22 F
10 F
2 50V
2 35V
G1
G1
1
0.01 F
2 50V
G1
0.1 F
1
3
2
4
KEEP TRACK LENGTHS DOWN
IC1
ADUM1100BR
VDD1
VDD2
VDD1
OUT
IN
GND2
GND2
GND1
8
6
7
5
2
IC3
DEIC420
1 3
5
4 6
R1
1
1, 1W, 5%
2
ISOLATION BOUNDARY
DEFLECTION
PLATES
G1
IDENTICAL CIRCUIT FOR SECOND PLATE

DRIVEN 180 OUT OF PHASE
2 R
3
82
35W
1
CONTROL RISE TIME
G1
INVERTED DRIVE SIGNAL
1
0.22 F
2 50V
G1
R2
1
C1
22 pF
C2
22 pF
SNUBBER
NETWORK
1, 1W, 5%
2
Figure 1
KEEP TRACK LENGTHS DOWN
You can use a high-speed, MOSFET-driver IC to drive ion-deflection plates.
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design
ideas
Parallel port provides

high-resolution temperature sensing
Martin Connors and Mike Foote, Athabasca University, AB, Canada
igh-resolution temperature sensing at low cost is possible using only
one chip attached to the PCs
Figure 1
parallel port (Figure 1). The Dallas Semiconductor (www.dalsemi.com)
DS1722 digital thermometer allows
measurement resolution as fine as
5V
0.0625C in digital form and with linear
response. The accuracy specification is
only 2C, but you can improve this figure
by careful calibration. Moreover, the acDS1722
1 VDDD 1 VDDA 8
curacy spec is unimportant in applica2 CE SERMODE 7
tions in which you measure only changes
SDI 6
3 SCK
in temperature or in which you must
4 GND
SDO 5
closely maintain a noncritical temperature. The measurement range is 55 to
120C, the part can use either three-
25
PAPER
The DS1722 connects to a PCs parallel port

through a male DB-25 connector, seen from the
pin side.
NACK
D7
D0
1
wire or SPI interface, and the cost is approximately $1. The eight-pin part is
available in SO or SOP packaging and
in large quantities as a flip-chip measuring only about 1 mm sq.
In this application, the chip attaches
directly to the PCs parallel port through
a male DB-25 connector. Because the device draws a maximum of 0.5 mA, the
port can supply the power, and its supply range tolerates variations in voltage
levels that may exist on varying ports.
The chip is in SPI mode with the SCK
LISTING 1TURBO C FOR DATA-TRANSFER CYCLE
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design
ideas
clock signal supplied by the PC; in this

way, data-transfer timing is noncritical.
A simple Turbo C program (Listing 1)
running in DOS mode effects the datatransfer cycle in the PC, whereas the
transfer is automatic in the chip upon reception of SCK. The routine reads a low
byte and a signed high byte and creates a
floating-point value by simply adding the
low byte, divided by 256, to the high byte.
In the highest resolution mode, which
this design uses, a data read can occur
only every 1.2 sec, and you should adjust
the timing loops accordingly. You may
also need to adjust the settling time,
DELTIME, depending on the speed of
the PC you use. The sample program
prints the bytes transferred as well as the
temperature, and you can easily modify
it. The data sheet explains the use of the
configuration register and changes to
make if you need a higher data rate with
lower resolution.You can download Listing 1 from the Web version of this Design
Idea at www.ednmag.com.
The data transfer takes place beginning
with the write of an address byte to the
chips SDI in the order A7 to A0 (high bit
to low bit). If A7 is high, a write takes
place; otherwise, a read occurs. For a
write, D7 to D0 route to the chips SDI.
For a read, D7 to D0 are available on the
chips SDO. The program always uses
both SDI and SDO and ignores whichever it doesnt need. For example, data goes
to the chips SDI even during a read, but
the chip ignores this data. Each byte
transfers as 8 bits, and each transfer involves the following steps:
1. The PC raises D1/SCK and places 0
or 1 on D2 for the chips SDI.
2. The PC then reads PAPER.
3. Finally, the PC drops D1/SCK.
This action repeats for each bit of the
pair of bytes being transferred (one in,

one out). By using the other parallel
ports output pins as chip selects, you
could string together several devices. You
can also use these pins to control a heater
by use of a switching transistor or an
SCR. With this scheme, you can achieve
high-resolution temperature control
with minimal parts and a simple program. Alternatively, if you need only low
accuracy, you can implement a very-lowcost thermostat with this part.

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ideas
Extend the input range of a low-dropout regulator

Jeff Falin, Texas Instruments, Dallas, TX
ecause of process limita2.9V4.4V. Thus, when the
IRF7601
tions, all ICs have an
MOSFET provides 100 mA, its
VIN
15V
TPS79228
VOUT
Figure 1
2.8V, 100-mA
input-voltage limitasource voltage does not drop beLINEAR REGULATOR
tion. This limitation can be cumlow 2.9V. The maximum gateR1
200k
bersome when you try to step
bias voltage is simply the maxidown a high supply voltage to a
mum recommended operating
R2
lower, regulated voltage using a
voltage for the regulator, or 5.5V.
100k
dc/dc converter, such as a linear
This voltage provides more than
regulator. Adding a FET to the inenough gate drive to provide the
put of a linear regulator creates a You can use a MOSFET switch to expand a low-dropout regularegulators 1 A of quiescent
dc/dc converter with a wider input- tors input-voltage range.
current during shutdown mode.
voltage range than the range of the
Although you can bias the gate
regulator alone. The excess voltage
between 4.4 and 5.5V, this design
and, therefore, power occurs in the
uses a bias voltage of 5V to acVARIABLE-SUPPLY
VOLTAGE
FET.
count for variations in the
Figure 1 shows an IRF7601 nthreshold voltage. Maximum
R1
channel MOSFET on the inpower dissipation for the FET is
Figure 2
TPS79228
VIN
VOUT
put of a TPS79228 2.8V,
100 mA(15V2.9V)1.21W.
2.8V, 100-mA
100-mA, low-noise, high-powerThe IRF7601, in a Micro 8 packLINEAR REGULATOR
supply rejection ratio low-dropout
age, can handle this power figure
regulator. R1 and R2 provide a bias
at an ambient temperature of
voltage to the gate of the MOSFET,
55C.
and the load current determines the A zener diode provides fixed gate drive to the MOSFET when
The circuit in Figure 2 is
voltage at the source of the MOS- the input voltage varies significantly.
slightly more complicated but
FET. (In other words, the FETs onmay be necessary if the input
resistance adjusts to accommodate the load current.) In this example, the max- voltage varies significantly. A zener diode
imum power-supply voltage is 15V, but replaces the R2 in Figure 1 and provides
the TPS79228 has a maximum recom- a fixed gate drive to the MOSFET. You seExtend the input range
mended operating input voltage of 5.5V, lect the output voltage of the zener diode
of a low-dropout regulator ..........................95
so this design uses a MOSFET with a 20V in a manner similar to that explained
above. Either of the two methods is acbreakdown voltage.
Convert your DMM to a pH meter ............96
To determine the minimum bias volt- ceptable for creating a dc/dc converter
AVR microcontroller makes
age for the gate of the MOSFET, you need with a wider input-voltage range than the
improved motor controller ..........................98
the MOSFETs drain-current, ID,-versus- converter IC allows. The single-MOSFET
Precision circuit closely
gate-source voltage, VGS, data-sheet solution is the simplest and least expenmonitors 48V bus ..................................100
curves. For the IRF7601, the curves indi- sive solution. The MOSFET biased with
cate that the device needs VGS slightly be- a zener diode is the best choice when the
PLD code reveals
low 1.5V for 100-mA output current. Be- supply is unregulated.
pc-board revisions ......................................102
cause the maximum dropout voltage of
Simple method tests cables ......................106
the regulator is 100 mV at 100 mA, the
regulators input voltage must stay above
2.9V. Therefore, you must bias the gate of Is this the best Design Idea in this
the MOSFET to at least 1.5V issue? Select at www.edn.com.
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October 17, 2002 | edn 95
design
ideas
Convert your DMM to a pH meter

Bill Donofrio, Nu-Products, Cordova, TN
ts often necessary to know the
9V
acidity of a solution to control a
0.1 F
process. Even inexpensive pH
Figure 1
meters can be relatively costly,
and many of the inexpensive models have
7
2
pH PROBE
no output that you can readily connect to
6
INPUT
LM351
3
a computer interface. A simple solution
5
OUTPUT
+
4
1
to this problem is to attach a pH probe
10k
to a high-impedance input of an op amp
0.1 F
OFFSET
and read the output with a digital voltmeter (Figure 1). Then, convert these
9V
readings to pH units using a calculator
that can calculate the slope of a line. To This simple pH tester uses a digital voltmeter
calibrate the system, you can use pH stan- and a calculator to determine the slope of a
dards. Generally, you would use three line.
standards: 4-, 7-, and 10-pH units. These
standards are inexpensive and available
volts) for each standard.
at any chemical-supply house. The cali3. Enter the values in your calculator
bration procedure is as follows:
and determine the slope of the line.
1. Short the input leads together and
Figure 2 shows a typical plot of pH
adjust the offset potentiometer such versus millivolt output. (Note that pH is
that the output reads 0 mV.
temperature-dependent; you have to re2. Place the pH probe in each standard calibrate if the temperature changes.)
and record the output (in milliIf you want to measure directly in pH
800
Figure 2
600
100C
400
25C
200
VOUT (mV)
200
10
12
14
16
400
600
800
pH
Available pH probes produce a linear slope of output voltage versus pH.
1k
Figure 3
9V
0.1 F
pH PROBE
INPUT
200
15 TURN
7
2
6
LM351
3
5
+
4
1
10k
0.1 F
1k
200
15 TURN
SLOPE
8
2
3 +
100k
1
1
/ 2LM353
OFFSET
100k
100k
6
5 +
7
1
/ 2LM353
OUTPUT
9V
9V
With this circuit, you can directly measure pH units.
Y INTERCEPT
9V 9V
units, you can use the circuit in Figure 3.

At approximately 24C, the equation for
the slope of the line is Y0.017X7.
To obtain readings in tenths of volts, you
multiply the equation by 10. The new
equation is 10Y0.17X70. The circuit in Figure 3 comprises three sections.
The voltage using the LM351 provides
the high-impedance input. The inverting
amplifier using one-half of the LM353
controls the slope. It multiplies the
LM351s output by 0.17. The other half
of the LM353 functions as a summing
amplifier and controls the Y intercept by
adding 70 mV to the input signal. When
you build this circuit, solder the BNC directly to the op amps input pin. This connection prevents slightly conductive pc
boards from affecting the impedance levels of the probe. Another point to remember is to remove the pH probe from
the unit when power is off.
To calibrate the circuit, first short the
inputs together and adjust the offset potentiometer to obtain 0-mV output from
the LM351. To calibrate the circuit for pH
units, place the pH probe into a pH standard. Measure the voltage at the output
of the LM351. Multiply this voltage by
0.17 and adjust the slope potentiometer
until the output of the second op amp
reads this inverted (negative) value.
Then, connect the meter to the output of
the circuit and adjust the Y-intercept potentiometer until the circuit yields the pH
of the standard you use. (For example, a
pH of 10.1 reads 0.101V.) To tweak the
circuit, place the pH probe in other standards and adjust the Y-intercept potentiometer. Note again, if the temperature
changes, you must recalibrate. The accuracy of this circuit is generally 0.1 pH
units. When you order pH probes, you
should order low-impedance units. This
circuit uses Cole-Parmer (www.cole
palmer.com) U-59001-65 probes.

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design
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AVR microcontroller makes

improved motor controller
Anthony Di Tommaso, Cranberry Township, PA, and George Simonoff, Petersburg, OH
he circuit in Figure 1 provides a
novel method of reading the pulse
train using an Atmel (www.atmel.
com) AVR processor, from a typical ra-
dio-controlled receiver, and to determine

the velocity of a motor. To capture the
pulse train from a typical receiver, you
need an external interrupt that triggers
based on a rising and a falling edge. Three

timers are also necessary: one 16-bit, freerunning timer to determine the period of
the input pulse and two 8-bit timers con-
LISTING 1MOTOR-CONTROL C LISTING
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design
ideas
VDD
figured as PWMs (pulse-width modulaVDD
VDD
tors) for driving the motor in both forPB:7
ward and reverse. Finally, two digital outPB:2
puts act in concert with the PWMs to
Q1
move the motor. You can find all these
IC1A
features in an AVR microcontroller. AsIC3A
suming that you use a typical transmitQ2
ter and receiver, such as a pair from Futaba (www.futaba.com), the range of pulse
width, tPH, should vary from 1 to 2 msec
for full reverse and full forward,
M
Figure 1
VDD
respectively. If the Timer 1 clocksource frequency is 500 kHz, the number
VDD
PB:4
of counts possible between full reverse
and full forward is 500, beginning at 500
PB:5
for a pulse width of 1 msec and ending
IC2A
at 1000 for a pulse width of 2 msec. A
Q4
pulse width of 1.5 msec identifies no-inIC4A
Q3
put or full-stop conditions. Listing 1 proV
DD
vides an example of this motion-control
application.
Subtract 494 ($1EE) from the value of
Timer 1, captured after the falling edge of
tPH
the pulse, assuming that the pulse is positive-going and that, at the rising edge of
the pulse, the value of the counter resets. An Atmel AVR microcontroller provides a novel method of controlling a motor.
The range of values between full reverse
and full forward becomes 6 to 506 ($6 to comes $01 to $FA. If you use the lower byte. Note that when the upper byte is 1,
$1FA). Forward motion is $101 to $1FA, byte of the adjusted Timer 1 value di- the direction is forward; when the upper
with $101 providing the least forward rectly to set the output comparison reg- byte is 0, the direction is reverse. You can
motion and $1FA providing the most isters OCR0 or OCR2 of Timer 0 or download the C-based Listing 1 from the
forward motion. Reverse motion ranges Timer 2, you can use as much as 98% of Web version of this Design Idea at
from $FF to $6, with $FF providing the the range of input values to the PWM. www.ednmag.com.
least amount of reverse motion and $6 You can choose which PWM-configured
providing the most amount of reverse timer to use based either on where the Is this the best Design Idea in this
motion. If negated, the reverse range be- value occurs in the range or on the upper issue? Select at www.edn.com.
Precision circuit closely monitors 48V bus

Paul Smith and Jim Staley, Analog Devices, Wilmington, MA
ver-greater complexity in communications systems has spurred a
need for power-supply management. POTS (plain-old telephone systems) obtain power from 48V supplies
backed by arrays of batteries in central offices and distributed throughout copper
lines. Although nominally 48V, the
voltage on the lines can vary from 40 to
80V, and the voltage is subject to surges
and fluctuations. Supply regulation at the
source has little effect on remote voltage
100 edn | October 17, 2002
levels. Equipment failures resulting from

surges, brownouts, or other line faults
may sometimes be undetectable. Capturing power-supply information from remote communications equipment requires precise measurement of the
voltagessometimes in outdoor temperatures. High-common-mode, voltage-difference amplifiers have been useful in monitoring current. However, you
can also use these versatile components
as voltage dividers, enabling remote
monitoring of voltage levels as well.

Figure 1a shows the basic circuit connections when you use a difference amplifier for high-line current sensing. With
the addition of a few parts, you can operate this amplifier in a negative-supply
system. Figure 1b shows a precision
monitor using just two ICs and deriving
its power from the 48V supply. All you
need to power the circuit are a transistor
and a zener diode to reduce the supply
voltage for the amplifiers. The AD629
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design
ideas
VPOS
AD629
Figure 1
REF 2 1
21.11k
IN 2
380k
+IN 3
380k
NC
380k
10k
8
15V
RSHUNT
VS
48V
4
20k
ISHUNT
48V
REF 1
AD629
6 10k
5
(a)
(b)
1 nF
COMPENSATION
AMPLIFIER
7 OP97
3
+
6
2
TO
ADC
48V
48V
A basic monitoring circuit (a) uses a difference amplifier for high-line current sensing; the complete circuit (b) requires just two ICs.
4.5
2.1064
Figure 2
Figure 3
2.1062
2.1060
3.5
OUTPUT
VOLTAGE
(V)
OUTPUT 2.1058
VOLTAGE
2.1056
(V)
2.1054
2.5
2.1052
2
30
40
50
60
70
INPUT VOLTAGE (V)
80
90
The circuit in Figure 1b produces an output thats a linear function of

the negative supply voltage.
shown in Figures 1a and 1b is a self-contained, high-common-mode, voltagedifference amplifier with unity gain.
Connected as shown, however, it reduces
the differential-input voltage by approximately 19, thus acting as a precision voltage divider. You need an additional am-
2.1050
50
0
50
TEMPERATURE (C)
100
Temperature drift in the circuit of Figure 1b is negligible.
plifier for loop stability. The circuit features several advantages over alternative
approaches. The laser-trimmed divider
resistors exhibit essentially perfect
matching and tracking over temperature.
Linearity errors from 40 to 80V are
nearly immeasurable. Figures 2 and 3
show the linearity and temperature-drift

curves for the monitoring circuit.

PLD code reveals pc-board revisions

he PLD (programmable-logic-device) code in Listing 1 implements
a pc-board-level revision-detection
system that detects whether PLD pins are
shorted together on a pc board. It is often
advantageous to field a single PLD programming file that works for several generations of physical hardware. The PLD
needs to understand what the board re-
102 edn | October 17, 2002
vision is, so that it can enable or disable

functions, pins, or both to external cirTABLE 1PATTERN-GENERATOR ACTIONS
State
REV_OUT line
0
Tristated
1
Tristated
2
Drive with pattern
3
Tristated
REV_IN[x] lines
Drive low
Tristated
Look for pattern
Tristated
cuitry. If a designer has not placed physical straps to indicate a pc-board-revision

level from the start, it may be difficult to
add them later. In PLD families that have
no integral pin-pullup or -pulldown resistors, redefining previously unused pins
as inputs means that these pins float, either causing erratic operation or indicating an improper pc-board-revision level.
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The software module generates a

short, simple pattern, such as a square
wave, onto a driver pin, REVO_OUT. The
input-detection pins, REVI_IN[x], look
for this pattern. If they detect the full pattern on a pin, the module indicates that
the pins are connected by setting the respective Q[x] high. If they do not detect
the full pattern, the module sets the Q[x]
line low. The pattern generator avoids
leaving the revision-detection inputs
floating by alternately driving and tristating the REVO_OUT and REVI_IN[x]
lines (Table 1). If you drive the circuit at
more than a few megahertz, the parasitic
pin capacitance of a few picofarads is sufficient to ensure that the REV_I[x] pins
stay low, even while they are tristated.
When the detection cycle is finished, the
COMPLETE line goes high.
The module generates the required
hardware from two compile-time parameters: LPM_WIDTH and CHANNELS. LPM_WIDTH sets the number of
times the detection cycle runs (for example, 5 bits yields 25, or 32 cycles), and
CHANNELS sets the number of strap inputs. Note that this function does not include tristate buffers; you must instantiate them at the design top level. The
REVO_EN and REVI_EN pins enable the
REVO_OUT and the REVI_IN[x] tristate buffers, respectively. The PLD code
is written in Alteras (www.altera.com)
high-level design language (AHDL); you
can directly compile it into any of Alteras
PLDs. An implementation of the design
with the parameters set to the default values takes 16 logic cells in an Altera
EP1K50BC256-3less than 1% of the
deviceand runs at rates as high as 185
MHz. Although the code is written for
Alteras devices, the design structure and
flow are readily translatable into VHDL
or Verilog.
LISTING 1AHDL CODE FOR REVISION DETECTION

104 edn | October 17, 2002
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design
ideas
Simple method tests cables

Jim Keith, Bell-Mark Technologies, Dover, PA
V
ngineers have long known how

40 mA
to test a cable for continuity
F
i
g
u
r
e
1
1
1
by simply connecting all con2
2
ductors in series and checking with an
ohmmeter. This method is sometimes
3
3
impractical, however, because it cannot
4
4
check for short circuits. The method
5
5
shown in Figure 1 solves the short-circuit
6
6
problem. Connecting LED indicators at
CABLE UNDER TEST
each shorting loop provides a visual inSENSITIVE
dication. The beauty of this scheme is
24V
RELAY
that any short circuit causes at least one
10 mA
LED to extinguish.You can then diagnose
K
the malfunction by the visual signature
of the LEDs. Taking the method one step
further, let the LEDs be the emitters of
photocouplers. Connecting the photo- This simple cable-testing method tests for continuity as well as short circuits.
transistors in series provides a simple gono-go test that requires no visual obser- when youre testing a cable with a large Is this the best Design Idea in this
vation. Note that the 2V LED for- number of conductors, so be sure to ap- issue? Select at www.edn.com.
ward-voltage drop presents a challenge ply a high enough voltage.
106 edn | October 17, 2002
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design
ideas
DPPs make nonvolatile microvolt DAC

he availability of a seemingly limVCC
3.3 TO 5V
itless variety of monolithic
8
7
Figure 1
1/
DAC chips makes it easy to
+
+
2 BURR BROWN
REF200
implement most digital-to-analog-con100 A
100 A

version applications with a single off-the2
1
shelf device. Sometimes, an unusual set
+
of requirements necessitates a multichip
CAT5113
48.7
CAT5113
VCC
VCC
approach, however. One example of such
I3
I1
8
8
3
a requirement is the need for nonvolatil3
CS 7
CS 7
K2
K
ity of the DACs setting in power-up and
V= 1 +
=0 TO 5 mV,
DIR
2
DIR 2
200 10,000 1-V
-down cycles. Another example is the
8
8
K1 10k
K2 10k
INC 1
INC 1
RESOLUTION
need for output resolution and stability
1
IC1
IC2
at less than 1 V. The circuit in Figure 1
4
4
7
7
combines inexpensive DPPs (digitally
I4
I2
programmed potentiometers) from Cat
alyst Semiconductor (www.catsemi.com)
NOTES:
I1=K1100 A.
with precision current references from
I2=(1K1)100 A.
Burr-Brown (www.ti.com) to achieve
I3=K2100 A.
I4=(1K2)100 A.
both nonvolatility and less-than-1-V
performance. Accurate simulation of the
signals from high-temperature platinum- Digitally programmed potentiometers combine to form a novel, microvolt-level DAC.
rhodium-based thermocouples requires
less-than-1-V performance. These tem- normally require the use of active circuit tentiometer is inadequate for many preperature sensors have Seebeck coeffi- elements, such as chopper-stabilized am- cision applications.
IC1, a CAT5113, like other DPPs, offers
cients of only 6 V/C. Therefore, only plifiers, with offset temperature coeffivoltage sources with 1-V-level stability cients not much higher than 1 nV/C. the versatility of an uncommitted resistand precision can simulate such sensors. The circuit in Figure 1 takes a different ance element and nonvolatility of the setTo achieve such low output drift would approach by using current division and ting. Its resolution, however, is only 100
a passive and, therefore, inherently drift- steps, which is slightly worse than 7 bits
free output that needs no amplifiers. Each and equivalent to 50 V in this circuit.
DPPs make
half of the REF200 sources a 100-A ref- You therefore incorporate a second DPP,
nonvolatile microvolt DAC ........................101
erence current. The twin currents each IC2, in the converter. IC2s output current
connect to the wiper of DPPS, IC1 and acts into the 1 load for a 50-to-1 resoCircuit manages power-up
. There, they split into two currents lution enhancement over IC1 alone. IC2
IC
sequencing ....................................................102
2
(for example, I1 and I2) in a wiper-to-to- thus adds a 0- to 100-V contribution to
Lower dc/dc-converter ripple by using
tal ratio, K1, which the programmed set- V. Hence, the composite output is
optimum capacitor hookup ......................104
ting of the DPP determines. I1K1100 VK1/200K2/10,000 with a 5-mV span
Add an auxiliary voltage
A, and I2(1K1)100 A. I1 passes and 1-V resolution. The circuit is an
to a buck regulator......................................108
through the series combination of the ideal approach for such applications as
48.7 resistor and the 1 output resistor the simulation of thermocouple signals
Circuit checks swamp-cooler
and thereby generates the output voltage: in precision temperature-measurement
water level......................................................110
VK1(50100 A)0 to 5 mV as K1 and -control systems.
varies
from 0 to 1. The operation is
straightforward and drift-free. Unfortu- Is this the best Design Idea in this
nately, the resolution with a single po- issue? Select at www.edn.com.
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October 31, 2002 | edn 101
design
ideas
Circuit manages power-up sequencing

Martin Galinski, Micrel Semiconductor, San Jose, CA
ower sequencing poses a unique
VIN
VIN
VOUT
problem in power manage3.3V
IC1
Figure 1
C1
ment. Because improper seMIC37302BR
quencing may cause damage to many
FB
EN
types of processors, power-up sequencing of these devices is critical. Devices
D1
OFF
that may require power-up sequencing
1N4148
ON
R3
control include FPGAs, ASICs, and DSP
300k
chips. These devices can require tracking
ENABLE
I/O and core voltages. Requirements for
+
R4
power-up sequencing may change ac4.99k

IC2

cording to device type and manufacturMIC7300BM5
C3
C4
er, so its important that you review se1000 pF
quencing requirements for each device.
This design use Xilinxs (www.xilinx.
com) power-up requirements for the
Spartan-II and Spartan-IIE families. The This circuit controls the power-up sequencing for Xilinxs Spartan ICs.
I/O voltage must reach full supply voltage in 2 to 50 msec. Also, the slew rate of
VIN
VIN
VOUT
3.3V
IC1
the supply voltage must not exceed 900
R1
C1
MIC37302BR
10k
mV/msec but must exceed 50 mV/msec.
FB
EN
The circuit in Figure 1 addresses these isR2
10k
sues, allowing for consistent and reliable
R3
D1
Q1
OFF
300k
1N4148
2N7002
power-up sequencing.
ON
The power-up sequencing circuit uses
IC2
ENABLE
an RC (R3 and C3) timing network to conMIC7300BM5
+
R4
4.99k
trol the slew rate of the output during

turn-on. IC2 compares the output of the
C3
C4
1000 pF
low-dropout regulator with the voltage at
D2
SCHOTTKY
the RC network. It then adjusts the outVIN
VOUT
put of the regulator, via the feedback voltIC3
C1
R1
age, to match the RC charge voltage.
MIC37302BR
10k
When the voltage between R3 and C3
FB
EN
R2
47.5k
IC4
MIC7300BM5
+

VOUT
2.5V
R1
10k
R2
10k
C2
47 F
CERAMIC
VOUT
2.5V
C2
47 F
CERAMIC
VOUT
1.5V
C2
47 F
CERAMIC
D1
1N4148
R4
4.99k

C4
1000 pF
Figure 3
This circuit controls the I/O and core-voltage power-on and poweroff sequencing.
C3 controls the rise time of the output of Figure 1s circuit.
102 edn | October 31, 2002
reaches the low-dropout regulators regulation voltage,

Figure 2
the output of
IC2 pulls low, reversebiasing D1, thereby removing the power-up
sequencing circuit from
the control loop. R4 and C4 provide compensation to maintain a smooth voltage

during the turn-on cycle. R1 and R2 provide the output regulation voltage. You
can calculate R1 and R2 from the following expression: R1R2 (VOUT/1.240 1).
Figure 2 shows slewing characteristics of
the output with various values of C3.
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ideas
Figure 3 is an I/O and core-voltage-sequencing circuit. Instead of using an RC

charge voltage to control the turn-on, IC3
of the core regulator compares the output of the I/O during turn-on and
matches the core voltage until it reaches
the regulation voltage. Figure 4 shows
the I/O and core voltages during the

power-on cycle. Equally important is the
power-down cycle. The I/O voltage must
never reach 0.6V below the core voltage.
This condition can forward-bias the substrate diode, damaging the processor. D2,
a Schottky diode with a forward voltage
Figure 4
The I/O and core voltages have controlled rise times during the poweron phase.
drop of 0.4V, keeps the I/O voltage from

dropping 0.6V below the core voltage
during the power-down cycle (Figure 5).

Figure 5
A Schottky diode keeps the I/O voltage from dropping 0.6V below the
core voltage.
Lower dc/dc-converter ripple

by using optimum capacitor hookup
Keith Szolusha, Linear Technology Corp, Milpitas, CA
ow-ripple-voltage positive-to5V
negative dc/dc converters find use in
VIN
CMDSH-3
many of todays high- frequency and
BOOST
0.22 F
noise-sensitive disk drives, batLT1765EFE
CDRH6D28-3R0
Figure 1
tery-powered devices, portable
VSW
VIN
computers, and automotive applications.
31.7k
FB
SYNC
Like a positive buck converter, a positiveto-negative converter can have low outSHDN
B320A
put-ripple voltage if you place the bulk
VC
GND
10 F
10 F
input capacitor between VIN and VOUT
16V
6.3V
10k
X5R
CERAMIC
X5R CERAMIC
rather than between VIN and ground. A
1800 pF
100 pF
common misconception is that positive2.4k
to-negative converters in the first configuration have noisy outputs. This configuration actually solves noise problems
VOUT
rather than introducing them. In either
5V, 1A
configuration, the VIN and ground pins
5V converter with the bulk input capacitor between VIN and VOUT has low output ripof the IC connect to VIN and VOUT, re- This 5-to-
spectively (figures 1 and 2). Therefore, ple. The high-di/dt path, indicated here with blue lines, does not include the output capacitor.
104 edn | October 31, 2002
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design
ideas
placing the input capacitor between VIN

10 F, 6.3V, X5R CERAMIC
and VOUT is equivalent to placing it between the ICs VIN and ground pins (Fig5V
CMDSH-3
VIN
ure 1). The other, commonly accepted
0.22 F
BOOST
method of placing the bulk input capacLT1765EFE
CDRH6D28-3R0
itor between VIN and ground (FigVIN
VSW
Figure 2
31.7k
ure 2) significantly increases the
SYNC
FB
output-voltage ripple (figures 3 and 4).
SHDN
B320A
To make matters worse, this configuraVC
GND
0.1 F
100 F
tion requires an additional high-fre16V
6.3V
10k
X5R CERAMIC
X5R CERAMIC
quency bypass capacitor between the VIN
4700 pF
100 pF
and ground pins of the IC.
22k
In simple positive-to-negative converters, such as those in figures 1 and 2,
VOUT
the output-voltage ripple is
5V, 1A
VOUT(P-P)ESRCOUTICOUT(P-P).
5V converter with the bulk capacitor between VIN and ground has much higher output
Low-ESR output capacitors, such as This 5-to-
ceramics, help to minimize the output- ripple than the circuit in Figure 1. The high-di/dt path, indicated here with blue lines, includes the
voltage ripple in dc/dc converters. For a output capacitor, thus increasing output ripple.
given output-capacitor ESR, you can further reduce the output-voltage ripple by placed as shown in Figure 2, the peak-to- moving the output capacitor from the
minimizing the current ripple that the peak ripple current in the output capac- high-di/dt switching loop (by judicious
output capacitor is forced to absorb. In itor is much higher than the inductors placement of the input capacitor) is a
Figure 2, the output capacitor is part of ripple current alone; it is almost equal to greatly simplified layout. You must place
the high-di/dt switching-current path, the inductors ripple current plus the in- the high-di/dt components in Figure 1 in
making the output voltage ripple pro- put capacitors ripple current:
the smallest loop possible to minimize
portionately larger. With the bulk input ICIN(P-P)IL(P)IOUTIINIL(P-P)/2, and trace inductance and the resulting voltcapacitor placed as shown in Figure 1, ICOUT (P-P) IL(P-P)ICIN(P-P). With age (noise) spikes. With one fewer comthe peak-to-peak ripple current in the much lower output-capacitor ripple cur- ponent to worry about in the layout, you
output capacitor is equal to the peak-to- rent, the output capacitor in the circuit can more easily create a noise-free circuit
in Figure 1 can be much smaller than using the layout in Figure 1 than it is uspeak ripple current in the inductor:
ICOUT(P-P)IL(P-P)(VIN duty cy- that of the circuit in Figure 2. Also, it ing the one in Figure 2.
cle)/(fSWL), where ICOUT(P-P)output needs to handle much less rms ripple
ripple current, IL(P-P)inductor ripple current (approximately equal to peak-tocurrent, and fSWswitching frequency.
peak ripple current divided by the square Is this the best Design Idea in this
When the bulk input capacitor is root of 12). Another advantage of re- issue? Select at www.edn.com.
In the circuit in Figure 1, the output capacitors

Figure 3
peak-to-peak current ripple is equal to the inductors peak-to-peak ripple with 1A output.
106 edn | October 31, 2002
In the circuit in Figure 2, the output capacitors

peak-to-peak current ripple is five times as high as
the inductors peak-to-peak ripple and, therefore, five times as high
as the current ripple shown in Figure 3 with 1A output.
Figure 4
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design
ideas
Add an auxiliary voltage to a buck regulator

John Betten, Texas Instruments, Dallas, TX
ou often need more
Q2
VIN
than one regulated
output voltQ3
Figure 1
age in a system.
NS
+
A frequently used and reaT1
sonably simple way to creFET
CONTROL
NP
DRIVER
CIRCUIT
ate this auxiliary output
Q1

voltage is to add a second
+
VF1
C
winding to the output in
ductor, creating a coupled
inductor or a transformer,
FEEDBACK
followed by a diode to rectify (peak-detect) this out- This synchronous buck converter has an auxiliary-output winding.
put voltage. The biggest
drawback of this approach is that the voltage across the primary winding. The
diodes voltage drop varies with temper- output capacitor on the auxiliary output,
ature and load current and can have a 2- V02, then charges to the peak of the secto-1 variation, resulting in poor output- ondary-winding voltage. FET Q2 turns off
voltage regulation. This problem be- when Q3 turns back on to prevent the outcomes more critical as output voltages put capacitor from discharging. The secdecrease and may require the addition of ondary voltage floats; you can add it to the
a linear regulator. The circuit shown in main output voltage by tying one end of
Figure 1 is an alternative approach that the secondary winding to the main outreplaces this diode with Q2, a p-channel put. You can also tie it to ground for an
FET. The circuit works as follows:
output voltage lower than V01, if desired.
During the conduction time of FET Q1, The equation that defines the auxiliarythe voltage across the primary winding of output voltage for the circuit in Figure 1
transformer T1 clamps to the voltage, is:
VOUTVF1, where VF1 is the voltage drop
N
N
across FET Q1. Through transformer acV02V01 1 S VF1 S VF2 .
N
N
tion, the voltage on the secondary windP
P
ing of inductor L1 is equal to the turns ratio between the windings times the
The second half of this equation rep-
Q1
IRLMS5703
Figure 2
5V
IC1
TPS62000DGS
1
VIN
4.5 TO 5.5V
2
3
4.7 F
6.3V
0.1 F
4
5
VIN
FC
GND
PG
FB
PGND 10
L 9
EN
SYNC
8
7
ILIM 6
10 F
6.3V
T1
3.3V
L1
10 H
R1
825k
R2
130k
This circuit is similar to the one in Figure 1, but uses an integrated buck-converter IC.
108 edn | October 31, 2002
10 F
6.3V
resents a voltage-error term

between FETs Q1 and Q2. To
cancel out the error attributV02
able to the FET voltage drops,
C
you need to make the voltage
drop of FET Q2 equal to
VF2VF1(NS/NP), where
V01
NS/NP is the transformers
turns ratio. Because these
FET voltages are a function
of the output currents and
the on-resistance of the FETs,
you can select the on-resistance of FET Q2 by using the
following equation:
R Q 2 = R Q1
NS
NP
I
N
V
(1d)1 + 01 d S , where d = 01 .
N P
VIN
I02
In Figure 2, the main output voltage is

3.3V, yielding an inductor primary voltage when Q1 is conducting equal to only
3.44V, because of the low voltage drop
across FET Q1. Thus, if you wanted a 5V
output, the secondary winding would
need to develop an additional 1.7V, necessitating a 2-to-1 step-down turns ratio. The desired on-resistance of the FET
internal to IC1 from the above equation
should be 0.16 to cancel the voltage
drop across Q1 at maximum loads and
while operating from a 5V input voltage.
This example uses a 0.20 FET with a
voltage drop equal to only 88 mV. This
choice allows for good voltage matching
between FETs Q1 and the FET internal to
IC1, resulting in excellent error cancellation, less power loss, and better overall
output-voltage regulation than diode
rectification provide. An added benefit of
this approach is that you can use it with
controllers that have integrated switching FETs, because you dont need access
to Q1 and Q3 gate drives. Measured results, although varying both outputs
loads over their full operational range,
showed less than a
3% variation in the
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ideas
Circuit checks swamp-cooler water level

Daniel Krones, Precision Design Services, Sky Forest, CA
swamp cooler is an
to create a pulsed tone
VCC
easy way to obto drive the piezoelecFigure 1
R1
tain effective air
tric-bell audible alarm.
1M
1
conditioning, especially in
Current consumption
IC1A
5
3
4
8
IC1B
2 4093
hot and dry climates, if a
in the off state is lower
1
IC1C
10
6
4093
PROBE
9 4093
2
water source is readily availthan 10 A, thus al10k
1k
C1
able. Although most units
lowing
the use of a
22k
0.01
are very reliable, the storagesimple
battery
to drive
F
PIEZO
12
reservoir control usually
the circuit. A buttonBELL
IC1D
11
13 4093
uses a single level-detector
cell lithium watch batcomponent. Failure of this
tery is sufficient. The
+
22k
5.6 F
component can lead to serismall physical size and
ous water damage. The cirwiring simplicity of
cuit of Figure 1 provides a Detect water level in a swamp-cooler reservoir with this simple circuit.
the circuit allow you to
simple, inexpensive backup
simply glue the unit to
alarm signal if the water level exceeds the have to experiment to determine a suit- the side of the cooler. Use a short piece
preset height. The circuit uses a single able value, depending on the conductiv- of twin-lead, 300 transmission line for
Schmitt-trigger IC to detect the water ity of the water supply.
the electrodes.
The highest practical vale of R1 prolevel, using the conductivity of the water
to drop the input level of IC1A. A 1- to 10- vides the widest range. The NAND gates Is this the best Design Idea in this
M resistor is suitable for R1. You might IC1B and IC1D implement gated oscillators issue? Select at www.edn.com.
110 edn | October 31, 2002
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design
ideas
DPP adds versatility to VFC

he basic VFC (voltage-to-frequenR2
cy converter) in Figure 1
F
i
g
u
r
e
1
comprises an integrator
(IC1) and a Schmitt-trigger circuit (IC2).
VIN
R3
C1
R1
The integrator converts the dc input voltage, VIN, to a linear voltage ramp, and the
_
Schmitt trigger sets the limits of the inIC1
tegrators output voltage. Feedback
+
around both circuits provides the condiINTEGRATOR
tion for oscillation. The DPP (digitally
programmable potentiometer) in Figure
2 adds programmable limits to the
Schmitt trigger and adds two powerful This schematic depicts a basic voltage-to-frequency converter.
features to the VFC. First, the scale or
conversion factor is programmaFigure 2
R2<<R1
D1
ble, and, second, for a fixed dc-in1k, 1%
put voltage, the converter is a programmable oscillator. The frequency, f0, of the
pR3 (1p)R3
VIN
single-supply converter in Figure 2 is:
6
3
f o f BASE
(1p ) (VIN 2.5V );

p
R1
20k, 1%
where fBASE1/2R1C1, and p is the relative position of the wiper from one end
(0) of the DPP to the other end (1). For
the100-tap Catalyst (www.catsemi.com)
VOUT
SCHMITT
TRIGGER
5V
8
1
2
7
5V
2 +
IC1
LT1097
+
4
IC2
_
5V
0 p0.5, and 2.5V VIN 5V ,
10k
C1
0.01 F
5V
2 _
R4
V1
510
IC2
LM211
3 _
CAT5113
DIGITAL
CONTROLS
V0UT
4
1
2.5V
DPP adds versatility

to VFC................................................................99
Power circuit terminates
DDR DRAMs..................................................100
Circuit protects bus
from 5V swings ............................................102
Use a 555 timer as a
switch-mode power supply........................104
VCO uses programmable logic................106
Controlling slew times tames
EMI in offline supplies ................................108
www.edn.com
edn021031dix30741
Using a digitally programmable potentiometer,
you can vary the scale factor of this voltage-to-freHeather
quency converter.
5113 potentiometer, the range of the rate resistors and capacitors. The scale
scale-factor term (1-p)/p is 1 to 99 with factor relates to the ratiometric tempera resolution and accuracy of approxi- ature coefficient of the DPP and hence is
mately 1%. For the values shown in Fig- minimally temperature-dependent. You
ure 2, the practical range of frequencies can use the circuit as a programmable osis 500 Hz to 25 kHz. Higher bandwidth, cillator when VIN is fixed and the potenrail-to-rail CMOS versions of IC1 and tiometers wiper setting changes the limIC2, and a greater R1/R2 ratio can extend its of the Schmitt trigger.
the accuracy and range of the circuit. The
automated, accurate setting ofedn021031dix30742
the scale
factor saves manufacturing test time and
Heather
eliminates the need for expensive, accu- issue? Select at www.edn.com.
November 14, 2002 | edn 99
design
ideas
Power circuit terminates DDR DRAMs

Ron Young, Maxim Integrated Products, Sunnyvale, CA
DR (double-data-rate) SDRAMs
find use in high-speed memory systems in workstations and servers.
The memory ICs operate with 1.8 or 2.5V
supply voltages and require a reference
voltage equal to half the supply voltage
(VREFVDD/2). In addition, the logic outputs terminate with a resistor to the termination voltage, VTT, which equals and
tracks VREF. VTT must source or sink current while maintaining VTTVREF
0.04V. The circuit of Figure 1 provides
the termination voltage for both 1.8 and
2.5V memory systems and delivers out-
Figure 1
5V
INPUT
4.7 F
10V
16
VP
9
15k
22 nF
put current as high as 6A. IC1 includes a

step-down controller and two linear-regulator controllers and operates with input voltages of 4.5 to 28V.
IC1s fixed-frequency, 200-kHz PWM
controller maintains the output voltage
by sourcing and sinking current. Maximum sink current equals the maximum
source current, though the sink current
has no current limiting. When sinking
current, the device returns some current
to the input supply. To implement the
tracking function, one of IC1s extra linear-regulator controllers is configured as
22 F
10V (4)
15
BST
14
ILIM
COMP
DH
13
0.1 F
FDS6690A
4.7
1000 pF
LX
IC1
MAX1864T
5V
DL
GND
OUT
POK
FB
POK
+
1.24V
11
10
FDS6690A
1.5 H
DO5022P
EC31
QS03L
1.25V
6A
+ 1200 F
2.5V
OS-CON
4.7
3
4
R5
10k
B2
R3
10k
FB2
R7
220
B3
5V
1 F
10V
CMPT
3906
330 pF
22.1k
8
FB3
EC31
QS03L
12
1OOk
1

1200 F
10V
MV-AX
CMPSH-3
VL
an inverting amplifier. This amplifier

compares VDD/2 (created by R1 and R2)
with VREF from IC1 and generates an error signal that connects via R3 to IC1s FB
pin, thereby forcing VOUT to track VDD/2.
A 10-mA load, R4, is necessary to bias the
inverting amplifier for accurate tracking.
VOUT can track VDD/2 for VDD in the range
1 to 4V.
22 F
10V
22.1k
R4
100
R1
1k
2.5V
0.1 F
R2
1k
This circuit generates the termination voltage for DDR synchronous DRAMs.
100 edn | November 14, 2002
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ideas
Circuit protects bus from 5V swings

Said Jackson, Equator Technologies Inc, Campbell, CA
C
1
he circuit in Figure 1 auto0.01 F
5V
matically detects voltage
5
3
Figure 1
VCC GND
and protects a bus, such
4
2 IC
as a 3.3V-limited PCI bus, from 5V
1+
PCI_SERR#
NC7SZ125
signal-level swings.You can also use
1
5V
the circuit to determine bus-voltage
4
swings within one bus-cycle for set10
PR
2 D PR Q 5
12
9
ting appropriate termination voltD
Q
IC2A
IC
2B
3
ages of protection diodes or termi5V
11
6
8
PCI_CLK
CLK
CLK
Q
Q
CL
CL
nation resistors. Todays deepR1
13
1 74LVC74A
3.3
74LVC74A
PLACE CLOSE
submicron VLSI-manufacturing
0603
PCI_RST#
TO PCI BUS
5
1
R4
techniques sometimes require cirPCI
Q
VCC
1.5k
C2
R3 0603 2
LS1 12V
AD10 R2 0603
+ C3
cuits to limit I/O voltages to 3.3V
GND IC3
0603
0.1 F
P9948-ND
1
10 F
4
2k
2k
3
0805
PANSONIC
IN
IN+
0805
signal swings. Connecting such cirPCI_AD[31..0]
1%
1%
2
EFB-CB37C11
METAL
METAL
C
cuits to a bus with 5V level-swing
MAX999
5V BUS
B
TOP VIEW
Q1
cards could damage the circuitry.
WARNING
1.88V5%
5V
BUZZER
The circuit in Figure 1 can accuE FMMT4123CT-ND
R6
C4
R5
9k
SOT-23
0.1 F
15k
rately andwithin one bus cycle
1%
METAL
JP1
0805
1% METAL
0603
detect a level swing larger than 3.3V
0603
1
ENABLE
PROTECTION
2
on any bus and, upon a fault situaHEADER2
tion, generate a reset signal and an
alarm output to notify the user and This circuit provides both an audible alarm and an error flag when an overvoltage condition exists.
the system of this fault. Some of the
The circuit generates a signal that can PCI_AD10. Every PCI device asserts this
novel circuit features include a highly accurate synchronous-detection capability reset the system, or it can generate a sys- signal at least once during PCI enumerto avoid false alarms arising from large tem-error signal. Because the alarm-reg- ation, but you can monitor other signals
signal overshoots, high impedance and ister memory, IC2B, serves as an asyn- if necessary. This method guarantees
low capacitive loading of the bus, auto- chronous register, you can switch the recognition of a 5V PCI device shortly afmatic system shutdown during fault con- alarm off only by removing power from ter the BIOS starts enumerating the PCI
ditions, and a single-cycle response time. the system or by asserting the reset signal. bus during system boot. IC2A then latchThis circuit successfully operates in To avoid false triggering by signal over- es the comparators, IC3, Q-output Pin 1
products using the high-performance shoot and undershoot, a flip-flop-based during the rising edge of the PCI clock.
3.3V MAP-CA processor family from register, IC2A, samples the comparator This action asserts flip-flop IC2B, which
Equator Technologies (www.equator. output only during the rising edges of the in turn enables buzzer LS1 and generates
com), but you can use it in other high- bus clock. This method allows for a gen- an open-collector, low-active, system-erspeed 3.3V or even lower voltage systems. erous 33-nsec period at 33 MHz for the ror signal through IC1. You could use this
Equators latest generation chips are 5V- bus signal to settle down before being error signal to automatically remedy the
tolerant, but you can adjust the circuit to sampled. Lowpass filtering by sensor re- fault condition by disabling the offendprotect other 1.8 and 2.5V chips. The cir- sistors R2, R3 and the 3- to 5-pF parasitic ing circuit on the bus. The sense and refcuit uses IC3, an ultrahigh-speed Maxim capacitance on Pin 3 of IC3 limit the max- erence resistors R2, R3, R5, and R6 should
(www.maxim-ic.com) MAX999 com- imum clock speed of this circuit. The be metal-film 1% types. The 5V reference
parator with 4.5-nsec propagation delay, traces connecting to Pin 3 of IC3, R2, and voltage connected to R5 determines the
TPD, to constantly compare a signal line, R3 thus must be as short as possible and accuracy of the trip voltage, and todays
PCI_AD10 in case of a PCI bus, to a ref- may limit the bus speed to approximate- power regulators have sufficient accuraerence level of 3.8V. This reference volt- ly 40 to 50 MHz. Symmetrically lower- cy so that you can use a 5V system-powage is an optimal compromise between ing the resistance of R2 and R3 increases er line as the reference voltage, obviating
5V signals clamped by 3.3V protection the maximum bus speed to a theoretical the need for a special 5V-reference gendiodes and the normal-operation 3.3V 7-nsec cycle time (greater than 140 MHz) erator. Removing jumper JP1 disables the
signals. Once the voltage exceeds this ref- at the expense of a higher signal-loading circuit.
erence level for an entire bus clock peri- current on the bus.
In the case of monitoring a PCI bus, Is this the best Design Idea in this
od, the system turns on an alarm buzzer
Pin 3 of comparator IC3 monitors signal issue? Select at www.edn.com.
connected to Q1.
www.edn.com
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ideas
Use a 555 timer as a switch-mode power supply

Aaron Lager, Masterwork Electronics, Rohnert Park, CA
ost switch-mode power supplies
rely on a PWM (pulse-widthmodulated) output that is controlled via voltage feedback. A 555-timer
IC can inexpensively perform PWM. The
circuit in Figure 1 shows how to turn a
555 PWM circuit into an switch-mode
power supply with only one simple equation. The design uses two 555s. IC1, in
astable mode, triggers IC2 in PWM mode.
IC1 is set to oscillate at approximately 60
kHz at a high duty cycle. The output is
low for only approximately 2.5 sec to
trigger the PWM circuit and then goes
high for the rest of the period. The PWM
circuit has a maximum pulse width of approximately 85 sec, and it becomes
shorter, depending on the control voltage
from the feedback circuit. You can reduce
the chip count by using a 556 or another
IC3, R1, R2, and V1 form the feedback circuit to set the output voltage. The outputvoltage equation is VOUTV1(R1/R21).
The TL431 is a popular part for setting a
voltage reference and can easily create the
1.25V shown for V1. You can supply 5V at
1.5A with an input of 9 to 40V. At voltages higher than 12V, you can add a 10V
zener-diode supply for the chips. The
zener supply only slightly reduces the efficiency. With 12V input, 5V, 1.5A output efficiency is approximately 70%, and
it drops to 65% with a 40V input and a
zener circuit. The zener diodes influence
is more noticeable at lower current levels;
at a 50-mA load the efficiency drops to
approximately 50%.
continuous-trigger source. The input

must be (1.5VOUTMargin), so for 5V
output you need 9V minimum input. If
you use CMOS chips and small timing
capacitors C1 and C2, you can keep the
operating current low. Thus, you can use
a simple zener-diode regulator for the
555 and increase the input voltage to
more than 30V. The input-voltage limit is
a function of how much power the zener supply can handle while delivering 5 to
10 mA to the 555s.
Q1 has low RDS(ON) and low VGS and can
handle more than 40V. D1 clamps any
voltage spikes, such as those that occur
when a large current flow ceases, causing
a large magnetic field to be left in the inductor. You should select D1 according to
the output voltage you need. For 5V output, use a 5.6V zener diode, for example.

POWER
PWM
ASTABLE TRIGGER
8
VCC
10k
0.1 F
2 TRIGGER
UNREGULATED
SUPPLY
+
4 RESET
5 CONTROL
83
IC1 OUTPUT
555
4
RESET
100
2
7 DISCHARGE
C2
0.001 F
3
GND
1
0.01 F
DISCHARGE
TRIGGER
6 THRESHOLD
Figure 1
4.7k
8
VCC
THRESHOLD
IC2
5
555 CONTROL
C1
0.01 F
OUTPUT
GND
1
POWER
0
3
Q1
ZVN4210G/ZTX
3
VOUT
REGULATED
SUPPLY
L1
68 H
1N5817
+
100 F
D1
1N4734
1
RLOAD
R1
10k
R2
3.33k
+ V1
1.25
V+
IC3
LF411/NS
OUT
5
4
FEEDBACK
VOUT1.25(1R1/R2).
0
Heres one more use for the ubiquitous 555 timer: a switch-mode power supply.
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design
ideas
VCO uses programmable logic

VCO (voltage-controlled oscillator) is an analog circuit, so
5V
5V
Figure 1
you cannot find it in the liR2
R4
R1
braries for the design of digital proR3
27k
6.8k
6.8k 27k
J2
STEERING
grammable chips. When you need such
OUTPUT
VOLTAGE
a circuit for synchronization or clock
1
1
multiplication, you need to find a circuit
2
ICST
D1
Q
2
1N4148
3
that works with the standard digital funcQ
D2
1N4148
tions, such as AND and NAND. Several
F
possibilities exist for building variableF
4
1
frequency oscillators. For example, you
IC1A
IC1B
can change the frequency using a varac74HC02
74HC02
tor diode. Unfortunately, these diodes
2 3
5 6
have a small change of frequency per volt.
C1
C2
So, the standard Pierce oscillator with
1 nF
1 nF
one inverter and capacitors is not useful
for these applications. Another idea is to
use a Schmitt-trigger inverter and to vary This unique VCO, implemented with discrete logic, has a wide tuning range.
the charging resistor. This method can
work, but the hysteresis of the IC usualNOT
NOT
2
1
1
2
ly has a wide tolerance, so the selected inverter chip has a large influence
Figure 2
on the frequency.
1
1
For these reasons, this design modifies
4
1
NOR2
a two-NOR-gate RC oscillator (Figure 1)
TRISTATE
TRISTATE
NOR2
to function as a VCO. For almost all pureBUFFER
BUFFER
CMOS circuits, the switching point be2
2
2 3
5 6
tween high and low states is approximately VCC/2. This point does not depend
PAD5
PAD2
PAD6
on the device. Using this circuit, you can
BIDIRECTIONAL
BIDIRECTIONAL
OUTPUT
obtain a wide frequency-tuning range.
1
Q
The output is a square wave with a 50%
1
2
Q
R4
duty cycle. At power-on, both capacitors
ICST 2
R4
1k
C1
C2
OUTPUT
C1 and C2 are uncharged, and IC1A has a
1k
1 nF
1 nF
STEERING
low output. Thus, the output of IC1B is
VOLTAGE
VST
high, and C2 charges with the time constant R2C2. The additional charging current from ICST and R4 also influences this This VCO uses an EPLD and has high gain, expressed in kilohertz per volt.
charging time. When the voltage on C2
reaches VCC/2, IC1B switches to a low state. VCOs gain. The circuit uses an Altera grammable-logic devices with CMOS inNow, the output of IC1A switches high, (www.altera.com) EPLD (erasable pro- puts. You can also use steering voltages
and C1 charges with time constant R1C1, grammable-logic device), the EPM3032. much higher then the supply voltage of
influenced by ICST and R3. The low sig- Tristate buffers replace the diodes in Fig- the programmable chip, because the voltnal at the output of IC1B forward-biases ure 1, and the charging resistors connect age on the input of the chip never goes
D2 and quickly discharges C2.
directly to the steering voltage. This con- higher then VCC/2. This fact makes the
This circuit produces a 50% duty cy- figuration produces the highest possible circuit suitable as a voltage-to-frequency
cle if C1C2, R1R2, and R3R4. The val- VCO gain: approximately 700 kHz/V for converter with a high input-voltage
ues of R4 and R3 and the steering voltage, the component values shown. You can range.
VST, determine the VCOs gain in kilo- switch off the VCO by using a steering
hertz per volt. The circuit in Figure 2 voltage lower then VCC/2. You can imple- Is this the best Design Idea in this
yields the highest possible value for the ment this circuit using almost all pro- issue? Select at www.edn.com.
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design
ideas
Controlling slew times tames

EMI in offline supplies
David Canny, Linear Technology Corp, Milpitas, CA
MI from offline switching power
supplies typically causes all sorts of
problems for power-supply designers. You may need a large EMI filter to
meet FCC emission requirements.
Switchers for high efficiency produce
high-frequency switching noise that can
propagate through the rest of the system
and cause problems. Board layout is critical, requiring considerable experimentation, even for experienced designers.
The low-noise circuit in Figure 1 significantly reduces the complexity of these issues by continuous, closed-loop control
of the voltage and current slew rates.
High-frequency noise suppression is particularly important for medical devices
because they dont require the ac-line-toearth ground capacitors (Y capacitors)
DANGER: HIGH VOLTAGE

L1
X1
1M
90 TO
264V
AC 1M
pin. Q2, Q3 and their associated circuitry

provide undervoltage lockout with hysteresis. During start-up, the SHDN pin
stays low until C5 charges to 12V via R1.
The LT1738 then turns on and subsequently obtains most of its operating
power from T1s auxiliary winding. The
feedback goes directly to the LT1738s VC
pin rather than to the FB pin because the
optocoupler provides the feedback gain
that the LT1738s internal feedback amplifier typically provides. C6 and L1 attenuate the low-frequency harmonics of
the LT1738 switching frequency.
You can see the benefits of the circuit
by measuring its ac-line-conducted EMI
and then comparing these measured results with those for basically the same circuit with the LT1738 replaced with a
that typically suppress this noise. The absence of these capacitors allows medical
devices to easily comply with the more
stringent low-leakage-current healthcare specifications of UL544, UL2601,
and CSA22.2.
Figure 1 shows a 30W (12V output at
2.5A) offline power supply. IC1, an
LT1738 low-noise switching regulator in
a flyback topology, drives Q1 and continuously controls the current slew using the
resistor at the RCSL pin. The IC controls
the voltage slew using the resistor at the
RVSL pin and the capacitance at the CAP
pin. IC2, an LT1431 programmable reference, and the optocoupler close the isolated loop back to the LT1738. The circuit
achieves current limit by sensing the current through a 68-m resistor at the CS
BR1
C6
0.1 F
250V AC
"X2"
P6KE200A
C1 +
100 F
400V
510
2W
200 pF
200V
T1 11
220 pF
K
X3
Figure 1
R1
510k
C5
56 F
35V
7.5V
IN755A
510k
7
51k
8
Q2
19.6k 16
3.9k 15
3.9k
2N2222
Q3
51k
NC
10
12
A2
C2 +
330 F
25V
C3 +
330 F
25V
C4
+
330 F
25V
VOUT
12V
2.5A
VOUT
470 pF
NFB
15 pF
600V
SHDN
V5
15 pF
IC1
SYNC LT1738
CAP
CT
GATE
RT
CS
1.5 nF
165k
2N2222
19
VIN
A1
3
BA521
17
14
MUR160
10
100k
2W
10
D1
2
Q1
MTP2N60E
0.1 F
4
RVSL
NC
RCSL
PGND
VC
FB
SS
GND
13
10 nF
11
18
20
12
VOUT
1k
ISO1
CNY17-3
0.068
0.5W
38.3k
1%
3
4
COMP
8
REF
IC2
COLL LT1431 RTOP 4
7
RMIO
G-F
G-S
6
1k
0.22 F
V+
GCL
0.1 F
1k
10k
1%
NOTES:
D1: MBR20300CT.
UNLESS OTHERWISE NOTED,
L1: HM18-10001.
ALL RESISTORS: 1206,5%.
BR1: GENERAL INSTRUMENTS WO6G. T1: PREMIER MAGNETICS POL-15033.
C2, C3, AND C4: SANYO MV-GX.
A 30W offline power supply passes FCC Class B emission requirements without line-to-earth-ground capacitors.
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design
ideas
generic switcher. The only circuit-parameter difference is that, unlike the

LT1738, the generic switcher doesnt actively control the switching current and
voltage slew rates. Figure 2 shows the frequency spectra for both circuits. You can
see by the respective frequency spectra
that the LT1738-based circuit generates
emissions well within FCC Class B requirements, whereas the circuit with the
(b)
(a)
generic part results in emissions that exceeds FCC Class B allowable emissions by
a significant margin.
In these 50-MHz-wide spectral plots, areas under horizontal lines indicate acceptable
Figure 2
Another benefit of the circuit
FCC Class B emission requirements. The spectral plot for the LT1738-based circuit (a)
in Figure 1 is that the output voltage shows emissions well within FCC Class B requirements, unlike the plot for the generic switcher (b).
noise comprises the fundamental ripple
with practically no high-frequency com- the output with little attenuation through in medical devices because the absence of
ponents. You can attenuate this ripple the parasitic capacitance of the output fil- Y capacitors results in low leakage current
voltage if desired to less than 300 V us- ters inductor. The circuit in Figure 1 to earth ground in compliance with
ing a 100-H, 100-F LC filter on the minimizes noise and EMI by controlling health-care specifications.
output. The generic switcher, on the oth- the voltage and current slew rates of the
er hand, produces more output noise be- external n-channel MOSFET. This circuit Is this the best Design Idea in this
cause the high-frequency noise passes to is well-suited for offline power supplies issue? Select at www.edn.com.
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Circuit provides cold-junction compensation

Mark Maddox, Analog Devices, Wilmington, MA, and
John Wynne, Analog Devices, Limerick, Ireland
he accuracy of any circuit or system that uses a thermocouple to determine the temperature of a
Figure 1
process is limited by the accuracy
of the method used to perform coldjunction compensation. In a thermocouple measurement, two wires of dissimilar
metal join together at the hot, or measurement, junction. The isothermal termination of the thermocouple wires provides a second cold, or reference,
junction. The potential across the thermocouple is proportional to the temperature difference between the two junctions. Thus, to determine the absolute
temperature of the hot junction, you
must also know the absolute temperature
of the cold junction. Tables of thermocouple voltage versus temperature use the
assumption that the cold junction is
maintained at 0C. A somewhat impractical way to use these tables is to place the
cold junction into an ice bath. A more
practical way is to measure the temperature of the cold junction and then add an
equivalent voltage to the one developed
by the hot junction. You then find the
5V
5V
RB1
IEXC
RB2
300 A
AIN1
AVDD
RTD 1
AIN2
R1
METAL A
C1
COPPER
COPPER
R2
METAL B
C2
AIN3
AIN4
AIN5
AD7708
RTD 2
AIN6
RPREC
470
TERMINAL
(ISOTHERMAL)
BLOCK
ROFF
470
AIN7
AIN8
AIN9
RB3
5V
ADR421
REFIN1 ()
REFIN1 ()
AGND
This circuit provides accurate cold-junction compensation in temperature-measurement systems.

Circuit provides cold-junction
compensation ................................................93
Solve low-frequency-cutoff problems
in capacitive sensors ....................................94
Noninverting op-amp circuit
has simple gain formula ..............................98
Controller IC and one-shot
form resonant controller ............................100
Circuit folds back current
during fault conditions ..............................102
www.edn.com
temperature of the hot junction in the temperature gradient is nonlinear, you

thermocouple tables.
can add an electrically isolated copper
A key issue to address is how to ther- strip along the length of the block to minmally bond the RTDs (resistance-tem- imize the nonlinearity. In the extreme
perature detectors) to the terminal block, case, you could use a temperature sensor
which is the cold junction. If the temper- per thermocouple pair with each sensor,
ature along the terminal block is con- thermally bonded to its respective juncstant, you could use a single sensor, ther-Edn021114di30331
tion.
Heather
mally bonded to the block. If a linear
The
design in Figure 1 uses a multitemperature gradient exists along the ter- channel, high-resolution ADC to measminal block, you could use a sensor at ure the thermocouple voltage and the reboth ends of the block. This method al- sistance of two RTDs at the cold junction.
lows for interpolation of the temperature Using the data from the ADC, a microat various points along the block. If the processor determines the temperature of
November 28, 2002 | edn 93
design
ideas
the cold junction, the amount of coldjunction compensation to apply, and,

then, the temperature of the hot junction.
Performing the cold-junction compensation in software allows users to use
mixed thermocouple types and is both
flexible and universal. The AD7708 digitizes the signals from the thermocouple
and from two three-wire RTD sensors,
which measure the cold-junction temperature at both ends of the terminal
block. The terminal block is local, so you
can ignore the wiring resistance between
the ADC and the RTDs. It is easier to obtain precision resistors and voltage references than precision current sources, so
the RTDs and the 470 precision resistor, RPREC, connect in series, and all obtain
excitation from the same current source,
IEXC. The voltage generated across RPREC
determines the exact value of the excitation current. Hence, the current source
need not be particularly stable over temperature. ROFF offsets input pair AIN7/AIN8 by more than 100 mV from
ground. ROFF is also a 470 resistor but
need not be a precision resistor. The
ADR421s 2.5V precision voltage reference directly drives the REFIN1()/REFIN1() inputs.
With IEXC set to 300 A and the internal programmable-gain amplifier set to
the 40-mV full-scale range, the ADC produces usable resolution of 2.4 V. With
100 RTDs, it accurately resolves a
0.02C temperature differential between
the two ends of the terminal block and
has an absolute accuracy of 0.01C for
either measurement. The differential
analog input pair, AIN1/AIN2, of the
AD7708 reads an input voltage equal to
IEXC(RTD 1), where RTD 1 represents the
resistance of the first RTD element. A sec-
ond differential input pair, AIN5/AIN6,

reads an input voltage equal to IEXC(RTD
2), where RTD 2 represents the resistance
of the second RTD element. One source
of error pertains to the RTDs themselves.
The most common type is the 100 platinum RTD with a resistance-temperature
coefficient of 0.00385//C. It is available in accuracy-tolerance classes A and
B (or DIN A and DIN B), which specify
both the initial accuracy at 0C and the
interchangeability over the operating
range. The Class A specification is
(0.150.002|t|), where t is the specified
interchangeability temperature; the Class
B specification is (0.30.005|t|).
It is possible to buy two Class A, 100
platinum RTDs from the same manufacturer and find that one is reading 0.2C
high at 25C and the other is reading
0.2C low at 25C. Thus, you have an apparent 0.4C difference before you even
commission t. One way to combat this
initial error is to request a matched pair
of RTDs from the manufacturer. Leading
RTD manufacturer Heraeus Sensor
(www.4hcd.com) makes available PRTDs
(platinum RTDs) that Heraeus sorts into
tolerance groups with maximum t
0.05C over 0 to 100C. A lower cost
solution and one that uses off-the-shelf
RTDs is to use the offset and gain registers on the AD7708 ADC to calibrate each
of the RTD errors. Noise pickup may be
an issue if the hot junction of the thermocouple is a long distance from the
measurement electronics. The very-highinput-impedance buffer inside the
AD7708 allows the addition of lowpass
filters R1-C1 and R2-C2 to the AIN3/AIN4
inputs to attenuate high-frequency-noise
pickup in the wiring.
A single-ended analog-input channel,
AIN9, and three burnout resistors, RB1

through RB3, provide both thermocouple
open-circuit, or burnout, and short-circuit-detection functions by forcing the dc
bias levels of AIN3/AIN4 away from their
normal operating levels of approximately 2.5V. A thermocouple short-circuit
fault condition from either Metal A or
Metal B to ground pulls the voltage across
RB3 to 0V. A thermocouple open-circuit
fault condition on either Metal A or Metal B causes the voltage across RB3 to move
to 1.66V. You can program either of these
voltage levels (converted by AIN9) to
raise an alarm signal.
A more difficult fault condition to detect is the condition in which the two
thermocouple wires short only to each
other. In this case, a new thermocouple
junction forms at the location of the
short circuit, and the junction behaves
like a normal thermocouple. The only
way to detect this fault condition is to
implement a rate-of-change alarm in
software. If the two wires short together
at the exit of the thermo-well, the new
thermocouple junction may well experience much the same temperature that
the original thermocouple junction experienced. This fault condition is difficult to spot. However, if the short circuit
occurs a long distance from the original
thermocouple junction, then this new
junction may be at a different temperature from that of the original junction
and produces a rate of change that channel does not normally see. You can use
this abnormal change to flag an alarm
condition.
Solve low-frequency-cutoff problems

in capacitive sensors
Julius Foit, Czech Technical University, Prague, Czech Republic
ne of the first problems a capacitive-sensor analog designer
must face is the low-frequency cutoff. Theoretically, you must fulfill just one
simple requirement: a sufficiently large
input resistance of the preamplifiers first

stage. In practice, however, many problems lurk behind the seemingly straightforward design rules. First, the preamplifiers active device must have a defined dc
operating point. Using field-effect devices renders the dc input current of the
first active device (a JFET or a MOSFET)
so low that you can neglect it in most cases. On the other hand, the circuit must
www.edn.com
design
ideas
have some dc-path-creating resistor to

SENSOR Q1
present the required dc potential to the
C1
input electrode. Assuming that a typical
CABLE
miniature capacitive sensor, such as a
R1
SHIELD
high-quality capacitive microphone, has
a small capacitance of 20 to 50 pF, for example, the resistor value to obFigure 1
tain a cutoff frequency as high as
C2
8
50 Hz would be on the order of 10 to
VOUT = VDD
109. Resistors with such high values are
R2
difficult to find in SMD formats, are expensive, have poor accuracy and stability, and are large and noisy. Moreover, fur- The JFET in this circuit effectively multiplies the
ther difficulties appear when the value of R1.
capacitive sensor requires an external poSENSOR Q1
larization voltage. Such a polarization
C1
voltage may have a value of 100V or
CABLE
more. This voltage must connect to the
R1
SHIELD
sensor via a separate circuit, and it sometimes creates problems if the need to have
at least one side of the sensor
Figure 2
grounded emerges. And, as in all
C2
similar cases, the preamplifier should be
VOUT = VDD
as close to the sensor as possible. It should
Q2
consume minimal space, need few connecting leads, and produce as little heat
as possible. The circuit in Figure 1 rep- The second JFET, Q2, in this circuit replaces R2
resents one possible approach to meeting in the circuit of Figure 1.
these challenges.
The circuit uses electronic multiplication of the gate resistor, R1, value via pos
itive feedback through the source-folSENSOR
lower action of JFET Q1. The multi+
VOUT
C2
plication factor is gfsR2. (Note: gfs is the
Q1
100 F
33 pF
real part of the differential forward transR3
R1
1k
fer admittance in common-source con10M
nection.) Assuming a typical value of
R2
C133 pF, reasonable values of
100k
F
i
g
u
r
e
3
R110 M and R210 k and
assuming a conservative value of gfs5
mA/V (typical in the JFET type BF245B An operational amplifier provides yet another
at VGS0V and VDS15V), you obtain means to achieve high impedance for capacitive
sensors.
the following low-frequency cutoff:
1
fL =
= 9.6 Hz .
and VGS0. Thus, you provide a polariz2C1R1g fs R 2
ing voltage of 100V to the sensor. Other
With this method, notwithstanding advantages of the circuit are obvious at
the extremely small sensor capacitance the first glance: Only two elements of the
and conservative values of all other com- circuit, R1 and Q1, must be connected diponents, you obtain a respectable cutoff rectly at the sensors location. Both these
frequency. At the same time, to get the re- components are readily available, and
quired high polarizing voltage to the sen- they are physically small (usually considsor while keeping one side connected di- erably smaller than the sensor itself), so
rectly to ground, you can use a supply they pose no space problems. The heat
voltage, VDDVDSVPOLARIZING115V, the JFET produces150 mWis low
where VPOLARIZINGIDR2, and ID is the enough to be negligible in most applicaJFETs drain current at the selected VDS tions. The circuit needs only three wires
for connection, and one of them can also

serve as cable shielding. The connecting
cable can be quite long; its maximum
length is limited primarily by its capacitance, which determines the upper cutoff
frequency. In most applications, the upper cutoff frequency of the sensor itself is
low enough to permit a rather long cable.
The only minor disadvantage of the circuit lies in its total power consumption,
mostly dissipated in R2 (1W in this case).
In cases not requiring a high polarizing voltage, the value of R2 might become
too small to obtain a sufficiently large
multiplication factor, . Then, another
JFET, Q2, can replace R2 (Figure 2). This
JFET has its gate shorted to its source and
operates as a constant-current source.
You can calculate the R1 multiplication
factor from the same formula as for
Figure 1, with the R2 value replaced by
the value of ROUTQ21/gDSQ2. You must
lower the overall supply voltage, VDD, accordingly to provide the same operating
point for Q1. The processing stage, the
amplifying stage, or both immediately
following the preamplifier should not
have too small a differential input resistance; this resistance appears in parallel
with R2 or Q2, so it reduces the multiplication factor, . A noninverting input of
an operational amplifier easily satisfies
this requirement.
Choosing a less common but still reasonable value of R1100 M pushes the
low-frequency cutoff below 1 Hz with no
other changes in the circuit necessary.
The dynamic range of the preamplifier is
respectable. The maximum permissible
positive swing of the input voltage is
equal to the forward threshold voltage of
Q1s gate-insulating pn junction multiplied by the same multiplication factor,
, as the input resistance. In the circuit
of Figure 1, with the cited component
values, at a 300K temperature and
VCC115V, the permissible swing exceeds
5V peak. The JFET alone determines the
noise figure; hence, it is rather low. The
maximum permissible negative swing of
the input voltage is usually much larger.
A second possible solution of the low-frequency-cutoff problem in capacitive-sensor analog preamplifiers appears in the
case of electret-biased sensors. These sensors need no external polarizing voltage,
thus simplifying the overall power-supwww.edn.com
design
ideas
ply design. In these cases, you can achieve

an even larger multiplication factor of
the biasing resistance by applying unity
positive voltage feedback in an operational amplifier (Figure 3).
To obtain a full unity positive voltage
feedback in the circuit, the value of R3
should be zero. A minor complication
exists, however. To prevent dc instability
(bistable flip-flop behavior), a dc path in
the positive-feedback circuit must not
exist. C2 is the dc-blocking device. Unfortunately, C2 introduces another pole
in the transfer function of the circuit. To
render its effects negligible, C2 would
need an uncomfortably large value. As
long as you are prepared to sacrifice a bit
of the otherwise extremely large R1-value multiplication factor, (theoretically
equal to the open-loop voltage gain of
the operational amplifier, or 105, typically), you can use a C2 value several orders of magnitude smaller under the
condition that doing so introduces some
additional damping into the circuit by
means of a nonzero value of R3. R2 is nec-
essary to provide a correct dc potential

(quiescent operating-point conditions)
for the noninverting input of the operational amplifier.
A detailed analysis of the circuit in
terms of stability and its response to harmonic and step-signal drive is rather
lengthy. You can base the analysis on the
rules of general active-filter theory, or
you can simulate the circuit behavior
with any of the common simulation
tools, such as Spice. By an intelligent
choice of passive-component values, you
can easily control the circuits behavior
in terms of low-frequency cutoff. Thus,
you can obtain a maximally flat frequency response or a maximally flat
transient response or set a predetermined amount of overshoot in the response to a step input, for example. The
operational amplifier must have quiescent dc currents of both inputs as low as
possible. CMOS op amps are best in this
respect. The circuit of Figure 3 requires
a somewhat larger space for components
in the immediate vicinity of the sensor,
as well as four instead of three connecting leads. On the other hand, it is less
sensitive to external loads than are the
circuits in figures 1 or 2.
The op amp in Figure 3 is a TS271,
a CMOS op amp from STMicroelectronics (www.stmicroelectronics.com).
The low-frequency cutoff is at 7 Hz, and
the step-response overshoot is 0%. With
larger values of C2 and smaller values of
R3, you can easily achieve a low-frequency cutoff of 0.1 Hz or lower. The circuit
in Figure 3 is well-suited for micropower applications. Using a micropower
CMOS operational amplifier, you can reliably obtain 10 years of unattended operation with standard passive components and just a single coin-sized lithium
cell as the power source. The properties
of the operational amplifier fully determine the high frequency cutoff and dynamic range of the circuit in Figure 3.

Noninverting op-amp circuit has simple gain formula

Jos Carrasco and Ausias Garrigs, Universidad Miguel Hernndez, Elche, Spain
R
R2
R2
VIN
2
2
asic textbooks describe invertVIN
R1
R1
ing and noninverting amplifiers

_
R3
R3
VOUT
based on operational amVOUT
+
F
i
g
u
r
e
1
plifiers. These amplifiers have
+
R4
R3
different gain equations. Whereas in the
R3
R4
inverting configuration, the gain is the raFigure 2
tio of the feedback and input resistances, in the noninverting amplifier, the gain This noninverting amplifier has a simple, proThis noninverting amplifier has a gain formula
ratio has an added term. In some designs portional gain formula.
identical to that of an inverting amplifier.
and for the sake of simplicity, it would be
desirable to have a simple, proportional plifier, the circuit in Figure 2 fills the bill. or R2, whichever is smaller, and the gain
gain ratio (for gains above and below Its close-approximation gain formula is error the approximation gives is less than
5%. For an exact computation, the error
unity) for both inverting and noninvert- VOUTVIN(R2/R1).
However, in the circuit of Figure 2, is equal to R4/2
(1/R11/R2). For the seing amplifiers. The noninverting amplifier in Figure 1 has a simple, proportion- some restrictions in the choice of R4 arise. lection of R4, you should take into acal formula for the gain: VOUT The accuracy of the gain formula of the count the fact that most op-amp ICs have
VIN(R2/2R1). This gain is proportional to circuit depends on R4s being much low- maximum output currents of approxia resistor ratio and can take any value. R3 er in value than R1 or R2. Nevertheless, mately 20 mA.
has no influence on the gain. If you need comparing the exact expression for the
a noninverting amplifier with a gain ra- gain and the above approximation proves Is this the best Design Idea in this
tio identical to that of an inverting am- that R4 is 10 times lower in value than R1 issue? Select at www.edn.com.
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design
ideas
Controller IC and one-shot

form resonant controller
C Rajan, Centre for Advanced Technology, Indore, India
esonant power supplies are pop2N6013
ular because of high effiVCC
Figure 1
R2
ciency, low noise, and comR1
7
8
R
T
pactness. You can implement a resonant
VREF
VCC
Q1
Q2
2 VFB
buck or boost converter using a single
MAIN
IC1
R3
switch. The regulation of the output in
6
MOSFET
UC3842 OUT
1
such a converter derives from using a
COMP
0
3
ISENSE
FEEDBACK
constant on or off time and a variable fre4
RT/CT
R4
quency. The UC1864 controller IC (Texas
C1
GND
C2
RSENSE
5
Instruments, www.ti.com) meets all the
CT
requirements for a single-switch quaVREF
0
siresonant converter. But you also can
16
achieve this performance with the inexVDD
CX 1
C3 R5
pensive and popular UC3842 currentIC2A
CD4098B
6
2
mode controller in conjunction with a
Q
RXCX
4
one-shot multivibrator. This circuit gives
TR
7
R6
Q
5
the desired current-mode operation
TR
RESET
along with constant off-time, variableD1
5V
frequency operation. Figure 1 shows the
3
controller circuit, configured as a resonant flyback converter for high-voltage
generation. For the implementation of This resonant flyback configuration uses only a controller IC and a one-shot multivibrator.
this function, the current-mode controller should have 100% duty cycle; thus,
you can use the UC3842 or 3843.
Figure 2
This circuit uses the 3842. The
operation of the circuit is as follows.
The output of IC1, the UC3842, is in a
high state until the internal current-sense
comparator goes high, and then the output of the IC switches low. As the output
voltage goes low, IC2, the negative-edgetriggered one-shot CD4098B, triggers,
and it generates a pulse. The pulse duration is a function of the values of R5 and
C3, and this time interval is the constant
off-time of the UC3842. The Q output of These waveforms typify operation at low (traces C and D) and high (traces A and B) duty cycles.
the one-shot sinks the base current of
transistor Q1 during this period, and so way that the output voltage goes low be- cy). You can see that the off-time is fixed
the transistor conducts. This action adds fore the ramp voltage reaches its upper- in both conditions, and only the frea 5V pulse to the ramp at the RT/CT pin threshold level. If not, a glitch can occur quency changes to achieve the desired
(Pin 4). This voltage remains at 5V until in the output, arising from the time conduty cycle. The voltage at the RT/CT pin
the pulse ends and Q goes high. As it goes stant consisting of the output resistance gives a clear view of how the circuit modhigh, Q1 turns off, but the voltage across of Q2 and CT. Figure 2 shows the voltage ifies the ramp. This control circuit genCT is 5V, which is higher than the upper waveforms at low and high duty cycles. erates a 2-kV, 5-mA dc power supply usthreshold of the RT/CT pin, so the inter- Traces D and C show the output and ing a resonant flyback scheme, and it
nal circuitry pulls the pins voltage to RT/CT-pin voltages, respectively, at a low performs well.
zero, and a fresh ramp and a fresh cycle duty cycle and, hence, high frequency.
start.
Traces B and A show the same voltages, Is this the best Design Idea in this
You must select RT and CT in such a but at a higher duty cycle (low frequen- issue? Select at www.edn.com.
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design
ideas
Circuit folds back current during fault conditions

Martin Galinski, Micrel Semiconductor, San Jose, CA
ou can use monolithic linear regu- big problem arises when you examine require 10 D-Pack-size MOSFETs to
lators at currents lower than 5A for power dissipation in a sustained short maintain an acceptable junction tempermost applications. Most manufac- circuit. Then, the pass element must ac- ature. Thus, you must overdesign the
turers of these devices integrate current- commodate 20W of dissipation. It would supply, increasing cost and board size to
limiting and thermal shutdown to prevent damage during fault
Figure 2
conditions. For currents greater
than 5A, most linear supplies use controllers that allow the user to select the
pass element to handle different current
requirements. Although these linear controllers may offer current limiting, they
generally dont support thermal shutdown. This limitation requires the design
to handle the maximum power dissipation and maintain an acceptable junction
temperature in the pass element. For example, assume that you use a 1.8V, 8A linear supply operating from a 2.5V rail. The
power dissipation in the pass element
equals (VINVOUT)
IOUT(2.5V1.8V)
8A5.6W. Over the specified temperature range, the pass element must be
able to dissipate this amount of power
and have a junction temperature lower
than the maximum allowable for that device. This approach probably requires
three to four D-Pack-size MOSFETS. A The circuit in Figure 1 cycles current in the event of a fault condition.
Q1
SUB15POI-02
R1
10 m
R2
90.9
IC3
LM40411.2
Figure 1
C1
R5
3k
VIN
R3
1k
EN
C2
0.1 F
R4
1k
R6
330k
IC2
MIC7221BM5
ISENSE
GATE
IC1
MIC51591.8BM5
FB
C4
100 F
CERAMIC
GND
C3
0.1 F
This circuit provides foldback current-limiting, thus reducing the power-handling requirements of the pass element.
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design
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survive a possible fault condition. The

circuit in Figure 1 solves the problem of
current-limit power dissipation.
The circuit uses a separate control loop
that folds back the currents during a
fault condition without involving the
problems of linear-foldback current limiting. Linear foldback can have problems
tripping the current limit during start-up
and returning to full load after a fault
condition disappears. These problems
tend to lock up the regulator in currentlimited state. IC3 provides a high-side reference below the supply voltage and
places this voltage on the inverting pin of
comparator IC2. The comparator compares this reference signal with the MOSFET side of R1. When the current exceeds
the current-limit threshold, IC2s inverting-input voltage is greater than that of
the noninverting input. This state causes the comparator to pull the currentsense pin on IC1 low. You can calculate
the current-limit threshold as follows:
R2
VIN VIC 3
R 2 + R 3
CURRENT LIMIT =
;
R1
CURRENT LIMIT
90.9
2.51.225
90.91000
;
10 m
CURRENT LIMIT10.207 A .
When the current-sense pin drops 50

mV below the input, the regulator turns
the output off. This action then causes
the current to go to zero, creating a high
condition on the output of the comparator. The comparator has an open collector; therefore, the ISENSE pin charges at
the RC charge rate of R6 and C3. The output of the regulator remains off, drawing no current, until the ISENSE pin charges
to 50 mV below VIN. At this point, the
output turns on. R5 and C2 provide a delay before re-engaging the current limit.
This delay prevents the current required

for charging the output capacitors from
prematurely tripping the current limit. It
also gives the circuit time to stabilize and
to determine whether it can deliver the
output current that the load demands. If
the load is still too heavy, the current limit re-engages. Figure 2 is an oscilloscope
photo of this circuit in operation. This
cycling of current, although periodically
delivering maximum current, integrates
over time into a lower average current.
You can calculate average current as a
ratio of on- to off-time: IAVGIPK
(TON/TOFF)10.2A
(2msec/17msec)
1.2A. This reduced average current
equates to a reduction in power dissipation. At 1.2A, the power dissipation decreases to 3W.

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design
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DPPs program key parameters of bandpass filter

he three-amplifier implementation of the state-variable filter
Figure 1
in Figure 1 provides for sec5V
0.1 F
ond-order bandpass, highpass, and low8
1 DPP1 INC
pass responses. The strength of the cir2
5
R3
U/D
cuit, however, is in the bandpass response
10k
6
3
7
_ 9
CS
(VOUT/VIN), in which its easy to achieve
1%
8
R5
4
IC
2
high gain (G) and high Q. These two
10k
10
+
characteristics are important in applications in which selectivity is a key paramR4
2.5V
eter in the filter. The application value of
10k
the circuit becomes even greater when
1%
DPPs (digitally programmable potentiometers) control and vary the bandDPP2
5V
C1
5
pass filters center frequency, f0, and pass5V
2 _
0.1
F
4
band gain, G. The independent control
6 _
6
3
1
IC1
of a bandpass filters parameters is a
DPP3
7
INC
R5
3
+
IC3
VOUT
11
10k
rarity among traditional filter-circuit
U/D
5 +
techniques.
CS
For the filter, IC1 functions as a sum2.5V
ming amplifier, and IC2 and IC3 function
VIN
as integrators. Three potentiometers,
NOTES:
10k
DPP1, DPP2, AND DPP3 ARE CAT5113s.
DPP1, DPP2, and DPP3, program the
R1
R2
IC1, IC2, AND IC3 ARE 1/4 LMC6484.
pR (1-p)R
center frequency and passband gain of
the filter. The 100-tap Catalyst potentiometers, DPP1 and DPP2, are electron- Using digitally programmable potentiometers, you can control a passband filters center frequency
and gain.
DPPs program key parameters
of bandpass filter............................................97
Encoder and PC make
complete motor-control system..................98
Use PSpice for behavioral
modeling of VCOs ......................................102
Circuit delivers high voltage
swing from lower supplies ........................104
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ically ganged to program the frequency,

f0, and DPP3 programs the gain, G. The
center frequency is f01/(2R5C1)
1/(2pRC1), and the gain is GR2/R1
(1p)/p, where p represents the relative
position of the wiper from one end (0) of
the potentiometer to the other end (1).
R represents the DPPs end-to-end resistance. The gain and Q are related by
Q(1G)/2. The increment/decrement
interface of the CAT5113 DPP allows for
real-time, closed-loop applications, in
which you can continuously vary the cen-
ter frequency of the filter to track an input signal or to accommodate a systemlevel requirement. For the values shown,
the center frequency varies from less than
200 Hz to more than 6 kHz with gain values as high as 25.

December 12, 2002 | edn 97
design
ideas
Encoder and PC make

complete motor-control system
his Design Idea combines a simple
ISA-bus-resident interface circuit; a
garden-variety PC; a high-resolution
optical shaft encoder; and a PWM-controlled, 0.05-hp, brushed, permanentmagnet dc motor to make a high-precision and high-power motion-control
system. The system sequences the precise
rotation of an evacuated steel bell jar several feet in diameter, such as those used
in molecular-beam spectroscopy (Figure
1). Although the speed of the intermittent rotation of the jar isnt fast, the sys-
B9
tem needs large torques to overcome the

friction of a large O-ring seal that is subjected to tens of tons of atmospheric
pressure. Moving against this drag requires a heavy-duty drive that energizes
a 48W (24V, 2A) motor. A different
choice of MOSFET in Figure 1 would allow the system to handle even heavier
loads.
The quadrature-output, incremental
optical shaft encoder that this Design
Idea uses is popular in high-performance, bidirectional, rotation-sensing ap-
plications. Incremental encoders provide

an inexpensive and reliable means for
digital readout of bidirectional mechanical motion. Theyre usable to 10,000 rpm
and higher. However, the interface logic
they need can sometimes be problematic. Such logic typically includes at least
one 16-bit or longer bidirectional counter. Several handy peripheral chips, such
as the 8253, 8254, and 9511, are available
that implement unidirectional counting,
but bidirectional counter chips are comparatively scarce. ASICs can provide the
12
+ 100 F
16V
Figure 1
B30
5V
B1
B10
B31
DB6
DB5
DB4
DB3
A3
A4
A5
A6
7
6
5
4
3
DB2
DB1
DB0
A7
A8
A9
A22
A23
A11
A25
A26
B13
LS645
11
12
13
14
15
16
17
4
5
6
7
8
I0R
A7
C1
15
A 10k
G0 11
10 13 12 11
10
68
D2
IN4148
C2
D0
0.0047 F
CS
12V
RD WR
23
8
C1
0.0047 F
Q2
2N4403
6 9
8
13
10
1
13
2
3
5V
8
Z746-ND
4A
17 AND 18
MOTOR
OUTPUT
6
5
8
K1
12
2
11
10
MOTOR
DC SUPPLY
(~24V AT 2A)
D3
SR504
R1
2.7M
D1
1N4148
3,4
A9
5
A8
AEN
A6
12
A5
11
5
I0W
6
5A
40V
Q3
IRFZ20-ND
Q1
2N4401
2
3
TO
ENCODER
0.1 F
O0
A1 A0
5
4
3
12V
C0
82C54
6 AND 7
+
5
9
1
Q4
2N4403
1,4
A28
4
2
4.7k
100 pF
5V
A29
B 10k
G1 14
9
21 20 19 22
A4
A1
A0
4.7k
HC14
2
3
G2 16
1 D7
2
3
18
2
19
B14
A24
18
5V
C2=CCW
C1=CW
7.2 MHz
9
A
8
DB7
5V
28 kHz
C2
A2
A27
A30
A31
12
+ 330 F AT
6.3V
+0.1
Q9
Q1
B3
B29
11
MCT4040
10
14.3 MHz
A2
A3
12 D
1
2
C11
HCT74 Q1
11, 3
9
D2
13, 10
5V
This block of bidirectional logic and a PC comprise a complete motion-control system.
98 edn | December 12, 2002
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design
ideas
needed functions, and hard-wired

or programmable logic is a viable,
though component-count-intensive, option.
Unfortunately, none of these options is ideal from either a cost or a
pc-board-area standpoint. This alternative combines the industrystandard 82C54 unidirectional
counter-timer peripheral chip with
simple software to create a convenient interface between quadrature
encoders and the ISA PC I/O bus.
Thus, you can easily digitize bidirectional motion. The trick is to use
two of the three unidirectional
counters in the 82C54one for
each encoder-rotation direction.
Reference 1 describes the logic involved in detail. This Design Idea
expands upon the material in Reference 1 by closing the motioncontrol loop with an 8-bit-resolution, digital PWM motor-speedcontrol circuit. The PWM modulator consists of counter-timer 0
(CT0) of the 82C54, operating in
retriggerable-one-shot mode and
controlling the Q1-Q2 drivers for
the MOSFET, Q3.
The HC4040 provides a 7.2MHz clock to CT0 and triggers CT0
at 28 kHz (7.2 MHz/256). The result is a variable-duty-factor PWM
waveform at CT0s output (O0). Q1
and Q2 buffer and boost the waveform to 12V p-p and apply the
boosted waveform to the gate of
MOSFET Q3. The MOSFET then
modulates the 24V-dc motor-supply rail
and thus generates a more-than-95%-efficient, programmable motor-speed control. The motors armature inductance
combines with flyback diode D3 to filter
the high-frequency components of the
28-kHz PWM waveform and to extract
the dc component. Minimizing the time
the MOSFET spends between full-off
and -on states is critical to the efficiency
of this PWM circuit, as in all power-handling topologies.
The Q1-Q2 driver circuit achieves fast
MOSFET on/off transition times of approximately 10 nsec, as well as minimal
12V supply-power consumption. The
driver circuit achieves these two goals by
avoiding saturation-induced cross-con-
LISTING 1MBASIC DEMO PROGRAM FOR MOTION CONTROL
duction of Q1 and Q2. The circuit avoids

the cross-conduction by taking advantage of the fact that Q3s gate presents an
almost entirely capacitive load to the Q1Q2 pair. Therefore, although currents of
approximately 100 mA into Q3s gate are
necessary during on/off transitions to
ensure efficiency-promoting speed, the
drive requirement drops to zero between
transitions. The circuit takes advantage
of the situation by using capacitive drive
to Q1 and Q2. Coupling capacitors C1 and
C2 deliver robust base drive during rise
and fall edges but virtually no drive after
the transitions. Hence, the circuit avoids
cross-conduction of the bipolar transistors. Meanwhile, R1 provides just a trickle of dc bias to Q1, so that Q3 and, there-
fore, the motor stays off before the programming of the 82C54, regardless of
whatever arbitrary state the IC may assume after power-up. Q4 is a pnp transistor that controls the direction-reversing relay, K1. Listing 1 is an MBasic demo
program for the motion-control system.
You can download the software from the
www.ednmag.com.
Reference
1. Woodward, Steve, Unidirectional
counters accumulate bidirectional pulses, EDN, April 11, 2002, pg 72.
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design
ideas
Use PSpice for behavioral modeling of VCOs

Dobromir Dobrev, Jet Electronics, Sofia, Bulgaria
Spice, a member of the Spice family for PC users, is becoming
Figure 1
a standard tool for analog
and mixed analog-digital simulation.
Many analog designers are familiar with
the software of Design Center, Design
Lab, and OrCad (www.orcad.com)
PSpice and use the software in their
everyday lives. This Design Idea should
be helpful to those who design and simulate PLL systems at a behavioral level. A
basic PLL system comprises a phase detector, a loop filter, and a VCO (voltagecontrolled oscillator), connected in a
negative-feedback loop. The phase detector produces a voltage that, after lowpass-filtering by the loop filter, becomes This PSpice simulation example symbolically represents the transfer function for a VCO.
an error voltage, VE, applied to the control input of the VCO to set the anFigure 2
gular frequency, (). When VE0,
the VCO oscillates at some initial frequency, 0, called the frequency offset or
free-running frequency. The output
frequency of the VCO is:
(t)0GVCOVE(t).
(1)
Here,
G VCO =
d
df
= 2
= 2g VCO , (2)
dVE
dVE
where GVCO is the VCOs voltage-to-radian frequency gain in radians per second
per volt and gVCO is the VCOs voltage-tofrequency gain in hertz per volt. Consider a sinusoidal voltage with amplitude
VAMPL, argument (t), and dc offset VOFF:
V(t) = VAMPL sin((t)) + VOFF .
(3)
The argument (t) is the time integral of

the angular frequency:
A simulation example shows the results for the behavioral model of a VCO.
(t) = (t)dt + (0) .
(4)
Assuming is constant and substituting

(t) in V(t) yields the popular form:
V(t) = VAMPL sin(t + (0)) + VOFF . (5)
If is not constant, the general form is:
V(t) = VAMPL sin ((t)dt + (0)
VVCO (t) = VAMPL

(6)
+ VOFF .
Replacing (t) with Equation 1 and considering (0)0, you obtain the VCOs
transfer function:
sin ( 0 + G VCO VE (t))dt
+ VOFF = VAMPL sin
(7)
(0t + GVCO VE (t)dt ) + VOFF .

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design
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Equation 7 is the heart of the VCOs

time-analysis modeling. Thus, you can
easily perform VCO behavioral modeling, using the ABM1 part from the Analog Behavioral Modeling Symbol Library
abm.slb (abm.olb in OrCad Capture).
You can simply write the formula for the
transfer function, adapted for PSpice.
Figure 1 shows the PSpice representation
of the process. Figure 2 shows a simulation example, in which VE is the VCOs
input voltage, and V(OUT1) is the output
voltage. Because most phase detectors

(types I, II, and III) use a digital input signal, you can easily obtain a digital VCOoutput waveform using the conditional
expression above the lower box in Figure
1. The simulated curve is V(OUT2), also
shown in Figure 2. Finally, for loop-gain
evaluation in ac analysis, you simply
model the VCO in the frequency domain
in an ideal integrating unit, using the
Laplace form TVCO(s)GVCO/s. Most obvious behavioral VCO models are based
on a real circuit concept. Thus, they comprise many elementsfor example, controllable sources, capacitors, and others.
Hence, the models are complicated. This
modeling is simple without involving superfluous computation resources.

Circuit delivers high voltage swing

from lower supplies
Bruce Carter and Ron Shakery, Texas Instruments, Dallas, TX
he need for higher voltage swings
in applications such as test-andmeasurement instruments is constantly increasing, but the power supplies
impose limitations on the operational
amplifier rails make the high-voltage
need a challenge for designers. How do
you deliver high-voltage swings to a load
without increasing the voltage levels of
the power supplies of the operational
amplifier? In other words, for example,
how can you produce a 16V or greater
signal swing across the load using only
15V power supplies? The circuit in Figure 1 uses a fully differential amplifier to
offer an answer to this problem. Fully differential amplifiers enable you to deliver
an output-voltage swing beyond the rails
into the load. One of the common problems in working with operational amplifiers is the limit that the power-supply
rails impose. The standard since the days
of analog computers has been 15V.
Analog computers are gone, but their
legacy remains in the power-supply voltages. These voltages find widespread use
in transducer interfaces and applications
in which voltage swing and dynamic
range are of primary importance.
This 15V supply voltage notwithstanding, applications exist that require a

higher swing range beyond the powersupply limits. Typical 15V operational
amplifiers are seldom optimized for railto-rail operation, and their useful output-voltage range may be only 24 to 26V.
Many audio consoles use older technology 741 op amps with 18, 20, and
even 22V power supplies to obtain
more voltage swing and, therefore, more
dynamic range from their systems in light
of this limitation. The op amps in these
systems often run hot and have heat
sinks. The advent of fully differential op
amps has given designers a better way to
extend the output-swing range. Fully differential operational amplifiers 40 to 50
years ago were tube or discrete-transistor
units. They have recently re-emerged as a
way to interface to fully differential A/D
converters and applications in which the
load needs differential drive for better
swing range or to reduce the noise effects
in the systems.
The outputs of fully differential op
amps have a characteristic that makes
them useful for doubling the swing. The
two outputs are 180 out of phase: When
one output swings positive, the other

swings negative and vice versa. The net effect is similar to what happens in a
bridged amplifier: The effective outputvoltage range doubles. The price of doubling this output-voltage swing is that you
can no longer connect the output load to
ground. Designers of automotive audio
amplifiers are familiar with this concept:
Audio-power bridged amplifiers have a
fully differential output. Many installers
have learned the hard way that the minus
speaker connection cannot connect to
ground. When the output voltage doubles, power quadruples. This feature is
useful for audio power amplifiers in a limited-power-supply-voltage application.
To illustrate the advantage of fully differential outputs, assume that a fully differential op amp has a voltage-rail limitation of 13V when operated from
15V supplies. The absolute- maximum
output range of each output is 13V. But
when the top output is at 13V, the bottom
output is 13V: (13V)(13V)26V.
When the top output is 13V, the bottom output is 13V. As a result, the output voltage is (13V)(13V)26V.
Therefore, the output-voltage range is
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design
ideas
15V
Figure 1
SENSE AMPLIFIER
R6A
R7A
15V
R5A
R2A
R4A
R1A
R3A
VIN
15V
WIRE
LOSSES
VOCM
LOAD
+
15V
R1B
R2B
R3B
R5B
R4B
R6B
15V
R7B
+
SENSE AMPLIFIER
15V
Similar to a bridged audio amplifier, this op-amp circuit delivers output-voltage swings to the load
beyond the span of the power supplies.
26V, which enables the output to swing

from 26V to 26V, resulting in a doubled voltage-swing range. Fully differential op-amp designs require that the two
feedback loops be symmetrical; the components in the top and the bottom sections must be the same. In Figure 1s
schematic, the components in the top
feedback path are labeled A, and those
in the bottom are labeled B. When this
design references a designator, the comment applies to both paths A and B.
The gain of the overall circuit is
VOUT/VINR3/R1. The location of the
load is often at the end of a balanced line.
You cannot discount the effect of the
wire; it affects the amplitude across the
load, reducing the expected gain of the
system. The sense lines help compensate
for the voltage drop across the lines, resulting in the delivery of the targeted
voltage to the load. The two sense amplifiers in the schematic are each com-
posed of an op amp and resistors R4

through R7. R2 acts as a summing component, adding small-signal amplitude
equal to the voltage drop of the wire back
into the input, boosting the op amps
output such that the expected gain appears at the load. If you make R4 though
R7 equal in value to R1, then it is easy to
calculate R2 : It takes the same value as R3.
If R4 through R7 cannot be equal to R1,
then R3 should be proportional to R2.You
should be aware that the resistors in the
sense amplifiers change the load characteristics. For 600 audio-distribution
systems, this fact is less of a problem than
it is in 50 systems. You should be aware,
however, of the output-drive characteristics of your operational amplifiers, if
you wish to deliver the exact desired voltage swing to the load.
www.edn.com
design
ideas
En
fa
Ha
Frequency comparator has status output

he original application for the
5V
circuit in Figure 1 was to check
Figure 1
the number of revolutions of
5V
5V
an engine with only one LED as an indi100 nF
cator. The measurement of the number
IC1
D1
22k
74HC4046 16
LED
of revolutions usually involves sensors
J1
4
470
with a frequency output proportional to
VCOUT VDD
1
3
CIN
the number of revolutions. The circuit
Q2
1 mF
14
2
BSS89
compares the frequency output of such
SIN
INPUT
P1
100k
13
SIGNAL
P2
6
15
a sensor with a lower and upper limit and
C1A
5V
P3
1 mF
7
1
C1B
gives a visual result, using one LED. If the
PP
11
C1
C2
10
R1
DEMO
frequency is below the lower limit, the
10 nF
12
2.2 mF
R2
5V
9
22k
VCOIN
5
LED remains unlit. If the frequency is be100k
INH
R1
R2
GND
100k
tween the limits, the LED blinks at a con100k
8
J2
stant rate, and if the speed is higher than
R4
1
the upper limit, the LED stays permaR3 100k
100k
nently lit. Although a microcontroller can
Q1
GND
BC548
do this job, it is sometimes better to use
100k
an analog circuitfor example, if the
frequency you want to check is too high
for a simple controller. The circuit in Figure 1 uses one standard, inexpensive IC, This analog frequency comparator uses an LED to indicate upper and lower frequency limits.
and you need not write any software. It
is also less costly than a comparable mi- age regulator. The chip contains an oscil- VCO increases to a second higher value
lator, a phase comparator, and one am- determined by R2 and R3, and the VCO
crocontroller-based circuit.
The main part is IC1, a 74HC4046 PLL plifier for the input signal. The input sig- generates the frequency for the high-limchip. With a 12V supply, you can also use nal connects to the input of the phase it switching point. If the frequency of the
the CD4046 without an additional volt- comparator with its integrated ac ampli- input signal is between these two limits,
fier. The circuit compares this amplified the phase comparator generates a recsignal with the VCO frequency. This fre- tangular waveform. The feedback capacFrequency comparator
quency is adjustable, using C1, R1, and the itor, C2 determines the frequency of this
has status output............................................58
voltage on Pin 9. If the frequency of the waveform. With a value of 2.2 mF for C2,
Envelope follower combines
input signal is lower than that of the you can achieve a frequency of approxifast response, low ripple ..............................59
VCO, the output of the phase compara- mately 1 Hz. This frequency is the blinktor (Pin 13) is low. In this case, Q2 is off, ing rate for the LED. If the frequency of
Positive regulator makes
Q1 is on, and the LED is off, indicating the input signal increases to a point highnegative dc/dc converter..............................60
low frequency. Resistors R2, R3, and R4 er than the upper VCO frequency value,
Multiplexer amplifiers form large,
determine the voltage on Pin 9 and the the phase comparator output stays high,
multiplane-multiplexer structures ..............62
lower frequency limit switching point. If and the LED turns on permanently. With
Circuit provides watchdog
the frequency of the input signal increas- the values shown in Figure 1, the lower
for microcontrollers........................................66
es and reaches the value of the VCOs fre- and upper frequency limits are 3.81 and
quency, the phase comparators output 7.35 kHz, respectively.
Circuit translates I2C voltages......................66
switches high.
This high-level output turns Q2 on and Is this the best Design Idea in this
Q1 off. With Q1 off, the voltage of the issue? Select at www.edn.com.
www.edn.com
volta
such
filter
betw
idly
amo
you
the o
badl
shap
mod
caus
prod
as a
lems
attac
and
sicia
any
expo
abru
is s
metr
Figure
C
0.1
This e
www
alue
VCO
limf the
mits,
recpacthis
r C2,
oxiinkcy of
ighlue,
high,
With
ower
and
Envelope follower combines

fast response, low ripple
Harry Bissell, Royal Oak, MI
nvelope followers extract am- zero crossings. The fundamental fre- follow the rapid decay of a muted string.
plitude information from complex quency range is typically from approxi- The design in Figure 1 features fast attack
audio waveforms. The resulting dc mately 80 Hz to 1.5 kHz. Previous circuits and low ripple with minimal filtering,
voltage often drives nonlinear stages, have used a full-wave bridge and a large and it can follow a rapid decrease in sigsuch as voltage-controlled amplifiers or averaging filter. A filter time constant suf- nal (mute).
filters. You must make a careful trade-off ficient to reduce ripple makes the circuit
The circuit uses three identical peakbetween the speed of response to a rap- unable to follow rapid changes in ampli- hold circuits in parallel that reset in a
idly changing input signal and the tude. Peak-detecting circuits can follow round-robin fashion. The circuit applies
amount of ripple in the dc output that the rapid attack and provide low ripple the input signal to all three stages simulyou can tolerate. If the system is too slow, during the exponential decay but cannot taneously. As each stage resets in turn, the
the output has low ripple but
two remaining stages still hold
badly distorts the envelope
the last peak voltage. Diodes
shape. If its too fast, ripple can
select the highest held voltage
modulate the nonlinear stages,
at the output of each peakcausing audible distortion
hold stage. A small RC filter
products. Audio sources, such
smoothes the step response as
as a guitar, pose special probthe peak-hold circuits reset, so
lems. The instrument has an
a lower output voltage results.
attack of a few milliseconds
To ensure that one of the deand a long decay time. The mutectors holds the highest peak
sician may mute the strings at
value for the entire input pe52.6
39.4
65.8
78.9
26.3
13.1
any time, causing the normal
riod, the reset clock period is
TIME (mSEC)
exponential decay to terminate
slightly longer than one-half
abruptly. The waveform
the period of the lowest input
Waveforms of typical circuit operation show the
Figure 2
is sometimes unsymfrequency. Figure 2 illustrates
improvement over full-wave average and peak-detecting
metrical and may have multiple circuits with similar time constants.
typical circuit operation and
Figure 1
PEAK DETECT 1
100k
IC2
TL072
3 +
12V
AUDIO IN
R1
10k
2 1
C1
0.1 mF
C2
R2
10k
8
IC1
TL072
5 +
4
R3
10k
7
1N4148
1N4148
2N3904
Q1
0.001 mF
1N4148
CK
1k
2
CKEN 1
15 RST 2 4
7
3
12V
4017
16
VDD
13
PEAK DETECT 2
D1
R5
100
112V
0.001 mF
14
6 1
1N4148
IC1
3 TL072
+
4584
1N4148
R4
100k
C3
0.1 mF
1N4148
PEAK DETECT 3
1N4148
VSS
this
.com
This envelope detector provides the seemingly contradictory features of fast response and low ripple.
www.edn.com
December 26, 2002 | edn 59
design
ideas
shows the improvement over full-wave

average and peak-detecting circuits with
similar time constants. CMOS Schmitt
inverter IC1 forms the master reset clock,
and C1 and R1 produce the desired period. CMOS counter IC2 is a ring counter
that provides the sequential reset pulses.
The peak-hold circuit is a classic configuration with the addition of the reset circuit. R2 and C2 differentiate the rising
edge of the reset pulse; this edge drives
the base of Q1. Series resistor R3 prevents
excessive op-amp current while Q1 is
conducting. The filter network compris-
ing R4, R5, C3, and D1 provides minimal

filtering to reduce the step changes in the
output during unusually fast decay times.

Positive regulator makes negative dc/dc converter

Keith Szolusha, Linear Technology Corp, Milpitas, CA
ower-supply designers can choose
1VIN
CMDSH-3
from a plethora of available
15V
Figure 1
positive buck regulators that
LT1765EFE
can also serve as negative boost dc/dc
fSW=1.25 MHz
0.22 mF
converters. Some buck regulators have a
CDRH5D28-2R5
BOOST
negative-feedback reference voltage exVIN
VSW
pressly for this purpose, but ICs that have
SYNC IC
FB
1
positive-reference feedback voltages far
CIN
SHDN
outnumber these negative-feedback reg10 mF
D4
6.3V
VC
GND
ulators. You can take advantage of this
UPS120
22 mF
X5R
64.9k
10k
16V
greater variety of devices by using a posX5R
4700 pF
itive buck switch-mode regulator to creCERAMIC
100 pF
6.8k
ate an excellent negative boost converter. All you need are a few small mod19V AT 1A
ifications to the typical buck-converter
configuration. Figure 1a shows a 25V1VOUT
(a)
input to 29-output, 1.4A negative boost
3.3V AT 2.2A
converter using the LT1765EFE positiveVOUT
CMDSH-3
buck-converter, switch-mode regulator.
This IC accepts 3 to 25V input, uses a
12V
LT1765EFE
1.2V feedback voltage, and has an interVIN
fSW=1.25 MHz
0.22 mF
nal 3A power switch. The 1.25-MHz
CDRH5D28-2R5
BOOST
switching frequency of the LT1765EFE
VIN
VSW
helps reduce the size of the inductor and
SYNC IC
FB
1
input and output capacitors. Figure 1b
17.5k
10 mF
SHDN
shows a typical positive-buck-converter
6.3V
B220A
V
C
GND
10 mF
application for the LT1765EFE: a 12V-inX5R
10k
16V
CERAMIC
put to 3.3V-output, 2.2A dc/dc convertX5R
1800 pF
CERAMIC
er. Figure 2 shows an efficiency plot for
100 pF
2.4k
the regulator in Figure 1a.
In Figure 1a, the ground pin of the IC
(b)
connects to the negative voltage VOUT.
This connection makes the negativeboost-converter configuration provide a The LT1765EFE positive buck converter can make a negative boost converter (a) or a positive buck
positive voltage at the FB pin with respect converter (b).
to the ground pin of the IC. In this topology, the maximum input voltage rating minimum input-voltage rating that is age can have an initial state of 0V.
of the IC has to be greater than the mag- less than the magnitude of the input voltNote that the maximum output curnitude of output voltage for the negative age, to ensure that the circuit turns on rent for the negative boost converter in
boost converter. The IC must also have a upon power-up, because the output volt- Figure 1a is much lower than the maxi-
www.edn.com
design
ideas
90
mum output current of the positive buck
converter in Figure 1b, even
85
Figure 2
though they use the same switch80
mode-regulator IC. The buck-converter
IC in both circuits has an internal powEFFICIENCY 75
er switch with a switch current rating of
(%)
3A. You choose the inductor based on
70
maximum output current, peak switch
65
current, and desired ripple current. First
calculate the duty cycle (DC) and then
60
calculate either the ripple current, IPP,
400
600
800
1000
1200
1400
0
200
based on the chosen inductor, L, or the
OUTPUT CURRENT (mA)
inductor value based on the desired ripple current. It is generally good practice Efficiency of the negative boost converter in Figure 1a is as high as 85% and typically greater than
to choose the inductor value so that the 80%.
peak-to-peak ripple current is approximately 40% of the input current. These mum allowable input current given the ISWMAX3ESRCOUT. Figures 1a and 1b
calculations are approximate and ignore ripple current: IOUTMAX5(ISWMAX2IPP/2) show the high-di/dt switching paths of
the effect of switch, inductor, and Schot- 3(VIN3h)/ VOUT. As in a typical boost the negative boost and positive buck
tky-diode power losses. You calculate as converter, the input capacitor in the neg- dc/dc converters.You must keep this loop
ative boost topology has low ripple cur- as small as possible by minimizing trace
follows:
DC5(VOUT2VIN)VOUT; IIN~(VOUT3IOUT)/ rent, and the output capacitor has high lengths to minimize trace inductance.
(VIN3h), where h is the overall efficien- discontinuous ripple current. The size of The discontinuous currents in this path
cy. IPP5IIN340%; IPP5(DC3VIN)/(f3L), the output capacitor is typically larger create high di/dt values. Any trace inwhere f is the switching frequency; and than that of the input capacitor to han- ductance in this loop results in voltage
L5(DC3VIN)/(f3IPP).
dle the greater rms ripple current:
spikes that can render a circuit noisy or
Maximum inductor current, ILMAX, is
ICINRMS5IPP/=12, and ICOUTRMS5 uncontrollable. For this reason, circuit
equal to the peak switch current in this =(12DC)3(IIN21IPP2/12).
layout can be just as important as comThe output capacitors ESR has a direct ponent selection. Note that the layout of
configuration. The IC has a maximum
switch current, ISWMAX, of 3A, so the max- effect on the output-voltage ripple of the a negative boost regulator differs from
imum inductor current must remain dc/dc converter. Choosing higher fre- that of a positive buck regulator, even
below 3A. To keep switch current below quency switch-mode regulators reduces though they use the same IC.
the maximum, you might need more the need for excessive rms ripple-current
inductance to keep the ripple current rating. Regardless, a low-ESR output
low enough. (ILMAX5ISWMAX5IIN1IPP/2.) capacitor, such as a ceramic, can miniMaximum output current, IOUTMAX, is an mize the output-voltage ripple of the Is this the best Design Idea in this
approximation derived from the maxi- negative boost converter: DVOUTPP5 issue? Select at www.edn.com.
Multiplexer amplifiers form

large, multiplane-multiplexer structures
Bill Stutz, Maxim Integrated Products, Sunnyvale, CA
he variety of video sources available to a home-video-switching system has grown from a few composite inputs to many multisignal sources.
These sources include cable, HDTV, satellite dishes, VCR, DVD, video games in
broadcast, and multi-PC or graphic
KVM (keyboard-video-mouse) applications. Each requires an N3M-to-1 multiplexer, in which M is the number of
sources and N is the number of channels
that make up the signal. As an example,
16 RGB or Y, Pb, and Pr sources require
a 3316-to-1 multiplexer. Constructing
such a multiplexer is difficult, and programming the source selection requires

that you combine the individual 16-to-1
multiplexer control with the three channels (Table 1). You can configure a group
of analog multiplexers as a large, multiplane video multiplexer that easily selects
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design
ideas
multichannel video sources, such as YC,

RGB, and Y Pb Pr. The cited 3316-to-1
RED INPUT 16
multiplexer comprises six 8-to-1 multiplexers (Figure 1) controlled by a 4-bit
75
binary code for source selection.
(MAX4315 ICs include a 2V/V fixedgain output buffer.)
The only external circuitry required is
an SN7404 hex inverter for inverting the
shutdown signals and 75V source and
load resistors for implementing unity
gain when driving a back-terminated
load. Substituting a MAX4312
Figure 1
eight-channel video multiplexer
with variable-gain output buffer allows
variable gain and rejects input common(a)
mode voltages. The high bandwidth and
slew rate of these ICs make them ideal for
selecting standard video and high-defiGREEN INPUT 16
nition broadcast video, as well as graphics sources with UXGA and higher reso75
lutions for KVM applications. The design
requires no additional buffering, because
the ICs can directly drive 150V back-terminated coaxial cable to within less than
0.75V of the supply rails, using single or
dual supplies. Their 40-nsec switching
speed and 10-mV p-p glitch voltage allow, in addition to source selection, insertion of on-screen display, closed captioning, and teletext in broadcast and
graphics video.
MAX4315
75
15
75
8
MAX4315
1
A0
A1
A2
A3
MAX4315
75
75
8
MAX4315
1
A0
A1
A2
A3

MAX4315
BLUE INPUT 16
RGB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
A0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
A1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
A2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
A3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
GREEN OUTPUT
15
(b)
TABLE 1SOURCE-SELECTION
PROGRAMMING
RED OUTPUT
BLUE OUTPUT
75
75 15
75
8
(c)
INPUTS 9 TO 16
MAX4315
1
A0
A1
INPUTS 1 TO 8
A2
A3
This multiplane multiplexer selects any one of 16 input signals, each of which comprises red (a),
green (b), and blue (c) channels.
www.edn.com
design
ideas
Circuit provides watchdog for microcontrollers

VM Holla, Bangalore, India
When the control signal remains
he watchdog circuit in
2
RESET
in a high state, C2 begins dischargFigure 1 uses a single
IC
3
OUT
4093 1
ing. When the control signal
NAND Schmitt-trigger
5V
switches low, the Reset output goes
IC. The circuit is more costR
5
1N4148
1N4148 1k
high. The same scenario prevails
effective than dedicated, comIC
4
8
IC
10
6 4093
R
with C1 when the control signal remercially available watchdog
C
4093
9
5V
100k
RESET
10 mF
mains low. You can choose the valICs. The circuit generates an
OUT
1N4148
12
ues of R1, C1, R2, and C2 as a funcactive-high reset signal upon
11 1N4148 1k
IC
13 4093
tion of the watchdog-time
power-up and remains in a
OPTIONAL
C
S RESET
100k
10 mF
duration and the reset pulse width
low state as long as the control
SWITCH
required. With the values shown,
input receives pulses. WhenCONTROL
IN
the circuit is appropriate for
ever the pulsing at the control
MCS51-family microcontrollers.
input stops, whether
Figure 1
This watchdog-timer circuit is a cost-effective alternaThe duration of the watchdog
the circuit is in a high or
time is approximately 300 msec,
a low state, the circuit emits a tive to dedicated watchdog ICs.
reset signal. Upon power-up, both inputs both inputs of IC1D reach a high level, the and the reset pulse width is approxiof gate IC1C are low, forcing the Reset Reset output goes low, and Reset goes mately 10 msec.
output to switch high and the Reset to go high. As long as the control input receives
low. Thus, the outputs of both IC1B and pulses, the outputs of IC1B and IC1D deIC1D are high. The high outputs charge liver pulses. The pulses hold the input of Is this the best Design Idea in this
the capacitors in the circuit, and, when gate IC1C high and the Reset output low. issue? Select at www.edn.com.
1A
1B
1C
1D
Circuit translates I2C voltages

Peter Liu, Optron X, Allentown, PA
his Design Idea explores level3.3V
shifting an I2C bus from 5V/
5V
ground (positive domain) to
5V
SDA_P
ground/25V (negative domain). In
MICRODAC
multisupply systems, you sometimes
SCL_P
CONTROLLER
t
face a situation in which digital infor5V
mation stored in logic circuits running
0V
from 5V to ground needs conversion to
t
SDA_N
analog signals referenced to a negative
SHIFTER
SCL_N
DAC
supply. Converting from digital to
Figure 1
15.2V
analog in the positive domain and
15.2V
then level-shifting to reference the neg15.2V
ative rail introduces errors and results
DEVICE
DEVICE
in a large component count. A better
1
2
approach is to level-shift the digital
data lines and convert with negative15.2V
15.2V
referenced A/D converters. I2C is a bidi2
rectional system employing a two-wire In this typical I C configuration, the microcontroller is the master, and all the peripheral devices
bus: one clock line and one data line. are slaves.
Pullup resistors and open-collector outputs establish dominant-low signaling. the microcontroller is the master, and all a unique I2C address. The master always
Figure 1 shows a typical setup, in which the peripherals are slaves. Each device has generates the clock, but, depending on
www.edn.com
design
ideas
the desired direction of data flow, either

the master or the slave could be
Figure 2
the transmitter on the data line.
VDD
To understand the level-shifting procedure, consider the simple circuit in FigR1
ure 2. The circuit level-shifts the clock
4
10k
line unidirectionally. Q1 comes with a
R2
VDD
22k
10k
pnp, an npn, and four bias resistors, all in
5
0V
0V
6
IN
OUT
one small SOT-363 package. R1 provides
VEE
3
the necessary pullup function in the positive domain, and R2 does the same in the
22k
negative domain. The operation of the
circuit is straightforward. When VIN is set
Q1
1
MUN5312DW
to VDD, Q1 remains off, so VOUT50V (logic high). When VIN is set to 0V, Q1 is on,
VEE
so VOUT5VEE (logic low). This unidirectional circuit does not allow the master
to detect when the slave holds the clock This transistor arrangement level-shifts the data or clock signals from positive to negative levels.
low. Therefore, if you desire I2C clock-extension (wait-stating), you would need a
VDD
bidirectional level-shifting circuit.
4
The data line needs a bidirectional circuit. Even when the master is transmitR2
R1
IC1
10k
5.62k
ting, the master needs to detect when the
1
2
5
R4
R3
negative-domain slave pulls the data line
5.62k
10k
4
3
SDA_POS
low on every ninth bit to acknowledge
6
3 74VHC1066
the transmitted byte. Also, when inD1A
Q2
1
structed, the slave may need to transmit
D1B
MUN5312DW
4
data back to the master. In the slaveBAT54SDW
SDA_NEG
transmitter mode, the slave would have
BAT54SDW 3
1
VEE
to detect when the master pulls the data
line low on every ninth bit to acknowl4
5
edge the transmitted byte. Despite
Figure 3
IC2
R5
this added complexity, you can
3.92k
5
2
1
still accomplish the task with just five
4
3
SOT-363-size packages and five discrete
6
3 74VHC1G66
resistors (Figure 3). To see that the circuit
2
Q3
in Figure 3 is topologically the same as
MUN5312DW
the one in Figure 2, assume transmission
gates IC1 and IC2 are on and ignore the
VEE
1
lower half of the circuit for the moment.
With SDA_POS set to VDD, Q2 is off, R3
and R4 pull up to 0V, resulting in A bidirectional level shifter translates data and clock signals from positive levels to negative levels,
SDA_NEG50V (logic high). With and vice versa.
SDA_POS set to 0V, Q2 is on, so
to construct the return path so that it kHz clock rate. For 100-kHz operation, it
SDA_NEG~VEE (logic low).
Now, trace the return path from slave doesnt depend on resistors to set logic is best to use an MUN5311, which has 10to master. With SDA_NEG set to 0V (log- levels. Transmission gates IC1 and IC2 and kV internal resistors instead of 22 kV.
ic high), Q3 is off, and R1 pulls SDA_POS Schottky diodes D1A and D1B break the You can use the same bidirectional circuit
up to VDD. With SDA_NEG set to VEE positive feedback path that would other- in Figure 3 for the clock signal, to cover
(logic low), Q3 is on, and R1||R2 forms a wise result when either master or slave all the I2C modes of operation.
voltage divider with R5 to yield pulls SDA to a logic low. Note that, withSDA_POS~0V. You select R1, R2, and R5 out these components, Q2 and Q3 would
to yield VDD55V and VEE525.2V. If de- form a latch. The circuit in Figure 3 eas- Is this the best Design Idea in this
sired, you could use additional transistors ily meets I2C timing requirements at a 50- issue? Select at www.edn.com.
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design

Edited by Bill Travis

Log amp uses capacitor-charging law

Log amp uses capacitorcharging law....................................................71

OUTPUT VOLTAGE (V)

Extend the timing capabilities of a PC ......72

Improved amplifier drives

INPUT VOLTAGE (V)

The circuit of Figure 1 produces a distinct logarithmic output.

January 10, 2002 | edn 71

with the applied voltage VIN.

TABLE 1OUTPUT VERSUS INPUT VOLTAGE

Extend the timing capabilities of a PC

72 edn | January 10, 2002

ic levels. If the timing signal is present at

account of the overhead of byte overflow.

Is this the best Design Idea in this

LISTING 1ZERO-POWER PHOTOGATE-ASSEMBLY PROGRAM

74 edn | January 10, 2002

Optocoupler simplifies power-line monitoring

76 edn | January 10, 2002

supply for the isolated block provides 5V

78 edn | January 10, 2002

Improved amplifier drives differential-input ADCs

80 edn | January 10, 2002

Circuit forms dc-motor switch with brake

82 edn | January 10, 2002

Edited by Bill Travis

Autoreferencing circuit nulls out sensor errors

Publish your Design Idea in EDN. See the

January 2 4, 2002 | edn 85

Low-power keypad consumes only 100 nA

interrupt on rising or falling edges, and

86 edn | January 2 4, 2002

lates to a worst-case maximum delay of

Time-tag impulses with zero-crossing circuit

88 edn | January 2 4, 2002

first half of IC2, an HC4538 resettable monostable multivibrator.

TABLE 1MEASUREMENT RESULTS AT 1 kHz AND WITH 20 mV RMS OF NOISE

90 edn | January 2 4, 2002

Circuit provides reference for multiple ADCs

matching among the converters.

racy. The gain of an ADC is in effect the

92 edn | January 2 4, 2002

dB lower (2156 dBFS), a 2V reference requires an extremely low noise level of 33

SINGLE EXTERNAL REFERENCE

94 edn | January 2 4, 2002

quired for precision-ADC operation.

96 edn | January 2 4, 2002

resistances between them. The load is 4

Is this the best Design Idea in this

Edited by Bill Travis

Motor-control scheme yields

system. The position depends on a set of

Motor-control scheme yields

Activating only one control input (for

Q1, Q2: 2N2222, 2N3904...

February 7, 2002 | edn 99

through Q6 are all high.

where ILOADmeasured current in amperes, VTHRESHcomparator threshold

Substituting sj and rearranging the real and imaginary