CISE 204 Digital System Design Lab Manual PDF
CISE 204 Digital System Design Lab Manual PDF
CISE 204 Digital System Design Lab Manual PDF
This manual helps to understand basic elements of CISE 204 and its
implementation.
Page 2
TABLE OF CONTENTS
Page 3
(c) Oscilloscope
(d) Multimeter
Figure L1.1: Instruments
Page 4
Page 5
Page 6
Page 7
Page 8
Voltage Reading
Page 9
Measured Values
Pulse width
Period
Amplitude
Table 1-2
Page 10
Table 1-3
Group Members:
(1) ______________________________________
(2) ______________________________________
(3) ______________________________________
(4) ______________________________________
10
Page 11
LAB 2: TTL Logic & Voltage switching characteristics of basic logic gates
Procedure:
1. Find the connection diagram for the 7400 quad 2-input NAND gate in the
manufacturer's specification sheet. Note that there are four gates on each of
these ICs.
2. Apply VCC and ground to the appropriate pins.
3. Then test one of the NAND gates by connecting all possible combinations of
inputs, as listed in Table 2-1.
4. Apply logic 1 through a series 1.0 W resistor and a logic 0 by connecting
directly to ground.
5. Show the logic output (1 or 0) as well as the measured output voltage in
Table 2-1.
6. Use the DMM to measure the output voltage.
11
Page 12
LAB 2: TTL Logic & Voltage switching characteristics of basic logic gates
Table 2-1
Exercise 2:
In this experiment, you will test the switching characteristics of the Hex Inverter.
Procedure:
1. Find the connection diagram for the 7404 Hex Inverter in the manufacturer's
specification sheet. Note that there are five inverters on each of these ICs.
2. Apply VCC and ground to the appropriate pins. Then test Hex Inverter gates
by applying the different voltage inputs Vin as highlighted in the Table 2-2.
3. Measure and note the Vout for different values of Vin in Table 2-2. Use the
DMM to measure the output voltage.
4. Start with small step and increase the step size if output voltage is not
changing significantly.
5. Repeat the experiment with different values of VCC = 4.8 V and VCC = 5.2 V.
12
Page 13
LAB 2: TTL Logic & Voltage switching characteristics of basic logic gates
Complete the following table for inverter IC 7404.
Vin
Vout
Vcc=5.0V
Vcc=4.8V
Vcc=5.2V
0.1
0.2
.
.
5.5
Table 2-1
Find from the data collected the following for the TTL hex Inverter:
1.
2.
3.
4.
13
Page 14
LAB 2: TTL Logic & Voltage switching characteristics of basic logic gates
Group Members:
(1) ______________________________________
(2) ______________________________________
(3) ______________________________________
(4) ______________________________________
14
Page 15
The decimal numbers range from 0,1,2,3,4,5,6 and 7. Let the decimal number inputs
be denoted as follows
where
and
,
Boolean expression relating the output, Y, and the input, A is obtained from the
truth table. There are 8 inputs and 3 outputs. At a given instant, only one input, Ai,
may be activated: two or more inputs may not be activated at the same time. To
appreciate this restriction, consider a computer keyboard. One can press only one
number key at any time instant and pressing simultaneously two or more number
keys are not allowed. Truth table for decimal to binary encoder is given in the Table
below. For values of decimal numbers from 0 to 7, corresponding binary numbers are
listed in Table 3-1.
15
Page 16
Output
A0
A1
A2
A3
A4
A5
A6
A7
a2
a1
a0
A1
A3
A5
A7
a0
16
Page 17
A2
A3
A6
A7
a1
A4
A5
A6
A7
a2
Input Decimal
A0
A1
Output Binary
A2
a2
A3
a1
A4
a0
A5
A6
A7
17
Page 18
Group Members:
(1) ______________________________________
(2) ______________________________________
(3) ______________________________________
(4) ______________________________________
18
Page 19
11
10
12
19
Page 20
Menu Bar
Design Toolbox
Component Toolbar
Standard Toolbar
5.
6.
7.
8.
View Toolbar
Simulation Toolbar
Main Toolbar
In Use List
9.
10.
11.
12.
Instruments Toolbar
Scroll Left/Right
Circuit Window
Spreadsheet View
The Menu Bar is where you find commands for all functions.
The Design Toolbox lets you navigate through the different types of files in
a project (schematics, PCBs, reports), view a schematics hierarchy and show
or hide different layers.
The Component toolbar contains buttons that let you select components
from the Multisim databases for placement in your schematic.
The Standard toolbar contains buttons for commonly-performed functions
such as Save, Print, Cut, and Paste.
The View toolbar contains buttons for modifying the way the screen is
displayed.
The Simulation toolbar contains buttons for starting, stopping, and other
simulation functions.
The Main toolbar contains buttons for common Multisim functions.
The In Use List contains a list of all components used in the design.
The Instruments toolbar contains buttons for each instrument.
The Circuit Window (or workspace) is where you build your circuit
designs.
The Spreadsheet View allows fast advanced viewing and editing of
parameters including component details such as footprints, RefDes,
attributes and design constraints. Users can change parameters for some or
all components in one step and perform a number of other functions.
20
Page 21
As mentioned, the model-1 system opens the outlet valve only when both sensors are
covered but, once opened; it remains open until both sensors are uncovered. This
concept requires knowing the current state of the output valve; hence in the design,
it is considered as both an output and an input to the logic. This idea is summarized
with the truth table shown as Table 1. Because the system is designed for TTL logic,
the outlet valve is opened with a LOW signal.
Inputs
Output
Action
LH
LL
VOUT
VOUT
Close valve.
21
Page 22
VOUT
LHLL
00
01
10
11
Figure 2: K-Map
Figure 3: Circuit for output valve of the model-1 tank
Notice that VOUT is returned to one of the inputs, which is the feedback referred to
previously. After constructing the circuit for the outlet valve of the model-1 tank
controller, it will be tested using switches for the inputs and an LED to represent
the outlet valve.
Multisim Tutorial:
This tutorial leads you through the circuit design flow, from schematic capture to
simulation. After following the steps outlined on the following pages, you will have
designed a circuit that you can use to implement the testing procedure without
building a circuit on Multisim.
Schematic Capture:
Opening and saving files
Complete the following step to launch Multisim:
1.
Complete the following steps to save the file with a new name:
Select FileSave As to display a standard Windows Save dialog.
2. Navigate to the location where you wish the file to reside, enter MyFirstCircuit
as the filename, and click the Save button.
1.
22
Page 23
guard against accidental loss of data, set up a timed auto-backup of the file in
the Save tab of the Preferences dialog box.
Complete the following step to open an existing file:
1.
Select FileOpen, navigate to the location where the file resides, highlight
the file, and click on the Open button.
To view files from earlier versions of Multisim, select the desired version in the
Files of Type drop-down in the Open dialog.
Tip:
Components Needed:
One LED
Two single-position DIP switches
Resistors: two 1.0 k4, one 330 S2
IC 7400,7404 as determined by the student
Placing components:
Complete the following steps to start placing components:
1.
2.
Tip: Once
Note: When
23
Page 24
Reference Designators (for example, U1, U2) are assigned in the order the
components are placed. If you place components in a different order than in the
original circuit, the numbering will differ. This will not affect the operation of the
circuit in any way.
Tip:
24
Page 25
You can also control the flow of the wire by clicking on points as you move the
mouse. Each click fixes the wire to that point. Finish wiring the circuit as
shown below.
Simulation:
Simulating your circuits with Multisim catches errors early in the design flow,
saving time and money. You can simulate the circuit by pressing either F5
function button or by navigating to file menu >>Simulate>>Run or by clicking the
green play or run button in the simulation toolbar.
Testing Procedure:
The test begins with both switches closed, meaning the level inputs are both LOW.
As the tank fills, LL is covered, so it will open and changes to a HIGH level. The
LED, representing the valve, remains OFF. Later, LH is covered, so it is opened and
changes to a HIGH level. This causes the LED to turn ON. At this point, closing the
HIGH level switch will have no effect on the LED as it remains ON until LL is again
covered, represented by a LOW.
25
Page 26
Group Members:
(1) ______________________________________
(2) ______________________________________
(3) ______________________________________
(4) ______________________________________
26
Page 27
MAN74A
MAN72A
27
Page 28
Procedure:
28
Page 29
Apply the 4-bit BCD digits through switch and observe the decimal display from 0 to
9. Inputs 1010 through 1111 have no meaning in BCD.
Results:
(1) Show your simulation and the circuit to me, or the lab assistant.
Evaluator signatures:______________ (simulation) ________________ (experiment)
29
Page 30
30
Page 31
IC type 7483 is a four-bit binary parallel adder. The four bit binary input numbers
are A1 through A4, and B1 through B4. The four-bit sum is obtained from S1
through S4. C0 is the input carry and C4 the output carry.
Two binary numbers can be subtracted by taking the 2s complement of the
subtrahend and adding it to the minuend. The 2s complement can be obtained by
taking the 1s complement and adding 1. To perform A-B, the complement of B is
taken and added to the four bits of A, and 1 is added from the input carry. As shown
in figure below, four XOR gates complement the bits of B when the mode select M=1,
and leaves the bits of B unchanged when M=0. Thus, when the mode select M is
equal to 1, the input carry C0 is equal to 1, and the sum output is A plus the 2s
CISE 204 Digital System Design
31
Page 32
C0
C4
9+5
9+15
9-5
5-9
9+9
9-9
32
Page 33
LAB 7: JK Flop-flop
LAB 7: JK FLOP-FLOP
Objective:
To learn to use flip-flops in digital circuits
Materials needed:
7476A dual JK flip-flop (Qty=1)
390 resistors (Qty=3), 1k resistor (Qty=4)
LEDs Red, Green, Yellow (Qty=1 each)
4-position DIP switch (Qty=1)
Theory:
The JK flip-flop is the most versatile of the three basic flip-flops (D, SR). All
applications for flip-flops can be accomplished with either the D or JK flip-flop. The
clocked SR is seldom used; it is used mostly as an internal component of the
integrated circuit.
JK flip-flops are available as either edge or pulse triggered devices. The older 7476 is
a level triggered flip-flop. The 74LS76A is edge-triggered on the HIGH to LOW
transition of the clock.
Procedure:
Build the circuit given below on the circuit board, and take different observations.
33
Page 34
LAB 7: JK Flop-flop
Data and Observations:
J
PRE
CLR
34
Page 35
LAB 7: JK Flop-flop
35
Page 36
36
Page 37
TASK1: (EXPERIMENT)
Design, built and test the circuit to use 555 as monostable multivibrator to generate
a pulse of width = 4 seconds (for the orange light) for the traffic signal when
triggered. Select appropriate values for R1 and C1.
A complete circuit is given below for your reference.
Design, built and test the circuit to use 555 as astable multivibrator to generate a
clock pulse of 10kHz to operate the traffic signal. Select appropriate values for R1,
R2 and C1.
37
Page 38
Check the output at pin3 on the Oscilloscope. On-time = _________ seconds, Dutycycle = _________ %
TASK 3: (SIMULATION)
Below is the circuit for traffic signal control. Simulate the circuit in Multi-Sim.
- Output 1 generates pulse of width = 25 seconds (Red and Green light) when
triggered. (monostable)
- Output 2 generates pulse of width = 4 seconds (Orange light) when triggered.
(monostable)
- Output 3 generates a clock of 10kHz. (astable)
38
Page 39
VCC
5V
X2
2.5 V
R1
2.2k
U1
2.5 V
R2
360
VCC
C1
10uF
RST
RST
DIS
DIS
THR
THR
TRI
TRI
CON
CON
OUT
GND
1
U2
VCC
LM555CM
C2
10uF
OUT
R3
1k
R4
1k
GND
1
U3
VCC
4
RST
DIS
THR
TRI
CON
OUT
GND
LM555CM
C3
47nF
LM555CM
J1
Key = A
J2
Key = B
Group Members:
(1) ______________________________________
(2) ______________________________________
(3) ______________________________________
(4) ______________________________________
39
Page 40
40
Page 41
Figure L9.1 (a) Pin connections for 74LS93A, (b) Connections for observations
Data and Observations:
Figure L9.2 Pin-outs for (Left) BCD-to-Seven segment decoder (7447/7448), (Right)
display (MAN72A, MAN74A), (Bottom) HDSP-5501 Common-Anode Seven-segment
Display
41
Page 42
42
Page 43
The basic cell in a static RAM is a flip-flop; it can be set or reset for writing
operations or tested without changing its state for read operations. In addition, the
RAM contains logic gates to control the read and write functions and decoding
circuitry. The RAM is organized as an array containing the memory cells in row and
CISE 204 Digital System Design
43
Page 44
(D1-D4), and four output lines (Y1-Y4) plus chip enable CE and a read/write control
line R / W . The output are shown with inverting bubbles, hence the complement of
the input data is present at the output when reading the data. The tri-state outputs
are in high impedance state when R / W line is LOW. To write the data, the address
____
is place on the address bus, data is place on the data bus, and CE and R / W are low
____
to WRITE. To read data, the address is placed on the address bus; CE is LOW and
R / W is HIGH.
Data and Observations
Write the five-digit postal code for KFUPM into the first five locations of memory,
then read those and display them on the seven-segment.
Table 1: Write operation
____
R /W
CE
A-D
D1-D4
CE
R /W
A-D
Seven-Segment
Output
44