Design of An Efficient FFT Processor For OFDM Systems: Haining Jiang, Hanwen Luo, Jifeng Tian and Wentao Song
Design of An Efficient FFT Processor For OFDM Systems: Haining Jiang, Hanwen Luo, Jifeng Tian and Wentao Song
Design of An Efficient FFT Processor For OFDM Systems: Haining Jiang, Hanwen Luo, Jifeng Tian and Wentao Song
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INTRODUCTION
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This work was supported in part by the National Natural Science Foundation of China under Grant No.60272079 and the National Hi-Tech Research & Development Program of China under Grant No. 2003AA123310.
Haining Jiang is with Shanghai Jiao Tong University, Shanghai, 200030,
China (e-mail: jhn2046@hotmail.com).
Hanwen Luo is with Shanghai Jiao Tong University, Shanghai, 200030,
China (e-mail: luo_hanwen@hotmail.com).
Jifeng Tian is with Shanghai Jiao Tong University, Shanghai, 200030,
China (e-mail: jeffhrb@hotmail.com).
Wentao Song is with Shanghai Jiao Tong University, Shanghai, 200030,
China (e-mail: radio_sjtu@hotmail.com).
Contributed Paper
Manuscript received July 17, 2005
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Datain_I
Datain_Q
ROM
RAM1
RAM2
Data
Address
Generation
Data Switch
Dataout_I
Dataout_Q
Block
Floatpoint
Unit
Butterfly
Twiddle
Address
Generation
RAM1
RAM2
Timing Control
Fig.2. Block diagram of an efficient FFT processor
WN = e
j 2 / N
(1)
A = ( A + C ) + ( B + D )
B = ( A C ) j ( B D ) WNp
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C = ( A + C ) ( B + D ) WN2 p
D = ( A C ) + j ( B D ) WN3 p
Fig.4.
(2)
At = ( A + C ) + ( B + D )
Bt = ( A C ) j ( B D)
Ct = ( A + C ) ( B + D)
Dt = ( A C ) + j ( B D )
(3)
and
A = At , B = Bt WNp ,
C = Ct WN2 p , D = Dt WN3 p
(4)
4-Point DFT
Twiddles
Multiplication
4-Point DFT
V.
The result of A
p = 4 m 1 l , m = 1, 2. , log 4 N ;
l=
l0 l0 l0
, l0 = 0,1, , N 4 m 1
(5)
repeat 4m 1 times
The results of B , C , D
Fig.3. Parallel butterfly architecture
B. Pipeline Architecture
To utilize the hardware resources more effectively, pipeline
architecture is introduced in the parallel butterfly algorithm.
The butterfly data-path has 4 pipeline stages, as shown in
From the equation above, we can see that the item p=0 comes
out regularly, and the bigger the value of m becomes, the more
item p=0 comes out. When m = log 4 N , all the values of p are
0, and the corresponding four twiddles equal to 1. That is,
there are no multiplications in the butterfly operation when
p=0. So, we can put this kind of butterfly operation, which
need no multiplications, parallel with other butterfly operations, which need multiplications. This kind of parallel architecture only introduces some simple addition operation, which
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VII. CONCLUSION
In this article, two butterfly algorithms -- parallel and dual
butterfly algorithms are proposed. The main idea of these two
algorithms is to make the operation without multiplications
(mainly contains addition operations) and the one with multiplications run in parallel. Because the area that addition units
occupy is very small, the FFT processor based on the two but-
terfly algorithms requires very small areas and has high processing speed. Performance evaluation and practical implementation proved that the FFT processor with these two novel algorithms is suitable for wireless LAN applications. Moreover,
it can also be used in other OFDM applications like digital
video broadcasting (DVB) and wireless MAN (802.16).
REFERENCES
[1]
[2]
[3]
[4]
[5]
[6]
BIOGRAPHIES
Haining Jiang received her B.S. and M.S. degrees in
electronic engineering from Harbin Engineering University in 1999 and 2002, respectively. She is currently
working toward the Ph.D. degree in electronic engineering at Shanghai Jiao Tong University, Shanghai, China.
Her research interests include B3G mobile communication systems and OFDM technique.
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Hanwen Luo was born in 1950. He received B.S. degree
from Shanghai Jiao Tong University in 1977, M.S. degree from Xidian University in 1992. He is currently a
professor of Department of Electronic Engineering,
Shanghai Jiao Tong University, China. His main research
interests are the 3G and 4G mobile communication systems and their key techniques for wireless transmission.
Jifeng Tian received his B.S. and M.S. degrees in electronic engineering from Harbin Engineering University
in 1999 and 2001, respectively. He is currently working
toward the Ph.D. degree in electronic engineering at
Shanghai Jiao Tong University, Shanghai, China. His
research interests include FPGA design for wireless
communications, B3G mobile communication systems
and OFDM technique.
Wentao Song was born in 1936. He received B.S. degree
from Shanghai Jiao Tong University in 1957. He is current the honorary chairman of Institute of Wireless Communication in Shanghai Jiao Tong University, the honorary director of Shanghai Institute of Electronics and fellow of China Institute of Communication. His research
areas include mobile communication and satellite communication.