Efficient Implementation Technique for OFDM on

FPGA
Ajinkya Desai Ashutosh Gupta Mayur Jambhale Vinit Chavan
(Dept. of Electronics and ( Dept. of Electronics and (Dept. of Electronics and (Dept. of Electronics and
Telecommunication Engineering Telecommunication Engineering Telecommunication Engineering Telecommunication Engineering)
KJSIEIT, Mumbai, India KJSIEIT, Mumbai, India KJSIEIT, Mumbai, India KJSIEIT, Mumbai, India
ajinkya.desai@somaiya.edu) ashutosh.gupta@somaiya.edu ) mayur.jambhale@somaiya.edu ) vinit.chavan@somaiya.edu )

Abstract—Orthogonal Frequency Division Multiplexing

(OFDM) is a multi-carrier system where data bits are encoded
to multiple sub-carriers, while being sent simultaneously. The
basic idea of OFDM is to divide the available spectrum in a
number of narrowband and low-rate orthogonal subcarriers, to
prevent interference between the closely carriers. This makes the
OFDM system resistant to multipath effect. Due to wide use of
OFDM, it is essential to develop a Digital Signal Processor (DSP)
to generate OFDM signals present in the various standards,
using a reconfigurable platform like Field Programmable Gate
Array (FPGA). The objective of the project is to design and
implement OFDM transmitter and receiver on FPGA hardware.
This project concentrates on developing custom single purpose
processor for OFDM with Fast Fourier Transform i.e., FFT
and Inverse Fast Fourier Transform i.e., IFFT in an efficient Fig. 1. Spectrum of OFDM showing overlapping subcarriers
way. The work also includes design of a mapping module
(Modulator)(64-QAM), serial to parallel, parallel to serial
converter and Vedic multiplier modules and interconnections
between them.Basically we are integrating different proposed
ideas into a single paper. The design uses 64-point FFT and
IFFT for the processing module, which indicate that the
processing block contain 64 inputs data. This design is simulated
on Zynq UltraScale+ FPGA Board(Part:xczu7ev-ffvf1517-1LV-i)
and tested and verified using Xilinx Vivado 2020 software.
Simulations on Python is also done to compare our result with
the results obtained from that of use of FPGA.
Keywords—OFDM,DFT,IDFT,FFT, IFFT, QAM, VHDL,FPGA

I. INTRODUCTION
Orthogonal Frequency Division Multiplexing is an innova-
tive modulation technique where data is transmitted over many Fig. 2. Block Diagram of FPGA
orthogonal subcarriers using Fourier Transform and is widely
used in multicarrier transmission. OFDM have advantages
such as high spectral efficiency, good performance in multipath representation of OFDM is made up of different orthogonal
channels. In single carrier system if signal gets fade or sinusoidal signals which are nothing but inverse Fourier trans-
interfered then entire link gets failed where as in multicarrier form. Thus, we implement blocks such as FFT/IFFT using
system only a small percentage of the subcarriers will be digital circuits for OFDM generation.
affected. This paper aims to increase the computation speed of FFT
FPGA are programmable semiconductor devices that are and IFFT blocks used in OFDM by incorporating it in FPGA
based around a matrix of logic blocks, connected through board with the use of efficient Vedic multipliers in them.
programmable interconnect. FPGA contains 3 main types of
II. LITERATURE SURVEY
resources: logic blocks, I/O(input-output) block for connect-
ing the pins of the package, and interconnection wires and In [1], C. Ebeling, C. Fisher, G. Xing, M. Shen & H. Liu
switches. For Xilinx’s FPGA, basic logic unit known as a proposed that The RaPiD(Reconfigurable pipelined data path)
configurable logic block (CLB). Exact numbers and features implementation has about six times the performance/cost of
vary from device to device, but every CLB consists of a 4 to a DSP implementation, while an ASIC(Application Specific
6 inputs RAM-based Look Up Tables (LUTs) to implement Integrated Circuit) has about six times the performance/cost
logic, some selection circuitry and flip flops. of RaPiD.
Mathematically modulating a waveform and adding it is equiv- “Future communication schemes tend to use the OFDM sys-
alent to taking an IFFT. This is because the time domain tem to provide high baud rates, less intercarrier interference,

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etc. MATLAB simulation of OFDM to see how the BER (Bit Since we are implementing 64-point FFT, N=64
error rate) of transmission varies versus the SNR” [2]. The n = log264 = 6
simulation results for the OFDM system with different M- So, number of stages(n)=6.
QAM schemes have been observed
In [3], proposed paper shows that the complex multiplier IV. RADIX-2 DECIMATION-IN-TIME FFT ALGORITHM
structure occupies a large chip area in VLSI implementation,
but Vedic techniques have helped in reducing the size and also The Radix or base indicates the decomposition size of
improving the speed of multipliers. FFT. Radix-2 is single-Radix FFT, for single Radix FFTs,
In [4], six different FFT architectures were designed and transform size must be power of Radix. Radix-2 indicates that
implemented on FPGA by comparing them. The implemented at initial stage of butterfly diagram, there will be grouping
FFT architectures were differing with respect to RAM memory of two samples. The radix-2 decimation-in-time algorithm
access, number of computational elements (butterflies), way rearranges the DFT equation into two parts: a sum over the
of processing of the input samples and memory storage even- numbered discrete-time indices n=[0,2,4,. . . ,N-2] and
requirements. a sum over the odd-numbered indices n=[1,3,5,. . . ,N-1].
Mathematical analysis reveal that all DFT frequency outputs
III. FAST FOURIER TRANSFORM AND INVERSE FAST X(k) can be computed as the sum of the outputs of two length-
FOURIER TRANSFORM (FFT/IFFT) (N/2) DFTs, of the even-indexed and odd-indexed discrete-
Discrete Time Fourier transform provides frequency domain time samples, respectively, where the odd-indexed DFT is
representation for a signal. FFT is an efficient algorithm to multiplied by a twiddle factor term.
calculate Discrete Fourier Transform (DFT) in a faster way In our project, there are 6 butterfly stages and 32 butter-
by incorporating use of butterfly diagrams. fly operations are computed in each stage to produce 64-
Discrete Fourier transform (DFT) of a signal is directly calcu- point FFT. In DIT-FFT, the input bits are in shuffled manner
late as: (decimation in x[n]) and the output is in original order (X (0),
2𝜋
−𝑗( )𝑘𝑛 X (1), X (3)). Radix-2 first computes the DFT of the even
X(k) =∑𝑁−1
𝑛=0 𝑥[𝑛]𝑒
𝑁 (1)
index inputs and odd index inputs and then combines two
results to produce the entire DFT sequence. The FFT operation
where k=0,1,...N-1 of butterfly diagram is shown in fig.3, and the powers of the
Here the phase factor or twiddle factor is defined by: twiddle factors used in butterflies are in natural order.
(WN )k = e−j(2π/N )k (2)

As a calculation method, decimation in time is used. This

means a remarkable savings over direct computation of the
DFT. For the decimation in time (DIT) N – Radix FFT is
defined as:

X(k) = ∑𝑁−1
𝑛=0 𝑥[𝑛](𝑊𝑁 )
𝑘𝑛
(3)
Fig. 3. Basic Butterfly Diagram

where k=0,1,...N-1
And Inverse Fast Fourier Transform (IFFT) is defined by: V. DIRECT FFT COMPUTATION ARCHITECTUR
In this implementation, the entire 64-point FFT architecture
is considered as one digital combinatorial logic block. In this
x[n] =1⁄𝑁 ∑𝑁−1
𝑛=0 𝑋(𝑘)(𝑊𝑁 )
−𝑘𝑛
(4) method, an optimized butterfly architecture with a single com-
plex multiplier, a single complex adder and a single complex
where n=0,1,...N-1 subtracter used. At the beginning of FFT computation, 64
FFT provides a fast calculation strategy by using symmetry complex input samples are read from the RAM memory, FFT
and periodicity properties of the phase factor to calculate is computed and results are written into the RAM memory at
DFT. Complexity of Radix 2 FFT is N.logN orO(N log N ) . end of FFT computation. This method needs lots of digital
The table shows the comparison of computations for IDFT logic such as multipliers, adders and subtracters. In this
and IFFT process: method, each butterfly is implemented as combinatorial block.
N =64 Complex Additions Complex Multiplications Then all the 192(32 X 6) 2-point butterflies are interconnected.
IDFT N (N − 1) = 4032 N 2 = 4096 The hard coded coefficient values are used for each butterfly
N
log2N = 192 digital logic. So, there is no need to store coefficients in the
IFFT Nlog2N = 384 2
ROM memory. The entire FFT computation is done in one
To find the number of stages mathematically for radix- single clock cycle. This method implements the flow graph
2 DIT FFT, the equation is n = log2N where N= number of shown in figure. In figure 4, the coefficient values for all the
samples, n= number of stages. six stages of FFT are also shown.

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 Fig. 5. Complex Vedic Twiddle Factor Multiplier

the sum and carry bits. The sum is the third corresponding
bit (s2) and the carry (c2) becomes the fourth bit of the final
product. This is repeated in similar manner until the MSB of
two numbers are multiplied. The final result is obtained by
combining all steps mentioned above.
The complex multiplier (16 x 16) is used in the algorithm
for multiplying the twiddle factor stored in ROM, which
is realized by Vedic multipliers, adder and subtractor. This
complex multiplier structure occupies large chip area in VLSI
implementation, but Vedic technique have helped in improving
the speed of multipliers. This Vedic multiplier is independent
on clock frequency because partial product and their sum is
calculated in parallel. In this paper we are presenting 16-
Fig. 4. The flow graph of 64-point FFT DIT butterfly bit multiplication and for that we require 2-bit, 4-bit, 8-
bit multiplier. This Vedic multiplier, is implemented from
the 8X8 multiplier. In fig.6, a0 to a15 are the bits of first
VI. COMPLEX MULTIPLIER DESIGN EMPLOYING VEDIC digit and b0 to b15 are the bits of second digit. For 16X16
CONCEPTS multiplier we require four 8X8 multiplier and three adders
after implementing as shown in Fig.6, we will get the result
Multiplication operation is most important function during
of 16X16 multiplier and the result obtained is of 32 bits.
computations but is a very complicated and expensive one.
Urdhva Tiryagbhyam Sutra which implies vertically and
crosswise, an interesting Indian Vedic Sutra is being utilized
for the multiplication in the FFT processor. Urdhva employs
a novel concept in which all partial products are calculated
in parallel and the delay is only due to the time taken for the
carry to propagate through the adders. The main advantage
of the Vedic Multiplication algorithm (Urdhva Tiryagbhyam
Sutra) is the fact that it can be very easily implemented in
FPGA due to its regularity and simplicity.

(Ar + jAi)(Br + jBi) = (ArBr − AiBi) + j(AiBr + ArBi)

Technique: In this sutra, firstly the least significant bits of

the numbers are multiplied which gives the least significant
bit of the final product s0 i.e., vertical Then, as the next step,
the LSB of the multiplier is multiplied with the next higher
bit of the multiplicand and is added with the product of
LSB of multiplicand and next higher bit of the multiplier i.e.
crosswise. The sum gives the second bit of the final product
(s1) and the carry (c1) is added with the partial product which Fig. 6. Vedic multiplier used in Twiddle factor Multiplier
is obtained by multiplying the most significant bits to give

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 VII. PROPOSED METHODOLOGY
In this project we aim to transmit voice signal. For this,
firstly we need ADC to convert Analog voice signals into
Digital domain. Then to generate OFDM symbols, a serial to
parallel converter is needed. The input data is in serial form
and need to converted into parallel format because the con-
stellation module requires parallel input for processing data.
These parallel converted data is mapped to appropriate symbol, Fig. 8. Simulation on Python
with the help of amplitude modulation mapping bank. Here
we are using 64-QAM (Quadrature Amplitude Modulation)
for modulation purpose. IFFT module is required to transform
the parallel symbols from frequency domain to time domain.
Now, the signals are added with a cyclic prefix and converted
into serial format, before being transmitted. For long distance
communication, transmission should be done serially as it is
economical.

Fig. 9. Transmitter Output of VHDL

output and is fed to Address which is the input of the 64 QAM

block. Address is a 6-bit parallel number as we are here using
the 64 QAM (26 = 64). Data out is the output of the 64
QAM and is fed to x one by one as it is the input of the 64
FFT where, x is 8-bit complex number i.e., 4-bits real and 4
bit imaginary. The output of FFT is denoted by y which is 32-
bit complex number i.e., 16 real and 16 imaginaries. This is
Fig. 7. Block diagram of OFDM system
further fed to cp which is the cyclic prefix.
At the receiver side, received data is in serial format. Since
FFT inputs is in parallel form, a module which converts
the data from serial to parallel form is required. On FPGA
board we are directly feeding the parallel output of IFFT with
cyclic prefix added to the FFT block after removing the cyclic
prefix added previously. The implemented Vedic multiplier
will be incorporated in the FFT and IFFT block. Output
from FFT is then demodulated using de-mapping module.
For de-modulation of the subcarrier using QAM modulation,
amplitude of the constellation and phase reference, on each
subcarrier are required. Output of de-modulating module (con-
stellation demapper) is converted back to serial format, through
parallel to serial converter, and then fed to DAC to get back Fig. 10. Receiver Output of VHDL
the transmitted data in analog form. Here FFT and IFFT used
are interchangeable as long as they are dual to each other. Fig.10 shows that the output of the Tx is used as input of
Rx i.e. cp which is of 32 bits which is 16 bits real and 16
VIII. SIMULATION RESULTS bits imaginary. The next block is IFFT where cyclic prefix
Fig.8 shows the simulation of OFDM on Python. The dif- is removed, the input of IFFT is x and the output is y. The
ference between Transmitted (TX) signal and Received (RX) output of IFFT consist of 8 bits which is 4 bits real and 4 bit
signal can be minimized by increasing SNR Value in the imaginary and this is fed for demodulation to DeQAM block
program. and the output of it is 6 bit of parallel data type po which is
Fig. 9 shows the simulation results of the OFDM transmitter further converted to serial output i.e. dout. Hence the given
where, si is the serial input of the transmitter, po is the parallel input is retrieved.

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 Device: xczu7ev-ffvf1517-1LV-i FFT OFDM Transmitter OFDM Receiver
No. of LUTs 12288 out of 230400(5.33%) 12396 out of 230400(5.38%) 48654 out of 230400(21.12%)
No.of CLB Registers 0 out of 460800(0.0%) 571 out of 460800(0.12%) 438 out 460800(0.10%)
No. of CARRY8 1536 out of 28800(5.33%) 1540 out of 28800(5.35%) 5694 out of 28800(19.77%)
No. of FF 0 out of 460800(0.0%) 27 out of 460800(0.01%) 54 out of 460800(0.01%)
No.of DSP 768 out of 1728(44.44%) 768 out of 1728(44.44%) 685 out of 1728(39.64%)
No. of BUFG 0 out of 544(0.0%) 2 out of 544(0.37%) 1 out of 544(0.18%)
No.of GLOBAL CLOCK BUFFERs 0 out of 544(0.0%) 2 out of 544(0.37%) 1 out of 544(0.18%)

The above table shows the device utilization report. [10] D. Matic, OFDM Synchronization and Wideband Power Measurements
Note that as we have used Direct FFT Architecture Radix-2 at 60 GHz for Future Wireless Broadband Multimedia Communications,
Ph.D. Thesis, Aalborg University, Denmark, September 2001.
FFT Algorithm it increases the resources required but makes [11] R.Durga Bhavani, D. Sudhakar “Design and Implementation of Inverse
the process faster. Direct FFT Architecture implies that FFT is Fast Fourier transform for OFDM” International Journal of Science and
calculated in 1 cycle which indicates the proposed method is in Engineering Applications Vol.2, Issue -7, 2013. pp. 155-158.
[12] Vijay Kumar Garg,Morgan Kaufmann Publications,”Wireless Commu-
accordance with that of [4] and also faster than the other three nications and Networking ”
architectures proposed in [4]. The obtained bit rate obtained at [13] Vinay BK, Sunil MP “FPGA Based Design Implementation of
the TX side is nearly 100 Mbps. Orthogonal Frequency Division Multiplexing ansceive Module using
VHDL”,International Journal of Advanced Research in Engineering and
Technology, Volume 4, Issue 6, September – October 2013,P.P 70-83.
IX. CONCLUSION
In this paper, custom single purpose FFT processor with
Radix-2 DIT-FFT algorithm based on direct architecture is
synthesized on Zynq UltraScale+ FPGA Board(Part:xczu7ev-
ffvf1517-1LV-i)FPGA Board for OFDM purpose. We had suc-
cessfully implemented various blocks of OFDM in VHDL and
the results obtained were compared with theoretical expected
results. FFT and IFFT implemented using Vedic concept for
multiplier was found to have a good performance and hardware
requirements and is therefore most suitable for use in OFDM.
Also, we used the concept of code reuse to implement IFFT
from FFT with minor changes. The speed of OFDM process
at the TX side was found in accordance with the operation
for the communication standard application requirements of
mobile WLAN (IEEE 802.11a), which uses OFDM modulated
wireless communication system.

REFERENCES
[1] ”Implementing an OFDM receiver on the RaPiD reconfigurable archi-
tecture”,C. Ebeling, C. Fisher, G. Xing, M. Shen ,H. Liu,Department of
Computer Science and Engineering, University of Washington, Seattle,
WA, USA ,December 2004.
[2] “Study Of Performance Parameters Effects On OFDM System ”, M.A.
Mohamed, A.S.Samarah, M.I.Fath Allah, Faculty of Engineering, Man-
soura University, Mansoura, Egypt, Delta Higher Institute for Engineer-
ing and Technology, Mansoura, Egypt, May 2012.
[3] ”FPGA Implementation of a Novel Efficient Vedic FFT/IFFT Processor
For OFDM”, Nisha John, Prof. Sadanandan G.K, Professor, Dept ECE,
Toc H Institute of Science and Technology, Cochin, Kerala, India,
September 2014.
[4] “Implementation of 64-point FFTs as a building block for OFDM-based
standards with respect to different criteria”, Krishnaiah Lokanadhan,
Saroja Narayana Murthy Rajavari KTH, School of Information and
Communication Technology (ICT),2013.
[5] J. G. Proakis, Digital Communications, McGraw-Hill, New York, USA,
Fourth edition,August 2000.
[6] Survey Report for Radix 2, Radix 4, Radix 8 FFT
Algorithms,International Journal of Innovative Research in
Science,Engineering and Technology,Vol. 4, Issue 7, July 2015
[7] C.R. Nassar et al., Multi-carrier Technologies for Wireless Communica-
tion, Kluwer Academic Publishers, Dordrecht, The Netherlands, 2002.
[8] R. Prasad, OFDM for Wireless Communications Systems, Artech House
Publishers, Norwood, MA, USA, September 2004.
[9] U.S. Jha, Low Complexity Resource Efficient OFDM Based Transceiver
Design, Ph.D.Thesis, Aalborg University, Denmark, September 2002.

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