Unit 1 8085 and 8086 Processor

1.

Draw and Explain the architecture of 8085?

Hardware Architecture

8085: 8 bit processor can process 8 bits in an instant.

It has 40 pins has a Dual Inline Package-(Made of epoxy material) known as DIP 40.
Pin 40 = power pin (+5 volt is given hence the 5 in the name 8085); Pin 20 = ground pin
Pins on 8085 chip can be grouped into
o Address Bus
o Data Bus
o Power supply & frequency
o Control & Status Signals
o Externally initiated signals
o Serial I/O ports

Buses in 8085:
8
Has 8 data lines hence can connect to 2 ( 256 nos ) I/O pe iphe als
16
6
10
Has 16 address lines hence has a memory capacity of 2 bits ( 2 x 2 = 64 KB )
In address bus, the higher byte A8 A15 are unidirectional
The lower order Address & data lines are bidirectional
The lower byte of the address line (A0 A7) and all the 8 Data lines (D0-D7) are multiplexed & hence
termed (AD0 AD7)
When ALE (Address enable latch) is enabled (during the early part of the execution), address is passed
through the lines, else data is passed (during the late part of the execution).
Hence 8085 has Von Neumann (or Princeton) architecture instruction fetch (or address fetch) and data
operation share a common bus.
ALU Arithmetic and Logical unit:

is responsible for all the arithmetic and Logical operations of the Processor
depends on the Accumulator and the temporary registers for its internal operations

Accumulator:

Special case register and Primary RAM memory in 8085

In every Arithmetic or logical operation, one of the operands is stored in Accumulator
The result of the same operation is usually stored in the accumulator

Temporary Register:

Not accessible to the user.

Used in internal operations of the processor.

General Purpose Registers:

Registers are RAM locations that can be accessed by the processor very easily.
They are
o B,C,D,E,H,L each have a capacity of 8 bits
o Can be used as 16 bit register pairs (BC , DE , HL pairs)

Stack Pointer:

Points always to the top of the stack.

The stack is used to store return address when the processor goes to perform a ISR (Interrupot Service
Routine).
Since it stores address, it is a 16 bit special case register.
Works in a LIFO last in First out Fashion.

Program Counter:

Stores the address location of the next instruction to be executed.

Since it stores address, it is a 16 bit special case register

Flags:
They indicate the current condition of the processor. They are given as follows.

Zero Flag:
ZF = 1, if ALU result = 0.
Sign Flag:
SF = 1, if MSB of ALU = 1.
Parity Flag:
PF = 1, if ALU result has even parity.
Carry Flag:
CF = 1, if carry occurs.
Auxiliary Carry Flag: ACF = 1, if carry occurs from lover to higher nibble (useful internally for BCD addition)

PSW - Processor Status Word:

The 8 bits of the accumulator + The 8 bits of the Flag are called = PSW
Hen e its a 16 it egiste

2.

Explain the interrupts in 8085?

Interrupts:

These are subroutines that the microprocessor responds to during its normal functioning.
Once the subroutine is responded to the microprocessor returns to the program with the help of stack
pointer and the stack.
The interrupts have priority assigned to them as given in the table.
Interrupts TRAP, RST 7.5, RST 6.5, RST 5.5 are called as Vector interrupts because their ISR are stored in
permanent locations as given in the table.
Masking can be termed as selective disabling- because the interrupts can be made active or inactive
depending on the needs and the concerns of the programmer. Interrupts RST 7.5, RST 6.5, RST 5.5 can be
masked.
TRAP is a non-maskable interrupt and has the highest priority assigned to it.
For INTR interrupt, (without the address of the service routine) is simply responded with an active low
signal INTA
There are 2 types of triggers to initiate the interrupts- thy are level triggered and edge triggered.

Hardware
Interrupts

Priority

Vector Address

Masking

Types of trigger

TRAP
RST 7.5
RST 6.5
RST 5.5

Highest

Non maskable Interrrupt

edge, level triggered

positive edge triggered

INTR

Lowest

0024 H
003C H
0034 H
002C H
Non Vector
Interrupt

3.

What is DMA? Explain the process in whole.

Mask-able
Level triggered

DMA (Direct Memory Access) Transfer:

When the processor needs to be accessed again and again when performing a repeated data copying
operation, then
o to save time & power, control of the data transfer lines is given to the input device controller
o HOLD & HLDA are used for this process
HOLD is sent from I/O device to the processor asking for control of the data lines
HLDA is sent from processor to the I/O device acknowledging the transfer of the control of the data lines.
In DMA, there are 2 modes
o Burst Mode
o Cycle stealing

Monitor Routines:
Reset in and Reset out are called as Monitor Routines.
Reset in takes the pointer of the microprocessor to 0000 where some already programmed stuff is kept.
Reset out is used to announce, the microprocessor is being reset to its connected peripherals.
Ready pin is used to connect the microprocessor with slow peripherals.
The clock out is used to communicate the frequency of the microprocessor to its peripherals.

Main Control Signals / Instructions:

IO/M, RD, WR are the three active low control signals that combine together to form the four important
active low control instructions.

Used for drawing timing diagram.

These are formed as given in the following table.

MEMR

MEMW

IOR

IOW

IO/M

RD

WR

4.

Draw and explain the architecture of 8086 processor ?

8086 Processor:

8086: First 16 bit processor can process 16 bits in an instant.

It has 40 pins has a Dual Inline Package (Made of epoxy material) - known as DIP 40.
Has 29,000 transistors
Frequency range of operation: 6 10 MHz

8086 architecture has 2 stage pipe-lining instruction execution. The central processing logic has been divided into

BIU (Bus interface Unit)

o Fetches the instructions or the data from the memory
o Inte fa es with pe iphe als and its po ts
o Writes data to memory
o Has a 6 byte instruction object code queue
Follows FIFO execution
Pre-fetching operation of BIU can be executed in parallel with EU operation, hence
speed of operation is improved.

EU (Execution Unit)
o Tells BIU where to fetch the instructions or the data from
o Decodes the instructions received from the queue
o Executes the instructions

Hen e BIUs ueue helps EU to fun tion faste . When EU is e e uting an inst u tion, BIU is us fet hing
the next instruction for the queue. This is called pipe lining (or) Parallel Processing.

It Follows Von Neumann architecture, where the 16 data lines are multiplexed

Multiprocessing in 8086:
8086 has 2 modes of operation: Helps to manage single and multiprocessing environment.

Minimum Mode (MN/MX = 1)

o Caters to single processor environment
Maximum Mode (MN / MX = 0)
o Caters to multiprocessor environment

What is Offset address in 8086?

It is the 8086 is the logical address that the program "thinks about" when it addresses a location in
memory. The Execution Unit (EU) is responsible for generating the offset address. The Bus Interface Unit
(BIU), on the other hand, takes the offset address and adds it to four times the selected segment register
value in order to determine a real address, which is now 20-bits in length.

Registers in 8086
It has 14 Sixteen Bit registers

Data Registers - (General Purpose but also has some special functions)
o Has 4 - Sixteen bit data registers
AX primary accumulator
BX used as base register while calculating data memory address
CX used to hold count in multi-iteration operations & loops
DX used in I/O instructions, multiply and divide instructions
o Upper and lower bytes are stored and addressed separately
o Hence can be used as 8 bit registers AH,AL,BH,BL,CH,CL,DH,DL
o Here L indicates lower; H indicates Higher; X indicates extended register

Segment Registers
o Additional Registers Used to generate memory address from the offset address in BIU

Has 4 - Sixteen bit registers

Code Segment
Used for addressing 64 KB of the memory location in the code segment of the
memory, where code of the executable program is stored
Data Segment
Points to the data segment of the 64 KB memory where the data is stored.
Stack Segment
Addressing stack segment of the memory
Extra Segment
Is another (additional) data segment of the memory space

Pointer and Index registers

o Used for pointing and indexing. They are
Stack Pointer
Holds offset address within the stack
Base pointer
Holds offset within the data
Source Index
Used to store offset of source data in data segment

5.

Destination Index
Used to store offset of destination data in source segment
Instruction Pointer
Instruction Register
o Points to the next instruction to be executed.

used in string
manipulations

Explain the Flags in 8086?

They indicate the current condition of the processor. They are given as follows.

Zero Flag:
ZF = 1, if ALU result = 0.
Sign Flag:
SF = 1, if MSB of ALU = 1.
Parity Flag:
PF = 1, if ALU result has even parity.
Carry Flag:
CF = 1, if carry occurs.
Auxiliary Carry Flag: ACF = 1, if carry occurs from lover to higher nibble (useful internally for BCD addition)
Trap Flag:
TF = 1, step by step error decoding is done
INTR Flag:
IF = 1, mask-able interrupt of INTR is enabled.
Direction Flag:
DF = 0, String is processed from lowest address to highest. Used for String
Manipulation
Overflow Flag
OF = 1, when over flow occurs as a result of signed operation

6.

Explain 8086 as a Multiprocessor and with regard to the interrupts?

8086 as Multiprocessor-

When a processor can be connected to work in cooperation with other processors in a connected
environment then it is termed as Multiprocessing.
(MN / MX) pin enables Multiprocessing in 8086. Hence 8086 has 2 states of operation.
o Minimum Mode
Active when (MN / MX) = 1, 8086 acts as a single processor
o Maximum Mode
Active when (MN / MX) = 0, 8086 acts as a Multiprocessor

8086 Interrupts:

These are subroutines that the microprocessor responds to during its normal functioning.
Once the subroutine is responded to the microprocessor returns to the program with the help of stack
pointer and the stack.
There are 2 types of interrupt in 8086 based on where they arise from
o External Interrupts Arises from outside the processor (Eg- from the peripheral devices)
o Internal Interrupts Arises from inside the processor
Masking can be termed as selective disabling- because the interrupts can be made active or inactive
depending on the needs and the concerns of the programmer. In 8086, Interrupts are classified again into
two types based on masking. They are
o NMI
Non Maskable interrupt interrupt cannot be masked.
o INTR Interrupt
Interrupt can be masked
8086 has Nested Interrupts
o That is - Interrupts can be interrupted by a higher order interrupt.
o This is enabled by the LIFO concept of the stack.

PIN DIAGRAM OF 8085 MICROPROCESSOR WITH DESCRIPTION

7) Describe the pin out of 8085 microprocessor with neat description

8085 is a general purpose microprocessor having 40 pins and works on single
power supply. To study the pin diagram we group the signals into 5 categories:
1.Power Supply
2.Clock Signals
3.Interrupt Signals
4.Address and Data bus
5.Control and Status signals
6.Serial I/O Port
7.DMA Request Signals

Power Supply Signal and clock signal:

VCC:-Vcc is to be connected to +5V power supply.
Vss:-Ground reference
X1 and X2:- This pin is used for providing the clock frequency to the
microprocessor. Generally Crystal oscillator or LC oscillator is used to generate
the frequency. The frequency generated here is internally divided into two.As we
know that the basic operating timing frequency of the microprocessor is 3 MHz
so 6 MHz frquency is applied.

Serial Input Output port:SID and SOD:-These pins are used for serial data communication.

Interrupt Signal:Pin 6 to 11:- These pins are used for interrupt signals. Generally and external
devices are connected here which requests the microprocessor to perform a
particular task.
There are 5 pins for hardware interruptsTRAP, RST7.5, RST 6.5, RST5.5 and INTR
INTA is used for acknowledgement. Microprocessor sends the acknowledgement
to external devices through the INTA pin.

Address Bus and DATA Buses:AD0-AD7:-These are multiplexed address and data bus. So it can be used to carry
the lower order 8 bit address as well as the data. Generally these lines are
demultiplexed using the Latch.
During the opcode fetch operation, in the first clock cycle the lines deliever the
lower order address bus A0-A7.
In the subsequent IO/M read or write it is used as data bus D0-D7. CPU can read
or write data through these lines.
A8-A15:- These are address bus used to address the memory location.

8085 MEMORY INTERFACING

MEMORY TERMINOLOGIES AND OPERATIONS:

Memories are made up of (registers).

Each register consists of one storage location.
Each location consists of an address.
The number of storage locations from few hundreds to several mega or giga locations.
The total number of memory storage is called memory capacity and measured in Bytes.
Each register consists of storage element (FF, capacitor for semiconductor) .
A storage element is called cell.
The data could be read from or written to memory .
MEMORY STRUCTURE AND ITS REQUIREMENTS

As mentioned earlier, read/write memories consist of an array of registers, in which each

register has unique address.
The size of the memory is N x M as shown below where N is the number of registers and M
is the word length, in number of bits .
LOGIC DIAGRAM OF RAM

LOGIC DIAGRAM OF EPROM

Example 1: If memory is having 12 address lines and 8 data lines, then

Number of registers/ memory locations (capacity) = 2N= 212= 4096.
Word length = M bit
= 8 bit
Example 2: If memory has 8192 memory locations, then it has 13 address lines.
NO OF ADDRESS LINES AND MEMORY CAPACITY:
Memory Capacity

Address lines Required

1k = 1024 memory locations

10

2k = 2048 memory locations

11

4k = 4096 memory locations

12

8k = 8192 memory locations

13

16k = 16384 memory locations

14

32k = 32768 memory locations

15

64k = 65536 memory locations

16

8) Explain the interfacing of memory devices with 8085 microprocessor?

For i terfa i g e ory de i es to p 8 8 , keep the follo i g poi ts i your i d:
p 8 8 a a ess KB e ory si e address us is -bit.
Generally EPROM (or EPROMs) is used as a program memory and RAM (or RAMs) as
data memory.
The capacity of program memory and data memory depends on the application.
It is not always necessary to select 1 EPROM and 1 RAM. We can have multiple
EPROMs and multiple RAMs as per the requirement of application.
Supposing if We have to implement 32 KB of program memory and 4KB EPROMs are
available. In this case we can connect 8 EPROMs in parallel.
We can place EPROM/RAM anywhere in full 64 KB address space. But program
memory (EPROM) should be located from address 0000 H.
It is not always necessary to locate EPROM and RAM in consecutive memory
address.
The memory interfacing requires to:

i) Select the chip

ii) Identify the register
iii) Enable the appropriate buffer.
p syste i ludes e ory a d I/O de i es.
It is i porta t to ote that p a o
u i ate read/ rite
a time, so address decoding needed.

ith o ly o e de i e at

ADDRESS DECODING TECHNIQUES:

There are two main techniques:
Absolute decoding/ Full Decoding.
Linear decoding / Partial Decoding .
ABSOLUTE DECODING:
All the higher address lines are decoded to select the memory chip, and the memory
chip is selected only for the specified logic level on these high-order address, no other
logic levels can select the chip.
This addressing technique is normally used in large memory systems

LINEAR DECODING:
In small systems, h/w for the decoding logic can be eliminated by using individual high-order
address lines to select memory chips.
This is referred to as linear decoding.
The figure below shows the addressing of RAM with linear decoding technique.
This technique is also called partial decoding.
It reduces the cost of the decoding, but it has a drawback of multiple address (shadow
addresses)

EXAMPLE 1:
9) Consider a system in which the full memory space 64kb is utilized for EPROM
memory. Interface the EPROM with 8085 processor?

The memory capacity is 64 Kbytes, that is ,

2^n = 64 x 1000 bytes where n = address lines.
Hence, n = 16. ( n = log2 64*1000).
In this system the entire 16 address lines of the processor are connected to address
input pins of memory IC in order to address the internal locations of memory.
The chip select (CS) pin of EPROM is permanently tied to logic low (i.e., tied to
ground).
Since the processor is connected to EPROM, the active low RD pin is connected to
active low output enable pin of EPROM.
The range of address for EPROM is 0000H to FFFFH.

EXAMPLE 2:
10) Consider a system in which the available 64kb memory space is equally divided
between EPROM and RAM. Interface the EPROM and RAM with 8085 processor?
Implement 32kb memory capacity of EPROM using single IC 27256.
32kb RAM capacity is implemented using single IC 62256.
The 32kb memory requires 15 address lines and so the address lines A0 - A14 of the
processor are connected to 15 address pins of both EPROM and RAM.
The unused address line A15 is used as to chip select. If A15 is 1, it select RAM and
If A15 is 0, it select EPROM.
Inverter is used for selecting the memory.
The memory used is both Ram and EPROM, so the low RD and WR pins of processor
are connected to low WE and OE pins of memory respectively.
The address range of EPROM will be 0000H to 7FFFH and that of RAM will be
7FFFH to FFFFH.

EXAMPLE 3:
11). Consider a system in which 32kb memory space is implemented using four number
of 8kb memory. Interface the EPROM and RAM with 8085 processor?
The total memory capacity is 32Kb. So, let two number of 8kb n memory be EPROM
and the remaining two numbers be RAM.
Each 8kb memory requires 13 address lines and so the address lines A0- A12 of the
processor are connected to 13 address pins of all the memory.
The address lines and A13 - A14 can be decoded using a 2-to-4 decoder to generate
four chip select signals.
These four chip select signals can be used to select one of the four memory IC at any
one time.
The address line A15 is used as enable for decoder.
The simplified schematic memory organization is shown.

EXAMPLE 4:
12)Consider a system in which the 64kb memory space is implemented using eight
numbers of 8kb memory. Interface the EPROM and RAM with 8085 processor. ?
The total memory capacity is 64Kb. So, let 4 numbers of 8Kb EPROM and 4 numbers
of 8Kb RAM.
Each 8kb memory requires 13 address lines. So the address line A0 - A12 of the
processor are connected to 13address pins of all the memory ICs.
The address lines A13, A14 and A]5 are decoded using a 3-to-8 coder to generate
eight chip select signals. These eight chip select signals can be used to select one of
the eight memories at any one time.
The memory interfacing is shown in following figure.

INPUT AND OUTPUT DEVICES INTERFACING WITH 8085

13) Write short notes on interfacing of I/O devices.

There are two types for interfacing I/O devices:
1. Memory mapped I/O device.
2. Standard I/O mapped I/O device or isolated I/O mapping.

14) A system requires 16kb EPROM and 16kb RAM. Also the system has 2
numbers of 8255, one number of 8279, one number of 8251 and one
number of 8254. (8255 - Programmable peripheral interface; 8279Keyboard/display controller, 8251 - USART and 8254 - Timer). Draw the
Interface diagram. Allocate addresses to all the devices. The peripheral IC
should be I/O mapped?

The I/O devices in the system should be mapped by standard I/O mapping. Hence
separate decoders can be used to generate chip select signals for memory IC and
peripheral IC's.
For 16kb EPROM, we can provide 2 numbers of 2764(8k x 8) EPROM.
For 16kb RAM we can provide 2 numbers of 6264 (8k x 8) RAM.
The 8kb memories require 13 address lines. Hence the address lines A0 - A12 are
used for selecting the memory locations.
The unused address lines A13, A14 and A15 are used as input to decoder 74LS138 (3to-8-deeoder) of memory IC. The logic low enables of this decoder are tied to IO/
M(low) of 8085, so that this decoder is enabled for memory read/write operation. The
other enable pins of decoder are tied to appropriate logic levels permanently. The 4outputs of the decoder are used to select memory lCs and the remaining 4 are kept for
future expansion.
The EPROM is mapped in the beginning of memory space from 0000H to 3FFF.
The RAM is mapped at the end of memory space from C000 to FFFFH.
There are five peripheral IC's to be interfaced to the system. The chip-select signals
for these IC's are given through another 3-to-8 decoder 74LS138 (I/O decoder). The
input to this decoder is A11, A12 and A13
The address lines A13, A14 and A15 are logically ORed and applied to low enable of
I/O decoder.
The logic high enable of I/O decoder is tied to IO / M(low) signal of 8085, so that this
decoder is enabled for I/O read/write operation.

Fig - Internal address of 8255

INTERRUPT STRCUTRE IN 8085

15) Describe the interrupt structure of 8085 microprocessor

Interrupt is signals send by an external device to the processor, to request the

processor to perform a particular task or work.
Mainly in the microprocessor based system the interrupts are used for data transfer
between the peripheral and the microprocessor.
The processor will check the interrupts always at the 2nd T-state of last machine
cycle.
If there is any interrupt it accept the interrupt and send the INTA (active low) signal
to the peripheral.
The vectored address of particular interrupt is stored in program counter.
The processor executes an interrupt service routine (ISR) addressed in program
counter.
It returned to main program by RET instruction

Types of Interrupts:
It supports two types of interrupts.
Hardware
Software

Software interrupts:
The software interrupts are program instructions. These instructions are inserted at
desired locations in a program.
The 8085 has eight software interrupts from RST 0 to RST 7. The vector address for
these interrupts can be calculated as follows.
Interrupt number * 8 = vector address
For RST 5,5 * 8 = 40 = 28H
Vector address for interrupt RST 5 is 0028H
The Table shows the vector addresses of all interrupts.

Hardware interrupts:
An external device initiates the hardware interrupts and placing an appropriate
signal at the interrupt pin of the processor.
If the interrupt is accepted then the processor executes an interrupt service routine.

The 8085 has five hardware interrupts

(1) TRAP (2) RST 7.5 (3) RST 6.5 (4) RST 5.5 (5) INTR

TRAP:

This interrupt is a non-maskable interrupt. It is unaffected by any mask or interrupt

enable.
TRAP bas the highest priority and vectored interrupt.
TRAP interrupt is edge and level triggered. This means hat the TRAP must go high
and remain high until it is acknowledged.
In sudden power failure, it executes a ISR and send the data from main memory to
backup memory.
The signal, which overrides the TRAP, is HOLD signal. (i.e., If the processor receives
HOLD and TRAP at the same time then HOLD is recognized first and then TRAP is
recognized).
There are two ways to clear TRAP interrupt.
1.By resetting microprocessor (External signal)
2.By giving a high TRAP ACKNOWLEDGE (Internal signal)

RST 7.5:
The RST 7.5 interrupt is a maskable interrupt.
It has the second highest priority.
It is edge sensitive. ie. Input goes to high and no need to maintain high state until it
recognized.
Maskable interrupt. It is disabled by,
1.DI instruction
2.System or processor reset.
3.After reorganization of interrupt.
Enabled by EI instruction.
RST 6.5 and 5.5:

The RST 6.5 and RST 5.5 both are level triggered. . ie. Input goes to high and stay
high until it recognized.
Maskable interrupt. It is disabled by,
1.DI, SIM instruction
2.System or processor reset.
3.After reorganization of interrupt.

Enabled by EI instruction.
The RST 6.5 has the third priority whereas RST 5.5 has the fourth priority.

INTR:
INTR is a maskable interrupt. It is disabled by,
1.DI, SIM instruction
2.System or processor reset.
3.After reorganization of interrupt.
Enabled by EI instruction.
Non- vectored interrupt. After receiving INTA (active low) signal, it has to supply the
address of ISR.
It has lowest priority.
It is a level sensitive interrupts. i.e. Input goes to high and it is necessary to maintain
high state until it recognized.

The following sequence of events occurs when INTR signal goes high.
1. The 8085 checks the status of INTR signal during execution of each
instruction.
2. If INTR signal is high, then 8085 complete its current instruction and sends
active low interrupt acknowledge signal, if the interrupt is enabled.
3. In response to the acknowledge signal, external logic places an instruction
OPCODE on the data bus. In the case of multibyte instruction, additional
interrupt acknowledge machine cycles are generated by the 8085 to transfer
the additional bytes into the microprocessor.
4. On receiving the instruction, the 8085 save the address of next instruction on
stack and execute received instruction.

SIM and RIM for interrupts:

The 8085 provide additional masking facility for RST 7.5, RST 6.5 and RST 5.5 using
SIM instruction.
The status of these interrupts can be read by executing RIM instruction.
The masking or unmasking of RST 7.5, RST 6.5 and RST 5.5 interrupts can be
performed by moving an 8-bit data to accumulator and then executing SIM
instruction.
The format of the 8-bit data is shown below.

The status of pending interrupts can be read from accumulator after executing RIM
instruction.

When RIM instruction is executed an 8-bit data is loaded in accumulator, which can
be interpreted as shown in fig.

TIMING DIAGRAM OF 8085 FOR VARIOUS MACHINE

CYCLES
The machine cycles are the basic operations performed by the processor, while
instructions are executed. The time taken for performing each machine cycle is
expressed in terms of T-states.
One T-state is the time period of one clock cycle of the microprocessor.
The various machine cycles are
1.
2.
3.
4.
5.
6.
7.

Opcode fetch ..
Memory Read .
Memory Write .
I/O Read ..
I/O Write .
Interrupt Acknowledge
Bus Idle

4/6T
3T
3T
3T
3T
6 / 12 T
2/3T

16)Discuss the (i) Opcode fetch (ii) Memory Read (iii) Memory Write
(iv) I/O read and (v) I/O write machine cycles of 8085.