H8 539 Extended

To all our customers
Regarding the change of names mentioned in the document, such as Hitachi

Electric and Hitachi XX, to Renesas Technology Corp.
The semiconductor operations of Mitsubishi Electric and Hitachi were transferred to Renesas
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Renesas Technology Corp.

Customer Support Dept.
April 1, 2003
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Hitachi Single-Chip Microcomputer
H8/539F-ZTAT™
HD64F5398
HD64F5398S
HD64F5398A
Hardware Manual
ADE-602-108B
Rev 3.0
2/18/1999
Hitachi, Ltd.
Cautions
1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s
patent, copyright, trademark, or other intellectual property rights for information contained in
this document. Hitachi bears no responsibility for problems that may arise with third party’s
rights, including intellectual property rights, in connection with use of the information
contained in this document.
2. Products and product specifications may be subject to change without notice. Confirm that you
have received the latest product standards or specifications before final design, purchase or
use.
3. Hitachi makes every attempt to ensure that its products are of high quality and reliability.
However, contact Hitachi’s sales office before using the product in an application that
demands especially high quality and reliability or where its failure or malfunction may directly
threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear
power, combustion control, transportation, traffic, safety equipment or medical equipment for
life support.
4. Design your application so that the product is used within the ranges guaranteed by Hitachi
particularly for maximum rating, operating supply voltage range, heat radiation characteristics,
installation conditions and other characteristics. Hitachi bears no responsibility for failure or
damage when used beyond the guaranteed ranges. Even within the guaranteed ranges,
consider normally foreseeable failure rates or failure modes in semiconductor devices and
employ systemic measures such as fail-safes, so that the equipment incorporating Hitachi
product does not cause bodily injury, fire or other consequential damage due to operation of
the Hitachi product.
5. This product is not designed to be radiation resistant.
6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document
without written approval from Hitachi.
7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi
semiconductor products.
Preface
1
The H8/539F is an F-ZTAT* microcontroller with on-chip flash memory that can be
2
reprogrammed onboard, offering even better field-programmability than ZTAT*
microcontrollers with user-programmable on-chip ROM.
The H8/539F is an original Hitachi high-performance single-chip microcontroller with a high-

speed 16-bit H8/500 CPU core and extensive on-chip peripheral functions. It is suitable for
controlling a wide range of medium-scale office and industrial equipment and consumer products.
The general-register architecture and highly orthogonal, optimized instruction set of the H8/500
CPU enable even programs coded in the high-level C language to be compiled into efficient object
code.
Many of the peripheral functions needed in microcontroller application systems are provided on-
chip, including large RAM and ROM, a powerful set of timers, a serial interface, a high-precision
A/D converter, and I/O ports. Compact, high-performance systems can thus be implemented
easily.
Additionally, the on-chip flash memory makes this microcontroller suitable for high-speed data
transfer and fast arithmetic/logic operations.
This document describes the H8/539F hardware. For further details about the H8/500 CPU
instruction set, refer to the H8/500 Series Programming Manual.
Notes: 1. F-ZTAI (Flexible-ZTAT) is a trademark of Hitachi, Ltd.

2. ZTAT (Zero Turn-Around Time) is a trademark of Hitachi, Ltd.
Rev. 3.0, 02/99, page v of 904

H8/539F Product Specification Comparison
To facilitate comparisons of H8/539F product specifications, the portions of the manual describing
points of difference are listed below. For information on the differences between the single power
source and dual power source models, refer to 1.4 Notes on S-Mask and A-Mask Models (Single
Power Source). The differences between the S-mask and A-mask models are described in 1.5
H8/539F A-Mask Overview
Portions of H8/539F Manual Describing Points of Difference
H8/539F H8/539F S-Mask H8/539F A-Mask

Product Dual power source Single power source Single power source
Specification On-chip step-down circuit
(EMI noise reduction)
Model HD64F5398F16 HD64F5398SF16 HD64F5398AF16
Pin Arrangement Figure 1.2 (a) H8/539F Figure 1.2 (b) H8/539F Figure 1.2 (c) H8/539F
Pin Arrangement S-Mask Model Pin A-Mask Model Pin
Arrangement Arrangement
RAM Section 17 RAM (H8/539F) Section 18 RAM (H8/539F S-Mask and A-Mask
Dual Power Source Models)
(VPP = 12 V)
Flash Memory Section 19 Flash Memory Section 20 Flash Memory
(H8/539F) Dual Power (H8/539F S-Mask and A-Mask Models:
Source Single Power Source)
(VPP = 12 V)
Electrical Section 22 Electrical Section 23 Electrical Section 24 Electrical
Characteristics Characteristics (H8/539F) Characteristics Characteristics
Dual Power Source (S-Mask Model) (A-Mask Model)
(VPP = 12 V)
Limitations 3.6 Notes on Use of 3.7 Notes on H8/539F S-Mask and A-Mask Models
Externally Expanded Modes (Single Power Source), Power-On Timing
of H8/539F
(Dual Power Source Model)
Notes  1.4 Notes on S-Mask and A-Mask Models
(Single Power Source)
On-Chip Step-   1.5 H8/539F A-Mask
Down Circuit Overview
On-Chip Appendix C On-Chip Appendix C On-Chip Registers
Registers Registers (2) H8/539F S-Mask and A-Mask Models
(1) H8/539F
Rev. 3.0, 02/99, page vi of 904

Contents
Section 1 Overview ...........................................................................................1

1.1 Features .............................................................................................................................1
1.2 Block Diagram ..................................................................................................................6
1.3 Pin Descriptions ................................................................................................................7
1.3.1 Pin Arrangement ..................................................................................................7
1.3.2 Pin Functions........................................................................................................12
1.4 Notes on S-Mask and A-Mask Models (Single Power Source).........................................23
1.4.1 Voltage Application .............................................................................................23
1.4.2 Product Type Names and Markings .....................................................................24
1.4.3 Differences in S-Mask and A-Mask Models ........................................................24
1.5 H8/539F A-Mask Overview ..............................................................................................29
1.5.1 Features ................................................................................................................29
1.5.2 On-Chip Step-Down Circuit.................................................................................29
1.5.3 Differences Between the S-Mask and A-Mask Models .......................................31
Section 2 CPU ...................................................................................................33

2.1 Overview ...........................................................................................................................33
2.1.1 Features ................................................................................................................33
2.1.2 Address Space ......................................................................................................34
2.1.3 Programming Model ............................................................................................36
2.2 General Registers ..............................................................................................................37
2.2.1 Overview ..............................................................................................................37
2.2.2 Register Configuration .........................................................................................37
2.2.3 Stack Pointer ........................................................................................................37
2.2.4 Frame Pointer .......................................................................................................38
2.3 Control Registers...............................................................................................................38
2.3.1 Overview ..............................................................................................................38
2.3.3 Program Counter ..................................................................................................39
2.3.4 Status Register......................................................................................................39
2.4 Page Registers ...................................................................................................................41
2.4.1 Overview ..............................................................................................................41
2.4.3 Code Page Register ..............................................................................................43
2.4.4 Data Page Register ...............................................................................................44
2.4.5 Extended Page Register........................................................................................44
2.4.6 Stack Page Register ..............................................................................................44
2.5 Base Register.....................................................................................................................45
2.5.1 Overview ..............................................................................................................45
Rev. 3.0, 02/99, page vii of 904

2.6 Data Formats .....................................................................................................................46
2.6.1 Data Formats in General Registers.......................................................................46
2.6.2 Data Formats in Memory .....................................................................................47
2.6.3 Stack Data Formats ..............................................................................................48
2.7 Addressing Modes and Effective Address Calculation .....................................................49
2.7.1 Addressing Modes................................................................................................49
2.7.2 Effective Address Calculation..............................................................................52
2.8 Operating Modes ...............................................................................................................55
2.8.1 Minimum Mode ...................................................................................................55
2.8.2 Maximum Mode...................................................................................................55
2.9 Basic Operational Timing .................................................................................................55
2.9.1 Overview ..............................................................................................................56
2.9.2 Access to On-Chip Memory.................................................................................56
2.9.3 Access to Two-State-Access Address Space........................................................57
2.9.4 Access to On-Chip Supporting Modules..............................................................58
2.9.5 Access to Three-State-Access Address Space......................................................59
2.10 CPU States.........................................................................................................................61
2.10.1 Overview ..............................................................................................................61
2.10.2 Program Execution State......................................................................................62
2.10.3 Exception-Handling State ....................................................................................62
2.10.4 Bus-Released State...............................................................................................63
2.10.5 Reset State............................................................................................................70
2.10.6 Power-Down State................................................................................................70
Section 3 MCU Operating Modes..................................................................... 71

3.1 Overview ...........................................................................................................................71
3.1.1 Selection of Operating Mode ...............................................................................71
3.2 Mode Control Register ......................................................................................................73
3.3 Operating Mode Descriptions............................................................................................74
3.3.1 Mode 1 (Expanded Minimum Mode)...................................................................74
3.3.2 Mode 2 (Expanded Minimum Mode)...................................................................74
3.3.3 Mode 3 (Expanded Maximum Mode) ..................................................................74
3.3.4 Mode 4 (Expanded Maximum Mode) ..................................................................74
3.3.5 Modes 5 and 6 ......................................................................................................74
3.3.6 Mode 7 (Single-Chip Mode) ................................................................................74
3.4 Pin Functions in Each Operating Mode.............................................................................75
3.5 Memory Map in Each Mode .............................................................................................76
3.6 Notes on Use of Externally Expanded Modes of H8/539F (Dual Power Source Model)..79
3.7 Notes on H8/539F S-Mask and A-Mask Models
(Single Power Source Model) ...........................................................................................80
Rev. 3.0, 02/99, page viii of 904

Section 4 Exception Handling ...........................................................................81
4.1 Overview ...........................................................................................................................81
4.1.1 Exception Handling Types and Priority ...............................................................81
4.1.2 Exception Handling Operation.............................................................................82
4.1.3 Exception Sources and Vector Table ...................................................................83
4.2 Reset ..................................................................................................................................85
4.2.1 Overview ..............................................................................................................85
4.2.2 Reset Sequence.....................................................................................................85
4.2.3 Interrupts after Reset ............................................................................................88
4.3 Address Error ....................................................................................................................88
4.3.1 Address Error in Instruction Prefetch...................................................................89
4.3.2 Address Error in Word Data Access ....................................................................89
4.3.3 Address Error in Single-Chip Mode.....................................................................90
4.4 Trace..................................................................................................................................92
4.5 Interrupts ...........................................................................................................................92
4.6 Invalid Instructions............................................................................................................93
4.7 Trap Instructions and Zero Divide ....................................................................................94
4.8 Cases in which Exception Handling is Deferred ...............................................................95
4.8.1 Instructions that Disable Exception Handling ......................................................95
4.8.2 Disabling of Exceptions Immediately after a Reset .............................................96
4.8.3 Disabling of Interrupts after a Data Transfer Cycle .............................................96
4.9 Stack Status after Completion of Exception Handling ......................................................97
4.9.1 PC Value Pushed on Stack for Trace, Interrupts, Trap Instructions,
and Zero Divide Exceptions .................................................................................98
4.9.2 PC Value Pushed on Stack for Address Error
and Invalid Instruction Exceptions.......................................................................98
4.10 Notes on Use of the Stack .................................................................................................98
Section 5 H8 Multiplier (H8MULT) .................................................................99

5.1 Overview ...........................................................................................................................99
5.1.1 Features ................................................................................................................99
5.1.2 Block Diagram .....................................................................................................100
5.2 Register Descriptions ........................................................................................................102
5.2.1 MULT Control Register .......................................................................................102
5.2.2 MULT Base Address Register .............................................................................103
5.2.3 MULT Multiplier Address Register .....................................................................104
5.2.4 MULT Multiplicand Address Register.................................................................104
5.2.5 MULT Multiplier Register A ...............................................................................104
5.2.6 MULT Multiplier Register B ...............................................................................105
5.2.7 MULT Multiplier Register C ...............................................................................105
5.2.8 MULT Immediate Multiplier Register .................................................................105
Rev. 3.0, 02/99, page ix of 904
5.2.9 MULT Immediate Multiplicand Register.............................................................106
5.2.10 MULT Result Register, Extended High Word .....................................................106
5.2.11 MULT Result Register, High Word .....................................................................106
5.2.12 MULT Result Register, Low Word......................................................................107
5.3 Operation...........................................................................................................................107
5.3.1 Initialization of MULT Result Registers ..............................................................107
5.3.2 Writing to MULT Multiplier Registers ................................................................108
5.3.3 Bus-Stealing Function ..........................................................................................109
5.3.4 Multiply and Multiply-Accumulate Functions .....................................................111
Section 6 Interrupt Controller ........................................................................... 119

6.1 Overview ...........................................................................................................................119
6.1.1 Features ................................................................................................................119
6.1.2 Block Diagram .....................................................................................................120
6.1.3 3Register Configuration .......................................................................................120
6.2 Interrupt Sources ...............................................................................................................121
6.2.1 NMI Interrupt .......................................................................................................123
6.2.2 IRQ0 Interrupt......................................................................................................124
6.2.3 IRQ1 to IRQ3 Interrupt ........................................................................................124
6.2.4 Internal Interrupts.................................................................................................127
6.3.1 Interrupt Priority Registers A to F........................................................................128
6.3.2 Timing of Priority Changes..................................................................................129
6.4 Interrupt Operations ..........................................................................................................129
6.4.1 Operations up to Interrupt Acceptance.................................................................129
6.4.2 Interrupt Exception Handling...............................................................................132
6.4.3 Interrupt Exception Handling Sequence...............................................................134
6.4.4 Stack after Interrupt Exception Handling.............................................................135
6.5 Interrupts during DTC Operation ......................................................................................137
6.6 Interrupt Response Time ...................................................................................................137
Section 7 Data Transfer Controller ................................................................... 139

7.1 Overview ...........................................................................................................................139
7.1.1 Features ................................................................................................................139
7.1.2 Block Diagram .....................................................................................................140
7.2.1 Data Transfer Mode Register ...............................................................................142
7.2.2 Data Transfer Source Address Register ...............................................................143
7.2.3 Data Transfer Destination Address Register ........................................................143
7.2.4 Data Transfer Count Register...............................................................................144
7.2.5 Data Transfer Enable Registers A to F.................................................................144
7.2.6 Note on Timing of DTE Modifications ................................................................145
Rev. 3.0, 02/99, page x of 904
7.3 Operation...........................................................................................................................146
7.3.1 DTC Operations ...................................................................................................146
7.3.2 DTC Vector Table................................................................................................148
7.3.3 Location of Register Information in Memory ......................................................151
7.3.4 Number of States per Data Transfer.....................................................................152
7.4 Procedure for Using DTC..................................................................................................154
7.5 Example.............................................................................................................................155
Section 8 Wait-State Controller.........................................................................159

8.1 Overview ...........................................................................................................................159
8.1.1 Features ................................................................................................................159
8.1.2 Block Diagram .....................................................................................................160
8.2 Wait Control Register........................................................................................................161
8.3 Operation...........................................................................................................................162
8.3.1 Programmable Wait Mode ...................................................................................163
8.3.2 Pin Wait Mode .....................................................................................................164
8.3.3 Pin Auto-Wait Mode ............................................................................................166
Section 9 Clock Pulse Generator .......................................................................169

9.1 Overview ...........................................................................................................................169
9.1.1 Block Diagram .....................................................................................................169
9.2 Oscillator Circuit ...............................................................................................................170
9.2.1 Connecting a Crystal Resonator ...........................................................................170
9.2.2 External Clock Input ............................................................................................172
9.3 Duty Adjustment Circuit ...................................................................................................174
Section 10 I/O Ports...........................................................................................175

10.1 Overview ...........................................................................................................................175
10.2 Port 1 .................................................................................................................................178
10.2.1 Overview ..............................................................................................................178
10.2.2 Register Descriptions ...........................................................................................179
10.2.3 Pin Functions in Each Mode ................................................................................180
10.2.4 Port 1 Read/Write Operations ..............................................................................181
10.3 Port 2 .................................................................................................................................184
10.3.1 Overview ..............................................................................................................184
10.4 Port 3 .................................................................................................................................190
10.4.1 Overview ..............................................................................................................190
Rev. 3.0, 02/99, page xi of 904
10.5 Port 4 .................................................................................................................................195
10.5.1 Overview ..............................................................................................................195
10.6 Port 5 .................................................................................................................................201
10.6.1 Overview ..............................................................................................................201
10.7 Port 6 .................................................................................................................................207
10.7.1 Overview ..............................................................................................................207
10.8 Port 7 .................................................................................................................................214
10.8.1 Overview ..............................................................................................................214
10.9 Port 8 .................................................................................................................................222
10.9.1 Overview ..............................................................................................................222
10.9.3 Port 8 Read Operation ..........................................................................................223
10.10 Port 9 .................................................................................................................................223
10.10.1 Overview ..............................................................................................................223
10.10.3 Port 9 Read Operation ..........................................................................................224
10.11 Port A ................................................................................................................................225
10.11.1 Overview ..............................................................................................................225
10.11.4 Port A Read/Write Operations .............................................................................231
10.12 Port B ................................................................................................................................237
10.12.1 Overview ..............................................................................................................237
10.12.4 Built-In Pull-Up Transistors.................................................................................241
10.12.5 Port B Read/Write Operations..............................................................................242
10.13 Port C ................................................................................................................................245
10.13.1 Overview ..............................................................................................................245
Rev. 3.0, 02/99, page xii of 904
10.13.4 Built-In MOS Pull-Up Transistors .......................................................................249
10.13.5 Port C Read/Write Operations..............................................................................249
Section 11 16-Bit Integrated-Timer Pulse Unit.................................................253

11.1 Overview ...........................................................................................................................253
11.1.1 Features ................................................................................................................253
11.1.2 Block Diagram .....................................................................................................254
11.1.3 Input/Output Pins .................................................................................................255
11.2 Timer Counters and Compare/Capture Registers ..............................................................256
11.3 Channel 1 Registers...........................................................................................................257
11.3.2 Timer Control Register (High) .............................................................................260
11.3.3 Timer Control Register (Low)..............................................................................262
11.3.4 Timer Status Register (High) ...............................................................................266
11.3.5 Timer Status Register (Low) ................................................................................270
11.3.6 Timer Output Enable Register..............................................................................275
11.4 Channel 2 to 5 Registers....................................................................................................280
11.4.2 Timer Control Register (Low)..............................................................................285
11.5 Channel 6 and 7 Registers .................................................................................................294
11.6 IPU Register Descriptions .................................................................................................303
11.6.1 Timer Mode Register A........................................................................................303
11.6.2 Timer Mode Register B........................................................................................306
11.6.3 Timer Start Register .............................................................................................309
11.7 H8/500 CPU Interface .......................................................................................................311
11.7.1 16-Bit Accessible Registers..................................................................................311
11.7.2 Eight-Bit Accessible Registers .............................................................................314
11.8 Examples of Timer Operation ...........................................................................................317
11.8.1 Examples of Counting..........................................................................................317
11.8.2 Selection of Output Level ....................................................................................320
11.8.3 Input Capture Function.........................................................................................323
11.8.4 Counter Clearing Function ...................................................................................327
11.8.5 PWM Output Mode..............................................................................................329
11.8.6 Synchronizing Mode ............................................................................................333
11.8.7 External Event Counting ......................................................................................336
Rev. 3.0, 02/99, page xiii of 904
11.8.8 Programmed Periodic Counting Mode.................................................................339
11.8.9 Phase Counting Mode ..........................................................................................342
11.9 Interrupts ...........................................................................................................................348
11.9.1 Interrupt Timing ...................................................................................................348
11.9.2 Interrupt Sources and DTC Interrupts ..................................................................350
11.10 Notes and Precautions .......................................................................................................352
Section 12 PWM Timers ................................................................................... 363

12.1 Overview ...........................................................................................................................363
12.1.1 Features ................................................................................................................363
12.1.2 Block Diagram .....................................................................................................364
12.1.3 Pin Configuration .................................................................................................365
12.2.1 Timer Counter (TCNT) ........................................................................................366
12.2.2 Duty Register (DTR) ............................................................................................366
12.2.3 Timer Control Register (TCR) .............................................................................367
12.3 PWM Timer Operation......................................................................................................369
12.4 Usage Notes.......................................................................................................................371
Section 13 Watchdog Timer.............................................................................. 373

13.1 Overview ...........................................................................................................................373
13.1.1 Features ................................................................................................................373
13.1.2 Block Diagram .....................................................................................................374
13.2.1 Timer Counter ......................................................................................................375
13.2.2 Timer Control/Status Register..............................................................................376
13.2.3 Reset Control/Status Register...............................................................................379
13.2.4 Notes on Register Access .....................................................................................380
13.3 Operation...........................................................................................................................382
13.3.1 Watchdog Timer Operation..................................................................................382
13.3.2 Interval Timer Operation......................................................................................383
13.3.3 Operation in Software Standby Mode ..................................................................384
13.3.4 Timing of Setting of Overflow Flag (OVF) .........................................................385
13.3.5 Timing of Setting of Watchdog Timer Reset (WRST).........................................386
13.4 Usage Notes.......................................................................................................................387
Section 14 Serial Communication Interface...................................................... 389

14.1 Overview ...........................................................................................................................389
14.1.1 Features ................................................................................................................389
14.1.2 Block Diagram .....................................................................................................390
Rev. 3.0, 02/99, page xiv of 904
14.2.1 Receive Shift Register ..........................................................................................393
14.2.2 Receive Data Register ..........................................................................................393
14.2.3 Transmit Shift Register ........................................................................................394
14.2.4 Transmit Data Register.........................................................................................394
14.2.5 Serial Mode Register ............................................................................................395
14.2.6 Serial Control Register .........................................................................................399
14.2.7 Serial Status Register ...........................................................................................403
14.2.8 Bit Rate Register ..................................................................................................408
14.3 Operation...........................................................................................................................417
14.3.1 Overview ..............................................................................................................417
14.3.2 Operation in Asynchronous Mode .......................................................................419
14.3.3 Clocked Synchronous Operation..........................................................................428
14.3.4 Multiprocessor Communication ...........................................................................437
14.4 Interrupts and DTC............................................................................................................444
14.5 Usage Notes.......................................................................................................................444
14.6 Notes on SCK Pin to Port Switching Using Clock Synchronized SCI..............................447
Section 15 A/D Converter .................................................................................449

15.1 Overview ...........................................................................................................................449
15.1.1 Features ................................................................................................................449
15.1.2 Block Diagram .....................................................................................................450
15.2.1 A/D Data Registers 0 to B....................................................................................453
15.2.2 A/D Control Status Register.................................................................................454
15.2.3 A/D Control Register ...........................................................................................459
15.2.4 A/D Trigger Register............................................................................................460
15.3 H8/500 CPU Interface .......................................................................................................462
15.4 Operation...........................................................................................................................464
15.4.1 Single Mode .........................................................................................................464
15.4.2 Scan Mode............................................................................................................467
15.4.3 Analog Input Sampling and A/D Conversion Time .............................................470
15.4.4 External Triggering of A/D Conversion...............................................................472
15.4.5 Starting A/D Conversion by IPU..........................................................................472
15.5 Interrupts and DTC............................................................................................................473
15.6 Usage Notes.......................................................................................................................473
Section 16 Bus Controller .................................................................................479

16.1 Overview ...........................................................................................................................479
16.1.1 Features ................................................................................................................479
Rev. 3.0, 02/99, page xv of 904
16.1.2 Block Diagram .....................................................................................................479
16.2.1 Byte Area Top Register........................................................................................481
16.2.2 Three-State Area Top Register.............................................................................482
16.2.3 Bus Control Register ............................................................................................483
16.3 Operation...........................................................................................................................488
16.3.1 Operation after Reset in Each Mode ....................................................................488
16.3.2 Timing of Changes in Bus Areas and Bus Size....................................................493
16.3.3 I/O Port Expansion Function................................................................................495
16.4 Usage Notes.......................................................................................................................496
Section 17 RAM (H8/539F).............................................................................. 503

17.1 Overview ...........................................................................................................................503
17.1.1 Block Diagram .....................................................................................................503
17.2 RAM Control Register ......................................................................................................505
17.3 Operation...........................................................................................................................506
17.3.1 Expanded Modes (Modes 1 to 6) .........................................................................506
17.3.2 Single-Chip Mode (Mode 7) ................................................................................506
Section 18 RAM (H8/539F S-Mask and A-Mask Models)............................... 507

18.1 Overview ...........................................................................................................................507
18.1.1 Block Diagram .....................................................................................................507
18.2 RAM Control Register ......................................................................................................509
18.3 Operation...........................................................................................................................510
18.3.1 Expanded Modes (Modes 1 to 6) .........................................................................510
18.3.2 Single-Chip Mode (Mode 7) ................................................................................510
Section 19 Flash Memory (H8/539F) Dual power source system

(VPP = 12 V) ..................................................................................... 511
19.1 Overview ...........................................................................................................................511
19.1.1 Flash Memory Overview......................................................................................511
19.1.2 Mode Programming and ROM Address Space ....................................................512
19.1.3 Features ................................................................................................................513
19.1.4 Block Diagram .....................................................................................................514
19.2.1 Flash Memory Control Register (FLMCR) ..........................................................516
19.2.2 Erase Block Register 1 (EBR1)............................................................................518
Rev. 3.0, 02/99, page xvi of 904
19.2.4 RAM Control Register (RAMCR) .......................................................................521
19.2.5 Flash Memory Emulation Register (FLMER)......................................................522
19.2.6 Flash Memory Status Register (FLMSR).............................................................523
19.3 On-Board Programming Modes ........................................................................................527
19.3.1 Boot Mode............................................................................................................527
19.3.2 User Program Mode .............................................................................................533
19.4 Programming and Erasing Flash Memory.........................................................................535
19.4.1 Program Mode......................................................................................................535
19.4.2 Program-Verify Mode ..........................................................................................536
19.4.3 Programming Flowchart and Sample Program ....................................................537
19.4.4 Erase Mode...........................................................................................................544
19.4.5 Erase-Verify Mode...............................................................................................544
19.4.6 Erasing Flowchart and Sample Program ..............................................................545
19.4.7 Prewrite-Verify Mode ..........................................................................................565
19.4.8 Protect Modes.......................................................................................................565
19.4.9 NMI Input Masking..............................................................................................568
19.5 Flash Memory Emulation by RAM...................................................................................569
19.6 PROM Mode .....................................................................................................................574
19.6.1 PROM Mode Setting ............................................................................................574
19.6.2 Socket Adapter and Memory Map .......................................................................574
19.6.3 Operation in PROM Mode ...................................................................................575
19.7 Flash Memory Programming and Erasing Precautions .....................................................583
19.8 Notes on Mounting Board DevelopmentHandling of VPP and Mode MD2 Pins ...........589
Section 20 Flash Memory

(H8/539F, S-Mask and A-Mask Models: Single Power Source) ....591
20.1 Overview ...........................................................................................................................591
20.1.1 Notes on S-Mask and A-Mask Models (Single Power Source) ...........................591
20.1.2 Mode Pin Settings and ROM Space .....................................................................592
20.1.3 Features ................................................................................................................593
20.1.4 Block Diagram .....................................................................................................594
20.1.5 Pin Configuration .................................................................................................595
20.2.1 Flash Memory Control Register (FLMCR) ..........................................................596
20.2.3 RAM Control Register (RAMCR) .......................................................................603
20.2.4 Flash Memory Emulation Register (FLMER)......................................................604
20.2.5 Flash Memory Status Register (FLMSR).............................................................606
20.3 On-Board Programming Mode..........................................................................................610
20.3.1 Boot Mode............................................................................................................610
20.3.2 User Program Mode .............................................................................................616
20.4 Flash Memory Programming/Erasing ...............................................................................618
Rev. 3.0, 02/99, page xvii of 904
20.4.1 Program Mode......................................................................................................618
20.4.2 Program-Verify Mode ..........................................................................................619
20.4.3 Sample 32-Byte Programming Flowchart ............................................................621
20.4.4 Erase Mode...........................................................................................................630
20.4.5 Erase-Verify Mode...............................................................................................630
20.4.6 Sample Flowchart for Erasing One Block............................................................631
20.4.7 Protection Modes .................................................................................................642
20.4.8 NMI Input Disabling Conditions..........................................................................645
20.5 Flash Memory Emulation in RAM....................................................................................647
20.6 PROM Mode .....................................................................................................................653
20.6.1 PROM Mode Setting ............................................................................................653
20.6.2 Socket Adapter and Memory Map .......................................................................653
20.6.3 PROM Mode Operation .......................................................................................654
20.6.4 Memory Read Mode.............................................................................................656
20.6.5 Auto-Program Mode ............................................................................................660
20.6.6 Auto-Erase Mode .................................................................................................662
20.6.7 Status Read Mode.................................................................................................664
20.6.8 PROM Mode Transition Time .............................................................................665
20.6.9 Notes on Memory Programming..........................................................................666
20.7 Flash Memory Programming and Erasing Precautions .....................................................667
Section 21 Power-Down State........................................................................... 673

21.1 Overview ...........................................................................................................................673
21.2 Sleep Mode........................................................................................................................673
21.2.1 Transition to Sleep Mode .....................................................................................673
21.2.2 Exit from Sleep Mode ..........................................................................................674
21.3 Software Standby Mode ....................................................................................................674
21.3.1 Transition to Software Standby Mode..................................................................674
21.3.2 Software Standby Control Register ......................................................................675
21.3.3 Exit from Software Standby Mode.......................................................................676
21.3.4 Sample Application of Software Standby Mode ..................................................677
21.3.5 Note......................................................................................................................677
21.4 Hardware Standby Mode...................................................................................................678
21.4.1 Transition to Hardware Standby Mode ................................................................678
21.4.2 Recovery from Hardware Standby Mode.............................................................678
21.4.3 Timing for Hardware Standby Mode ...................................................................679
21.5 φ Clock Output Prohibit Function .....................................................................................680
21.5.1 Overview ..............................................................................................................680
21.5.2 Register Description ..............................................................................................680
21.5.3 Pin Status in Different Processing Modes .............................................................681
Rev. 3.0, 02/99, page xviii of 904

Section 22 Electrical Characteristics
(H8/539F) Dual Power Source System (VPP = 12 V).......................683
22.1 Absolute Maximum Ratings..............................................................................................683
22.2 Electrical Characteristics ...................................................................................................684
22.2.1 DC Characteristics................................................................................................684
22.2.2 AC Characteristics................................................................................................687
22.2.3 A/D Conversion Characteristics ...........................................................................693
22.2.4 Flash Memory Characteristics..............................................................................694
22.3 Operational Timing ...........................................................................................................695
22.3.1 Bus Timing...........................................................................................................695
22.3.2 Control Signal Timing..........................................................................................699
22.3.3 Clock Timing .......................................................................................................701
22.3.4 I/O Port Timing ....................................................................................................702
22.3.5 PWM Timer Output Timing.................................................................................702
22.3.6 IPU Timing...........................................................................................................703
22.3.7 SCI Input/Output Timing .....................................................................................704
22.3.8 Flash Memory Read Timing ................................................................................705
Section 23 Electrical Characteristics (H8/539F S-Mask model).......................707

23.1 Absolute Maximum Ratings (H8/539F S-Mask model)....................................................707
23.2 Electrical Characteristics (H8/539F S-Mask Model) ........................................................707
23.2.2 AC Characteristics (H8/539F S-Mask Model) .....................................................712
23.2.3 A/D Conversion Characteristics (H8/539F S-Mask Model) ................................717
23.2.4 Flash Memory Characteristics (H8/539F S-Mask Model) ...................................718
23.3 Operational Timing (H8/539F S-Mask Model).................................................................719
23.3.1 Bus Timing...........................................................................................................719
23.3.2 Control Signal Timing (H8/539F S-Mask Model) ...............................................723
23.3.3 Clock Timing (H8/539F S-Mask Model) .............................................................725
23.3.4 I/O Port Timing (H8/539F S-Mask Model)..........................................................726
23.3.6 IPU Timing (H8/569F S-Mask Model) ................................................................727
23.3.7 SCI Input/Output Timing (H8/569F S-Mask Model)...........................................728
Section 24 Electrical Characteristics (H8/539F A-Mask model) ......................729

24.1 Absolute Maximum Ratings (H8/539F A-Mask model) ...................................................729
24.2 Electrical Characteristics (H8/539F A-Mask Model)........................................................730
24.2.2 AC Characteristics (H8/539F A-Mask Model) ....................................................734
24.2.3 A/D Conversion Characteristics (H8/539F A-Mask Model)................................738
24.2.4 Flash Memory Characteristics (H8/539F A-Mask Model)...................................739
24.3 Operational Timing (H8/539F A-Mask Model) ................................................................741
Rev. 3.0, 02/99, page xix of 904
24.3.1 Bus Timing...........................................................................................................741
24.3.2 Control Signal Timing (H8/539F A-Mask Model)...............................................745
24.3.3 Clock Timing (H8/539F A-Mask Model) ............................................................747
24.3.4 I/O Port Timing (H8/539F A-Mask Model) .........................................................748
24.3.6 IPU Timing (H8/569F A-Mask Model) ...............................................................749
24.3.7 SCI Input/Output Timing (H8/569F A-Mask Model) ..........................................750
Appendix A Instruction Set............................................................................... 751

A.1 Instruction List ..................................................................................................................751
A.2 Machine-Language Instruction Codes...............................................................................758
A.3 Operation Code Map .........................................................................................................770
A.4 Number of States Required for Execution.........................................................................775
A.5 Instruction Set ...................................................................................................................785
A.5.1 Features ................................................................................................................785
A.5.2 Instruction Types..................................................................................................785
A.5.3 Basic Instruction Formats.....................................................................................786
A.5.4 Data Transfer Instructions ....................................................................................787
A.5.5 Arithmetic Instructions.........................................................................................791
A.5.6 Logic Instructions.................................................................................................798
A.5.7 Shift Instructions ..................................................................................................800
A.5.8 Bit Manipulation Instructions...............................................................................802
A.5.9 Branch Instructions ..............................................................................................804
A.5.10 System Control Instructions .................................................................................812
A.5.11 Short-Format Instructions ....................................................................................819
Appendix B Initial Values of CPU Registers.................................................... 820
Appendix C On-Chip Registers......................................................................... 821

C.1 H8/539F Dual power source model...................................................................................821
C.2 H8/539F S-Mask and A-Mask Models..............................................................................841
Appendix D Pin Function Selection.................................................................. 861

D.1 Port 3 Function Selection ..................................................................................................861
D.6 Port A Function Selection .................................................................................................870
Appendix E I/O Port Block Diagrams............................................................... 875
Appendix F Memory Maps ............................................................................... 896

Rev. 3.0, 02/99, page xx of 904
Appendix G Pin States.......................................................................................897
G.1 States of I/O Ports..............................................................................................................897
G.2 Pin States at Reset .............................................................................................................899
Appendix H Package Dimensions .....................................................................904
Rev. 3.0, 02/99, page xxi of 904

Section 1 Overview
1.1 Features
The H8/539F is a CMOS microcomputer unit (MCU) with an original Hitachi architecture. It
consists of an H8/500 CPU core plus supporting functions required in system configurations.
The H8/500 CPU features a highly orthogonal instruction set that permits addressing modes and
data sizes to be specified independently in each instruction. An internal 16-bit architecture and
16-bit, two-state access to both on-chip memory and external memory enhance the CPU's data-
processing capability and provide the speed needed for realtime control applications.
The on-chip supporting functions include RAM, ROM, timers, a serial communication interface
(SCI), A/D converter, and I/O ports. An on-chip data transfer controller (DTC) provides an
efficient way to transfer data in either direction between memory and I/O without using the CPU.
A ZTAT™* (Zero Turn-Around Time) version of the H8/539 is already available, with on-chip
ROM that can be freely programmed by the user. However, the PROM in the ZTAT version can
be programmed once only. Flash memory, on the other hand, is electrically programmable and
erasable, so that it can be reprogrammed while mounted on the circuit board. Moreover, the
single-transistor structure of flash memory-in contrast to the two-transistor structure of EEPROM-
makes it suitable for large-capacity applications.
Use of the H8/539F with on-chip flash memory allows the program and data to be modified even
after embedding in the application system, offering QTAT capability for small-lot, multiple-model
production, and the possibility of optimization tuning on an individual product basis, as well as
version upgrading and maintenance affer shipment.
Note: * ZTAT™ is a trademark of Hitachi, Ltd.
Table 1-1 lists the main features of the H8/539F.
Rev. 3.0, 02/99, page 1 of 904

Table 1-1 Features
Feature Description
H8/500 CPU General-register machine
• Eight 16-bit general registers
• Five 8-bit and two 16-bit control registers
High-speed operation
• Maximum clock rate : 16 MHz (oscillator frequency: 16 MHz)
Two operating modes

• Minimum mode: maximum 64-kbyte address space
• Maximum mode: maximum 1-Mbyte address space
Highly orthogonal instruction set

• Addressing modes and data size can be specified independently for each
instruction
Register and memory addressing modes

• Register-register operations
• Register-memory (or memory-register) operations
Instruction set optimized for C language

• Special short formats for frequently-used instructions and addressing
modes
Memory • RAM: 4-kbyte high-speed on-chip RAM

• ROM:
128-kbyte flash memory
(Eight large-block divisions, eight small-block divisions)
Dual power source system VPP = 12 V
• ROM:
128-kbyte flash memory
8 block divisions
(32 kB × 3, 28 kB × 1, 1 kB × 4)
S-mask and A-mask models single power source
Rev. 3.0, 02/99, page 2 of 904

Table 1-1 Features (cont)
Feature Description
16-bit integrated- Pulse unit with seven 16-bit timer channels
timer pulse unit Compare/Capture
(IPU) Channel Compare Registers Registers
Channel 1 4 4
Channels 2 to 5 2 each 2 each
Channels 6 & 7  2 each
Clock source can be selected independently for each channel

• Thirteen internal clock sources
• Three external clock sources
Two counting modes

• Free-running timer
• Interval timer
Three types of pulse output

• One-shot output
• Toggle output
• PWM output
Automatic measurement functions

• Programmable period counting
• Phase counting
Synchronization function
• Counters on different channels can be synchronized
Serial • Asynchronous or clocked synchronous mode (selectable)

communication • Full duplex: can send and receive simultaneously
interface (SCI)
• Dedicated on-chip baud rate generator
• Multiprocessor communication function (asynchronous mode)
A/D converter • Ten-bit resolution

• Twelve channels, single mode or scan mode selectable
• Can be triggered externally, or by IPU compare match
• Selectable analog conversion voltage range
Rev. 3.0, 02/99, page 3 of 904

Feature Description
I/O ports • 74 input/output pins
• 12 input-only pins
Interrupt controller • Five external interrupt pins (NMI, ,540 to ,543)

(INTC) • Thirty-nine internal interrupt sources
• Eight programmable priority levels
Data transfer • Can transfer data in both directions between memory and I/O without using
controller (DTC) the CPU
Wait-state • Can insert wait states (TW) in access to external I/O or memory
controller (WSC)
Bus controller • Address space can be partitioned into 16-bit-bus and 8-bit-bus areas
(BSC) • Address space can be partitioned into two-state-access and three-state-
access areas
• I/O ports can be expanded and reconfigured
Operating modes Seven operating modes

1. High-speed 16-bit bus modes, starting in 2-state 16-bit mode at reset
• Expanded minimum mode (mode 1)
• Expanded maximum modes (modes 3 and 4)
2. Low-speed 16-bit bus modes, starting in 3-state 8-bit mode on reset
release
• Expanded maximum mode (mode 5)
3. Low-speed 8-bit bus mode
4. Single-chip mode
• Maximum mode (mode 7)
Power-down state Three power-down modes

• Sleep mode
• Software standby mode
• Hardware standby mode
Watchdog timer • Timer overflow can generate reset output

(WDT) (H8/539F dual power source model only)
• Also usable as an interval timer
PWM timer • Duty cycle: 0% to 100%

• Resolution: 1/250
Rev. 3.0, 02/99, page 4 of 904

Feature Description
Multiplier • 16 bit × 16 bit signed or unsigned multiplication
(MULT) • Multiply-accumulate: 32 bits (saturating); 42 bits (non-saturating)
Other features • On-chip clock oscillator
Product lineup
Model Package ROM
Dual power HD64F5398F 112-pin Flash memory
source system plastic QFP (VPP = 12 V)
(FP-112)
Single power HD64F5398SF 112-pin Flash memory
source system plastic QFP (single power
(S-mask model) (FP-112) source)
Single power HD64F5398AF
source system
Noise reduction
(A-mask model)
Rev. 3.0, 02/99, page 5 of 904

1.2 Block Diagram
Figure 1-1 shows a block diagram of the H8/539F.
P17/D15
P16/D14
P15/D13
P14/D12
P13/D11
P12/D10
PB7/A15
PB6/A14
PB5/A13
PB4/A12
PB3/A11
PB2/A10
PC7/A7
PC6/A6
PC5/A5
PC4/A4
PC3/A3
PC2/A2
PC1/A1
PC0/A0
P27/D7
P26/D6
P25/D5
P24/D4
P23/D3
P22/D2
P21/D1
P20/D0
P11/D9
P10/D8
PB1/A9
PB0/A8
Port 2 Port 1 Port C Port B
PA6/BACK/T3OC2/TXD3
PA5/BREQ/T3OC1/RXD3
PA4/WAIT
Port A
PA3/A19/T5OC2/SCK3
PA2/A18/T5OC1/PW3
Data bus (lower)

EXTAL Clock Wait- RAM Flash memory PA1/A17/T4OC2/PW2
oscil- state Multiplier 4 kbytes 128 kbytes
XTAL lator controller PA0/A16/T4OC1/PW1
*1
Data bus (upper)

RESO/VPP P97/AN7
NMI Interrupt P96/AN6
controller P95/AN5
RES
H8/500 CPU P94/AN4
Port 9
STBY Data
transfer P93/AN3
Address bus
MD0 controller
MD1 P92/AN2
MD2 P91/AN1
PWM timer 10-bit A/D P90/AN0
HWR converter
(3 channels)
LWR (12 channels)
RD
AS P83/AN11
Watchdog
Port 8
φ timer P82/AN10
*2 VCC Bus controller
Address bus
P81/AN9
VCC P80/AN8
VCC
Data bus (upper)
VSS 16-bit
VSS integrated- Serial
VSS timer pulse communication P77/SCK2/PW2
Data bus (lower)
VSS unit (IPU) interface P76/SCK1/PW1

VSS (3 channels)
P75/RXD2
VSS
Port 7
AVCC P74/TXD2
AVSS P73/RXD1
VREF P72/TXD1
P71/IRQ1/ADTRG
P70/IRQ0
Port 3 Port 4 Port 5 Port 6

P60/IRQ2/PW3
P35/T2OC2
P34/T2OC1
P33/T1OC4
P32/T1OC3
P31/T1OC2
P30/T1OC1
P47/T7IOC2
P46/T7IOC1
P45/T6IOC2
P44/T6IOC1
P43/T5IOC2
P42/T5IOC1
P41/T4IOC2
P40/T4IOC1
P57/T3IOC2
P56/T3IOC1
P55/T2IOC2
P54/T2IOC1
P53/T1IOC4
P52/T1IOC3
P51/T1IOC2
P50/T1IOC1
P61/IRQ3
P64/TCLK3
P63/TCLK2
P62/TCLK1
Note: *1 In the dual power source model (VPP = 12 V), this is the RESO (output)/VPP (input) pin.
In the S-mask and A-mask models (single power source), it is the FWE (input) pin.
*2 In the A-mask model (single power source), pin 1 (FP-112) is the VCL pin, not the VCC pin.
Figure 1-1 H8/539F Block Diagram

Rev. 3.0, 02/99, page 6 of 904
1.3 Pin Descriptions
1.3.1 Pin Arrangement
Figure 1-2 (a) shows the pin arrangement of the H8/539F (FP-112 package).
Rev. 3.0, 02/99, page 7 of 904

PA5/BREQ/T3OC1/RXD3
PA6/BACK/T3OC2/TXD3
PA3/A19/T5OC2/SCK3
PA2/A18/T5OC1/PW3
PA1/A17/T4OC2/PW2
PA0/A16/T4OC1/PW1
PA4/WAIT
PB7/A15
PB6/A14
PB5/A13
PB4/A12
PB3/A11
EXTAL
STBY
XTAL
HWR
AVCC
LWR
RES
MD2
MD1
MD0
NMI
VCC
VSS
RD
AS
φ
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
VREF 85 56 PB2/A10
P90/AN0 86 55 PB1/A9
P91/AN1 87 54 PB0/A8
P92/AN2 88 53 VSS
P93/AN3 89 52 PC7/A7
P94/AN4 90 51 PC6/A6
P95/AN5 91 50 PC5/A5
P96/AN6 92 49 PC4/A4
P97/AN7 93 48 PC3/A3
P80/AN8 94 47 PC2/A2
P81/AN9 95 46 PC1/A1
P82/AN10 96 45 PC0/A0
P83/AN11 97 44 VCC
AVSS 98 Top view 43 P17/D15
VSS 99 (FP-112) 42 P16/D14
P70/IRQ0 100 41 P15/D13
P71/IRQ1/ADTRG 101 40 P14/D12
P72/TXD1 102 39 P13/D11
P73/RXD1 103 38 P12/D10
P74/TXD2 104 37 P11/D9
P75/RXD2 105 36 P10/D8
P76/SCK1/PW1 106 35 VSS
P77/SCK2/PW2 107 34 P27/D7
P60/IRQ2/PW3 108 33 P26/D6
P61/IRQ3 109 32 P25/D5
P62/TCLK1 110 31 P24/D4
P63/TCLK2 111 30 P23/D3
P64/TCLK3 112 29 P22/D2
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
1
2
3
4
5
6
7
8
9
RESO*/VPP
VSS
P20/D0
P21/D1
VSS
P30/T1OC1
P31/T1OC2
P32/T1OC3
P33/T1OC4
P34/T2OC1
P35/T2OC2
P50/T1IOC1
P51/T1IOC2
P52/T1IOC3
P53/T1IOC4
P54/T2IOC1
P55/T2IOC2
P56/T3IOC1
P57/T3IOC2
P40/T4IOC1
P41/T4IOC2
P42/T5IOC1
P43/T5IOC2
P44/T6IOC1
P45/T6IOC2
P46/T7IOC1
P47/T7IOC2
VCC
Note: *Pin 19 is the RESO/VPP pin in the dual power source

model (VPP = 12 V), and the FWE pin in the S-mask H8/539
and A-mask models. (The S-mask and A-mask
models do not have a RESO output.) HD64F5398F
JAPAN
Pin 1
Figure 1-2 (a) H8/539F Pin Arrangement (FP-112, Top View)
Rev. 3.0, 02/99, page 8 of 904

Figure 1-2 (b) shows the pin arrangement of the H8/539F S-mask model (FP-112 package). The
pin arrangement is the same for the S-mask model (single power source) and dual power source
model, but the function of the FWE pin (pin 19) is different.
PA5/BREQ/T3OC1/RXD3
PA6/BACK/T3OC2/TXD3
PA3/A19/T5OC2/SCK3
PA2/A18/T5OC1/PW3
PA1/A17/T4OC2/PW2
PA0/A16/T4OC1/PW1
PA4/WAIT
PB7/A15
PB6/A14
PB5/A13
PB4/A12
PB3/A11
EXTAL
STBY
MD2 *
XTAL
HWR
AVCC
LWR
RES
MD1
MD0
NMI
VCC
VSS
RD
AS
φ
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
VREF 85 56 PB2/A10
P90/AN0 86 55 PB1/A9
P91/AN1 87 54 PB0/A8
P92/AN2 88 53 VSS
P93/AN3 89 52 PC7/A7
P94/AN4 90 51 PC6/A6
P95/AN5 91 50 PC5/A5
P96/AN6 92 49 PC4/A4
P97/AN7 93 48 PC3/A3
P80/AN8 94 47 PC2/A2
P81/AN9 95 46 PC1/A1
P82/AN10 96 45 PC0/A0
P83/AN11 97 44 VCC
VSS 99 (FP-112) 42 P16/D14
P70/IRQ0 100 41 P15/D13
P71/IRQ1/ADTRG 101 40 P14/D12
P72/TXD1 102 39 P13/D11
P73/RXD1 103 38 P12/D10
P74/TXD2 104 37 P11/D9
P75/RXD2 105 36 P10/D8
P76/SCK1/PW1 106 35 VSS
P77/SCK2/PW2 107 34 P27/D7
P60/IRQ2/PW3 108 33 P26/D6
P61/IRQ3 109 32 P25/D5
P62/TCLK1 110 31 P24/D4
P63/TCLK2 111 30 P23/D3
P64/TCLK3 112 29 P22/D2
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
1
2
3
4
5
6
7
8
9
VSS
P20/D0
P21/D1
P30/T1OC1
P31/T1OC2
P32/T1OC3
P33/T1OC4
P34/T2OC1
P35/T2OC2
P50/T1IOC1
P51/T1IOC2
P52/T1IOC3
P53/T1IOC4
P54/T2IOC1
P55/T2IOC2
P56/T3IOC1
P57/T3IOC2
P40/T4IOC1
P41/T4IOC2
P42/T5IOC1
P43/T5IOC2
P44/T6IOC1
P45/T6IOC2
P46/T7IOC1
P47/T7IOC2
VSS
*FWE
VCC
Notes: * (1) Pin 19 is the /VPP pin in the dual power source
model (VPP = 12 V), and the FWE pin* in the S-mask
model (single power source). (* The S-mask model H8/539
does not have a output.) S
HD64F5398F
(2) Under no circumstances apply 12 V to the JAPAN
S-mask model (single power source), as this
may cause permanent damage to the chip. Pin 1
Figure 1-2 (b) H8/539F S-Mask Model Pin Arrangement (FP-112, Top View)
Rev. 3.0, 02/99, page 9 of 904

Figure 1.2 (c) shows the pin arrangement of the H8/539F A-mask model. The pin arrangements of
the A-mask model (single power source) and the dual power source model are the same, with the
exception of VCL (pin 1). Also, the function of the FWE pin (pin 19) is different. The pin
arrangements of the A-mask and S-mask models (single power source) and the dual power source
model are the same, with the exception of VCL (pin 1). Also, the function of the FWE pin (pin 19)
is identical.
Rev. 3.0, 02/99, page 10 of 904

PA5/BREQ/T3OC1/RXD3
PA6/BACK/T3OC2/TXD3
PA3/A19/T5OC2/SCK3
PA2/A18/T5OC1/PW3
PA1/A17/T4OC2/PW2
PA0/A16/T4OC1/PW1
PA4/WAIT
PB7/A15
PB6/A14
PB5/A13
PB4/A12
PB3/A11
EXTAL
MD2*1
STBY
XTAL
HWR
AVCC
LWR
RES
MD1
MD0
NMI
VCC
VSS
RD
AS
φ
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
VREF 85 56 PB2/A10
P90/AN0 86 55 PB1/A9
P91/AN1 87 54 PB0/A8
P92/AN2 88 53 VSS
P93/AN3 89 52 PC7/A7
P94/AN4 90 51 PC6/A6
P95/AN5 91 50 PC5/A5
P96/AN6 92 49 PC4/A4
P97/AN7 93 48 PC3/A3
P80/AN8 94 47 PC2/A2
P81/AN9 95 46 PC1/A1
P82/AN10 96 45 PC0/A0
P83/AN11 97 44 VCC
VSS 99 (FP-112) 42 P16/D14
P70/IRQ0 100 41 P15/D13
P71/IRQ1/ADTRG 101 40 P14/D12
P72/TXD1 102 39 P13/D11
P73/RXD1 103 38 P12/D10
P74/TXD2 104 37 P11/D9
P75/RXD2 105 36 P10/D8
P76/SCK1/PW1 106 35 VSS
P77/SCK2/PW2 107 34 P27/D7
P60/IRQ2/PW3 108 33 P26/D6
P61/IRQ3 109 32 P25/D5
P62/TCLK1 110 31 P24/D4
P63/TCLK2 111 30 P23/D3
P64/TCLK3 112 29 P22/D2
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
1
2
3
4
5
6
7
8
9
VSS
P20/D0
P21/D1
P30/T1OC1
P31/T1OC2
P32/T1OC3
P33/T1OC4
P34/T2OC1
P35/T2OC2
P50/T1IOC1
P51/T1IOC2
P52/T1IOC3
P53/T1IOC4
P54/T2IOC1
P55/T2IOC2
P56/T3IOC1
P57/T3IOC2
P40/T4IOC1
P41/T4IOC2
P42/T5IOC1
P43/T5IOC2
P44/T6IOC1
P45/T6IOC2
P46/T7IOC1
P47/T7IOC2
*1FWE
VSS
VCL
*2 0.1µF
Note: 1. (1) Pin19 is the RESO/VPP pin in the dual power source H8/539
model (VPP = 12 V), and the FWE pin* in the A-mask A
model. (*The A-mask model does not have a RESO HD64F5398F
output.) JAPAN
(2) 12 V must not be applied to the A-mask Pin 1

model (single power source), as this may
cause permanent damage to the chip.
2 . (1) Connect a 0.1µF capacitor between VCL and VSS (located near the pin) .
(2) The VCC power supply must not be connected to the VCL pin.
Figure 1-2 (c) H8/539F A-Mask Model Pin Arrangement (FP-112, Top View)
Rev. 3.0, 02/99, page 11 of 904

1.3.2 Pin Functions
(1) Pin Assignments in Each Operating Mode: Table 1-2 lists the assignments of the pins of the
FP-112 package in each operating mode.
Table 1-2 Pin Assignments in Each Operating Mode (FP-112)

Expanded Minimum Expanded Maximum Single-Chip
Modes Modes Mode
Modes Modes
No. 1 and 6 Mode 2 3 and 5 Mode 4 Mode 7 Notes
1 VCC VCC VCC VCC VCC Dual power
source S-mask
model
VCL VCL VCL VCL VCL A-mask model
2 P50/T1IOC1 P50/T1IOC1 P50/T1IOC1 P50/T1IOC1 P50/T1IOC1
10 VSS VSS VSS VSS VSS
19 5(62/VPP 5(62/VPP 5(62/VPP 5(62/VPP 5(62/VPP Dual power
source (VPP=12V)
1 1 1 1 1
FWE* FWE* FWE* FWE* FWE* S Mask model
(single power
source)
Rev. 3.0, 02/99, page 12 of 904

Modes Modes Mode
Modes Modes
20 P30/T1OC1 P30/T1OC1 P30/T1OC1 P30/T1OC1 P30/T1OC1
2 2 2
27 D0* P20 D0* D0* P20
2 2 2
28 D1* P21 D1* D1* P21
2 2
29 D2* P22 D2* D2 P22
2 2
30 D3* P23 D3* D3 P23
2 2
31 D4* P24 D4* D4 P24
2 2
32 D5* P25 D5* D5 P25
2 2
33 D6* P26 D6* D6 P26
2 2
34 D7* P27 D7* D7 P27
36 D8 D8 D8 D8 P10
37 D9 D9 D9 D9 P11
38 D10 D10 D10 D10 P12
39 D11 D11 D11 D11 P13
40 D12 D12 D12 D12 P14
41 D13 D13 D13 D13 P15
42 D14 D14 D14 D14 P16
43 D15 D15 D15 D15 P17
Rev. 3.0, 02/99, page 13 of 904

Modes Modes Mode
Modes Modes
44 VCC VCC VCC VCC VCC
45 A0 PC0/A0 A0 PC0/A0 PC0
46 A1 PC1/A1 A1 PC1/A1 PC1
47 A2 PC2/A2 A2 PC2/A2 PC2
48 A3 PC3/A3 A3 PC3/A3 PC3
49 A4 PC4/A4 A4 PC4/A4 PC4
50 A5 PC5/A5 A5 PC5/A5 PC5
51 A6 PC6/A6 A6 PC6/A6 PC6
52 A7 PC7/A7 A7 PC7/A7 PC7
54 A8 PB0/A8 A8 PB0/A8 PB0
55 A9 PB1/A9 A9 PB1/A9 PB1
56 A10 PB2/A10 A10 PB2/A10 PB2
57 A11 PB3/A11 A11 PB3/A11 PB3
58 A12 PB4/A12 A12 PB4/A12 PB4
59 A13 PB5/A13 A13 PB5/A13 PB5
60 A14 PB6/A14 A14 PB6/A14 PB6
61 A15 PB7/A15 A15 PB7/A15 PB7
62 PA0/T4OC1/ PA0/T4OC1/ A16 PA0/A16/ PA0/T4OC1/
PW1 PW1 PW1 PW1
PW2 PW2 PW2 PW2
PW3 PW3 PW3 PW3
SCK3 SCK3 SCK3 SCK3
66 PA4/:$,7 PA4/:$,7 PA4/:$,7 PA4/:$,7 PA4
67 PA5/%5(4/ PA5/%5(4/ PA5/%5(4/ PA5/%5(4/ PA5/T3OC1/
T3OC1/RXD3 T3OC1/RXD3 T3OC1/RXD3 T3OC1/RXD3 RXD3
68 PA6/%$&. PA6/%$&. PA6/%$&. PA6/%$&. PA6/T3OC2
T3OC2/TXD3 T3OC2/TXD3 T3OC2/TXD3 T3OC2/TXD3 TXD3
69 φ φ φ φ φ
Rev. 3.0, 02/99, page 14 of 904

Modes Modes Mode
Modes Modes
70 67%< 67%< 67%< 67%< 67%<
71 5(6 5(6 5(6 5(6 5(6
72 NMI NMI NMI NMI NMI
74 EXTAL EXTAL EXTAL EXTAL EXTAL
75 XTAL XTAL XTAL XTAL XTAL
76 VCC VCC VCC VCC VCC
77 $6 $6 $6 $6 $6
78 5' 5' 5' 5' 5'
79 +:5 +:5 +:5 +:5 +:5
80 /:5 /:5 /:5 /:5 /:5
81 MD0 MD0 MD0 MD0 MD0
82 MD1 MD1 MD1 MD1 MD1
1 1 1 1 1
83 MD2* MD2* MD2* MD2* MD2*
84 AVCC AVCC AVCC AVCC AVCC
85 VREF VREF VREF VREF VREF
86 P90/AN0 P90/AN0 P90/AN0 P90/AN0 P90/AN0
Rev. 3.0, 02/99, page 15 of 904

Modes Modes Mode
Modes Modes
98 AVSS AVSS AVSS AVSS AVSS
100 P70/,540 P70/,540 P70/,540 P70/,540 P70/,540
101 P71/,541/ P71/,541/ P71/,541/ P71/,541/ P71/,541/
$'75* $'75* $'75* $'75* $'75*
102 P72/TXD1 P72/TXD1 P72/TXD1 P72/TXD1 P72/TXD1
103 P73/RXD1 P73/RXD1 P73/RXD1 P73/RXD1 P73/RXD1
104 P74/TXD2 P74/TXD2 P74/TXD2 P74/TXD2 P74/TXD2
105 P75/RXD2 P75/RXD2 P75/RXD2 P75/RXD2 P75/RXD2
106 P76/SCK1/ P76/SCK1/ P76/SCK1/ P76/SCK1/ P76/SCK1/
PW1 PW1 PW1 PW1 PW1
107 P77/SCK2/ P77/SCK2/ P77/SCK2/ P77/SCK2/ P77/SCK2/
PW2 PW2 PW2 PW2 PW2
108 P60/,542/ P60/,542/ P60/,542/ P60/,542/ P60/,542/
PW3 PW3 PW3 PW3 PW3
109 P61/,543 P61/,543 P61/,543 P61/,543 P61/,543
110 P62/TCLK1 P62/TCLK1 P62/TCLK1 P62/TCLK1 P62/TCLK1
Notes: For the PROM mode, see section 19, "Flash Memory (H8/539F)" and section 20, "Flash
Memory (H8/539F S-Mask and A-Mask Models)".
1. 12 V must not be applied to the S-mask or A-mask model (single power source), as this
will permanently damage the device.
2. In modes 5 and 6, the external bus space has a 16-bit bus width, but an 8-bit bus width
is set after a reset. In this case, the upper half of the data bus (D15 to D8) is enabled,
and the lower half (D7 to D0) is disabled. The bus width can be changed to 16 bits (D15
to D0) by software after setting the BCRE bit to 1 in the bus control register (BCR). In
modes 1, 3, and 4, the external bus space has a 16-bit bus width (D15 to D0) after a
reset, but this can be changed to 8 bits by a byte area top register (ARBT) setting. In
this case, the upper half of the data bus (D15 to D8) is enabled, and the lower half (D7 to
D0) is disabled. For details of the settings, see section 16, Bus Controller.
Rev. 3.0, 02/99, page 16 of 904

(2) Pin Functions: Table 1-3 indicates the function of each pin.
Table 1-3 Pin Functions
Type Symbol Pin No. I/O Name and Function

Power VCC 1 Input Power: Connected to the power supply (4.5 V to
(Dual power- 5.5 V). Connect all VCC pins to the system power
source S-mask supply (4.5 V to 5.5 V). The chip will not operate
model) if any VCC pin is left unconnected.
VCL Output VCL pin: Not necessary to connect to the power
(A-mask supply (4.5 to 5.5 V). Connect to the VSS pin via a
model) 0.1 µF capacitor (located near the pin).
VCC 44, 76 Input Power: Connected to the power supply (4.5 V to
5.5 V). Connect all VCC pins to the system power
supply (4.5 V to 5.5 V). The chip will not operate
if any VCC pin is left unconnected.
VSS 10, 26, Input Ground: Connected to ground (0 V). Connect all
35, 53, VSS pins to the 0-V system power supply. The
73, 99 chip will not operate if any VSS pin is left
unconnected.
Clock XTAL 75 Input Crystal: Connected to a crystal resonator. The
frequency should be equal to the desired system
clock frequency (φ). If an external clock is input at
the EXTAL pin, input a complementary clock at
XTAL.
EXTAL 74 Input Crystal/external clock: Connected to a crystal
resonator or external clock. The frequency should
be equal to the desired system clock frequency
(φ). An external clock can also be input from the
EXTAL pin. See section 9.2, "Oscillator Circuit"
for examples of connections at XTAL and EXTAL.
φ 69 Output System clock: Supplies the system clock (φ) to
peripheral devices.
System %$&. 68 Output Bus request acknowledge: Indicates that the
control bus right has been granted to an external device.
A device requesting the bus sends a %5(4 signal
to the microcontroller. The microcontroller replies
with a %$&. signal.
%5(4 67 Input Bus request: Sent by an external device to the
microcomputer chip to request the bus right. Bus
acquisition should be confirmed with the %$&.
signal.
67%< 70 Input Standby: Input pin for transition to the hardware
standby mode (a power-down state).
5(6 71 Input Reset: Input pin for transition to the reset state.
Rev. 3.0, 02/99, page 17 of 904

Address A19–A0 65–54, Output Address bus: Address output pins.
bus 52–45
1
Data bus D15–D0* 43–36, Input/ Data bus: Sixteen-bit bidirectional data bus.
34–27 Output
Bus :$,7 66 Input Wait: Requests insertion of wait states (T W) in
control external-device access cycles by the CPU; used
signals for interfacing to low-speed external devices.
$6 77 Output Address strobe: Indicates valid address output
on the address bus during external-device access.
5' 78 Output Read: Indicates reading of data from the data bus
during external-device access. The CPU latches
read data at the rising edge of 5'.
+:5 79 Output High write: Indicates output of data on the upper
data bus (D15 to D8) during external-device access.
/:5 80 Output Low write: Indicates output of data on the lower
data bus (D7 to D0) during external-device access.
Interrupt NMI 72 Input Nonmaskable interrupt: Nonmaskable interrupt
signals request signal. The input edge can be selected in
the NMI control register (NMICR).
,540 100 Input Interrupt request 0 to 3: Maskable interrupt
IRQ1 101 request signals. The type of input can be selected
,542 108 in the IRQ control register (IRQCR).
,543 109
Rev. 3.0, 02/99, page 18 of 904

2
Operating MD2* 83 Input Mode 2 to mode 0: Input pins for setting the
mode MD1 82 operating mode. The following table lists the
control MD0 81 operating modes and bus widths.
H8/500
CPU Exter-
Pin Settings
Operating Operating On-Chip nal
1
MD2* MD1 MD0 Mode Mode ROM Bus
0 0 0 Do not use
0 0 1 Mode 1 Expanded Disabled 16 bits
minimum
0 1 0 Mode 2 Expanded Enabled 8 bits
minimum
maximum
1 0 0 Mode 4 Expanded Enabled 16 bits
maximum
maximum
minimum
1 1 1 Mode 7 Single chip Enabled 
maximum
Serial TXD1 102 Output Transmit data 1, 2, and 3: Serial transmit data
commu- TXD2 104 output pins for SCI1, SCI2, and SCI3.
nication TXD3 68
interface RXD1 103 Input Receive data 1, 2, and 3: Serial receive data
(SCI)
RXD2 105 input pins for SCI1, SCI2, and SCI3.
RXD3 67
SCK1 106 Input/ Serial clock 1, 2, and 3: Serial clock input/output
SCK2 107 Output pins for SCI1, SCI2, and SCI3. Used for input and
SCK3 65 output of the serial clock in clocked synchronous
mode, and of the SCI operating clock in
asynchronous mode.
PWM PW1 62 Output PWM1, PWM2, and PWM3 output: Output pins
timer 106 for PWM1, PWM2, and PWM3.
PW2 63 Output
107
PW3 64 Output
108
Rev. 3.0, 02/99, page 19 of 904

16-bit T1IOC1 2 Input/ Input capture/output compare 1 to 4 (channel
integrated- T1IOC2 3 Output 1): Input capture input or output compare output
timer pulse T1IOC3 4 pins for IPU channel 1.
unit (IPU) T1IOC4 5
T1OC1 20 Output Output compare 1 to 4 (channel 1): Dedicated
T1OC2 21 output compare output pins for IPU channel 1.
T1OC3 22
T1OC4 23
T2IOC1 6 Input/ Input capture/output compare 1 and 2 (channel
T2IOC2 7 Output 2): Input capture input or output compare output
pins for IPU channel 2.
T2OC1 24 Output Output compare 1 and 2 (channel 2): Dedicated
T3OC1 67 Output Output compare 1 and 2 (channel 3):
T3OC2 68 Dedicated output compare output pins for IPU
channel 3.
TCLK1 110 Input Timer clock 1 to 3 (all channels): IPU external
TCLK2 111 clock input pins. All channels can select these
TCLK3 112 clock inputs.
Rev. 3.0, 02/99, page 20 of 904

A/D AN11–AN0 97–86 Input Analog input 11 to 0: Analog input pins for the
converter A/D converter.
VREF 85 Input Reference power supply (VREF ≤ AVCC): Input pin
for the A/D converter's reference voltage. Apply a
voltage corresponding to the A/D conversion full-
scale value.
AVCC 84 Input Analog power supply: Power supply pin for
analog circuits in the A/D converter. Connect to a
stable +5-V analog power supply separate from
the other power supply pins.
AVSS 98 Input Analog ground: Ground pin for analog circuits in
the A/D converter. Connect to a stable 0-V
analog power supply separate from the other
power supply pins.
$'75* 101 Input A/D trigger: Trigger input for starting A/D
conversion. The A/D conversion start time is
specified by the falling edge of $'75*.
Watchdog 5(62 19 Output Reset output: If reset output is selected, a low
timer pulse is output for 132 cycles when the watchdog
timer overflows. 5(62 is an open-drain output
pin and should be pulled up to VCC (+5 V)
externally, regardless of whether reset output is
selected or not. The S-mask and A-mask models
do not have this function.
Flash Dual power 19 Input Program power supply: The flash memory
Memory source type programming power supply pin. Connect to the
VPP programming power supply (12 V) when
programming and erasing.
Single power Flash write enable: Enables program mode
source type setting.
(S-mask
2
model) FWE*
I/O ports P17–P10 43 –36 Input/ Port 1: 8-bit input/output port. The direction of
Output each bit can be selected in the port 1 data
direction register (P1DDR).
P27–P20 34–27 Input/ Port 2: 8-bit input/output port. Input or output can
Output be set for each bit in the port 2 data direction
register (P2DDR).
Rev. 3.0, 02/99, page 21 of 904

I/O ports P35–P30 25–20 Input/ Port 3: 6-bit input/output port. Input or output can
register (P3DDR). LEDs can be driven directly
(10-mA sink).
P47–P40 18–11 Input/ Port 4: 8-bit input/output port with Schmitt-trigger
Output inputs. Input or output can be set for each bit in
the port 4 data direction register (P4DDR).
P57–P50 9–2 Input/ Port 5: 8-bit input/output port with Schmitt-trigger
Output inputs. Input or output can be set for each bit in
the port 5 data direction register (P5DDR). LEDs
can be driven directly (10-mA sink).
register (P6DDR).
register (P7DDR).
P83–P80 97–94 Input Port 8: 4-bit input port.
P97–P90 93–86 Input Port 9: 8-bit input port.
PA6–PA0 68–62 Input/ Port A: 7-bit input/output port. Input or output can
Output be set for each bit in the port A data direction
register (PADDR).
PB7–PB0 61–54 Input/ Port B: 8-bit input/output port with MOS input pull-
Output up transistors. Input or output can be set for each
bit in the port B data direction register (PBDDR).
PC7–PC0 52–45 Input/ Port C: 8-bit input/output port with MOS input pull-
Output up transistors. Input or output can be set for each
bit in the port C data direction register (PCDDR).
Notes: 1. When the external bus space uses an 8-bit bus width, D15 to D8 are enabled and D7 to D0
are disabled.
2. 12 V must not be applied to the S-mask or A-mask model (single power source), as this
will permanently damage the device.
Rev. 3.0, 02/99, page 22 of 904

1.4 Notes on S-Mask and A-Mask Models (Single Power Source)
There are three models of the H8/539F with on-chip flash memory: a dual power source model
and two single power source models (S-mask and A-mask). Points to be noted when using the
H8/539F single power source S-mask and A-mask models are given below.
1.4.1 Voltage Application
12 V must not be applied to the S-mask or A-mask model (single power source), as this will
permanently damage the device.
The flash memory programming power source for the S-mask and A-mask models (single power
source) is VCC.
The programming power source for the dual power source model was the VPP pin (12 V), but
there is no VPP pin in the single power source models. In the S-mask and A-mask models the
FWE pin is provided at the same pin position as the VPP pin in the dual power source model, but
FWE is not a power source pin-it is used to control flash memory write enabling.
Also, in boot mode, 12 V must be applied to the MD2 pin in the dual power source model, but this
is not necessary in the S-mask and A-mask models (single power source).
The maximum rating of the FWE and MD2 pins in the S-mask and A-mask models (single power
source) is VCC +0.3 V. Applying a voltage in excess of the maximum rating will permanently
damage the device.
Do not select the HN28F101 programmer setting for the S-mask or A-mask model (single power
source). If this setting is made by mistake, 12.0 V may be applied to the FWE pin, causing
permanent damage to the device.
When using a PROM programmer to program the on-chip flash memory in the S-mask or A-mask
model (single power source), use a PROM programmer that supports Hitachi microcomputer
device types with 128-kbyte on-chip flash memory.
Rev. 3.0, 02/99, page 23 of 904

1.4.2 Product Type Names and Markings
Table 1-4 shows examples of product type names and markings for the H8/539F (dual power
source model), H8/539F S-mask model (single power source), and the H8/539F A-mask model
(single power source), and the differences in flash memory programming power source.
Table 1-4 Differences in H8/539F and H8/539F S-Mask and A-Mask Models Markings
Dual Power Source Single Power Source Single Power Source

Model: Model: Model:
H8/539F H8/539F S-Mask Model H8/539F A-Mask Model
Product type nameHD64F5398F16 HD64F5398SF16 HD64F5398AF16
Sample markings
H8/539 H8/539 H8/539

S A
HD64F539816 HD64F539816 HD64F5398F16
JAPAN JAPAN JAPAN
"S" is printed above "A" is printed above

the type name the type name
Flash memory VPP power source VCC power source VCC power source
programming (12.0 ±0.6 V) (5.0 ±10%) (5.0 ±10%)
power source
1.4.3 Differences in S-Mask and A-Mask Models
Table 1-5 shows the differences between the H8/539F (dual power source model) and H8/539F S-
mask and A-mask models (single power source model).
Rev. 3.0, 02/99, page 24 of 904

Table 1-5 Differences between H8/539F and H8/539F S-Mask and A-Mask Models
Item Dual Power Source Model: Single Power Source Model:

H8/539F H8/539F S-Mask and A-Mask Models
Program/ 12 V must be applied to VPP power 12 V application not required.
erase voltage source pin from off-chip VCC single power source programming
VPP (FWE) pin Dual function as VPP power FWE pin function only.
function source and RESO output RESO pin function eliminated
Programming • PROM mode • PROM mode
modes
• On-board: Boot mode • On-board: Boot mode
User program mode User program mode
Operating modes Modes 4 and 7 Modes 4 and 7

allowing on-board
programming
On-board Byte-unit programming 32-byte-unit programming
programming unit
Programming Select Hitachi stand-alone flash Special programming mode setting
with PROM memory HN28F101 setting required. Use of PROM programmer
programmer that supports Hitachi microcomputer
device types with 128-kbyte on-chip
flash memory (128-byte-unit fast page
programming)
Rev. 3.0, 02/99, page 25 of 904

Table 1-5 Differences between H8/539F and H8/539F S-Mask and A-Mask Models (cont)

Boot mode MD2 = VPP/RESO = 12 V FWE = 1 input
setting method Reset release Mode 4: Set mode 5
Mode 7: Set mode 6
Reset release
Pin
Mode MD2 MD1 MD0 FWE
Mode 4 1 0 1 1
Mode 7 1 1 0 1
User program VPP/RESO = 12 V FWE = 1
mode setting
method
Programming tMDS tMDS
RES RES
mode timing
MD0 to MD1 MD0 to MD2
12 V 5V
MD2 FWE
min 0 µs
12 V
VPP
tMDS: 4tcyc (min.) tMDS: 4tcyc (min.)
Prewrite Required before erasing Not required

processing
Multiple-block Multiple blocks can be erased Block-unit erasing. Multiple blocks
erase simultaneously (verification performed cannot be erased simultaneously
block by block, only unerased blocks (Erase procedure is also different)
re-erased)
Programming Block corresponding to programming Settings at left not required
processing address must be set in EBR1/2 (Programming procedure is also
registers before programming different)
Rev. 3.0, 02/99, page 26 of 904


EBR register EBR1, EBR2 EBR1
configuration (See section 19 for bit functions) (See section 20 for bit functions)
Memory map EB0 (1 kbyte)
LB7 (12 kbytes)
(block EB1 (1 kbyte)
SB0 (512 bytes) EB2 (1 kbyte)
configuration)
/////////Shadow area
SB2 (512 bytes)
Page 0 16 kbytes Page 0 16 kbytes
SB3 (512 bytes)
SB4 (512 bytes)
EB4 (12 kbytes)
SB5 (512 bytes)
SB6 (512 bytes)
SB7 (512 bytes)
EB0 (1 kbyte)
LB7 (12 kbytes)
EB1 (1 kbyte)
SB2 (512 bytes)
SB3 (512 bytes)
EB4 (28 kbytes)
SB4 (512 bytes)
SB5 (512 bytes)
SB6 (512 bytes)
SB7 (512 bytes)
LB6 (16 kbytes)

EB5 (32 kbytes)
Page 1 Page 1
to 128 kbytes to 128 kbytes
Page 2 LB5 (16 kbytes) Page 2
LB4 (16 kbytes)
EB6 (32 kbytes)

LB3 (16 kbytes)
LB2 (16 kbytes)
LB1 (16 kbytes)

EB7 (32 kbytes)
LB0 (16 kbytes)
Block configuration: 16 blocks Block configuration: 8 blocks

16 kbytes × 7: LB0 to LB6 32 kbytes × 3: EB5 to EB7
12 kbytes × 1: LB7 28 kbytes × 1: EB4
512 bytes × 8: SB0 to SB7 1 kbyte × 4: EB0 to EB3
Reset during Drive 5(6 pin low for at least Drive 5(6 pin low for at least 20
operation 6 system clock cycles (6φ) system clock cycles (20φ)
(5(6 pulse width tRESW = (5(6 pulse width tRESW =
min. 6.0 tcyc) min. 20 tcyc)
Rev. 3.0, 02/99, page 27 of 904


FLMCR register 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
VPP VPPE − − EV PV E P FWE SWE ESU PSU EV PV E P
(See section 19 for bit functions) (See section 20 for bit functions)
RAM emulation On-chip RAM Flash memory On-chip RAM Flash memory
block configuration EE80 0000 EE80 0000
////////Shading
F000 F000
shows areas for EB0
which ROM/RAM F200 2FFF 03FF
overlapping is 3000 F3FF 0400
SB0 F400
permitted during F400 3200 EB1
F600 F67F
RAM emulation SB1 F7FF F67F
F680 3400 F800 F680 07FF
SB2 0800
F800
3600 EB2
FA00 SB3
3800 0BFF
SB4 FBFF 0C00
FC00
3A00 EB3
FDFF
SB5
FE7F FE7F 0FFF
3C00
SB6 1000
3D00
SB7
3FFF 3FFF
FLMER register 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
OVLPE − − − A11E A10E A9E − OVLPE − − − A11E A10E − −
Bit 1 = A9E bit Bit 1 = Reserved

(See section 19 for bit functions) (See section 20 for bit functions)
RAMCR register 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
RAME1 − RAME2 − − RAM2 RAM1 RAM0 RAME1 − RAME2 − − RAM2 RAM1 −
Bit 0 = RAM0 bit Bit 0 = Reserved

(See sections 17 and 19 for bit (See sections 18 and 20 for bit
functions) functions)
Details concerning See section 19, Flash Memory See section 20, Flash Memory
flash memory (H8/539F) Dual Power System (H8/539F, S-Mask and A-Mask Models:
(VPP = 12 V) Single Power Source)
(Programming/erasing procedure, etc.,
is also different)
Electrical See section 22, See section 23, Electrical
characteristics ElectricalCharacteristics (H8/539F) Characteristics (H8/539F S-Mask
Model) Section 24, Electrical
Characteristics (H8/539F A-Mask
Model)
(Wait times during programming/
erasing, etc., are also different)
List of registers See Appendix C, See Appendix C, Registers, (2)
Registers, (1) H8/539F H8/539F S-Mask and A-Mask Models
Rev. 3.0, 02/99, page 28 of 904

1.5 H8/539F A-Mask Overview
The A-mask version of the H8/539F is a microcomputer developed based on the S-mask (single
power source) model and incorporating EMI noise reduction. An on-chip step-down circuit is
built-in to reduce EMI noise, the output buffers have been further miniaturized, and the internal
power supply has been optimized.
Table 1.7 lists the points of difference with the S-mask model.
For the most effective noise reduction, it is recommended that the A-mask model be used in the
singe-chip mode (mode 7).
A description of the H8/539F A-mask model is provided below.
1.5.1 Features
The features of the H8/539F A-mask model with on-chip step-down circuit are as follows.
• EMI Noise
EMI noise has been reduced approximately 10 to 20 dB compared with the H8/539F S-mask
model.
• Current Consumption
Current consumption during normal operation has been reduced approximately 30% compared
with the H8/539F S-mask model.
• Compatibility with S-Mask Version
The H8/539F A-mask model is functionally compatible with the S-mask model. With the
exception of the VCL pin, it is also completely pin compatible. In the single-chip mode, its
electrical characteristics are compatible* as well. The bus timing AC characteristics differ in
the externally expanded modes due to the slower bus interface.
Note: * The (φ clock output AC characteristics (tCL, tCH, tCr, tCf) differ from those of the S-mask
model.
1.5.2 On-Chip Step-Down Circuit
The on-chip step-down circuit automatically lowers the microcomputer's internal power source
voltage to the optimum level. The H8/539F A-mask model is equipped with a VCL (internal step-
down pin) which must be connected to a 0.1 µF capacitor to stabilize the internal voltage.
Table 1.6 lists pin functions and Figure 1.3 shows the method for connecting the external
capacitor.
Rev. 3.0, 02/99, page 29 of 904

Do not connect the VCC power source to the VCL pin of the A-mask model. (As before, connect
the VCC power source to the other VCC pins.) Care should be exercised as the VCL output pin of the
A-mask model is in the same pin position as one of the VCC pins of the S-mask model.
Table 1.6 Pin Functions
Pin Name Symbol I/O Function

Internal step-down pin VCL Output Pin for connecting to a capacitor to stabilize
the internal voltage
VCC power
External source
capacitor
VCL VCC
0.1µF
H8/539F A-mask model H8/539F S-mask model
Note: Do not connect the VCC power source to the Note: The S-mask model has a VCC pin in the
VCL pin of the A-mask model. (As before, same position as the VCL output pin of the
connect the VCC power source to the other A-mask model.
VCC pins.)
Position the capacitor near the pin.
Figure 1.3 Method of Connecting A-Mask VCL Capacitor and Differences with S-Mask Model
Rev. 3.0, 02/99, page 30 of 904

1.5.3 Differences Between the S-Mask and A-Mask Models
Table 1.7 lists the points of difference between the S-mask and A-mask models.
Table 1.7 Points of Difference Between S-Mask and A-Mask Models
H8/539F S-Mask Model H8/539F A-Mask Model

Product type HD64F5398SF16 HD64F5398AF16
name
Sample markings
H8/539 H8/539
S A
HD64F5398F16 HD64F5398F16
JAPAN JAPAN
"S" is printed above "A" is printed above

the type name. the type name.
Flash memory VCC single power source
programming
power source
Internal power VCC power source Internal step-down power source
source voltage
Pin arrangement Pin 1 (FP-112): VCC pin Pin 1 (FP-112): VCL pin
VCC pin is connected to the VCC A 0.1 µF capacitor must be connected
power source. between VCL and VSS.
The VCL pin must not be connected to
the VCC power source.
(As before, connect the VCC power
source to the other VCC pins.)
Current Normal operating current: 65 mA (typ) Normal operating current: 45 mA (typ)
consumption (f = 16 MHz) (f = 16 MHz)
AC Single- AC characteristics are the same except for the bus timing.
char- chip (The φ clock output AC characteristics (tCL, tCH, tCr, tCf) differ between the S-mask
acter- mode and A-mask models.)
istics
Expanded Bus timing compatible with both fast Bus timing compatible with slow mode.
modes and slow modes. (Wait states inserted as necessary.)
Refer to AC Characteristics (H8/539F Refer to AC Characteristics (H8/539F A-
S-Mask Model), Bus Timing. Mask Model), Bus Timing.
Rev. 3.0, 02/99, page 31 of 904

Section 2 CPU
2.1 Overview
The H8/539F has the H8/500 CPU, which is common to all chips in the H8/500 Family. The
H8/500 CPU is a high-speed central processing unit that is designed for realtime control and
supports a large address space. Its architecture features eight general registers, 16-bit internal data
paths, and an optimized instruction set.
The H8/500 CPU is suitable for control of a wide range of medium-scale office and industrial
equipment.
Section 2 summarizes the CPU architecture, instruction set, and operation.
2.1.1 Features
The main features of the H8/500 CPU are listed below.
• General-register machine
 Eight 16-bit general registers
 Seven control registers (two 16-bit registers, five 8-bit registers)
• High-speed operation: 16 MHz maximum clock rate
At 16 MHz a register-register add operation takes only 125 ns.
• Maximum address space: 1 Mbyte
 Managed in 64-kbyte pages
 Four pages available simultaneously: code page, stack page, data page, and extended
page.
The CPU architecture supports up to 16 Mbytes, but the chip has only enough pins to address 1
Mbyte.
• Two CPU operating modes

 Minimum mode: 64-kbyte address space
 Maximum mode: 1-Mbyte address space
• Highly orthogonal instruction set
Addressing modes and data sizes can be specified independently within each instruction.
• Register and memory addressing modes
Register-register and register-memory (or memory-register) operations are supported.
• Instruction set optimized for C language
In addition to the general registers and orthogonal instruction set, the CPU has special short
formats for frequently-used instructions and addressing modes.
Rev. 3.0, 02/99, page 33 of 904
2.1.2 Address Space
The H8/500 CPU has different address spaces in its two operating modes, the minimum mode and
maximum mode. The CPU operating mode is selected by the input at the mode pins (MD2 to
MD0) at a reset. Table 2-1 summarizes the CPU operating modes. Figure 2-1 shows a memory
map for the minimum mode. Figure 2-2 shows a memory map for the maximum mode.
Table 2-1 CPU Operating Modes
Operating Mode Features

Minimum mode Maximum combined size of program area and data area: 64 kbytes
Maximum mode Maximum combined size of program area and data area: 1 Mbyte
H'0000
64 kbytes
H'FFFF
Figure 2-1 Memory Map in Minimum Mode
Rev. 3.0, 02/99, page 34 of 904

H'00000
Page 0
(64 kbytes)
H'0FFFF
H'10000
Page 1
(64 kbytes)
H'1FFFF
1 Mbyte
H'20000
H'F0000
Page 15
(64 kbytes)
H'FFFFF
Figure 2-2 Memory Map in Maximum Mode
Rev. 3.0, 02/99, page 35 of 904

2.1.3 Programming Model
Figure 2-3 shows a programming model of the H8/500 CPU.
15 0
R0
R1
R2
R3
R4
R5
R6 (FP)
R7 (SP)
FP: Frame pointer
SP: Stack pointer
15 0
PC
PC: Program counter
SR
CCR
15 8 7 0
T − − − − I2 I1 I0 − − − − N Z V C
SR: Status register
CCR: Condition code register
CP
CP: Code page register
DP
DP: Data page register
EP
EP: Extended page register
TP
TP: Stack page register
BR
BR: Base register
Figure 2-3 Programming Model
Rev. 3.0, 02/99, page 36 of 904

2.2 General Registers
The H8/500 CPU has eight 16-bit general registers.
The general registers are described next.
2.2.1 Overview
All eight of the general registers are functionally alike; there is no distinction between data
registers and address registers. When these registers are accessed as data registers, either byte or
word size can be selected.
When these registers are accessed as address registers, word size is implicitly assumed.
2.2.2 Register Configuration
Figure 2-4 shows the general register configuration.
15 0
R0
R1
R2
R3
R4
R5
R6 (FP)
R7 (SP)
FP: Frame pointer
SP: Stack pointer
Figure 2-4 General Register Configuration
2.2.3 Stack Pointer
R7 functions as the stack pointer (SP), and is used implicitly in exception handling and subroutine
calls. It is also used implicitly in pre-decrement or post-increment mode by the LDM and STM
instructions, which load and store multiple registers on the stack.
Rev. 3.0, 02/99, page 37 of 904

2.2.4 Frame Pointer
R6 functions as a frame pointer (FP). The LINK and UNLK instructions use R6 implicitly to
reserve or release a stack frame.
2.3 Control Registers

The H8/500 CPU has two control registers.
The control registers are described next.
2.3.1 Overview
The control registers include a 16-bit program counter and a 16-bit status register.
The program counter and status register are described next.
Figure 2-5 illustrates the program counter and status register.
15 0
PC
PC: Program counter
SR
CCR
15 8 7 0
T − − − − I2 I1 I0 − − − − N Z V C
SR: Status register
CCR: Condition code register
Figure 2-5 Program Counter and Status Register
Rev. 3.0, 02/99, page 38 of 904

2.3.3 Program Counter
The 16-bit program counter (PC) indicates the address of the next instruction the CPU will
execute.
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PC
2.3.4 Status Register
The 16-bit status register (SR) contains status flags that indicate the internal state of the CPU.
CCR
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SR T − − − − I2 I1 I0 − − − − N Z V C
Carry flag
Overflow flag
Zero flag
Negative flag
Reserved bits
Interrupt mask bits
Reserved bits
Trace bit
The lower eight bits of the status register are referred to as the condition code register (CCR).
Byte access to the CCR is possible.
(1) Bit 15—Trace (T): Selects trace mode.
Bit 15
T Description
0 Instructions are executed in succession (initial mode after reset)
1 Trace exception handling starts after each instruction (trace mode)
For information about trace exception handling, see section 4.4, "Trace."
(2) Bits 14 to 11—Reserved: Read-only bits, always read as 0.
Rev. 3.0, 02/99, page 39 of 904

(3) Bits 10 to 8—Interrupt mask (I2, I1, I0): These bits indicate the interrupt request mask level
(0 to 7) of the program that is currently executing. Table 2-2 explains the interrupt request mask
levels.
Table 2-2 Interrupt Mask Levels
Interrupt Mask
I2 I1 I0 Level Priority Acceptable Interrupts
1 1 1 7 High NMI
1 1 0 6 Level 7 and NMI
1 0 1 5 Levels 6, 7 and NMI
1 0 0 4 Levels 5 to 7 and NMI
0 0 0 0 Low Levels 1 to 7 and NMI
The CPU accepts only interrupts higher than the interrupt mask level. NMI (level 8) is accepted at
any interrupt mask level*. After accepting an interrupt, the H8/500 CPU updates I 2, I1, and I0 to
the level of the interrupt. Table 2-3 indicates the values of the interrupt mask bits after an
interrupt is accepted. A reset sets all three interrupt mask bits to 1.
Note: * The exception is when programming or erasing flash memory, in which case NMI input is
disabled. See section 19.4.9, "NMI Input Masking" and section 20.4.8, "NMI Input
Masking" for details.
Table 2-3 Interrupt Mask Bits (I2, I1, I0) after an Interrupt is Accepted
Interrupt Mask
Level of Interrupt Accepted I2 I1 I0
NMI (8) 1 1 1
7 1 1 1
6 1 1 0
5 1 0 1
4 1 0 0
3 0 1 1
2 0 1 0
1 0 0 1
Rev. 3.0, 02/99, page 40 of 904

(5) Bit 3—Negative (N): The most significant data bit, regarded as a sign bit.
(6) Bit 2—Zero (Z): Set to 1 to indicate zero data and cleared to 0 at other times.
(7) Bit 1—Overflow (V): Set to 1 when an arithmetic overflow occurs and cleared to 0 at other
times.
(8) Bit 0—Carry (C): Set to 1 when a carry or borrow occurs at the most significant data bit and
cleared to 0 at other times.
The specific changes that occur in the condition code bits when each instruction is executed are
listed in Appendix A.1 "Instruction Tables." See the H8/500 Series Programming Manual for
further details.
2.4 Page Registers

The H8/500 CPU has four page registers.
The page registers are described next.
2.4.1 Overview
All page registers are eight-bit registers.
The four page registers are the code page register (CP), data page register (DP), extended page
register (EP), and stack page register (TP).
The page registers are not used to calculate effective addresses in minimum mode. In maximum
mode, the page registers combine with the program counter and general registers to generate 24-
bit effective addresses as shown in figure 2-6, thereby expanding the program area, data area, and
stack area.
Rev. 3.0, 02/99, page 41 of 904

Page register General register
8 bits 16 bits
CP PC
R0
R1
DP R2
R3
@aa:16
R4
EP
R5
R6
TP
R7
24 bits (effective address)
Figure 2-6 Combinations of Page Registers with PC and General Registers
Rev. 3.0, 02/99, page 42 of 904

Figure 2-7 shows the page registers.
7 0
CP
CP: Code page register
DP
DP: Data page register
EP
EP: Extended page register
TP
TP: Stack page register
Figure 2-7 Page Registers
2.4.3 Code Page Register
The code page register (CP) combines with the program counter to generate a 24-bit program code
address. CP contains the upper eight bits of the address.
Bit 7 6 5 4 3 2 1 0
CP
In maximum mode, CP is initialized at a reset to a value loaded from the vector table, and CP and
PC are both saved and restored in exception handling.
The LDC instruction can be used to modify the CP contents.
Rev. 3.0, 02/99, page 43 of 904

2.4.4 Data Page Register
The data page register (DP) combines with general registers R0 to R3 to generate a 24-bit
effective address. DP contains the upper eight bits of the address.
Bit 7 6 5 4 3 2 1 0
DP
DP is used to calculate effective addresses in register indirect addressing mode using R0 to R3,
and in absolute addressing mode (but not short absolute addressing mode).
The LDC instruction can be used to modify the DP contents.
2.4.5 Extended Page Register
The extended page register (EP) combines with general register R4 or R5 to generate a 24-bit
operand address. EP contains the upper eight bits of the address.
Bit 7 6 5 4 3 2 1 0
EP
EP is used to calculate effective addresses in register indirect addressing mode using R4 or R5.
The LDC instruction can be used to modify the EP contents.
2.4.6 Stack Page Register
The stack page register (TP) combines with R6 (SP) or R7 (FP) to generate a 24-bit stack address.
TP contains the upper eight bits of the address.
Bit 7 6 5 4 3 2 1 0
TP
TP is used to calculate effective addresses in the register indirect addressing mode using R6 or R7,
in exception handling, and in subroutine calls.
The LDC instruction can be used to modify the TP contents.
Rev. 3.0, 02/99, page 44 of 904

2.5 Base Register
The H8/500 CPU has one 8-bit base register.
The base register is described next.
2.5.1 Overview
The eight-bit base register (BR) stores the base address used in short absolute addressing mode
(representing the upper eight bits of an address in page 0). Figure 2-8 illustrates the base register
and short absolute addressing mode. In this addressing mode a 16-bit effective address is
generated by using the BR contents as the upper eight bits and an address given in the instruction
code as the lower eight bits. The short absolute addressing mode always addresses page 0.
The LDC instruction can be used to modify the BR contents.
8 bits 8 bits
BR @aa:8
16 bits (effective address)
Figure 2-8 Short Absolute Addressing Mode and Base Register
Figure 2-9 shows the base register.
7 0
BR
Figure 2-9 Base Register
Rev. 3.0, 02/99, page 45 of 904

2.6 Data Formats
The H8/500 CPU can process five types of data: one-bit data, four-bit BCD data, eight-bit (byte)
data, 16-bit (word) data, and 32-bit (longword) data. Bit manipulation instructions operate on one-
bit data. Decimal arithmetic instructions operate on four-bit BCD data. All instructions except
certain arithmetic and data transfer instructions can operate on byte and word data. Multiply and
divide instructions operate on longword data.
The data formats are described next.
2.6.1 Data Formats in General Registers
Table 2-4 indicates the data formats in general registers. All sizes of data can be stored: one-bit
data, four-bit BCD data, eight-bit (byte) data, 16-bit (word) data, and 32-bit (longword) data.
In addressing of one-bit data, bit 15 is the most significant bit and bit 0 is the least significant bit.
BCD and byte data are stored in the lower eight bits of a general register. All 16 bits of a general
register are used to store word data. Two general registers are used for longword data: the upper
16 bits are stored in Rn (n must be an even number); the lower 16 bits are stored in Rn+1.
Operations performed on BCD data or byte data do not alter the upper eight bits of the register.
Rev. 3.0, 02/99, page 46 of 904

Table 2-4 General Register Data Formats
Data Type Register No. Data Structure

One bit Rn 15 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BCD Rn
7 43 0
Don't care Upper digit Lower digit
Byte Rn 7 0
Don't care MSB LSB
Word Rn 15 0
MSB LSB
Longword* Rn 31 16
Rn+1 MSB Upper 16 bits
Lower 16 bits LSB
15 0
Note: * For longword data n must be even (0, 2, 4, or 6).
2.6.2 Data Formats in Memory
Table 2-5 indicates the data formats in memory.
Instructions that access bit data in memory have byte or word operands. The instruction specifies
a bit number to indicate a specific bit in the operand.
Access to word data in memory must always begin at an even address. Access to word data
starting at an odd address causes an address error. The upper eight bits of word data are stored in
address n (where n is an even number); the lower eight bits are stored in address n + 1.
Rev. 3.0, 02/99, page 47 of 904

Table 2-5 Data Formats in Memory
Data Type Data Format

One bit (in byte operand data)
Address n 7 6 5 4 3 2 1 0
One bit (in word operand data)

Even address 15 14 13 12 11 10 9 8
Odd address 7 6 5 4 3 2 1 0
Byte
Address n MSB LSB
Word
Even address MSB Upper 8 bits
Odd address Lower 8 bits LSB
2.6.3 Stack Data Formats
Table 2-6 shows the data formats on the stack.
When the stack is accessed in exception processing (to save or restore the program counter, code
page register, or status register), word access is always performed, regardless of the actual data
size. Similarly, when the stack is accessed by an instruction using the pre-decrement or post-
increment register indirect addressing mode specifying R7 (@-R7 or @R7+), which is the stack
pointer, word access is performed regardless of the operand size specified in the instruction.
Programs should be coded so that the stack pointer always indicates an even address. An address
error will occur if the stack pointer indicates an odd address.
Table 2-6 Data Formats on the Stack
Data Type Data Format

Byte data on stack
Even address Undetermined data
Odd address MSB LSB
Word data on stack

Even address MSB Upper 8 bits
Odd address Lower 8 bits LSB
Rev. 3.0, 02/99, page 48 of 904

2.7 Addressing Modes and Effective Address Calculation
The H8/500 CPU supports seven addressing modes.
These modes and the corresponding effective address calculations are described next.
2.7.1 Addressing Modes
The seven addressing modes supported by the H8/500 CPU are:
1. Register direct
2. Register indirect
3. Register indirect with displacement
4. Register indirect with pre-decrement or post-increment
5. Immediate
6. Absolute
7. PC-relative
Due to the highly orthogonal nature of the instruction set, most instructions having operands can
use any applicable addressing mode from 1 through 6. The PC-relative mode 7 is used by
branching instructions.
In most instructions, the addressing mode is specified in the effective address (EA) field and
effective address extension (if present).
Table 2-7 indicates how the addressing mode is specified in the effective address field.
(1) Register Direct Addressing Mode: The contents of a general register Rn are used directly as
operand data. This addressing mode is specified by giving the general register name.
Register direct addressing mode
Rn
General register name
Rev. 3.0, 02/99, page 49 of 904

(2) Register Indirect Addressing Mode: The contents of a general register Rn are used as a
memory address, and data access is performed at that memory address. This addressing mode is
specified by giving the general register name with an address qualifier (@).
Register indirect addressing mode
@Rn

Address qualifier
(3) Register Indirect Addressing Mode with Displacement: A displacement value is added to
the contents of a general register Rn, the sum is used as a memory address, and data access is
performed at that memory address. This addressing mode is specified by giving the general
register name with the address qualifier (@) and an 8-bit or 16-bit displacement value.
Register indirect addressing mode with displacement
@(disp:8, Rn) or @(disp:16, Rn)

8-bit displacement (with :8) 16-bit displacement (with :16)
Address qualifier
(4) Register Indirect Addressing Mode with Pre-Decrement or Post-Increment: In register

indirect addressing mode with pre-decrement, a general register value is first decremented by -1 or
-2, then the result is used as a memory address and data access is performed at that memory
address. In register indirect addressing mode with post-increment, a general register value is used
as a memory address and data access is performed at that memory address, then the register value
is incremented by 1 or 2. This addressing mode is specified by giving the general register name
with the address qualifier (@) and a plus or minus sign (+ or -).
Register indirect addressing mode with pre-decrement or post-increment
@−Rn or @Rn+
General register name Plus sign (post-increment)

Minus sign (pre-decrement) General register name
Address qualifier Address qualifier
Rev. 3.0, 02/99, page 50 of 904

(5) Immediate Addressing Mode: Eight-bit or 16-bit immediate data given in the instruction are
used directly as the operand data. This addressing mode is specified by giving the immediate data
with a data qualifier (#).
Immediate addressing mode
#xx:8 or #xx:16
8-bit immediate data 16-bit immediate data

Data qualifier Data qualifier
(6) Absolute Addressing Mode: Data access is performed at a memory address given as a 16-bit
absolute address in the instruction, or given as an eight-bit absolute address in the instruction and
combined with the base register (BR) value. This addressing mode is specified by giving the
absolute address with an address qualifier.
Absolute addressing mode
@aa:16 or @aa:8
16-bit absolute address 8-bit absolute address

Address qualifier (lower 8 bits of address* )
Address qualifier
* Upper 8 bits are specified by BR
(7) PC-Relative Addressing Mode: An eight-bit or 16-bit displacement value given in the
instruction is added to the program counter value, the sum is used as a memory address, and this
memory address is moved into the program counter. This addressing mode is specified by giving
the displacement value.
PC-relative addressing mode
disp
Displacement
Rev. 3.0, 02/99, page 51 of 904

Table 2-7 Addressing Modes
No. Addressing Mode Mnemonic EA Field EA Extension

1 Register direct Rn None
1 0 1 0 Sz r r r
*1 *2
2 Register indirect @Rn None

1 1 0 1 Sz r r r
3 Register indirect @(d:8,Rn) Displacement

with displacement @(d:16,Rn) 1 1 1 0 Sz r r r (1 byte)
1 1 1 1 Sz r r r Displacement
(2 bytes)
4 Register indirect @-Rn None
with pre-decrement @Rn+ 1 0 1 1 Sz r r r
Register indirect 1 1 0 0 Sz r r r
with post-increment
5 Immediate #xx:8 Immediate data
#xx:16 0 0 0 0 0 1 0 0 (1 byte)
0 0 0 0 1 1 0 0 Immediate data
(2 bytes)
6 Absolute (@aa:8 is @aa:8 1-byte absolute
short absolute) @aa:16 0 0 0 0 Sz 1 0 1 address (offset
0 0 0 1 Sz 1 0 1 from BR)
2-byte absolute
address
7 PC-relative disp No EA field. Addressing mode 1- or 2-byte
is specified in op-code. displacement
Notes: 1. Sz specifies the operand size. 2. rrr specifies a general register.
Sz Operand Size rrr General Register

0 Byte 000 R0
1 Word 001 R1
010 R2
011 R3
100 R4
101 R5
110 R6
111 R7
2.7.2 Effective Address Calculation
Table 2-8 explains how an effective address is calculated in each addressing mode.
Rev. 3.0, 02/99, page 52 of 904
The page registers are not used to calculate effective addresses in minimum mode.
Table 2-8 Effective Address Calculation
Addressing
Mode Mnemonic
No. EA Field Effective Address Calculation Effective Address
1 Register direct − Operand is contents of Rn.
Rn
1 0 1 0 Sz r r r
2 Register indirect − 23 15 0
@Rn DP *2 Rn
1 1 0 1 Sz r r r
Or TP or EP
3 Register indirect 23 15 0
with displacement 15 0 DP *2 Result
@(d:8,Rn) Rn
1 1 1 0 Sz r r r Or TP or EP
+
15 0
Displacement
16 bits
(8 bits with sign-bit extension)
@(d:16,Rn) 23 15 0
15 0 DP *2 Result
1 1 1 1 Sz r r r
Rn
Or TP or EP
+
15 0
Displacement
4 Register indirect 23 15 0
with pre- 15 0 DP *2 Result
decrement Rn
@-Rn Or TP or EP
1 0 1 1 Sz r r r −
*1
1 or 2
Rn is decremented by 1 or 2 before
instruction execution.
Register indirect − 23 15 0
with post-
DP *2 Rn
increment Rn is incremented by 1 or 2 after
@Rn+ instruction execution.
Or TP or EP
1 1 0 0 Sz r r r
Notes: 1. 1 for a byte operand, 2 for a word operand, and always 2 for R7 in register indirect mode with
pre-decrement or post-increment, even if byte size is specified.
2. Register Indirect Page Register
R7, R6 TP
R5, R4 EP
R3-R0 DP
Rev. 3.0, 02/99, page 53 of 904

Table 2-8 Effective Address Calculation (cont)
Addressing
Mode Mnemonic
No. EA Field Effective Address Calculation Effective Address
5 Absolute −
@aa:8 23 15 0
H'00 BR EA extension data
0 0 0 0 Sz 1 0 1
@aa:16 −
23 15 0
0 0 0 1 Sz 1 0 1 DP EA extension data
6 Immediate − Operand is 1-byte EA extension data.

#xx:8
0 0 0 0 010 0
#xx:16 − Operand is 2-byte EA extension data.

0 0 0 0 110 0
7 PC-relative 23 15 0
d:8 15 0 CP Result
No EA field. PC
Specified in
op-code. +
15 0
Displacement
16 bits
(8 bits with sign extension)
d:16 23 15 0
No EA field. 15 0 CP Result
Specified in PC
op-code.
+
15 0
Displacement
Rev. 3.0, 02/99, page 54 of 904

2.8 Operating Modes
The H8/500 CPU has two operating modes: minimum mode and maximum mode. The mode is
selected by the mode pins (MD2 to MD0).
The operating modes are described next.
2.8.1 Minimum Mode
Minimum mode supports an address space of up to 64 kbytes. The page registers are ignored.
Instructions that branch across page boundaries (PJMP, PJSR, PRTS, PRTD) are invalid.
2.8.2 Maximum Mode
In maximum mode the page registers are valid, expanding the maximum address space to 1
Mbyte. It is possible to move from one page to another with branching instructions (PJMP, PJSR,
PRTS, PRTD) and when branching to interrupt-handling routines.
When data access crosses a page boundary, the program must rewrite the page register before it
can access the data in the next page.
For further information on the operating modes, see section 3, "MCU Operating Modes."
2.9 Basic Operational Timing

When an external clock signal is fed to the EXTAL pin or a crystal resonator is connected across
the XTAL and EXTAL pins, supplying a signal of the same frequency as the system clock (φ),
duty adjustment is performed by the duty adjustment circuit to generate the φ clock. Figure 2-10
shows a block diagram of the clock oscillator.
The basic operational timing of the H8/500 CPU is described next.
CPG
XTAL Duty adjustment

Oscillator Prescaler
EXTAL circuit
φ φ/2- φ/4096
Figure 2-10 Block Diagram of Clock Oscillator
Rev. 3.0, 02/99, page 55 of 904

2.9.1 Overview
The system clock (φ) produced by duty adjustment of the clock (fOSC) supplied from the clock
oscillator is the H8/500 CPU's time base. One cycle of the system clock is referred to as a "state."
The H8/500 CPU's bus cycle consists of two or three states. The CPU uses different methods to
access on-chip memory, on-chip supporting modules, and external devices.
These access methods are described next.
2.9.2 Access to On-Chip Memory
On-chip memory is accessed in two states using a 16-bit bus. Figure 2-11 shows the on-chip
memory access cycle. Figure 2-12 shows the pin states during on-chip memory access.
Bus cycle
T1 state T2 state
φ
Internal address bus Address
Internal read signal
Internal data bus

(read access) Read data
Internal write signal
Internal data bus

Write data
(write access)
Figure 2-11 On-Chip Memory Access Cycle
Rev. 3.0, 02/99, page 56 of 904

T1 state T2 state
φ
A19-A0 Address
High
AS, RD, HWR, LWR
High impedance
D15-D0
Figure 2-12 Pin States during Access to On-Chip Memory
2.9.3 Access to Two-State-Access Address Space
Two-state access permits high-speed processing. No wait states (TW) can be inserted in access to
the two-state-access address space. The external two-state-access address space is accessed via a
16-bit bus. Figure 2-13 shows the access cycle for the external two-state-access address space.
Bus cycle
T1 state T2 state
φ
A19-A 0 Address
AS, RD
D15-D 0 Read data
HWR, LWR
D15-D 0 Write data
Figure 2-13 Access Cycle for External Two-State-Access Address Space
Rev. 3.0, 02/99, page 57 of 904

2.9.4 Access to On-Chip Supporting Modules
The on-chip supporting modules are always accessed in three states. The data bus is eight bits
wide, except that some of the registers in the 16-bit integrated-timer pulse unit (IPU) are accessed
via a 16-bit data bus.
Figure 2-14 shows the on-chip supporting module access cycle. Figure 2-15 indicates the pin
states during access to an on-chip supporting module.
Bus cycle
T1 state T2 state T3 state
φ
Internal
Address
address bus
Internal read
signal
Internal data bus Read data

(read access)
Internal write
signal
Internal data bus Write data

(write access)
Figure 2-14 Access Cycle for On-Chip Supporting Modules

φ
A19-A 0 Address
AS, RD, HWR, High

LWR
High impedance
D15-D 0
Figure 2-15 Pin States during Access to On-Chip Supporting Modules
Rev. 3.0, 02/99, page 58 of 904

2.9.5 Access to Three-State-Access Address Space
Three-state access is used for interfacing to low-speed devices.
The wait-state controller (WSC) can insert wait states (TW) in access to the three-state-access
address space.
Figure 2-16 shows the three-state read access cycle. Figure 2-17 shows the three-state write
access cycle.
Read cycle
A19-A 0 Address
AS
RD
HWR, LWR
High
D15-D 0
Read data
(read access)
Figure 2-16 Read Access Cycle for Three-State-Access Address Space
Rev. 3.0, 02/99, page 59 of 904

Write cycle
A19-A 0 Address
AS
RD High
HWR, LWR
D15-D 0
Write data
(write access)
Figure 2-17 Write Access Cycle for Three-State-Access Address Space
Rev. 3.0, 02/99, page 60 of 904

2.10 CPU States
The H8/500 CPU has five processing states.
These states are described next.
2.10.1 Overview
The five processing states of the H8/500 CPU are the program execution state, exception-handling
state, bus-released state, reset state, and power-down state.
The power-down state is further divided into a sleep mode, software standby mode, and hardware
standby mode. Table 2-9 summarizes these states. Figure 2-18 shows a map of the state
transitions.
Table 2-9 Processing States
State Description
Program execution state The H8/500 CPU executes program instructions in sequence.
Exception-handling state A transient state in which the H8/500 CPU executes a
hardware sequence (saving the program counter and status
register, fetching a vector, etc.) triggered by a reset, interrupt,
or other exception.
Bus-released state The H8/500 CPU has released the external bus in response to
an external bus request signal.
Reset state The H8/500 CPU and all on-chip supporting modules have
been initialized and are stopped.
Power- Sleep mode Some or all clock signals are stopped to conserve power.
down
Software
state
standby mode
Hardware
standby mode
Rev. 3.0, 02/99, page 61 of 904

Program execution
=1
state
=0
EQ
BR
EQ
SLEEP
=1
tion
instruc-
=0
BR SLEEP
EQ
tion
dlin cep
instruc-
EQ
BR
x
tion with
n
BR
h an of e
ptio
g
SSBY
xce
d bit set
En
Bus-released state dlin for e Sleep mode

han uest
g
t
ues
req
Req
rr upt
Inte
Exception-handling NMI Software standby

state mode
RES = 1 STBY = 1
RES = 0 Hardware standby
Reset state*1 mode*2
Notes: 1. From any state except hardware standby mode, a transition to the reset state
occurs whenever RES is set to 0.
2. From any state, a transition to hardware standby mode occurs when STBY
is set to 0.
Figure 2-18 State Transitions
2.10.2 Program Execution State
In this state the H8/500 CPU executes program instructions in normal sequence.
2.10.3 Exception-Handling State
The exception-handling state is a transient state that occurs when the H8/500 CPU alters the
normal program flow due to an interrupt, trap instruction, address error, or other exception.
See section 4, "Exception Handling" for further information on the exception-handling state.
Rev. 3.0, 02/99, page 62 of 904

2.10.4 Bus-Released State
When so requested, the H8/500 CPU can grant control of the external bus to an external device.
While an external device has the bus right, the H8/500 CPU is said to be in the bus-released state.
Granting of the bus is controlled by the %5(4 and %$&. signals. Bus requests are input at the
%5(4 pin. When the bus has been released, an acknowledging signal is output at the %$&. pin.
Figure 2-19 illustrates the procedure for releasing the bus.
1. When the H8/500 CPU

H8/500 External device
receives a low BREQ
signal it drives the BACK
Request bus pin low to notify the
BREQ external device that the
= Low bus has been released.
BREQ reception
2. After receiving the BACK
Acknowledge bus signal, the external device
release BACK that requested the bus
= Low becomes the bus master.
Check BACK It can use the address bus
Place A19 to A0, D15 (A19 to A0), data bus (D15
to D0, AS, RD, LWR, to D0), and bus control
and HWR in high- signals (AS, RD, LWR,
impedance state HWR).
Get bus
3. When the H8/500 CPU
releases the bus it places
the address bus, data bus,
and bus control signals
Bus-released state in the high-impedance
state. The device that
became bus master
controls the bus.
Figure 2-19 Bus Release Procedure
Rev. 3.0, 02/99, page 63 of 904

Bus Release Control Register (Address H'FF1B): This register (BRCR) enables and disables
%5(4 input and %$&. output. BRCR is initialized to H'FE by a reset and in hardware standby
mode. It is not initialized in software standby mode. The BRCR bit structure is shown next.
Bit 7 6 5 4 3 2 1 0
− − − − − − − BRLE
Initial value 1 1 1 1 1 1 1 0
R/W − − − − − − − R/W
Reserved bits Bus release

enable bit
Selects port A
functions
Bits 7 to 1—Reserved: Read-only bits, always read as 1.
Bit 0—Bus Release Enable Bit (BRLE): Selects the functions of pins PA6 and PA5.
Bit 0
BRLE Description
0 PA6 and PA5 are used for general-purpose input and output
1 PA6 is used for %$&. output; PA5 is used for %5(4 input
(1) Case in which %5(4 is Acknowledged at End of Bus Cycle
Figure 2-20 shows the timing when the H8/500 CPU acknowledges the %5(4 signal at the end of
a bus cycle.
The %5(4 signal is sampled during every instruction fetch cycle and data read or write cycle. In
word data access by means of two successive byte accesses, first to the upper byte, then to the
lower byte (access to the eight-bit-bus-access address space or an on-chip supporting module), the
H8/500 CPU does not release the bus right until it has accessed the lower byte.
Rev. 3.0, 02/99, page 64 of 904

BREQ acknowledged at
end of bus cycle
T1 T2 T3 Tx Tx
φ
A19-A 0 Address Hi-Z
D15-D 0 Data Hi-Z
AS, RD Hi-Z
LWR, HWR High Hi-Z
BREQ (input)
Bus-release acknowledge
BACK (output) signal output
Read cycle* Bus-released state
Note: * Instruction fetch or data read cycle. In access to word data in the byte-access
address space, the cycle shown is the lower byte read cycle.
Figure 2-20 Case of %5(4 Acknowledged at End of Bus Cycle (Read Cycle Example)
(2) Case in which %5(4 is Acknowledged at End of Machine Cycle
Figure 2-21 shows the timing when the H8/500 CPU acknowledges the %5(4 signal at the end of
a machine cycle.
The H8/500 CPU acknowledges the %5(4 signal at the end of machine cycles during execution
of the MULXU or DIVXU instruction.
Rev. 3.0, 02/99, page 65 of 904

end of machine cycle
MULXU or DIVXU calculation cycles Tx Tx

φ
A19-A 0 n n+1 n+2 Hi-Z
D15-D 0 Hi-Z Hi-Z
AS, RD High Hi-Z
LWR, HWR High Hi-Z
BREQ (input)
Bus-released state
Figure 2-21 Case of %5(4 Acknowledged at End of Machine Cycle

(During Execution of MULXU or DIVXU Instruction)
(3) Case in which %5(4 is Acknowledged in Sleep Mode
Figure 2-22 shows the timing when the H8/500 CPU acknowledges the %5(4 signal in sleep
mode.
The H8/500 CPU acknowledges the %5(4 signal at any time during sleep mode.
Rev. 3.0, 02/99, page 66 of 904

any time
Sleep mode Tx Tx
φ
A19-A 0 Hi-Z Hi-Z
D15-D 0 Hi-Z Hi-Z
AS, RD High Hi-Z
LWR, HWR High Hi-Z
BREQ (input)
Bus-released state
Figure 2-22 Case of %5(4 Acknowledged in Sleep Mode
(4) Bus-Release Operation during Two-State Access
Figure 2-23 shows the timing when the bus is requested during a two-state access cycle.
When an external device requests the bus during two-state access, the H8/500 CPU enters the bus-
released state as follows:
(1) The %5(4 pin is sampled at the start of the T1 state. If %5(4 is low, at the end of the bus
cycle the H8/500 CPU halts and enters the bus-released state.
(2) In the case of two-state access, at the end of the T2 state the %$&. signal goes low to indicate
that the bus-released state has been entered. The address bus (A19 to A0), data bus (D15 to D0),
and bus control signals ($6, 5', /:5, +:5) are placed in the high-impedance state.
(3) While the bus is released, the H8/500 CPU constantly samples the %5(4 pin (at each Tx state)
and remains in the bus-released state while %5(4 is low.
(4) When %5(4 is high during a Tx state, at the end of the next state the H8/500 CPU drives the
%$&. signal high to indicate that it has regained possession of the bus (and that CPU cycles
will resume).
(5) CPU cycles resume at the end of the next state after %$&. goes high.
Rev. 3.0, 02/99, page 67 of 904

CPU cycles Bus-released cycles CPU cycles
Two-state
access
T2 T1 T2 Tx Tx Tx Tx T1
φ
A19-A 0 Address Address
D15-D 0 Data
AS, RD
LWR, HWR High
BREQ (input)
BACK (output)
(1) (2) (3) (4) (5)
Figure 2-23 Bus Release during Two-State Access (Read Cycle Example)
(5) Bus-Release Operation during Three-State Access
Figure 2-24 shows the timing when the bus is requested during a three-state access cycle.
When an external device requests the bus during three-state access, the H8/500 CPU enters the
bus-released state as follows:
(1) The %5(4 pin is sampled at the start of the T1, T2, and TW states. If %5(4 is low, at the end
of the bus cycle the H8/500 CPU halts and enters the bus-released state.
(2) In the case of three-state access, at the end of the T3 state the %$&. signal goes low to indicate
that the bus-released state has been entered. The address bus (A19 to A0), data bus (D15 to D0),
and bus control signals ($6, 5', /:5, +:5) are placed in the high-impedance state.
will resume).
Rev. 3.0, 02/99, page 68 of 904

Three-state access
T1 T2 TW T3 Tx Tx Tx T1
φ
A19-A 0 Address
D15-D 0 Data
AS, RD
LWR, HWR High
BREQ (input)
BACK (output)
(1) (2) (3) (4)
Figure 2-24 Bus Release during Three-State Access (Read Cycle Example)
(6) Bus-Release Operation during Internal CPU Operations
Figure 2-25 shows the timing when the bus is requested during internal CPU operations.
When an external device requests the bus during internal CPU operations, the H8/500 CPU enters
the bus-released state as follows:
(1) The %5(4 pin is sampled at the start of the T1 state. If %5(4 is low, at the end of the internal
cycle the H8/500 CPU halts and enters the bus-released state.
(2) In the case of internal CPU operations, at the end of a T1 state the %$&. signal goes low to
indicate that the bus-released state has been entered. The address bus (A19 to A0), data bus (D15
to D0), and bus control signals ($6, 5', /:5, +:5) are placed in the high-impedance state.
will resume).
Rev. 3.0, 02/99, page 69 of 904

Internal CPU operation
T1 T1 T1 T1 Tx Tx Tx T1
φ
A19-A 0 Address
D15-D 0 Hi-Z Hi-Z
AS, RD High
LWR, HWR High
BREQ (input)
BACK (output)
(1) (2) (3) (4)
Figure 2-25 Bus Release during Internal CPU Operation
(7) Notes
• The H8/500 CPU does not accept interrupts while in the bus-released state.
• The %5(4 signal must be held low until %$&. goes low. If %5(4 returns to the high level
before %$&. goes low, the bus release operation may be executed incorrectly.
2.10.5 Reset State
In the reset state, the H8/500 CPU and all on-chip supporting modules are initialized and placed in
the stopped state. The H8/500 CPU enters the reset state whenever the 5(6 pin goes low, unless
the H8/500 CPU is currently in the hardware standby mode.
See section 4.2, "Reset" for further information on the reset state.
2.10.6 Power-Down State
The power-down state comprises three power-down modes: sleep mode, software standby mode,
and hardware standby mode.
See section 21, "Power-Down State" for further information.

Rev. 3.0, 02/99, page 70 of 904
Section 3 MCU Operating Modes
3.1 Overview
3.1.1 Selection of Operating Mode
The H8/539F has seven operating modes (modes 1 to 7).
Modes 1 to 6 are externally expanded modes in which external memory and peripheral devices can
be accessed. Modes 1, 2, and 6 are expanded minimum modes, supporting a 64-kbyte address
space. Modes 3, 4, and 5 are expanded maximum modes, supporting a maximum 1-Mbyte address
space. When using modes 1 to 6, refer to section 3.6, Notes on Use of Externally Expanded
Modes of H8/539F (Dual Power-Source Model). See section 3.7, Notes on H8/539F S-Mask and
A-Mask Models (Single Power Source Model), concerning all modes (1 to 7) in the H8/539F S-
mask and A-mask models (single power source model).
Mode 7 is a single-chip mode: all ports are available for general-purpose input and output, but
external addresses cannot be used.
Mode 0 is reserved for future use and must not be selected in the H8/539F.
Both the pin functions and address space vary depending on the mode. Table 3-1 summarizes the
selection of operating modes.
Table 3-1 Operating Mode Selection
MCU CPU
Operating Operating On-Chip On-Chip Data Bus
Mode MD2 MD1 MD0 Description Mode RAM ROM Width
Mode 0 0 0 0     
1
Mode 1 0 0 1 Expanded Minimum Enabled* Disabled 16 bits
minimum mode
mode
3 1
Mode 2* 0 1 0 Expanded Minimum Enabled* Enabled 8 bits
minimum mode
mode
1
Mode 3 0 1 1 Expanded Maximum Enabled* Disabled 16 bits
maximum mode
mode
3 1
Mode 4* 1 0 0 Expanded Maximum Enabled* Enabled 16 bits
maximum mode
mode
Rev. 3.0, 02/99, page 71 of 904

Table 3-1 Operating Mode Selection (cont)
MCU CPU
Operating Operating On-Chip On-Chip Data Bus
Mode MD2 MD1 MD0 Description Mode RAM ROM Width
1 2
Mode 5 1 0 1 Expanded Maximum Enabled* Disabled 16 bits*
maximum mode
mode
1 2
Mode 6 1 1 0 Expanded Minimum Enabled* Disabled 16 bits*
minimum mode
mode

3
Mode 7* 1 1 1 Single-chip Maximum Enabled Enabled
mode mode
Legend
0: Low
1: High
: Not available
Notes: 1. If RAM enable bits 1 and 2 (RAME1 and RAME2) in the RAM control register (RAMCR)
are cleared to 0, these addresses become external addresses.
2. Eight-bit three-state-access address space after a reset.
3. In the dual power source model (VPP = 12 V), when pin settings are made for mode 2, 4,
or 7 and 12 V is applied to the VPP pin, flash memory can be programmed or erased.
See section 19, Flash Memory (H8/539F Dual Power Source System (VPP = 12 V)) for
details.
In the S-mask model (single power source), when pin settings are made for mode 4 or 7
and pin FWE is in the high level input state, flash memory can be programmed or
erased. See section 20, Flash Memory (H8/539F S-Mask and A-Mask Models: Single
Power Source) for details.
S-Mask and A-Mask Models (Single Power Source): Programming/erasing is enabled by

making pin settings for mode 4 or 7, and setting the FLMCR register with the FWE pin in the
high-level input state. For details, see section 20, Flash Memory (H8/539F S-Mask and A-Mask
Models).
The MCU operating mode can be monitored in the mode control register (MDCR). Table 3-2
summarizes this register.
Table 3-2 Register Configuration
Address Name Abbreviation R/W Initial Value

H'FF19 Mode control register MDCR R Undetermined
Rev. 3.0, 02/99, page 72 of 904

3.2 Mode Control Register
The mode control register (MDCR) is an eight-bit register that indicates the current operating
mode of the H8/539F. The MDCR bit structure is shown next.
Bit 7 6 5 4 3 2 1 0
− − − − − MDS2 MDS1 MDS0
Initial value 1 1 0 0 0 − * − * − *
R/W − − − − − R R R
Mode select 2 to 0
Bits indicating the current
operating mode
Reserved bits
Note: * Determined by pins MD2 to MD0. MDCR latches the inputs at the mode pins
(MD2 to MD0) at the rise of the RES signal.
Reserved: Read-only bits, always read as 1.

(1) Bits 7 and 6

(2) Bits 5 to 3
Mode Select 2 to 0 (MDS2 to MDS0): These bits indicate the values of pins
(3) Bits 2 to 0
MD2 to MD0 latched at the rise of the 5(6 signal (the current operating mode).
MDS2 to MDS0 correspond to pins MD2 to MD0.
MDS2 to MDS0 are read-only bits.
Rev. 3.0, 02/99, page 73 of 904

3.3 Operating Mode Descriptions
3.3.1 Mode 1 (Expanded Minimum Mode)
In mode 1 the data bus is 16 bits wide. The bus controller's byte area register (ARBT) is enabled
in mode 1, so part of the address space can be accessed with an eight-bit bus width. The
maximum address space supported in mode 1 is 64 kbytes.
The on-chip ROM is disabled in mode 1.
3.3.2 Mode 2 (Expanded Minimum Mode)
In mode 2 the data bus is eight bits wide. The on-chip ROM is enabled.
The maximum address space supported in mode 2 is 64 kbytes.
The bus controller's byte-area register (ARBT) is disabled in mode 2.
3.3.3 Mode 3 (Expanded Maximum Mode)
maximum address space supported in mode 3 is 1 Mbyte.
The on-chip ROM is disabled in mode 3.
3.3.4 Mode 4 (Expanded Maximum Mode)
maximum address space supported in mode 4 is 1 Mbyte. The on-chip ROM is enabled.
3.3.5 Modes 5 and 6
Mode 5 is functionally identical to mode 3, and mode 6 is functionally identical to mode 1. When
the chip comes out of reset, however, the bus controller's byte area register (ARBT) is disabled in
modes 5 and 6 and eight-bit, three-state access is performed throughout the address space. The
byte area register can be enabled by setting the BCRE bit to 1 in the bus control register (BCR).
3.3.6 Mode 7 (Single-Chip Mode)
The external address space cannot be accessed.
Rev. 3.0, 02/99, page 74 of 904

3.4 Pin Functions in Each Operating Mode
The pin functions of the I/O ports vary depending on the operating mode. Table 3-3 summarizes
the functions in each mode. Selection of pin functions is described in section 10, "I/O Ports."
Table 3-3 Pin Functions in Each Mode
Expanded Minimum Modes Expanded Maximum Modes Single-Chip Mode

Port Modes 1 and 6 Mode 2 Modes 3 and 5 Mode 4 Mode 7
6 6
Port 1 Data bus* Data bus Data bus* Data bus Input/output
(D15 to D8) (D15 to D8) (D15 to D8) (D15 to D8) port
Port 2 Data bus Input/output Data bus Data bus Input/output
(D7 to D0) port (D7 to D0) (D7 to D0) port
1
Port 3 Input/output Input/output Input/output Input/output Input/output port*
1 1 1 1
port* port* port* port*
1
1 1 1 1
1
1 1 1 1
4
,542, ,543
4 4 4 4
,542, ,543 ,542, ,543 ,542, ,543 ,542, ,543
5
,540, ,541,
5 5 5 5
,540, ,541, ,540, ,541, ,540, ,541, ,540, ,541, $'75*
$'75* $'75* $'75* $'75*
3 3 3 3 3
Port 8 Input port* Input port* Input port* Input port* Input port*
3 3 3 3 3
Port 9 Input port* Input port* Input port* Input port* Input port*
2
Port A Input/output Input/output Input/output Input/output Input/output port* ,
2 4 2 4 1 2 2 4 4
port* , * port* , * port* , * port* , * *
%5(4, %$&., %5(4, %$&., %5(4, %$&., %5(4, %$&.,
:$,7 :$,7 :$,7, address :$,7, address
bus (A19 to A16) bus (A19 to A16)
Port B Address bus Input port/ Address bus Input port/ Input/output
(A15 to A8) address bus (A15 to A8) address bus port
(A15 to A8) (A15 to A8)
Port C Address bus Input port/ Address bus Input port/ Input/output
(A7 to A0) address bus (A7 to A0) address bus port
(A7 to A0) (A7 to A0)
Notes on next page.
Rev. 3.0, 02/99, page 75 of 904

Notes: 1. Also used for timer input/output.
2. Also used for serial communication interface.
3. Also used for A/D conversion.
4. Also used for timer output and PWM timer output.
5. Also used for serial communication interface and PWM timer output.
and the lower half (D7 to D0) is disabled. After the BCRE bit in the bus control register
(BCR) has been set to 1 by software, the bus width can be changed to 16 bits (D15 to
D0) by a byte area top register (ARBT) setting. In modes 1, 3, and 4, the external bus
space has a 16-bit bus width (D15 to D0) after a reset, but this can be changed to 8 bits
by an ARBT setting. In this case, the upper half of the data bus (D15 to D8) is enabled,
and the lower half (D7 to D0) is disabled. For details of the settings, see section 16,
Bus Controller.
3.5 Memory Map in Each Mode

Figure 3-1 shows a memory map for the expanded minimum modes (modes 1, 6, and 2). Figure 3-
2 shows a memory map for the expanded maximum modes (modes 3, 5, and 4). Figure 3-3 shows
a memory map for single-chip mode (mode 7).
H'0000 H'0000
Vector table H'00FF Vector table
H'00FF
H'0100 H'0100
On-chip ROM
External (16 kbytes)
Memory space
H'3FFF
H'4000 External
H'EE7F H'EE7F Memory space
H'EE80 H'EE80
On-chip RAM On-chip RAM
H'FE7F (4 kbytes) H'FE7F (4 kbytes)
H'FE80 On-chip registers H'FE80 On-chip registers
(384 bytes) (384 bytes)
H'FFFF H'FFFF
Modes 1 and 6 Mode 2
Figure 3-1 Memory Map in Expanded Minimum Modes
Rev. 3.0, 02/99, page 76 of 904

H'00000 H'00000
H'001FF Vector table H'001FF Vector table
H'00200 H'00200
On-chip ROM
Memory space Page 0 Page 0
H'03FFF
H'04000
External
H'0EE7F H'0EE7F Memory space
H'0EE80 On-chip RAM H'0EE80 On-chip RAM
H'0FE7F (4 kbytes) H'0FE7F (4 kbytes)
H'0FE80 On-chip registers H'0FE80 On-chip registers
H'0FFFF H'0FFFF
H'10000 H'10000
External Page 1 On-chip ROM Page 1
Memory space (64 kbytes)
H'1FFFF H'1FFFF
H'20000 H'20000
On-chip ROM
Pages (64 kbytes) Pages
2 to 15 H'2FFFF 2 to 15
H'30000 External
Memory space
H'FFFFF H'FFFFF
Figure 3-2 Memory Map in Expanded Maximum Modes
Rev. 3.0, 02/99, page 77 of 904

H'00000
H'001FF Vector table
H'00200
On-chip ROM
(16 kbytes)
H'03FFF
H'04000
H'0EE7F
H'0EE80 On-chip RAM
(4 kbytes)
H'0FE7F
H'0FE80
On-chip registers
(384 bytes)
H'0FFFF
H'10000
On-chip ROM
(64 kbytes)
H'1FFFF
H'20000
On-chip ROM
(64 kbytes)
H'2FFFF
Mode 7
Figure 3-3 Memory Map in Single-Chip Mode
Rev. 3.0, 02/99, page 78 of 904

3.6 Notes on Use of Externally Expanded Modes of H8/539F (Dual Power
Source Model)
The following points must be observed when using the H8/539F in an externally expanded mode
(modes 1 to 6).
• Initialize the φOE bit* to 1 before an external space access.
When using the H8/539F in an externally expanded mode with on-chip ROM enabled (mode 2 or
4), the φOE bit in the φ control register (φCR) must be initialized to 1 before accessing the external
bus space.
• In modes with on-chip ROM disabled, enter standby mode at power-on.
When using the H8/539F in an externally expanded mode with on-chip ROM disabled (mode 1, 3,
5, or 6), hardware standby mode must be entered at power-on. Figure 3-4 shows the power-on
timing.
Note that when ø output is inhibited, the φ pin goes to the high-impedance state and external space
accesses will not function correctly .
Note: * For details, see section 21.5, φ Clock Output Prohibit Function.
See section 3.7, Notes on H8/539F S-Mask and A-Mask Models (Single Power Source Model), for
further information concerning the H8/539F S-mask and A-mask models (single power source
model).
4.5 V
VCC
VIH (VCC-0.7 V)
STBY VIL (0.4 V)
VIL (0.4 V)
RES
Standby state Oscillation setting time

(1 µs or more) (20 ms)
Figure 3-4 Power-On Timing
Rev. 3.0, 02/99, page 79 of 904

3.7 Notes on H8/539F S-Mask and A-Mask Models (Single Power Source
Model)
The following points should be noted when using the H8/539F S-mask and A-mask models (single
power source model) in any of modes 1 to 7.
At power-on, set hardware standby mode in all modes (1 to 7) with the H8/539F S-mask and A-
mask Models (single power source).
Figure 3-5 shows the power-on timing.
Note that when ø output is disabled the φ pin goes to the high-impedance state, and external space
access will not function correctly.
For information concerning the H8/539F (dual power source model), see section 3.6, Notes on Use
of Externally Expanded Mode of H8/539F (Dual Power Supply Model).
Note: For details, refer to 21.5 φ Clock Output Prohibit Function.
4.5 V
VCC
VIH (VCC-0.7 V)
STBY VIL (0.4 V)
VIL (0.4 V)
RES
Standby state Oscillation settling time

(1 µs or more) (20 ms)
Figure 3-5 Power-On Timing
Rev. 3.0, 02/99, page 80 of 904

Section 4 Exception Handling
4.1 Overview
There are five types of exceptions: reset, address error, trace, interrupt, and instruction exceptions.
There are three types of instruction exceptions: invalid instruction, trap instruction, and DIVXU
instruction with zero divisor.
Handling of these exceptions is described next.
4.1.1 Exception Handling Types and Priority
Table 4-1 lists the types of exception handling for exceptions other than instruction exceptions,
and indicates their priority. The system assigns a reserved priority to each of these exception
types. If two or more exceptions occur simultaneously, they are accepted and handled in priority
order.
Table 4-2 lists the types of instruction exception handling. Instruction exceptions cannot occur
simultaneously, so there is no priority order.
Table 4-1 Exception Types and Priority
Priority Exception Type Source Start of Exception Handling

High Reset 5(6 input Rising edge of 5(6 signal
↑ Address error Invalid access (address error) End of instruction execution


 Trace Trace bit (T) = 1 in SR End of instruction execution

 Interrupt External or internal interrupt End of instruction execution or
↓ request end of exception handling
Low
Table 4-2 Instruction Exceptions
Exception Type Source Start of Exception Handling

Invalid instruction Fetching of undefined code Start of execution of instruction with
undefined code
Trap instruction Trap instruction Start of execution of trap instruction
Zero divide DIVXU instruction Start of execution of DIVXU instruction with
zero divisor
Rev. 3.0, 02/99, page 81 of 904

4.1.2 Exception Handling Operation
Exception handling can originate from a variety of sources.
Exception handling other than reset exception handling is described next. For reset exception
handling, see section 4.2, "Reset."
Figure 4-1 is a flowchart of the handling of exceptions other than a reset.
In minimum mode, the program counter (PC) and status register (SR) are saved on the stack. In
maximum mode the code page register (CP), PC, and SR are saved on the stack. Next the T bit in
the status register is cleared to 0, the start address corresponding to the exception source is read
from the exception vector table, and program execution begins from the indicated address.
Exception
Exception handling
PC → @ − SP
State saving:
CP → @ − SP PC, CP, and SR are pushed in that order on
the stack. CP is pushed only in maximum mode.
SR → @ − SP
0 → T bit (SR)
Preparations for program execution:
Start address → CP After the trace bit is cleared to 0, an address is
loaded from the vector table into CP and PC.
CP is loaded only in maximum mode.
Start address → PC
Start of program execution
Figure 4-1 Exception Handling Flowchart
Rev. 3.0, 02/99, page 82 of 904

4.1.3 Exception Sources and Vector Table
Figure 4-2 classifies the exception sources. Table 4-3 shows the exception vector table. The
vector addresses differ between minimum and maximum modes. In maximum mode the vector
table is located in page 0. For internal interrupt vectors, see table 6-3, "Interrupt Priorities and
Vector Addresses."
• Reset
• Address error
• Trace
NMI
External interrupts IRQ0
IRQ1−3
Exception sources • Interrupts
39 interrupt sources
Internal interrupts in on-chip supporting
modules
Invalid instruction
TRAPA instruction
• Instructions
TRAP/VS instruction
Zero divide
Figure 4-2 Classification of Exception Sources
Rev. 3.0, 02/99, page 83 of 904

Table 4-3 Exception Vector Table
Vector Address
Exception Source Minimum Mode Maximum Mode
Reset (initial PC value) H'0000−H'0001 H'0000−H'0003
(Reserved for system) H'0002−H'0003 H'0004−H'0007
Invalid instruction H'0004−H'0005 H'0008−H'000B
DIVXU instruction (zero divisor) H'0006−H'0007 H'000C−H'000F
TRAP/VS instruction H'0008−H'0009 H'0010−H'0013
(Reserved for system) H'000A−H'000B H'0014−H'0017
. .
. .
. .
H'000E−H'000F H'001C−H'001F
Address error H'0010−H'0011 H'0020−H'0023
Trace H'0012−H'0013 H'0024−H'0027
(Reserved for system) H'0014−H'0015 H'0028−H'002B
External interrupt: NMI H'0016−H'0017 H'002C−H'002F
(Reserved for system) H'0018−H'0019 H'0030−H'0033
. .
. .
. .
H'001E−H'001F H'003C−H'003F
TRAPA instruction (16 sources) H'0020−H'0021 H'0040−H'0043
. .
. .
. .
H'003E−H'003F H'007C−H'007F
External interrupt: IRQ0 H'0040−H'0041 H'0080−H'0083
WDT interval interrupt H'0042−H'0043 H'0084−H'0087
External interrupts: IRQ1 H'0048−H'0049 H'0090−H'0093
IRQ2 H'004A−H'004B H'0094−H'0097
IRQ3 H'004C−H'004D H'0098−H'009B
Internal interrupts H'0044−H'0045 H'0088−H'008B
H'0050−H'0051 H'00A0−H'00A3
. .
. .
. .
H'009E−H'009F H'013C−H'013F
Rev. 3.0, 02/99, page 84 of 904

4.2 Reset
4.2.1 Overview
A reset has the highest exception priority.
Reset exception handling is described below.
When the 5(6 pin goes low, all processing halts and the chip enters the reset state. A reset
initializes the internal state of the H8/500 CPU and the registers of on-chip supporting modules.
When the 5(6 pin rises from low to high, the H8/500 CPU begins reset exception handling.
4.2.2 Reset Sequence
The chip enters the reset state when the 5(6 pin goes low.
To ensure that the chip is reset, the 5(6 pin should be held low for at least 20 ms at power-up. To
reset the chip during operation, the 5(6 pin should be held low for at least six system clock cycles
(6φ) in the H8/539F. In the H8/539F S-mask and A-mask models, the 5(6 pin should be held low
for at least 20 system clock cycles (20φ). When an external clock is used, the 5(6 pin should be
held low for at least the external clock output setting delay time (tDEXT) at power-up and in a reset
start from the standby state.
See appendix G, "Pin States" for the states of the pins in the reset state.
When the 5(6 pin rises to the high level after being held low for the necessary time, the H8/500
CPU begins reset exception handling. Figure 4-3 shows the sequence of operations at the end of
the reset state.
RES pin
End of reset (low-to-high transition)
Reset exception handling
MD2−0 → MDS2−0 (1) Values of mode pins (MD2 to MD0) are latched
in bits MDS2 to MDS0 in MDCR.
0 → T bit (SR)
(2) T bit in SR is cleared to 0 to disable trace mode.
1 → I2 to I0 bits (SR) Interrupt mask bits I2 to I0 are all set to 1 (level 7).
Start address → CP
(3) Start address is loaded from vector table. H8/500
Start address → PC CPU starts program execution from that address.
Program execution begins
Figure 4-3 Reset Exception Handling Flowchart
Rev. 3.0, 02/99, page 85 of 904

The vector table contents differs between minimum and maximum mode. The vector table
contents in each mode are described next.
(1) Minimum Mode: Figure 4-4 shows the reset vector in minimum mode.
In minimum mode the reset vector is located at addresses H'0000 and H'0001. When exception
handling begins, the H8/500 CPU copies the reset vector into the program counter (PC). Program
execution then starts from the PC address.
H'0000 PCH
H'0001 PCL
Figure 4-4 Reset Vector in Minimum Mode
Figure 4-5 shows the reset sequence in minimum mode.
Figure 4-5 shows the case in which the program area and stack area are both located in the eight-
bit-bus three-state-access address space.
RES
A15−A 0 (1) Vector address Vector address (3)
D7 −D0 (2) Vector (PCH) Vector (PCL) (4)
RD
Reset interval* Internal pro- Fetching Fetching Prefetching first instruc- Instruction
cessing cycles reset reset tion of program execution
vector (PCH) vector (PCL) starts
(1) Instruction prefetch address (3) Program start address

(2) Operation code (4) First operation code of program
Note: * H8/539F: at least six system clock cycles (6φ)
H8/539F S-mask model: at least 20 system clock cycles (20φ)
Figure 4-5 Reset Sequence in Minimum Mode
Rev. 3.0, 02/99, page 86 of 904

(2) Maximum Mode: Figure 4-6 shows the reset vector in maximum mode.
In maximum mode the reset vector is located at addresses H'0000 to H'0003. When exception
handling begins, the H8/500 CPU copies the reset vector into the code page register (CP) and
program counter (PC), ignoring the vector data at H'0000. Program execution then starts from the
CP and PC address.
H'0000 Don't care

H'0001 CP
H'0002 PCH
H'0003 PCL
Figure 4-6 Reset Vector in Maximum Mode
Figure 4-7 shows the reset sequence in maximum mode.
Figure 4-7 shows the case in which the program area and stack area are both located in the 16-bit-
bus two-state-access address space.
RES
V: Vector address
Internal (1) V V + 2 (3)
address bus
Internal (2) (4)
data bus
D15 - D0 CP PC
Internal
read signal
Reset
vector
Reset interval* Internal processing Fetching Prefetching Instruction execution

cycles reset first instruction starts
vector of program
(1) Instruction prefetch address (3) Program start address
(2) Operation code (4) First operation code of program
Note: * H8/539F: at least six system clock cycles (6φ)
H8/539F S-mask model: at least 20 system clock cycles (20φ)
Figure 4-7 Reset Sequence in Maximum Mode
Rev. 3.0, 02/99, page 87 of 904

4.2.3 Interrupts after Reset
If an interrupt is accepted after a reset but before the stack pointer (SP) is initialized, the program
counter and status register will not be saved correctly, leading to a program crash. This danger
can be avoided as explained next.
When the chip comes out of the reset state all interrupts, including NMI, are disabled, so the first
instruction is always executed. Crashes can be avoided by using this first instruction to initialize
SP. In minimum mode, the first instruction after a reset should initialize SP. In maximum mode,
the first instruction after a reset should initialize the stack page register (TP), and the next
instruction should initialize SP.
Examples:
1. Minimum mode
.ORG H'0000
MOV.W #H'FE80, SP
·
·
·
2. Maximum mode
.ORG H'0000
LDC.B #H'00, TP
MOV.W #H'FE80, SP
·
·
·
4.3 Address Error

An address error occurs when invalid access is attempted. There are three types of address errors:
1. Address error in instruction prefetch

2. Address error in word data access
3. Address error in single-chip mode
When an address error occurs, the H8/500 CPU begins address error exception handling and clears
the T bit of the status register to 0. The interrupt mask level in bits I2 to I0 is not changed.
Each type of address error is described next.
Rev. 3.0, 02/99, page 88 of 904

4.3.1 Address Error in Instruction Prefetch
An attempt to prefetch an instruction from the on-chip registers at addresses H'FE80 to H'FFFF
causes an address error.
The address error exception handling sequence for this case is:
Instruction prefetch from on-chip register area (H'FE80 to H'FFFF)

↓
Wait for execution of current instruction to end
↓
Address error exception handling
The PC value pushed on the stack is the start address of the instruction immediately following the
last instruction executed.
Program code should not be located in addresses H'FE7D to H'FE7E. If program code is located
in these addresses, instruction prefetch will be attempted in the on-chip register area, causing an
address error.
Figure 4-8 shows the areas in which instruction prefetch leads to an address error.
<Page 0>
H'0000
H'FE7D (3 bytes)
H'FE80
On-chip register area Areas in which instruction
H'FFFF prefetch leads to address error
Figure 4-8 Areas in which Instruction Prefetch Leads to Address Error
4.3.2 Address Error in Word Data Access
An address error occurs if an attempt is made to access word data starting at an odd address. The
PC value pushed on the stack is the address of the next instruction after the instruction that
attempted to access word data at an odd address.
Rev. 3.0, 02/99, page 89 of 904

Figure 4-9 shows an example of illegal location of word data.
2m
2m+1 Upper data Word data located at

2m+2 Lower data odd address (error)
(Example) MOV.W @2m+1, R0 causes

an address error.
Figure 4-9 Example of Illegal Location of Word Data
4.3.3 Address Error in Single-Chip Mode
In single-chip mode there is no external memory, so in addition to the word access address errors
described in section 4.3.2, Address Error in Word Data Access, address errors can occur due to
access to missing areas in the address space.
(1) Access to Addresses H'04000 to H'0EE7F and H'30000 to H'FFFFF: In single-chip mode
these addresses form a missing address area; they are assigned neither to on-chip memory nor to
on-chip registers.
Instruction prefetch, byte data access, or word data access in the missing address area causes an
address error. An address error also occurs if an instruction is located in the last three bytes of on-
chip ROM in page 0, because the H8/500 CPU will attempt to prefetch the next instruction from
addresses H'04000 to H'04002 in the missing address area.
The same type of error will not occur if an instruction is located in the last three bytes of on-chip
ROM in page 1 or page 2.
Rev. 3.0, 02/99, page 90 of 904

Page 0
H'00000
ROM area
(3 bytes)
H'03FFD Missing address area
H'04000 (data access also causes an address error)
H'0EE7F
H'0EE80
On-chip
RAM area
H'0FE7D (3 bytes)
H'0FE80 Areas in which instruction prefetch
On-chip register area leads to address error
H'0FFFF

(Single-Chip Mode)
(2) Access to Disabled RAM Area: When the on-chip RAM area is disabled in single-chip mode,
addresses H'04000 to H'0FE7F are also a missing area. Instruction prefetch, byte data access, or
word data access in this missing address area causes an address error. An address error also occurs
if an instruction is located in the last three bytes of on-chip ROM in page 0, because the H8/500
CPU will attempt to prefetch the next instruction from addresses H'04000 to H'04002 in the
missing address area.
The same type of error will not occur if an instruction is located in the last three bytes of on-chip
ROM in page 1 or page 2.
H'00000
ROM area
(3 bytes)
H'03FFD
H'04000
H'0EE80 Missing address area

On-chip RAM area (data access also causes an address error)
(on-chip RAM
disabled)
H'0FE80
On-chip register area Areas in which instruction prefetch
H'0FFFF leads to address error

(Single-Chip Mode with On-Chip RAM Disabled)
Rev. 3.0, 02/99, page 91 of 904

4.4 Trace
Trace mode can be used by a debug program, for example, to monitor the execution of a program
under test.
(1) Trace Mode: When the trace bit (T bit) in the status register (SR) is set to 1, the H8/500 CPU
operates in trace mode. A trace exception occurs at the completion of each instruction.
In trace exception handling the T bit in SR is cleared to 0 to disable trace mode. The interrupt
mask level in bits I2 to I0 is not changed, however; interrupts are accepted during trace exception
handling.
The trace exception-handling routine should end with an RTE instruction. When the trace routine
returns with the RTE instruction, the status register is popped from the stack and trace mode
resumes.
(2) Contention with Address Error Exception Handling: Address error exception handling
occurs at the end of a bus cycle, so it does not normally conflict with trace exception handling.
One instruction is always executed after returning from exception handling, however, so
contention may occur at this point, requiring special consideration.
If address error and trace exceptions both occur at the end of an instruction, because of the priority
relationship between these exceptions, address error exception handling is carried out. Trace
mode is disabled during execution of the instruction that caused the address error and during the
address error exception handling routine. After return from address error exception handling, one
instruction is executed, then trace mode resumes.
4.5 Interrupts
There are five external sources of interrupt exception handling (NMI, ,540, ,541, ,542, ,543) and
39 sources in the on-chip supporting modules. Table 4-4 classifies the interrupt sources. The on-
chip supporting modules that can request interrupts are the 16-bit integrated timer pulse unit
(IPU), serial communication interfaces 1 and 2 (SCI1 and SCI2), A/D converter, and watchdog
timer (WDT).
NMI is the highest-priority interrupt and is always accepted*. The other 43 interrupt sources are
controlled by the interrupt controller. The interrupt controller arbitrates between simultaneous
interrupts by means of internal registers in which interrupt priorities are assigned to each module.
The interrupt priorities are set in interrupt priority registers A to F (IPRA to IPRF) in the interrupt
controller. An interrupt priority level from 7 to 0 can be assigned to IRQ0. A single priority level
from 7 to 0 can be assigned collectively to IRQ1, IRQ2, and IRQ3. Independent priority levels
from 7 to 0 can also be assigned to each of the on-chip supporting modules.
Rev. 3.0, 02/99, page 92 of 904

The interrupt controller also controls the starting of the data transfer controller (DTC) in response
to an interrupt. The DTC can transfer data in either direction between memory and I/O without
using the CPU.
Whether to start the DTC can be selected on an individual interrupt basis in data transfer enable
registers A to F (DTEA to DTEF) in the interrupt controller. The DTC is started if the
corresponding bit in DTEA to DTEF is set to 1. If this bit is cleared to 0, interrupt exception
handling is carried out. A few interrupts, including NMI, cannot start the DTC. The CPU halts
during DTC operation.
For details of DTC interrupts, see section 7, "Data Transfer Controller." Interrupt controller
functions are detailed in section 6, "Interrupt Controller."
Table 4-4 Interrupt Sources
Interrupt Category Number of Sources

External interrupts NMI 1
IRQ0 1
IRQ1-IRQ3 3
Internal interrupts IPU 29
SCI1 4
SCI2/SCI3 4
A/D converter 1
WDT 1
4.6 Invalid Instructions

An invalid instruction is an instruction with an undefined operation code or illegal addressing
mode. If an attempt is made to execute an invalid instruction, the H8/500 CPU starts invalid
instruction exception handling. The PC value pushed on the stack is the value of the program
counter when the invalid instruction code was detected.
In the invalid instruction exception-handling sequence the T bit of the status register is cleared to
0, but the interrupt mask level (I2 to I0) is not changed.
Rev. 3.0, 02/99, page 93 of 904

4.7 Trap Instructions and Zero Divide
When the TRAPA or TRAP/VS instruction is executed, the H8/500 CPU starts trap exception
handling. If an attempt is made to execute a DIVXU instruction with a zero divisor, the H8/500
CPU starts zero divide exception handling.
In the exception-handling sequences for these exceptions the T bit of the status register is cleared
to 0, but the interrupt mask level (I2 to I0) is not changed.
If a normal interrupt is requested during execution of a trap or zero-divide instruction, interrupt

handling begins after the exception-handling sequence for the trap or zero-divide instruction has
been executed.
(1) TRAPA Instruction: When the TRAPA instruction is executed, the H8/500 CPU starts
exception handling according to the CPU operating mode.
The TRAPA instruction includes a vector number from 0 to 15. The start address is read from the
corresponding location in the vector table.
(2) TRAP/VS Instruction: When the TRAP/VS instruction is executed, the H8/500 CPU starts
exception handling if the overflow (V) flag in the condition code register (CCR) is set to 1.
If the V flag is cleared to 0, no exception occurs and the next instruction is executed.
(3) DIVXU Instruction with Zero Divisor: The H8/500 CPU starts exception handling if an
attempt is made to divide by zero in a DIVXU instruction.
Rev. 3.0, 02/99, page 94 of 904

4.8 Cases in which Exception Handling is Deferred
Exception handling of address errors, trace exceptions, external interrupt requests (NMI, ,540,
,541, ,542, ,543), and internal interrupt requests (39 sources) is not carried out immediately after
execution of an interrupt-disabling instruction, reset exception, or data transfer cycle, but is
deferred until after the next instruction has been executed.
4.8.1 Instructions that Disable Exception Handling
Interrupts are disabled immediately after the execution of five instructions: XORC, ORC, ANDC,
LDC, and RTE.
After executing one of these instructions, the H8/500 CPU always executes the next instruction. If
the next instruction is also one of these five, the next instruction after that is executed too.
Exception handling starts after the next instruction that is not one of these five has been executed.
See the following example.
Example:
Program flow
Interrupt controller notifies H8/500 CPU

LDC.B #H'00,TP
of interrupt request
MOV.W #H'FE80,SP
H8/500 CPU executes next instruction before
starting exception handling
MOV.B #H'00,@WCR To exception handling
Rev. 3.0, 02/99, page 95 of 904

4.8.2 Disabling of Exceptions Immediately after a Reset
After carrying out reset exception handling, the H8/500 CPU always executes the initial
instruction.
If an interrupt is accepted after a reset but before SP is initialized, the program counter and status
register will not be saved correctly, leading to a program crash. To prevent this, in minimum
mode the first instruction after a reset should initialize SP. In maximum mode, the first instruction
after a reset should be an LDC instruction initializing TP, and the next instruction should initialize
SP.
4.8.3 Disabling of Interrupts after a Data Transfer Cycle
If an interrupt starts the data transfer controller and a second interrupt is requested during the data
transfer cycle, when the data transfer cycle ends, the H8/500 CPU always executes the next
instruction before handling the second interrupt.
Even if a nonmaskable interrupt (NMI) occurs during a data transfer cycle, it is not accepted until
the next instruction has been executed. An example is shown next.
Example:
Program flow
DTC interrupt request

ADD.W R2,R0
Data transfer cycle NMI request
MOV.W R0,@H'EF00 After data transfer cycle, H8/CPU executes

next instruction before starting exception
handling
MOV.W @H'EF02,R0 To NMI exception handling
Rev. 3.0, 02/99, page 96 of 904

4.9 Stack Status after Completion of Exception Handling
The status of the stack after exception handling is described next.
Table 4-5 shows the stack after completion of exception handling for various types of exceptions
in minimum and maximum modes.
Table 4-5 Stack after Exception Handling
Exception
Source Minimum Mode Maximum Mode
Trace, interrupt,
trap instruction,
DIVXU SP SR (upper 8 bits) TP:SP SR (upper 8 bits)
(zero divide) SR (lower 8 bits)
SR (lower 8 bits)
Next instruction address (upper 8 bits) Don't care
Next instruction address (lower 8 bits) Next instruction page address (8 bits)
Next instruction address (upper 8 bits)
Next instruction address (lower 8 bits)
Note: The RTE instruction returns to the next instruction after the instruction being executed when
the exception occurred.
Invalid instruction
SP SR (upper 8 bits) TP:SP SR (upper 8 bits)

SR (lower 8 bits) SR (lower 8 bits)
PC (upper 8 bits) when error occurred Don't care
PC (lower 8 bits) when error occurred CP (8 bits) when error occurred
PC (upper 8 bits) when error occurred
PC (lower 8 bits) when error occurred
Note: The CP and PC values pushed on the stack are not necessarily the address of the first byte
of the invalid instruction.
Address error
SP SR (upper 8 bits) TP:SP SR (upper 8 bits)

SR (lower 8 bits) SR (lower 8 bits)
PC (upper 8 bits) when error occurred Don't care
PC (lower 8 bits) when error occurred CP (8 bits) when error occurred
PC (upper 8 bits) when error occurred
PC (lower 8 bits) when error occurred
Note: The CP and PC values pushed on the stack are the address of the next instruction after
the last instruction executed.
Rev. 3.0, 02/99, page 97 of 904

4.9.1 PC Value Pushed on Stack for Trace, Interrupts, Trap Instructions, and Zero
Divide Exceptions
The PC value pushed on the stack for a trace, interrupt, trap, or zero divide exception is the
address of the next instruction at the time when the interrupt was accepted.
4.9.2 PC Value Pushed on Stack for Address Error and Invalid Instruction Exceptions
The PC value pushed on the stack for an address error or invalid instruction exception differs
depending on the conditions when the exception occurs.
4.10 Notes on Use of the Stack

When using the stack, pay attention to the following points. Mistakes may lead to address errors
when the stack is accessed, or may cause system crashes.
1. Always set SP on an even address.

If SP indicates an odd address, an address error will occur when the H8/500 CPU accesses the
stack during interrupt handling or for a subroutine call. To keep SP pointing to an even
address, always use word data size when saving or restoring register data or other data to or
from the stack.
2. @−SP and @SP+ addressing modes
To keep SP pointing to an even address, in the @−SP and @SP+ addressing modes the H8/500
CPU performs word access even if the instruction specifies byte size.
This is not true in the @−Rn (pre-decrement) and @Rn+ (post-increment) addressing modes
when Rn is a register from R0 to R6.
Rev. 3.0, 02/99, page 98 of 904

Section 5 H8 Multiplier (H8MULT)
5.1 Overview
The on-chip multiplier module (H8MULT) can perform 16-bit × 16-bit signed or unsigned
multiply and multiply-accumulate operations. These operations can be speeded up by a bus-
stealing function.
5.1.1 Features
Features of the H8MULT module are listed below.
• 16-bit × 16-bit multiplication executed in two clock cycles

Signed or unsigned multiplication can be selected. Up to three multiplier values can be
designated in advance.
• Multiply-and-accumulate operations can be executed in three clock cycles
Saturating or non-saturating operation can be selected. The results of non-saturating multiply-
accumulate operations are stored in 42-bit form. The results of saturating multiply-accumulate
operation are stored in 32-bit form. Up to three multiplier values can be designated in the
H8MULT registers in advance, an arrangement ideally suited for second-order digital filtering.
• Built-in bus-stealing function
For higher-speed operation, the bus-stealing function enables multipliers and multiplicands to
be loaded into H8MULT while the CPU is reading memory.
Rev. 3.0, 02/99, page 99 of 904

5.1.2 Block Diagram
Figure 5-1 shows a block diagram of the H8MULT module.
Internal address bus (A15 to A0)
Internal data bus (D15 to D0)
MLTBR
MLTCR MLTAR MLTMAR
S-ON
Module data bus
MAC,
MUL,
CLR
MCA
Multiplier matrix
MACXH MCB
MACH
MCC
MACL
MR
Legend
MLTCR: MULT control register
MLTAR: MULT multiplier address register MMR
MLTMAR: MULT multiplicand address register
MLTBR: MULT base address register
MCA: MULT multiplier register A
MCB: MULT multiplier register B
MCC: MULT multiplier register C
MACXH: MULT result register, extended high word
MACH: MULT result register, high word
MACL: MULT result register, low word
MR: MULT immediate multiplier register
MMR: MULT immediate multiplicand register
Figure 5-1 H8MULT Block Diagram
Rev. 3.0, 02/99, page 100 of 904

Table 5-1 summarizes the internal registers of the H8MULT module. The type of operation
(multiply or multiply-accumulate, signed or unsigned) and the bus-stealing function can be
selected by register settings.
Table 5-1 H8MULT Registers
Type Address Name Abbreviation R/W Initial Value

Control H'FFA0 MULT control register MLTCR R/W H'38
registers
H'FFA1 MULT base address register MLTBR R/W H'00
H'FFA2 MULT multiplier address MLTAR R/W H'00
register
H'FFA3 MULT multiplicand address MLTMAR R/W H'00
register
Arithmetic H'FFB0 MULT multiplier register A MCA R/W H'0000
1
registers*
H'FFB2 MULT multiplier register B MCB R/W H'0000
H'FFB4 MULT multiplier register C MCC R/W H'0000
H'FFB6 MULT result register, extended MACXH R/W Undetermined
high word
2
H'FFB8 MULT result register, high word MACH R/W* Undetermined
2
H'FFBA MULT result register, low word MACL R/W* Undetermined
H'FFBC MULT immediate multiplier MR W Undetermined
register
H'FFBE MULT immediate multiplicand MMR W Undetermined
register
Notes: 1. The arithmetic registers require word-size access. Byte-size access is not supported.
If byte-size access is attempted, subsequent results may be incorrect.
2. MULT result registers MACH and MACL cannot be modified independently. Write
access to MACH must be immediately followed by write access to MACL, so that the
modification takes place 32 bits at a time.
Example: MOV.W #aa:16, @MACH
MOV.W #aa:16, @MACL
These instructions must be executed consecutively.
Rev. 3.0, 02/99, page 101 of 904

5.2 Register Descriptions
This section describes the H8MULT registers.
5.2.1 MULT Control Register
The MULT control register (MLTCR) is an eight-bit readable/writable register that clears the
MULT result registers, selects the type of multiplication operation, and selects the bus-stealing
function. The bit structure of MLTCR is shown next.
Bit 7 6 5 4 3 2 1 0
CLR S_ON − − − SIGN MUL MAC
R/W R/W R/W R R R R/W R/W R/W
Multiply-accumulate bit
Enables or disables the
multiply-accumulate
function
Multiply bit
Enables or disables
the multiply function
Sign bit
Selects signed arithmetic
Reserved bits
Bus-steal on bit
Enables or disables the bus-stealing function
Clear bit
Simplifies the procedure for initializing MULT result
registers MACXH, MACH, and MACL
Bit 7—Clear (CLR): The purpose of this bit is to simplify the procedure for initializing MULT
result registers MACXH, MACH, and MACL. If the CLR bit is set to 1, when a write access is
made to one of these three registers (MACXH, MACH, or MACL), regardless of the value of the
write data, the other two registers are initialized to H'0000.
Rev. 3.0, 02/99, page 102 of 904

Bit 6—Bus-Steal On (S_ON): Enables or disables the bus-stealing function. If the S_ON bit is set
to 1, data can be set in the MULT registers at the same time as the CPU accesses memory. If the
S_ON bit is cleared to 0, this bus-stealing function is disabled.
For further information, see section 5.3.3 "Bus-Stealing Function."
Bits 5 to 3—Reserved: These bits are reserved for future expansion. They are always read as 1
and cannot be modified.
Bit 2—Sign (SIGN): Specifies signed arithmetic. The multiplication is performed in signed mode
if the SIGN bit is set to 1, and in unsigned mode if the SIGN bit is cleared to 0. When a multiply-
accumulate operation is executed, the operation is performed in non-saturating mode or saturating
mode. The results of saturating multiply-accumulate operations are stored in 32-bit form of
MACH and MACL registers. In this case, MACXH register is not used. When an overflow occurs,
set bit 0 in the MACXH register to 1. The results of non-saturating multiply-accumulate
operations are stored in 42-bit form of MACXH, MACH, and MACL registers. In this case, an
overflow is not detected.
For details on the SIGN bit and the operation contents, see section 5.3.4 "Multiply and Multiply-
Accumulate Functions."
Bit 1—Multiply (MUL): Enables or disables the multiply function. The multiply function is
enabled when the MUL bit is set to 1. Do not set both the MUL bit and MAC bit (bit 0) to 1 at the
same time. If both bits are set to 1, neither function is enabled.
Bit 0—Multiply-Accumulate (MAC): Enables or disables the multiply-accumulate function. The

multiply-accumulate function is enabled when the MAC bit is set to 1. Do not set both the MAC
bit and MUL bit (bit 1) to 1 at the same time. If both bits are set to 1, neither function is enabled.
5.2.2 MULT Base Address Register
The MULT base address register (MLTBR) is a readable/writable register that specifies the upper
eight bits of the memory address of the multiplier or multiplicand in multiply or multiply-
accumulate operations when the bus-stealing function is enabled.
Bit 7 6 5 4 3 2 1 0
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Rev. 3.0, 02/99, page 103 of 904

5.2.3 MULT Multiplier Address Register
The MULT multiplier address register (MLTAR) is a readable/writable register that specifies the
lower eight bits of the memory address of the multiplier in multiply or multiply-accumulate
operations when the bus-stealing function is enabled.
Bit 7 6 5 4 3 2 1 0
5.2.4 MULT Multiplicand Address Register
The MULT multiplicand address register (MLTMAR) is a readable/writable register that specifies
the lower eight bits of the memory address of the multiplicand in multiply or multiply-accumulate
operations when the bus-stealing function is enabled.
Bit 7 6 5 4 3 2 1 0
5.2.5 MULT Multiplier Register A
MULT multiplier register A (MCA) is a 16-bit readable/writable register that stores a multiplier
for use in multiply or multiply-accumulate operations.
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Note: MCA requires word-size access.
Rev. 3.0, 02/99, page 104 of 904

5.2.6 MULT Multiplier Register B
MULT multiplier register B (MCB) is a 16-bit readable/writable register that stores a multiplier
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Note: MCB requires word-size access.
5.2.7 MULT Multiplier Register C
MULT multiplier register C (MCC) is a 16-bit readable/writable register that stores a multiplier
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Note: MCC requires word-size access.
5.2.8 MULT Immediate Multiplier Register
The MULT immediate multiplier register (MR) is a 16-bit write-only register into which a
multiplier value can be loaded for use in multiply or multiply-accumulate operations.
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Initial value − − − − − − − − − − − − − − − −
R/W W W W W W W W W W W W W W W W W
MR is a write-only register. When read, it always returns H'FFFF.
Note: MR requires word-size access.
Rev. 3.0, 02/99, page 105 of 904

5.2.9 MULT Immediate Multiplicand Register
The MULT immediate multiplicand register (MMR) is a 16-bit write-only register into which a
multiplicand value can be loaded for use in multiply or multiply-accumulate operations.
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Initial value − − − − − − − − − − − − − − − −
R/W W W W W W W W W W W W W W W W W
MMR is a write-only register. When read, it always returns H'FFFF.
Note: MMR requires word-size access.
5.2.10 MULT Result Register, Extended High Word
The MULT result register (MACXH) is a 16-bit readable/writable register that stores the upper 10
bits of the 42-bit result of a non-saturating multiply-accumulate operation. The sign-extended
value of bit 9 is set in bits 15 to 10 of MACXH.
MACXH is not used in multiply operations, and bits 15 to 1 are not used in saturating multiply-
accumulate operations.
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Initial value − − − − − − − − − − − − − − − −
Bit 0 of the MACXH register is an overflow flag (OVF) that is set to 1 when the result of a
saturating multiply-accumulate operation overflows.
Note: MACXH requires word-size access.
5.2.11 MULT Result Register, High Word
The MULT result register, high word (MACH) is a 16-bit readable/writable register that stores bits
31 to 16 of a non saturating multiply-accumulate operation.
Rev. 3.0, 02/99, page 106 of 904

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Initial value − − − − − − − − − − − − − − − −
Note: MACH requires word-size access.
5.2.12 MULT Result Register, Low Word
The MULT result register, low word (MACL) is a 16-bit readable/writable register that stores bits
15 to 0 of a non saturating multiply-accumulate operation.
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Initial value − − − − − − − − − − − − − − − −
Note: MACL requires word-size access.
5.3 Operation
The operation of the H8/539F’s on-chip multiplier module will be described in the following
order: initialization of MULT result registers; register write; bus-stealing function; then multiply
and multiply-accumulate operations.
5.3.1 Initialization of MULT Result Registers
MULT result registers MACXH, MACH, and MACL are not initialized by a reset. In a multiply-
accumulate operation, in which the multiplication result is added to the value in the MULT result
registers, the MULT result registers must be initialized before use, either by clearing them or by
writing the necessary values in them ahead of time. Initialization is not necessary when these
registers are only used for multiplication.
Initialization should be performed by one of the following methods.
(1) Individual Register Initialization: The registers can be initialized by writing to them
individually. The MACH and MACL registers must be written to consecutively.
Rev. 3.0, 02/99, page 107 of 904

Example:
MOV.W #H'0000, @MACXH

MOV.W #H'0000, @MACH; Do not change the order of these two instructions
MOV.W #H'0000, @MACL
or
CLR.W @MACXH
CLR.W @MACH ; Do not change the order of these two instructions
CLR.W @MACL
(2) One-Step Initialization: All three registers can be initialized at once. MACXH, MACH, and
MACL are all initialized to #H'0000, regardless of the write data.
Example:
BSET.B #7, @MLTCR ; Set CLR bit in MLTCR

MOV.W #aa:16, @MACXH; Destination can be @MACH or @MACL instead
(BCLR.B #7, @MLTCR)
The one-step initialization function operates at a write access to MACXH, MACH, or MACL. It
does not operate at a read access, or a write access to any other register, so the CLR bit does not
necessarily have to be cleared to 0 after one-step initialization.
5.3.2 Writing to MULT Multiplier Registers
The MULT multiplier registers (MCA, MCB, MCC) can be loaded by writing to them directly, or
by bus stealing. The bus-stealing function and direct writing are performed independently for
MCA, MCB, and MCC, so both types of loading can be used together.
(1) Direct Writing: This method writes to MCA, MCB, or MCC by direct addressing. Specify
the address of MCA, MCB, or MCC as the destination operand in a write instruction. Be sure to
use a word-size instruction.
Example:
MOV.W #aa:16, @MCA ; Write 16-bit data #aa in MCA
(2) Loading Data by Bus Stealing: When the CPU accesses its memory address space, the data
on the data bus can be loaded automatically into a MULT multiplier register (bus stealing). Bus
stealing is performed only for particular addresses, which are specified in the MULT multiplier
address register (MLTAR) and MULT base address register (MLTBR).
For further information, see section 5.3.3 "Bus-Stealing Function."

Rev. 3.0, 02/99, page 108 of 904
Example:
BSET.B #6, @MLTCR ;

MOV.B #H'FE, @MLTBR ; Set up bus-stealing function
MOV.B #H'80, @MLTAR ;
MOV.W #aa:16, @FE80 ; Write data #aa:16 to @FE80 and load same data into MCA
·
·
·
MOV.W @FE80, R0 ; Read data from @FE80 and load same data into MCA
· ; TST.W @FE80 instruction would do the same
·
·
5.3.3 Bus-Stealing Function
The bus-stealing function loads the value on the data bus into the H8MULT module when the
CPU accesses its memory address space. The bus-stealing function can be used to multiply or
multiply-and-accumulate two values stored in memory.
The bus-stealing function can be enabled or disabled by bit 6 (S_ON) in the MULT control
register (MLTCR).
(1) Loading of Multiplier by Bus Stealing: Figure 5-2 shows the loading of data into register
MCA by bus stealing. If the S_ON bit is set to 1, the H8MULT module monitors the address bus
when the CPU accesses its memory address space, and compares the address on the bus with the
MULT base address register (MLTBR) and MULT multiplier address register (MLTAR).
If MLTBR (upper 8 bits) and MLTAR (lower 8 bits) = @aa:16, the data on the data bus is loaded
into MULT multiplier register A (MCA).
If MLTBR (upper 8 bits) and MLTAR (lower 8 bits) + 2 = @aa:16, the data on the data bus is
loaded into MULT multiplier register B (MCB).
If MLTBR (upper 8 bits) and MLTAR (lower 8 bits) + 4 = @aa:16, the data on the data bus is
loaded into MULT multiplier register C (MCC).
Rev. 3.0, 02/99, page 109 of 904

Direct write control section Bus-stealing control section
Address bus (@aa:16)
Data bus (#aa:16)
Upper 8 Lower 8
address bits address bits
Address decoder MLTBR MLTAR
(@aa: 16)
Write
Address comparator
Match
S_ON (MLTCR bit 6)
MCA (#aa: 16)
Bus Read/write
MCB interface
MCC Controls writing to registers
Data on bus loaded into MCA
Figure 5-2 Loading of Data into Register MCA by Bus Stealing
(2) Loading of Multiplicand and Activation of Multiplier by Bus Stealing: Figure 5-3 shows
the loading of the multiplicand and automatic selection of the multiplier register by bus stealing. If
the S_ON bit is set to 1, the H8MULT module monitors the address bus when the CPU accesses
its memory address space, and compares the address on the bus with the MULT base address
register (MLTBR) and MULT multiplicand address register (MLTMAR).
If MLTBR (upper 8 bits) and MLTMAR (lower 8 bits) = @aa:16, the data on the data bus is
loaded as the multiplicand, the multiplier is fetched from MULT multiplier register A (MCA), and
these values are multiplied, or multiplied and accumulated.
If MLTBR (upper 8 bits) and MLTMAR (lower 8 bits) + 2 = @aa:16, the multiplier is fetched
from MULT multiplier register B (MCB).
If MLTBR (upper 8 bits) and MLTMAR (lower 8 bits) + 4 = @aa:16, the multiplier is fetched
from MULT multiplier register C (MCC).
Rev. 3.0, 02/99, page 110 of 904

Address bus (@aa:16)
Data bus (#aa:16)
Upper 8 Lower 8
Activate multiplier address bits address bits
matrix MLTBR MLTMAR
(@aa: 16)
Multiplicand
Address comparator
Match
Multiplier matrix
S_ON (MLTCR bit 6)
Multiplier
Read/write
MCA (#aa: 16) Bus-stealing control section

Bus
MCB interface
MCC Multiplier selected automatically
Figure 5-3 Loading of Multiplicand and Activation of Multiplier by Bus Stealing
5.3.4 Multiply and Multiply-Accumulate Functions
The H8MULT module can execute 16 × 16-bit multiplication, and accumulate products up to a
data length of 42 bits. The multiplier and multiplicand on which arithmetic is carried out can be
specified in two ways. They can be loaded directly into the H8MULT module, or data in memory
can be loaded into the H8MULT module by the bus-stealing function. Multiply and multiply-
accumulate operations are described below.
(1) Multiply: Direct Loading of Multiplier and Multiplicand: The procedure is given next.
(a) Select the multiply function.

 Unsigned multiplication: Set bits 2 to 0 (SIGN, MUL, MAC) in the MULT control register
(MLTCR) to 010.
 Signed multiplication: Set MLTCR bits 2 to 0 (SIGN, MUL, MAC) to 110.
Thre results are stored in 42-bit form of MACXH, MACH and MACL registers. In this case,
an overflow is not detected.
(b) Set the multiplier and multiplicand.
Load the multiplier into the MULT immediate multiplier register (MR), then load the
multiplicand into the MULT immediate multiplicand register (MMR). The multiplier matrix is
activated automatically when the multiplicand is loaded.
Rev. 3.0, 02/99, page 111 of 904
Be sure to use word-size data transfer instructions to load the multiplier and multiplicand. The
instruction that loads MMR must be executed immediately after the instruction that loads MR.
A coding example is given next.
Example: signed multiplication, #AAAA × #BBBB
MOV.B #06, @MLTCR ; SIGN = 1, MUL = 1

MOV.W #AAAA, @MR ; Load multiplier
MOV.W #BBBB, @MMR ; Load multiplicand and start multiplying
(2) Multiply: Multiplier Loaded by Bus Stealing, Multiplicand Loaded Directly: The
procedure is given next.

See under (1).
(b) Select the bus-stealing function.
Set bit 6 (S_ON) to 1 in the MULT control register (MLTCR), and specify the address at
which the multiplier will be located in the MULT base address register (MLTBR) and MULT
multiplier address register (MLTAR). The multiplier can be located in any of three words
starting at the specified address. Place the upper eight bits of the address in MLTBR and the
lower eight bits in MLTAR. See the example in figure 5-4.
Memory
H8MULT
MLTBR #EE Set this address

MLTAR #80
H'EE80 #(multiplier 0)
Figure 5-4 MLTBR and MLTAR Settings
(c) Set the multiplier and multiplicand

The multiplicand must be set immediately after the multiplier. First access the multiplier in
memory, then load the multiplicand into MMR. The multiplier matrix is activated
automatically when the multiplicand is loaded.
Be sure to use word-size instructions to access the multiplier in memory and load the
multiplicand. These instructions must be executed consecutively.
A coding example is given next. Figure 5-5 shows the data flow.
Rev. 3.0, 02/99, page 112 of 904

Example: Unsigned multiplication, multiplier × #BBBB, multiplier loaded from @EE80 on
memory by bus stealing
MOV.B #42, @MLTCR ; S_ON = 1, MUL = 1

MOV.B #EE, @MLTBR
MOV.B #80, @MLTAR ; Multiplier address = #EE80
MOV.W @EE80, R0 ; Access multiplier address

; Bus-stealing function loads multiplier into MCA
MOV.W #BBBB, @MMR ; Load multiplicand to start multiplying
multiplier × #BBBB
Memory
R0
H8MULT H'EE80 #(multiplier 0)
MLTBR #EE H'EE82 #(multiplier 1)
MLTAR #80 H'EE84 #(multiplier 2)
Multiplier matrix
#BBBB #(multiplier 0) is loaded by bus stealing
into MCA and multiplier matrix
MCA
MCB
MCC
Figure 5-5 Multiplication Data Flow
(3) Multiply: Multiplier and Multiplicand Loaded by Bus Stealing

See under (1).
See under (2) (b).
To load the multiplicand by bus stealing, in addition to the steps in (2) (b), set the lower eight
bits of the address where the multiplicand will be located in the MULT multiplicand address
register (MLTMAR). See the example in figure 5-6.
Rev. 3.0, 02/99, page 113 of 904

Memory
H8MULT
MLTBR #EE H'EE80 #(multiplier 0)
MLTAR #80 H'EE82 #(multiplier 1)
MLTMAR #A0 H'EE84 #(multiplier 2)
H'EEA0 #(multiplicand 0)
Figure 5-6 MLTBR, MLTAR, and MLTMAR Settings

Access the multiplier, then the multiplicand. The two accesses do not have to be consecutive.
When the multiplier is accessed in memory, it is temporarily stored in one of the MULT
multiplier registers (MCA, MCB, or MCC) by the bus-stealing function. After that, when the
multiplicand is accessed, the multiplier is fetched from MCA, MCB, or MCC, the multiplier
and multiplicand are both loaded into the H8MULT module, and multiplication begins.
The register from which the multiplier is fetched is determined by the multiplicand address.
For details see section 5.3.3 "Bus-Stealing Function." A coding example is given next. Figure
5-7 shows the data flow.
Example: Unsigned multiplication, multiplier (@EE80) × multiplicand (@EEA0), loaded
from memory by bus stealing
MOV.B #42, @MLTCR ; S_ON = 1, MUL = 1

MOV.B #EE, @MLTBR
MOV.B #A0, @MLTMAR ; Multiplicand address = #EEA0

MOV.W @EEA0, R0 ; Access multiplicand address; H8MULT loads

; multiplicand by bus-stealing function, gets
; multiplier from MCA, loads multiplier into
; multiplier matrix, and starts multiplying
Rev. 3.0, 02/99, page 114 of 904

(4) Multiply and Accumulate: Direct Loading of Multiplier and Multiplicand: The procedure
is given next.
(a) Select the multiply-accumulate function.

 Saturating accumulation: Set bits 2 to 0 (SIGN, MUL, MAC) in the MULT control register
(MLTCR) to 001. The results are stored in 32-bit form in the MACH and MACL registers.
When an overflow occurs, bit 0 in the MACXH register is set to 1.
 Non-saturating accumulation: Set bits 2 to 0 (SIGN, MUL, MAC) in the MULT control
register (MLTCR) to 101. The results are stored in 42-bit form in the MACXH, MACH,
and MACL registers. In this case, an overflow is not detected.
(b) Set a constant and specify the multiplier and multiplicand.
First set a constant in the MULT result registers (MACXH, MACH, MACL), or clear these
registers. Next load the multiplier into the MULT immediate multiplier register (MR), then
load the multiplicand into the MULT immediate multiplicand register (MMR). The multiplier
matrix is activated automatically when the multiplicand is loaded.
The operation performed is (multiplier) × (multiplicand) + (constant).
Be sure to use word-size data transfer instructions to load the multiplier and multiplicand. The
instruction that loads MMR must be executed immediately after the instruction that loads MR.
Example: Non-saturating multiply-accumulate, #AAAA × #BBBB + #CCCC
BSET.B #7, @MLTCR ; CLR = 1

CLR.W @MACXH ; Initialize MACXH, MACH, and MACL
BCLR.B #7, @MLTCR ; CLR = 0
MOV.W #0000, @MACH

MOV.W #CCCC, @MACL ; Set 32-bit constant
MOV.B #05, @MLTCR ; SIGN = 1, MUL = 1
MOV.W #AAAA, @MR ; Load multiplier
MOV.W #BBBB, @MMR ; Load multiplicand and start multiplying
(5) Multiply and Accumulate: Multiplier Loaded by Bus Stealing, Multiplicand Loaded
Directly: The procedure is given next.

See under (4).
Rev. 3.0, 02/99, page 115 of 904

Set bit 6 (S_ON) to 1 in the MULT control register (MLTCR), and specify the address at
which the multiplier will be located in the MULT base address register (MLTBR) and MULT
multiplier address register (MLTAR). The multiplier can be located in any of three words
starting at the specified address. Place the upper eight bits of the address in MLTBR and the
lower eight bits in MLTAR.
The multiplicand must be set immediately after the multiplier. First access the multiplier in
memory, then load the multiplicand into MMR. The multiplier matrix is activated
automatically when the multiplicand is loaded.
Be sure to use word-size instructions to access the multiplier in memory and load the
multiplicand. These instructions must be executed consecutively.
Example: Saturating accumulation, multiplier × #BBBB + #CCCC, multiplier loaded from
@EE80 on memory by bus stealing

CLR.W @MACXH ;
MOV.W #0000, @MACH

MOV.W #CCCC, @MACL
MOV.B #41, @MLTCR ; S_ON = 1, MAC = 1
MOV.B #EE, @MLTBR

Bus-stealing function loads multiplier into MCA
MOV.W #BBBB, @MMR ; Load multiplicand to start multiply-accumulate
; operation multiplier × #BBBB + #CCCC.
(6) Multiply and Accumulate: Multiplier and Multiplicand Loaded by Bus Stealing

See under (4).
See under (5) (b).
To load the multiplicand by bus stealing, in addition to the steps in (5) (b), set the lower eight
bits of the address where the multiplicand will be located in the MULT multiplicand address
register (MLTMAR).
Rev. 3.0, 02/99, page 116 of 904

Access the multiplier, then the multiplicand. The two accesses do not have to be consecutive.
When the multiplier is accessed in memory, it is temporarily stored in one of the MULT
multiplier registers (MCA, MCB, or MCC) by the bus-stealing function. After that, when the
multiplicand is accessed, the multiplier is fetched from MCA, MCB, or MCC, the multiplier
and multiplicand are both loaded into the H8MULT module, and multiplication begins.
The register from which the multiplier is fetched is determined by the multiplicand address.
For details see section 5.3.3 "Bus-stealing function." A coding example is given next.
Example: Saturating multiplication and accumulation, bus stealing, multiplier (@EE80) ×

multiplicand (@EEA0) + #CCCC

CLR.W @MACXH
MOV.W #0000, @MACH

MOV.W #CCCC, @MACL
MOV.B #41, @MLTCR ; S_ON = 1, MAC = 1
MOV.B #EE, @MLTBR
MOV.B #A0, @MLTAR ; Multiplicand address = #EEA0

MOV.W @EEA0, R0 ; Access multiplicand address; H8MULT loads

; multiplicand by bus-stealing function, fetches
; multiplier from MCA, loads multiplier into
; multiplier matrix, and starts multiplying
Rev. 3.0, 02/99, page 117 of 904

Section 6 Interrupt Controller
6.1 Overview
The interrupt controller decides when to start interrupt exception handling and when to start the
data transfer controller (DTC), and arbitrates between competing interrupts. This section
describes the interrupts and the functions, features, internal structure, and registers of the interrupt
controller.
For details of data transfers performed by the DTC, see section 7, "Data Transfer Controller."
6.1.1 Features
The features of the interrupt controller are:
• Six interrupt priority registers (IPR)

Priority levels from 7 to 0 can be assigned to IRQ0, IRQ1 to IRQ3, and each of the on-chip
supporting modules, covering all interrupts except NMI.
• Default priority order for simultaneous interrupts on the same level
Lower-priority interrupts remain pending until higher-priority interrupts have been handled.
NMI has the highest priority level (8) and cannot be masked.*
• Six data transfer enable (DTE) registers
Software can select which interrupts (other than NMI) to have served by the DTC.
Rev. 3.0, 02/99, page 119 of 904

6.1.2 Block Diagram
Figure 6-1 shows a block diagram of the interrupt controller.
Interrupt controller
NMI NMI
request
Priority decision logic

IRQ0
IRQ1 to IRQ 3 IPRA . . . IPRF
Interrupt request signals
IPU
from modules
Comparator
WDT
SCI1
Interrupt
SCI2/SCI3 request
A/D converter
DTEA . . . DTEF
DTC
request
I2 I1 I0 SR (CPU)
Legend
IPU: Integrated-timer pulse unit
WDT: Watchdog timer
SCI: Serial communication interface
SR: Status register
IPR: Interrupt priority register
DTE: Data transfer enable register
Figure 6-1 Block Diagram of Interrupt Controller
6.1.3 3Register Configuration
The interrupt controller has six interrupt priority registers (IPRA to IPRF) and six data transfer
enable registers (DTEA to DTEF). See section 7.2.5, "Data Transfer Enable Registers A to F" for
details of DTEA to DTEF.
Table 6-1 summarizes these registers.

Rev. 3.0, 02/99, page 120 of 904
Table 6-1 Interrupt Controller Registers

H'FF00 Interrupt priority register A IPRA R/W H'00
H'FF01 Interrupt priority register B IPRB R/W H'00
H'FF02 Interrupt priority register C IPRC R/W H'00
H'FF03 Interrupt priority register D IPRD R/W H'00
H'FF04 Interrupt priority register E IPRE R/W H'00
H'FF05 Interrupt priority register F IPRF R/W H'00
H'FF08 Data transfer enable register A DTEA R/W H'00
H'FF09 Data transfer enable register B DTEB R/W H'00
H'FF0A Data transfer enable register C DTEC R/W H'00
H'FF0B Data transfer enable register D DTED R/W H'00
H'FF0C Data transfer enable register E DTEE R/W H'00
H'FF0D Data transfer enable register F DTEF R/W H'00
Table 6-2 summarizes the NMI control register (NMICR), IRQ control register (IRQCR), and IRQ
flag register (IRQFR).
Table 6-2 Interrupt Controller Registers

H'FF1C NMI control register NMICR R/W H'FE
H'FF1D IRQ control register IRQCR R/W H'F0
H'FEDE IRQ flag register IRQFR R/W H'F1
6.2 Interrupt Sources

There are two types of interrupts: external interrupts (NMI, IRQ0, and IRQ1 to IRQ3.), and
internal interrupts (39 sources). Table 6-3 indicates the default priority order and vector addresses
of these interrupts.
When multiple interrupts occur simultaneously, the interrupt with the highest priority is served
first. Using IPRA to IPRF, software can assign priorities to interrupts on a module basis. Relative
priorities within the same module are fixed. If the same priority is assigned to two or more
modules, simultaneous interrupt requests from those modules are served in the priority order
shown in table 6-3.
After a reset, all interrupts except NMI are assigned priority 0 and are disabled.
Rev. 3.0, 02/99, page 121 of 904

Table 6-3 Interrupt Priorities and Vector Addresses
Assignable Vector Table Entry Address
Priority Priority Priority among
Levels Corresponding within Minimum Maximum Interrupts on
Interrupt Source (initial value) IPR Bits Module Mode Mode Same Level
NMI 8 (8) − − H'0016–0017 H'002C–002F High
IRQ0 7–0 (0) IPRA 2 H'0040–0041 H'0080–0083
Interval timer upper 1 H'0042–0043 H'0084–0087
A/D ADI 4 bits 0 H'0044–0045 H'0088–008B
converter
IRQ1 7–0 (0) IPRA 2 H'0048–0049 H'0090–0093

IRQ2 lower 1 H'004A–004B H'0094–0097
IRQ3 4 bits 0 H'004C–004D H'0098–009B
IPU IMI1 7–0 (0) IPRB 3 H'0050–0051 H'00A0–00A3
channel IMI2 upper 2 H'0052–0053 H'00A4–00A7
1 CMI1/CMI2 4 bits 1 H'0054–0055 H'00A8–00AB
OVI 0 H'0056–0057 H'00AC–00AF
IMI3 7–0 (0) IPRB 2 H'0058–0059 H'00B0–00B3
IMI4 lower 1 H'005A–005B H'00B4–00B7
CMI3/CMI4 4 bits 0 H'005C–005D H'00B8–00BB
IPU IMI1 7–0 (0) IPRC 3 H'0060–0061 H'00C0–00C3
channel IMI2 upper 2 H'0062–0063 H'00C4–00C7
2 CMI1/CMI2 4 bits 1 H'0064–0065 H'00C8–00CB
OVI 0 H'0066–0067 H'00CC–00CF
IPU IMI1 7–0 (0) IPRC 3 H'0068–0069 H'00D0–00D3
channel IMI2 lower 2 H'006A–006B H'00D4–00D7
3 CMI1/CMI2 4 bits 1 H'006C–006D H'00D8–00DB
OVI 0 H'006E–006F H'00DC–00DF
IPU IMI1 7–0 (0) IPRD 3 H'0070–0071 H'00E0–00E3
channel IMI2 upper 2 H'0072–0073 H'00E4–00E7
4 CMI1/CMI2 4 bits 1 H'0074–0075 H'00E8–00EB
OVI 0 H'0076–0077 H'00EC–00EF
IPU IMI1 7–0 (0) IPRD 3 H'0078–0079 H'00F0–00F3
channel IMI2 lower 2 H'007A–007B H'00F4–00F7
5 CMI1/CMI2 4 bits 1 H'007C–007D H'00F8–00FB
OVI 0 H'007E–007F H'00FC–00FF
IPU IMI1 7–0 (0) IPRE 2 H'0080–0081 H'0100–0103
channel IMI2 upper 1 H'0082–0083 H'0104–0107
6 OVI 4 bits 0 H'0086–0087 H'010C–010F
IPU IMI1 7–0 (0) IPRE 2 H'0088–0089 H'0110–0113
channel IMI2 lower 1 H'008A–008B H'0114–0117
7 OVI 4 bits 0 H'008E–008F H'011C–011F
SCI1 ERI1 7–0 (0) IPRF 3 H'0090–0091 H'0120–0123
RI1 upper 2 H'0092–0093 H'0124–0127
TI1 4 bits 1 H'0094–0095 H'0128–012B
TEI1 0 H'0096–0097 H'012C–012F
SCI2/ ERI2/ERI3 7–0 (0) IPRF 3 H'0098–0099 H'0130–0133
SCI3 RI2/RI3 lower 2 H'009A–009B H'0134–0137
TI2/TI3 4 bits 1 H'009C–009D H'0138–013B
TEI2/TEI3 0 H'009E–009F H'013C–013F Low
Rev. 3.0, 02/99, page 122 of 904

The five external interrupts are NMI and IRQ0 to IRQ3.
Each external interrupt is described below.
6.2.1 NMI Interrupt
NMI has the highest interrupt priority level (8) and cannot be masked*. Input at the NMI pin is
edge-sensed. Either the rising edge or falling edge can be selected by setting or clearing the
nonmaskable interrupt edge bit (NMIEG) in the NMI control register (NMICR).
In NMI exception handling the T bit in the status register (SR) is cleared to 0 and I2 to I0 are all
set to 1, thereby setting the interrupt mask level to 7.
NMI Control Register (Address H'FF1C): The NMI control register (NMICR) selects the
sensitive edge of the NMI input. NMICR is initialized to H'FE by a reset and in hardware standby
mode. It is not initialized in software standby mode. The NMICR bit structure is shown next.
Bit 7 6 5 4 3 2 1 0
− − − − − − − NMIEG
R/W − − − − − − − R/W
Nonmaskable
interrupt edge
Selects sensitive
Reserved bits edge of NMI input
Bit 0—Nonmaskable Interrupt Edge (NMIEG): Selects the sensitive edge of the NMI input.
Bit 0
NMIEG Description
0 NMI is requested on falling edge of NMI input (Initial value)
1 NMI is requested on rising edge of NMI input
Rev. 3.0, 02/99, page 123 of 904

6.2.2 IRQ0 Interrupt
An IRQ0 interrupt can be requested by an interrupt signal from the ,540 pin or an interrupt signal
from the watchdog timer (WDT). These two interrupt sources have different vectors.
The interrupt from the ,540 pin is level-sensed. A ,540 input requests an IRQ0 interrupt if the
interrupt request enable 0 bit (IRQ0E) in the IRQ control register (IRQCR) is set to 1. A WDT
overflow requests an IRQ0 interrupt when the WDT is set to interval timer mode. The WDT then
requests an IRQ0 interrupt each time the timer counter (TCNT) overflows.
A priority level from 7 to 0 can be assigned to IRQ0 in the upper four bits of IPRA. If bit 4 in
DTEA is set to 1, IRQ0 is served by the DTC.
In IRQ0 exception handling the T bit in SR is cleared to 0 and the interrupt mask level is set to the
value selected in the four upper bits of IPRA.
6.2.3 IRQ1 to IRQ3 Interrupt
Interrupts IRQ1 to IRQ3 are requested by interrupt signals from the ,541 to ,543 pins. The ,541
to ,543 inputs are sensed on the falling edge. The falling edge generates an ,541 to I#,543
interrupt request if the interrupt request enable 1, 2, or 3 bit (IRQ1E, IRQ2E, or IRQ3E) in the
IRQ control register (IRQCR) is set to 1.
A priority level from 7 to 0 can be assigned to IRQ1, IRQ2, and IRQ3 collectively in the lower
four bits of IPRA. If bits 2 to 0 in DTEA are set, these interrupts are served by the DTC.
In IRQ1, IRQ2, and IRQ3 exception handling the T bit in SR is cleared to 0 and the interrupt mask
level is set to the value selected in the lower four bits of IPRA.
IRQ Control Register (Address H'FF1D): The IRQ control register (IRQCR) enables and
disables inputs at ,541 to ,543, and ,540. IRQCR is initialized to H'F0 by a reset and in hardware
standby mode. It is not initialized in software standby mode. The bit structure of IRQCR is
shown next.
Bit 7 6 5 4 3 2 1 0
− − − − IRQ3E IRQ2E IRQ1E IRQ0E
R/W − − − − R/W R/W R/W R/W
Interrupt request enable bits

These bits select functions
Reserved bits of ports 6 and 7
Rev. 3.0, 02/99, page 124 of 904

Bit 3—Interrupt Request 3 Enable (IRQ3E): Selects the function of pin P61.
Bit 3
IRQ3E Description
0 P61 is used for general-purpose input and output (Initial value)
1 P61 is used for ,543 input
Bit 2
IRQ2E Description
Bit 1
IRQ1E Description
Bit 0
IRQ0E Description
Rev. 3.0, 02/99, page 125 of 904

IRQ Flag Register (Address H'FEDE): The IRQ flag register (IRQFR) indicates the presence of
IRQ1 to IRQ3 interrupt requests. When an IRQ1 to IRQ3 interrupt is requested by external input,
the H8/500 CPU sets the interrupt request 1, 2, or 3 flag (IRQ1F, IRQ2F, or IRQ3F) to 1. The
interrupt request can be cleared by reading this flag after it has been set to 1, then writing 0. The
H8/500 CPU clears IRQ1F, IRQ2F, or IRQ3F to 0 when it outputs the interrupt vector.
IRQFR is initialized to H'F1 by a reset and in hardware standby mode. It is not initialized in
software standby mode. The bit structure of IRQFR is shown next.
Bit 7 6 5 4 3 2 1 0
− − − − IRQ3F IRQ2F IRQ1F −
R/W − − − − R/W* R/W* R/W* −
Reserved bit
Interrupt request flags

These bits indicate
Reserved bits interrupt request input
Note: * Software can only write 0 to clear the flag.
Bit 3—Interrupt Request 3 Flag (IRQ3F): Indicates that interrupt request 3 (IRQ3) has been
input.
Bit 3
IRQ3F Description
0 Interrupt request 3 (IRQ3) has not been input (Initial value)
1 Interrupt request 3 (IRQ3) has been input and is waiting for interrupt service
[Clearing conditions]
• Cleared to 0 automatically when the H8/500 CPU accepts IRQ3 and the
interrupt vector is output
• Can also be cleared by reading 1, then writing 0, in which case the pending
IRQ3 interrupt request is deleted
Rev. 3.0, 02/99, page 126 of 904

input.
Bit 2
IRQ2F Description
input.
Bit 1
IRQ1F Description
Bit 0—Reserved: Read-only bit, always read as 1.
6.2.4 Internal Interrupts
There are 39 internal interrupt sources in the on-chip supporting modules. A different interrupt
vector address is assigned to each source, so the interrupt handling routine does not have to
determine which interrupt has occurred.
Priority levels from 7 to 0 are assigned to each module in IPRA to IPRF. DTEA to DTEF indicate
which interrupts in each module are served by the DTC.
When an internal interrupt request is accepted, the T bit in SR is cleared to 0 and the interrupt
mask level in I2 to I1 is set to the value selected in IPRA to IPRF.
Rev. 3.0, 02/99, page 127 of 904

6.3.1 Interrupt Priority Registers A to F
The six interrupt priority registers (IPRA to IPRF) assign priority levels from 7 to 0 to interrupt
sources other than NMI. A reset initializes IPRA to IPRF to H'00.
The bit structure of IPRA to IPRF is shown next.
Bit 7 6 5 4 3 2 1 0
0 0
R/W − R/W R/W R/W − R/W R/W R/W
Lower four bits

Upper four bits
Bits 7 to 4—Interrupt Priority, Upper Four Bits: These bits select an interrupt priority level.
Bit 7 must always be cleared to 0.
Bits 3 to 0—Interrupt Priority, Lower Four Bits: These bits select an interrupt priority level.
Bit 3 must always be cleared to 0.
The on-chip supporting modules are mapped onto the interrupt priority registers as shown in table
6-4. Each interrupt priority register is assigned two on-chip supporting modules. The upper four
bits of the interrupt priority register specify the priority level of one module; the lower four bits
specify the priority of the other module.
Table 6-5 indicates how priority levels are set in the interrupt priority registers. For example, to
assign level 7 to SCI1, set bits 6 to 4 in IPRF to 111.
Rev. 3.0, 02/99, page 128 of 904

Table 6-4 On-Chip Supporting Modules and Interrupt Priority Registers
Bits 6 to 4 Bits 2 to 0
Register On-Chip Supporting Module On-Chip Supporting Module
IPRA ,540, WDT, A/D converter ,541 to ,543
IPRB IPU channel 1 IPU channel 1
IPRC IPU channel 2 IPU channel 3
IPRD IPU channel 4 IPU channel 5
IPRE IPU channel 6 IPU channel 7
IPRF SCI1 SCI2/SCI3
Table 6-5 Interrupt Priority Settings in IPRH and IPRL
Bits 6 to 4
or Bits 2 to 0 Interrupt Priority Level
000 0
001 1
010 2
011 3
100 4
101 5
110 6
111 7
6.3.2 Timing of Priority Changes
The interrupt controller requires two system clock cycles (2φ) to determine the priority level of an
interrupt. Therefore, when an instruction modifies an instruction priority register (IPRA to IPRF),
the new priority takes effect starting from the third state after that instruction has been executed.
6.4 Interrupt Operations

Interrupt operations are described next.
6.4.1 Operations up to Interrupt Acceptance
Figure 6-2 is a flowchart of the interrupt sequence up to the point at which an interrupt is accepted.
1. The interrupt controller receives interrupt request signals from one or more on-chip supporting
modules or external interrupt sources.
Rev. 3.0, 02/99, page 129 of 904
2. The interrupt controller checks the interrupt priorities assigned in IPRA to IPRF and selects the
interrupt with the highest priority level. Interrupts with lower priorities remain pending.
Among interrupts with the same assigned level, the interrupt controller determines priority as
explained in table 6-3.
3. The interrupt controller compares the priority level of the selected interrupt request with the
mask level in SR bits I2 to I0. If the priority level is equal to or less than the mask level, the
interrupt request remains pending. If the priority level is higher than the mask level, the
interrupt controller accepts the interrupt request.
4. After accepting an interrupt, the interrupt controller checks the corresponding bit in DTEA to
DTEF. If this bit is set to 1, the data transfer controller is started. If it is cleared to 0,
interrupt exception handling is started.
Rev. 3.0, 02/99, page 130 of 904

Program
execution state
Interrupt No
requested?
Yes
Address No
error?
No
Trace?
Yes
No
NMI?
Yes Level-7 No
Yes interrupt?
Level-6 No
Yes interrupt?
Level-1 No
Yes interrupt?
Yes
SR mask
level ≤ 6? No
SR mask
Yes
level ≤ 5? No
SR mask
Yes level = 0? No
Yes
Held pending
Data transfer Yes

enabled?
No
Interrupt exception handling Start DTC
Figure 6-2 Flowchart up to Interrupt Acceptance
Rev. 3.0, 02/99, page 131 of 904

6.4.2 Interrupt Exception Handling
Interrupt exception handling is described below. Figure 6-3 shows a flowchart. For DTC
operations, see section 7, "Data Transfer Controller."
1. When the interrupt controller accepts an interrupt, after the H8/500 CPU finishes executing the
current instruction, PC and SR (in minimum mode) or PC, CP, and SR (in maximum mode)
are pushed on the stack, leaving the stack in the condition shown in section 6.4.4, "Stack after
Interrupt Exception Handling."
2. The interrupt controller clears the T bit in SR to 0, and sets the interrupt mask level (I2 to I0)
to the priority level of the interrupt.
3. In minimum mode, the interrupt controller reads a one-word vector address corresponding to
the accepted interrupt from the vector table and copies this word into PC. Execution of the
interrupt handling routine then starts from the PC address. In maximum mode, the interrupt
controller reads a two-word vector address corresponding to the accepted interrupt from the
vector table, copies the lower byte of the first word into CP, and copies the second word into
PC. Execution of the interrupt handling routine then starts from the address indicated by CP
and PC.
Rev. 3.0, 02/99, page 132 of 904

Save PC
Maximum Yes
mode?
No
Save CP
Save SR
Clear T bit
No
Trace?
Yes
Address No
error?
Change mask level

Yes
Vectoring
To interrupt handling routine
Figure 6-3 Interrupt Exception Handling Flowchart
Rev. 3.0, 02/99, page 133 of 904

6.4.3 Interrupt Exception Handling Sequence
Figure 6-4 is a timing diagram of the interrupt sequence in minimum mode, for the case in which
the interrupt handling routine starts at an even address and the program area and stack area are in
the external 16-bit-bus two-state-access address space.
Address bus Vector

(1) (1) (1) SP-2 SP-4 address (3)
NMI, IRQ0,
IRQn (n = 1-3)
Data bus
(2) (2) (2) PC SR Vector (4)
(16 bits)
RD
WR
Priority level Internal Stack access Interrupt Prefetch first Start

decision and proces- vector instruction instruction
wait for end sing of interrupt- execution
of current cycles handling
instruction routine
Interrupt is accepted
(1) Instruction prefetch address (3) Starting address of interrupt-handling routine

(2) Operation code (4) First instruction of interrupt-handling routine
Figure 6-4 Interrupt Sequence in Minimum Mode
Figure 6-5 is a timing diagram of the interrupt sequence in maximum mode, for the case in which
the interrupt handling routine starts at an even address and the program area and stack area are in
the external 16-bit-bus two-state-access address space.
Rev. 3.0, 02/99, page 134 of 904

φ
Address bus Vector Vector

(1) (1) (1) SP-2 SP-4 SP-6 address address (3)
NMI, IRQ0,
IRQn (n = 1-3)
Data bus Vector Vector

(16 bits) (2) (2) (2) PC CP SR CP PC (4)
RD
WR
Priority level Inter- Stack access Interrupt vector Prefetch first Start
decision and nal instruction of instruc-
wait for end cy- interrupt- tion
of current cles handling routine execu-
instruction tion
Interrupt is accepted
(1) Instruction prefetch address (3) Starting address of interrupt-handling routine

(2) Operation code (4) First instruction of interrupt-handling routine
Figure 6-5 Interrupt Sequence in Maximum Mode
6.4.4 Stack after Interrupt Exception Handling
Figure 6-6 shows the stack before and after interrupt exception handling in minimum mode.
Figure 6-7 shows the stack before and after interrupt exception handling in maximum mode. The
PC value saved on the stack is the address of the next instruction to be executed.
SP must always point to an even address. If an odd address is set in SP, an address error will
occur when the stack is accessed.
Rev. 3.0, 02/99, page 135 of 904

Address Address
2m-4 2m-4 SR (upper 8 bits) SP

2m-3 2m-3 SR (lower 8 bits)
2m-2 2m-2 PC (upper 8 bits)
2m-1 2m-1 PC (lower 8 bits)
2m SP 2m
Stack area
Before exception handling After exception handling

Save to stack
Figure 6-6 Stack before and after Interrupt Exception Handling in Minimum Mode
Address Address
2m-6 2m-6 SR (upper 8 bits) SP
2m-5 2m-5 SR (lower 8 bits)
2m-4 2m-4 Don't care
2m-3 2m-3 CP
2m-2 2m-2 PC (upper 8 bits)
2m-1 2m-1 PC (lower 8 bits)
2m SP 2m
Stack area
Before exception handling After exception handling

Save to stack
Figure 6-7 Stack before and after Interrupt Exception Handling in Maximum Mode
Rev. 3.0, 02/99, page 136 of 904

6.5 Interrupts during DTC Operation
If an interrupt is requested during a DTC data transfer cycle, the interrupt controller holds the
interrupt pending until the data transfer cycle has been completed and the next instruction has been
executed. An example is shown below.
Example:
Program flow
ADD.W R2,R0 DTC interrupt request
Data transfer cycle NMI interrupt request
MOV.W R0,@H'FE00 After data transfer cycle, H8/500 CPU

executes next instruction before starting
exception handling
MOV.W @H'FE02,R0 To NMI exception handling
6.6 Interrupt Response Time

The H8/539F can access a memory area in two states via a 16-bit bus. Fastest interrupt service is
obtained by placing the program and stack in this area. Table 6-6 indicates the interrupt response
time in minimum mode. The maximum number of states occurs when the LDM instruction is
executed with all registers specified.
Rev. 3.0, 02/99, page 137 of 904

Table 6-6 Number of States before Interrupt Service in Minimum Mode
Number of States
1 2
Stack Area: 16* Stack Area: 8*
Instruction: Instruction: Instruction: Instruction:
3 4 3 4
Reason for Wait 16* 8* 16* 8*
Interrupt priority decision and 2 2 2 2
comparison with SR mask level
Maximum number of states to 38  38 
completion of current instruction  74 + 16 m  74 + 16 m
Saving of PC and SR 16 16  
  28 + 6 m 28 + 6 m
Total number of states 56 92 + 16 m 68 + 6 m 104 + 22 m
Notes: 1. Stack area in 16-bit-bus two-state-access address space
2. Stack area in 8-bit-bus three-state-access address space
3. Instruction in 16-bit-bus two-state-access address space
4. Instruction in 8-bit-bus three-state-access address space
m: Number of wait states inserted in memory access
Table 6-7 indicates the interrupt response time in maximum mode. The maximum number of
states occurs when the LDM instruction is executed with all registers specified.
Table 6-7 Number of States before Interrupt Service in Maximum Mode
Number of States
1 2
Stack Area: 16* Stack Area: 8*
Instruction: Instruction Instruction Instruction
3 4 3 4
Reason for Wait 16* 8* 16* 8*
Interrupt priority decision and 2 2 2 2
comparison with SR mask level
Maximum number of states to 38 74 + 16 m 38 74 + 16 m
completion of current instruction
Saving of PC, CP, and SR 21 21 41 + 10 m 41 + 10 m
Total number of states 61 97 + 16 m 81 + 10 m 117 + 26 m
Notes: 1. Stack area in 16-bit-bus two-state-access address space
2. Stack area in 8-bit-bus three-state-access address space
3. Instruction in 16-bit-bus two-state-access address space
4. Instruction in 8-bit-bus three-state-access address space
Rev. 3.0, 02/99, page 138 of 904

Section 7 Data Transfer Controller
7.1 Overview
An interrupt-triggered data transfer controller (DTC) is included on-chip. The DTC can transfer
data between memory and I/O, memory and memory, or I/O and I/O without using the CPU. For
example, the DTC can set data in the registers of an on-chip supporting module or send data to an
I/O port or serial communication interface (SCI) independently of program execution. The
H8/500 CPU halts while the DTC is operating.
7.1.1 Features
The features of the DTC are:
• The source address and destination address can be set anywhere in the 64-kbyte address space
of page 0.
• The source address and destination address can be incremented or left unchanged after a data
transfer.
• The DTC can be programmed to transfer one byte or one word of data per interrupt.
• A data transfer count of up to 65,536 bytes or words can be set in the data transfer counter
register (DTCR).
• After a data transfer, if the data transfer count is zero, the interrupt request that started the DTC
is transferred to the H8/500 CPU. The H8/500 CPU then starts normal interrupt exception
handling.
Rev. 3.0, 02/99, page 139 of 904

7.1.2 Block Diagram
Figure 7-1 shows a block diagram of the data transfer controller.
When DTC service is requested, the DTC loads its control registers from memory with
information corresponding to the interrupt source, transfers a byte or word of data, and writes any
altered register information back to memory.
Internal data bus
DTC service request

Memory
Interrupt controller DTC Register

IRQ0 information 0
IRQ1 Register
information 1
DTEA DTMR
DTEB DTSR
DTDR
DTEF DTCR
Legend
DTMR: Data transfer mode register
DTSR: Data transfer source address register
DTDR: Data transfer destination address register
DTCR: Data transfer count register
DTEA to DTEF: Data transfer enable registers A to F
Figure 7-1 Block Diagram of Data Transfer Controller
Rev. 3.0, 02/99, page 140 of 904

Table 7-1 summarizes the DTC control registers.
Table 7-1 DTC Registers
Name Abbreviation R/W

Data transfer mode register DTMR 
Data transfer source address register DTSR 
Data transfer destination address register DTDR 
Data transfer count register DTCR 
These registers cannot be accessed directly. To set information in the DTC control registers,
software should alter the information in memory.
Starting of the DTC is controlled by the interrupt controller's data transfer enable registers.
Table 7-2 summarizes these registers.
Table 7-2 Data Transfer Enable Registers

H'FF08 Data transfer enable register A DTEA R/W H'00
H'FF09 Data transfer enable register B DTEB R/W H'00
H'FF0A Data transfer enable register C DTEC R/W H'00
H'FF0B Data transfer enable register D DTED R/W H'00
H'FF0C Data transfer enable register E DTEE R/W H'00
H'FF0D Data transfer enable register F DTEF R/W H'00
Rev. 3.0, 02/99, page 141 of 904

7.2.1 Data Transfer Mode Register
The data transfer mode register (DTMR) is a 16-bit register that selects the data size and specifies
whether to increment the source and destination addresses. The DTMR bit structure is shown
next.
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Sz SI DI − − − − − − − − − − − − −
R/W − − − − − − − − − − − − − − − −
Reserved bits
Destination increment mode bit

Selects destination address increment mode
Source increment mode bit

Selects source address increment mode
Size bit
Selects byte-size or word-size data transfer
(1) Bit 15–Size (Sz): Selects byte-size or word-size data transfer.
Bit 15
Sz Description
0 Byte transfer
1 Word (two-byte) transfer*
Note: * For word transfer, DTSR and DTDR must indicate even addresses.
(2) Bit 14–Source Increment Mode (SI): Specifies whether to increment the source address.
Bit 14
SI Description
0 Not incremented
1 1. If Sz = 0: incremented by 1 after each data transfer
2. If Sz = 1: incremented by 2 after each data transfer
Rev. 3.0, 02/99, page 142 of 904

(3) Bit 13–Destination Increment Mode (DI): Specifies whether to increment the destination
address.
Bit 13
DI Description
0 Not incremented
1 1. If Sz = 0: incremented by 1 after each data transfer
2. If Sz = 1: incremented by 2 after each data transfer
(4) Bits 12 to 0–Reserved: Reserved bits.
7.2.2 Data Transfer Source Address Register
The data transfer source address register (DTSR) is a 16-bit register that designates the data
transfer source address. The DTSR bit structure is shown next.
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R/W − − − − − − − − − − − − − − − −
For word transfer the source address must be even. In maximum mode, the source address is
implicitly located in page 0.
7.2.3 Data Transfer Destination Address Register
The data transfer destination address register (DTDR) is a 16-bit register that designates the data
transfer destination address. The DTDR bit structure is shown next.
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R/W − − − − − − − − − − − − − − − −
For word transfer the destination address must be even. In maximum mode, the destination
address is implicitly located in page 0.
Rev. 3.0, 02/99, page 143 of 904

7.2.4 Data Transfer Count Register
The data transfer count register (DTCR) is a 16-bit register that designates the number of bytes or
words to be transferred. The initial count can be set from 1 to 65,536. A register value of 0
designates an initial count of 65,536. The DTCR bit structure is shown next.
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R/W − − − − − − − − − − − − − − − −
The data transfer count register is decremented automatically after each byte or word is
transferred. When the count reaches 0, indicating that the designated number of bytes or words
have been transferred, the DTC sends the H8/500 CPU an interrupt request with the same interrupt
source that started the data transfer.
7.2.5 Data Transfer Enable Registers A to F
The six data transfer enable registers (DTEA to DTEF) specify whether an interrupt starts the
DTC. (Certain interrupts, such as NMI, cannot start the DTC.) The bit structure of DTEA to
DTEF is shown next.
Bit 7 6 5 4 3 2 1 0
0 0
The bits in these registers are assigned to interrupts as indicated in table 7-3.
If the bit for a certain interrupt is set to 1, that interrupt is regarded as a request for DTC service.
If the bit is cleared to 0, the interrupt is regarded as an H8/500 CPU interrupt request.
Only the interrupts indicated in table 7-3 can request DTC service in the H8/539F. DTE bits not
assigned to any interrupt (indicated by "−" in table 7-3) must be cleared to 0.
Rev. 3.0, 02/99, page 144 of 904

Table 7-3 Bit Assignments of Data Transfer Enable Registers
On-Chip On-Chip
Supporting Supporting
Register Module Bits 7 to 4 Module Bits 3 to 0
DTEA IRQ0, ADI 7 6 5 4 IRQ1-3 3 2 1 0
− ADI (IRQ0) IRQ0 − IRQ3 IRQ2 IRQ1
DTEB IPU (CH1) IPU (CH1)

− CMI1, 2 IMI2 IMI1 − CMI3,4 IMI4 IMI3
DTEC IPU (CH2) IPU (CH3)

− CMI1, 2 IMI2 IMI1 − CMI1, 2 IMI2 IMI1
DTED IPU (CH4) IPU (CH5)

− CMI1, 2 IMI2 IMI1 − CMI1, 2 IMI2 IMI1
DTEE IPU (CH6) IPU (CH7)

− − IMI2 IMI1 − − IMI2 IMI1
DTEF SCI1 SCI2/SCI3

− TI RI − − TI RI −
7.2.6 Note on Timing of DTE Modifications
The interrupt controller requires two system clock cycles (2φ) to determine the priority level of an
interrupt. When an instruction modifies one of registers DTEA to DTEF, the new setting takes
effect starting from the third state after the instruction has been executed.
Rev. 3.0, 02/99, page 145 of 904

7.3 Operation
DTC operations are described next.
7.3.1 DTC Operations
Data transfer operations when the DTC is activated are described below. Figure 7-2 is a flowchart
of the DTC operations.
Figure 7-2 is a flowchart of the data transfer operations performed by the DTC. For operations
from the occurrence of an interrupt until the DTC is activated, see section 6.4.1, "Operations up to
Interrupt Acceptance."
1. From the DTC vector table, the DTC reads the address at which the register information for the
interrupt is stored in memory and loads the stored information into its control registers.
When the DTC is activated, the interrupt source that activated the DTC is cleared, except for
interrupts from the serial communication interface.
2. The DTC transfers the data and increments the source and destination addresses as required,
then decrements DTCR.
If the DTC was activated by an interrupt from the serial communication interface, the interrupt
source is cleared when the DTC accesses the transmit data register (TDR) or receive data
register (RDR).
3. The DTC writes updated register information back to memory.
4. If the DTCR value is 0, the H8/500 CPU starts interrupt exception handling for the interrupt
that activated the DTC.
Rev. 3.0, 02/99, page 146 of 904

INT Interrupt
No
DTC interrupt? H8/500 CPU
Yes interrupt handling
DTC
starts. See section
Read DTC vector 6.4.2, "Interrupt
Exception Handling."
Read data transfer mode
Read source address
Read data
Source
Yes
address increment
mode?
Increment source address (+1 or +2)
No
Write source address
Read destination address
Write data
Destination Yes
address increment
mode?
Increment destination address
No (+1 or +2)
Write destination address
Read DTCR
DTCR -1 → DTCR
Write DTCR
Yes
DTCR = 0?
No
Program execution state
Figure 7-2 Flowchart of DTC Operations
Rev. 3.0, 02/99, page 147 of 904

7.3.2 DTC Vector Table
Figure 7-3 shows how the DTC vector table works.
For each interrupt that can request DTC service, the DTC vector table provides a pointer to an
address in memory where the DTC control register information for that interrupt is stored.
Register information tables can be placed in any available locations in page 0.
Figure 7-3 shows an example in which the register information is located in RAM. Register
information can also be stored in ROM if there is no need to update the information after each
transfer (if the source and destination addresses are not incremented and the desired data transfer
count is one).
Vector table RAM
DTMR0
TA0
Register DTSR0
Exception information 0 DTDR0
vector table
DTCR0
TA1 DTMR1
TA0*
Register DTSR1
information 1 DTDR1
TA1*
DTCR1
DTC vector
table
Note: * TA0, TA1, ...: Addresses of DTC register information tables in memory.
Figure 7-3 DTC Vector Table
The DTC vector table structure differs between minimum and maximum modes. In maximum
mode there is no page specification: page 0 is assumed implicitly.
Figure 7-4 shows a DTC vector table entry in minimum and maximum mode.
Rev. 3.0, 02/99, page 148 of 904

Vector table Memory Vector table
Address Address
m Address (high) Register information Don't care* 2m
m+1 Address (low) Don't care* 2m+1
Address (high) 2m+2
Address (low) 2m+3
(1) Minimum mode (2) Maximum mode
Note: * Addresses 2m and 2 m + 1 are not accessed when the vector is read.
Figure 7-4 DTC Vector Table Entry
Table 7-4 lists the address of the entry in the DTC vector table for each interrupt source.
Rev. 3.0, 02/99, page 149 of 904

Table 7-4 Addresses of DTC Vectors
Address of Vector Table Entry

Interrupt Source Minimum Mode Maximum Mode
IRQ0 H'00C0-00C1 H'0180-0183
Interval timer H'00C2-00C3 H'0184-0187
AD converter ADI H'00C4-00C5 H'0188-018B
IRQ1 H'00C8-00C9 H'0190-0193
IRQ2 H'00CA-00CB H'0194-0197
IRQ3 H'00CC-00CD H'0198-019B
IPU channel 1 IMI1 H'00D0-00D1 H'01A0-01A3
IMI2 H'00D2-00D3 H'01A4-01A7
CMI1/CMI2 H'00D4-00D5 H'01A8-01AB
  
IMI3 H'00D8-00D9 H'01B0-01B3
IMI4 H'00DA-00DB H'01B4-01B7
CMI3/CMI4 H'00DC-00DD H'01B8-01BB
IPU channel 2 IMI1 H'00E0-00E1 H'01C0-01C3
IMI2 H'00E2-00E3 H'01C4-01C7
CMI1/CMI2 H'00E4-00E5 H'01C8-01CB
  
IPU channel 3 IMI1 H'00E8-00E9 H'01D0-01D3
IMI2 H'00EA-00EB H'01D4-01D7
CMI1/CMI2 H'00EC-00ED H'01D8-01DB
  
IPU channel 4 IMI1 H'00F0-00F1 H'01E0-01E3
IMI2 H'00F2-00F3 H'01E4-01E7
CMI1/CMI2 H'00F4-00F5 H'01E8-01EB
  
IPU channel 5 IMI1 H'00F8-00F9 H'01F0-01F3
IMI2 H'00FA-00FB H'01F4-01F7
CMI1/CMI2 H'00FC-00FD H'01F8-01FB
  
IPU channel 6 IMI1 H'00A0-00A1 H'0140-0143
IMI2 H'00A2-00A3 H'0144-0147
  
IPU channel 7 IMI1 H'00A8-00A9 H'0150-0153
IMI2 H'00AA-00AB H'0154-0157
  
Rev. 3.0, 02/99, page 150 of 904

Table 7-4 Addresses of DTC Vectors (H8/539) (cont)
Address of Vector Table Entry

Interrupt Source Minimum Mode Maximum Mode
SCI1   
RI1 H'00B2-00B3 H'0164-0167
TI1 H'00B4-00B5 H'0168-016B
  
SCI2/SCI3   
RI2/RI3 H'00BA-00BB H'0174-0177
TI2/TI3 H'00BC-00BD H'0178-017B
  
7.3.3 Location of Register Information in Memory
For each interrupt, the DTC control register information is stored in memory in the order shown in
figure 7-5.
Vector table Memory
DTMR
TA + 2 DTSR
TA TA + 4 DTDR
TA + 6 DTCR
8 bits 8 bits
Figure 7-5 Order of Register Information in Memory
Rev. 3.0, 02/99, page 151 of 904

7.3.4 Number of States per Data Transfer
Table 7-5 lists the number of states required per data transfer, assuming that the DTC control
register information is stored in the 16-bit-bus two-state-access address space.
Table 7-5 Number of States per Data Transfer
16-Bit-Bus On-Chip 8-Bit-Bus On-Chip

2-State-Access Supporting 3-State-Access Supporting
Increment Mode Address Space ↔ Module Address Space ↔ Module
Source Destination
(SI) (DI) Byte Transfer Word Transfer Byte Transfer Word Transfer
0 0 31 34 32 38
0 1 33 36 34 40
1 0 33 36 34 40
1 1 35 38 36 42
Note: Numbers in the table are the number of states.
The values in table 7-5 are calculated from the formula:
N = 26 + 2 × SI + 2 × DI + MS + MD
Where MS and MD have the following meanings:
MS: Number of states for reading source data
MD: Number of states for writing data to destination
The values of MS and MD depend on the data location as follows:
1. Byte or word data in 16-bit-bus two-state-access address space: 2 states

2. Byte data in eight-bit-bus three-state-access address space or on-chip supporting module: 3
states
3. Word data in eight-bit-bus three-state-access address space or on-chip supporting module: 6
states
If the DTC control register information is stored in the eight-bit-bus three-state-access address
space, 20 + 4 × SI + 4 × DI must be added to the values in table 7-5.
Table 7-6 indicates the number of additional states between the occurrence of an interrupt request
and the starting of the DTC (states during which the interrupt controller checks priority and waits
for execution of the current instruction to end). At maximum, this number of states is the sum of
the values indicated for items No. 1 and 2 in table 7-4.
Rev. 3.0, 02/99, page 152 of 904

If the data transfer count is 0 at the end of a data transfer cycle, the number of states from the end
of the data transfer cycle until the first instruction of the interrupt-handling routine is executed is
the value given for item No. 3 in table 7-4. The maximum number of states in table 7-6 occurs
when the LDM instruction is executed with all registers specified.
Table 7-6 Number of States before Interrupt Service
Number of States
No. Reason for Wait Minimum Mode Maximum Mode
1 Interrupt priority decision and comparison 2
with mask level in SR
2 Number of states to Instruction is in 16-bit-bus (LDM instruction specifying all
completion of current two-state-access address registers)
instruction space 38
Instruction is in 8-bit-bus (LDM instruction specifying all
three-state-access address registers)
space 74 + 16 m
3 Number of statues Instruction is in 16-bit-bus 16 21
from saving of PC two-state-access address
and SR or PC, CP, space
and SR until
Instruction is in 8-bit-bus 28 + 6 m 41 + 10 m
prefetching of first
three-state-access address
instruction of
space
interrupt-handling
routine
Notation
Rev. 3.0, 02/99, page 153 of 904

7.4 Procedure for Using DTC
The procedure for using the DTC is explained next. Figure 7-6 shows the flowchart.
Procedure for Using the DTC
1. DTC register setup: Set the appropriate DTMR, DTSR, DTDR, and DTCR register
information in the memory location indicated in the DTC vector table.
2. DTEn, IPRn (n = A to F), and SR setup: Set the data transfer enable bit of the pertinent
interrupt to 1, and set the priority of the interrupt source (in the interrupt priority register) and
the interrupt mask level (in the CPU status register) so that the interrupt can be accepted.
3. Interrupt enabling: Set the interrupt enable bit for the interrupt source in the control register of
the on-chip supporting module (or IRQ control register).
Following these preparations, the DTC will be started each time the interrupt occurs.
DTC
#DTMR→ @DT_REG
#DTSR→ @DT_REG + 2
Set DTC register values
#DTDR→ @DT_REG + 4
#DTCR→ @DT_REG + 6
<1> → DTE bit (DTEn)
<Interrupt level> → IPRn Set DTEn, IPRn, and SR (n = A to F)
<Interrupt mask level> → SR
Enable interrupt request Enable interrupt request
DTC is enabled
Figure 7-6 Procedure for Using DTC
Rev. 3.0, 02/99, page 154 of 904

7.5 Example
(1) Purpose: To receive 128 bytes of serial data via serial communication interface.
(2) Conditions:
• Operating mode: minimum mode.

• Receive data is to be stored in consecutive addresses starting at H'FC00.
• The DTC vector table contains H'F6 at address H'00B2 and H'80 at address H'00B3.
• The desired interrupt mask level in the CPU status register is 4, and the desired SCI interrupt
priority level is 5.
Table 7-7 shows the DTC control register information to be set in RAM.
Table 7-7 DTC Control Register Information Set in RAM
Register Setting Value

DTMR Byte transfer H'2000
Source address fixed
Destination address incremented
DTSR Address of SCI1 receive data register H'FECD
DTDR Address H'FC00 H'FC00
DTCR Transfer count (128) H'0080
(3) Operation
(a) Software sets DTMR, DTSR, DTDR, and DTCR information in RAM addresses H'F680 to
H'F687 as shown in table 7-7.
(b) Software sets the RI (SCI1 Receive Interrupt) bit in data transfer enable register F (DTEF) to
1.
(c) Software sets the interrupt mask level in SR bits I2 to I0 to 4, and the SCI1 interrupt priority
level in the upper four bits of interrupt priority register F (IPRF) to 0101 (5).
(d) Software sets SCI1 to the appropriate receive mode, and sets the receive interrupt enable bit
(RIE) in the serial control register (SCR) to 1 to enable receive interrupts.
(e) Thereafter, each time SCI1 receives one byte of data, the DTC is activated and transfers the
byte of receive data into RAM. The DTC automatically clears the SCI1 receive interrupt
request.
(f) When 128 bytes have been transferred (DTCR = 0), SCI1 receive interrupt exception handling
begins.
(g) The interrupt-handling routine executes a receive wrap-up routine.
Rev. 3.0, 02/99, page 155 of 904

Figure 7-7 is a flowchart for this example.
DTC setup
#DTMR → @F680
#DTSR → @F682
(a) Write DTC control register information on RAM
#DTDR → @F684
#DTCR → @F686
<1> → RI bit (DTEF) (b) Set RI bit in DTEF to 1
<100> → I2 to I0 (SR)
(c) Set interrupt mask level (SR) and interrupt
<101> → IPRF (bits 6 to 4) priority level (IPRF)
Set up SCI1 and enable (d) Set SCI1 to receive mode and enable interrupt
interrupt requests
End of setup
Start DTC
@ DTSR → @DTDR+ (e) Transfer receive data to RAM
Clear interrupt request (f) Test for end of data: start interrupt handling if
DTCR = 0
DTCR - 1 → DTCR (e) (g) Interrupt handling: receive-data wrap-up routine
No
DTCR = 0? <Interrupt handling routine>
(f) Yes SCI1 receive wrap-up (g)
routine
Figure 7-7 Flowchart for DTC Example
Rev. 3.0, 02/99, page 156 of 904

Figure 7-8 shows an example of the use of the DTC for continuous SCI reception.
DTC vector table RAM

Address
Address H'F680 H'20 Data transfer
H'F681 H'00 mode
H'00B2 H'F6
H'FE
H'00B3 H'80 Source address
H'CD
H'FC Destination
H'00 address
H'00
Transfer count
H'F687 H'80
H'FC00 Receive data 1

Receive data 2
Transferred
by DTC
H'FC7F Receive data 128
RDR
SCI
Figure 7-8 Example of Use of DTC to Receive Continuous Serial Data
Rev. 3.0, 02/99, page 157 of 904

Section 8 Wait-State Controller
8.1 Overview
For interfacing to low-speed external devices, an on-chip wait-state controller (WSC) can insert
wait states (TW) into bus cycles. The wait function can be used in CPU and DTC access cycles to
the external three-state-access address space. It is not used in access to the two-state-access
address space or the on-chip register area (H'FE80 to H'FFFF).
Wait states are inserted between the T2 state and T3 state in the bus cycle. The number of wait
states can be selected by a value set in the wait control register (WCR), or by holding the :$,7
pin low for the required interval.
8.1.1 Features
The features of the wait-state controller are:
• Selection of three operating modes

Programmable wait mode, pin wait mode, or pin auto-wait mode
• Selection of number of wait states
0, 1, 2, or 3 wait states can be inserted, and 4 or more wait states can be inserted in pin wait
mode by holding the :$,7 pin low.
Rev. 3.0, 02/99, page 159 of 904

8.1.2 Block Diagram
Figure 8-1 shows a block diagram of the wait-state controller.
Internal data bus
WCR
− − − − WMS1 WMS0 WC1 WC0
Wait counter
Wait request Control logic WAIT input
Legend
WCR: Wait control register
WMS1/0: Wait mode select bits 1 and 0
WC1/0: Wait count bits 1 and 0
Figure 8-1 Block Diagram of Wait State Controller
Table 8-1 summarizes the wait control register.
Table 8-1 Wait Control Register

H'FF14 Wait control register WCR R/W H'F3
Rev. 3.0, 02/99, page 160 of 904

8.2 Wait Control Register
The wait control register (WCR) is an eight-bit register that specifies the wait mode and the
number of wait states to be inserted. The WCR bit structure is shown next.
Bit 7 6 5 4 3 2 1 0
− − − − WMS1 WMS0 WC1 WC0
R/W − − − − R/W R/W R/W R/W
Wait count 1 and 0

These bits indicate
the number of wait
states to be inserted
Wait mode select 1 and 0

These bits select the wait mode
Reserved bits
WCR is initialized to H'F3 by a reset and in hardware standby mode. WCR is not initialized in
software standby mode.
Bits 7 to 4–Reserved: Read-only bits, always read as 1.
Bits 3 and 2–Wait Mode Select 1 and 0 (WMS1 and WMS0): These bits select the wait mode.
Bit 3 Bit 2
WMS1 WMS0 Description
0 0 Programmable wait mode (Initial value)
0 1 No wait states (TW) inserted, regardless of wait count
1 0 Pin wait mode
1 1 Pin auto-wait mode
Rev. 3.0, 02/99, page 161 of 904

Bits 1 and 0–Wait Count 1 and 0 (WC1 and WC0): These bits specify the number of wait states
to be inserted. Wait states (TW) are inserted only in bus cycles in which the CPU or DTC accesses
the external three-state-access address space.
Bit 1 Bit 0
WC1 WC0 Description
0 0 No programmable wait states (TW) inserted
0 1 1 wait state inserted
1 0 2 wait states inserted
1 1 3 wait states inserted (Initial value)
8.3 Operation
Table 8-2 summarizes the operation of the three wait modes.
Table 8-2 Wait Modes
Description
Number of Wait
Mode WAIT Pin Function Insertion Conditions States Inserted
Programmable Disabled Inserted in access to 1 to 3 states are inserted
wait mode external three-state- as specified by bits WC0
WMS1 = 0 access address space and WC1
WMS0 = 0
Pin wait mode Enabled Inserted in access to • 0 to 3 states are
WMS1 = 1 external three-state- inserted as specified
WMS0 = 0 access address space
by bits WC0 and WC1
• Additional states can
be inserted by driving
the :$,7 signal low
Pin auto-wait Enable Inserted in access to 1 to 3 states are inserted

mode external three-state- as specified by bits WC0
WMS1 = 1 access address space and WC1
WMS0 = 1 if :$,7 is low
Rev. 3.0, 02/99, page 162 of 904

8.3.1 Programmable Wait Mode
Programmable wait mode is selected when WMS1 = 0 and WMS0 = 0.
Whenever the CPU or DTC accesses the external three-state-access address space, the number of
wait states selected by bits WC1 and WC0 are inserted. The PA4/#:$,7 pin is not used for wait
control; it is available for general-purpose input or output.
Figure 8-2 shows the timing of operation in this mode when the wait count is 1 (WC1 = 0, WC0 =
1).
One wait state inserted

by wait count
T1 T2 T1 T2 TW T3 T1
A19-A 0 External three-state-access address space
AS
RD
(read access)
Read data Read data
D15-D 0
(read access)
HWR, LWR
(write access)
D15-D 0
Write data
(write access)
3-state access + 1 wait state
Figure 8-2 Programmable Wait Mode

(Example of External 16-Bit-Bus, Three-State-Access Address Space)
Rev. 3.0, 02/99, page 163 of 904

8.3.2 Pin Wait Mode
Pin wait mode is selected when WMS1 = 0 and WMS0 = 1. In this mode the :$,7 function of
the PA4/#:$,7 pin is used automatically.
The number of wait states indicated by wait count bits WC1 and WC0 are inserted into any bus
cycle in which the CPU or DTC accesses the external three-state-access address space. In
addition, wait states are inserted if the :$,7 signal is driven low, even if the wait count is 0.
Wait states continue to be inserted until the :$,7 signal goes high.
This mode is useful for inserting four or more wait states, or when different external devices
require different numbers of wait states.
1) and the :$,7 signal is held low to insert one additional wait state.
Rev. 3.0, 02/99, page 164 of 904

One wait state inserted Pin-requested wait (one state)
by wait count
T1 T2 T1 T2 TW TW T3
φ * *
WAIT
AS
RD
(read access)
Read data Read data
D15-D 0
(read access)
HWR, LWR
(write access)
D15-D 0 Write data

(write access)
3-state access + 1 wait state +

pin-requested wait (1 state)
Note: * Arrows indicate times at which the WAIT pin is sampled.
Figure 8-3 Pin Wait Mode

Rev. 3.0, 02/99, page 165 of 904

8.3.3 Pin Auto-Wait Mode
Pin auto-wait mode is selected when WMS1 = 1 and WMS0 = 1. In this mode the :$,7 function
of the PA4/#:$,7 pin is used automatically. When the CPU or DTC accesses the external three-
state-access address space, if the :$,7 pin is low the number of wait states indicated by bits
WC1 and WC0 are inserted.
This mode offers a simple way to interface a low-speed device: wait states can be inserted by
routing the address strobe signal ($6) and a decoded address signal to the :$,7 pin.
1).
In pin auto-wait mode the :$,7 pin is sampled only once, on the falling edge of the system clock
(φ) in the T2 state. If the :$,7 signal is low at this time, the wait-state controller inserts the
number of wait states indicated by bits WC1 and WC0. The :$,7 pin is not sampled during the
TW and T3 states, so no additional wait states are inserted even if the :$,7 signal continues to be
held low.
Rev. 3.0, 02/99, page 166 of 904

Pin auto-wait (one wait state)
inserted by wait count
T1 T2 T3 T1 T2 TW T3
* *
φ
WAIT
AS
RD
(read access)
Read data Read data
D15-D 0
(read access)
HWR, LWR
(write access)
D15-D 0
Write data
(write access)
3-state access + pin auto-wait

(1 state)
Note: * Arrows indicate times at which the WAIT pin is sampled.
Figure 8-4 Pin Auto-Wait Mode

Rev. 3.0, 02/99, page 167 of 904

Section 9 Clock Pulse Generator
9.1 Overview
This LSI has an on-chip clock pulse generator (CPG). The clock pulse generator consists of an
oscillator, system clock frequency divider, and frequency dividers (prescalers) for the clock
signals of the on-chip supporting modules.
The H8/539F has an on-chip 1:1 clock pulse generator.
The 1:1 clock pulse generator does not include a frequency divider, but includes a circuit for
adjusting the duty of the input clock.
9.1.1 Block Diagram
Figure 9-1 shows the configuration of the 1:1 clock pulse generator.
CPG
XTAL Duty
Oscillator adjustment Prescalers
EXTAL circuit
φ φ /2-φ /4096
Figure 9-1 Block Diagram of 1:1 Clock Pulse Generator
Rev. 3.0, 02/99, page 169 of 904

9.2 Oscillator Circuit
Clock pulses can be generated by connecting a crystal resonator to the clock oscillator circuit, or
by supplying an external clock signal. These two methods are described next.
9.2.1 Connecting a Crystal Resonator
(1) Circuit Configuration: A crystal resonator can be connected as in the example in figure 9-2.
An AT-cut parallel resonating crystal should be used. For the 1:1 clock pulse generator, insert a
damping resistor as listed in table 9-1.
CL
EXTAL
Rd
XTAL
* CL = 10-22 pF CL
Note: * Insert a damping resistor for the H8/539F.
Figure 9-2 Example of Crystal Resonator Connection
Table 9-1 Damping Resistance (Examples)
Frequency (MHz) 2 4 8 10 12 16
Rd max (Ω) 1k 500 200 0 0 0
(2) Crystal Resonator: Figure 9-3 shows an equivalent circuit of the crystal resonator. The
crystal resonator should have the characteristics listed in table 9-2. Use a crystal resonator with a
frequency equal to the system clock frequency (φ).
Rev. 3.0, 02/99, page 170 of 904

CL
L Rs
XTAL EXTAL
C0
AT-cut parallel resonator
Figure 9-3 Crystal Resonator Equivalent Circuit
Table 9-2 Crystal Resonator Parameters
Frequency (MHz) 2 4 8 10 12 16
Rs max (Ω) 500 120 80 70 60 50
C0 max (pF) 7
(3) Notes on Board Design: When a crystal resonator is connected, the following points should
be noted:
• Other signal lines should be routed away from the oscillator circuit to prevent induction from
interfering with correct oscillation. See figure 9-4.
• When the board is designed, the crystal resonator and its load capacitors should be placed as
close as possible to the XTAL and EXTAL pins.
Signal Signal
Not allowed
line A line B
H8/539F
CL
XTAL
EXTAL
CL
Figure 9-4 Example of Incorrect Board Design
Rev. 3.0, 02/99, page 171 of 904

9.2.2 External Clock Input
(1) Circuit Configuration: An external clock signal can be input at the EXTAL pin as shown in
the example in figure 9-5. A reverse-phase clock should be input at the XTAL pin.
When the circuit configuration in figure 9-5 is used, the external clock should be held high in
standby mode.
EXTAL
External clock input
XTAL
74HC04 or equivalent
Figure 9-5 Example of External Clock Input
Note: The H8/539F can be driven with the XTAL pin left open if the stray capacitance at the
XTAL pin does not exceed 10 pF and the clock input can be held high in standby mode.
(2) External Clock
Table 9-3 and figure 9-6 indicate the required clock timing.
The external clock output settling delay time is shown in table 22-5 in section 22.2.2, "AC
Characteristics" and in table 23-5 in section 23.2.2 "AC Characteristics". The external clock
output settling delay timing is shown in figure 22-2 in section 22.3.3, "Clock Timing", and in table
23-11 in section 23.3.3, "Clock Timing".
When the specified clock is input at the EXTAL pin, internal clock signal output settles after the
elapse of the external clock output settling delay time (tDEXT). As the clock signal output remains
unsettled during the tDEXT period, the reset signal should be driven low to retain the reset state.
Rev. 3.0, 02/99, page 172 of 904

Table 9-3 Clock Timing
VCC = 5.0 V ±10%

Item Symbol Min Max Unit Test Conditions
External tEXr  5 ns Figure 9-6
clock rise
time
External tEXf  5 ns
clock fall
time
External  30 70 % φ ≥ 5 MHz Figure 9-6
clock input
40 60 % φ < 5 MHz
duty (a/tcyc)
Clock duty  40 60 % Figure 9-7
cycle
(b/tcyc)
tcyc
EXTAL
VCC × 0.5
tEXr tEXf
Figure 9-6 External Clock Input Timing
tcyc
φ
VCC × 0.5
Figure 9-7 φ Clock Output Timing
Rev. 3.0, 02/99, page 173 of 904

9.3 Duty Adjustment Circuit
When the external clock frequency is 5 MHz or higher, the duty adjustment circuit adjusts the duty
cycle to create the system clock (φ).
Rev. 3.0, 02/99, page 174 of 904

Section 10 I/O Ports
10.1 Overview
The H8/539F has twelve I/O ports. Ports 1, 2, 4, 5, 7, B, and C are eight-bit input/output ports.
Port 3 is a six-bit input/output port. Port 6 is a five-bit input/output port. Port A is a seven-bit
input/output port. Port 8 is a four-bit input port. Port 9 is an eight-bit input port.
These ports are multiplexed with inputs and outputs of the on-chip supporting modules. The
functions of ports 1, 2, A, B, and C also differ depending on the operating mode.
Each port has a data direction register (DDR) for selecting input or output, and a data register
(DR) for holding output data. In addition to DR and DDR, port A has a bus release control
register (BRCR), and ports B and C have MOS input pull-up transistor control registers (PBPCR
and PCPCR).
Ports 1, 2, A, B, and C can drive one TTL load and a 90-pF capacitive load. Ports 3 to 7 can drive
one TTL load and a 30-pF capacitive load. Ports 3 and 5 can drive LEDs (with 10-mA current
sink). Ports 4 and 5 have Schmitt-trigger input circuits.
PWM output pin functions have been added to ports 6 and 7 of the H8/539F, and both serial
communication input/output and PWM output pin functions have been added to port A.
Table 10-1 summarizes ports 1 to C of the H8/539F, giving the pin names and functions in each
mode.
Rev. 3.0, 02/99, page 175 of 904

Table 10-1 Ports 1 to C, Pin Names, and Functions in Each Mode
Expanded Minimum Expanded Maximum

Mode 7
Modes Modes (Single-Chip
Port Description Pins 1 and 6 Mode 2 3 and 5 Mode 4 Mode)
Port 1 8-bit input/ P17-P10/ Data bus General-
output port D15-D8 (D15 to D8) purpose
input/output
Port 2 8-bit input/ P27-P20/ Data bus General- Data bus Data bus General-
output port D7-D0 (D7 to D0) purpose (D7 to D0) (D7 to D0) purpose
input/ input/output
output
Port 3 6-bit input/ P35-P30/ Output (T2OC2, T2OC1, T1OC4 to T1OC1) from 16-bit integrated-
output port T2OC2, T2OC1, timer pulse unit (IPU), and general-purpose input/output
T1OC4-T1OC1
Port 4 8-bit input/ P47/T7IOC2, Input and output (T7IOC2,T7IOC1, T6IOC2, T6IOC1, T5IOC2, T5IOC1,
output port P46/T7IOC1, T4IOC2, T4IOC1) for 16-bit integrated-timer pulse unit (IPU), and
P45/T6IOC2, general-purposeinput/output
P44/T6IOC1,
P43/T5IOC2,
P42/T5IOC1,
P41/T4IOC2,
P40/T4IOC1
Port 5 8-bit input/ P57-P50/ Input and output (T3IOC2, T3IOC1, T2IOC2, T2IOC1, T1IOC4 to
output port T3IOC2, T3IOC1, T1IOC1) for 16-bit integrated-timer pulse unit (IPU), and general-
T2IOC2, T2IOC1, purpose input/output
T1IOC4-T1IOC1
Port 6 5-bit input/ P64/TCLK3, Clock input (TCLK3 to TCLK1) for 16-bit integrated-timer pulse unit
output port P63/TCLK2, (IPU), external interrupt input (,543,#,542), PWM timer output (PW3),
P62/TCLK1, and general-purpose input/output
P61/,543,
P60/,542/PW3
Port 7 8-bit input/ P77/SCK2/PW2, Input and output (SCK2, SCK1, TXD2, TXD1, RXD2, RXD1) for serial
output port P76/SCK1/PW1, communication interfaces 1 and 2 (SCI1/2), external interrupt input
P75/RXD2, (,541,#,540), A/D converter trigger input ($'75*), PWM timer
P74/TXD2, output (PW2, PW1), and general-purpose input/output
P73/RXD1,
P72/TXD1,
P71/,541/
$'75*,
P70/,540
Port 8 4-bit input P83-P80/ Analog input for A/D converter (AN11 to AN8) and general-purpose
port AN11-AN8 input
Port 9 8-bit input P97-P90/ Analog input for A/D converter (AN7 to AN0) and general-purpose
port AN7-AN0 input
Rev. 3.0, 02/99, page 176 of 904

Table 10-1 Ports 1 to C, Pin Names, and Functions in Each Mode (cont)
Expanded Minimum Expanded Maximum

Mode 7
Modes Modes (Single-Chip
Port Description Pins 1 and 6 Mode 2 3 and 5 Mode 4 Mode)
Port A 7-bit input/ PA6/T3OC2/ Output from 16-bit integrated-timer pulse unit (IPU), 16-bit
output port %$&./TXD3, input and output (TXD3, RXD3) for serial integrated-
PA5/T3OC1/ communication interface 3 (SCI3), general-purpose timer pulse
%5(4/RXD3, input/output, and %$&., %5(4, and :$,7 input and unit (IPU)
PA4/:$,7 output if enabled by settings in bus release control output, serial
register (BRCR), wait control register (WCR), and port communica-
A control register (PACR) tion interface
3 (SCI3) input
and output
(TXD3, RXD3),
and general-
purpose
input/output
(PA4: general-
purpose
input/output
only)
PA3/A19/ Output (T5OC2, T5OC1, Page Page Page address
T5OC2/SCK3, T4OC2, T4OC1) from 16-bit address address output
PA2/A18/ integrated- output output (A19 to A16),
T5OC1/PW3, timer pulse unit (IPU), (A19 to A16) (A19 to A16), serial com-
PA1/A17/ and general-purpose serial communication
T4OC2/PW2, input/output munication interface 3
PA0/A16/ interface 3 (SCI3)
T4OC1/PW1 (SCI3) input/output
input/output (SCK3),
(SCK3), output (PW1
output (PW1 to PW3) from
to PW3) PWM timers
from PWM (PW1 to PW3),
timers (PW1 and general-
to PW3), purposeinput/
and general- output
purpose
input/output
Port B 8-bit input/ PB7-PB0/ Address Address Address Address General-
output port A15-A8 output output output output purpose
(A15 to A0) (A15 to A0) (A15 to A0) (A15 to A0) input/output
Port C 8-bit input/ PC7-PC0/
when DDR = when DDR =
output port A7-A0
1, general- 1, general-
purpose purpose
input when input when
DDR = 0 DDR = 0
Rev. 3.0, 02/99, page 177 of 904

10.2 Port 1
10.2.1 Overview
Port 1 is an eight-bit general-purpose input/output port in mode 7. In modes 1 to 6, port 1 is a data

bus (D15 to D8).
Pins in port 1 can drive one TTL load and a 90-pF capacitive load. They can also drive a
Darlington transistor pair.
Figure 10-1 summarizes the pin functions. Figure 10-2 shows examples of output loads for port 1.
P17/D15
P16/D14
P15/D13
P14/D12
Port 1
P13/D11
P12/D10
P11/D9
P10/D8
Figure 10-1 Port 1 Pin Functions
HD7404 etc.
Darlington pair
2 kΩ
H8/539F H8/539F
Port 1 HD74LS04 etc. Port 1
(1) One TTL load or four LS-TTL loads (2) Darlington transistor pair
Figure 10-2 Examples of Port 1 Output Loads
Rev. 3.0, 02/99, page 178 of 904

10.2.2 Register Descriptions
Table 10-2 summarizes the registers of port 1.
Table 10-2 Port 1 Registers

H'FE80 Port 1 data direction register P1DDR W H'00
H'FE82 Port 1 data register P1DR R/W H'00
(1) Port 1 Data Direction Register: The port 1 data direction register (P1DDR) is an eight-bit
register. Each bit selects input or output for one pin in port 1. These input/output designations are
valid only in mode 7.
Bit 7 6 5 4 3 2 1 0
P17DDR P16DDR P15DDR P14DDR P13DDR P12DDR P11DDR P10DDR
R/W W W W W W W W W
A pin in port 1 becomes an output pin if the corresponding P1DDR bit is set to 1, and an input pin
if this bit is cleared to 0. P1DDR is a write-only register. All bits always return the value 1 when
read.
P1DDR is initialized to H'00 by a reset and in hardware standby mode. P1DDR is not initialized
in software standby mode.
(2) Port 1 Data Register: The port 1 data register (P1DR) is an eight-bit register that stores data
for pins P10 to P17. P1DR is used only in mode 7. In modes 1 to 6, the bit values in P1DR cannot
be modified and always read 1.
Bit 7 6 5 4 3 2 1 0
P17 P16 P15 P14 P13 P12 P11 P10
When a bit in P1DDR is set to 1, the corresponding P1DR bit value is output at the corresponding
pin. If port 1 is read the value in P1DR is returned, regardless of the actual state of the pin.
Rev. 3.0, 02/99, page 179 of 904

When a bit in P1DDR is cleared to 0, it is possible to write to the corresponding P1DR bit but the
value is not output at the pin. If P1DR is read the value at the pin is returned, regardless of the
value written in P1DR.
P1DR is initialized to H'00 by a reset and in hardware standby mode. P1DR is not initialized in
10.2.3 Pin Functions in Each Mode
The functions of port 1 differ between the externally expanded modes (modes 1 to 6) and single-
chip mode (mode 7). The pin functions in each mode are described below.
(1) Pin Functions in Externally Expanded Modes (Modes 1 to 6): The settings in P1DDR are
ignored. Port 1 automatically becomes a bidirectional data bus. Figure 10-3 shows the pin
functions in modes 1 to 6.
Pin Functions
D15 (bidirectional data bus)
Port 1
Figure 10-3 Pin Functions in Modes 1 to 6
Rev. 3.0, 02/99, page 180 of 904

(2) Pin Functions in Single-Chip Mode (Mode 7): Port 1 consists of general-purpose
input/output pins. Input or output can be selected separately for each pin. A pin becomes an
output pin if the corresponding P1DDR bit is set to 1 and an input pin if this bit is cleared to 0.
Figure 10-4 shows the pin functions in mode 7.
Pin Functions
P17 (input/output pin)
Port 1
Figure 10-4 Pin Functions in Mode 7
(3) Software Standby Mode: Transition to software standby does not change the pin functions in
single-chip mode. In the externally expanded modes, port 1 is in the high-impedance state during
software standby.
10.2.4 Port 1 Read/Write Operations
P1DR and P1DDR have different read/write functions depending on whether port 1 is used as a
data bus (D15 to D8) or for general-purpose input or output (P17 to P10). The operating states and
functions of port 1 are described next.
(1) Data Bus (Modes 1 to 6): Figure 10-5 shows a block diagram illustrating the data-bus
function. Table 10-3 indicates register read/write data. When port 1 operates as a data bus, the
values in the port 1 data register (P1DR) have no effect on the bus lines. When read, P1DR
returns all 1s.
Rev. 3.0, 02/99, page 181 of 904

Data bus
Internal data bus

D15-D 8
VCC
Read
Write
P1DR
Figure 10-5 Data Bus: D15 to D8 (Modes 1 to 6)
Table 10-3 Register Read/Write Data
Read Write
P1DR Always 1 Don't care*
Note: The register can be written to, but the value is not output at the pines.
(2) Input Port (Mode 7): Figure 10-6 shows a block diagram illustrating the general-purpose
input function. Table 10-4 indicates register read/write data. When port 1 operates as an input
pin, values written in the port 1 data register (P1DR) have no effect on general-purpose input
lines. When read, P1DR returns the value at the pin.
Internal data bus
Read
P17-P1 0
Write
P1DR
Figure 10-6 Input Port (Mode 7)
Read Write
P1DR Pin value Don't care*
Rev. 3.0, 02/99, page 182 of 904

(3) Output Port (Mode 7): Figure 10-7 shows a block diagram illustrating the general-purpose
output function. Table 10-5 indicates register read/write data. The value written in the port 1 data
register (P1DR) is output at the pin. When read, P1DR returns the value written in P1DR.
Internal data bus

P17-P1 0
Read/
Write
P1DR
Figure 10-7 Output Port (Mode 7)
Read Write
P1DR P1DR value Value output at pin
Rev. 3.0, 02/99, page 183 of 904

10.3 Port 2
10.3.1 Overview
Port 2 is an eight-bit general-purpose input/output port in modes 2 and 7. In modes 1, 3, 4, 5, and

6, port 2 is a data bus (D7 to D0).
Figure 10-8 summarizes the pin functions. Figure 10-9 shows examples of output loads for port 2.
P27/D7
P26/D6
P25/D5
P24/D4
Port 2
P23/D3
P22/D2
P21/D1
P20/D0
HD7404 etc. Darlington pair
2 kΩ
H8/539F H8/539F
Rev. 3.0, 02/99, page 184 of 904


register. Each bit selects input or output for one pin in port 2. These input/output designations are
valid only in modes 2 and 7.
Bit 7 6 5 4 3 2 1 0
R/W W W W W W W W W
read.
Rev. 3.0, 02/99, page 185 of 904

for pins P27 to P20. P2DR is used only in modes 2 and 7. In modes 1, 3, 4, 5, and 6, the bit values
in P2DR cannot be modified and always read 1.
Bit 7 6 5 4 3 2 1 0
P27 P26 P25 P24 P23 P22 P21 P20
The functions of port 2 differ between modes 1, 3, 4, 5, and 6 on the one hand, and modes 2 and 7
on the other hand. The pin functions in each mode group are described below.
(1) Pin Functions in Modes 1, 3, 4, 5, and 6: The settings in P2DDR are ignored. Port 2
automatically becomes a bidirectional data bus. Figure 10-10 shows the pin functions in modes 1,
3, 4, 5, and 6.
Pin Functions
Port 2
Figure 10-10 Pin Functions in Modes 1, 3, 4, 5, and 6
Rev. 3.0, 02/99, page 186 of 904

(2) Pin Functions in Modes 2 and 7: Port 2 consists of general-purpose input/output pins. Input
or output can be selected separately for each pin. A pin becomes an output pin if the
corresponding P2DDR bit is set to 1 and an input pin if this bit is cleared to 0. Figure 10-11
shows the pin functions in modes 2 and 7.
Pin Functions
Port 2
Figure 10-11 Pin Functions in Modes 2 and 7
(3) Software Standby Mode: Transition to software standby does not change the pin functions in
modes 2 and 7. In the externally expanded modes, port 2 is in the high-impedance state during
software standby.
P2DR and P2DDR have different read/write functions depending on whether port 2 is used as a
data bus (D7 to D0) or for general-purpose input or output (P27 to P20). The operating states and
Rev. 3.0, 02/99, page 187 of 904

(1) Data Bus (Modes 1, 3, 4, 5, and 6): Figure 10-12 shows a block diagram illustrating the data-
bus function. Table 10-7 indicates register read/write data. When port 2 operates as a data bus,
the values in the port 2 data register (P2DR) have no effect on the bus lines. When read, P2DR
returns all 1s.
Data bus
Internal data bus
D7-D 0
VCC
Read
Write
P2DR
Figure 10-12 Data Bus: D7 to D0 (Modes 1, 3, 4, 5, and 6)
Read Write
P2DR Always 1 Don't care*
(2) Input Port (Modes 2 and 7): Figure 10-13 shows a block diagram illustrating the general-
purpose input function. Table 10-8 indicates register read/write data. Values written in the port 2
data register (P2DR) have no effect on general-purpose input lines. When read, P2DR returns the
value at the pin.
Internal data bus
Read
P27-P2 0
Write
P2DR
Figure 10-13 Input Port (Modes 2 and 7)
Rev. 3.0, 02/99, page 188 of 904

Read Write
(3) Output Port (Modes 2 and 7): Figure 10-14 shows a block diagram illustrating the general-
purpose output function. Table 10-9 indicates register read/write data. The value written in the
port 2 data register (P2DR) is output at the pin. When read, P2DR returns the value written in
P2DR.
Internal data bus
P27-P2 0
Read/
Write
P2DR
Figure 10-14 Output Port (Modes 2 and 7)
Read Write
Rev. 3.0, 02/99, page 189 of 904

10.4 Port 3
10.4.1 Overview
Port 3 is a six-bit input/output port that is multiplexed with output compare pins (T2OC2, T2OC1,
T1OC4 to T1OC1) of the 16-bit integrated-timer pulse unit (IPU). Figure 10-15 summarizes the
pin functions.
Darlington transistor pair or LED (with 10-mA current sink).
P35 (input/output)/T2OC2 (output)

Port 3
Figure 10-16 shows examples of output loads for port 3.
Rev. 3.0, 02/99, page 190 of 904

HD7404 etc.
Darlington pair
H8/539F H8/539F 2 kΩ
VCC
600 Ω
H8/539F
Port 3
LED
(3) LED driving circuit

H'FE84 Port 3 data direction register P3DDR W H'C0
H'FE86 Port 3 data register P3DR R/W H'C0
register. Each bit selects input or output for one pin.
Rev. 3.0, 02/99, page 191 of 904

Bit 7 6 5 4 3 2 1 0
− − P35DDR P34DDR P33DDR P32DDR P31DDR P30DDR
R/W − − W W W W W W
read.
P3DDR is initialized to H'C0 by a reset and in hardware standby mode. P3DDR is not initialized
for pins P35 to P30.
Bit 7 6 5 4 3 2 1 0
− − P35 P34 P33 P32 P31 P30
R/W − − R/W R/W R/W R/W R/W R/W
P3DR is initialized to H'C0 by a reset and in hardware standby mode. P3DR is not initialized in
In all modes port 3 can be used for general-purpose input or output, or for the output compare
function of the 16-bit integrated-timer pulse unit (IPU).
(1) Pin Functions in Modes 1 to 7: When a pin is used for IPU output, the setting in P3DDR is
ignored. T1OC1 to T1OC4, T2OC1, or T2OC2 output is selected automatically. For methods of
selecting pin functions, see appendix D "Pin Function Selection."
(2) Software Standby Mode: Transition to software standby mode initializes the on-chip
supporting modules, so port 3 becomes an input or output port according to P3DDR and P3DR.
Rev. 3.0, 02/99, page 192 of 904

P3DR and P3DDR have different read/write functions depending on whether port 3 is used for the
output compare function (T1OC1 to T1OC4, T2OC1, T2OC2) of the 16-bit integrated-timer pulse
unit (IPU) or general-purpose input or output (P35 to P30). The operating states and functions of
port 3 are described next.
(1) Input Port (Modes 1 to 7): Figure 10-17 shows a block diagram illustrating the general-
purpose input function. Table 10-11 indicates register read/write data. Values written in the port
3 data register (P3DR) have no effect on general-purpose input lines. When read, P3DR returns
the value at the pin.
Internal data bus
Read
P35-P3 0
Write
P3DR
Figure 10-17 Input Port (Modes 1 to 7)
Read Write
(2) Output Port (Modes 1 to 7): Figure 10-18 shows a block diagram illustrating the general-
P3DR.
Rev. 3.0, 02/99, page 193 of 904

Internal data bus
P35-P3 0
Read/
Write
P3DR
Figure 10-18 Output Port (Modes 1 to 7)
Read Write
(3) Timer Output Pins (Modes 1 to 7): Figure 10-19 shows a block diagram illustrating the
output function using the output compare output pins. Table 10-13 indicates register read/write
data. When a pin in port 3 is used as an output compare output pin, the setting in the port 3 data
direction register (P3DDR) is ignored. The value in the port 3 data register (P3DR) has no effect
on the timer output. When read, P3DR returns the timer output level (T1OC1 to T1OC4, T2OC1, or
T2OC2).
Timer output
Internal data bus
Read T1OC1 to T1OC4

T2OC1, T2OC2
Write
P3DR
Figure 10-19 Timer Output Pins (Modes 1 to 7)
Read Write
Rev. 3.0, 02/99, page 194 of 904

10.5 Port 4
10.5.1 Overview
Port 4 is an eight-bit input/output port that is multiplexed with output compare and input capture
pins (T7IOC2, T7IOC1, T6IOC2, T6IOC1, T5IOC2, T5IOC1, T4IOC2, T4IOC1) of the 16-bit
integrated-timer pulse unit (IPU). Figure 10-20 summarizes the pin functions.
Darlington transistor pair. P47 to P40 have Schmitt-trigger input circuits.
P47 (input/output)/T7IOC2 (input/output)

Port 4
HD7404 etc. Darlington pair
2 kΩ
H8/539F H8/539F
Rev. 3.0, 02/99, page 195 of 904


Bit 7 6 5 4 3 2 1 0
R/W W W W W W W W W
read.
Bit 7 6 5 4 3 2 1 0
P47 P46 P45 P44 P43 P42 P41 P40
Rev. 3.0, 02/99, page 196 of 904

In all modes port 4 can be used for general-purpose input or output, or for the input capture and
output compare functions of the 16-bit integrated-timer pulse unit (IPU).
(1) Pin Functions in Modes 1 to 7: When a pin is used for the IPU output-compare function, the
setting in P4DDR has no effect. T4IOC1, T4IOC2, T5IOC1, T5IOC2, T6IOC1, T6IOC2, T7IOC1, or
T7IOC2 output is selected automatically. When the IPU input capture function is selected, the
P4DDR setting is valid and the pin can simultaneously function as a general-purpose input or
output port. For methods of selecting pin functions, see appendix D "Pin Function Selection."
input capture or output compare function (T4IOC1, T4IOC2, T5IOC1, T5IOC2, T6IOC1, T6IOC2,
T7IOC1, T7IOC2) of the 16-bit integrated-timer pulse unit (IPU) or for general-purpose input or
output (P47 to P40). The operating states and functions of port 4 are described next.
Internal data bus
Read
P47-P4 0
Write
P4DR
Rev. 3.0, 02/99, page 197 of 904

Read Write
P4DR.
Internal data bus
P47-P4 0
Read/
Write
P4DR
Read Write
output compare function. Table 10-17 indicates register read/write data. When a pin in port 4 is
used for output compare, the value in the port 4 data register (P4DR) has no effect on the timer
output. When read, P4DR returns the timer output level (T4IOC1, T4IOC2, T5IOC1, T5IOC2,
T6IOC1, T6IOC2, T7IOC1, or T7IOC2).
Rev. 3.0, 02/99, page 198 of 904

Timer output
Internal data bus

Read
T4IOC1, T4IOC 2
T5IOC1, T5IOC2
Write
P4DR T6IOC1, T6IOC2
T7IOC1, T7IOC2
Figure 10-24 Output Compare Pins (Modes 1 to 7)
Read Write
(4) Timer Input Combined with General-Purpose Output (Modes 1 to 7): Figure 10-25 shows
a block diagram illustrating the input capture function when combined with general-purpose
output. Table 10-18 indicates register read/write data. An input capture pin can also function as
an output port, in which case the output value is input to the timer.
Input capture input

Internal data bus
T4IOC1, T4IOC 2
Read/
Write T5IOC1, T5IOC2
P4DR T6IOC1, T6IOC2
T7IOC1, T7IOC2
Figure 10-25 Input Capture Combined with General-Purpose Output (Modes 1 to 7)
Read Write
P4DR P4DR value Value output at pin (timer input)
Rev. 3.0, 02/99, page 199 of 904

(5) Timer Input Combined with General-Purpose Input (Modes 1 to 7): Figure 10-26 shows a
block diagram illustrating the input capture function when combined with general-purpose input.
Table 10-19 indicates register read/write data. An input capture pin can also be read as an input
port, to monitor the timer input level at T4IOC1, T4IOC2, T5IOC1, T5IOC2, T6IOC1, T6IOC2,
T7IOC1, or T7IOC2.
Input capture input

Internal data bus
Read
T4IOC1, T4IOC 2
T5IOC1, T5IOC2
Write
P4DR T6IOC1, T6IOC2
T7IOC1, T7IOC2
Figure 10-26 Input Capture Combined with General-Purpose Input (Modes 1 to 7)
Read Write
P4DR Timer input Don't care*
Rev. 3.0, 02/99, page 200 of 904

10.6 Port 5
10.6.1 Overview
Port 5 is an eight-bit input/output port that is multiplexed with output compare and input capture
pins (T3IOC2, T3IOC1, T2IOC2, T2IOC1, T1IOC4 to T1IOC1) of the 16-bit integrated-timer pulse
unit (IPU). Figure 10-27 summarizes the pin functions.
Darlington transistor pair or LED (with 10-mA current sink). Inputs are Schmitt-triggered.

Port 5
Rev. 3.0, 02/99, page 201 of 904

HD7404 etc.
Darlington pair
H8/539F H8/539F 2 kΩ
VCC
600 Ω
H8/539F
Port 5
LED
(3) LED driving circuit

H'FE8A Port 5 data register P5DR R/W H'00
Rev. 3.0, 02/99, page 202 of 904

Bit 7 6 5 4 3 2 1 0
R/W W W W W W W W W
read.
Bit 7 6 5 4 3 2 1 0
P57 P56 P55 P54 P53 P52 P51 P50
In all modes port 5 can be used for general-purpose input or output, or for the input capture and
output compare functions of the 16-bit integrated-timer pulse unit (IPU).
(1) Pin Functions in Modes 1 to 7: When a pin is used for the IPU output compare function, the
setting in P5DDR is ignored. T1IOC1 to T1IOC4, T2IOC1, T2IOC2, T3IOC1, or T3IOC2 output is
selected automatically. When the IPU input capture function is selected, the P5DDR setting is
Rev. 3.0, 02/99, page 203 of 904
valid and the pin can simultaneously function as a general-purpose input or output port. For
methods of selecting pin functions, see appendix D "Pin Function Selection."
input capture or output compare function (T1IOC1 to T1IOC4, T2IOC1, T2IOC2, T3IOC1, T3IOC2)
of the 16-bit integrated-timer pulse unit (IPU) or for general-purpose input or output. The
operating states and functions of port 5 are described next.
Internal data bus
Read
P57-P5 0
Write
P5DR
Read Write
P5DR.
Rev. 3.0, 02/99, page 204 of 904

Internal data bus
P57-P5 0
Read/
Write
P5DR
Read Write
output compare function. Table 10-23 indicates register read/write data. When a pin in port 5 is
used for output compare, the value in the port 5 data register (P5DR) has no effect on the timer
output. P5DR can be read to monitor the timer output level (T1IOC1 to T1IOC4, T2IOC1, T2IOC2,
T3IOC1, T3IOC2).
Output compare output

Internal data bus
Read
T1IOC1 -T1IOC4

P5DR T3IOC1, T3IOC2
Read Write
Rev. 3.0, 02/99, page 205 of 904

(4) Timer Input Combined with General-Purpose Output (Modes 1 to 7): Figure 10-32 shows
a block diagram illustrating the input capture function when combined with general-purpose
output. Table 10-24 indicates register read/write data. An input capture pin can also function as
an output port, in which case the output value is input to the timer.
Internal data bus Input capture input
T1IOC1 -T1IOC4
Read/
P5DR T3IOC1, T3IOC2
Figure 10-32 Input Capture Combined with General-Purpose Output (Modes 1 to 7)
Read Write
P5DR P5DR value Value output at pin (Timer input)
(5) Timer Input Combined with General-Purpose Input (Modes 1 to 7): Figure 10-33 shows a
block diagram illustrating the input capture function when combined with general-purpose input.
Table 10-25 indicates register read/write data. An input capture pin can also be read as an input
port, to monitor the timer input level at T1IOC1 to T1IOC4, T2IOC1, T2IOC2, T3IOC1, or T3IOC2.
Input capture input

Internal data bus
Read
T1IOC1 -T1IOC4

P5DR T3IOC1, T3IOC2
Figure 10-33 Input Capture Combined with General-Purpose Input (Modes 1 to 7)
Read Write
Rev. 3.0, 02/99, page 206 of 904

10.7 Port 6
10.7.1 Overview
Port 6 is a five-bit input/output port that is multiplexed with the external clock pins (TCLK3 to
TCLK1) of the 16-bit integrated-timer pulse unit (IPU), with external interrupt pins (,543 and
,542), and with a PWM timer output pin (PW3). Figure 10-34 summarizes the pin functions.
P64 (input/output)/TCLK3 (input)

P63 (input/output)/TCLK2 (input)
Port 6 P62 (input/output)/TCLK1 (input)
P61 (input/output)/IRQ3 (input)
P60 (input/output)/IRQ2 (input)/PW3 (output)
HD7404 etc.
Darlington pair
2 kΩ
H8/539F H8/539F
Rev. 3.0, 02/99, page 207 of 904


H'FE89 Port 6 data direction register P6DDR W H'E0
H'FE8B Port 6 data register P6DR R/W H'E0
H'FEDB Port 6/7 control register P67CR R/W H'3E
Bit 7 6 5 4 3 2 1 0
− − − P64DDR P63DDR P62DDR P61DDR P60DDR
R/W − − − W W W W W
read.
P6DDR is initialized to H'E0 by a reset and in hardware standby mode. P6DDR is not initialized
Bit 7 6 5 4 3 2 1 0
− − − P64 P63 P62 P61 P60
R/W − − − R/W R/W R/W R/W R/W
pin.
Rev. 3.0, 02/99, page 208 of 904
P6DR is initialized to H'E0 by a reset and in hardware standby mode. P6DR is not initialized in
(3) Port 6/7 Control Register: The port 6/7 control register (P67CR) is an eight-bit register that
controls the functions of pin P60 in port 6 and pins P77 and P76 in port 7.
Bit 7 6 5 4 3 2 1 0
PW2E PW1E − − − − − PW3E
R/W R/W R/W R R R R R R/W
Bits 7 and 6-PW2 Enable and PW1 Enable (PW2E, PW1E): These bits control the PWM output
function of pins P77/SCK2/PW2 and P76/SCK1/PW1 in port 7. When bits PW2E and PW1E are set
to 1, these pins can be used for PW2 and PW1 output and cannot be used for SCK2 and SCK1
output.
Bit 0-PW3 Enable (PW3E): Controls the PWM output function of pin P60/,542/PW3 in port 6.
When bit PW3E is set to 1, this pin can be used for PW3 output.
(1) Pin Functions in Modes 1 to 7: When a pin is used for IPU external clock input (TCLK3 to
TCLK1) or external interrupt input (,543,#,542), it can simultaneously function as a general-
purpose input or output port. When a pin is used for PWM timer output (PW3), the P6DDR setting
is disregarded and the PW3 function is selected. For methods of selecting pin functions, see
appendix D "Pin Function Selection."
P6DR and P6DDR have different read/write functions depending on whether port 6 is used for
external clock input (TCLK3 to TCLK1) to the 16-bit integrated-timer pulse unit (IPU), external
interrupt input (,543,#,542), PWM timer output (PW3), or general-purpose input or output (P64 to
P60). The operating states and functions of port 6 are described next.
Rev. 3.0, 02/99, page 209 of 904

Internal data bus
Read
P64-P6 0
Write
P6DR
Read Write
P6DR.
Internal data bus
P64-P6 0
Read/
Write
P6DR
Read Write
(3) ,543 or ,542 Input Combined with General-Purpose Output (P61, P60: modes 1 to 7):
Figure 10-38 shows a block diagram illustrating the ,543 and ,542 input function of P61 and P60
when combined with general-purpose output. Table 10-29 indicates register read/write data.
When P61 and P60 are used for ,543 and ,542 input they can also function as general-purpose
Rev. 3.0, 02/99, page 210 of 904

output ports. If the general-purpose output function is used, however, output of a falling edge will
cause an interrupt.
IRQ2 or IRQ3 input
Internal data bus

IRQ2, IRQ3
Read/
Write
P6DR
Figure 10-38 ,543 or ,542 Input Combined with General-Purpose Output (Modes 1 to 7)
Read Write
(4) ,543 or ,542 Input Combined with General-Purpose Input (P61, P60: Modes 1 to 7):
Figure 10-39 shows a block diagram illustrating the ,543 and ,542 input function when combined
with general-purpose input. Table 10-30 indicates register read/write data. When P61 and P60 are
used for ,543 and ,542 input they can also be read as general-purpose input ports, to monitor the
input level at ,543 or ,542.
IRQ2 or IRQ3 input

Internal data bus
Read
IRQ2, IRQ3
Write
P6DR
Figure 10-39 ,543 or ,542 Input Combined with General-Purpose Input (Modes 1 to 7)
Read Write
Rev. 3.0, 02/99, page 211 of 904

(5) Timer Clock Input Combined with General-Purpose Output (P64 to P62: Modes 1 to 7):
Figure 10-40 shows a block diagram illustrating the TCLK3 to TCLK1 input function of P64 to P62
when combined with general-purpose output. Table 10-31 indicates register read/write data.
When P64 to P62 are used for TCLK3, TCLK2, and TCLK1 input they can also function as general-
purpose output ports.
TCLK3 to TCLK1 input

Internal data bus
TCLK3 −TCLK 1
Read/
Write
P6DR
Figure 10-40 TCLK3 to TCLK1 Input Combined with General-Purpose Output

(Modes 1 to 7)
Read Write
(6) Timer Clock Input Combined with General-Purpose Input (P64 to P62: Modes 1 to 7):
Figure 10-41 shows a block diagram illustrating the TCLK3 to TCLK1 input function of P64 to P62
when combined with general-purpose input. Table 10-32 indicates register read/write data. When
P64 to P62 are used for TCLK3, TCLK2, and TCLK1 input they can also be read as general-purpose
input ports, to monitor the input level at TCLK3 to TCLK1.
TCLK3 to TCLK1 input

Internal data bus
Read
TCLK3 −TCLK 1
Write
P6DR
Figure 10-41 TCLK3 to TCLK1 Input Combined with General-Purpose Input

(Modes 1 to 7)
Rev. 3.0, 02/99, page 212 of 904

Read Write
(7) PW3 Output Combined with General-Purpose Input (P60: Modes 1 to 7): Figure 10-42
shows a block diagram illustrating the PW3 output function of P60 when combined with general-
purpose input. Table 10-33 indicates register read/write data. When P60 is used for PW3 output it
can also be read as a general-purpose input port, to monitor the state of the PW3 pin.
PW3 output
Internal data bus
Read
PW3
Write
P6DR
Figure 10-42 PW3 Output Combined with General-Purpose Input (Modes 1 to 7)
Read Write
Rev. 3.0, 02/99, page 213 of 904

10.8 Port 7
10.8.1 Overview
Port 7 is an eight-bit input/output port that is multiplexed with the serial clock input/output pins
(SCK2 and SCK1), transmit data output pins (TXD2 and TXD1), and receive data input pins (RXD2
and RXD1) of the serial communication interface (SCI), with PWM timer output pins (PW1 and
PW2), with external interrupt pins (IRQ1 and IRQ0), and with the external trigger pin ($'75*) of
the A/D converter. Figure 10-43 summarizes the pin functions. Pins in port 7 can drive one TTL
load and a 30-pF capacitive load. They can also drive a Darlington transistor pair.
P77 (input/output)/SCK2 (input/output)/PW2 (output)

P76 (input/output)/SCK1 (input/output)/PW1 (output)
P75 (input/output)/RXD2 (input)
P74 (input/output)/TXD2 (output)
Port 7
P73 (input/output)/RXD1 (input)
P72 (input/output)/TXD1 (output)
P71 (input/output)/IRQ1 (input)/ADTRG (input)
P70 (input/output)/IRQ0 (input)
HD7404 etc.
Darlington pair
2 kΩ
H8/539F H8/539F
Rev. 3.0, 02/99, page 214 of 904


H'FE8C Port 7 data direction register P7DDR W H'00
H'FE8E Port 7 data register P7DR R/W H'00
H'FEDE Port 6/7 control register P67CR R/W H'3E
Bit 7 6 5 4 3 2 1 0
R/W W W W W W W W W
read.
Bit 7 6 5 4 3 2 1 0
P77 P76 P75 P74 P73 P72 P71 P70
Rev. 3.0, 02/99, page 215 of 904

(3) Port 6/7 Control Register: The port 6/7 control register (P67CR) is an eight-bit register that
controls the functions of pin P60 in port 6 and pins P77 and P76 in port 7.
Bit 7 6 5 4 3 2 1 0
PW2E PW1E − − − − − PW3E
R/W R/W R/W R R R R R R/W
Bits 7 and 6-PW2 Enable and PW1 Enable (PW2E, PW1E): These bits control the PWM output
function of pins P77/SCK2/PW2 and P76/SCK1/PW1 in port 7. When bits PW2E and PW1E are set
to 1, these pins can be used for PW2 and PW1 output and cannot be used for SCK2 and SCK1
output.
Bit 0-PW3 Enable (PW3E): Controls the PWM output function of pin P60/,542/PW3 in port 6.
When bit PW3E is set to 1, this pin can be used for PW3 output.
(1) Pin Functions in Modes 1 to 7: When a pin is used for input or output by the serial
communication interface (SCI) or a PWM timer, the P7DDR setting is disregarded and the pin is
used for serial clock input or output (SCK2, SCK1), transmit data output (TXD2, TXD1), receive
data input (RXD2, RXD1), or PWM timer output (PW1, PW2).
When P71 and P70 are used for external interrupt input (,541 and ,540), they can simultaneously
function as general-purpose input or output ports. P71 can also function as the external trigger
signal ($'75*) for the A/D converter.
For methods of selecting pin functions, see appendix D "Pin Function Selection."
P7DR and P7DDR have different read/write functions depending on whether port 7 is used for
output of transmit data (TXD1, TXD2), input of receive data (RXD1, RXD2), input or output of
serial clocks (SCK1, SCK2) for the serial communication interface, PWM timer output (PW2, PW1),
external interrupt input (,541,#,540), or general-purpose input or output. The operating states and
Rev. 3.0, 02/99, page 216 of 904

purpose input function. Table 10-35 indicates register read/write data. Values written in the port 7
data register (P7DR) have no effect on general-purpose input lines. When read, P7DR returns the
value at the pin.
Internal data bus Read

P77-P7 0
Write
P7DR
Read Write
P7DR.
Internal data bus
P77-P7 0
Read/
Write
P7DR
Read Write
Rev. 3.0, 02/99, page 217 of 904

(3) ,541 or ,540 Input Combined with General-Purpose Output (P71, P70: Modes 1 to 7):
with general-purpose output. Table 10-37 indicates register read/write data. When P71 and P70 are
used for ,541 and ,540 input they can also function as general-purpose output ports. If the
general-purpose output function is used, however, output of a falling edge will cause an interrupt.
IRQ1 or IRQ0 input

Internal data bus
IRQ1, IRQ0
Read/
Write
P7DR
Figure 10-47 ,541 or ,540 Input Combined with General-Purpose Output (Modes 1 to 7)
Read Write
(4) ,541 or ,540 Input Combined with General-Purpose Input (P71, P70: Modes 1 to 7):
with general-purpose input. Table 10-38 indicates register read/write data. When P71 and P70 are
used for ,541 and ,540 input they can also be read as general-purpose input ports, to monitor the
input level at ,541 or ,540.
IRQ1 or IRQ0 input

Internal data bus
Read
IRQ1, IRQ0
Write
P7DR
Figure 10-48 ,541 or ,540 Input Combined with General-Purpose Input (Modes 1 to 7)
Rev. 3.0, 02/99, page 218 of 904

Read Write
(5) TXD2 and TXD1 Output (P74 and P72: Modes 1 to 7): Figure 10-49 shows a block diagram
illustrating the TXD2 and TXD1 output function. Table 10-39 indicates register read/write data.
When P74 and P72 are used for TXD2 and TXD1 output, the value written in P7DR is ignored, but
P7DR can be read to monitor the levels at the TXD2 and TXD1 pins.
Transmit data output

Internal data bus
Read
TXD2, TXD1
Write
P7DR
Figure 10-49 TXD2 and TXD1 Output (Modes 1 to 7)
Read Write
(6) RXD2 and RXD1 Input (P75 and P73: Modes 1 to 7): Figure 10-50 shows a block diagram
illustrating the RXD2 and RXD1 input function. Table 10-40 indicates register read/write data.
When P75 and P73 are used for RXD2 and RXD1 input, the value written in P7DR is ignored, but
P7DR can be read to monitor the levels at the RXD2 and RXD1 pins (to detect the line break state,
for example).
Rev. 3.0, 02/99, page 219 of 904

Receive data input
Internal data bus

Read
RXD2, RXD1
Write
P7DR
Figure 10-50 RXD2 and RXD1 Input (Modes 1 to 7)
Read Write
(7) SCK2 and SCK1 Pins (P77 and P76: Modes 1 to 7): Figure 10-51 shows a block diagram
illustrating the SCK2 and SCK1 input/output function. Table 10-41 indicates register read/write
data. When P77 and P76 are used for SCK2 and SCK1 input or output, the value written in P7DR is
ignored, but P7DR can be read to monitor the levels at the SCK 2 and SCK1 pins.
Serial clock input

or output
Internal data bus
Read
SCK2, SCK1
Write
P7DR
Figure 10-51 SCK2 and SCK1 Pins (Modes 1 to 7)
Read Write
Rev. 3.0, 02/99, page 220 of 904

(8) PW2 and PW1 Output (P77 and P76: Modes 1 to 7): Figure 10-52 shows a block diagram
illustrating the PWM output function. Table 10-42 indicates register read/write data. When P77
and P76 function as PW2 and PW1, data written in the port 7 data register (P7DR) is not output at
the pins, but P7DR can be read to monitor the levels of the PW2 and PW1 pins.
PWM output

PW1, PW2
Write
P7DR
Figure 10-52 PW2 and PW1 Output (Modes 1 to 7)
Read Write
Rev. 3.0, 02/99, page 221 of 904

10.9 Port 8
10.9.1 Overview
Port 8 is a four-bit input port that is multiplexed with analog input pins of the A/D converter.
Figure 10-53 summarizes the pin functions.
P83/AN11 (input)
P82/AN10 (input)
Port 8
P81/AN9 (input)
P80/AN8 (input)
Table 10-43 summarizes the registers of port 8. Since port 8 is used only for input, there is no
data direction register.

H'FE8F Port 8 data register P8DR R Undetermined
(1) Port 8 Data Register: The port 8 data register (P8DR) is an eight-bit register that indicates
the values of pins P83 to P80.
Bit 7 6 5 4 3 2 1 0
− − − − P83 P82 P81 P80
Initial value 1 1 1 1 − − − −
R/W − − − − R R R R
P8DR is a read-only register. It cannot be written. The upper four bits of P8DR are reserved bits
that always return the value 1 when read.
Rev. 3.0, 02/99, page 222 of 904
10.9.3 Port 8 Read Operation
Figure 10-54 shows a block diagram of port 8.
While being used for analog input, port 8 can also function as a general-purpose input port. When
read, P8DR returns the values at the pins. If P8DR is read when the A/D converter is sampling an
analog input, however, the pin being sampled is read as 1.
AN11 to AN8 input

Internal data bus
Read
P83-P8 0
Figure 10-54 Analog Input and General-Purpose Input (Modes 1 to 7)
10.10 Port 9
10.10.1 Overview
Port 9 is an eight-bit input port that is multiplexed with analog input pins of the A/D converter.
Figure 10-55 summarizes the pin functions.
P97/AN7 (input)
P96/AN6 (input)
P95/AN5 (input)
P94/AN4 (input)
Port 9
P93/AN3 (input)
P92/AN2 (input)
P91/AN1 (input)
P90/AN0 (input)
Rev. 3.0, 02/99, page 223 of 904

Table 10-44 summarizes the registers of port 9. Since port 9 is used only for input, there is no
data direction register.

H'FE92 Port 9 data register P9DR R Undetermined
(1) Port 9 Data Register: The port 9 data register (P9DR) is an eight-bit register that indicates
the values of pins P97 to P90.
Bit 7 6 5 4 3 2 1 0
P97 P96 P95 P94 P93 P92 P91 P90
Initial value − − − − − − − −
R/W R R R R R R R R
P9DR is a read-only register. It cannot be written.
10.10.3 Port 9 Read Operation
Figure 10-56 shows a block diagram of port 9.
While being used for analog input, port 9 can also function as a general-purpose input port. When
read, P9DR returns the values at the pins. If P9DR is read when the A/D converter is sampling an
analog input, however, the pin being sampled is read as 1.
AN7 to AN0 input

Internal data bus
Read
P97-P9 0
Figure 10-56 Analog Input and General-Purpose Input (Modes 1 to 7)
Rev. 3.0, 02/99, page 224 of 904

10.11 Port A
10.11.1 Overview
Port A is a seven-bit input/output port that is multiplexed with output compare pins (T5OC2,
T5OC1, T4OC2, T4OC1, T3OC2, T3OC1) of the 16-bit integrated-timer pulse unit (IPU), pins for
the %5(4, %$&., and :$,7 signals, PWM timer output pins (PW1 to PW3), serial
communication interface 3 input and output pins (TXD 3, RXD3, SCK3), and the page address bus
(A19 to A16). Figure 10-57 summarizes the pin functions. Pins in port A can drive one TTL load and
a 90-pF capacitive load. They can also drive a Darlington transistor pair.
PA6 (input/output)/T3OC2 (output)/BACK (output)/TXD3 (output)

PA5 (input/output)/T3OC1 (output)/BREQ (input)/RXD3 (input)
PA4 (input/output)/WAIT (input)
Port A PA3 (input/output)/T5OC2 (output)/A19 (output)/SCK3 (input/output)
PA2 (input/output)/T5OC1 (output)/A18 (output)/PW3 (output)
Figure 10-57 Port A Pin Functions
Figure 10-58 shows examples of output loads for port A.
HD7404 etc.
Darlington pair
H8/539F H8/539F 2 kΩ
Port A HD74LS04 etc. Port A
Figure 10-58 Examples of Port A Output Loads
Rev. 3.0, 02/99, page 225 of 904

Table 10-45 summarizes the registers of port A.
Table 10-45 Port A Registers

H'FE91 Port A data direction register PADDR W H'80
H'FE93 Port A data register PADR R/W H'80
H'FEDA Port A control register PACR R/W H'90
(1) Port A Data Direction Register: The port A data direction register (PADDR) is an eight-bit
Bit 7 6 5 4 3 2 1 0
− PA6DDR PA5DDR PA4DDR PA3DDR PA2DDR PA1DDR PA0DDR
R/W − W W W W W W W
A pin in port A becomes an output pin if the corresponding PADDR bit is set to 1, and an input
pin if this bit is cleared to 0. PADDR is a write-only register. All bits always return the value 1
when read.
PADDR is initialized to H'80 by a reset and in hardware standby mode. PADDR is not initialized
(2) Port A Data Register: The port A data register (PADR) is an eight-bit register that stores
data for pins PA6 to PA0.
Bit 7 6 5 4 3 2 1 0
− PA6 PA5 PA4 PA3 PA2 PA1 PA0
R/W − R/W R/W R/W R/W R/W R/W R/W
When a bit in PADDR is set to 1, the corresponding PADR bit value is output at the corresponding
pin. If port A is read the value in PADR is returned, regardless of the actual state of the pin.
When a bit in PADDR is cleared to 0, it is possible to write to the corresponding PADR bit but the
value is not output at the pin. If PADR is read the value at the pin is returned, regardless of the
value written in PADR.
Rev. 3.0, 02/99, page 226 of 904

PADR is initialized to H'80 by a reset and in hardware standby mode. PADR is not initialized in
(3) Port A Control Register: The port A control register (PACR) is an eight-bit register that
controls the functions of pin PA6 to PA0.
Bit 7 6 5 4 3 2 1 0
− TXD3E RXD3E − SCK3E PW3E PW2E PW1E
R/W R R/W R/W R R/W R/W R/W R/W
Bits 6, 5, and 3—TXD3 Enable, RXD3 Enable, and SCK3 Enable (TXD3E, RXD3E, SCK3E):
These bits control the TXD3, RXD3, and SCK3 functions of pins PA6/T3OC2/%$&./TXD3,
PA5/T3OC1/%5(4/RXD3, and PA3/T5OC2/A19/SCK3 in port A. When bits TXD3E, RXD3E, and
SCK3E are set to 1, pins PA6, PA5, and PA3 can be used for TXD3 output, RXD3 input, and SCK3
input or output.
Bits 2 to 0—PW3 Enable, PW2 Enable, and PW1 Enable, (PW3E, PW2E, PW1E): These bits
control the PW3 to PW1 functions of pins PA2/T5OC1/A18/PW3, PA1/T4OC2/A17/PW2, and
PA0/T4OC1/A16/PW1 in port A. When bits PW3E, PW2E, and PW1E are set to 1, these pins can be
used for PW3 output, PW2 output, and PW1 output.
Port A has different functions in different operating modes. A description for each mode is given
next.
(1) Pin Functions in Modes 1, 2, and 6: Port A can be used for the output-compare function
(T3OC2, T3OC1, T4OC2, T4OC1, T5OC2, T5OC1) of the 16-bit integrated-timer pulse unit (IPU),
bus control (%5(4 and %$&.), serial communication interface 3 input and output (SCK3, TXD3,
RXD3), PWM timer output (PW3, PW2, PW1), wait signal input (:$,7), and general-purpose
output.
When a pin is used for output compare, bus control, serial communication interface 3 input or
output, PWM timer output, or wait signal input, the PADDR setting is ignored.
The priority of pin functions for PA5/T3OC1/%5(4/RXD3 and PA6/T3OC2/%$&./TXD3 is:
Bus control > TXD3, RXD3 > output compare > general-purpose output
The TXD3 and RXD3 pin functions are available when bits TXD3E and RXD3E are set to 1 in the
port A control register (PACR). When these bits are set to 1, the corresponding pins cannot be
used for output compare.
Rev. 3.0, 02/99, page 227 of 904
The priority of pin functions for PA3/T5OC2/SCK3, PA2/T5OC1/PW3, PA1/T4OC2/PW2, and
PA0/T4OC1/PW1 is:
PWM output pins, serial communication interface pins > output compare output pins > output
portst
The SCK3, PW3, PW2, and PW1 pin functions are available when bits SCK3E, PW3E, PW2E, and
PW1E, respectively, are set to 1 in PACR. When these bits are set to 1, the corresponding pins
cannot be used as output compare pins.
Figure 10-59 shows the functions of port A in modes 1, 2, and 6.
PA 6/T3OC2/BACK/TXD3
PA 5/T3OC1/BREQ/RXD3
PA 4/WAIT
Port A PA 3/T5OC2/SCK3
PA 2/T5OC1/PW3
PA 1/T4OC2/PW2
PA 0/T4OC1/PW1
Figure 10-59 Port A Pin Functions in Modes 1, 2, and 6
(2) Pin Functions in Modes 3 and 5: Port A has pins that can be used for the output compare
function (T3OC2, T3OC1) of the 16-bit integrated-timer pulse unit (IPU), bus control (%5(4 and
%$&.), serial communication interface 3 input and output (TXD3, RXD3), wait signal input
(:$,7), or general-purpose input or output, and pins that are used for page address output (A19 to
A16). When a pin is used for output compare, bus control, serial communication input/output, or
wait signal input, the PADDR setting is ignored.
TXD3, RXD3 > bus control > output compare > general-purpose output
Rev. 3.0, 02/99, page 228 of 904

Figure 10-60 shows the functions of port A in modes 3 and 5.
PA 6 /T3OC2/BACK/TXD3
PA 5 /T3OC1/BREQ/RXD3
PA 4 /WAIT
Port A A19 (page address bus)
A18 (page address bus)
Figure 10-60 Port A Pin Functions in Modes 3 and 5
(3) Pin Functions in Mode 4: Port A has pins that can be used for the output compare function
(T3OC2, T3OC1) of the 16-bit integrated-timer pulse unit (IPU), bus control (%5(4 and %$&.),
serial communication interface 3 input and output (SCK3, TXD3, RXD3), PWM timer output (PW1,
PW2, PW3), wait signal input (:$,7), page address output (A19 to A16), and general-purpose input
or output. When a pin is used for output compare, bus control, serial communication input/output,
PWM timer output, or wait signal input, the PADDR setting is ignored.
The SCK3, PW3, PW2, and PW1 functions of pins PA3 to PA0 are available when bits SCK3E,
PW3E, PW2E, and PW1E are set to 1 in the port A control register (PACR). When these bits are
set to 1, the corresponding pins cannot be used for page address output. When bits SCK3E, PW3E,
PW2E, and PW1E are cleared to 0 in PACR, these pins are used for page address output if the
corresponding PADDR bit is set to 1, and for general-purpose input if the corresponding PADDR
bit is cleared to 0.
Bus control > TXD3, RXD3 > output compare > general-purpose output
The priority of pin functions for PA3/A19/SCK3, PA2/A18/PW3, PA1/A17/PW2, and PA0/A16/PW1 is:
SCK3, PW3 to PW1 > address bus > general-purpose input
Figure 10-61 shows the functions of port A in mode 4.
Rev. 3.0, 02/99, page 229 of 904

PA 6/T3OC2/BACK/TXD3
PA 5/T3OC1/BREQ/RXD3
PA 4/WAIT
Port A PA 3 (input)/A19 (page address bus)/SCK3
PA 2 (input)/A18 (page address bus)/PW3
Figure 10-61 Port A Pin Functions in Mode 4
(4) Pin Functions in Mode 7: Port A can be used for the output compare function (T3OC2,
T3OC1, T4OC2, T4OC1, T5OC2, T5OC1) of the 16-bit integrated-timer pulse unit (IPU), serial
communication interface 3 input and output (SCK3, TXD3, RXD3), PWM timer output (PW1, PW2,
PW3), and general-purpose input or output. When a pin is used for serial communication interface
3 input or output, PWM timer output, or output compare, the PADDR setting is ignored.
The priority of pin functions for PA6/T3OC2/TXD3 and PA5/T3OC1/RXD3 is:
TXD3, RXD3 > output compare > general-purpose output
The priority of pin functions for PA3/T5OC2/SCK3, PA2/T5OC1/PW3, PA1/T4OC2/PW2, and

PA0/T4OC1/PW1 is:
PWM output pins, serial communication interface pins > output compare output pins >
output ports
The SCK3, PW3, PW2, and PW1 pin functions are available when bits SCK3E, PW3E, PW2E, and
PW1E, respectively, are set to 1 in PACR. When these bits are set to 1, these pins cannot be used
as output compare pins.
Figure 10-62 shows the functions of port A in mode 7.
Rev. 3.0, 02/99, page 230 of 904

PA 6/T3OC2/TXD3
PA 5/T3OC1/RXD3
PA 4
Port A PA 3/T5OC2/SCK3
PA 2/T5OC1/PW3
PA 1/T4OC2/PW2
PA 0/T4OC1/PW1
Figure 10-62 Port A Pin Functions in Mode 7
10.11.4 Port A Read/Write Operations
PADR and PADDR have different read/write functions depending on whether port A is used for
bus control (%5(4, %$&.), wait signal input (:$,7), the output compare function (T5OC2,
T5OC1, T4OC2, T4OC1, T3OC2, T3OC1) of the 16-bit integrated-timer pulse unit (IPU), serial
communication interface 3 input or output (SCK3, TXD3, RXD3), or general-purpose input or
output. The operating states and functions of port A are described next.
(1) Input Port (PA6 to PA4 in Modes 1 to 7; PA3 to PA0 in Modes 1, 2, 4, 6, and 7): Figure 10-
63 shows a block diagram illustrating the general-purpose input function. Table 10-46 indicates
register read/write data. Values written in the port A data register (PADR) have no effect on
general-purpose input lines. When read, PADR returns the value at the pin.
Internal data bus
Read
PA6-PA 0
Write
PADR
Rev. 3.0, 02/99, page 231 of 904

Read Write
PADR Pin value Don't care*
(2) Output Port (PA6 to PA4 in Modes 1 to 7; PA3 to PA0 in Modes 1, 2, 4, 6, and 7): Figure
10-64 shows a block diagram illustrating the general-purpose output function. Table 10-47
indicates register read/write data. The value written in the port A data register (PADR) is output
at the pin. When read, PADR returns the value written in PADR.
Internal data bus
PA6-PA 0
Read/
Write
PADR
Read Write
PADR PADR value Value output at pin
(3) %5(4 Pin (PA5: Modes 1 to 6): Figure 10-65 shows a block diagram illustrating the %5(4
function. Table 10-48 indicates register read/write data. When PA5 is used for %5(4 input, the
value written in the port A data register (PADR) has no effect.
BREQ input
Internal data bus
Read
BREQ
Write
PADR
Figure 10-65 %5(4 Input Pin (Modes 1 to 6)
Rev. 3.0, 02/99, page 232 of 904

Read Write
(4) %$&. Pin (PA6: Modes 1 to 6): Figure 10-66 shows a block diagram illustrating the %$&.
function. Table 10-49 indicates register read/write data. When PA6 is used for %$&. output, the
value written in the port A data register (PADR) has no effect. When read, PADR returns an
undetermined value.
BACK output
Internal data bus
BACK
Write
PADR
Figure 10-66 %$&. Output Pin (Modes 1 to 6)
Read Write
PADR Undetermined value Don't care*
(5) :$,7 Pin (PA4: Modes 1 to 6): Figure 10-67 shows a block diagram illustrating the :$,7
function. Table 10-50 indicates register read/write data. When PA4 is used for :$,7 input, the
value written in the port A data register (PADR) has no effect.
WAIT input
Internal data bus
Read
WAIT
Write
PADR
Figure 10-67 :$,7 Input Pin (Modes 1 to 6)
Rev. 3.0, 02/99, page 233 of 904

Read Write
(6) Timer Output Pins (PA6, PA5, PA3 to PA0: Modes 1 to 7): Figure 10-68 shows a block
diagram illustrating the timer output function. Table 10-51 indicates register read/write data.
When PA6, PA5, and PA3 to PA0 are used for T3OC2, T3OC1, T5OC2, T5OC1, T4OC2, and T4OC1
output, values written in the port A data register (PADR) have no effect on the timer output.
PADR can be read to monitor the timer output level (T3OC2, T3OC1, T5OC2, T5OC1, T4OC2,
T4OC1).
Output compare output

Internal data bus
Read
T3OC2, T3OC1
Write T5OC1, T5OC2

PADR T4OC1, T4OC2
Read Write
(7) Page Address Bus (PA3 to PA0: Modes 3 to 5): Figure 10-69 shows a block diagram
illustrating the page-address-bus function. Table 10-52 indicates register read/write data. When
PA3 to PA0 are used for A19 to A16 output, values written in the port A data register (PADR) have
no effect. When read, PADR returns an undetermined value.
Rev. 3.0, 02/99, page 234 of 904

Page address
Internal data bus

A19-A 16
Write
PADR
Figure 10-69 Page Address Bus (Modes 3 to 5)
Read Write
PADR Undetermined value Don't care*
(8) TXD3 Output (PA6: Modes 1, 2, 4, 6, and 7): Figure 10-70 shows a block diagram
illustrating the TXD3 output function. Table 10-53 indicates register read/write data. When PA6 is
used for TXD3 output, the value written in PADR is ignored, but PADR can be read to monitor the
level at the TXD3 pin.
TXD3
output
Internal data bus
Read
TXD3
Write
PADR
Figure 10-70 TXD3 Output (Modes 1, 2, 4, 6, and 7)
Read Write
Rev. 3.0, 02/99, page 235 of 904

(9) RXD3 Input (PA5: Modes 1, 2, 4, 6, and 7): Figure 10-71 shows a block diagram illustrating
the RXD3 input function. Table 10-54 indicates register read/write data. When PA5 is used for
RXD3 input, the value written in PADR is ignored, but PADR can be read to monitor the level at
the RXD3 pin.
RXD3
input

RXD3
Write
PADR
Figure 10-71 RXD3 Input (Modes 1, 2, 4, 6, and 7)
Read Write
(10) SCK3 Pin (PA3: Modes 1, 2, 4, 6, and 7): Figure 10-72 shows a block diagram illustrating
the SCK3 input/output function. Table 10-55 indicates register read/write data. When PA3 is used
for SCK3 input or output, the value written in PADR is ignored, but PADR can be read to monitor
the level at the SCK3 pin.
SCK3
input or output
Internal data bus
Read
SCK3
Write
PADR
Figure 10-72 SCK3 Pins (Modes 1, 2, 4, 6, and 7)
Rev. 3.0, 02/99, page 236 of 904

Read Write
10.12 Port B
10.12.1 Overview
Port B is an-eight-bit input/output port. Figure 10-73 summarizes the pin functions.
Pins in port B can drive one TTL load and a 90-pF capacitive load. They can also drive a
Darlington transistor pair. They have software-programmable built-in MOS pull-up transistors.
PB7 (input/output)/A15 (output)

Port B
Figure 10-73 Port B Pin Functions
Figure 10-74 shows examples of output loads for port B.
Rev. 3.0, 02/99, page 237 of 904

HD7404 etc.
Darlington pair
H8/539F H8/539F 2 kΩ
Port B HD74LS04 etc. Port B
Figure 10-74 Examples of Port B Output Loads
Table 10-56 summarizes the registers of port B.
Table 10-56 Port B Registers

H'FE94 Port B data direction register PBDDR W H'00
H'FE96 Port B data register PBDR R/W H'00
H'FE98 Port B pull-up transistor control register PBPCR R/W H'00
(1) Port B Data Direction Register: The port B data direction register (PBDDR) is an-eight-bit
Bit 7 6 5 4 3 2 1 0
PB7DDR PB6DDR PB5DDR PB4DDR PB3DDR PB2DDR PB1DDR PB0DDR
R/W W W W W W W W W
A pin in port B becomes an output pin if the corresponding PBDDR bit is set to 1, and an input pin
if this bit is cleared to 0. PBDDR is a write-only register. All bits always return the value 1 when
read.
PBDDR is initialized to H'00 by a reset and in hardware standby mode. PBDDR is not initialized
Rev. 3.0, 02/99, page 238 of 904

(2) Port B Data Register: The port B data register (PBDR) is an-eight-bit register that stores data
for pins PB7 to PB0.
Bit 7 6 5 4 3 2 1 0
PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0
When a bit in PBDDR is set to 1, the corresponding PBDR bit value is output at the corresponding
pin. If port B is read the value in PBDR is returned, regardless of the actual state of the pin.
When a bit in PBDDR is cleared to 0, it is possible to write to the corresponding PBDR bit but the
value is not output at the pin. If PBDR is read the value at the pin is returned, regardless of the
value written in PBDR.
PBDR is initialized to H'00 by a reset and in hardware standby mode. PBDR is not initialized in
(3) Port B Pull-Up Transistor Control Register: The port B pull-up transistor control register
(PBPCR) is an-eight-bit register that turns the MOS pull-up transistors of PB7 to PB0 on and off.
PBPCR is ignored in modes 1 to 6 and used only in mode 7.
Bit 7 6 5 4 3 2 1 0
PB7PON PB6PON PB5PON PB4PON PB3PON PB2PON PB1PON PB0PON
When a PBDDR bit is cleared to 0, if the corresponding PBPCR bit is set to 1, the built-in pull-up
transistor is turned on.
PBPCR is initialized to H'00 by a reset and in hardware standby mode. PBPCR is not initialized
Rev. 3.0, 02/99, page 239 of 904

Port B has one set of functions in modes 1, 3, 5, and 6, another set of functions in modes 2 and 4,
and another set of functions in mode 7. A description for each mode group is given next.
(1) Pin Functions in Modes 1, 3, 5, and 6: Port B is used for address output (A15 to A8). The
PBDDR settings are ignored. Figure 10-75 shows the pin functions in modes 1, 3, 5, and 6.
A15 (address bus)

A14 (address bus)
A13 (address bus)
A12 (address bus)
Port B
A11 (address bus)
A10 (address bus)
A9 (address bus)
A8 (address bus)
Figure 10-75 Pin Functions in Modes 1, 3, 5, and 6
(2) Pin Functions in Modes 2 and 4: Port B can be used for address output (A15 to A8) or
general-purpose input. A pin is used for address output if the corresponding PBDDR bit is set to
1, and for general-purpose input if this bit is cleared to 0. Figure 10-76 shows the pin functions in
modes 2 and 4.
PB7 (input)/A15 (address bus)

Port B
Rev. 3.0, 02/99, page 240 of 904

(3) Pin Functions in Mode 7: Port B consists of general-purpose input/output pins. Input or
output can be selected separately for each pin. A pin becomes an output pin if the corresponding
PBDDR bit is set to 1 and an input pin if this bit is cleared to 0. Figure 10-77 shows the pin
functions in mode 7.
PB7 (input/output pin)

Port B
10.12.4 Built-In Pull-Up Transistors
Port B has built-in MOS pull-up transistors that can be controlled by software. To turn an input
pull-up transistor on, clear its PBDDR bit to 0 and set its PBPCR bit to 1. The input pull-up
transistors are turned off by a reset and in hardware standby mode. Table 10-57 summarizes the
states of the input pull-ups in each mode.
Table 10-57 Pull-Up Transistor States in Each Mode
Hardware Other Modes (Including

Mode Reset Standby Mode Software Standby Mode)
1-6 Off Off Off
7 On/Off
Rev. 3.0, 02/99, page 241 of 904

10.12.5 Port B Read/Write Operations
PBDR and PBDDR have different read/write functions depending on whether port B is used for
address output (A15 to A8) or general-purpose input or output. The operating states and functions
of port B are described next.
B data register (PBDR) have no effect on general-purpose input lines. When read, PBDR returns
Internal data bus
Read
PB7-PB 0
Write
PBDR
Read Write
PBDR Pin value Don't care*
(2) Input Port with Internal Pull-Up (Mode 7): Figure 10-79 shows a block diagram illustrating
the general-purpose input function and built-in input pull-up transistors. Table 10-59 indicates
register read/write data. Values written in the port B data register (PBDR) have no effect on
general-purpose input lines. When read, PBDR returns the value at the pin. When a bit in the port
B pull-up transistor control register (PBPCR) is set to 1, the corresponding PBDR bit always reads
1.
Rev. 3.0, 02/99, page 242 of 904

Read/
Write
PBPCR
Internal data bus

Read
PB7-PB 0
Write
PBDR
Figure 10-79 Input Port with Built-In Pull-Up Transistors (Mode 7)
Read Write
1 2
PBDR Pin value, or always 1* Don't care*
1
PBPCR PBPCR value 0/1*
Note: 1. If set to 1, the corresponding PBDR bit always reads 1.
2. The register can be written to, but the value is not output at the pines.
output function. Table 10-60 indicates register read/write data. The value written in the port B
data register (PBDR) is output at the pin. When read, PBDR returns the value written in PBDR.
Internal data bus
PB7-PB 0
Read/
Write
PBDR
Read Write
PBDR PBDR value Value output at pin
Rev. 3.0, 02/99, page 243 of 904

(4) Address Bus (Modes 1 to 6): Figure 10-81 shows a block diagram illustrating the address-
bus function. Table 10-61 indicates register read/write data. When port B is used as an address
bus, values written in the port B data register (PBDR) have no effect on the bus lines. When read,
PBDR returns the value written in PBDR.
Address
Internal data bus

A15-A 8
Read/
Write
PBDR
Figure 10-81 Address Bus (Modes 1 to 6)
Read Write
PBDR PBDR value Don't care*
Rev. 3.0, 02/99, page 244 of 904

10.13 Port C
10.13.1 Overview
Port C is an-eight-bit input/output port. Figure 10-82 summarizes the pin functions.
Port C is an address bus (A7 to A0) in modes 1, 3, 5, and 6. In modes 2 and 4 port C can be used
for address output (A7 to A0) or general-purpose input. In mode 7 port C is a general-purpose
input/output port.
Pins in port C can drive one TTL load and a 90-pF capacitive load. They can also drive a
Darlington transistor pair. They have software-programmable built-in MOS pull-up transistors.
PC7 (input/output)/A7 (output)

Port C
Figure 10-82 Port C Pin Functions
Figure 10-83 shows examples of output loads for port C.
HD7404 etc.
Darlington pair
2 kΩ
H8/539F H8/539F
Port C HD74LS04 etc. Port C
Figure 10-83 Examples of Port C Output Loads
Rev. 3.0, 02/99, page 245 of 904

Table 10-62 summarizes the registers of port C.
Table 10-62 Port C Registers

H'FE95 Port C data direction register PCDDR W H'00
H'FE97 Port C data register PCDR R/W H'00
H'FE99 Port C pull-up transistor control register PCPCR R/W H'00
(1) Port C Data Direction Register: The port C data direction register (PCDDR) is an-eight-bit
Bit 7 6 5 4 3 2 1 0
PC7DDR PC6DDR PC5DDR PC4DDR PC3DDR PC2DDR PC1DDR PC0DDR
R/W W W W W W W W W
A pin in port C becomes an output pin if the corresponding PCDDR bit is set to 1, and an input pin
if this bit is cleared to 0. PCDDR is a write-only register. All bits always return the value 1 when
read.
PCDDR is initialized to H'00 by a reset and in hardware standby mode. PCDDR is not initialized
(2) Port C Data Register: The port C data register (PCDR) is an-eight-bit register that stores data
for pins PC7 to PC0.
Bit 7 6 5 4 3 2 1 0
PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0
When a bit in PCDDR is set to 1, the corresponding PCDR bit value is output at the corresponding
pin. If port C is read the value in PCDR is returned, regardless of the actual state of the pin.
When a bit in PCDDR is cleared to 0, it is possible to write to the corresponding PCDR bit but the
value is not output at the pin. If PCDR is read the value at the pin is returned, regardless of the
value written in PCDR.
Rev. 3.0, 02/99, page 246 of 904

PCDR is initialized to H'00 by a reset and in hardware standby mode. PCDR is not initialized in
(3) Port C Pull-Up Transistor Control Register: The port C pull-up transistor control register
(PCPCR) is an-eight-bit register that turns the MOS pull-up transistors of PC7 to PC0 on and off.
PCPCR is ignored in modes 1 to 6 and used only in mode 7.
Bit 7 6 5 4 3 2 1 0
PC7PON PC6PON PC5PON PC4PON PC3PON PC2PON PC1PON PC0PON
When a PCDDR bit is cleared to 0, if the corresponding PCPCR bit is set to 1, the built-in pull-up
transistor is turned on.
PCPCR is initialized to H'00 by a reset and in hardware standby mode. PCPCR is not initialized
Port C has one set of functions in modes 1, 3, 5, and 6, another set of functions in modes 2 and 4,
and another set of functions in mode 7. A description for each mode group is given next.
(1) Pin Functions in Modes 1, 3, 5, and 6: Port C is used for address output (A7 to A0). The
PCDDR settings are ignored. Figure 10-84 shows the pin functions in modes 1, 3, 5, and 6.
A7 (address bus)
A6 (address bus)
A5 (address bus)
A4 (address bus)
Port C
A3 (address bus)
A2 (address bus)
A1 (address bus)
A0 (address bus)
Figure 10-84 Pin Functions in Modes 1, 3, 5, and 6
Rev. 3.0, 02/99, page 247 of 904

(2) Pin Functions in Modes 2 and 4: Port C can be used for address output (A7 to A0) or general-
purpose input. A pin is used for address output if the corresponding PCDDR bit is set to 1, and for
general-purpose input if this bit is cleared to 0. Figure 10-85 shows the pin functions in modes 2
and 4.
PC7 (input)/A7 (address bus)

Port C
(3) Pin Functions in Mode 7: Port C consists of general-purpose input/output pins. Input or
output can be selected separately for each pin. A pin becomes an output pin if the corresponding
PCDDR bit is set to 1 and an input pin if this bit is cleared to 0. Figure 10-86 shows the pin
functions in mode 7.
PC7 (input/output pin)

Port C
Rev. 3.0, 02/99, page 248 of 904

10.13.4 Built-In MOS Pull-Up Transistors
Port C has built-in MOS pull-up transistors that can be controlled by software. To turn an input
pull-up transistor on, clear its PCDDR bit to 0 and set its PCPCR bit to 1. The input pull-up
transistors are turned off by a reset and in hardware standby mode. Table 10-63 summarizes the
states of the input pull-ups in each mode.
Table 10-63 Pull-Up Transistor States in Each Mode
Hardware Other Modes (Including

Mode Reset Standby Mode Software Standby Mode)
1-6 Off Off Off
7 On/Off
10.13.5 Port C Read/Write Operations
PCDR and PCDDR have different read/write functions depending on whether port C is used for
address output (A7 to A0) or general-purpose input or output. The operating states and functions of
port C are described next.
C data register (PCDR) have no effect on general-purpose input lines. When read, PCDR returns
Internal data bus
Read
PC7-PC 0
Write
PCDR
Read Write
PCDR Pin value Don't care*
Rev. 3.0, 02/99, page 249 of 904

(2) Input Port with Internal Pull-Up (Mode 7): Figure 10-88 shows a block diagram illustrating
the general-purpose input function of port C using the built-in input pull-up transistors. Table 10-
65 indicates register read/write data. Values written in the port C data register (PCDR) have no
effect on general-purpose input lines. When read, PCDR returns the value at the pin. When a bit
in the port C pull-up transistor control register (PCPCR) is set to 1, the corresponding PCDR bit
always reads 1.
Read/
Write
PCPCR
Internal data bus
Read
PC7-PC 0
Write
PCDR
Figure 10-88 Input Port with Built-In Pull-Up Transistors (Mode 7)
Read Write
1 2
PCDR Pin value, or always 1* Don't care*
1
PCPCR PCPCR value 0/1*
Note: 1. If set to 1, the corresponding PCDR bit always reads 1.
2. The register can be written to, but the value is not output at the pines.
output function. Table 10-66 indicates register read/write data. The value written in the port C
data register (PCDR) is output at the pin. When read, PCDR returns the value written in PCDR.
Internal data bus
PC7-PC 0
Read/
Write
PCDR

Rev. 3.0, 02/99, page 250 of 904
Read Write
PCDR PCDR value Value output at pin
(4) Address Bus (Modes 1 to 6): Figure 10-90 shows a block diagram illustrating the address-
bus function. Table 10-67 indicates register read/write data. When port C is used as an address
bus, values written in the port C data register (PCDR) have no effect on the bus lines. When read,
PCDR returns the value written in PCDR.
Address
Internal data bus
A7-A 0
Read/
Write
PCDR
Figure 10-90 Address Bus (Modes 1 to 6)
Read Write
PCDR PCDR value Don't care*
Rev. 3.0, 02/99, page 251 of 904

Section 11 16-Bit Integrated-Timer Pulse Unit
11.1 Overview
The built-in 16-bit integrated-timer pulse unit (IPU) has seven channels and three types of timers.
The IPU can output 28 independent waveforms, or output 12 waveforms and process 16 pulse
inputs or outputs. It can also provide six-phase PWM output, automatically measure pulse widths
and periods, count input from a two-phase encoder, and start the A/D converter.
11.1.1 Features
The IPU features are listed below.
• Twelve waveform outputs and sixteen pulse inputs or outputs

• Sixteen registers with software-assignable output compare or input capture functions
• Twenty-eight independent comparators
Channel Output Compare Registers Output Compare/Input Capture Registers

CH1 4 4
CH2–5 2 2
CH6, 7 — 2
• Selection of sixteen counter clock sources (external clock sources are shared by all channels):
φ, φ/2, φ/4, φ/8, φ/16, φ/32, φ/64, φ/128, φ/256, φ/512, φ/1024, φ/2048, φ/4096, TCLK1,
TCLK2, TCLK3
• Input capture function
Rising edge, falling edge, or both edges
• Pulse output
One-shot, toggle, or PWM output
• Counter synchronization function
Software can write to two or more timer counters simultaneously. Counters can be cleared
simultaneously by compare match or input capture.
• PWM output mode
One-phase, two-phase, or three-phase PWM output (up to nine-phase PWM output using the
counter synchronization function)
• Auto-measure function
Two timer channels can be coordinated for automatic measurement of pulse width or
frequency and for two-phase encoder counting
Rev. 3.0, 02/99, page 253 of 904

• Thirty-five interrupt sources
16 compare match/input capture interrupts, 12 compare match interrupts, and 7 overflow
interrupts: total 35 sources. The compare match/input capture interrupts and overflow
interrupts are independently vectored. The compare match interrupts have one interrupt vector
per two interrupt sources. The compare match/input capture interrupts and compare match
interrupts can start the data transfer controller (DTC) to transfer data.
11.1.2 Block Diagram
Figure 11-1 shows a block diagram of the IPU.
T1IMI1 to T7IMI2, T1CMI1 to

TCLK1Ð3 Clock selector Interrupt control T5CMI2, T1OVI to T7OVI
φ−φ/4096 (interrupt signals)
T1OC1−T5OC2 Counter control and pulse ADTRG
T1IOC1−T7IOC2 I/O control unit
16-bit timer
CH1
CH4
CH5
CH7
CH2
CH3
CH6
TMDRA
Bus interface
TMDRB On-chip
data bus
TSTR
Module data bus
TMDRA: Timer mode register A (8 bits)

TMDRB: Timer mode register B (8 bits)
TSTR: Timer start register (8 bits)
Figure 11-1 IPU Block Diagram
Rev. 3.0, 02/99, page 254 of 904

11.1.3 Input/Output Pins
Table 11-1 summarizes the IPU pins.
Table 11-1 IPU Pins
Channel Pin Name Input/Output Function

1 T1IOC1 Input/Output T1GR1 output compare/input capture pin
(multiplexed with PWM output)
T1IOC2 Input/Output T1GR2 output compare/input capture pin
T1OC1 Output T1DR1 output compare pin (multiplexed with PWM
output)
T1OC2 Output T1DR2 output compare pin
Rev. 3.0, 02/99, page 255 of 904

Table 11-1 IPU Pins (cont)
Channel Pin Name Input/Output Function

External TCLK1 Input External clock 1 input pin (A phase input for phase
clock measurement mode)
TCLK2 Input External clock 2 input pin (B phase input for phase
measurement mode)
TCLK3 Input External clock 3
11.2 Timer Counters and Compare/Capture Registers

The IPU has seven 16-bit timer counters (TCNTs), one for each channel. Each counter can be
accessed 16 bits at a time.
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TCNT
Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Each of the seven channels has 16-bit capture and compare registers. A capture register latches
the TCNT value when an external capture signal is received or an event occurs. An interrupt can
also be requested at this time compare register contents are compared with the TCNT value at all
times, and a compare match signal and/or interrupt is generated when the two match. The
configuration of each channel will be described next.
Rev. 3.0, 02/99, page 256 of 904

11.3 Channel 1 Registers
Channel 1 has four general registers used for both input capture and output compare, and four
dedicated registers used only for output compare.
The input capture/output compare registers function as output compare registers after a reset.
They can be switched over to input capture by setting bits IEG41 to IEG10 in the timer control
registers.
Channel 1 can simultaneously generate a maximum of eight waveforms, or can simultaneously

generate four waveforms and measure four waveforms. Three-phase PWM output is possible in
PWM mode. See section 11.8, "Examples of Timer Operation" for details.
Figure 11-2 shows a block diagram of channel 1.
TCLK1 −TCLK3
φ−φ/4096
T1OC1-T1OC 4
Clock selector Control logic T1IOC1-T1IOC 4
Comparator
Control registers
TCRH TCRL
TSRAH TSRAL
GR1 (ICR/OCR)
GR2 (ICR/OCR)
GR3 (ICR/OCR)
GR4 (ICR/OCR)
Bus interface
16-bit counter
DR1 (OCR)
DR2 (OCR)
DR3 (OCR)
DR4 (OCR)
TOERA On-chip
data bus
TCRA
TSRBH TSRBL
TOERB
Module data bus
GR1 to GR4: Input capture/output compare registers (16 bits × 4)

DR1 to DR4: Output compare registers (16 bits × 4)
TCRH and TCRL: Timer control register (8 bits × 2)
TSRAH and TSRAL: Timer status register A (8 bits × 2)
TCRA: Timer control register A (8 bits)
TSRBH and TSRBL: Timer status register B (8 bits × 2)
TOERA: Timer output enable register A (8 bits)
TOERB: Timer output enable register B (8 bits)
Figure 11-2 Channel 1 Block Diagram
Rev. 3.0, 02/99, page 257 of 904

Table 11-2 summarizes the channel 1 registers.
Table 11-2 Channel 1 Registers

Chan- Address Name Abbre- R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Initial
nel viation Value
1 H'FF20 Timer control T1CRH R/W — — CKEG1 CKEG0 TPSC3 TPSC2 TPSC1 TPSC0 H'C0
register (high)
H'FF21 Timer control T1CRL R/W — CCLR2 CCLR1 CCLR0 IEG21 IEG20 IEG11 IEG10 H'80
register (low)
H'FF22 Timer status T1SRAH R/W — — — OVIE CMIE2 CMIE1 IMIE2 IMIE1 H'E0
register A (high)
H'FF23 Timer status T1SRAL R/W — — — OVF CMF2 CMF1 IMF2 IMF1 H'E0
register A (low)
H'FF24 Timer output T1OERA R/W DOE21 DOE20 DOE11 DOE10 GOE21 GOE20 GOE11 GOE10 H'00
enable register A
H'FF25 Timer mode TMDRA R/W MD6·7 MD4·7 MD3·5 MD2·6 SYNC3 SYNC2 SYNC1 SYNC0 H'00
register A
H'FF26 Timer counter T1CNTH R/W H'00
register (high)
H'FF27 Timer counter T1CNTL R/W H'00
register (low)
H'FF28 General T1GR1H R/W H'FF
register 1 (high)
H'FF29 General T1GR1L R/W H'FF
register 1 (low)
H'FF2A General T1GR2H R/W H'FF
register 2 (high)
H'FF2B General T1GR2L R/W H'FF
register 2 (low)
H'FF2C Dedicated T1DR1H R/W H'FF
register 1 (high)
H'FF2D Dedicated T1DR1L R/W H'FF
register 1 (low)
H'FF2E Dedicated T1DR2H R/W H'FF
register 2 (high)
H'FF2F Dedicated T1DR2L R/W H'FF
register 2 (low)
H'FF30 Timer start TSTR R/W — STR7 STR6 STR5 STR4 STR3 STR2 STR1 H'80
register
H'FF31 Timer control T1CRA R/W — — — — IEG41 IEG40 IEG31 IEG30 H'F0
register A
Rev. 3.0, 02/99, page 258 of 904

Table 11-2 Channel 1 Registers (cont)
Chan- Address Name Abbre- R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Initial
nel viation Value
H'FF32 Timer status T1SRBH R/W — — — — CMIE4 CMIE3 IMIE4 IMIE3 H'F0
register B (high)
H'FF33 Timer status T1SRBL R/W — — — — CMF4 CMF3 IMF4 IMF3 H'F0
register B (low)
H'FF34 Timer output T1OERB R/W DOE41 DOE40 DOE31 DOE30 GOE41 GOE40 GOE31 GOE30 H'00
enable register B
H'FF35 Timer mode TMDRB R/W — — MDF PWM4 PWM3 PWM2 PWM1 PWM0 H'C0
register B
register 3 (high)
register 3 (low)
register 4 (high)
register 4 (low)
register 3 (high)
register 3 (low)
register 4 (high)
register 4 (low)
Rev. 3.0, 02/99, page 259 of 904

11.3.2 Timer Control Register (High)
Timer control register high (TCRH) is an eight-bit readable/writable register that selects the timer
clock source. Each channel has one TCRH. The bit structure of TCRH in channel 1 is shown
next.
Bit 7 6 5 4 3 2 1 0
TCRH − − CKEG1 CKEG0 TPSC3 TPSC2 TPSC1 TPSC0
R/W R R R/W R/W R/W R/W R/W R/W
Timer prescaler 3−0

These bits select the
clock source
Clock edge 1/0

These bits select the external clock edge
Reserved bits
Bits 7 and 6—Reserved: Read-only bits, always read as 1.
Bits 5 and 4—Clock Edge 1/0 (CKEG1/0): These bits select the external clock edge.
Bit 5 Bit 4
CKEG1 CKEG0 Description
0 0 Increment on rising edge (Initial value)
0 1 Increment on falling edge
1 0 Increment on both edges
1 1
CKEG1/0 can be set to increment the count on the rising edge, falling edge, or both edges of the
external clock. When TPSC3 to TPSC0 are set so as not to select an external clock source,
CKEG1 and CKEG0 are ignored.
For further details, see section 11.8.7, "External Event Counting."
Rev. 3.0, 02/99, page 260 of 904

(3) Bits 3 to 0—Timer Prescaler (TPSC3 to TPSC0): These bits select the clock source. One of
16 clock sources can be selected, as listed next.
Bit 3 Bit 2 Bit 1 Bit 0

TPSC3 TPSC2 TPSC1 TPSC0 Description
0 0 0 0 φ (100 ns)* (Initial value)
0 0 0 1 φ/2 (200 ns)*
0 0 1 0 φ/4 (400 ns)*
0 0 1 1 φ/8 (800 ns)*
0 1 0 0 φ/16 (1.6 µs)*
0 1 0 1 φ/32 (3.2 µs)*
0 1 1 0 φ/64 (6.4 µs)*
0 1 1 1 φ/128 (12.8 µs)*
1 0 0 0 φ/256 (25.6 µs)*
1 0 0 1 φ/512 (51.2 µs)*
1 0 1 0 φ/1024 (102.4 µs)*
1 0 1 1 φ/2048 (204.8 µs)*
1 1 0 0 φ/4096 (409.6 µs)*
1 1 0 1 External clock (TCLK1)
Note: * Values in parentheses are resolution values for a 10-MHz clock rate.
Rev. 3.0, 02/99, page 261 of 904

11.3.3 Timer Control Register (Low)
Timer control register low (TCRL) is an eight-bit readable/writable register that selects input
capture edges, and selects the timer counter clear source.
Channel 1 has two timer control registers (low), designated TCRL and TCRA. The bit structure of
TCRL in channel 1 is shown next.
Bit 7 6 5 4 3 2 1 0
TCRL − CCLR2 CCLR1 CCLR0 IEG21 IEG20 IEG11 IEG10
Input capture edge 21/20/11/10

These bits select register
functions and the valid edges
of input capture signals
Counter clear 2−0

These bits select the counter clear source
Reserved bit
Bit 7 —Reserved: Read-only bit, always read as 1.
Rev. 3.0, 02/99, page 262 of 904

Bits 6 to 4—Counter Clear 2 to 0 (CCLR2/1/0): These bits select the counter clear source.
Bit 6 Bit 5 Bit 4

CCLR2 CCLR1 CCLR0 Description
0 0 0 Counter not cleared (Initial value)
0 0 1 Synchronized counter clearing enabled
0 1 0
0 1 1
1 0 0 Counter cleared on GR1 compare match or capture
1 0 1 Counter cleared on DR2 compare match
1 1 0 Counter cleared on GR3 compare match or capture
1 1 1 Counter cleared on DR4 compare match
When CCLR2 is 0 and either CCLR1 or CCLR0 is set to 1, or both CCLR1 and CCLR0 are set to
1, the counter is cleared in synchronization with the clearing of a timer pair selected in timer mode
register A (TMDA).
If GR1 or GR3 is used as a compare register the counter is cleared by compare match. If GR1 or
GR3 is used as a capture register the counter is cleared by input capture.
For further details, see section 11.8.4, "Counter Clearing Function" and section 11.8.6,
"Synchronizing Mode. "
Bits 3 and 2—Input Capture Edge 21/20 (IEG21/20): These bits select the function of GR2 and
the valid edge of the input capture signal.
Bit 3 Bit 2
IEG21 IEG20 Description
0 0 GR2 is not used for input capture (Initial value) *
0 1 Capture in GR2 on rising edge of input capture signal
1 0 Capture in GR2 on falling edge of input capture signal
1 1 Capture in GR2 on both edges of input capture signal
Note: * GR2 becomes an output compare register.
A reset clears bits IEG21 and IEG20 to 0, disabling input capture and making GR2 an output
compare register. If IEG21 or IEG20 is set to 1, or both IEG21 and IEG20 are set to 1, GR2
becomes an input capture register.
For further details, see section 11.8.3, "Input Capture Function. "
Rev. 3.0, 02/99, page 263 of 904

Bit 1 Bit 0
0 0 GR1 is not used for input capture (Initial value)*
TCRA is an eight-bit readable/writable register. The bit structure of TCRA in channel 1 is shown
next.
Bit 7 6 5 4 3 2 1 0
TCRA − − − − IEG41 IEG40 IEG31 IEG30
R/W − − − − R/W R/W R/W R/W

These bits select register functions
and the valid edges of input capture
signals
Reserved bits
Bits 7 to 4 —Reserved: Read-only bits, always read as 1.
Rev. 3.0, 02/99, page 264 of 904

Bit 3 Bit 2
Bit 1 Bit 0
Rev. 3.0, 02/99, page 265 of 904

11.3.4 Timer Status Register (High)
Timer status register high (TSRH) is an eight-bit readable/writable register that enables and
disables timer interrupts.
After OVIE, CMIE2, CMIE1, IMIE2, or IMIE1 is set to 1 in TSRH, an interrupt is requested
when OVF, CMF2, CMFI, IMF2, or IMF1 is set to 1 in TSRL.
Channel 1 has two timer status registers (high), designated TSRAH and TSRBH. Channels 2 to 7
have one TSRH each. The bit structure of TSRAH in channel 1 is shown next.
Bit 7 6 5 4 3 2 1 0
TSRAH − − − OVIE CMIE2 CMIE1 IMIE2 IMIE1
Input capture/
Compare match
interrupt enable
2/1
These bits enable
and disable GR2
and GR1 compare
match and input
capture interrupts
Compare match interrupt enable 2/1

These bits enable and disable DR2
and DR1 compare match interrupts
Overflow interrupt enable

Enables or disables counter overflow
Reserved bits interrupts
Rev. 3.0, 02/99, page 266 of 904

Bit 4—Overflow Interrupt Enable (OVIE): Enables or disables the counter overflow interrupt.
For further details, see section 11.9.1, "Interrupt Timing. "
Bit 4
OVIE Description
0 Counter overflow interrupt is disabled (Initial value)
1 Counter overflow interrupt is enabled
Bit 3—Compare Match Interrupt Enable 2 (CMIE2): Enables or disables the DR2 compare
match interrupt. For further details, see section 11.9.1, "Interrupt Timing. "
Bit 3
CMIE2 Description
0 DR2 compare match interrupt is disabled (Initial value)
1 DR2 compare match interrupt is enabled
Bit 2
CMIE1 Description
Bit 1—Input Capture/Compare Match Interrupt Enable 2 (IMIE2): Enables or disables the
GR2 compare match or input capture interrupt. For further details, see section 11.9.1, "Interrupt
Timing. "
Bit 1
IMIE2 Description
0 GR2 compare match or input capture interrupt is disabled (Initial value)
1 GR2 compare match or input capture interrupt is enabled
Rev. 3.0, 02/99, page 267 of 904

Timing. "
Bit 0
IMIE1 Description
TSRBH is an eight-bit readable/writable register. The bit structure of TSRBH in channel 1 is

shown next.
Bit 7 6 5 4 3 2 1 0
TSRBH − − − − CMIE4 CMIE3 IMIE4 IMIE3
R/W − − − − R/W R/W R/W R/W
Input capture/
Compare match
interrupt enable
4/3
These bits enable
and disable GR4
and GR3 compare
match and input
capture interrupts

Reserved bits
Rev. 3.0, 02/99, page 268 of 904

Bit 3
CMIE4 Description
Bit 2
CMIE3 Description
Timing. "
Bit 1
IMIE4 Description
Timing. "
Bit 0
IMIE3 Description
Rev. 3.0, 02/99, page 269 of 904

11.3.5 Timer Status Register (Low)
Timer status register low (TSRL) is an eight-bit readable/writable register that indicates timer
status. Writing to TSRL is restricted to clearing a flag to 0 after reading the 1 value of that flag.
After OVIE, CMIE2, CMIE1, IMIE2, or IMIE1 is set to 1 in TSRH, an interrupt is requested
when OVF, CMF2, CMF1, IMF2, or IMF1 is set to 1 in TSRL.
Channel 1 has two timer status registers (low), designated TSRAL and TSRBL. Channels 2 to 7
have one TSRL each. The bit structure of TSRAL in channel 1 is shown next.
Bit 7 6 5 4 3 2 1 0
TSRAL − − − OVF CMF2 CMF1 IMF2 IMF1
Input capture/
Compare match
flag 2/1
Flags indicating
GR2 and GR1
compare match
or input capture
Compare match flag 2/1

Flags indicating DR2 and DR1
compare match
Overflow flag
Flag indicating counter overflow
Reserved bits
Rev. 3.0, 02/99, page 270 of 904

Bit 4—Overflow Flag (OVF): Set to 1 when the counter overflows from H'FFFF to H'0000. For
further details, see section 11.9.1, "Interrupt Timing. "
Bit 4
OVF Description
0 Cleared by reading OVF after OVF is set to 1, then writing 0 in OVF
(Initial value)
1 Set when counter overflow occurs
Bit 3—Compare Match Flag 2 (CMF2): Set to 1 when the counter value matches the DR2
value. For further details, see section 11.9.1, "Interrupt Timing. "
Bit 3
CMF2 Description
0 1. Cleared by reading CMF2 after CMF2 is set to 1, then writing 0 in CMF2
(Initial value)
2. Cleared when the DTC is activated by a CMI2 interrupt
1 Set when DR2 compare match occurs
Bit 2
CMF1 Description
(Initial value)
Rev. 3.0, 02/99, page 271 of 904

Bit 1—Input Capture/Compare Match Flag 2 (IMF2): Set to 1 when the counter value matches
the GR2 value, or the counter value is captured in GR2. For further details, see section 11.9.1,
"Interrupt Timing. "
Bit 1
IMF2 Description
0 1. Cleared by reading IMF2 after IMF2 is set to 1, then writing 0 in IMF2
(Initial value)
2. Cleared when the DTC is activated by an IMI2 interrupt
1 Set when GR2 input capture or compare match occurs
Bit 0
IMF1 Description
(Initial value)
Rev. 3.0, 02/99, page 272 of 904

TSRBL is an eight-bit readable/writable register. The bit structure of TSRBL in channel 1 is
shown next.
Bit 7 6 5 4 3 2 1 0
TSRBL − − − − CMF4 CMF3 IMF4 IMF3
R/W − − − − R/W R/W R/W R/W
Input capture/
Compare match
flag 4/3
Flags indicating
GR4 and GR3
compare match
or input capture

compare match
Reserved bits
Bit 3
CMF4 Description
(Initial value)
Rev. 3.0, 02/99, page 273 of 904

Bit 2
CMF3 Description
(Initial value)
Bit 1
IMF4 Description
(Initial value)
Bit 0
IMF3 Description
(Initial value)
Rev. 3.0, 02/99, page 274 of 904

11.3.6 Timer Output Enable Register
The timer output enable register (TOER) is an eight-bit readable/writable register that enables or
disables output of compare match signals and selects the output level.
Channel 1 has two timer output enable registers, designated TOERA and TOERB. Channels 2 to
7 have one TOER each. The bit structure of TOERA in channel 1 is shown next.
For the selection of general register (GR) functions, see section 11.3.3, "Timer Control Register
(Low). "
Bit 7 6 5 4 3 2 1 0
TOERA DOE21 DOE20 DOE11 DOE10 GOE21 GOE20 GOE11 GOE10
General register
General register output enable
Dedicated output enable 11/10
Dedicated
register output 21/20 These bits enable
register output and disable output
enable 11/10 These bits enable
enable 21/20 of the counter-GR1
These bits enable and disable output
These bits enable and disable output of the counter-GR2 compare match
and disable output of the counter-DR1 signal, and select
compare match
of the counter-DR2 compare match the output level
signal, and select
compare match signal, and select the output level
signal, and select the output level
the output level
Rev. 3.0, 02/99, page 275 of 904

Bits 7 and 6—Dedicated Register Output Enable 21/20 (DOE21/20): These bits enable and
disable output of the counter-DR2 compare match signal, and select the output level. For further
details, see section 11.8.2, "Selection of Output Level. "
Bit 7 Bit 6
DOE21 DOE20 Description
0 0 Compare match signal output is disabled (Initial value)
0 1 Output 0 on compare match
1 1
Bit 5 Bit 4
1 1
Bits 3 and 2—General Register Output Enable 21/20 (GOE21/20): These bits enable and
disable output of the counter-GR2 compare match signal, and select the output level.
Bit 3 Bit 2
GOE21 GOE20 Description
1 1
When GR2 is used for input capture, however, compare match signal output is disabled regardless
of the setting of GOE21 and GOE20. Bits 3 and 2 are thus ignored except when IEG21 =
IEG20 = 0.
For further details, see section 11.8.2, "Selection of Output Level. "
Rev. 3.0, 02/99, page 276 of 904

Bit 1 Bit 0
1 1
IEG10 = 0.
TOERB is an eight-bit readable/writable register. The bit structure of TOERB in channel 1 is

shown next.
(Low). "
Bit 7 6 5 4 3 2 1 0
TOERB DOE41 DOE40 DOE31 DOE30 GOE41 GOE40 GOE31 GOE30

General register
output enable
General register 31/30
output enable These bits enable
Dedicated
41/40 and disable output
register output
Dedicated enable 31/30 These bits enable of the counter-GR3
register output and disable output compare match
These bits enable
enable 41/40 of the counter-GR4 signal, and select
and disable output the output level
These bits enable compare match
of the counter-DR3
and disable output signal, and select
compare match
of the counter-DR4 the output level
signal, and select
compare match the output level
signal, and select
the output level
Rev. 3.0, 02/99, page 277 of 904

Bit 7 Bit 6
1 1
Bit 5 Bit 4
1 1
Bit 3 Bit 2
1 1
IEG40 = 0.
Rev. 3.0, 02/99, page 278 of 904

Bit 1 Bit 0
1 1
IEG30 = 0.
Rev. 3.0, 02/99, page 279 of 904

11.4 Channel 2 to 5 Registers
Channels 2 to 5 each have two general registers used for output compare and input capture, and
two dedicated registers used only for output compare.
The general registers function as output compare registers after a reset. They can be switched over
to input capture by setting bits IEG21 to IEG10 in the timer control registers.
Each of channels 2 to 5 can simultaneously generate a maximum of four waveforms, or can

simultaneously generate two waveforms and measure two waveforms. In programmed periodic
counting mode, channels 2 to 4 are used for setting the measurement period, and channel 5 is used
to measure the waveform. Channels 2 and 3 can provide two-phase PWM output. See section
11.8, "Examples of Timer Operation" for details.
Figure 11-3 shows a block diagram of channels 2 to 5.
TCLK1 −TCLK3
φ−φ/4096
T2OC1−T2OC2
Clock selector Control logic
T2IOC1−T2IOC2
Comparator
Control registers
Bus interface
TCRH* TCRL
GR1 (ICR/OCR)
GR2 (ICR/OCR)
16-bit counter
On-chip
DR2 (OCR)
DR1 (OCR)
TSRH TSRL
data bus
TOER
Module data bus

Note: The diagram shows 16-bit timer channel 2.
GR1 and GR2: Output compare/input capture registers (16 bits × 2)

DR1 and DR2: Output compare registers (16 bits × 2)
TCRH and TCRL: Timer control registers (8 bits × 2)
TSRH and TSRL: Timer status registers (8 bits × 2)
TOER: Timer output enable register (8 bits)
Note: * For TCRH, see section 11.3.2, "Timer Control Register (High)."
Figure 11-3 Block Diagram of Channels 2 to 5

Rev. 3.0, 02/99, page 280 of 904
Table 11-3 summarizes the registers of channels 2 and 3.
Table 11-3 Registers of Channels 2 and 3

Chan- Abbre- Initial
nel Address Name viation R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value
register (high)
H'FF41 Timer control T2CRL R/W — — CCLR1 CCLR0 IEG21 IEG20 IEG11 IEG10 H'C0
register (low)
H'FF42 Timer status T2SRH R/W — — — OVIE CMIE2 CMIE1 IMIE2 IMIE1 H'E0
register (high)
H'FF43 Timer status T2SRL R/W — — — OVF CMF2 CMF1 IMF2 IMF1 H'E0
register (low)
H'FF44 Timer output T2OER R/W DOE21 DOE20 DOE11 DOE10 GOE21 GOE20 GOE11 GOE10 H'00
enable register
register (high)
register (low)
register 1 (high)
register 1 (low)
register 2 (high)
H'FF4B Genera T2GR2L R/W H'FF
register 2 (low)l
register 1 (high)
register 1 (low)
register 2 (high)
register 2 (low)
Rev. 3.0, 02/99, page 281 of 904

Table 11-3 Registers of Channels 2 and 3 (cont)
register (high)
register (low)
register (high)
register (low)
enable register
register (high)
register (low)
register 1 (high)
register 1 (low)
register 2 (high)
register 2 (low)
register 1 (high)
register 1 (low)
register 2 (high)
register 2 (low)
Rev. 3.0, 02/99, page 282 of 904


register (high)
register (low)
register (high)
register (low)
enable register
register (high)
register (low)
register 1 (high)
register 1 (low)
register 2 (high)
register 2 (low)
register 1 (high)
register 1 (low)
register 2 (high)
register 2 (low)
Rev. 3.0, 02/99, page 283 of 904

register (high)
register (low)
register (high)
register (low)
enable register
register (high)
register (low)
register 1 (high)
register 1 (low)
register 2 (high)
register 2 (low)
register 1 (high)
register 1 (low)
register 2 (high)
register 2 (low)
Rev. 3.0, 02/99, page 284 of 904

11.4.2 Timer Control Register (Low)
Timer control register low (TCRL) is an eight-bit readable/writable register. For timer control
register high (TCRH), see section 11.3.2, "Timer Control Register (High)." The bit structure of
TCRL in channels 2 to 5 is shown next.
Bit 7 6 5 4 3 2 1 0
TCRL − − CCLR1 CCLR0 IEG21 IEG20 IEG11 IEG10

These bits select register
functions and the valid edges
of input capture signals
Counter clear 1/0

These bits select the counter clear source
Reserved bits
Bits 7 and 6 —Reserved: Read-only bits, always read as 1.
Bits 5 and 4—Counter Clear 1 and 0 (CCLR1/0): These bits select the counter clear source.
Bit 5 Bit 4
CCLR1 CCLR0 Description
0 0 Counter not cleared (Initial value)
0 1 Counter cleared on GR1 compare match or capture
1 0 Counter cleared on DR2 compare match*
1 1 Synchronous clearing of counter enabled
Note: * In channels 6 and 7 the counter is cleared on GR2 compare match or capture.
When CCLR1 = CCLR0 = 1, the counter is cleared in synchronization with the clearing of the
paired timer selected in timer mode register A.
If GR1 is used as a compare register the counter is cleared by compare match. If GR1 is used as a
capture register the counter is cleared by input capture.
Rev. 3.0, 02/99, page 285 of 904

For further details, see section 11.8.4, "Counter Clearing Function" and section 11.8.6,
"Synchronizing Mode. "
Bit 3 Bit 2
Bit 1 Bit 0
0 1 Capture in GR1 on s rising edge of input capture signal
Rev. 3.0, 02/99, page 286 of 904

Timer status register high (TSRH) is an eight-bit readable/writable register. After OVIE, CMIE2,
CMIE1, IMIE2, or IMIE1 is set to 1 in TSRH, an interrupt is requested when OVF, CMF2, CMF1,
IMF2, or IMF1 is set to 1 in TSRL. The bit structure of TSRH in channels 2 to 5 is shown next.
Bit 7 6 5 4 3 2 1 0
TSRH − − − OVIE CMIE2 CMIE1 IMIE2 IMIE1
Input capture/
Compare match
interrupt enable
2/1
These bits enable
and disable GR2
and GR1 compare
match and input
capture interrupts


Enables or disables counter overflow
Reserved bits interrupts
Bit 4
OVIE Description
Rev. 3.0, 02/99, page 287 of 904

Bit 3
CMIE2 Description
match interrupt. For further details, see section 11.9.1, "Interrupt Timing."
Bit 2
CMIE1 Description
Timing.""
Bit 1
IMIE2 Description
0 GR2 input capture or compare match interrupt is disabled (Initial value)
1 GR2 input capture or compare match interrupt is enabled
Timing.""
Bit 0
IMIE1 Description
Rev. 3.0, 02/99, page 288 of 904

Timer status register low (TSRL) is an eight-bit readable/writable register. After OVIE, CMIE2,
CMIE1, IMIE2, or IMIE1 is set to 1 in TSRH, an interrupt is requested when OVF, CMF2, CMF1,
IMF2, or IMF1 is set to 1 in TSRL. Writing to TSRL is restricted to clearing a flag to 0 after
reading the 1 value of that flag. The bit structure of TSRL in channels 2 to 5 is shown next.
Bit 7 6 5 4 3 2 1 0
TSRL − − − OVF CMF2 CMF1 IMF2 IMF1
Input capture/
Compare match
flag 2/1
Flags indicating
GR2 and GR1
compare match
or input capture

compare match
Overflow flag
Flag indicating counter overflow
Reserved bits
Bit 4—Overflow Flag (OVF): Set to 1 when the counter overflows from H'FFFF to H'0000. For
further details, see section 11.9.1, "Interrupt Timing. "
Bit 4
OVF Description
(Initial value)
Rev. 3.0, 02/99, page 289 of 904

value. For further details, see section 11.9.1, "Interrupt Timing."
Bit 3
CMF2 Description
(Initial value)
Bit 2
CMF1 Description
(Initial value)
Bit 1
IMF2 Description
(Initial value)
Rev. 3.0, 02/99, page 290 of 904

Bit 0
IMF1 Description
(Initial value)
The timer output enable register (TOER) is an eight-bit readable/writable register. The bit
structure of TOER in channels 2 to 5 is shown next.
(Low). "
Bit 7 6 5 4 3 2 1 0
TOER DOE21 DOE20 DOE11 DOE10 GOE21 GOE20 GOE11 GOE10
General register
output enable
General register 11/10
output enable These bits enable
Dedicated 21/20 and disable output
These bits enable of the counter-GR1
register output
enable 11/10 and disable output compare match
Dedicated
These bits enable of the counter-GR2 signal, and select
register output compare match the output level
enable 21/20 and disable output
of the counter-DR1 signal, and select
These bits enable the output level
compare match
and disable output
signal, and select
of the counter-DR2
the output level
compare match
signal, and select
the output level
Rev. 3.0, 02/99, page 291 of 904

Bit 7 Bit 6
1 1 Toggle on compare match*
Note: * Channels 2 and 3 do not have an output toggle function. If these bits are set to 11, the
output goes to 1 on compare match.
Bit 5 Bit 4
output goes to 1 on compare match.
Bit 3 Bit 2
timer outputs 1 on compare match.
Rev. 3.0, 02/99, page 292 of 904

of the setting of GOE21 and GOE20. Bits 3 and 2 are thus ignored except when IEG21 = IEG20 =
0.
Bit 1 Bit 0
1 1 Toggle on compare match *
timer outputs 1 on compare match.
IEG10 = 0.
Rev. 3.0, 02/99, page 293 of 904

11.5 Channel 6 and 7 Registers
Channels 6 and 7 each have two general registers used for output compare and input capture.
The general registers function as output compare registers after a reset. They can be switched over
to input capture by setting bits IEG21 to IEG10 in the timer control registers.
Each of channels 6 and 7 can simultaneously measure two waveforms and generate one waveform.
Channels 6 and 7 can each be used to measure waveforms in programmed periodic counting mode.
The timer counter in channel 7 can count up or down according to the phase of two external clock
signals in phase counting mode. Channels 6 and 7 can provide single-phase PWM output in PWM
output mode. See section 11.8, "Examples of Timer Operation" for details.
Figure 11-4 shows a block diagram of channels 6 and 7.
TCLK1 −TCLK3
φ−φ/4096
T6IOC1−T6IOC2
Clock selector Control logic
Comparator
Control registers Bus interface
TCRH*1 TCRL*2
GR1 (ICR/OCR)
GR2 (ICR/OCR)
16-bit counter
On-chip
TSRH TSRL
data bus
TOER
Module data bus
GR1 and GR2: Output compare/input capture registers (16 bits × 2)

TCRH and TCRL: Timer control registers (8 bits × 2)
TSRH and TSRL: Timer status registers (8 bits × 2)
TOER: Timer output enable register (8 bits)
Notes: The diagram shows 16-bit timer channel 6.
1. For TCRH, see section 11.3.2, "Timer Control Register (High)."
2. For TCRL, see section 11.4.2, "Timer Control Register (Low)"
Figure 11-4 Block Diagram of Channels 6 and 7

Rev. 3.0, 02/99, page 294 of 904

register (high)
register (low)
H'FF82 Timer status T6SRH R/W — — — — — OVIE IMIE2 IMIE1 H'F8
register (high)
H'FF83 Timer status T6SRL R/W — — — — — OVF IMF2 IMF1 H'F8
register (low)
H'FF84 Timer output T6OER R/W — — — — GOE21 GOE20 GOE11 GOE10 H'F0
enable register
register (high)
register (low)
register 1 (high)
register 1 (low)
register 2 (high)
register 2 (low)
Rev. 3.0, 02/99, page 295 of 904

register (high)
register (low)
H'FF92 Timer status T7SRH R/W — — — — — OVIE IMIE2 IMIE1 H'F8
register (high)
H'FF93 Timer status T7SRL R/W — — — — — OVF IMF2 IMF1 H'F8
register (low)
H'FF94 Timer output T7OER R/W — — — — GOE21 GOE20 GOE11 GOE10 H'F0
enable register
register (high)
register (low)
register 1 (high)
register 1 (low)
register 2 (high)
register 2 (low)
Rev. 3.0, 02/99, page 296 of 904

Timer status register high (TSRH) is an eight-bit readable/writable register. After OVIE, IMIE2,
or IMIE1 is set to 1 in TSRH, an interrupt is requested when OVF, IMF2, or IMF1 is set to 1 in
TSRL. For timer control register high and low, see section 11.3.2, "Timer Control Register (High)
" and section 11.4.2, "Timer Control Register (Low). " The bit structure of TSRH in channels 6
and 7 is shown next.
Bit 7 6 5 4 3 2 1 0
TSRH − − − − − OVIE IMIE2 IMIE1
R/W − − − − − R/W R/W R/W
Input capture/
Compare match
interrupt enable
2/1
These bits enable
and disable
compare match
and input capture
interrupts

Enables or disables counter
overflow interrupts
Reserved bits
Bit 2
OVIE Description
Rev. 3.0, 02/99, page 297 of 904

Timing. "
Bit 1
IMIE2 Description
Timing. "
Bit 0
IMIE1 Description
Rev. 3.0, 02/99, page 298 of 904

Timer status register low (TSRL) is an eight-bit readable/writable register. After OVIE, IMIE2, or
IMIE1 is set to 1 in TSRH, an interrupt is requested when OVF, IMF2, or IMF1 is set to 1 in
TSRL. Writing to TSRL is restricted to clearing a flag to 0 after reading the 1 value of that flag.
The bit structure of TSRL in channels 6 and 7 is shown next.
Bit 7 6 5 4 3 2 1 0
TSRL − − − − − OVF IMF2 IMF1
R/W − − − − − R/W R/W R/W
Input capture/
Compare match
interrupt enable
2/1
Flags indicating
GR2 and GR1
compare match
or input capture
Overflow flag
Flag indicating counter
overflow
Reserved bits
Bit 2—Overflow Flag (OVF): Set to 1 when the counter overflows from H'FFFF to H'0000 or
when the counter in channel 7 underflows from H'0000 to H'FFFF in phase counting mode. For
further details, see section 11.9.1, " Interrupt Timing," and section 11.8.9, " Phase counting
Mode."
Bit 2
OVF Description
(Initial value)
Rev. 3.0, 02/99, page 299 of 904

"Interrupt Timing."
Bit 1
IMF2 Description
(Initial value)
"Interrupt Timing."
Bit 0
IMF1 Description
(Initial value)
Rev. 3.0, 02/99, page 300 of 904

The timer output enable register (TOER) is an eight-bit readable/writable register. The bit
structure of TOER in channels 6 and 7 is shown next.
(Low)."
Bit 7 6 5 4 3 2 1 0
TOER − − − − GOE21 GOE20 GOE11 GOE10
R/W − − − − R/W R/W R/W R/W
General register
output enable
11/10
These bits enable
and disable output
of the counter-GR1
compare match
signal, and select
the output level
General register output enable

21/20
These bits enable and disable
output of the counter-GR2 compare
match signal, and select the output
level
Reserved bits
Rev. 3.0, 02/99, page 301 of 904

Bit 3 Bit 2
1 1
IEG20 = 0.
For further details, see section 11.8.2, "Selection of Output Level."
Bit 1 Bit 0
1 1
IEG10 = 0.
For further details, see section 11.8.2, "Selection of Output Level."
Rev. 3.0, 02/99, page 302 of 904

11.6 IPU Register Descriptions
11.6.1 Timer Mode Register A
Timer mode register A (TMDRA) is an eight-bit readable/writable register that selects timer
synchronizing and operating modes. The bit structure of TMDRA is shown next.
Bit 7 6 5 4 3 2 1 0
TMDRA MD6-7 MD4-7 MD3-5 MD2-6 SYNC3 SYNC2 SYNC1 SYNC0
Timer synchronizing bits 3-0

These bits synchronize
two timers
Timer mode 6-7, 4-7, 3-5, 2-6
These bits operate two timers
in programmed periodic counting mode
Bit 7—Timer Mode 6-7 (MD6-7): Operates channels 6 and 7 in programmed periodic counting
mode.
Bit 7
MD6-7 Description
0 Timers 6 and 7 operate normally (Initial value)
1 Timers 6 and 7 operate in programmed periodic counting mode
The counter value in channel 7 is captured in GR2 in channel 7 at intervals set in GR2 in channel
6. If channel 7 is externally clocked, the number of external events occurring in regular intervals
timed by channel 6 can be counted. For further details see section 11.8.8, "Programmed Periodic
Counting Mode."
Rev. 3.0, 02/99, page 303 of 904

mode.
Bit 6
MD4-7 Description
The counter value in channel 7 is captured in GR1 in channel 7 at intervals set in DR2 in channel
Counting Mode."
mode.
Bit 5
MD3-5 Description
Counting Mode."
mode.
Bit 4
DM2-6 Description
Counting Mode."
Rev. 3.0, 02/99, page 304 of 904

Bit 3—Timer Synchronizing Bit 3 (SYNC3): Synchronizes two timer channels.
Bit 3
SYNC3 Description
0 Timer counters in channels 6 and 7 operate independently (Initial value)
1 Timer counters in channels 6 and 7 are synchronized
When SYNC3 = 1, timer counters can be preset and cleared in synchronization. If two or more
bits among SYNC3, SYNC2, SYNC1, and SYNC0 are set to 1 simultaneously, all selected timer
counters are synchronized. For further details, see section 11.8.6 "Synchronizing Mode."
Bit 2
SYNC2 Description
Bit 1
SYNC1 Description
Bit 0—Timer Synchronizing Bit 0 (SYNC0): Synchronizes the timer counters in channel 1 and
other channels.
Bit 0
SYNC0 Description
0 Timer counters in channel 1 and other channels operate independently
(Initial value)
Rev. 3.0, 02/99, page 305 of 904

11.6.2 Timer Mode Register B
Timer mode register B (TMDRB) is an eight-bit readable/writable register that selects timer
operating modes. The bit structure of TMDRB is shown next.
Bit 7 6 5 4 3 2 1 0
TMDRB − − MDF PWM4 PWM3 PWM2 PWM1 PWM0
PWM timer mode 4-0

These bits operate
channels 7, 6, 3, 2,
and 1 as pulse-width
modulators
Phase counting mode

Operates channel 7 in phase counting mode
Reserved bits
Bit 5—Phase Counting Mode (MDF): Operates channel 7 in phase counting mode. For further
details see section 11.8.9, "Phase Counting Mode."
Bit 5
MDF Description
0 Channel 7 operates normally (Initial value)
Rev. 3.0, 02/99, page 306 of 904

Bit 4—PWM Timer Mode 4 (PWM4): Operates channel 7 as a PWM timer.
Bit 4
PWM4 Description
1 Channel 7 operates as a PWM timer
Channel 7 operates as a PWM timer with independent period and duty cycle, providing one PWM
output. When PWM4 = 1, settings of GOE11 and GOE10 in the channel 7 timer output enable
register (TOER) are ignored. For further details, see section 11.8.5 "PWM Output Mode."
Bit 3
PWM3 Description
Channel 6 operates as a PWM timer with independent period and duty cycle, providing one PWM
output. When PWM3 = 1, settings of GOE11 and GOE10 in the channel 6 timer output enable
register (TOER) are ignored. For further details, see section 11.8.5 "PWM Output Mode."
Bit 2
PWM2 Description
Channel 3 operates as a PWM timer with independent period and duty cycle. Channel 3 can
provide two-phase PWM output. When PWM2 = 1, settings of GOE21, GOE20, GOE11, and
GOE10 in the channel 3 timer output enable register (TOER) are ignored. For further details, see
section 11.8.5 "PWM Output Mode."
Rev. 3.0, 02/99, page 307 of 904

Bit 1
PWM1 Description
provide two-phase PWM output. When PWM1 = 1, settings of GOE21, GOE20, GOE11, and
GOE10 in the channel 2 timer output enable register (TOER) are ignored. For further details, see
section 11.8.5 "PWM Output Mode."
Bit 0
PWM0 Description
provide three-phase PWM output. When PWM0 = 1, settings of DOE11, DOE10, GOE21,
GOE20, GOE11, and GOE10 in the channel 1 timer output enable register (TOER) are ignored.
For further details, see section 11.8.5 "PWM Output Mode."
Rev. 3.0, 02/99, page 308 of 904

11.6.3 Timer Start Register
The timer start register (TSTR) is an eight-bit readable/writable register that starts and stops the
counters. The bit structure of TSTR is shown next.
Bit 7 6 5 4 3 2 1 0
TSTR − STR7 STR6 STR5 STR4 STR3 STR2 STR1
Counter start 7 to 1
These bits start and stop the
Reserved bit counters
Bit 7—Reserved: Read-only bit, always read as 1.
Bit 6—Counter Start 7 (STR7): Starts and stops the counter in channel 7.
Bit 6
STR7 Description
0 Timer counter 7 is halted (Initial value)
1 Timer counter 7 is counting
Bit 5
STR6 Description
Bit 4
STR5 Description
Rev. 3.0, 02/99, page 309 of 904

Bit 3
STR4 Description
Bit 2
STR3 Description
Bit 1
STR2 Description
Bit 0
STR1 Description
Rev. 3.0, 02/99, page 310 of 904

11.7 H8/500 CPU Interface
Some IPU registers can be accessed 16 bits at a time, while others are limited to eight-bit access.
These two types of registers differ in their write timing, as explained next.
11.7.1 16-Bit Accessible Registers
The timer counters (TCNT), general registers (GR), and dedicated registers (DR) are 16-bit
registers. The H8/500 CPU can access these registers a word at a time using a 16-bit data bus.
Byte access is also possible.
Figure 11-5 shows an example of word write timing to a timer counter. Figure 11-6 shows an
example of byte write timing to a timer counter.
T1 T2 T3
A19−A0 Timer counter address
Internal write
signal
Internal data
bus New value
Timer counter
value Old value New value
Figure 11-5 Example of Word Write Timing for Timer Counter
Rev. 3.0, 02/99, page 311 of 904

T1 T2 T3 T1 T2 T3
A19−A0 Low address High address
Internal write
signal
Internal data
New value New value
bus
Timer counter Old value Lower byte only Upper byte only
value
Figure 11-6 Example of Byte Write Timing for Timer Counter
Read and Write Operations: Timer counters, general registers, and dedicated registers can be
written and read a word at a time or a byte at a time. Figure 11-7 illustrates word read/write
operations. Figure 11-8 illustrates upper byte read/write operations. Figure 11-9 illustrates lower
byte read/write operations.
On-chip
data bus 16 16
Module data bus
Bus
H8/500 CPU
interface
8 8
High Low
address address
Figure 11-7 Word Read/Write Operations
Rev. 3.0, 02/99, page 312 of 904

On-chip
data bus 16 16
Module data bus
Bus
H8/500 CPU
interface
High Low
address address
Figure 11-8 Upper Byte Read/Write Operations
On-chip
data bus 16 16
Module data bus
Bus
H8/500 CPU
interface
High Low
address address
Figure 11-9 Lower Byte Read/Write Operations
Rev. 3.0, 02/99, page 313 of 904

11.7.2 Eight-Bit Accessible Registers
The IPU's timer control registers (TCRH and TCRL), timer status registers (TSRH and TSRL),
timer output enable registers (TOER), timer mode register A (TMDA), timer mode register B
(TMDB), and timer start register (TSTR) are eight-bit registers. The H8/500 CPU accesses these
registers a byte at a time using an eight-bit data bus. If an instruction specifies word size, two
registers are accessed at consecutive addresses, upper byte (even address) first and lower byte (odd
address) second.
Figure 11-10 shows an example of byte write timing to a timer control register. Figure 11-11
shows an example of write timing to a timer control register by an instruction specifying word
operand size.
T1 T2 T3
A19−A0 Timer control register address
Internal write
signal
Internal data
bus New value
Timer control
register value Old value New value
Figure 11-10 Example of Byte Write Timing for Timer Control Register
Rev. 3.0, 02/99, page 314 of 904

T1 T2 T3 T1 T2 T3
A19−A0 TCRH address TCRL address
Internal write
signal
Internal data New value New value

bus
Timer control
Old value Updated TCRH Updated TCRL
register value
Figure 11-11 Example of Write Timing for Timer Control Register by Instruction
Specifying Word Operand Size
Read and Write Operations: Table 11-6 lists the byte-accessed registers. Figure 11-12
illustrates upper byte read/write operations. Figure 11-13 illustrates lower byte read/write
operations.
Table 11-6 Eight-Bit Access Registers
Abbreviation
Name Byte Access Word Access
Timer control registers (high) TCRH TCR Upper
Timer control registers (low) TCRL Lower
Timer status registers (high) TSRH TSR Upper
Timer status registers (low) TSRL Lower
Timer output enable registers TOER TOER Upper
Timer mode registers TMDR TMDR Lower
Timer start registers TSTR TSTR Upper
T1CRB Lower
Rev. 3.0, 02/99, page 315 of 904

On-chip
data bus 8 8
Module data bus
Bus
H8/500 CPU
interface
High Low
address address
Figure 11-12 Upper Byte Read/Write Operations
On-chip
data bus 8 8
Module data bus
Bus
H8/500 CPU
interface
High Low
address address
Figure 11-13 Lower Byte Read/Write Operations
Rev. 3.0, 02/99, page 316 of 904

11.8 Examples of Timer Operation
The 16-bit integrated-timer pulse unit (IPU) has several application-oriented operating modes.
These are outlined and examples are given below.
11.8.1 Examples of Counting
When a start (STR) bit in the timer start register (TSTR) is set to 1, the corresponding counter
starts counting from H'0000. There are two counting modes: a free-running mode and a periodic
mode. Figure 11-14 shows the procedure for selecting the counting mode.
Procedure for Selecting Counting Mode
Counting mode
selection
STR bit = 1 (1) (1) Set the counter's STR bit in

TSTR to 1.
(2) Periodic counter: Set the
count period in a dedicated or
Periodic counter Free-running general register and select
counter the clear source in TCRH.
(3) Free-running counter: No
Set period in DR or GR (2) (3) need to set count period or
select clear source.
Select clear source

CCLR ≠ 00
<Periodic counter> <Free-running counter>
Figure 11-14 Procedure for Selecting Counting Mode
Rev. 3.0, 02/99, page 317 of 904

Counter Operation: Figure 11-15 illustrates counter operations.
Counter operation
(1) When an STR bit is

Hold value set to 1, the
No
corresponding
STR = 1? counter starts
counting up.
Yes (1)
(2) Periodic counter:
After incrementing,
the counter value is
<Increment> checked against
the count period.
(3) Periodic counter: If
the counter value
matches the count
Periodic counter Free-running period, the CMF or
counter IMF bit in TSRL is
set to 1.
No No (4) Free-running
Compare match?* Overflow? counter: After
incrementing,
Yes Yes counter overflow is
(2) (4) checked.
CMF/IMF = 1 (3) OVF = 1 (5) (5) Free-running
counter: If the
count has
overflowed, the
OVF bit in TSRL is
set to 1.
TCNT ← 0 (6) (6) The timer counter
is reset and starts
counting up again
from zero.
Note: * TCNT = count period
Figure 11-15 Counter Operation
Rev. 3.0, 02/99, page 318 of 904

A reset leaves the IPU in free-running mode. Figure 11-16 shows an example of free-running
counting. The counter starts from H'0000, counts up to H'FFFF, then returns to H'0000, at which
point the OVF flag is set in timer status register high (TSRH). Counting then continues from
H'0000.
If compare match is selected as a counter clear source, the IPU operates in periodic counting
mode. Figure 11-17 shows an example of periodic counting. The counter starts from H'0000 and
counts up to H'8000. At this point a compare match with DR2 occurs, so the CMF2 flag in TSRH
is set to 1 and the counter is automatically cleared. Counting then continues from H'0000.
Timer
counter value H'0000 H'0001 H'FFFE H'FFFF H'0000 H'0001
STR bit
(TSTR) Counting starts when STR bit is set to 1
OVF flag
(TSRH)
Overflow flag (OVF) is set
when count changes from
H'FFFF to H'0000
Figure 11-16 Free-Running Counter Operation
Timer
counter value H'0000 H'0001 H'7FFF ∗ H'0000 H'0001 H'0002
STR bit
(TSTR) Note: ∗ H'8000
Counting starts when STR bit
is set to 1
CMF2 flag
(TSRH) Compare match with DR2 sets
compare match flag 2 (CMF2)
and clears counter
DR2 value H'FFFF H'8000
Cycle length H'8000 is set in DR2
Figure 11-17 Periodic Counter Operation
Rev. 3.0, 02/99, page 319 of 904

11.8.2 Selection of Output Level
Compare match signals can be output in three modes: high, low, or toggle. Figure 11-18 shows
the procedure for selecting the output level.
Procedure for Selecting Output Level
Output selection
(1) Select the counting mode.
(2) Set a value in a dedicated or general register to
select the pulse output time.
Select counting mode (1)
(3) Low output: To have the output go low at
compare match, set the GOE or DOE bits in
the timer output enable register (TOER) to 01.
Set compare value
(2) (4) High output: To have the output go high at
in DR or GR
TOER to 10.
(5) Toggle output: To have the output toggle at
TOER to 11. Toggle output is available only
on channels 4 and 5.
Low output (3) High output (4) Toggle output (5)
GOE/DOE = 11
GOE/DOE = 01 GOE/DOE = 10
(channel 4 or 5)
<Waveform output> <Waveform output> <Waveform output>
Figure 11-18 Procedure for Selecting Output Level
Rev. 3.0, 02/99, page 320 of 904

Waveform Output Operation: Figure 11-19 illustrates waveform output operations.
Waveform output (1) CMF or IMF bit in timer status register

low (TSRL) is set to 1 at compare match.
<Compare match> (2)

Waveform is output according
(3) to setting of timer output enable
(4) register (TOER).
CMF/IMF = 1 (1)
Low output High output Toggle output
(2) (3) (4)
or
Pin level Pin level Pin level

(low output) (high output) (toggles between low and high)
Figure 11-19 Waveform Output
Rev. 3.0, 02/99, page 321 of 904

Figure 11-20 shows examples of waveform output on channel 4. High output is selected from
T4IOC1, low output from T4IOC2, and toggle output from T4OC1.
High output is selected by setting bits GOE11 and GOE10 to 10 in the channel 4 timer output
enable register (TOER). The IPU drives T4IOC1 high when the counter matches the value in GR1
(H'0001). Low output is selected by setting bits GOE21 and GOE20 to 01 in the channel 4 TOER.
The IPU drives T4IOC2 low when the counter matches the value in GR2 (H'0003). Toggle output
is selected by setting bits GOE11 and GOE10 to 11 in the channel 4 TOER. The IPU toggles
T4OC1 when the counter matches the value in DR1 (H'0004). The counter is cleared when the
count matches the value in DR2 (H'00FF).
If high or low output is selected, when compare match occurs, and if the pin is already at the
selected output level, the output level does not change.
• Settings
 TOER (channel 4): H'36
 TCRL (channel 4): H'E0 (clear on T4DR2 compare match)
Note: * 00FF
Timer counter
value 0001 0002 0003 0004 00FE * 0000 0001 0002 0003 0004
GR1 value H'0001
Output
GR2 value goes H'0003
high at
Counter is
compare
cleared at
DR1 value match
H'0004 compare match
Output
DR2 value goes H'00FF
low at
compare
match
T4IOC 1
(GOE11/10 = 10)
Output toggles at
T4IOC 2 compare match
(GOE21/20 = 01)
T4OC1
(GOE11/10 = 11)
Figure 11-20 Example of Waveform Output on Channel 4
Rev. 3.0, 02/99, page 322 of 904

11.8.3 Input Capture Function
The counter value can be captured into a register when a transition occurs at an input capture pin.
Capture can take place on the rising edge, falling edge, or both edges. Figure 11-21 shows the
procedure for selecting the input capture function.
Procedure for Selecting Input Capture Mode
Input selection (1) Select the counting mode.

(2) Capture on rising edge: To capture on the rising
edge of the capture input signal, set the IEG bits in
Select counting mode (1) timer control register low (TCRL) to 01.
(3) Capture on falling edge: To capture on the falling
edge of the capture input signal, set the IEG bits in
TCRL to 10.
(4) Capture on both edges: To capture on both edges
of the capture input signal, set the IEG bits in TCRL
to 11.
Rising edge Falling edge Both edges
IEG = 01 IEG = 10 IEG = 11

(2) (3) (4)
(low input) (high input) (low or high input)
or
<Capture> <Capture> <Capture>
Figure 11-21 Procedure for Selecting Capture Input Mode
Rev. 3.0, 02/99, page 323 of 904

Capture Operation: Figure 11-22 illustrates input capture operations.
Capture operation (1) The capture pin is monitored, and when

the edge selected by the IEG bits in
timer control register low (TCRL) is
detected, the IMF bit in timer status
register low (TSRL) is set to 1.
<Edge detect> (2) The counter value is transferred to and

held in a general register (GR).
IMF bit = 1 (1)
Counter value → GR (2)
Figure 11-22 Capture Mode Operation
Rev. 3.0, 02/99, page 324 of 904

Figure 11-23 shows an example of input capture on channel 1.
The rising edge of T1IOC1 is selected by setting bits IEG11 and IEG10 to 01 in channel 1 timer
control register low (TCRL). The IPU transfers the counter value (H'0001 and H'0100) to GR1 on
the rising edge of the T1IOC1 input. The falling edge of T1IOC2 is selected by setting bits IEG21
and IEG20 in channel 1 TCRL to 10. The IPU transfers the counter value (H'0002 and H'0102) to
GR2 on the falling edge of the T1IOC2 input. The rising and falling edges of T1IOC3 are selected
by setting bits IEG31 and IEG30 in channel 1 timer control register A (TCRA) to 11. The IPU
transfers counter value H'0004 on the rising edge and value H'0104 on the falling edge of the
T1IOC1 input, to GR3.
• Settings
 TCRL: H'89
 TCRA: H'F3
Timer
0001 0002 0003 0004 0100 0101 0102 0103 0104 0105
counter value
GR1 value H'0000 H'0001 H'0100
GR2 value H'0000 H'0002 H'0102
GR3 value H'0000 H'0004 H'0104
T1IOC1
(IEG11/10 = 01)
T1IOC2
(IEG21/20 = 10)
T1IOC3
(IEG31/30 = 11)
Figure 11-23 Example of Input Capture on Channel 1
Rev. 3.0, 02/99, page 325 of 904

Figure 11-24 shows an example of input capture timing on channel 2. The IPU latches the input
capture signal input at the T2IOC1 pin on the rising edge of the system clock (φ). One system
clock cycle (1.0tCYC) after the input capture signal is latched, the counter value (n + 1) is
transferred to T2GR1. The IMF1 flag in timer status register low (TSRL) is set 1.5tCYC after the
input capture signal is latched.
The pulse width of the input capture signal must be at least 1.5tCYC.
Note: tTICS: 50 ns (min)
tTICS tTICS
T2IOC1 Minimum width:

1.5tCYC
Internal capture
signal
TCNT2 n n+1 m m+1
T2GR1 H'FFFF (Initial value) n+1 m+1
IMF1
(channel 2)
Figure 11-24 Capture Input Timing
Rev. 3.0, 02/99, page 326 of 904

11.8.4 Counter Clearing Function
A counter can be cleared by input capture or compare match. When compare match is selected as
a counter clear source, the count repeats cyclically from H'0000 to the value in the compare
register. When input capture is selected as a counter clear source, the counter can be cleared at
intervals determined by external events. Figure 11-25 shows the procedure for selecting the
counter clear source.
Procedure for Selecting Counter Source
Selection
of clear source (1) Clear on compare match:
To clear the counter on
compare match, set the
clear period in a dedicated
or general register, then
Compare match (1) Capture (2) set the CCLR bits in TCRL
to 01 or 10. (The counter
operates as a periodic
Set period in DR or GR Select edge(s) counter.)
(2) Clear on capture:
To clear the counter by
CCLR = 01 (IEG ≠ 00)
Set CCLR = 01 (IEG = 00) input capture, select the
or CCLR = 10 input edge or edges in
TCRL, then set the CCLR
bits to 01.
<Counter clear> <Counter clear>
Figure 11-25 Procedure for Selecting Counter Clear Source
Counter Clear Operation: Figure 11-26 illustrates the counter clear operation.
Counter clear
(1) When the counter clear source condition occurs,
TCNT is reset to 0 and starts counting up again.
If capture is selected, the counter value is first
<Clear condition satisfied> captured in a register, then the counter is cleared.
TCNT ← 0 (1)
Figure 11-26 Counter Clearing Operation

Rev. 3.0, 02/99, page 327 of 904
Figure 11-27 shows an example of counter clearing on channel 4.
In this example the channel-4 counter is cleared by input capture at T4IOC1. This clear condition
is selected by setting CCLR1 and CCLR0 in channel 4 timer control register low (TCRL) to 01.
The rising edge is selected by setting IEG11 and IEG10 to 01. The IPU transfers the counter value
(H'0003) on the rising edge of the T4IOC1 input to GR1, then clears the counter.
To clear the counter on DR2 compare match, set CCLR1 and CCLR0 to 10 in TCRL.
• Settings
 TCRL (channel 4): H'D4 (to clear on input capture in T4GR1)
 TCRL (channel 4): H'E0 (to clear on compare match with T4DR2)
Counter cleared by
input capture
H'0003 0000
0000
Timer counter
0001 0002 0001 00FE ∗ 0001 0002 0003 0004
value
GR1 value H'0000 H'0003

Counter cleared by
compare match
DR2 value H'00FF
T4IOC1
(IEG = 01) Note: ∗ H'00FF
Figure 11-27 Example of Input Counter Clearing on Channel 4
Rev. 3.0, 02/99, page 328 of 904

11.8.5 PWM Output Mode
Channels 1, 2, 3, 6, and 7 can be used as PWM timers. Channel 1 can provide three-phase PWM
output, channels 2 and 3 can provide two-phase PWM output, and channels 6 and 7 can provide
single-phase PWM output. Figure 11-28 shows the procedure for selecting PWM output mode.
Procedure for Selecting PWM Mode
PWM mode
selection
Set compare values

(1) (1) First set the counting period, pulse set time, and
in DR/GR
pulse reset time in dedicated (DR) or general (GR)
registers.
Select periodic counting (2) (2) Select periodic counting and the counter clear
(CCLR ≠ 00) source by setting the CCLR bits in timer control
register low (TCRL).
PWM bit = 1 (3) (3) Set the PWM bit in timer mode register B
(TMDRB) to 1.
<PWM mode>
Figure 11-28 Procedure for Selecting PWM Output Mode
Rev. 3.0, 02/99, page 329 of 904

PWM Output Operation: Figure 11-29 illustrates PWM output operations.
PWM output* (1) U phase set time:

The GR1 value is
constantly compared
U phase with the TCNT value.
(2) U phase reset time:
The GR3 value is
constantly compared
GR1: TCNT GR3: TCNT with the TCNT value.
(1) (2) (3) GR1-TCNT compare
match generates a U
phase set command.
<Compare match> <Compare match> (4) GR3-TCNT compare
match generates a U
U phase set command U phase reset command phase reset
(3) (4) command.
(5) Contention decision:
Contention between
Yes
Output remains U phase set and
Contention? reset commands is
unchanged
(5) tested; if contention
No
occurs, the output
<U phase set or reset> level remains
unchanged.
(6) (6) If there is no set-
reset contention, the
U phase output is set or reset.
Note: ∗ Channel 1:
Example of U
phase in 3-phase
PWM output.
Figure 11-29 PWM Output Operation
Figure 11-30 shows an example of three-phase PWM output on channel 1.
The U phase is output at the T1IOC1 pin. The V phase is output at the T1IOC2 pin. The W phase
is output at the T1OC1 pin. The IPU sets T1IOC1 when the timer counter matches GR1 (H'0001),
and resets T1IOC1 when the timer counter matches GR3 (H'00FE). The IPU sets T1IOC2 when the
timer counter matches GR2 (H'0002), and resets T1IOC2 when the timer counter matches GR4
(H'00FD). The IPU sets T1IOC3 when the timer counter matches DR1 (H'0003), and resets
T1IOC3 when the timer counter matches DR3 (H'00FC).
The IPU clears the counter when the timer counter matches DR4 (H'00FF).
Rev. 3.0, 02/99, page 330 of 904

• Settings
— TMDRB: H'C1 (PWM output on channel 1)
— TCRL: H'F0 (clear on T1DR4 compare match)
— TCRA: H'F0
Timer counter
* 0000 0001 0002 0003 00FB 00FC 00FD 00FE * 0000 0001
value
GR1 value
(U phase set ) H'0001
GR3 value
(U phase reset ) H'00FE
GR2 value
(V phase set ) H'0002
GR4 value Counter is

(V phase reset ) H'00FD cleared by
compare
match
DR1 value
(W phase set ) H'0003
DR3 value
(W phase reset ) H'00FC
DR4 value
H'00FF
(PWM period)
T1IOC1
(U phase)
T1IOC2
(V phase)
T1OC1
(W phase)
PWM
Note: * H'00FF
Figure 11-30 Example of Three-Phase PWM Output on Channel 1

Rev. 3.0, 02/99, page 331 of 904
In PWM mode the compare registers are paired: one register sets the pulse; the other register resets
the pulse. The counter should be set to periodic counting mode. Table 11-7 indicates the register
pair assigned to each output pin.
Table 11-7 Output Pins and Register Pairs
Channel Output Pin Set Reset PWM Period

1 T1IOC1 GR1 GR3 DR2, GR3, DR4
T1IOC2 GR2 GR4
T1OC1 DR1 DR3
2 T2IOC1 GR1 DR1 DR2
T2IOC2 GR2 DR2
3 T3IOC1 GR1 DR1 DR2
T3IOC2 GR2 DR2
6 T6IOC1 GR1 GR2 GR2
7 T7IOC1 GR1 GR2 GR2
Usage Notes
1. In PWM output mode, the output levels of PWM output pins cannot be set in the timer output
enable register (TOER). Any output level settings made will be ignored.
2. Settings of the IEG bits in timer control register low (TCRL) are valid in PWM output mode.
The IEG bits must be cleared to 0.
3. In PWM output mode, periodic counting should be used by selecting a counter clear source in
TCRL. Table 11-7 lists the registers that can set the PWM period in each channel.
Rev. 3.0, 02/99, page 332 of 904

11.8.6 Synchronizing Mode
In synchronizing mode two or more timer counters can be rewritten or cleared simultaneously.
Figure 11-31 shows the procedure for selecting synchronizing mode.
Procedure for Selecting Synchronizing Mode
Selection of (1) Set desired SYNC bit(s) in TMDRA

(1) to 1.
synchronizing mode
(2) Synchronized preset: Enabled by

setting a SYNC bit to 1.
SYNC bit = 1
(3) Synchronized clear: A function that
clears one counter in synchronization
with another counter.
Synchronized Synchronized (4) Master: Select the clear source.

preset clear
(2) (3) (5) Slave: Select synchronized reset
(CCLR = 11).
Master or slave? Slave
Master
Select clear source: Select synchronized clear:

CCLR bits = 00, 01, or 10 CCLR bits = 11*
(4) (5)
<Synchronized preset> <Counter clear> <Synchronized clear>
Note: * Channels 2 to 7
Figure 11-31 Procedure for Selecting Synchronizing Mode
Rev. 3.0, 02/99, page 333 of 904

Synchronized Operation: Figure 11-32 shows an example of synchronized operation of channels
2 and 3.
(1) When a counter clear

condition occurs on
Counter clear channel 2, channel 3 is
commanded to clear in
synchronization.
<Clear condition satisfied>
(1) (2) The counters in

channels 2 and 3 are
Synchronized clear* (3) cleared simultaneously.
TCNT2 ← 0 (2) TCNT3 ← 0 (3)
Synchronizing
preset*
Synchronizing preset:
<Write> (4) Writing to channel 2 or
3 writes the same
(5) value simultaneously
into both counters.
TCNT2 ← DATA TCNT3 ← DATA
(4) (5)
Note: * Example of synchronized operation of channels 2 and 3.
Figure 11-32 Example of Synchronized Operation of Channels 2 and 3
Rev. 3.0, 02/99, page 334 of 904

Figure 11-33 shows an example of the synchronization of timer counters 2 and 3.
Timer counters 2 and 3 are synchronized by setting the SYNC1 bit in timer mode register A
(TMDRA) to 1. The timer counters are synchronously preset by writing a new value to either
timer counter 2 or 3; the IPU simultaneously writes the same value in the other timer counter.
Synchronized clearing is selected by setting CCLR0 = CCLR1 = 1 in timer control register low
(TCRL) as the clear source for timer counter 3. The IPU clears timer counters 2 and 3
simultaneously when timer counter 2 matches T2GR1 (H'00FF).
• Settings
 T2GR1: H'00FF
 TMDRA: H'02 (SYNC1 = 1)
 TCRL (channel 2): H'D0 (clear at compare match with T2GR1)
 TCRL (channel 3): H'F0 (enabling synchronized clearing)
Write to TCNT2 TCNT2 and TCNT3

and TCNT3 are simultaneously
Write to (synchronizing cleared by compare
Write to
TCNT2 preset) match*2
TCNT3
0000
Timer counter 0000 0001 0002 m 0000 0001 00FE *1 0001
2 value
Timer counter
n n + 1 0000 m + 2 0000 0001 00FE *1 0001
3 value
0000
T2GR1 value
(channel 2) H'FFFF H'00FF
TMDRA value H'0000 H'0001 (SYNC1 =1)
Synchronization of timer
counters 2 and 3 enabled
Timer counter 2 Timer counter 2 and timer

and timer counter counter 3 operate in
3 are not synchronized synchronization
Notes: 1. H'00FF
2. Set CCLR1 = CCLR0 = 1 (synchronized clearing)
as the clear source for timer counter 3.
Figure 11-33 Example of Synchronization of Timer Counters 2 and 3

Rev. 3.0, 02/99, page 335 of 904
11.8.7 External Event Counting
The IPU has three external clock input pins. If external event signals are input at these external
clock input pins, external events can be counted. The counter can be set to increment on the rising
or falling edge, or on both edges of the external clock signal. The value of an externally clocked
counter can be captured at regular intervals to measure external event frequencies. Figure 11-34
shows the procedure for selecting external event counting mode.
Procedure for Selecting External Event Counting Mode
(1) Set the TPSC bits in timer control register high (TCRH) to
Input selection select an external clock.
(2) Count on rising edge: To count rising edges of the
external clock signal, set bits CKEG1 and CKEG0 to 00
in TCRH.
Select external clock (1) (3) Count on falling edge: To count falling edges of the
external clock signal, set bits CKEG1 and CKEG0 to 01
in TCRH.
(4) Count on both edges: To count both rising and falling
edges of the external clock signal, set bits CKEG1 and
CKEG0 to 10 or 11 in TCRH.
(5) Counting starts when the corresponding STR bit in the
timer start register (TSTR) is set to 1.
Rising edge Falling edge Both edges
CKEG1/0 = 00 CKEG1/0 = 01 CKEG1/0 = 10, 11

(2) (3) (4)
(high input) (low input) (low or high input)
or
STR bit = 1
(5)
<Start incrementing>
Figure 11-34 Procedure for Selecting External Event Counting Mode
Rev. 3.0, 02/99, page 336 of 904

External Event Counting Operation: Counting operations are the same as for an internal clock.
For details, see section 11.8.1, "Examples of Counting."
Figure 11-35 shows an example of external event counting.
In this example timer counters 1, 2, and 3 count external event inputs at TCLK1. In channel 1, the
rising edge of TCLK1 is selected by setting the CKEG1 and CKEG0 bits in TCRH to 00. The IPU
counts rising edges of TCLK1. In channel 2, the falling edge of TCLK1 is selected by setting the
CKEG1 and CKEG0 bits in TCRH to 01. The IPU counts falling edges of TCLK1. In channel 3,
both edges of TCLK1 are selected by setting the CKEG1 and CKEG0 bits in TCRH to 10 or 11.
The IPU counts both rising and falling edges of TCLK1.
• Settings
 TCRH (channel 1): H'CD (count rising edges)
 TCRH (channel 2): H'DD (count falling edges)
 TCRH (channel 3): H'ED or H'FD (count both rising and falling edges)
Incremented on rising
edge of TCLK1
Timer counter 1
value (CKEG = H'0001 H'0002 H'0003 H'0004
00)
Incremented on falling
edge of TCLK1
Timer counter 2
value (CKEG = H'0000 H'0001 H'0002 H'0003
01)
Incremented on both
edges of TCLK1
Timer counter 3
value (CKEG = H'0001 H'0002 H'0003 H'0004 H'0005 H'0006 H'0007
10 or 11)
TCLK1
Figure 11-35 Example of External Event Counting
Rev. 3.0, 02/99, page 337 of 904

Figure 11-36 shows an example of external clock input timing.
The IPU latches external clock signals (TCLK1 to TCLK3) on the rising edge of the system clock
(φ). TCNT2 is incremented 1.5 system clock cycles (1.5tCYC) after the external clock is latched.
The pulse width of the external clock signal must be at least 1.5tCYC.
tTCKS: 50 ns (min)
tTCKS tTCKS
TCLK1 −TCLK 3
Minimum width: at least 1.5t CYC
Internal counter
clock
TCNT2 n n+1 m m+1
Figure 11-36 External Clock Input Timing
Rev. 3.0, 02/99, page 338 of 904

11.8.8 Programmed Periodic Counting Mode
In programmed periodic counting mode, the value of an externally clocked counter is captured
into a general register by compare match on a different channel. No external input capture signal
is needed. Figure 11-37 shows the procedure for selecting programmed periodic counting mode.
Procedure for Selecting Programmed Periodic Counting Mode : Example when bit MD2-6 = 1
in timer mode register A (TMDRA)
Setup procedure (1) Channel 6: Select

external event
(Channel 6) (Channel 2) counting mode.
Select the external
clock and edge or
External event Measurement edges in timer control
counting period setup register high (TCRH).
(1) (2)
(2) Channel 2: Select the
Select external clock Select clock source channel 6 measurement
period. Select the clock
source in TCRH, then
Select edge(s) Set measurement set the measurement
interval in DR2 period in DR2.
Select DR2 compare
Select counter clear source match as the counter
clear source in timer
control register low
(TCRL).
(3) After setting up
MD2-6 bit = 1 (3)
channels 2 and 6, set
the MD2-6 bit in
(4) TMDRA to 1.
STR bits = 1
(4) Operation begins
when the STR2 and
STR6 bits are set to 1
<Programmed periodic counting mode> in the timer start
register (TSTR).
Figure 11-37 Procedure for Selecting Programmed Periodic Counting Mode
Rev. 3.0, 02/99, page 339 of 904

Programmed Periodic Counting Operation: Figure 11-38 shows the programmed periodic
counting operation.
Programmed (1) Channel 6: Counts

periodic counting external events.
(2) Channel 2: Counts
(Channel 6) (Channel 2) the measurement
period and
generates
compare matches.
(3) When a compare
<Edge detect> <Increment> match occurs on
channel 2, the
TCNT ← TCNT + 1 (1) <Compare match> counter value in
channel 6 is
(2) captured in GR1.
TCNT ← 0 (4)
(4) The channel 2
<Capture> counter is cleared
to 0 and starts
counting a new
TCNT6 → GR1 (3) measurement
period.
Figure 11-38 Operation in Programmed Periodic Counting Mode
Rev. 3.0, 02/99, page 340 of 904

Figure 11-39 shows an example of programmed periodic counting. Table 11-8 lists the possible
combinations of compare-match channels and capture channels.
In this example external events are counted over a programmed period using channels 2 and 6.
The IPU automatically transfers the value of timer counter 6 (H'0012) to T6GR1 when timer
counter 2 matches T2DR2 (H'0100). Timer counter 2 is set to be cleared by compare match with
T2DR2.
• Settings
 TCRL (channel 2): H'E0 (cleared by compare match with T2DR2)
 TCRH (channel 6): H'ED or H'FD (increment on both rising and falling edges)
 TMDRA: H'10 (capture in T6GR1 on compare match with T2DR2)
Timer counter 2
0000 0001 0002 0003 0004 00F9 00FA 00FB 00FC 00FD 00FE 00FF * 0 0001 0002
value
T2DR2 value
(channel 2)
H'0100
Counter is cleared
by compare match
TCLK1
Timer counter 6
H'0000 H'0001 H'0010 H'0011 H'0012
value
Timer counter 6 value is captured

T6GR1 value in T6GR1 on compare match in
H'FFFF channel 2 H'0012
(channel 6)
TMDRA value H'00 H'10 (MD2-6 = 1)
Note: * H'0100
Figure 11-39 Example of Programmed Periodic Counting
Rev. 3.0, 02/99, page 341 of 904

Table 11-8 Combinations of Compare Match Channels and Capture Channels
Compare Match Channel Capture Channel

Channel No. Register Channel No. Register
MD2-6 Channel 2 DR2 Channel 6 GR1
MD6-7 Channel 6 GR2 Channel 7 GR2
11.8.9 Phase Counting Mode
One application of phase counting mode is control of an AC servo motor. If the output of a two-
phase encoder is fed to two external clock pins, the phase relationship between the two clock
signals is detected and the counter is incremented or decremented accordingly. Phase counting is
available only on channel 7. Figure 11-40 shows the procedure for selecting phase counting
mode.
Procedure for Selecting Phase Counting Mode
Mode selection
(1) Set the MDF bit to 1 in timer mode

MDF bit = 1 (1)
register B (TMDRB) to select
phase counting mode.
STR7 bit = 1 (2) (2) Counting begins when the STR7

bit is set to 1 in the timer start
register (TSTR).
<Increment or decrement>
Figure 11-40 Procedure for Selecting Phase Counting Mode
Rev. 3.0, 02/99, page 342 of 904

Phase Counting Operation: Figure 11-41 shows the phase counting operation.
Phase counting
(1) The phases of TCLK1

and TCLK2 are
Phase comparison (1)
compared.
(2) (3) (2) The channel 7 counter

is incremented or
TCLK1 TCLK1 High (3) decremented according
to the counting
conditions.
TCLK2 High TCLK2
or or
TCLK1 TCLK1 Low
TCLK2 Low TCLK2
<Decrement> <Increment>
No No
Underflow? Overflow? (4) When an overflow or
underflow occurs, the
Yes (4) Yes OVF bit in timer status
register low (TSRL)
is set to 1.
OVF ← 1
Figure 11-41 Operation in Phase Counting Mode
Rev. 3.0, 02/99, page 343 of 904

Figure 11-42 shows an example in which the counter counts up, overflows, then counts down.
In up-counting, the counter counts repeatedly from H'0000 to H'FFFF. The IPU sets the overflow
flag (OVF) in timer status register low (TSRL) when the count returns from H'FFFF to H'0000.
For the up/down counting conditions, see figure 11-44 "Counting Conditions" and table 11-9
"Up/Down-Counting Conditions."
Counting up Counting
down
Timer counter
0000 0001 0002 FFFE FFFF 0000 0001 0002 0001 0000
7 value
TCLK2
TCLK1
OVF flag
(TSRL)
Overflow flag (OVF) is set to 1
H'FFFF to H'0000
Figure 11-42 Example of Up-Counting, Overflow, and Down-Counting
Rev. 3.0, 02/99, page 344 of 904

Figure 11-43 shows an example in which the counter counts down, underflows, then counts up.
In down-counting, the counter counts repeatedly from H'FFFF to H'0000. The IPU sets the
overflow flag (OVF) in timer status register low (TSRL) when the count returns from H'0000 to
H'FFFF. For the up/down counting conditions, see figure 11-44 "Counting Conditions" and table
11-9, "Up/Down-Counting Conditions."
Counting down Counting

up
Timer counter
0100 00FF 00FE 0001 0000 FFFF FFFE FFFD FFFE FFFF
7 value
TCLK1
TCLK2
OVF flag
(TSRL)
Overflow flag (OVF) is set to 1
H'0000 to H'FFFF
Figure 11-43 Example of Down-Counting, Underflow, and Up-Counting
Rev. 3.0, 02/99, page 345 of 904

Figure 11-44 shows the counting conditions. Table 11-9 indicates the up- and down-counting
conditions. The IPU counts all edges of TCLK1 and TCLK2.
Counter value
Counting up
Counting down
Timer counter 7
Time
TCLK2
TCLK1
Figure 11-44 Counting Conditions
Table 11-9 Up/Down-Counting Conditions
Counting Direction Up-Counting Down-Counting
TCLK2 High Low Low High
TCLK1 Low High High Low
Rev. 3.0, 02/99, page 346 of 904

Figure 11-45 shows the external clock input timing in phase counting mode.
The IPU latches the external clock signals on the rising edge of the system clock (φ). The counter
is incremented 1.5 system clock cycles (1.5tCYC) after the external clock is latched.
The external clock pulse width must be at least 1.5 system clock cycles (1.5tCYC). The phase
difference between TCLK1 and TCLK2 must be at least 1.0tCYC.
tTCKS : 50 ns (min)
φ
tTCKS tTCKS
TCLK1 Minimum width:

at least1.5tCYC
Minimum phase
Minimum phase difference:
difference: tTCKS at least tTCKS
at least 1.0tCYC
1.0tCYC
TCLK2
Minimum width: at least 1.5tCYC
Internal counter
clock
TCNT2 n n+1 n+2
Figure 11-45 External Clock Input Timing in Phase Counting Mode
Rev. 3.0, 02/99, page 347 of 904

11.9 Interrupts
The IPU can request three types of interrupts: compare match, input capture, and overflow. The
timing of each type of interrupt request is described next.
11.9.1 Interrupt Timing
(1) Output Compare Timing: Figure 11-46 shows the timing from counter incrementation to
generation of a compare match interrupt request. One system clock cycle (1.0tCYC) after timer
counter 2 matches the T2GR1 value (N), the IPU sets the input capture/compare match flag (IMF).
A compare match signal (T2IOC1) is output 0.5tCYC after IMF is set. The interrupt request
(T2IMI1) is generated 0.5tCYC after the T2IOC1 output. The T2IMI1 interrupt request therefore
comes 2.0tCYC after the counter is incremented to N.
2.0tCYC
Timer counter
N-1 N N+1
2 value
Compare match
Internal compare
match signal
1.0tCYC
IMF2 (TSRL)
T2IOC1
1.5tCYC
T2IMI1
Compare match
interrupt request
T2GR1 N
Figure 11-46 Timing from Incrementation to Compare Match Interrupt Request
Rev. 3.0, 02/99, page 348 of 904

(2) Input Capture Timing: Figure 11-47 shows the timing from capture signal input to
generation of an input capture interrupt request. A maximum 1.5tCYC after input of the capture
signal, the IPU transfers the timer counter value (N) to T2GR1. The input capture/compare match
flag (IMF) is set 0.5tCYC after the input capture transfer. The interrupt request (T2IMI1) is
generated 1.0tCYC after IMF is set. The T2IMI1 interrupt request therefore comes a maximum
3.0tCYC after the counter value becomes N.
3.0tCYC (max)
T2IOC1
Timer counter
2 value N-1 N N+1
Internal capture
signal
T2GR1 N
IMF2 (TSRL) 1.5tCYC (max)
2.0tCYC (max)
T2IMI1
Input capture
interrupt request
Figure 11-47 Timing from Capture Input to Input Capture Interrupt Request
Rev. 3.0, 02/99, page 349 of 904

(3) Overflow Timing: Figure 11-48 shows the timing from counter incrementation to generation
of an overflow interrupt request. When the value of timer counter 2 returns from H'FFFF to
H'0000 the IPU sets the overflow flag (OVF). The interrupt request (T2OVI) is generated 1.0tCYC
after OVF is set.
In phase counting mode, the IPU sets the overflow flag (OVF) when the timer counter value
returns from H'0000 to H'FFFF. For usage in phase counting mode, see section 11.8.9 "Phase
Counting Mode."
1.0tCYC
Timer counter
H'FFFF H'0000 H'0001
2 value
OVF (TSRL)
T2OVI
Overflow interrupt request
Figure 11-48 Timing from Counter Incrementation to Overflow Interrupt Request
11.9.2 Interrupt Sources and DTC Interrupts
The IPU has 35 interrupt sources. Of these, the compare match interrupt sources and the compare
match/input capture interrupt sources can start the data transfer controller (DTC) to transfer data.
Table 11-10 lists the interrupt sources and indicates which can start the DTC.
The exclusive compare match interrupt sources (such as T1CMI1 and T1CMI2) are paired. Both
sources in each pair share the same vector. Data transfer should not be enabled for both interrupt
sources at the same time.
Rev. 3.0, 02/99, page 350 of 904

Table 11-10 Interrupt Sources and DTC Interrupts
Channel Interrupt Description DTC Activation Priority

Source Possible Order
1 T1IMI1 GR1 compare match or input capture Yes High
T1IMI2 GR2 compare match or input capture Yes
T1CMI1/ DR1 or DR2 compare match Yes
T1CMI2
T1OVI Timer counter 1 overflow No
T1CMI4
2 T2IMI1 GR1 compare match or input capture Yes
T2CMI2
T3CMI2
T4CMI2
T5CMI2
T7IMI2 GR2 compare match or input capture Yes Low
Rev. 3.0, 02/99, page 351 of 904

11.10 Notes and Precautions
This section describes contention between the compare registers and various IPU operations, and
other matters requiring special attention.
(1) Contention between Counter Read/Write by the H8/500 CPU and IPU Operations
Contention between Writing to Timer Counter by H8/500 CPU (T3) and Clearing by
Compare Match: Clearing the counter has priority.
T1 T2 T3 If the internal write signal

followed the dotted line,
φ a write would occur on the
falling edge of T3.
Timer counter
N-1 N H'0000
value
Internal counter
clear signal
Masked
The internal counter
Internal write clear signal masks the
signal write signal, so clearing
of the counter takes
priority. (The dotted
line shows the normal
write signal.)
Figure 11-49 Contention between Writing to Timer Counter by H8/500 CPU (T3) and
Clearing by Compare Match
Rev. 3.0, 02/99, page 352 of 904

Contention between Writing to Timer Counter by H8/500 CPU (T3) and Clearing by
Capture Input: Clearing the counter has priority.
If the internal write signal

T1 T2 T3 followed the dotted line,
a write would occur on the
φ falling edge of T3.
Input capture
pin
Capture input generates clear signal
Timer counter
N H'0000
value
Internal counter
clear signal
Masked
The internal counter
Internal write clear signal masks the
signal write signal, so clearing
of the counter takes
priority. (The dotted line
shows the normal write
signal.)
Figure 11-50 Contention between Writing to Timer Counter by H8/500 CPU (T3) and
Clearing by Capture Input
Rev. 3.0, 02/99, page 353 of 904

Contention between Timer Counter Write (T3) and Increment: Writing has priority.
T1 T2 T3
Internal write
signal
Even if H'AAAA is set in
Internal data a compare register,
bus Write data (H'AAAA) a compare match does
not occur here.
Timer counter
N H'AAAA
value
Masked
Internal increment The internal write signal masks
signal the increment signal, so writing
to the counter takes priority.
(The dotted line shows the
normal increment signal.)
Figure 11-51 Contention between Timer Counter Write (T3) by H8/500 CPU and
Increment
Rev. 3.0, 02/99, page 354 of 904

Contention between Timer Counter Write (T3) and Setting of Overflow Flag: Setting the
overflow flag has priority.
T1 T2 T3
Internal write
signal
Internal data Write data (H'AAAA)

bus
Timer counter
H'FFFF H'AAAA
value
Overflow flag
(OVF)
If the write occurs at the instant
when the count would have
changed from H'FFFF to H'0000,
the overflow flag (OVF) is set.
Figure 11-52 Contention between Timer Counter Write (T3) by H8/500 CPU and
Setting of Overflow Flag
Rev. 3.0, 02/99, page 355 of 904

Contention between Timer Counter Byte Write (T2) and Increment: If the write is to the upper
byte, the new value is written in the upper byte and the lower byte retains its old value. If the
write is to the lower byte, the new value is written in the lower byte and the upper byte retains its
old value. If the contention occurs at T3, however, the byte that is not written is incremented.
T1 T2 T3
Internal write
signal
Internal data
bus Write data (H'AA)
Timer counter
value (upper H'FF H'AA
byte)
Timer counter
value (lower H'00 H'01 H'00
byte)
Internal Value prior to increment
increment is retained.
signal
Figure 11-53 Contention between Timer Counter Byte Write (T2) by H8/500 CPU
and Increment
Rev. 3.0, 02/99, page 356 of 904

Contention between Capture Register Read (T3) and Input Capture: The H8/500 CPU reads
the data prior to capture.
T1 T2 T3
Internal read
signal
Value prior to capture is read
Internal data Read data (H'FFFF)
bus
Capture register H'FFFF H'AAAA

value
Input capture Data updated by input capture
pin
Figure 11-54 Contention between Capture Register Read (T3) by H8/500 CPU
and Input Capture
Rev. 3.0, 02/99, page 357 of 904

Contention between Writing to General Register or Dedicated Register by H8/500 CPU (T3)
and Compare Match: Compare match does not occur.
If the internal write

T1 T2 T3 signal followed the
dotted line, a write
φ world occur on the
falling edge of T3.
A19−A0 GR or DR address
Internal write
signal
Internal data Write data (H'0A0A)

bus
Timer counter H'0A09 H'0A0A

value
GR or DR value H'AAAA H'0A0A

Masked
Internal compare
match signal
The internal write signal masks the compare

match signal, so compare match does not occur.
(Dotted line indicates normal compare match
signal.)
Figure 11-55 Contention between Writing to General Register or Dedicated Register

by H8/500 CPU (T3) and Compare Match
Rev. 3.0, 02/99, page 358 of 904

(2) Note on Writing in Synchronizing Mode: After a write in synchronizing mode, all 16 bits of
all specified counters have the same value as the counter that was written. This is true regardless
of the operand size (word or byte).
Example: When channels 2 and 3 are synchronized
• Word write to channel 2 or word write to channel 3
TCNT2 FF 00 TCNT2 01 01
TCNT3 AA 55 Write H'0101 TCNT3 01 01
Upper byte Lower byte Upper byte Lower byte
• Byte write to channel 2 or byte write to channel 3

Write H'01 to
upper byte
TCNT2 FF 00 TCNT2 01 00
of channel 2
TCNT3 AA 55 TCNT3 01 00
Upper byte Lower byte Upper byte Lower byte

Write H'01 to
lower byte of
channel 3
TCNT2 AA 01
TCNT3 AA 01
Upper byte Lower byte
Rev. 3.0, 02/99, page 359 of 904

(3) Note on Compare Register Setting: The compare match frequency differs depending on
whether the timer counter clock source is the system clock (φ) or another source.
When the counter increments on the system clock as in figure 11-56, the compare match frequency
is:
T = φ /(N + 1)
(T: compare match frequency. φ: system clock frequency. N: value set in compare register.)
When the counter increments on a clock source other than the system clock as in figure 11-57, the
compare match frequency is:
T = φ /(D* × N) * Example: If the counter clock source is φ/2, then D = 2.
(T: compare match frequency. φ: system clock frequency. D: frequency ratio of system clock
to counter clock source. N: value set in compare register.)
In this case, if H'0000 is set in the compare register, compare match does not occur.
Counter clock
source
Counter
N H'0000 H'0001 H'0002 N-1 N H'0000 H'0001
value
Compare match
signal
(toggle output)
Cycle: T = φ/(N + 1)
Figure 11-56 Compare Match Frequency when Clock Source is System Clock
Rev. 3.0, 02/99, page 360 of 904

φ
Counter clock
source
Counter
value N−1 N H'0000 H'0001 N−1 N H'0000 H'0001
Compare match
signal
(toggle output)
Cycle: T = φ/(D +N)
Figure 11-57 Compare Match Frequency when Clock Source is not System Clock
Note on Rewriting the Compare Match Register: To generate a compare match after rewriting
the register, the following condition must be satisfied. Note that even if the counter value when
rewriting the register and the register value after rewriting the register do match, a compare match
will not be generated.
1. Slowing down compare match timing

Reg ≤ Count < Reg' ................................................................................................... (1)
However, if Reg ≈ TCNT, the following condition must be met:
Count < Reg' ............................................................................................................. (1')
Where Reg: Register value before rewriting
Count: Register value during rewriting
Reg': Register value after rewriting
tcyc: Counter refresh cycle or overflow cycle
2. Speeding up compare match timing
Reg ≤Count ≤ tcyc ....................................................................................................... (2)
Where Reg: Register value before rewriting
Count: Register value during rewriting
tcyc: Counter refresh cycle or overflow cycle
Rev. 3.0, 02/99, page 361 of 904

Rewriting the Compare Match Register in PWM Mode: In PWM mode, to shorten the pulse
width, two register values must be rewritten within the same cycle. Restrictions regarding writing
to the register are as described previously. Refer to figure 11-58 for a timing diagram of actual
rewrite processing (updating).
• Example: PWM pulse output on channel 1

 Pulse set: GR1
 Pulse reset: GR3
• Setting range
 GR1: Between 0 and 1/2 tcyc. (Between 1 and 1/2 tcyc when φ is selected as the clock source.)
 GR3: Between 1/2 tcyc and tcyc.
Here, tcyc refers to one cycle of the counter.
• Rewriting register to shorten pulse width
 GR1 rewrite: At GR1, or while 1/2 tcyc < count ≤ tcyc.
 GR3 rewrite: At GR3 or while 0 < count ≤ tcyc (1 < count < 1/2 tcyc if φ is the clock source).
T0 tcyc T0 T0 T0
Counter value
1/2 tcyc
GR1 rewrite GR1 rewrite

GR3 rewrite GR3 rewrite
T1IOC1
Compare Compare
match match
GR1 GR3 GR1 GR3 GR1 GR3
Figure 11-58 Example of Register Rewrite Timing in PWM Mode
Rev. 3.0, 02/99, page 362 of 904

Section 12 PWM Timers
12.1 Overview
The H8/539F has a built-in pulse-width modulation (PWM) timer module with three independent
channels. Each PWM timer has an eight-bit timer counter (TCNT) and an eight-bit duty register
(DTR). DTR settings can provide pulse output with any duty cycle from 0% to 100%.
12.1.1 Features
The PWM timer features are:
• Selection of eight counter clock sources

• Selection of duty cycles from 0% to 100% with 1/250 resolution
• Selection of direct or inverted PWM output
Rev. 3.0, 02/99, page 363 of 904

Figure 12-1 shows a block diagram of one PWM timer.
DTR
Compare
Bus interface
Output match Internal
PW Comparator data bus
control
TCNT Module
data
bus
TCR
Internal clock sources

φ/2
φ/8
φ/32
Clock Clock φ/128

select φ/256
φ/1024
Legend
DTR: Duty register φ/2048
TCNT: Timer counter
TCR: Timer control register φ/4096
Figure 12-1 Block Diagram of PWM Timer
Rev. 3.0, 02/99, page 364 of 904

12.1.3 Pin Configuration
Table 12-1 summarizes the PWM timer output pins.
Table 12-1 PWM Timer Pins
Name Abbreviation I/O Function

PWM1 output pin PW1 Output PWM timer 1 pulse output
Table 12-2 summarizes the internal registers of the PWM timers.
Table 12-2 PWM Timer Registers
Channel Name Abbreviation R/W Initial Value Address

1 Timer control register TCR R/W H'38 H'FEF0
Duty register DTR R/W H'FF H'FEF1
Timer counter TCNT R/(W)* H'00 H'FEF2
Timer counter TCNT R/(W)* H'00 H'FEF6
Timer counter TCNT R/(W)* H'00 H'FEFA
Note: * Can be written and read, but the write function is for test purposes only. Do not write to
these registers during normal operation.
Rev. 3.0, 02/99, page 365 of 904

12.2.1 Timer Counter (TCNT)
Bit 7 6 5 4 3 2 1 0
R/W R/(W) R/(W) R/(W) R/(W) R/(W) R/(W) R/(W) R/(W)
The timer counter (TCNT) is an eight-bit up-counter. When the output enable bit (OE) is set to 1
in TCR, TCNT starts counting pulses of the internal clock selected by clock select bits 2 to 0
(CKS2 to CKS0). After counting from H'00 to H'F9, the count repeats from H'00.
TCNT can be written to and read, but the write function is for test purposes only. Do not write to
TCNT during normal operation, because this may have unpredictable effects.
TCNT is initialized to H'00 by a reset and in standby mode, and when the OE bit is cleared to 0.
12.2.2 Duty Register (DTR)
Bit 7 6 5 4 3 2 1 0
The duty register (DTR) specifies the duty cycle of the output pulse. Any duty cycle from 0% to
100% can be output by setting the corresponding value in DTR. The resolution is 1/250. Writing
0 (H'00) in DTR gives a 0% duty cycle. Writing 125 (H'7D) gives a 50% duty cycle. Writing 250
(H'FA) gives a 100% duty cycle.
The DTR and TCNT values are constantly compared. When the values match, the PWM output is
placed in the 0 state. When the TCNT value changes from H'00 to H'01, the PWM output is placed
in the 1 state, unless the DTR value is H'00, in which case the duty cycle is 0% and the PWM
output remains in the 0 state.
DTR is double-buffered. A new value written in DTR does not become valid until after the timer
count changes from H'F9 to H'00. While the OE bit is cleared to 0 in TCR, however, new values
written in DTR become valid immediately. When DTR is read, the value read is the currently valid
value.
Rev. 3.0, 02/99, page 366 of 904

DTR is initialized to H'FF by a reset and in standby mode.
12.2.3 Timer Control Register (TCR)
Bit 7 6 5 4 3 2 1 0
OE OS − − − CKS2 CKS1 CKS0
R/W R/W R/W − − − R/W R/W R/W
The timer control register (TCR) is an eight-bit readable/writable register that selects the clock
input to TCNT and controls PWM output.
TCR is initialized to H'38 by a reset and in standby mode.
Bit 7—Output Enable (OE): Starts or stops TCNT and controls PWM output.
Bit 7
OE Description
0 PWM output is disabled and the TCNT value is cleared to 0 (Initial value)
1 PWM output is enabled and TCNT is counting
Bit 6—Output Select (OS): Selects direct or inverted PWM output.
Bit 6
OS Description
0 Direct PWM output (Initial value)
1 Inverted PWM output
Rev. 3.0, 02/99, page 367 of 904

Bits 2 to 0—Clock Select (CKS2 to CKS0): These bits select one of eight internal clock sources,
obtained by dividing the system clock (φ), for input to TCNT.
Bit 2 Bit 1 Bit 0

CKS2 CKS1 CKS0 Description
0 0 0 φ/2 (Initial value)
0 0 1 φ/8
0 1 0 φ/32
0 1 1 φ/128
1 0 0 φ/256
1 0 1 φ/1024
1 1 0 φ/2048
1 1 1 φ/4096
The PWM resolution, period, and frequency can be calculated as follows from the frequency of
the selected internal clock source.
Resolution = 1/(internal clock frequency)

PWM period = resolution × 250
PWM frequency = 1/(PWM period)
Table 12-3 lists the resolution, PWM period, and PWM frequency for each clock source when the
system clock frequency (φ) is 10 MHz.
Table 12-3 PWM Period and Resolution
Internal Clock Frequency Resolution PWM Period PWM Frequency

φ/2 200 ns 50 µs 20 kHz
φ/8 800 ns 200 µs 5 kHz
φ/32 3.2 µs 800 µs 1.25 kHz
φ/128 12.8 µs 3.2 ms 312.5 Hz
φ/256 25.6 µs 6.4 ms 156.3 Hz
φ/1024 102.4 µs 25.6 ms 39.1 Hz
φ/2048 204.8 µs 51.2 ms 19.5 Hz
φ/4096 409.6 µs 102.4 ms 9.8 Hz
Rev. 3.0, 02/99, page 368 of 904

12.3 PWM Timer Operation
PWM timer operation is described below. Figure 12-2 shows a timing diagram.
(1) Direct Output (OS = 0)
• When OE = 0 [(a) in figure 12-2]

The timer count is held at H'00 and PWM output is disabled. The pin state depends on the port
data register (DR) and data direction register (DDR) settings. A value (N) written in DTR
becomes valid immediately.
• When OE is set to 1
 TCNT begins counting up, and the PWM output goes to the 1 state. [(b) in figure 12-2]
 When the count reaches the DTR value, the PWM output goes to the 0 state. [(c) in figure
12-2]
 If the DTR value is changed (by writing M), the new value becomes valid after TCNT
changes from H'F9 to H'00. [(d) in figure 12-2]
(2) Inverted Output (OS = 1): The PWM output is inverted. [(e) in figure 12-2]
Rev. 3.0, 02/99, page 369 of 904

Rev. 3.0, 02/99, page 370 of 904
φ
TCNT input
clock
OE
Figure 12-2 PWM Operation Timing
N-1 N+1
TCNT (a) H'00 (b) H'01 H'02 N H'F9 (d) H'00 H'01
(c)
DTR H'FF N (d) M
Write N in DTR Write M in DTR
(a) (b) (c)

*
(OS = 0)
PWM output
*
(OS = 1)
(e)
Note: * State determined by port DR and DDR settings.

12.4 Usage Notes
When using the PWM timers, note the following points.
To use port 6, 7, or A for PWM output, first set the appropriate bit (PWM1E, PWM2E, or
PWM3E) to 1 in P67CR or PACR. Each of these bits can be set independently.
The H8/538 has no PWM timers.
• Any necessary changes to bits CKS2 to CKS0 and OS should be made before the OE bit is set
to 1.
• If the DTR value is H'00, the duty cycle is 0% (always 0). If the DTR value is H'FA to H'FF,
the duty cycle is 100% (always 1).
For inverted output, these output levels are inverted.
Rev. 3.0, 02/99, page 371 of 904

Section 13 Watchdog Timer
13.1 Overview
System operation can be monitored by the on-chip watchdog timer (WDT, one channel). The
WDT can generate a reset signal for the entire chip if a system crash allows the timer counter
(TCNT) to overflow. When this watchdog function is not needed, the WDT can be used as an
interval timer. In interval timer operation, an IRQ0 interrupt is requested at each counter overflow.
The WDT is also used in recovering from software standby mode.
13.1.1 Features
WDT features are listed below.
• Selection of eight counter clock sources

• Interval timer option
• Timer counter overflow generates a reset signal or interrupt
The reset signal is generated in watchdog timer operation. An IRQ0 interrupt is requested in
interval timer operation.
• Overflow reset signal resets the entire chip internally, and can also be output externally
The reset signal generated by timer counter overflow during watchdog timer operation resets
the entire chip internally. If enabled by the reset output enable bit, an external reset signal can
be output to reset other system devices simultaneously, in the H8/539F (dual power source
model).
The H8/539F S-mask and A-mask models (single power source) do not have a reset external
output function.
Rev. 3.0, 02/99, page 373 of 904

Figure 13-1 shows a block diagram of the WDT.
Overflow
Internal
Interrupt signal Interrupt TCNT data bus
Read/
control write
IRQ0
control
(interval timer) TCSR
Internal clock sources

φ/2
RSTCSR φ/32
φ/64
Clock Clock φ/128
Reset Reset control
select φ/256
(internal *, external) φ/512
φ/2048
φ/4096
Legend
TCNT: Timer counter
TCSR: Timer control/status register
RSTCSR: Reset control/status register
Note:* The H8/539F dual power source model has an external reset output function,
but the H8/539F S-mask and A-mask models (single power source) do not.
Figure 13-1 WDT Block Diagram
Table 13-1 summarizes the WDT registers.
Table 13-1 WDT Registers
Address
Write Read Name Abbreviation R/W Initial Value
H'FF10 H'FF10 Timer control/status register TCSR R/(W)* H'18
H'FF11 Timer counter TCNT R/W H'00
H'FF1F Reset control/status register RSTCSR R/(W)* H'3F
Note: * Software can write 0 in bit 7 to clear the flag, but cannot write 1.
Rev. 3.0, 02/99, page 374 of 904

The watchdog timer has three registers, which are described next.
13.2.1 Timer Counter
The timer counter (TCNT) is an eight-bit readable and writable* up-counter. The TCNT bit
structure is shown next.
Bit 7 6 5 4 3 2 1 0
When the timer enable bit (TME) in the timer control/status register (TCSR) is set to 1, the timer
counter starts counting pulses of an internal clock source selected by clock select bits 2 to 0
(CKS2 to CKS0) in TCSR. When the count overflows (changes from H'FF to H'00), an overflow
flag (OVF) in TCSR is set to 1. The timer count is initialized to H'00 by a reset and when the
TME bit is cleared to 0.
Note: * TCNT is write-protected by a password. See section 13.2.4, "Notes on Register Access"
for details.
Rev. 3.0, 02/99, page 375 of 904

13.2.2 Timer Control/Status Register
The timer control/status register (TCSR) is an eight-bit readable and partly writable* register.
Its functions include selecting the timer mode and clock source. The TCSR bit structure is shown
next.
Note: * TCSR is write-protected by a password. See section 13.2.4 "Notes on Register Access"
for details.
Bit 7 6 5 4 3 2 1 0
OVF WT/IT TME − − CKS2 CKS1 CKS0
R/W R/(W)* R/W R/W − − R/W R/W R/W
Clock select bits

These bits select the
TCNT clock source
Reserved bits
Timer enable bit

Enables and disables the timer
Timer mode select bit

Selects the mode
Overflow flag
Status flag indicating overflow
Note: * Software can write 0 in bit 7 to clear the flag, but cannot write 1.
Bits 7 to 5 are initialized to 0 by a reset, in hardware standby mode, and in software standby mode.
Bits 2 to 0 are initialized to 0 by a reset and in hardware standby mode, but retain their values in
Rev. 3.0, 02/99, page 376 of 904

Bit 7—Overflow Flag (OVF): This status flag indicates that the timer counter has overflowed
from H'FF to H'00 in interval timer mode. When OVF = 1, an IRQ0 interrupt is requested.
Bit 7
OVF Description
0 Cleared by reading OVF after it has been set to 1, (Initial value)
then writing 0 in OVF
1 Set when TCNT overflows
Bit 6—Timer Mode Select (WT/,7 ,7):

,7 Selects whether to use the WDT as a watchdog timer or
interval timer. If used as an interval timer (WT/,7 = 0), the WDT generates an IRQ0 interrupt
request when the timer counter (TCNT) overflows. If used as a watchdog timer (WT/,7 = 1), the
WDT generates a reset when the timer counter (TCNT) overflows.
Bit 6
,7
WT/,7 Description
0 Interval timer: IRQ0 interrupt request (Initial value)
1 Watchdog timer: reset request
Bit 5—Timer Enable (TME): Enables or disables the timer counter (TCNT). Always clear TME
to 0 before entering software standby mode.
Bit 5
TME Description
0 Timer disabled: TCNT is initialized to H'00 and stopped. (Initial value)
1 Timer enabled: TCNT starts counting.
Rev. 3.0, 02/99, page 377 of 904

Bits 2 to 0—Clock Select 2 to 0 (CKS2/1/0): These bits select one of eight internal clock sources
for input to TCNT. The clock signals are obtained by prescaling the system clock (φ). The
overflow interval listed in the following table is the time from when TCNT begins counting from
H'00 until an overflow occurs. When the WDT operates as an interval timer, IRQ0 interrupts are
requested at this interval. Set CKS2 to CKS0 to the clock settling time before entering software
standby mode.
Bit 2 Bit 1 Bit 0 Description

CKS2 CKS1 CKS0 Clock Source Overflow Interval (φ = 10 MHz)
0 0 0 φ/2 51.2 µs (Initial value)
0 0 1 φ/32 819.2 µs
0 1 0 φ/64 1.6 ms
0 1 1 φ/128 3.3 ms
1 0 0 φ/256 6.6 ms
1 0 1 φ/512 13.1 ms
1 1 0 φ/2048 52.4 ms
1 1 1 φ/4096 104.9 ms
Rev. 3.0, 02/99, page 378 of 904

13.2.3 Reset Control/Status Register
The H8/539F S-mask and A-mask models (single power source) do not have a 5(62 pin or a
reset external output function. RSTOE in the RSTCSR register can be set and read, but a reset
external output operation is not performed.
The reset control/status register (RSTCSR) is an eight-bit readable and partly writable* register
that indicates when a reset signal has been generated by WDT overflow, and controls external
output of this reset signal.
Note: * RSTCSR is write-protected by a password. See section 13.2.4, "Notes on Register

Access" for details
Bit 7 6 5 4 3 2 1 0
WRST RSTOE − − − − − −
R/W R/(W)* R/W − − − − − −
Reserved bits
Reset output enable bit
Enables or disables external reset signal output
Watchdog timer reset bit

Indicates reset occurrence
Note: * Only a 0 can be written in bit 7 to clear the flag, after first reading the RSTCSR register.
Bits 7 and 6 are initialized by input of a reset signal at the 5(6 pin. They are not initialized by a
reset signal generated by the WDT.
Bit 7—Watchdog Timer Reset (WRST): Indicates that the watchdog timer counter has
overflowed and generated a reset signal. This reset signal resets the entire chip. If the reset output
enable bit (RSTOE)is set to 1, the reset signal is also output (low) at the 5(62 pin to initialize
external system devices.
Rev. 3.0, 02/99, page 379 of 904

Bit 7
WRST Description
0 Cleared to 0 by reset signal input at 5(6 pin, when 0 is written in WRST after
reading WRST = 1 by software (Initial value)
1 Set by TCNT overflow when WDT is used as a watchdog timer, generating areset
signal
Note: If 0 is written in WRST without reading WRST = 1, the WRST bit will not be cleared.
Bit 6—Reset Output Enable (RSTOE): Enables or disables external output at the 5(62 pin* of
the reset signal generated if the timer counter (TCNT) overflows when the WDT is used as a
watchdog timer.
Bit 6
RSTOE Description
0 Reset signal generated by TCNT overflow is not output externally (Initial value)
1 Reset signal generated by TCNT overflow is output externally
Note: * H8/539F (Dual power source model):
The 5(62 pin is an open-drain output pin. Regardless of whether reset output is uesd, the
5(62 pin should be pulled up to Vcc externally. A sample circuit is shown in figure 19-24
in section 19.7, "Flash Memory Programming and Erasing Precautions", and figure 19-28,
section 19.8 "Notes on Mounting Board Development-Handling of VPP and Mode MD2
Pins. " The 5(62 output is multiplexed with Vpp input (the flash memory power supply),
and therefore reset output off-chip must be disabled (by clearing RSTOE to 0) when 12 V is
applied to the Vpp pin. For cautions concerning the 5(62/Vpp pin, see notes 5 and 6 in
section 19.7, "Flash Memory Programming and Erasing Precautions. "
The H8/539F S-mask and A-mask models (single power source) do not have 5(62 pin
function. When set to RSTOE, it is readable but there is no external output reset operation.
13.2.4 Notes on Register Access
The watchdog timer’s TCNT, TCSR, and RSTCSR registers differ from other registers in being
more difficult to write. The procedures for writing and reading these registers are given below.
(1) Writing to TCNT and TCSR: These registers must be written by word access. They cannot
be written by byte instructions. Figure 13-2 shows the format of data written to TCNT and TCSR.
TCNT and TCSR both have the same write address. The write data must be contained in the
lower byte of the written word. The upper byte must contain H'5A (password for TCNT) or H'A5
(password for TCSR). This transfers the write data from the lower byte to TCNT or TCSR.
Rev. 3.0, 02/99, page 380 of 904

<TCNT write>
15 8 7 0
Address H'FF10 H'5A Write data
<TCSR write>
15 8 7 0
Address H'FF10 H'A5 Write data
Figure 13-2 Format of Data Written to TCNT and TCSR
(2) Writing to RSTCSR: RSTCSR must be written by word access. It cannot be written by byte
instructions. Figure 13-3 shows the format of data written to RSTCSR. To write 0 in the WRST
bit, the write data must have H'A5 in the upper byte and H'00 in the lower byte. The H'00 in the
lower byte clears the WRST bit in RSTCSR to 0. To write to the RSTOE bit, the upper byte must
contain H'5A and the lower byte must contain the write data. Writing this word transfers a write
data value into the RSTOE bit.
<Writing 0 in WRST bit>

15 8 7 0
Address H'FF1E H'A5 H'00
<Writing to RSTOE bit>

15 8 7 0
Address H'FF1E H'5A Write data
Figure 13-3 Format of Data Written to RSTCSR
(3) Reading TCNT, TCSR, and RSTCSR: These registers are read like other registers. Byte
access instructions can be used. The read addresses are H'FF10 for TCSR, H'FF11 for TCNT, and
H'FF1F for RSTCSR, as listed in table 13-2.
Table 13-2 Read Addresses of TCNT, TCSR, and RSTCSR
Address Register
H'FF10 TCSR
H'FF11 TCNT
H'FF1F RSTCSR
Rev. 3.0, 02/99, page 381 of 904

13.3 Operation
This section describes operations when the WDT is used as a watchdog timer and as an interval
timer, and the WDT’s function in software standby mode.
13.3.1 Watchdog Timer Operation
Figure 13-4 illustrates watchdog timer operation. To use the WDT as a watchdog timer, set the
WT/,7 and TME bits to 1. Software must prevent TCNT overflow by rewriting the TCNT value
(normally by writing H'00) before overflow occurs. If TCNT fails to be rewritten and overflows
due to a system crash etc., the chip is internally reset for 518 system clock cycles (518φ).
The watchdog reset signal can be externally output from the 5(62* pin to reset external system
devices. The reset signal is output externally for 132 system clock cycles (132φ). External output
can be enabled or disabled by the RSTOE bit in RSTCSR.
A watchdog reset has the same vector as a reset generated by input at the 5(6 pin. Software can
distinguish a 5(6 reset from a watchdog reset by checking the WRST bit in RSTCSR.
If a 5(6 reset and a watchdog reset occur simultaneously, the 5(6 reset always takes priority.
WDT overflow
H'FF
TCNT
count value TME set to 1
H'00
OVF = 1
Start H'00 written Reset H'00 written in TCNT

in TCNT 518φ
RESO pin
Note: The H8/539F S-mask and A-mask models (single
power source) do not have a RESO pin or a reset
external output function. RSTOE in the RSTCSR
register can be set and read, but a reset external 132φ
output operation is not performed.
Figure 13-4 Watchdog Timer Operation
Rev. 3.0, 02/99, page 382 of 904

13.3.2 Interval Timer Operation
Figure 13-5 illustrates interval timer operation. To use the WDT as an interval timer, clear WT/,7
to 0 and set TME to 1. An IRQ0 request is generated each time the timer count overflows. This
function can be used to generate IRQ0 requests at regular intervals.
This IRQ0 interrupt has a different vector from the interrupt requested by ,540 input. Software
does not have to check whether the interrupt request came from the ,540 pin or the interval timer.
H'FF
TCNT
count value
Time t
H'00
WT/IT = 0 IRQ0 IRQ0 IRQ0 IRQ0 IRQ0

TME = 1 request request request request request
Figure 13-5 Interval Timer Operation
Rev. 3.0, 02/99, page 383 of 904

13.3.3 Operation in Software Standby Mode
The watchdog timer has a special function in recovery from software standby mode. WDT
settings required when software standby mode is used are described next.
(1) Before Transition to Software Standby Mode: The TME bit in the timer control/status
register (TCSR) must be cleared to 0 to stop the watchdog timer counter before execution of the
SLEEP instruction. The chip cannot enter software standby mode while the TME bit is set to 1.
Before entering software standby mode, software should also set bits CKS2 to CKS0 in TCSR so
that the overflow interval is equal to or greater than the settling time of the clock oscillator (tOSC2)*.
(2) Recovery from Software Standby Mode: In recovery from software standby mode the WDT
operates as follows.
When an NMI request signal is received, the clock oscillator starts running and the timer counter
(TCNT) starts counting at the rate selected by bits CKS2 to CKS0 in TCSR before software
standby mode was entered. When TCNT overflows (changes from H'FF to H'00), the system
clock (φ) is presumed to be stable and usable, clock signals are supplied to the entire chip,
software standby mode ends, and the NMI interrupt-handling routine starts executing. This timer
overflow does not set the OVF flag in TCSR to 1, and the TME bit remains cleared to 0.
Note: * When using an external clock, make a WDT timer control/status register (TCSR) setting
that will secure the external clock output settling delay time (tDEXT).
Rev. 3.0, 02/99, page 384 of 904

13.3.4 Timing of Setting of Overflow Flag (OVF)
Figure 13-6 shows the timing of setting of the OVF flag in the timer control/status register
(TCSR). The OVF flag is set to 1 when the timer counter overflows. When OVF is set to 1, an
IRQ0 interrupt is requested simultaneously.
TCNT H'FF H'00
OVF
IRQ0 interrupt request

IRQ0
interrupt
Figure 13-6 Timing of Setting of OVF
Rev. 3.0, 02/99, page 385 of 904

13.3.5 Timing of Setting of Watchdog Timer Reset (WRST)
The WRST bit in the reset control/status register (RSTCSR) is valid when WT/,7 = 1 and TME =
1. Figure 13-7 shows the timing of setting of WRST and the internal reset timing. The WRST bit
is set to 1 when the timer count overflows and OVF is set to 1. At the same time an internal reset
signal is generated for the entire chip. This internal reset signal clears OVF, but the WRST bit
remains set to 1. The reset routine must therefore contain an instruction that clears the WRST bit.
TCNT H'FF H'00
OVF
WDT
internal
reset
WRST
Figure 13-7 Timing of Setting of WRST Bit and Internal Reset
Rev. 3.0, 02/99, page 386 of 904

13.4 Usage Notes
Note the following points when using the watchdog timer.
(1) Contention between Timer Counter (TCNT) Write and Increment: If a timer counter
clock pulse is generated during the T3 state of a write cycle to the timer counter, the write takes
priority and the timer counter is not incremented. See figure 13-8.
Write cycle: CPU writes to TCNT
T1 T2 T3
TCNT
Internal write signal
TCNT clock pulse
TCNT N M
Counter write data
Figure 13-8 Contention between TCNT Write and Increment
(2) Changing CKS2 to CKS0 Values: Software should stop the watchdog timer (by clearing the
TME bit to 0) before changing the values of bits CKS2 to CKS0 in the timer control/status register
(TCSR).
Rev. 3.0, 02/99, page 387 of 904

Section 14 Serial Communication Interface
14.1 Overview
The H8/539F has an on-chip serial communication interface (SCI) with three independent
channels. All channels are functionally identical. The SCI supports both asynchronous and
clocked synchronous serial communication. It also has a multiprocessor communication function
for serial communication among two or more processors.
14.1.1 Features
SCI features are listed below.
• Selection of asynchronous or synchronous mode

a. Asynchronous mode
Serial data communication is performed using the start/stop method, in which
synchronization is established character by character.
The SCI can communicate with a UART (Universal Asynchronous Receiver/Transmitter),
ACIA (Asynchronous Communication Interface Adapter), or other chip that employs
standard asynchronous serial communication. It can also communicate with two or more
other processors using the multiprocessor communication function. There are twelve
selectable serial data communication formats.
• Data length: seven or eight bits
• Stop bit length: one or two bits
• Parity: even, odd, or none
• Multiprocessor bit: one or none
• Receive error detection: parity, overrun, and framing errors
• Break detection: by reading the RXD level directly when a framing error occurs
b. Clocked synchronous mode
Serial data communication is synchronized with a clock signal. The SCI can communicate
with other chips having a clocked synchronous communication function.
There is one serial data communication format.
• Data length: eight bits
• Receive error detection: overrun errors
• Full duplex communication
The transmitting and receiving sections are independent, so the SCI can transmit and receive
simultaneously. Both sections use double buffering, so continuous data transfer is possible in
both the transmit and receive directions.
Rev. 3.0, 02/99, page 389 of 904

• Built-in baud rate generator with selectable bit rates
• Internal or external transmit/receive clock source: baud rate generator or SCK pin
• Four types of interrupts
Transmit-data-empty, transmit-end, receive-data-full, and receive-error interrupts are requested
independently. The transmit-data-empty and receive-data-full interrupts can be served by the
on-chip data transfer controller (DTC) to transfer data.
In the H8/539F, SCI2 and SCI3 have the same interrupt vectors.
Figure 14-1 shows a block diagram of the SCI.
Internal data bus

Bus interface
Module data bus
RDR TDR SSR BRR
SCR
φ
RSR TSR SMR Baud rate φ//4
RXD
generator φ/16
Transmit/ φ/64
receive control
TXD
Parity generation Clock
Parity check
External clock
SCK
TEI
TXI
Legend RXI
RSR: Receive shift register ERI
RDR: Receive data register
TSR: Transmit shift register
TDR: Transmit data register
SMR: Serial mode register
SCR: Serial control register
SSR: Serial status register
BRR: Bit rate register
Figure 14-1 SCI Block Diagram
Rev. 3.0, 02/99, page 390 of 904

Table 14-1 summarizes the serial communication pins for each SCI channel.
Table 14-1 SCI Pins
Channel Pin Name Abbreviation Input/Output Function

1 Serial clock pin SCK1 Input/output SCI1 clock input/output
Receive data pin RXD1 Input SCI1 receive data input
Transmit data pin TXD1 Output SCI1 transmit data output
Table 14-2 summarizes the SCI registers. These registers select the communication mode
(asynchronous or clocked synchronous), specify the data format and bit rate, and control the
transmitter and receiver sections.
Rev. 3.0, 02/99, page 391 of 904

Table 14-2 Channel 1 Registers
Channel Address Name Abbreviation R/W Initial Value

1 H'FEC8 Serial mode register SMR R/W H'00
H'FEC9 Bit rate register BRR R/W H'FF
H'FECA Serial control register SCR R/W H'00
H'FECB Transmit data register TDR R/W H'FF
H'FECC Serial status register SSR R/(W)* H'84
H'FECD Receive data register RDR R H'00
2 H'FED0 Serial mode register SMR R/W H'00
H'FED1 Bit rate register BRR R/W H'FF
H'FED2 Serial control register SCR R/W H'00
H'FED3 Transmit data register TDR R/W H'FF
H'FED4 Serial status register SSR R/(W)* H'84
H'FED5 Receive data register RDR R H'00
3 H'FEC0 Serial mode register SMR R/W H'00
H'FEC1 Bit rate register BRR R/W H'FF
H'FEC2 Serial control register SCR R/W H'00
H'FEC3 Transmit data register TDR R/W H'FF
H'FEC4 Serial status register SSR R/(W)* H'84
H'FEC5 Receive data register RDR R H'00
Note: * Software can write 0 to clear flags, but cannot write 1.
Rev. 3.0, 02/99, page 392 of 904

14.2.1 Receive Shift Register
The receive shift register (RSR) receives serial data.
Bit 7 6 5 4 3 2 1 0
R/W − − − − − − − −
Data input at the RXD pin are loaded into RSR in the order received, LSB (bit 0) first. In this way
the SCI converts received data to parallel form. When one byte has been received, it is
automatically transferred to the receive data register (RDR). The H8/500 CPU cannot read or
write RSR directly.
14.2.2 Receive Data Register
The receive data register (RDR) stores serial receive data.
Bit 7 6 5 4 3 2 1 0
R/W R R R R R R R R
The SCI completes the reception of one byte of serial data by moving the received data from the
receive shift register (RSR) into RDR for storage. RSR is then ready to receive the next data.
This double buffering allows the SCI to receive data continuously.
The H8/500 CPU can read but not write RDR. RDR is initialized to H'00 by a reset and in the
standby modes.
Rev. 3.0, 02/99, page 393 of 904

14.2.3 Transmit Shift Register
The transmit shift register (TSR) transmits serial data.
Bit 7 6 5 4 3 2 1 0
R/W − − − − − − − −
The SCI loads transmit data from the transmit data register (TDR) into TSR, then transmits the
data serially from the TXD pin, LSB (bit 0) first. After transmitting one data byte, the SCI
automatically loads the next transmit data from TDR into TSR and starts transmitting again. If
TDRE is set to 1, however, the SCI does not load the TDR contents into TSR. The H8/500 CPU
cannot read or write TSR directly.
14.2.4 Transmit Data Register
The transmit data register (TDR) is an eight-bit register that stores data for serial transmission.
Bit 7 6 5 4 3 2 1 0
When the SCI detects that the transmit shift register (TSR) is empty, it moves transmit data written
in TDR into TSR and starts serial transmission. Continuous serial transmission is possible by
writing the next transmit data in TDR during serial transmission from TSR.
The H8/500 CPU can always read and write TDR. TDR is initialized to H'FF by a reset and in the
standby modes.
Rev. 3.0, 02/99, page 394 of 904

14.2.5 Serial Mode Register
The serial mode register (SMR) is an eight-bit register that specifies the SCI serial communication
format and selects the clock source for the baud rate generator.
Bit 7 6 5 4 3 2 1 0
C/A CHR PE O/E STOP MP CKS1 CKS0
Clock select 1/0

These bits select
the baud rate
generatorÕs clock
source
Multiprocessor mode
Selects the multipro-
cessor function
Stop bit length

Selects stop bit length
Parity mode
Selects even or odd parity
Parity enable
Selects whether data includes a parity bit
Character length
Selects data length in asynchronous mode
Communication mode
Selects asynchronous or clocked synchronous mode
The H8/500 CPU can always read and write SMR. SMR is initialized to H'00 by a reset and in the
standby modes.
Rev. 3.0, 02/99, page 395 of 904

Bit 7—Communication Mode (C/A): Selects whether the SCI operates in asynchronous or
clocked synchronous mode.
Bit 7
$
C/$ Description
0 Asynchronous mode (Initial value)
1 Clocked synchronous mode
Bit 6—Character Length (CHR): Selects seven-bit or eight-bit data in asynchronous mode. In
clocked synchronous mode the data length is always eight bits, regardless of the CHR setting.
Bit 6
CHR Description
0 Eight-bit data (Initial value)
1 Seven-bit data*
Note: * When seven-bit data is selected, the MSB of the transmit data register (bit 7) is not
transmitted.
Bit 5—Parity Enable (PE): Selects whether to add a parity bit to transmit data and check parity
of receive data, in asynchronous mode. In clocked synchronous mode the parity bit is neither
added nor checked, regardless of the PE setting.
Bit 5
PE Description
0 Parity bit not added or checked (Initial value)
1 Parity bit added and checked*
Note: * When PE is set to 1 an even or odd parity bit is added to transmit data, depending on the
parity mode (O/() setting. Receive data parity is checked according to the even/odd (O/()
mode setting.
Rev. 3.0, 02/99, page 396 of 904

Bit 4—Parity Mode (O/( (): Selects even or odd parity when parity bits are added and checked.
The O/#( setting is used only in asynchronous mode and only when the parity enable bit (P#() is
set to 1 to enable parity generation and checking. The O/E setting is ignored in clocked
synchronous mode, or in asynchronous mode when parity is disabled.
Bit 4
(
O/( Description
1
0 Even parity* (Initial value)
2
1 Odd parity*
Notes: 1. If even parity is selected, the parity bit added to transmit data makes an even number of
1s in the transmitted character and parity bit combined. Receive data must have an
even number of 1s in the received character and parity bit combined.
2. If odd parity is selected, the parity bit added to transmit data makes an odd number of
1s in the transmitted character and parity bit combined. Receive data must have an
odd number of 1s in the received character and parity bit combined.
Bit 3—Stop Bit Length (STOP): Selects one or two bits as the stop bit length in asynchronous
mode. This setting is used only in asynchronous mode. It is ignored in clocked synchronous
mode because no stop bits are added.
Bit 3
STOP Description
1
0 One stop bit* (Initial value)
2
1 Two stop bits*
Notes: 1. In transmitting, a single 1 bit (Stop bit) is added at the end of each transmitted
character.
2. In transmitting, two 1 bits (Stop bit) are added at the end of each transmitted character.
In receiving, only the first stop bit is checked, regardless of the STOP bit setting. If the second
stop bit is 1 it is treated as a stop bit. If the second stop bit is 0 it is treated as the start bit of the
next incoming character.
Rev. 3.0, 02/99, page 397 of 904

Bit 2—Multiprocessor Mode (MP): Selects a multiprocessor format. When a multiprocessor
format is selected, settings of the parity enable (PE) and parity mode (O/#() bits are ignored. The
MP bit setting is used only in asynchronous mode; it is ignored in clocked synchronous mode. For
the multiprocessor communication function, see section 14.3.4, "Multiprocessor Communication."
Bit 2
MP Description
0 Multiprocessor function disabled (Initial value)
1 Multiprocessor format selected
Bits 1 and 0—Clock Select 1 and 0 (CKS1/0): These bits select the internal clock source of the
on-chip baud rate generator. Four clock sources are available: φ, φ/4, φ/16, and φ/64. For further
information on the clock source, bit rate register settings, and bit rate, see section 14.2.8, "Bit Rate
Register."
Bit 1 Bit 0
CKS1 CKS0 Description
0 0 System clock (φ) (Initial value)
0 1 φ/4
1 0 φ/16
1 1 φ/64
Rev. 3.0, 02/99, page 398 of 904

14.2.6 Serial Control Register
The serial control register (SCR) enables the SCI transmitter and receiver, selects serial clock
output in asynchronous mode, enables and disables interrupts, and selects the transmit/receive
clock.
Bit 7 6 5 4 3 2 1 0
TIE RIE TE RE MPIE TEIE CKE1 CKE0
Clock enable 1/0

Selects the SCI
clock source
Transmit end interrupt

enable
Enables and disables
transmit-end interrupts
(TEI)
Multiprocessor interrupt enable

Enables and disables multiprocessor
interrupts
Receive enable
Enables and disables the receiver
Transmit enable
Enables and disables the transmitter
Receive interrupt enable
Enables and disables receive-data-full interrupts (RXI)
and receive error interrupts (ERI)
Transmit interrupt enable

Enables and disables transmit-data-empty interrupts (TXI)
The H8/500 CPU can always read and write SCR. SCR is initialized to H'00 by a reset and in the
standby modes.
Rev. 3.0, 02/99, page 399 of 904

Bit 7-Transmit Interrupt Enable (TIE): Enables or disables the transmit-data-empty interrupt
(TXI) requested when the transmit data register empty bit (TDRE) in the serial status register
(SSR) is set to 1 due to transfer of serial transmit data from TDR to TSR.
Bit 7
TIE Description
0 Transmit-data-empty interrupt request (TXI) is disabled* (Initial value)
1 Transmit-data-empty interrupt request (TXI) is enabled
Note: * The TXI interrupt request can be cleared by reading TDRE after it has been set to 1, then
clearing TDRE to 0, or by clearing TIE to 0.
Bit 6-Receive Interrupt Enable (RIE): Enables or disables the receive-data-full interrupt (RXI)
requested when the receive data register full bit (RDRF) in the serial status register (SSR) is set to
1 due to transfer of serial receive data from RSR to RDR. Also enables or disables receive-error
interrupt (ERI) requests.
Bit 6
RIE Description
0 Receive-data-full interrupt (RXI) and receive-error interrupt (ERI) (Initial value)
requests are disabled*
1 Receive-data-full interrupt (RXI) and receive-error interrupt (ERI)
requests are enabled
Note: * RXI and ERI interrupt requests can be cleared by reading the RDRF flag or error flag (FER,
PER, or ORER) after it has been set to 1, then clearing the flag to 0, or by clearing RIE to 0.
Bit 5-Transmit Enable (TE): Enables or disables the SCI transmitter.
Bit 5
TE Description
1
0 Transmitter disabled* , TXD pin available for general-purpose I/O (Initial value)
2
1 Transmitter enabled* , TXD used for transmit data output
Notes: 1. The transmit data register empty bit (TDRE) in the serial status register (SSR) is locked
at 1.
2. Serial transmitting starts when the transfer data register empty (TDRE) bit in the serial
status register (SSR) is cleared to 0 after writing of transmit data into TDR. Select the
transmit format in SMR before setting TE to 1.
Rev. 3.0, 02/99, page 400 of 904

Bit 4-Receive Enable (RE): Enables or disables the SCI receiver.
Bit 4
RE Description
1
0 Receiver disabled* , RXD pin available for general-purpose I/O (Initial value)
2
1 Receiver enabled* , RXD used for receive data input
Notes: 1. Clearing RE to 0 does not affect the receive flags (RDRF, FER, PER, ORER). These
flags retain their previous values.
2. Serial receiving starts when a start bit is detected in asynchronous mode, or serial clock
input is detected in clocked synchronous mode. Select the receive format in SMR
before setting RE to 1.
Bit 3-Multiprocessor Interrupt Enable (MPIE): Enables or disables multiprocessor interrupts.

The MPIE setting is used only in asynchronous mode, and only if the multiprocessor mode bit
(MP) in the serial mode register (SMR) is set to 1. The MPIE setting is ignored in clocked
synchronous mode or when the MP bit is cleared to 0.
Bit 3
MPIE Description
0 Multiprocessor interrupts are disabled (normal receive operation) (Initial value)
1 Multiprocessor interrupts are enabled.*
Until data is received in which the multiprocessor bit set to 1
receive-data-full interrupt requests (RXI), receive-error interrupt
requests (ERI), and setting of the RDRF, FER, and ORER status
flags in the serial status register (SSR) are disabled.
MPIE is cleared to 0 when:
1. MPIE is cleared to 0, or
2. Multiprocessor bit (MPB) is set to 1 in receive data.
Note: * The SCI does not transfer receive data from RSR to RDR, does not detect receive errors,
and does not set the RDRF, FER, and ORER flags in the serial status register (SSR).
When it receives data with the multiprocessor bit (MPB) set to 1, the SCI automatically
clears MPIE to 0, enables RXI and ERI interrupts (if the TIE and RIE bits in SCR are set to
1), and allows FER and ORER to be set.
Rev. 3.0, 02/99, page 401 of 904

Bit 2-Transmit-End Interrupt Enable (TEIE): Enables or disables the transmit-end interrupt
(TEI) requested if TDR does not contain effective transmit data when the MSB is transmitted.
Bit 2
TEIE Description
0 Transmit-end interrupt (TEI) requests are disabled* (Initial value)
1 Transmit-end interrupt (TEI) requests are enabled*
Note: * The TEI request can be cleared by reading the TDRE bit in the serial status register (SSR)
after it has been set to 1, then clearing TDRE to 0, thereby clearing the transmit end
(TEND) bit to 0; or by clearing the TEIE bit to 0.
Bits 1 and 0-Clock Enable 1 and 0 (CKE1/0): These bits select the SCI clock source and enable
or disable clock output from the SCK pin. Depending on the combination of CKE1 and CKE0,
the SCK pin can be used for general-purpose input/output, serial clock output, or serial clock
input.
The CKE0 setting is valid only in asynchronous mode, and only when the SCI is internally
clocked (CKE1 = 0). The CKE0 setting is ignored in clocked synchronous mode, or when an
external clock source is selected (CKE1 = 1). Select the SCI operating mode in the serial mode
register (SMR) before setting CKE1 and CKE0. For further details on selection of the SCI clock
source, see table 14-9 in section 14.3, "Operation."
Bit 1 Bit 0
CKE1 CKE0 Description
0 0 Asynchronous mode Internal clock, SCK pin available for general-
1
purpose input/output*
Clocked synchronous mode Internal clock, SCK pin used for serial clock
1
output*
2
0 1 Asynchronous mode Internal clock, SCK pin used for clock output*
Clocked synchronous mode Internal clock, SCK pin used for serial clock
output
3
1 0 Asynchronous mode External clock, SCK pin used for clock input*
Clocked synchronous mode External clock, SCK pin used for serial clock input
3
1 1 Asynchronous mode External clock, SCK pin used for clock input*
Clocked synchronous mode External clock, SCK pin used for serial clock input
Notes: 1. Initial value
2. The output clock frequency is the same as the bit rate.
3. The input clock frequency is 16 times the bit rate.
Rev. 3.0, 02/99, page 402 of 904

14.2.7 Serial Status Register
The serial status register (SSR) is an eight-bit register containing multiprocessor bit values, and
status flags that indicate SCI operating status.
The H8/500 CPU can always read and write SSR, but cannot write 1 in the status flags (TDRE,
RDRF, ORER, PER, and FER). These flags can be cleared to 0 only if they have first been read
after being set to 1. Bits 2 (TEND) and 1 (MPB) are read-only bits and cannot be written.
Bit 7 6 5 4 3 2 1 0
TDRE RDRF ORER FER PER TEND MPB MPBT
R/W R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R R R/W
Multiprocessor
bit transfer
Value of multi-
processor bit to
be transmitted
Multiprocessor bit
Stores received multi-
processor bit value
Transmit end
Status flag indicating end
of transmission
Parity error
Status flag indicating detection
of a receive parity error
Framing error
Status flag indicating detection of a receive
framing error
Overrun error
Status flag indicating detection of a receive overrun error
Receive data register full
Status flag indicating that the SCI has stored receive data in RDR
Transmit data register empty
Status flag indicating that the SCI has loaded transmit data
from TDR into TSR and new data can be written in TDR
Note: * Software can write 0 to clear the flag, but cannot write 1.
SSR is initialized to H'84 by a reset and in the standby modes.
Rev. 3.0, 02/99, page 403 of 904

Bit 7—Transmit Data Register Empty (TDRE): Indicates that the SCI has loaded transmit data
from TDR into TSR and new data can be written in TDR.
Bit 7
TDRE Description
0 TDR contains valid transmit data
TDRE is cleared to 0 when:
1. Software reads TDRE after it has been set to 1, then writes 0 in TDRE
2. The DTC writes data in TDR
1 TDR does not contain valid transmit data (Initial value)
TDRE is set to 1 when:
1. The chip is reset or enters standby mode
2. The TE bit in the serial control register (SCR) is cleared to 0, or
3. TDR contents are loaded into TSR, so new data can be written in TDR
Bit 6—Receive Data Register Full (RDRF): Indicates that RDR contains new receive data.
Bit 6
RDRF Description
0 RDR does not contain new receive data (Initial value)
RDRF is cleared to 0 when:
2. Software reads RDRF after it has been set to 1, then writes 0 in RDRF
3. The DTC reads data from RDR
1 RDR contains new receive data
RDRF is set to 1 when serial data are received normally and transferred from RSR
to RDR.
Note: RDR and RDRF are not affected by detection of receive errors or by clearing of the RE bit
to 0 in the serial control register. They retain their previous contents. If RDRF is still set to
1 when reception of the next data ends, an overrun error (ORER) occurs and receive data
is lost.
Rev. 3.0, 02/99, page 404 of 904

Bit 5—Overrun Error (ORER): Indicates that data reception ended
abnormally due to an overrun error.
Bit 5
ORER Description
1
0 Receiving is in progress or has ended normally (Initial value)*
ORER is cleared to 0 when:
2. Software reads ORER after it has been set to 1, then writes 0 in ORER
2
1 A receive overrun error occurred*
ORER is set to 1 if reception of the next serial data ends when RDRF is set to 1
Notes: 1. Clearing the RE bit to 0 in the serial control register does not affect the ORER bit, which
retains its previous value.
2. RDR continues to hold the receive data before the overrun error, so subsequent receive
data are lost. Serial receiving cannot continue while ORER is set to 1. In clocked
synchronous mode, serial transmitting is also disabled.
Bit 4—Framing Error (FER): Indicates that data reception ended abnormally due to a framing
error in asynchronous mode.
Bit 4
FER Description
1
0 Receiving is in progress or has ended normally (Initial value)*
FER is cleared to 0 when:
2. Software reads FER after it has been set to 1, then writes 0 in FER
1 A receive framing error occurred
FER is set to 1 if the stop bit at the end of receive data is checked and found to be
2
0* .
Notes: 1. Clearing the RE bit to 0 in the serial control register does not affect the FER bit, which
2. When the stop bit length is two bits, only the first bit is checked. The second stop bit is
not checked. When a framing error occurs the SCI transfers the receive data into RDR
but does not set RDRF. Serial receiving cannot continue while FER is set to 1. In
clocked synchronous mode, serial transmitting is also disabled.
Rev. 3.0, 02/99, page 405 of 904

Bit 3—Parity Error (PER): Indicates that data reception ended abnormally due to a parity error
in asynchronous mode.
Bit 3
PER Description
1
0 Receiving is in progress or has ended normally)* (Initial value)
PER is cleared to 0 when:
2. Software reads PER after it has been set to 1, then writes 0 in PER
2
1 A receive parity error occurred* .
PER is set to 1 if the number of 1s in receive data, including the parity bit, does not
match the even or odd parity setting of the parity mode bit (O/E) in the serial mode
register (SMR).
Notes: 1. Clearing the RE bit to 0 in the serial control register does not affect the PER bit, which
2. When a parity error occurs the SCI transfers the receive data into RDR but does not set
RDRF. Serial receiving cannot continue while PER is set to 1. In clocked synchronous
mode, serial transmitting is also disabled.
Bit 2—Transmit End (TEND): Indicates that when the last bit of a serial character was
transmitted TDR did not contain new transmit data, so transmission has ended. TEND is a read-
only bit and cannot be written.
Bit 2
TEND Description
0 Transmission is in progress
TEND is cleared to 0 when:
1. Software reads TDRE after it has been set to 1, then writes 0 in TDRE
2. The DTC writes data in TDR
1 End of transmission (Initial value)
TEND is set to 1 when:
2. TE is cleared to 0 in the serial control register (SCR)
3. TDRE is 1 when the last bit of a serial character (1 byte) is transmitted
Rev. 3.0, 02/99, page 406 of 904

Bit 1—Multiprocessor Bit (MPB): Stores the value of the multiprocessor bit in receive data
when a multiprocessor format is used in asynchronous mode. MPB is a read-only bit and cannot
be written.
Bit 1
MPB Description
0 Multiprocessor bit value in receive data is 0* (Initial value)
1 Multiprocessor bit value in receive data is 1
Note: * If RE is cleared to 0 when a multiprocessor format is selected, MPB retains its previous
value.
Bit 0—Multiprocessor Bit Transfer (MPBT): Stores the value of the multiprocessor bit added to
transmit data when a multiprocessor format is selected for transmitting in asynchronous mode.
The MPBT setting is ignored in clocked synchronous mode, when a multiprocessor format is not
selected, or when the SCI is not transmitting.
Bit 0
MPBT Description
0 Multiprocessor bit value in transmit data is 0 (Initial value)
1 Multiprocessor bit value in transmit data is 1
Rev. 3.0, 02/99, page 407 of 904

14.2.8 Bit Rate Register
The bit rate register (BRR) is an eight-bit register that, together with the CKS1 and CKS0 bits in
the serial mode register (SMR) that select the baud rate generator clock source, determines the
serial transmit/receive bit rate.
Bit 7 6 5 4 3 2 1 0
The H8/500 CPU can always read and write BRR. BRR is initialized to H'FF by a reset and in the
standby modes. SCI1 and SCI2 have independent baud rate generator control, so different values
can be set in the two channels.
Table 14-3 shows examples of BRR settings in asynchronous mode.
Table 14-3 Examples of Bit Rates and BRR Settings in Asynchronous Mode (1)
φ (MHz)
1 1.2288 2 2.097152
Bit Rate Error Error Error Error
(bits/s) n N (%) n N (%) n N (%) n N (%)
110 1 70 +0.03 1 86 +0.31 1 141 +0.03 1 148 -0.04
150 0 207 +0.16 0 255 0 1 103 +0.16 1 108 +0.21
300 0 103 +0.16 0 127 0 0 207 +0.16 0 217 +0.21
600 0 51 +0.16 0 63 0 0 103 +0.16 0 108 +0.21
1200 0 25 +0.16 0 31 0 0 51 +0.16 0 54 -0.70
2400 0 12 +0.16 0 15 0 0 25 +0.16 0 26 +1.14
4800 − − − 0 7 0 0 12 +0.16 0 13 -2.48
9600 − − − 0 3 0 − − − − − −
19200 − − − 0 1 0 − − − − − −
31250 0 0 0.00 − − − 0 1 0 − − −
38400 − − − 0 0 0 − − − − − −
Rev. 3.0, 02/99, page 408 of 904

φ (MHz)
2.4576 3 3.6864 4
(bits/s) n N (%) n N (%) n N (%) n N (%)
110 1 174 -0.26 1 212 +0.03 2 64 +0.70 2 70 +0.03
150 1 127 0 1 155 +0.16 1 191 0 1 207 +0.16
300 0 255 0 1 77 +0.16 1 95 0 1 103 +0.16
600 0 127 0 0 155 +0.16 0 191 0 0 207 +0.16
1200 0 63 0 0 77 +0.16 0 95 0 0 103 +0.16
2400 0 31 0 0 38 +0.16 0 47 0 0 51 +0.16
4800 0 15 0 0 19 -2.34 0 23 0 0 25 +0.16
9600 0 7 0 0 9 -2.34 0 11 0 0 12 +0.16
19200 0 3 0 0 4 -2.34 0 5 0 − − −
31250 − − − 0 2 0 − − − 0 3 0
38400 0 1 0 − − − 0 2 0 − − −
φ (MHz)
4.9152 5 6 6.144
(bits/s) n N (%) n N (%) n N (%) n N (%)
110 2 86 +0.31 2 88 -0.25 2 106 -0.44 2 108 +0.08
150 1 255 0 2 64 +0.16 2 77 0 2 79 0
300 1 127 0 1 129 +0.16 1 155 0 1 159 0
600 0 255 0 1 64 +0.16 1 77 0 1 79 0
1200 0 127 0 0 129 +0.16 0 155 +0.16 0 159 0
2400 0 63 0 0 64 +0.16 0 77 +0.16 0 79 0
4800 0 31 0 0 32 -1.36 0 38 +0.16 0 39 0
9600 0 15 0 0 15 +1.73 0 19 -2.34 0 19 0
19200 0 7 0 0 7 +1.73 − − − 0 9 0
31250 0 4 -1.70 0 4 0 0 5 0 0 5 +2.40
38400 0 3 0 0 3 +1.73 − − − 0 4 0
Rev. 3.0, 02/99, page 409 of 904

φ (MHz)
7.3728 8 9.8304 10
(bits/s) n N (%) n N (%) n N (%) n N (%)
110 2 130 -0.07 2 141 +0.03 2 174 -0.26 3 43 +0.88
150 2 95 0 2 103 +0.16 2 127 0 2 129 +0.16
300 1 191 0 1 207 +0.16 1 255 0 2 64 +0.16
600 1 95 0 1 103 +0.16 1 127 0 1 129 +0.16
1200 0 191 0 0 207 +0.16 0 255 0 1 64 +0.16
2400 0 95 0 0 103 +0.16 0 127 0 0 129 +0.16
4800 0 47 0 0 51 +0.16 0 63 0 0 64 +0.16
9600 0 23 0 0 25 +0.16 0 31 0 0 32 -1.36
19200 0 11 0 0 12 +0.16 0 15 0 0 15 +1.73
31250 − − − 0 7 0 0 9 -1.70 0 9 0
38400 0 5 0 − − − 0 7 0 0 7 +1.73
307200 − − − − − − 0 0 0 − − −
312500 − − − − − − − − − 0 0 0
Rev. 3.0, 02/99, page 410 of 904

φ (MHz)
12 12.288 14 14.7456
(bits/s) n N (%) n N (%) n N (%) n N (%)
110 2 212 0.03 2 217 0.08 2 248 - 0.17 3 64 0.07
150 2 155 0.16 2 159 0.00 2 181 0.16 2 191 0.00
300 2 77 0.16 2 79 0.00 2 90 0.16 2 95 0.00
600 1 155 0.16 1 159 0.00 1 181 0.16 1 191 0.00
1200 1 77 0.16 1 79 0.00 1 90 0.16 1 95 0.00
2400 0 155 0.16 0 159 0.00 0 181 0.16 0 191 0.00
4800 0 77 0.16 0 79 0.00 0 90 0.16 0 95 0.00
9600 0 38 0.16 0 39 0.00 0 45 -0.93 0 47 0.00
19200 0 19 -2.34 0 19 0.00 0 22 -0.93 0 23 0.00
31250 0 11 0.00 0 11 2.40 0 13 0.00 0 14 -1.70
38400 0 9 -2.34 0 9 0.00 0 10 3.57 0 11 0.00
Rev. 3.0, 02/99, page 411 of 904

φ (MHz)
16
Bit Rate Error
(bits/s) n N (%)
110 3 70 0.03
150 2 207 0.16
300 2 103 0.16
600 1 207 0.16
1200 1 103 0.16
2400 0 207 0.16
4800 0 103 0.16
9600 0 51 0.16
19200 0 25 0.16
31250 0 15 0.00
38400 0 12 0.16
Notes: 1. Settings with an error of 1% or less are recommended.
2. The BRR setting is calculated as follows:
N = [φ/(64 × 2 × B)] × 10 - 1
2n-1 6
B: Bit rate
N: BRR setting for baud rate generator (0 ≤ N ≤ 255)
φ: Operation frequency (MHz)
n: Baud rate generator clock source (n = 0, 1, 2, 3)
(For the clock sources and values of n, see table 14-4.)
Table 14-4 Clock Sources and n
SMR Settings
n Clock Source CKS1 CKS0
0 φ 0 0
1 φ/4 0 1
2 φ/16 1 0
3 φ/64 1 1
3. Error is calculated as follows:
Error (%) = {[φ × 10 / (N + 1) × B × 64 ] - 1} × 100
6 2n-1
Rev. 3.0, 02/99, page 412 of 904

Tables 14-5 and 14-6 indicate the maximum bit rates in asynchronous mode for various system
clock frequencies.
Table 14-5 Maximum Bit Rates for Various Frequencies (Asynchronous Mode)
Settings
φ (MHz) Maximum Bit Rate (Bits/s) n N
1 31250 0 0
1.2288 38400 0 0
2 62500 0 0
2.097152 65536 0 0
2.4576 76800 0 0
3 93750 0 0
3.6864 115200 0 0
4 125000 0 0
4.9152 153600 0 0
5 156250 0 0
6 187500 0 0
6.144 192000 0 0
7.3728 230400 0 0
8 250000 0 0
9.8304 307200 0 0
10 312500 0 0
12 375000 0 0
12.288 384000 0 0
14 437500 0 0
14.7456 460800 0 0
16 500000 0 0
17.2032 537600 0 0
18 562500 0 0
19.6608 614400 0 0
20 625000 0 0
Rev. 3.0, 02/99, page 413 of 904

Table 14-6 Maximum Bit Rates with External Clock Input (Asynchronous Mode)
φ (MHz) External Clock Input (MHz) Maximum Bit Rate (Bits/s)

1 0.2500 15625
1.2288 0.3072 19200
2 0.5000 31250
2.097152 0.5243 32768
2.4576 0.6144 38400
3 0.7500 46875
3.6864 0.9216 57600
4 1.0000 62500
4.9152 1.2288 76800
5 1.2500 78125
6 1.5000 93750
6.144 1.5360 96000
7.3728 1.8432 115200
8 2.0000 125000
9.8304 2.4576 153600
10 2.5000 156250
12 3.0000 187500
12.288 3.0720 192000
14 3.5000 218750
14.7456 3.6864 230400
16 4.0000 250000
17.2032 4.3008 268800
18 4.5000 281250
19.6608 4.9152 307200
20 5.0000 312500
Rev. 3.0, 02/99, page 414 of 904

Table 14-7 shows examples of settings in clocked synchronous mode.
Table 14-7 Examples of Bit Rates and BRR Settings in Synchronous Mode
φ (MHz)
1 2 4 8 10 16
Bit Rate (Bits/s) n N n N n N n N n N n N
110 − − 3 70 − − − − − − − −
250 1 249 2 124 2 249 3 124 − − 3 249
500 1 124 1 249 2 124 2 249 − − 3 124
1k 0 249 1 124 1 249 1 124 − − 3 249
2.5 k 0 99 0 199 1 99 1 199 1 249 2 99
5k 0 49 0 99 0 199 1 99 1 124 1 199
10 k 0 24 0 49 0 99 0 199 0 249 1 99
25 k 0 9 0 19 0 39 0 79 0 99 0 159
50 k 0 4 0 9 0 19 0 39 0 49 0 79
100 k − − 0 4 0 9 0 19 0 24 0 39
250 k 0 0* 0 1 0 3 0 7 0 9 0 15
500 k 0 0* 0 1 0 3 0 4 0 7
1M 0 0* 0 1 − − 0 3
2.5 M − − 0 0* − −
Blank: No setting available
−: Setting possible, but error occurs
* : Continuous transmit/receive not possible
Note: The BRR setting is calculated as follows:
N = [φ/(8 × 2 × B)] × 10 - 1
2n-1 6
B: Bit rate
N: BRR setting for baud rate generator (0 ≤ N ≤ 255)
φ: Operation frequency (MHz)
n: Baud rate generator clock source (n = 0, 1, 2, 3)
(For the clock sources and values of n, see table 14-8.)
Rev. 3.0, 02/99, page 415 of 904

Table 14-8 Clock Sources and n
SMR Settings
n Clock Source CKS1 CKS0
0 φ 0 0
1 φ/4 0 1
2 φ/16 1 0
3 φ/64 1 1
Rev. 3.0, 02/99, page 416 of 904

14.3 Operation
14.3.1 Overview
The SCI has an asynchronous mode in which characters are synchronized individually, and a
clocked synchronous mode in which communication is synchronized with clock pulses. Serial
communication is possible in either mode. Asynchronous or clocked synchronous mode and the
communication format are selected in the serial mode register (SMR), as shown in table 14-9. The
SCI clock source is selected by the C/$ bit in the serial mode register (SMR) and the CKE1 and
CKE0 bits in the serial control register (SCR), as shown in table 14-10.
(1) Asynchronous Mode
• Data length is selectable: seven or eight bits.

• Parity and multiprocessor bits are selectable. So is the stop bit length (one or two bits). The
foregoing selections constitute the communication format (The combination of these items
determines the communication format and the character length.).
• In receiving, it is possible to detect framing errors (FER), parity errors (PER), overrun errors
(ORER), and the break state.
• An internal or external clock can be selected as the SCI clock source.
 When an internal clock is selected, the SCI operates using the built-in baud rate generator,
and can output a serial clock signal with a frequency matching the bit rate.
 When an external clock is selected, the external clock input must have a frequency 16 times
the bit rate. (The built-in baud rate generator is not used.)
(2) Clocked Synchronous Mode
• The communication format has a fixed eight-bit data length.

• In receiving, it is possible to detect overrun errors (ORER).
• An internal or external clock can be selected as the SCI clock source.
 When an internal clock is selected, the SCI operates using the built-in baud rate generator,
and outputs a serial clock signal to external devices.
 When an external clock is selected, the SCI operates on the input serial clock. The built-in
baud rate generator is not used.
Rev. 3.0, 02/99, page 417 of 904

Table 14-9 Serial Mode Register Settings and SCI Communication Formats
SMR Settings SCI Communication Format

Bit 7 Bit 6 Bit 5 Bit 2 Bit 3 Multi- Stop
Data processor Bit
$
C/$ CHR PE MP STOP MODE Length Parity Bit Bit Length
0 0 0 0 0 Asynchronous mode 8-bit data Absent Absent 1 bit
1 2 bits
1 0 Present 1 bit
1 2 bits
1 0 0 7-bit data Absent 1 bit
1 2 bits
1 0 Present 1 bit
1 2 bits
0 * 1 0 Asynchronous mode 8-bit data Absent Present 1 bit
* 1 (multiprocessor format) 2 bits
1 * 0 7-bit data 1 bit
* 1 2 bits
1 * * * * Clocked synchronous 8-bit data Absent None
mode
Note: Asterisks (*) in the table indicate don’t-care bits.
Table 14-10 SMR and SCR Settings and SCI Clock Source Selection
SMR SCR Settings SCI Transmit/Receive Clock

Bit 7 Bit 1 Bit 0 Clock
$
C/$ CKE1 CKE0 Mode Source SCK Pin Function
0 0 0 Asynchronous Internal General-purpose input/output (SCI does
mode not use the SCK pin)
1 Outputs a clock with frequency matching
the bit rate
1 0 External Inputs a clock with frequency 16 times the
bit rate
1
1 0 0 Clocked Internal Outputs the serial clock
1 synchronous mode
1 0 External Inputs the serial clock

1
Rev. 3.0, 02/99, page 418 of 904

14.3.2 Operation in Asynchronous Mode
In asynchronous mode each transmitted or received character begins with a start bit and ends with
a stop bit. Serial communication is synchronized one character at a time.
The transmitting and receiving sections of the SCI are independent, so full duplex communication
is possible. The transmitter and receiver are both double buffered, so data can be written and read
while transmitting and receiving are in progress, enabling continuous transmitting and receiving.
Figure 14-2 shows the general format of asynchronous serial communication. In asynchronous
serial communication the communication line is normally held in the mark (high) state. The SCI
monitors the line and starts serial communication when the line goes to the space (low) state,
indicating a start bit. One serial character consists of a start bit (low), data (LSB first), parity bit
(high or low), and stop bit (high), in that order.
When receiving in asynchronous mode, the SCI synchronizes on the falling edge of the start bit.
The SCI samples each data bit on the eighth pulse of a clock with a frequency 16 times the bit rate.
Receive data is latched at the center of each bit.
Mark (idle) state

1 (LSB) (MSB) 1
Serial 0 D0 D1 D2 D3 D4 D5 D6 D7 0/1 1 1
data
Start Parity Stop
bit bit bit
Transmit or receive data
1 bit 7 or 8 bits 1 bit 1 or

or 2 bits
no bit
One data character (frame)
Figure 14-2 Data Format in Asynchronous Communication

(Example: 8-Bit Data with Parity and Two Stop Bits)
Rev. 3.0, 02/99, page 419 of 904

(1) Transmit/Receive Formats: Table 14-11 shows the 12 communication formats that can be
selected in asynchronous mode. The format is selected by settings in the serial mode register
(SMR).
Table 14-11 Serial Communication Formats (Asynchronous Mode)
SMR Settings Serial Communication Format and Frame Length
CHR PE MP STOP 1 2 3 4 5 6 7 8 9 10 11 12
0 0 0 0 S 8-bit data STOP
0 0 0 1 S 8-bit data STOP STOP
0 1 0 0 S 8-bit data P STOP
0 1 0 1 S 8-bit data P STOP STOP
1 0 0 0 S 7-bit data STOP
1 0 0 1 S 7-bit data STOP STOP
1 1 0 0 S 7-bit data P STOP
1 1 0 1 S 7-bit data P STOP STOP
0 * 1 0 S 8-bit data MPB STOP
0 * 1 1 S 8-bit data MPB STOP STOP
1 * 1 0 S 7-bit data MPB STOP
1 * 1 1 S 7-bit data MPB STOP STOP
SMR: serial mode register P: parity bit

S: start bit MPB: multiprocessor bit
STOP: stop bit
Note: Asterisks (*) in the table indicate don't-care bits.
Rev. 3.0, 02/99, page 420 of 904

(2) Clock: An internal clock generated by the on-chip baud rate generator or an external clock
input from the SCK pin can be selected as the SCI transmit/receive clock. The clock source is
selected by the C/$ bit in the serial mode register (SMR) and bits CKE1 and CKE0 in the serial
control register (SCR). See table 14-10.
When an external clock is input at the SCK pin, it must have a frequency equal to 16 times the
desired bit rate.
When the SCI operates on an internal clock, it can output a clock signal at the SCK pin. The
frequency of this output clock is equal to the bit rate. The phase is aligned as in figure 14-3 so that
the rising edge of the clock occurs at the center of each transmit data bit.
SCK
Serial 0 D0 D1 D2 D3 D4 D5 D6 D7 0/1 1 1
data
1 frame
Figure 14-3 Phase Relationship between Output Clock and Serial Data
(Asynchronous Mode)
(3) Transmitting and Receiving Data
SCI Initialization (Asynchronous Mode): Before transmitting or receiving, software must clear
the TE and RE bits to 0 in the serial control register (SCR), then initialize the SCI as follows.
When changing the communication mode or format, always clear the TE and RE bits to 0 before
following the procedure given below. Clearing TE to 0 sets TDRE to 1 and initializes the transmit
shift register (TSR). Clearing RE to 0, however, does not initialize the RDRF, PER, FER, and
OER flags and receive data register (RDR), which retain their previous contents.
When an external clock is used, the clock should not be stopped during initialization or subsequent
operation. SCI operation becomes unreliable if the clock is stopped.
Figure 14-4 is a sample flowchart for initializing the SCI.
Rev. 3.0, 02/99, page 421 of 904

Start of initialization
Clear TE and RE bits to 0 in SCR
Select communication (1) Select the communication format in

(1)
format in SMR the serial mode register (SMR).
(2) Select the clock source in the

Set CKE1 and CKE0 bits in SCR serial control register (SCR).
(2)
(leaving TE and RE cleared to 0) Leave RIE, TIE, TEIE, MPIE, TE,
and RE cleared to 0. If clock
output is selected, clock output
starts immediately after the setting
is made in SCR.
(3) Write the value corresponding to

(3) Set value in BRR the bit rate in the bit rate register
(BRR). (Not necessary when using
an external clock).
Wait
No
1 bit interval elapsed?
Yes (4) Wait for at least the interval

required to transmit or receive one
bit, then set TE or RE in the serial
(4) Set TE or RE to 1 in SCR control register (SCR). Also set
Set RIE, TIE, TEIE, and MPIE RIE, TIE, TEIE, and MPIE.
Setting TE or RE enables the SCI
to use the TXD or RXD pin.
The initial states are the mark
Start transmitting transmit state, and the idle receive
or receiving state (waiting for a start bit).
Figure 14-4 Sample Flowchart for SCI Initialization
Rev. 3.0, 02/99, page 422 of 904

Transmitting Serial Data (Asynchronous Mode): Figure 14-5 shows a sample flowchart for
transmitting serial data and indicates the procedure to follow.
(1) Initialize (1) SCI initialization: the transmit data

output function of the TXD pin is
Start transmitting selected automatically.
(2) Read TDRE bit in SSR (2) SCI status check and transmit data
write: read the serial status
register (SSR), check that the
No TDRE bit is 1, then write transmit
TDRE = 1?
data in the transmit data register
Yes (TDR) and clear TDRE to 0.
Write transmit data in TDR and

clear TDRE bit to 0 in SSR
No
(3) All data transmitted? (3) To continue transmitting serial
data: read the TDRE bit to check
Yes whether it is safe to write; if so,
write data in TDR, then clear
TDRE to 0. When the DTC is
Read TEND bit in SSR started by a transmit-data-empty
interrupt request (TXI) to write data
in TDR, the TDRE bit is checked
No and cleared automatically.
TEND = 1?
Yes
No
(4) Output break signal? (4) To output a break signal at the end
of serial transmission: set the DDR
Yes bit to 1 and the DR bit to 0 (DDR
and DR are I/O port registers),
Set DR = 0, DDR = 1 then clear TE to 0 in SCR.
Clear TE bit in SCR to 0
End
Figure 14-5 Sample Flowchart for Transmitting Serial Data
Rev. 3.0, 02/99, page 423 of 904

In transmitting serial data, the SCI operates as follows.
1. The SCI monitors the TDRE bit in SSR. When TDRE is cleared to 0 the SCI recognizes that
the transmit data register (TDR) contains new data, and loads this data from TDR into the
transmit shift register (TSR).
2. After loading the data from TDR into TSR, the SCI sets the TDRE bit to 1 and starts
transmitting. If the transmit-data-empty interrupt enable bit (TIE) is set to 1 in SCR, the SCI
requests a transmit-data-empty interrupt (TXI) at this time.
Serial transmit data is transmitted in the following order from the TXD pin:
a. Start bit: one 0 bit is output.
b. Transmit data: seven or eight bits are output, LSB first.
c. Parity bit or multiprocessor bit: one parity bit (even or odd parity) or one multiprocessor bit
is output. Formats in which neither a parity bit nor a multiprocessor bit is output can also
be selected.
d. Stop bit: one or two 1 bits (stop bits) are output.
e. Mark state: output of 1 bits continues until the start bit of the next transmit data.
3. The SCI checks the TDRE bit when it outputs the stop bit. If TDRE is 0, the SCI loads new
data from TDR into TSR, outputs the stop bit, then begins serial transmission of the next
frame. If TDRE is 1, the SCI sets the TEND bit to 1 in SSR, outputs the stop bit, then
continues output of 1 bits in the mark state. If the transmit-end interrupt enable bit (TEIE) in
SCR is set to 1, a transmit-end interrupt (TEI) is requested.
Figure 14-6 shows an example of SCI transmit operation in asynchronous mode.
Rev. 3.0, 02/99, page 424 of 904

Start Parity Stop Start Parity Stop
1 bit Data bit bit bit Data bit bit 1
Serial 0 D0 D1 D7 0/1 1 0 D0 D1 D7 0/1 1 Mark (idle)

data state
TDRE
TEND
TXI TXI interrupt TXI TEI

request handler writes request request
data in TDR and
clears TDRE to 0
1 frame
Figure 14-6 Example of SCI Transmit Operation

(8-Bit Data with Parity and One Stop Bit)
Rev. 3.0, 02/99, page 425 of 904

Receiving Serial Data (Asynchronous Mode): Figure 14-7 shows a sample flowchart for
receiving serial data and indicates the procedure to follow.
(1) Initialize (1) SCI initialization: the receive data

function of the RXD pin is selected
automatically.
Start receiving
(2) , (3) Receive error handling and break
detection: if a receive error occurs,
Read ORER, PER, read the ORER, PER, and FER bits in
(2)
and FER in SSR SSR to identify the error. After
executing the necessary error
handling, clear ORER, PER, and FER
PER or FER or Yes all to 0. Receiving cannot resume if
ORER = 1? ORER, PER, or FER remains set to 1.
When a framing error occurs, the RXD
pin can be read to detect the break
state.
(4) Read RDRF bit in SSR
(3)
Error handling
No
RDRF = 1?
(4) SCI status check and receive data
read: read the serial status register
Yes
(SSR), check that RDRF is set to 1,
Read receive data then read receive data from the
from RDR, and clear RDRF receive data register (RDR) and clear
bit to 0 in SSR RDRF to 0.
(5) To continue receiving serial data:

Finished No check RDRF, read RDR, and clear
(5) RDRF to 0 before the stop bit of the
receiving?
current frame is received. If the DTC is
Yes started by a receive-data-full interrupt
(RXI) to read RDR, the RDRF bit is
Clear RE to 0 in SCR cleared automatically so this step is
unnecessary.
End
Figure 14-7 Sample Flowchart for Receiving Serial Data

(Continued on Next Page)
Rev. 3.0, 02/99, page 426 of 904

(3) Start of error
handling
Overrun error
handling
Yes
ORER = 1?
Yes
Break?
No
Yes
FER = 1? No
Framing error
No handling
Yes
PER = 1?
No
Parity error
Clear ORER, PER, Clear RE to 0 in SCR
handling
and FER to 0 in SSR
End
RTS
Figure 14-7 Sample Flowchart for Receiving Serial Data (cont)
In receiving, the SCI operates as follows.
1. The SCI monitors the receive data line. When it detects a start bit 0, the SCI synchronizes
internally and starts receiving.
2. Receive data is shifted into RSR in order from LSB to MSB.
3. The parity bit and stop bit are received.
After receiving these bits, the SCI makes the following checks:
a. Parity check: the number of 1s in the receive data must match the even or odd parity setting
of the O/( bit in SMR.
b. Stop bit check: the stop bit value must be 1. If there are two stop bits, only the first stop bit
is checked.
c. Status check: RDRF must be 0 so that receive data can be loaded from RSR into RDR.
If these checks all pass, the SCI sets RDRF to 1 and stores the received data in RDR. If one of
the checks fails (receive error), the SCI operates as indicated in table 14-12.
Note: When a receive error flag is set, further receiving is disabled. When receiving resumes
after an error flag was set, the RDRF bit is not set to 1.
4. After setting RDRF to 1, if the receive-data-full interrupt enable bit (RIE) is set to 1 in SCR,
the SCI requests a receive-data-full interrupt (RXI). If one of the error flags (ORER, PER, or
FER) is set to 1 and the receive-data-full interrupt enable bit (RIE) in SCR is also set to 1, the
SCI requests a receive-error interrupt (ERI).
Rev. 3.0, 02/99, page 427 of 904
Figure 14-8 shows an example of SCI receive operation in asynchronous mode.
Table 14-12 Receive Error Conditions and SCI Operation
Receive Error Abbreviation Condition Data Transfer

Overrun error ORER Receiving of next data ends while Receive data not loaded
RDRF is still set to 1 in SSR from RSR into RDR
Framing error FER Stop bit is 0 Receive data loaded
from RSR into RDR
Parity error PER Parity of receive data differs from Receive data loaded
even/odd parity setting in SMR from RSR into RDR
Start Parity Stop Start Parity Stop

bit Data bit bit bit Data bit bit 1
1
Serial 0 D0 D1 D7 0/1 1 0 D0 D1 D7 0/1 0 Mark (idle)
data state
RDRF
FER
RXI RXI interrupt handler Framing error,

request reads data in RDR ERI request
and clears RDRF to 0
1 frame
Figure 14-8 Example of SCI Receive Operation

(8-Bit Data with Parity and One Stop Bit)
14.3.3 Clocked Synchronous Operation
In clocked synchronous mode, the SCI transmits and receives data in synchronization with clock
pulses. This mode is suitable for high-speed serial communication.
The SCI transmitter and receiver share the same clock but are otherwise independent, so full
duplex communication is possible. The transmitter and receiver are also double buffered, so
continuous transmitting or receiving is possible by reading or writing data while transmitting or
receiving is in progress.
Figure 14-9 shows the general format in clocked synchronous serial communication.
Rev. 3.0, 02/99, page 428 of 904
Transfer direction
One unit (character or frame) of serial data
* *
Serial clock
LSB MSB
Serial
Don't care Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Don't care
data
Note: * High except in continuous transmitting or receiving
Figure 14-9 Data Format in Clocked Synchronous Communication
In clocked synchronous serial communication, each data bit is placed on the communication line
from one falling edge of the serial clock to the next. Data is guaranteed valid at the rising edge of
the serial clock. In each character, the serial data bits are transmitted in order from LSB (first) to
MSB (last). After output of the MSB, the communication line remains in the state of the MSB. In
clocked synchronous mode the SCI receives data by synchronizing with the rising edge of the
serial clock.
(1) Communication Format: The data length is fixed at eight bits. No parity bit or
multiprocessor bit can be added.
(2) Clock: An internal clock generated by the on-chip baud rate generator or an external clock
input from the SCK pin can be selected according to the setting of the C/$ bit in the serial mode
register (SMR) and the CKE1 and CKE0 bits in the serial control register (SCR). See table 14-9.
When the SCI operates on an internal clock, it outputs the clock signal at the SCK pin. Eight
clock pulses are output per transmitted or received character. When the SCI is not transmitting or
receiving, the clock signal remains in the high state.
SCI Initialization (Clocked Synchronous Mode): Before transmitting or receiving, software

must clear the TE and RE bits to 0 in the serial control register (SCR), then initialize the SCI as
follows.
When changing the communication mode or format, always clear the TE and RE bits to 0 before
following the procedure given below. Clearing TE to 0 sets TDRE to 1 and initializes the transmit
shift register (TSR). Clearing RE to 0, however, does not initialize the RDRF, PER, FER, and
ORER flags and receive data register (RDR), which retain their previous contents.
Rev. 3.0, 02/99, page 429 of 904

Figure 14-10 is a sample flowchart for initializing the SCI.
Start of initialization
Clear TE and RE bits to 0 in SCR
Set CKE1 and CKE0 in SCR

(1) Select the clock source in the
(1) (leaving RIE, TIE, TEIE, MPIE, TE,
serial control register (SCR).
and RE cleared to 0)
Write 0 in RIE, TIE, TEIE, MPIE,
TE, and RE.
(2) Set value in BRR (2) Write the value corresponding to

the bit rate in the bit rate register
(BRR). (Not necessary when using
an external clock).
(3) Select communication format (3) Select the serial communication

in SMR format in the serial mode register
(SMR).
Wait
(4) Wait for at least the interval
required to transmit or receive one
No
1 bit interval elapsed? bit, then set TE or RE to 1 in the
serial control register (SCR). Also
set RIE, TIE, TEIE, and MPIE as
Yes necessary. Setting TE or RE
enables the SCI to use the TXD or
Set TE or RE to 1 in SCR RXD pin.
(4) Set RIE, TIE, TEIE, and MPIE
as necessary
Start transmitting
or receiving
Figure 14-10 Sample Flowchart for SCI Initialization
Rev. 3.0, 02/99, page 430 of 904

Transmitting Serial Data (Clocked Synchrous Mode): Figure 14-11 shows a sample flowchart
for transmitting serial data and indicates the procedure to follow.
(1) Initialize (1) SCI initialization: the transmit

data output function of the TXD
pin is selected automatically.
Start transmitting
(2) (2) SCI status check and transmit

Read TDRE bit in SSR
data write: read the serial
status register (SSR), check
that the TDRE bit is 1, then
No write transmit data in the
TDRE = 1? transmit data register (TDR)
and clear TDRE to 0.
Yes
Write transmit data in TDR and

clear TDRE bit to 0 in SSR
No (3) To continue transmitting serial

(3) All data transmitted?
data: read the TDRE bit to
Yes check whether it is safe to
write; if so, write data in TDR,
then clear TDRE to 0. When
Read TEND bit in SSR the DTC is started by a
transmit-data-empty interrupt
request (TXI) to write data in
TDR, the TDRE bit is checked
No
TEND = 1? and cleared automatically.
Yes
Clear TE bit to 0 in SCR
End
Figure 14-11 Sample Flowchart for Serial Transmitting
Rev. 3.0, 02/99, page 431 of 904

transmitting. If the transmit-data-empty interrupt enable bit (TIE) in SCR is set to 1, the SCI
If clock output is selected, the SCI outputs eight serial clock pulses. If an external clock
source is selected, the SCI outputs data in synchronization with the input clock. Data is output
from the TXD pin in order from LSB (bit 0) to MSB (bit 7).
3. The SCI checks the TDRE bit when it outputs the MSB (bit 7). If TDRE is 0, the SCI loads
data from TDR into TSR and begins serial transmission of the next frame. If TDRE is 1, the
SCI sets the TEND bit in SSR to 1, and after transmitting the MSB, holds the transmit data pin
(TXD) in the MSB state. If the transmit-end interrupt enable bit (TEIE) in SCR is set to 1, a
transmit-end interrupt (TEI) is requested at this time.
4. After the end of serial transmission, the SCK pin is held in the high state.
Figure 14-12 shows an example of SCI transmit operation.
Rev. 3.0, 02/99, page 432 of 904

Transmit direction
Serial
clock
Serial
Bit 0 Bit 1 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7
data
TDRE
TEND
TXI TXI interrupt TXI TEI request

request handler writes request
data in TDR and
clears TDRE to 0
1 frame
Rev. 3.0, 02/99, page 433 of 904

Receiving Serial Data (Clocked Synchronous Mode): Figure 14-13 shows a sample flowchart
for receiving serial data and indicates the procedure to follow. When switching from
asynchronous mode to clocked synchronous mode, make sure that ORER, PER, and FER are
cleared to 0. If ORER, PER, or FER is set to 1 the RDRF bit will not be set and both transmitting
and receiving will be disabled.
(1) Initialize (1) SCI initialization: the receive data function

of the RXD pin is selected automatically.
Start receiving
(2), (3) Receive error handling and break
detection: if a receive error occurs, read
(2) Read ORER in SSR the ORER bit in SSR then, after executing
the necessary error handling, clear
ORER to 0. Neither transmitting nor
Yes receiving can resume while ORER
ORER = 1?
remains set to 1.
(3)
No
Error handling
(4) Read RDRF bit in SSR
(4) SCI status check and receive data read:
read the serial status register (SSR),
No check that RDRF is set to 1, then read
RDRF = 1?
receive data from the receive data
Yes register (RDR) and clear RDRF to 0.
Read receive data

(5) To continue receiving serial data: check
from RDR, and clear
RDRF bit to 0 in SSR RDRF, read RDR, and clear RDRF to 0
before the MSB (bit 7) of the current frame
is received. If the DTC is started by
Finished No a receive-data-full interrupt request (RXI)
(5)
receiving? to read RDR, the RDRF bit is cleared
Yes automatically so this step is unnecessary.
Clear RE to 0 in SCR
End
(3) Start of error
handling
Yes
ORER = 1?
Overrun error
No handling
Clear ORER to 0
in SSR
RTS
Figure 14-13 Sample Flowchart for Serial Receiving

Rev. 3.0, 02/99, page 434 of 904
In receiving, the SCI operates as follows.
1. The SCI synchronizes with serial clock input or output and initializes internally.
2. Receive data is shifted into RSR in order from LSB to MSB.
After receiving the data, the SCI checks that RDRF is 0 so that receive data can be loaded from
RSR into RDR. If this check passes, the SCI sets RDRF to 1 and stores the received data in
RDR. If the check does not pass (receive error), the SCI operates as indicated in table 14-12.
Note: Both transmitting and receiving are disabled while a receive error flag is set. The
RDRF bit is not set to 1. Be sure to clear the error flag.
3. After setting RDRF to 1, if the receive-data-full interrupt enable bit (RIE) is set to 1 in SCR,
the SCI requests a receive-data-full interrupt (RXI). If the ORER bit is set to 1 and the
receive-data-full interrupt enable bit (RIE) in SCR is also set to 1, the SCI requests a receive-
error interrupt (ERI).
Figure 14-14 shows an example of SCI receive operation.
Transmit direction
Serial
clock
Serial
Bit 7 Bit 0 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7
data
RDRF
ORER
RXI RXI interrupt handler RXI Overrun error,

request reads data in RDR and request ERI request
clears RDRF to 0
1 frame
Rev. 3.0, 02/99, page 435 of 904

Transmitting and Receiving Serial Data Simultaneously (Clocked Synchronous Mode):
Figure 14-15 shows a sample flowchart for transmitting and receiving serial data simultaneously
and indicates the procedure to follow.
(1) Initialize * (1) SCI initialization: the transmit data output function of the TXD
pin and receive data input function of the RXD pin are
selected, enabling simultaneous transmitting and receiving.
Start transmitting
and receiving
(2) SCI status check and transmit data write: read the serial
status register (SSR), check that the TDRE bit is 1, then write
(2) Read TDRE bit in SSR transmit data in the transmit data register (TDR) and clear
TDRE to 0.
No (3) Receive error handling: if a receive error occurs, read the

TDRE = 1?
ORER bit in SSR then, after executing the necessary error
Yes handling, clear ORER to 0. Neither transmitting nor receiving
can resume while ORER remains set to 1.
Write transmit data
in TDR and clear TDRE
bit to 0 in SSR (4) SCI status check and receive data read: read the serial
status register (SSR), check that the RDRF bit is 1, then read
receive data from the receive data register (RDR) and clear
Read ORER bit in SSR RDRF to 0.
Yes
ORER = 1?
No (3)
(4) Read RDRF bit in SSR Error handling
No (5) To continue transmitting and receiving serial data: check

RDRF = 1? RDRF, read RDR, and clear RDRF to 0 before the MSB (bit
Yes 7) of the current frame is received. Also read the TDRE bit to
check whether it is safe to write; if so, write data in TDR, then
Read receive data clear TDRE to 0 before the MSB (bit 7) of the current frame is
from RDR and clear RDRF transmitted. When the DTC is started by a transmit-data-
bit to 0 in SSR empty interrupt request (TXI) to write data in TDR, the TDRE
bit is checked and cleared automatically. When the DTC is
started by a receive-data-full interrupt request (RXI) to read
Finished No RDR, the RDRF bit is cleared automatically.
(5) transmitting and
receiving?
Yes
Clear TE and RE bits

to 0 in SCR
Note: * In switching from transmitting or receiving to simultaneous

End transmitting and receiving, clear both TE and RE to 0,
then set both TE and RE to 1.
Figure 14-15 Sample Flowchart for Simultaneous Transmitting and Receiving
Rev. 3.0, 02/99, page 436 of 904

14.3.4 Multiprocessor Communication
The multiprocessor communication function enables several processors to share a single serial
communication line. The processors communicate in asynchronous mode using a format with an
additional multiprocessor bit (multiprocessor format).
In multiprocessor communication, each receiving processor is addressed by an ID. A serial

communication cycle consists of an ID-sending cycle that identifies the receiving processor, and a
data-sending cycle. The multiprocessor bit distinguishes ID-sending cycles from data-sending
cycles.
The transmitting processor should start by sending the ID of the receiving processor with which it
wants to communicate as data with the multiprocessor bit set to 1. Next the transmitting processor
should send transmit data with the multiprocessor bit cleared to 0.
When a receiving processor receives data with the multiprocessor bit set to 1, if multiprocessor
interrupts are enabled, an interrupt is requested. The interrupt-handling routine should compare
the data with the processor's own ID. If the ID matches, the processor should continue to receive
data. If the ID does not match, the processor should skip further incoming data until it again
receives data with the multiprocessor bit set to 1. Multiple processors can send and receive data in
this way.
Figure 14-16 shows an example of communication among different processors using a

multiprocessor format.
(1) Communication Formats: Four formats are available. Parity-bit settings are ignored when a
multiprocessor format is selected. For details see table 14-9.
(2) Clock: See the description of asynchronous mode.
Rev. 3.0, 02/99, page 437 of 904

Transmitting
processor
Serial communication line
Receiving Receiving Receiving Receiving

processor A processor B processor C processor D
(ID = 01) (ID = 02) (ID = 03) (ID = 04)
Serial H'01 H'AA

data
(MPB = 1) (MPB = 0)
ID-sending cycle: Data-sending cycle:

receiving processor address data sent to receiving
processor specified by ID
MPB: Multiprocessor bit
Figure 14-16 Example of Communication among Processors using Multiprocessor Format

(Sending Data H'AA to Receiving Processor A)
Rev. 3.0, 02/99, page 438 of 904

Transmitting Multiprocessor Serial Data: Figure 14-17 shows a sample flowchart for
transmitting multiprocessor serial data and indicates the procedure to follow.
(1) Initialize (1) SCI initialization: the transmit data

output function of the TXD pin is
Start transmitting selected automatically.
(2) Read TDRE bit in SSR (2) SCI status check and transmit data
write: read the serial status register
(SSR), check that the TDRE bit is 1,
No then write transmit data in the
TDRE=1? transmit data register (TDR). Also
Yes set MPBT (multiprocessor bit
transfer) to 0 or 1 in SSR. Finally,
Write transmit data in TDR
clear TDRE to 0.
and set MPBT in SSR
Clear TDRE bit to 0
No
(3) All data transmitted? (3) To continue transmitting serial data:
Yes read the TDRE bit to check whether
it is safe to write; if so, write data in
TDR, then clear TDRE to 0. When
Read TEND bit in SSR the DTC is started by a transmit-
data-empty interrupt request (TXI)
No to write data in TDR, the TDRE bit is
TEND=1? checked and cleared automatically.
Yes
No
(4) To output a break signal at the end
(4) Output break signal?
of serial transmission: set the DDR
Yes bit to 1 and the DR bit to 0 (DDR
and DR are I/O port registers), then
clear TE to 0 in SCR.
Set DR = 0, DDR = 1
Clear TE bit to 0 in SCR
End
Figure 14-17 Sample Flowchart for Transmitting Multiprocessor Serial Data
Rev. 3.0, 02/99, page 439 of 904

transmitting. If the transmit-data-empty interrupt enable bit (TIE) in SCR is set to 1, the SCI
Serial transmit data is transmitted in the following order from the TXD pin:
a. Start bit: one 0 bit is output.
b. Transmit data: seven or eight bits are output, LSB first.
c. Multiprocessor bit: one multiprocessor bit (MPBT value) is output.
d. Stop bit: one or two 1 bits (stop bits) are output.
e. Mark state: output of 1 bits continues until the start bit of the next transmit data.
3. The SCI checks the TDRE bit when it outputs the stop bit. If TDRE is 0, the SCI loads data
from TDR into TSR, outputs the stop bit, then begins serial transmission of the next frame. If
TDRE is 1, the SCI sets the TEND bit in SSR to 1, outputs the stop bit, then continues output
of 1 bits in the mark state. If the transmit-end interrupt enable bit (TEIE) in SCR is set to 1, a
transmit-end interrupt (TEI) is requested at this time.
Figure 14-18 shows an example of SCI transmit operation using a multiprocessor format.
1 Start Data Parity Stop Start Data Parity Stop 1

bit bit bit bit bit bit
Serial data 0 D0 D1 D7 0/1 1 0 D0 D1 D7 0/1 0 Mark (idle)
state
RDRF
FER
RXI request ERI generated by

framing error
RXI interrupt handler
reads RDR data and
clears RDRF to 0.
1 frame

(8-Bit Data with Multiprocessor Bit and One Stop Bit)
Rev. 3.0, 02/99, page 440 of 904

Receiving Multiprocessor Serial Data: Figure 14-19 shows a sample flowchart for receiving
multiprocessor serial data and indicates the procedure to follow.
(1) Initialize (1) SCI initialization: the receive data

function of the RXD pin is selected
automatically.
Start receiving
(2) ID receive cycle: Set the MPIE bit in the
(2) Set MPIE bit to 1 in SCR serial control register (SCR) to 1.
(3) SCI status check and ID check: read

Read ORER and FER bits in SSR the serial status register (SSR), check
that RDRF is set to 1, then read receive
Yes data from the receive data register
FER or ORER = 1? (RDR) and compare with the
No processorÕs own ID. If the ID does not
match the receive data, set MPIE to 1
(3) Read RDRF bit in SSR again and clear RDRF to 0. If the ID
matches the receive data, clear RDRF
No to 0.
RDRF = 1?
(4) SCI status check and data receiving:
Yes read SSR, check that RDRF is set to 1,
Read receive data from RDR then read data from the receive data
register (RDR).
No
Own ID? (5) Receive error handling and break
detection: if a receive error occurs, read
Yes
the ORER and FER bits in SSR to
Read ORER and FER bits in SSR identify the error. After executing the
necessary error handling, clear both
ORER and FER to 0. Receiving cannot
Yes
FER or ORER = 1? resume while ORER or FER remains
set to 1. When a framing error occurs,
No
the RXD pin can be read to detect the
(4) Read RDRF bit in SSR break state.
No
RDRF = 1?
Yes
Read receive data from RDR
(5)
Error handling
No
Finished receiving?
Yes
Clear RE to 0 in SCR
End
Figure 14-19 Sample Flowchart for Receiving Multiprocessor Serial Data

(Continued on Next Page)
Rev. 3.0, 02/99, page 441 of 904

Overrun error
Error handling
handling
Yes
ORER = 1?
No Yes
Yes Break?
FER = 1?
No No
Framing error Clear RE bit to
Clear ORER and FER handling? 0 in SCR
bits to 0 in SSR
End
RTS
Figure 14-19 Sample Flowchart for Receiving Multiprocessor Serial Data (cont)
Rev. 3.0, 02/99, page 442 of 904

Figure 14-20 shows an example of SCI receive operation using a multiprocessor format.
a. Own ID does not match data
Start Stop Start Stop

1 bit Data (ID1) MPB bit bit Data (Data1) MPB bit 1
Serial data 0 D0 D1 D7 1 1 0 D0 D1 D7 0 1 Idle (mark)

state
MPIE
RDRF
RDR value ID1
MPB detection RXI generation RXI handler Not own ID, No RXI request,
MPIE = 0 reads RDR so MPIE is RDR not updated
data and set to 1 again
clears RDRF
to 0
(Multiprocessor interrupt)
b. Own ID matches data
Start Stop Start Stop

1 bit Data (ID2) MPB bit bit Data (Data2) MPB bit 1
Serial data 0 D0 D1 D7 1 1 0 D0 D1 D7 0 1 Idle (mark)

state
MPIE
RDRF
RDR value ID1 ID2 Data2
MPB detection RXI generation RXI handler Own ID, so receiv- MPIE set to
MPIE = 0 reads RDR ing continues, with 1 again
data and data received at
clears RDRF each RXI
to 0
(Multiprocessor interrupt)

(Eight-Bit Data with Multiprocessor Bit and One Stop Bit)
Rev. 3.0, 02/99, page 443 of 904

14.4 Interrupts and DTC
The SCI has four interrupt sources in each channel: transmit-end (TEI), receive-error (ERI),
receive-data-full (RXI), and transmit-data-empty (TXI). Table 14-13 lists the interrupt sources
and indicates their priority.
Table 14-13 SCI Interrupt Sources
Interrupt Source Description DTC Availability Priority

ERI Receive error (ORER, PER, or FER) No High
RXI Receive data register full (RDRF) Yes
TXI Transmit data register empty (TDRE) Yes
TEI Transmit end (TEND) No Low
These interrupts can be enabled and disabled by the TIE, RIE bits in the serial control register
(SCR). Each interrupt request is sent separately to the interrupt controller. TXI is requested when
the TDRE bit in SSR is set to 1. TEI is requested when the TEND bit in SSR is set to 1. TXI can
start the data transfer controller (DTC) to transfer data. TDRE is automatically cleared to 0 when
the DTC executes the data transfer. TEI cannot start the DTC.
RXI is requested when the RDRF bit in SSR is set to 1. ERI is requested when the ORER, PER,
or FER bit in SSR is set to 1. RXI can start the DTC to transfer data. RDRF is automatically
cleared to 0 when the DTC executes the data transfer. ERI cannot start the DTC.
14.5 Usage Notes

Note the following points when using the SCI.
(1) TDR Write and TDRE: The TDRE bit in the serial status register (SSR) is a status flag
indicating loading of transmit data from TDR into TSR. The SCI sets TDRE to 1 when it transfers
data from TDR to TSR.
Data can be written into TDR regardless of the state of TDRE. If new data is written in TDR
when TDRE is 0, the old data stored in TDR will be lost because this data has not yet been
transferred to TSR. Before writing transmit data to TDR, be sure to check that TDRE is set to 1.
(2) Simultaneous Multiple Receive Errors: Table 14-14 indicates the state of SSR status flags
when multiple receive errors occur simultaneously. When an overrun error occurs the RSR
contents are not transferred to RDR, so receive data is lost.
Rev. 3.0, 02/99, page 444 of 904

Table 14-14 SSR Status Flags and Transfer of Receive Data
SSR Status Flags Receive Data

Transfer
RDRF ORER FER PER
RSR → RDR Receive Errors
1 1 0 0 × Overrun error
0 0 1 0 O Framing error
0 0 0 1 O Parity error
1 1 1 0 × Overrun error + framing error
1 1 0 1 × Overrun error + parity error
0 0 1 1 O Framing error + parity error
1 1 1 1 × Overrun error + framing error + parity error
O: Receive data is transferred from RSR to RDR.
×: Receive data is not transferred from RSR to RDR.
(3) Break Detection and Processing: Break signals can be detected by reading the RXD pin
directly when a framing error (FER) is detected. In the break state the input from the RXD pin
consists of all 0s, so FER is set and the parity error flag (PER) may also be set. In the break state
the SCI receiver continues to operate, so if the FER bit is cleared to 0 it will be set to 1 again.
(4) Sending a Break Signal: When TE is cleared to 0 the TXD pin becomes an I/O port, the level
and direction (input or output) of which are determined by the DR and DDR bits. This feature can
be used to send a break signal.
After the serial transmitter is initialized, the DR value substitutes for the mark state until TE is set
to 1 (the TXD pin function is not selected until TE is set to 1). The DDR and DR bits should
therefore both be set to 1 beforehand.
To send a break signal during serial transmission, clear the DR bit to 0, then clear TE to 0. When
TE is cleared to 0 the transmitter is initialized, regardless of its current state, so the TXD pin
becomes I/O port outputting the value 0.
(5) Receive Error Flags and Transmitter Operation (Clocked Synchronous Mode Only):
When a receive error flag (ORER, PER, or FER) is set to 1, the SCI will not start transmitting
even if TDRE is set to 1. Be sure to clear the receive error flags to 0 when starting to transmit.
Note that clearing RE to 0 does not clear the receive error flags.
(6) Receive Data Sampling Timing in Asynchronous Mode and Receive Margin: In
asynchronous mode the SCI operates on an base clock with 16 times the bit rate frequency. In
receiving, the SCI synchronizes internally with the falling edge of the start bit, which it samples
on the base clock. Receive data is latched on the rising edge of the eighth base clock pulse. See
figure 14-21.
Rev. 3.0, 02/99, page 445 of 904

16 clocks
8 clocks
0 7 15 0 7 15 0
Internal base
clock
Receive data Start bit

D0 D1
(RXD)
Synchronization
sampling timing
Data sampling
timing
Figure 14-21 Receive Data Sampling Timing in Asynchronous Mode
The receive margin in asynchronous mode can therefore be expressed as in equation (1).
1 1 |D – 0.5|
M = {(0.5 – ) - (L – 0.5 – ) F- (1 + F)} × 100% ..................................... (1)
2N 2N N
M: Receive margin (%)
N: Ratio of clock frequency to bit rate (N = 16)
D: Clock duty cycle (D = 0 to 1.0) L: Frame length (L = 9 to 12)
F: Absolute deviation of clock frequency
From equation (1), if F = 0 and D = 0.5 the receive margin is 46.875%, as given by equation (2).
D = 0.5, F = 0
M = (0.5 - 1/2 ×16) ×100%
= 46.875% ........................................................................................................ (2)
This is a theoretical value. A reasonable margin to allow in system designs is 20 to 30%.
(7) SCI Channel 3: Use of pins for this channel must be enabled by setting bits 6, 5, and 3 in the
port A control register (PACR).
Rev. 3.0, 02/99, page 446 of 904

14.6 Notes on SCK Pin to Port Switching Using Clock Synchronized SCI
When switching from SCK pin to port using clock synchronized SCI, the following items should
be borne in mind.
Problem in Operation: After setting DDR and DR to 1 and using synchronous SCI clock output,
when the SCK pin is switched to the port function at the end of transmission, a low-level signal is
output for one half-cycle before the port output state is established.
When switching to the port function by making the following settings while DDR = 1, DR = 1,
C/$ = 1, CKE1 = 0, CKE0 = 0, and TE = 1, low-level output occurs for one half-cycle.
(1) End of serial data transmission

(2) TE bit = 0
(3) C/$ bit = 0 ... switchover to port output
(4) Occurrence of low-level output (see figure 1)
Half-cycle low-level output occurs
SCK/port
(1) End of transmission (4) Low-level output
Data Bit 6 Bit 7
(2) TE=0
TE
(3) C/A=0
C/A
CKE1
CKE0
Figure 14-22 Operation when Switching from SCK Pin Function to Port Pin Function
Rev. 3.0, 02/99, page 447 of 904

Usage Note: The procedure shown below should be used to prevent low-level output when
switching from the SCK pin function to the port function.
As this procedure temporarily places the SCK pin in the input state, the SCK/port pin should be
pulled up beforehand with an external circuit.
With DDR = 1, DR = 1, C/$ = 1, CKE1 = 0, CKE0 = 0, and TE = 1, make the following settings
in the order shown.
(1) End of serial data transmission

(2) TE bit = 0
(3) CKE bit = 1
(4) C/$ bit = 0 ... switchover to port output
(2) bit = 0
High-level output
SCK/port
(1) End of transmission
Data Bit 6 Bit 7
(2) TE=0
TE
(4) C/A=0
C/A
(3) CKE1=1
(5) CKE1=0
CKE1
CKE0
Figure 14-23 Operation when Switching from SCK Pin Function to Port Pin Function
(Preventing Low-Level Output)
Rev. 3.0, 02/99, page 448 of 904

Section 15 A/D Converter
15.1 Overview
The H8/539F includes a 10-bit successive-approximations A/D converter. Software can select a
maximum of 12 analog input channels.
15.1.1 Features
A/D converter features are listed below.
• Ten-bit resolution
Number of input channels: 12
• High-speed conversion
Conversion time: minimum 8.3 µs per channel (φ = 16-MHz system clock)
• Two conversion modes
Single mode: A/D conversion of one channel
Scan mode: continuous conversion on one to 12 channels
• Twelve 10-bit A/D data registers
A/D conversion results are transferred for storage into 12 A/D data registers. Each channel has
its own A/D data register.
• Built-in sample-and-hold function
A sample-and-hold circuit is built into the A/D converter, permitting a simplified external
analog input circuit.
• A/D conversion interrupt with DTC (data transfer controller) support
At the end of A/D conversion, an A/D end interrupt request (ADI) can be sent to the H8/500
CPU. The ADI interrupt can also be served by the DTC.
• External triggering
A/D conversion can be started by an external trigger signal.
• Selectable analog conversion voltage range
The analog voltage conversion range can be set by input at the VREF pin.
• A/D conversion can also be started by the IPU.
Rev. 3.0, 02/99, page 449 of 904

Figure 15-1 shows a block diagram of the A/D converter.
VREF
Successive-approximations
AVCC
ADDRB
ADDRA
ADDR0
ADDR1
ADDR2
ADDR3
ADDR4
ADDR5
ADDR6
ADDR7
ADDR8
ADDR9
register
10-bit
D/A
AVSS
Module data bus
Bus interface
AN0
− A/D conversion
ADCSR
ADCR
control circuit
AN1 On-chip
AN2 data bus
Analog multiplexer
AN3
AN4 Sample-and-hold
AN5 circuit
AN6
AN7
AN8
AN9 ADI interrupt request signal
AN10 ADTRG external trigger signal
AN11 (or IPU compare match signal)
φ/8
φ/16
Legend
ADDR0: A/D data register 0 ADDR7: A/D data register 7
ADDR3: A/D data register 3 ADDRA: A/D data register A
ADDR4: A/D data register 4 ADDRB: A/D data register B
ADDR5: A/D data register 5 ADCR: A/D control register
ADDR6: A/D data register 6 ADCSR: A/D control/status register
Figure 15-1 A/D Converter Block Diagram
Rev. 3.0, 02/99, page 450 of 904

Table 15-1 summarizes the A/D converter’s input pins. The 12 analog input pins (AN0 to AN11)
are divided into three groups: AN0 to AN3 (group 0), AN4 to AN7 (group 1), and AN8 to AN11
(group 2). The $'75* pin can trigger the start of A/D conversion externally. The A/D converter
starts A/D conversion when a low pulse is applied to this pin. AVCC and AVSS are the power
supply for the analog circuits in the A/D converter. VREF is a conversion reference voltage.
To protect the reliability of the chip, AVCC , AVSS , VCC , and VSS should be related as follows: AVCC
= VCC ± 10%; AVSS = VSS. AVCC and AVSS must not be left open, even if the A/D converter is not
used (including hardware/software standby mode). Voltages applied to the analog input pins
should be in the range AVSS ≤ ANn ≤ VREF .
Table 15-1 A/D Converter Pins
Pin Name Abbreviation Input/Output Function

Analog power supply AVCC Input Analog power supply
Analog ground AVSS Input Analog ground and reference voltage
Reference voltage VREF Input Analog reference voltage
Analog input 0 AN0 Input Analog input pins 0 to 3 (analog group 0)
Analog input 1 AN1 Input
A/D trigger $'75* Input External trigger pin for A/D conversion
Rev. 3.0, 02/99, page 451 of 904

Table 15-2 summarizes the A/D converter’s registers.
Table 15-2 A/D Converter Registers

H'FEA0 A/D data register 0 (high/low) ADDR0(H/L) R H'0000
H'FEAA A/D data register 5 (high/low) ADDR5(H/L) R H'0000
H'FEAC A/D data register 6 (high/low) ADDR6(H/L) R H'0000
H'FEAE A/D data register 7 (high/low) ADDR7(H/L) R H'0000
H'FEB0 A/D data register 8 (high/low) ADDR8(H/L) R H'0000
H'FEB2 A/D data register 9 (high/low) ADDR9(H/L) R H'0000
H'FEB4 A/D data register A (high/low) ADDRA(H/L) R H'0000
H'FEB6 A/D data register B (high/low) ADDRB(H/L) R H'0000
H'FEB8 A/D control/status register ADCSR R/W* H'00
H'FEB9 A/D control register ADCR R/W H'1F
H’FEDC A/D trigger register ADTRGR R/W H’FF
Note: * Software can write 0 in bit 7 of the A/D control/status register (ADCSR) to clear the flag, but
cannot write 1.
Rev. 3.0, 02/99, page 452 of 904

15.2.1 A/D Data Registers 0 to B
A/D data registers 0 to B (ADDR0 to ADDRB) are 16-bit read-only registers that store the results
of A/D conversion of the analog inputs. There are 12 registers, corresponding to analog inputs 0
to 11 (AN0 to AN11). The A/D data registers are initialized to H'0000 by a reset and in the standby
modes.
Bit 7 6 5 4 3 2 1 0
ADDRnH
AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2
(upper byte)
R/W R R R R R R R R
Bit 7 6 5 4 3 2 1 0
ADDRnL
AD1 AD0 − − − − − −
(lower byte)
R/W R R R R R R R R
(n = 0 to B)
The on-chip A/D converter converts the analog inputs to 10-bit digital values. The upper eight of
the 10 bits are stored in the upper byte of the A/D data register of the selected channel. The lower
two bits are stored in the lower byte of the A/D data register. Only the two upper bits of the lower
byte of an A/D data register are valid. Table 15-3 indicates the pairings of analog input channels
and A/D data registers.
The H8/500 CPU can always read and write the A/D data registers. The upper byte must always
be read before the lower byte. It is possible to read only the upper byte of an A/D data register,
but it is not possible to read only the lower byte. For further details see section 15.3, "H8/500
CPU Interface." Bits 5 to 0 of the A/D data registers are reserved bits that cannot be modified and
always read 0.
Rev. 3.0, 02/99, page 453 of 904

Table 15-3 Analog Input Channels and A/D Data Registers
Analog Input A/D Data Analog Input A/D Data Analog Input A/D Data
Channel Register Channel Register Channel Register
AN0 ADDR0 AN4 ADDR4 AN8 ADDR8
AN1 ADDR1 AN5 ADDR5 AN9 ADDR9
AN2 ADDR2 AN6 ADDR6 AN10 ADDRA
AN3 ADDR3 AN7 ADDR7 AN11 ADDRB
15.2.2 A/D Control Status Register
The A/D control status register (ADCSR) is an eight-bit readable/writable register that selects the
A/D conversion mode. ADCSR is initialized to H'00 by a reset and in the standby modes.
Bit 7 6 5 4 3 2 1 0
ADF ADIE ADM1 ADM0 CH3 CH2 CH1 CH0
R/W R/(W)* R/W R/W R/W R/W R/W R/W R/W
Channel select 3−0

These bits select analog input
channels
A/D mode 1/0
These bits select the A/D conversion mode
(single and scan modes)
A/D interrupt enable

Enables and disables A/D end interrupts
A/D end flag

Indicates end of A/D conversion
Note: * Software can write 0 to clear the flag, but cannot write 1.
Rev. 3.0, 02/99, page 454 of 904

Bit 7—A/D End Flag (ADF): Indicates the end of A/D conversion. ADF is initialized to 0 by a
reset and in the standby modes.
Bit 7
ADF Description
0 A/D conversion is in progress or the A/D converter is idle (Initial value)
ADF is cleared to 0 when:
1. Software reads ADF after it has been set to 1, then writes 0 in ADF
2. The DTC is started by ADI
1 A/D conversion has ended and a digital value has been loaded into one or more
A/D data registers
ADF is set to 1 when:
1. A/D conversion ends in single mode
2. All conversion in one selected analog group ends
After ADF is set to 1, the A/D converter operates differently in single mode and scan mode. In
single mode, after loading a digital value into an A/D data register, the A/D converter sets ADF to
1 then goes into the idle state. In scan mode, after completing all conversion in one selected
analog group, the A/D converter sets ADF to 1 then continues converting.
Software cannot write 1 in ADF.
Bit 6—A/D Interrupt Enable (ADIE): Enables or disables the A/D end interrupt (ADI). ADIE
is initialized to 0 by a reset and in the standby modes.
Bit 6
ADIE Description
0 A/D end interrupt (ADI) is disabled (Initial value)
1 A/D end interrupt (ADI) is enabled
When A/D conversion ends and the ADF bit in ADCSR is set to 1, if ADIE is also set to 1 an A/D
end interrupt (ADI) is requested. The ADI interrupt request can be cleared by clearing ADF to 0
or clearing ADIE to 0.
Rev. 3.0, 02/99, page 455 of 904

Bits 5 and 4—A/D Mode 1/0 (ADM1/0): These bits select single mode, four-channel scan mode,
eight-channel scan mode, or 12-channel scan mode as the A/D conversion mode. ADM1 and
ADM0 are cleared to 00 by a reset and in the standby modes, selecting single mode. To ensure
correct operation, always clear ADST to 0 before changing the conversion mode.
Bit 5 Bit 4
ADM1 ADM0 Description
0 0 Single mode (Initial value)
0 1 Four-channel scan mode (analog group 0, 1, or 2)
1 0 Eight-channel scan mode (analog groups 0 and 1)
1 1 Twelve-channel scan mode (analog groups 0, 1, and 2)
When ADM1 and ADM0 are cleared to 00, single mode is selected. In single mode one analog
channel is converted once. The channel is selected by bits CH3 to CH0 in ADCSR.
Setting ADM1 and ADM0 to 01 selects four-channel scan mode. In scan mode, one or more
channels are converted continuously. The channels converted in scan mode are selected by bits
CH3 to CH0 in ADCSR. In four-channel scan mode, A/D conversion is performed in the four
channels in analog group 0 (AN0 to AN3), analog group 1 (AN4 to AN7), or analog group 2 (AN8 to
AN11).
Setting ADM1 and ADM0 to 10 selects eight-channel scan mode. A/D conversion is peformed in
the eight channels in analog group 0 (AN0 to AN3) and analog group 1 (AN4 to AN7).
Setting ADM1 and ADM0 to 11 selects 12-channel scan mode. A/D conversion is performed in
the 12 channels in analog group 0 (AN0 to AN3), analog group 1 (AN4 to AN7), and analog group 2
(AN8 to AN11).
For further details on operation in single and scan modes, see section 15.4, "Operation."
Rev. 3.0, 02/99, page 456 of 904

Bits 3 to 0—Channel Select 3 to 0 (CH3 to CH0): These bits and ADM1 and ADM0 select the
analog input channels. CH3 to CH0 are initialized to 0000 by a reset and in the standby modes.
To ensure correct operation, always clear ADST to 0 in the A/D control register (ADCR) before
changing the analog input channel selection.
Bit 3 Bit 2 Bit 1 Bit 0 Analog Input Channels

CH3 CH2 CH1 CH0 Single Mode Four-Channel Scan Mode
0 0 0 0 AN0 (Initial value) AN0
0 1 AN1 AN0, AN1
1 0 AN2 AN0 to AN2
1 1 AN3 AN0 to AN3
1 0 0 AN4 AN4
0 1 AN5 AN4, AN5
1 0 AN6 AN4 to AN6
1 1 AN7 AN4 to AN7
1
1 0* 0 0 AN8 AN8
0 1 AN9 AN8, AN9
1 0 AN10 AN8 to AN10
1 1 AN11 AN8 to AN11
Rev. 3.0, 02/99, page 457 of 904

Bit 3 Bit 2 Bit 1 Bit 0 Analog Input Channels
CH3 CH2 CH1 CH0 Eight-Channel Scan Mode 12-Channel Scan Mode
0 0 0 0 AN0,AN4 AN0, AN4, AN8
0 1 AN0,AN1, AN4, AN5 AN0, AN1, AN4, AN5, AN8,
AN9
1 0 AN0 to AN2, AN4 to AN6 AN0 to AN2, AN4 to AN6,
AN8 to AN10
1 1 AN0 to AN7 AN0 to AN11
1 0 0 AN0, AN4 AN0, AN4, AN8
0 1 AN0, AN1, AN4, AN5 AN0, AN1, AN4, AN5, AN8,
AN9
1 0 AN0 to AN2, AN4 to AN6 AN0 to AN2, AN4 to AN6,
AN8 to AN10
1 1 AN0 to AN7 AN0 to AN11
1 2
1 0* 0 0 Reserved* AN0, AN4, AN8
0 1 AN0, AN1, AN4, AN5, AN8,
AN9
1 0 AN0 to AN2, AN4 to A6, AN8
to AN10
1 1 AN0 to AN11
Notes: 1. Must be cleared to 0.
2. Reserved for future expansion. Must not be used.
Rev. 3.0, 02/99, page 458 of 904

15.2.3 A/D Control Register
The A/D control register (ADCR) is an eight-bit readable/writable register that controls the start of
A/D conversion and selects the A/D clock. ADCR is initialized to H'1F by a reset and in the
standby modes. Bits 4 to 0 of ADCR are reserved for future expansion. They cannot be modified
and always read 1.
Bit 7 6 5 4 3 2 1 0
TRGE CKS ADST − − − − −
R/W R/W R/W R/W − − − − −
Reserved bits
A/D start
Starts and stops A/D conversion
Clock select
Selects the A/D conversion time
Trigger enable
Enables and disables external triggering of A/D conversion
Bit 7—Trigger Enable (TRGE): Enables or disables external triggering of A/D conversion.
When TRGE is set to 1, P71 automatically becomes the $'75* input pin. TRGE is initialized to
0 by a reset and in the standby modes.
Bit 7
TRGE Description
0 A/D conversion cannot be externally triggered (Initial value)
1 A/D conversion can be externally triggered (P71 is the $'75* pin)
After TRGE is set to 1, if a low pulse is input at the $'75* pin, the A/D converter detects the
falling edge of the pulse and sets the ADST bit in ADCR to 1. Subsequent operation is the same
as if software had set the ADST bit to 1. External triggering operates only when the ADST bit is
cleared to 0.
When the external trigger function is used, the low pulse input at the $'75* pin must have a
width of at least 1.5 system clocks (1.5φ). For further details see section 15.4.4, "External
Triggering of A/D Conversion."
Rev. 3.0, 02/99, page 459 of 904

Bit 6—Clock Select (CKS): Selects the A/D conversion time. A/D conversion is performed in
266 states when CKS is cleared to 0, or in 134 states when CKS is set to 1. CKS is initialized to 0
by a reset and in the standby modes. To ensure correct operation, always clear ADST to 0 before
changing the A/D conversion time.
Bit 6
CKS Description
0 Conversion time = 266 states (maximum) (Initial value)
1 Conversion time = 134 states (maximum)
Bit 5—A/D Start (ADST): Starts and stops A/D conversion. A/D conversion starts when ADST
is set to 1 and stops when ADST is cleared to 0. ADST is initialized to 0 by a reset and in the
standby modes.
Bit 5
ADST Description
0 A/D conversion is stopped (Initial value) (Initial value)
1 A/D conversion is in progress
Clearing conditions:
1. Single mode: cleared to 0 automatically at the end of A/D conversion
2. Scan mode: check that ADF is set to 1 in ADCSR, then write 0 in ADST
The ADST bit operates differently in single and scan modes. In single mode, ADST is cleared to
0 automatically after A/D conversion of one channel. In scan mode, after all selected analog
inputs have been converted A/D conversion of all these channels begins again, so ADST remains
set to 1. When the conversion time or analog input channel selection is changed in scan mode, the
ADST bit should first be cleared to 0 to halt A/D conversion.
Before changing the A/D conversion time (CKS bit in ADCR), operating mode (ADM1/0 bits in
ADCSR), or analog input channel selection (bits CH3 to CH0 in ADCSR), always check that the
A/D converter is stopped (ADST = 0). Making these changes while the A/D converter is
operating (ADST = 1) may produce incorrect values in the A/D data registers.
Bits 4 to 0—Reserved: These bits are reserved for future expansion. They cannot be modified
and always read 1.
15.2.4 A/D Trigger Register
The A/D trigger register (ADTRGR) is used to switch the A/D external trigger. The A/D external
trigger can be selected from the ADTRG pin or an IPU channel 1 DR3 compare match. ADTRGR
is set to H'FF in standby mode and by a reset.
Rev. 3.0, 02/99, page 460 of 904

Bit 7 6 5 4 3 2 1 0
EXTRG − − − − − − −
R/W R/W − − − − − − −
Reserved bits
External trigger source select

Selects an IPU channel compare match or the ADTRG pin
as the A/D external trigger
Bit 7—External Trigger Source Select (EXTRG): This bit selects the A/D external trigger from
an IPU channel 1 compare match or the ADTRG pin. The A/D external trigger source is the
ADTRG pin when EXTRG is set to 1, and an IPU channel 1 DR3 compare match when EXTRG is
cleared to 0. EXTRG is initialized to 1 by a reset and in standby mode.
Bit 7
EXTRG Description
0 A TPU channel 1 DR3 compare match is set as the A/D external trigger source
1 The ADTRG pin is set as the A/D external trigger source (Initial value)
Bit 6—Bits 6 to 0: Reserved: These bits are reserved for future expansion. They are always read
as 1 and cannot be modified.
For a description of a sample operation, see section 15.4.5 "Starting the A/D Converter with the
IPU."
Rev. 3.0, 02/99, page 461 of 904

15.3 H8/500 CPU Interface
A/D data registers 0 to B (ADDR0 to ADDRB) are 16-bit registers, but they are connected to the
H8/500 CPU via an eight-bit on-chip data bus. The upper and lower bytes of an A/D data register
are necessarily read separately. To prevent data from changing between the reading of the upper
and lower bytes of an A/D data register, the lower byte is read using a temporary register (TEMP).
The upper byte can be read directly.
An A/D data register is read as follows. The upper byte must be read first. The H8/500 CPU
receives the upper-byte data directly at this time. At the same time, the A/D converter transfers
the lower-byte data internally into TEMP. Next, when the lower byte is read, the H8/500 CPU
receives the contents of TEMP.
When reading an A/D data register using byte operand size, always read the upper byte before the
lower byte. It is possible to read only the upper byte, but if only the lower byte is read incorrect
data may be obtained. When an A/D data register is read using word operand size, the upper byte
will automatically be read before the lower byte.
Figure 15-2 shows the data flow when an A/D data register is read. In the example shown, the
upper byte of the A/D data register contains H'AA and the lower byte contains H'40. First the
H8/500 CPU reads H'AA directly from the upper byte while H'40 is transferred to TEMP in the
A/D converter. Next, when the H8/500 CPU reads the lower byte of the A/D data register, it
obtains the TEMP contents.
Rev. 3.0, 02/99, page 462 of 904

(1) ADDRnH (upper byte) read: ADDRnH [H'AA] → H8/500 CPU [H'AA] A
ADDRnL [H'40] → TEMP [H'40] B
A Module data bus
Bus interface
H8/500 CPU
(H'AA)
On-chip bus
A TEMP (H'40)
ADDRnH (H'AA) ADDRnL (H'40)
(2) ADDRnL (lower byte) read: ADDRnH [H'??] → Don't care

ADDRnL [H'??] → Don't care
TEMP [H'40] → H8/500 CPU [H'40] C
C Module data bus

Bus interface
H8/500 CPU
(H'40)
On-chip bus
C
TEMP (H'40)
ADDRnH (H'??) ADDRnL (H'??)
Figure 15-2 A/D Data Register Read Operation (Reading H'AA40)
Rev. 3.0, 02/99, page 463 of 904

15.4 Operation
The A/D converter operates by successive approximations with 10-bit resolution. It has two
operating modes: single mode and scan mode. In single mode, one selected channel is converted
once. In scan mode, one or more selected channels are converted repeatedly until the ADST bit in
the A/D control register (ADCR) is cleared to 0.
15.4.1 Single Mode
Single mode can be selected to perform one A/D conversion on one channel. Single mode is
selected by clearing bits ADM1 and ADM0 to 00 in the A/D control/status register (ADCSR).
A/D conversion then starts when the ADST bit is set to 1 in ADCR. The ADST bit remains set to
1 during A/D conversion and is automatically cleared to 0 when conversion ends. When
conversion ends the ADF bit is set to 1 in ADCSR. If the ADIE bit is also set to 1, an ADI
interrupt is requested. To clear ADF to 0, first read ADF after ADF has been set to 1, then write 0
in ADF. If the ADI interrupt is served by the data transfer controller (DTC), however, ADF is
cleared to 0 automatically.
Figure 15-3 shows a flowchart for selecting analog input channel 1 (AN1) and performing A/D
conversion in single mode. Figure 15-4 is a timing diagram.
Rev. 3.0, 02/99, page 464 of 904

Single mode
(1) With ADST cleared to 0, set
TRGE and CKS (the settings
shown disable external
(1) H'20 → ADCR
triggering and select 134-
(TRGE = 0, ADST = 0, CKS = 1)
state conversion time).
(2) Set ADIE, ADM1, ADM0 and
CH3 to CH0 in ADCSR (the
(2) H'01 → ADCSR
settings shown enable ADI
(ADIE = 0, ADM1, 0 = 00, CH3-0 = 0001)
interrupts, select single
mode, and select AN1).
(3) Set ADST to 1 to start A/D
conversion.
(3) 1 → ADST
(4) Wait for ADF (A/D end flag)
to be set to 1 in ADCSR.
When ADF is set, an ADI
interrupt is requested and the
(4) ADF = 1? A/D result processing routine
No
starts (5).
Yes
(5) [A/D result processing
Read A/D data register routine]
(5)
(while ADF = 1 and ADST = 0) Read the A/D data register.
(ADST has been cleared to 0
automatically.)
(6) Read the 1 value of ADF,
(6) Read ADCSR and clear ADF to 0 then write 0 to clear ADF to 0.
(7) To convert the same channel
again, go to step (3). To
Yes change the mode or channel,
(7) Convert again? go to step (1).
No
End
Figure 15-3 Flowchart for Single Mode
Rev. 3.0, 02/99, page 465 of 904

ADI interrupt request
Set ADST ADST cleared to 0 Set ADST to 1*
ADST bit
to 1*
(ADCR bit 5)
Clear ADF Clear ADF
A/D conversion starts to 0* to 0*
ADF bit
(ADCSR bit 7)
Channel 0 (AN0) Waiting

Waiting A/D (1) Waiting A/D (2) Waiting
Channel 1 (AN1) conversion conversion




Read conversion result*
ADDR0 H'0000
ADDR1 H'0000 (1) Conversion (2)

A/D conversion result result
ADDR2 H'0000
ADDR3 H'0000
ADDR4 H'0000
ADDR5 H'0000
ADDR6 H'0000
ADDR7 H'0000
ADDR8 H'0000
ADDR9 H'0000
ADDRA H'0000
ADDRB H'0000
Note: * Vertical arrows (↓) indicate instructions executed by software. Boxes

indicate operations performed by the A/D converter.
Figure 15-4 Example of A/D Converter Operation (Single Mode, Channel 1 Selected)
Rev. 3.0, 02/99, page 466 of 904

15.4.2 Scan Mode
Scan mode can be selected to perform A/D conversion on one or more channels repeatedly (to
monitor the channels continuously, for example). Scan mode is selected by setting bits ADM1
and ADM0 in the A/D control/status register (ADCSR) to 01, 10, or 11. The 01 setting selects
four-channel scan mode. The 10 setting selects eight-channel scan mode. The 11 setting selects
12-channel scan mode. A/D conversion starts when the ADST bit in ADCR is set to 1.
In scan mode the channels are converted in ascending order of channel number (AN0, AN1, …,
AN11). The ADST bit remains set to 1 until software clears it to 0.
When all conversion in one selected analog group is completed, the ADF bit in ADCSR is set to 1,
then A/D conversion is performed again. If the ADIE bit in ADCSR is set to 1, then when ADF is
set to 1 an ADI interrupt is requested. To clear ADF to 0, first read ADF after it has been set to 1,
then write 0 in ADF. If the ADI interrupt is served by the data transfer controller (DTC),
however, ADF is cleared to 0 automatically.
Figure 15-5 shows a flowchart for selecting analog input channels 0 and 1 (AN0 and AN1) and
performing A/D conversion in four-channel scan mode. Figure 15-6 is a timing diagram.
Rev. 3.0, 02/99, page 467 of 904

Scan mode
(1) With ADST cleared to 0, set
TRGE and CKS (the settings
shown disable external
(1) H'20 → ADCR
triggering and select 134-
(TRGE = 0, ADST = 0, CKS = 1)
state conversion time).
(2) Set ADIE, ADM1, ADM0 and
CH3 to CH0 in ADCSR (the
(2) H'11 → ADCSR
settings shown enable ADI
(ADIE = 0, ADM1, 0 = 01, CH3-0 = 0001)
interrupts, select four-channel
scan mode, and select AN0
and AN1).
(3) Set ADST to 1 to start A/D
(3) 1 → ADST conversion.
(4) Wait for ADF (A/D end flag)
to be set to 1 in ADCSR.
When ADF is set, an ADI
(4) ADF = 1? interrupt is requested and the
No
A/D result processing routine
Yes starts (5).
Read A/D data registers (5) [A/D result processing
(5)
(while ADF = 1 and ADST = 1) routine]
Read the A/D data registers.
(ADST remains set to 1.)
(6) (6) Read the 1 value of ADF,

Read ADCSR and clear ADF to 0 then write 0 to clear ADF to 0.
(7) To continue monitoring, go
to step (4). To change the
Yes mode or channels, go to step
(7) Continue monitoring? (1)
(8) Write 0 in ADST to stop A/D
No
conversion.
(8) 0 → ADST
End
Figure 15-5 Flowchart for Scan Mode
Rev. 3.0, 02/99, page 468 of 904

Set ADST
ADST bit to 1*
(ADCR bit 5) Clear ADF Clear ADF
A/D conversion starts to 0* to 0*
ADF bit
(ADCSR bit 7)
Continuous A/D conversion
A/D A/D A/D
Channel 0 (AN0) Waiting conversion Waiting conversion Waiting conversion
A/D A/D
Channel 1 (AN1) Waiting conversion Waiting conversion Waiting


ADDR0 A/D conversion A/D conversion

H'0000 result result
ADDR1 H'0000 A/D conversion result A/D conversion

result
ADDR2 H'0000 Read conversion result*

ADDR3 H'0000
ADDR4 H'0000
ADDR5 H'0000
ADDR6 H'0000
ADDR7 H'0000
ADDR8 H'0000
ADDR9 H'0000
ADDRA H'0000
ADDRB H'0000
Note: * Vertical arrows (↓) indicate instructions executed by software. Boxes

indicate operations performed by the A/D converter.
Figure 15-6 Example of A/D Converter Operation

(Four-Channel Scan Mode, Channels 0 and 1 Selected)
Rev. 3.0, 02/99, page 469 of 904
15.4.3 Analog Input Sampling and A/D Conversion Time
The A/D converter has a built-in sample-and-hold circuit. The A/D converter starts sampling the
analog inputs at a time tD (synchronization delay) after the ADST bit is set to 1 in the A/D control
register (ADCR). Figure 15-7 shows the sampling timing.
The A/D conversion time (tCONV) includes tD and the analog input sampling time (tSPL). The length
of tD varies because it includes time needed to synchronize the A/D converter. The total
conversion time therefore varies within the ranges indicated in table 15-4.
In scan mode, the tCONV values given in table 15-4 apply to the first conversion. In the second and
subsequent conversions there is no tD, and tCONV is fixed at 256 states when CKS = 0 or 128 states
when CKS = 1.
Table 15-4 A/D Conversion Time (Single Mode)
CKS = 0 CKS = 1
Item Symbol Min Typ Max Min Typ Max Unit
Synchronization delay tD 10 — 17 6 — 9 States
Input sampling time tSPL — 80 — — 40 —
A/D conversion time tCONV 259 — 266 131 — 134
Rev. 3.0, 02/99, page 470 of 904

A/D conversion time (tCONV)
Analog input
Synchronization sampling time
delay (tD) (tSPL)
A/D synchroni-
Write cycle zation time
(3 states) (max 14 states)
Address bus ADCR
Internal write
signal
ADST write
Analog input timing
sampling signal
A/D converter Idle Sample & hold A/D conversion
End of A/D
conversion
ADF (ADCR)
Figure 15-7 A/D Conversion Timing
Rev. 3.0, 02/99, page 471 of 904

15.4.4 External Triggering of A/D Conversion
A/D conversion can be started by input of an external trigger signal. External triggering is enabled
by setting the TRGE bit to 1 in the A/D control register. When the TRGE bit is set to 1, P71
automatically becomes the $'75* input pin. If a low pulse is input at the $'75* pin in this
state, the A/D converter detects the falling edge of the pulse and sets the ADST bit to 1. Figure
15-8 shows the external trigger input timing.
The ADST bit is set to 1 one state after the A/D converter samples the falling edge of the $'75*
signal. The time from when the ADST bit is set to 1 until A/D conversion begins is the same as
when software writes 1 in ADST.
1 state
Setup time ADTRG pin

ADTRG input ≥ tIRQ1S sampling timing
(worst case)
Setup time < tIRQ1S
ADTRG input
(best case)
ADST bit
(ADCR) ADST = 1
Figure 15-8 External Trigger Input Timing
15.4.5 Starting A/D Conversion by IPU
In the H8/539F, A/D conversion can be started by a compare match in the on-chip integrated-timer
pulse unit (IPU). To start A/D conversion by IPU compare match, follow the procedure given
next.
1. Set bits DOE21 and DOE20 (bits 7 and 6) to 1, 0 in IPU channel 1 timer output enable register
A (TOERA).
2. Set the starting time of the A/D converter in IPU channel 1 dedicated register 2 (DR2).
3. Set the TRGE bit (bit 7) in the A/D control register (ADCR) to 1.
4. Clear bit 7 of the ADTRGR register at address H'FEDC to 0.
After these settings, A/D conversion will start when the IPU channel 1 timer counter value
matches DR2. In this case A/D conversion cannot be started by input at the $'75* pin. When
Rev. 3.0, 02/99, page 472 of 904
the IPU starts A/D conversion, the timing is the same as if the T1OC2 pin were externally
connected to the $'75* pin. See the relevant timing diagrams for these pins.
15.5 Interrupts and DTC

The A/D converter can request an A/D end interrupt (ADI) at the end of conversion. ADI is
enabled when the ADIE bit is set to 1 in the A/D control/status register (ADCSR), and disabled
when ADIE is cleared to 0.
If the ADI bit in the interrupt controller’s data transfer enable register A (DTEA) is set to 1, the
ADI interrupt is served by the data transfer controller (DTC). When the DTC is started by ADI to
perform a data transfer, the ADF bit in ADCSR is automatically cleared to 0. For further details
on the DTC, see section 7, "Data Transfer Controller."
15.6 Usage Notes

When using the A/D converter, note the following points:
(1) Analog Input Voltage Range: During A/D conversion, the voltages input to the analog input
pins should be in the range AVSS ≤ ANn ≤ VREF .
(2) Relationships of AVCC and AVSS to VCC and VSS : AVCC , AVSS , VCC , and VSS should be related
as follows: AVCC = VCC ± 10%; AVSS = VSS. AVCC and AVSS must not be left open, even if the A/D
converter is not used (include hardware/software stand-by mode).
(3) VREF Input Range: The reference voltage input at the VREF pin should be in the range
VREF ≤ AVCC .
Failure to observe points (1), (2), and (3) above may degrade chip reliability.
(4) Note on Board Design: In board layout, separate the digital circuits from the analog circuits as
much as possible. Particularly avoid layouts in which the signal lines of digital circuits cross or
closely approach the signal lines of analog circuits. Induction and other effects may cause the
analog circuits to operate incorrectly, or may adversely affect the accuracy of A/D conversion.
The analog input signals (AIN), analog reference voltage (VREF), and analog supply voltage (AVCC)
must be separated from digital circuits by the analog ground (AVSS). The analog ground (AVSS)
should be connected to a stable digital ground (VSS) at one point on the board.
(5) Note on Noise: To prevent damage from surges and other abnormal voltages at the analog
input pins (AIN) and analog reference voltage pin (VREF), connect a protection circuit like the one in
figure 15-9 between AV CC and AVSS. The bypass capacitors connected to AVCC and VREF and the
filter capacitors connected to AIN must be connected to AVSS. If filter capacitors like those in
figure 15-9 are connected, the voltage values input to the analog input pins (AIN) will be smoothed,
Rev. 3.0, 02/99, page 473 of 904

which may give rise to error. Also, when A/D conversion is frequently performed with the A/D
converter in scan mode, etc., if the current charged or discharged by the analog input capacitance
of the H8/539F exceeds the current input via the input impedance Rin), an error will arise in the
filter capacitor voltage. The circuit constants should therefore be selected carefully.
AVCC
VREF
*2
Rin 100 Ω H8/539F
AIN (AN0-AN11)
*1 *1
0.1µF
AVSS
Notes: 1.
10 µF 0.01 µF
2. Rin: input impedance
Figure 15-9 Example of Analog Input Protection Circuit
10.0 kΩ
AN0−11 To A/D converter
20 pF
Note: Numeric values are approximate, except in table 15-5.
Figure 15-10 Analog Input Pin Equivalent Circuit
Rev. 3.0, 02/99, page 474 of 904

Table 15-5 Analog Input Pin Ratings
Conditions: VCC = 5.0 ± 10%, AVCC = 5.0 ± 10%, VREF = 5.0 ± 10%, (VREF ≤ AVCC),
VSS = AVSS = 0V
Item Min Max Unit

Analog input capacitance — 20 pF
Allowable signal-source 8.38 µs ≤ conversion time < 13.4 µs — 5 kΩ
impedance
Conditions other than above — 10
(6) A/D Conversion Accuracy Definitions: A/D conversion accuracy in the H8/539F is defined
as follows:
• Resolution: digital output code length of A/D converter

• Offset error: deviation from ideal A/D conversion characteristic of analog input voltage
required to raise digital output from minimum voltage value 0000000000 to 0000000001,
excluding quantization error (figure 15-12)
• Full-scale error: deviation from ideal A/D conversion characteristic of analog input voltage
required to raise digital output from 1111111110 to 1111111111, excluding quantization error
(figure 15-12)
• Quantization error: intrinsic error of the A/D converter; 0.5 LSB (figure 15-11)
• Nonlinearity error: deviation from ideal A/D conversion characteristic in range from zero volts
to full scale, excluding of offset error, full-scale error, and quantization error.
• Absolute accuracy: deviation of digital value from analog input value, including offset error,
full-scale error, quantization error, and nonlinearity error.
Rev. 3.0, 02/99, page 475 of 904

Digital output
Ideal A/D conversion

characteristic
111
110
101
100
011
010 Quantization error
001
000
0 1/7 2/7 3/7 4/7 5/7 6/7 7/FS
Analog input voltage
Figure 15-11 A/D Converter Accuracy Definitions (1)
Rev. 3.0, 02/99, page 476 of 904

Digital output Full-scale error
Ideal A/D conversion

characteristic
Nonlinearity
error
Actual A/D conversion

characteristic
FS
Analog input voltage
Offset error
Figure 15-12 A/D Converter Accuracy Definitions (2)
Rev. 3.0, 02/99, page 477 of 904

Section 16 Bus Controller
16.1 Overview
The on-chip bus controller (BSC) can dynamically alter the bus width and the length of the bus
cycle. When a 16-bit bus mode is selected by the inputs at the mode pins, the bus controller can
reserve part of the address space as a byte access area accessed via an eight-bit bus, switch another
part from a three-state bus cycle to a high-speed two-state bus cycle, and switch the eight-bit-bus
area to 16-bit access.
16.1.1 Features
Bus controller features are listed below.
• An eight-bit access area can be defined in the 16-bit bus modes (modes 1, 3, 4, 5*, and 6*)
The eight-bit access area consists of addresses greater than the value set in the byte area top
register (ARBT). (This area does not include the address set in ARBT, which is the boundary
of the word area.) When an address greater than the ARBT value is accessed, only the upper
data bus (D15 to D8) is valid. The access is performed with eight-bit bus width. The ARBT
setting does not change the bus width of the on-chip ROM, on-chip RAM, and on-chip register
areas.
Note: * Modes 5 and 6 have a 16-bit bus, but when the chip comes out of reset the ARBT and
AR3T settings are ignored: the entire external address space is accessed in three states via
an eight-bit bus. Software can enable the ARBT and AR3T settings by altering a value in
the bus control register (BCR).
• Two-state access area can be defined

The three-state-access area consists of addresses equal to or greater than the value set in the
three-state area top register (AR3T). (The address set in AR3T is included as the boundary of
the three-state area.) When addresses less than the AR3T value are accessed, the bus cycle
consists of two states. Wait states (TW) cannot be inserted in two-state access. The AR3T
setting does not change the bus cycle length of the on-chip ROM, on-chip RAM, and on-chip
register areas.
• Areas can be defined in steps of 256 bytes in minimum mode, or 4 kbytes in maximum mode.
Figure 16-1 shows a block diagram of the bus controller.
Rev. 3.0, 02/99, page 479 of 904

On-chip address bus (A19 to A16)
On-chip data bus (D15 to D8)
Mode 5 or 6
BCR
Multiplexer ARBT AR3T

Multiplexer
Lower 4 bits Lower 4 bits
Upper 4 bits Upper 4 bits
Comparator Comparator Comparator Comparator

BCRE
ARBT = Addr AR3T = Addr
ARBT < Addr ARBT < Addr AR3T < Addr AR3T ≤ Addr
Mode
3, 4, or 5
Mode 2
On-chip
register area*
ROM/RAM
area
Eight-bit access request Three-state access request

Legend
ARBT: Byte area top register
AR3T: Three-state area top register
BCR: Bus control register
BCRE: Bus controller enable
Note: * Except 16-bit accessible IPU registers.
Figure 16-1 Bus Controller Block Diagram
Rev. 3.0, 02/99, page 480 of 904

Table 16-1 summarizes the bus controller's registers. The bus controller has three 8-bit registers: a
byte area top register (ARBT) that designates the boundary of the word area; a three-state area top
register (AR3T) that designates the boundary of the three-state-access address space; and a bus
control register (BCR) used to switch the bus width in modes 5 and 6. The H8/500 CPU can
always read and write ARBT, AR3T, and BCR.
Table 16-1 Bus Controller Registers
Address Register Name Abbreviation R/W Initial Value

H'FF16 Byte area top register ARBT R/W H'FF
1
H'FF17 Three-state area top register AR3T R/W H'EE (H'0E)*
2
H'FEDF Bus control register BCR R/W H'BF (H'3F)*
Notes: 1. H'0E is the initial value in modes 3, 4, and 5. In modes 1, 2, 6, and 7 the initial value is
H'EE.
2. H'3F is the initial value in modes 5 and 6. In modes 1 to 4 and 7 the initial value is
H'BF.
16.2.1 Byte Area Top Register
The byte area top register (ARBT) specifies the boundary address that separates the area accessed
with 16-bit bus width from the area accessed using only the upper eight bits of the 16-bit bus. The
address set in ARBT is the word area boundary: the last address accessed with 16-bit bus width.
Bit 7 6 5 4 3 2 1 0
The bus controller controls the H8/500 CPU so that external addresses exceeding the ARBT value
are accessed with eight-bit bus width.
In expanded maximum mode, the ARBT value is treated as bits A19 to A12 (the upper eight bits) of
the word area boundary address. The word area boundary can be set in minimum 4-kbyte steps. In
expanded maximum mode, addresses H'00000 to H'00FFF are always a word access area.
Rev. 3.0, 02/99, page 481 of 904

In expanded minimum mode, the ARBT value is treated as bits A15 to A8 (the upper eight bits) of
the word area boundary address. The word area boundary can be set in minimum 256-byte steps.
In expanded minimum mode, addresses H'0000 to H'00FF are always a word access area.
The ARBT setting applies only to external addresses. It cannot change the bus width of the on-
chip ROM or RAM or on-chip register areas. In mode 2 the ARBT setting is ignored: the external
address bus has a fixed eight-bit width. In modes 5 and 6 the ARBT setting is ignored until the
BCRE bit is set to 1 in the bus control register (BCR).
ARBT is initialized to H'FF by a reset and in hardware standby mode. ARBT is not initialized in
16.2.2 Three-State Area Top Register
The three-state area top register (AR3T) specifies the boundary address that separates the area
accessed in two states from the area accessed in three states. The address set in AR3T is the
three-state area boundary: the first address accessed in three states.
Bit 7 6 5 4 3 2 1 0
Initial value 1 (0)* 1 (0)* 1 (0)* 0 1 1 1 0

Note: * Modes 3 to 5
The bus controller controls the H8/500 CPU so that external addresses equal to or greater than the
ARBT value are accessed in three states. Wait states cannot be inserted into the two-state-access
area.
In expanded maximum mode, the AR3T value is treated as bits A19 to A12 (the upper eight bits) of
the three-state area boundary address. The three-state area boundary can be set in minimum 4-
kbyte steps. In expanded maximum mode, addresses H'FF000 to H'FFFFF are always a three-
state-access area.
In expanded minimum mode, the AR3T value is treated as bits A15 to A8 (the upper eight bits) of
the three-state area boundary address. The three-state area boundary can be set in minimum 256-
byte steps. In expanded minimum mode, addresses H'FF00 to H'FFFF are always a three-state-
access area.
The AR3T setting applies only to external addresses. It cannot change the bus cycle length of the
on-chip ROM or RAM or on-chip register areas. In mode 2 the AR3T setting is ignored: the
Rev. 3.0, 02/99, page 482 of 904
external address space is always a three-state-access area. In modes 5 and 6 the AR3T setting is
ignored until the BCRE bit is set to 1 in the bus control register (BCR).
AR3T is initialized to H'EE (modes 1, 2, 6, and 7) or H'0E (modes 3 to 5) by a reset and in

hardware standby mode. ARBT is not initialized in software standby mode.
16.2.3 Bus Control Register
The bus control register (BCR) enables or disables the bus controller's bus control functions in
modes 5 and 6, and enables or disables on-chip I/O port functions.
Rev. 3.0, 02/99, page 483 of 904

Bit 7 6 5 4 3 2 1 0
BCRE 0P3T − P9AE EXIOP PCRE PBCE P12E
Initial value 0 (1)* 0 1 1 1 1 1 1

R/W R/W (R)* R/W − R/W R/W R/W R/W R/W
Ports 1 and 2
enable
Enables and
disables
reading and
writing of
ports 1 and 2
Ports B and C enable

Enables and disables
reading and writing
of ports B and C
Reserved bit
Pull-up transistor control register
enable
Enables and disables reading and
writing of port B and C pull-up
transistor control registers
Expanded I/O ports

Allocates H'0FE9C to H'0FE9F as external
addresses
Ports 9 and A enable

Enables and disables reading and writing of ports 9 and A
Zero page three-state

Forces three-state access to all addresses in page 0
Bus controller enable

Enables and disables bus control functions of the bus controller
Note: * In modes 1, 2, 3, 4, and 7.
When the bus controller enable bit (BCRE) is set to 1, the bus controller controls the bus
according to the values in ARBT and AR3T. As an exception, when the zero page three-state bit
(0P3T; bit 6) is set to 1, all external addresses in page 0 are placed in the three-state-access area
regardless of the AR3T setting.
Rev. 3.0, 02/99, page 484 of 904

Bits 4, 2, 1, and 0 enable or disable reading and writing of on-chip I/O ports. If one of these bits is
cleared to 0, the corresponding on-chip I/O ports cannot be accessed. The port addresses become
part of the external eight-bit three-state-access area instead.
Bit 3 is for I/O port expansion. When this bit is cleared to 0, H'0FE9C to H'0FE9F become part of
the external eight-bit three-state-access area.
For precautions on modifying the BCR value, see section 16.4, "Usage Notes."
(1) Bit 7—Bus Controller Enable (BCRE): Enables or disables bus control functions using the
values in ARBT and AR3T in modes 5 and 6.
Bit 7
BCRE Description
0 The H8/500 CPU accesses all external addresses in three states using an eight-bit
bus* (Initial value in modes 5 and 6)
This bit cannot be cleared to 0 in modes 1 to 4 and 7.
1 The H8/500 CPU accesses external addresses according to the ARBT and AR3T
settings (Initial value in modes 1 to 4 and 7; cannot be cleared to 0)
Note: * Access is performed using only the upper eight bits (D15 to D8) of the 16-bit bus.
(2) Bit 6—Zero Page Three-State (0P3T): Selects three-state access for all external addresses in
page 0, regardless of the AR3T setting.
Bit 6
0P3T Description
0 The H8/500 CPU accesses external addresses according to (Initial value)
the ARBT and AR3T settings
1 The H8/500 CPU accesses external addresses according to the ARBT and AR3T
settings except in page 0, where three-state access is selected regardless of the
AR3T setting*
Note: * In mode 7 there is no external address space, so the 0P3T value has no meaning.
(3) Bit 5—Reserved: Read-only bit, always read as 1. Reserved for future expansion.
Rev. 3.0, 02/99, page 485 of 904

(4) Bit 4—Port 9 and A Enable (P9AE): Enables or disables reading and writing of ports 9 and
A, allowing these I/O ports to be reconfigured off-chip.
Bit 4
P9AE Description
0 On-chip I/O ports 9 and A cannot be written or read
The DR and DDR addresses of ports 9 and A (H'0FE90 to H'0FE93) become part
of the external eight-bit three-state-access area.*
1 On-chip I/O ports 9 and A can be written and read (Initial value)
Note: * Cannot be cleared to 0 in mode 7.
For details see section 16.3.3, "I/O Port Expansion Function."
(5) Bit 3—Expanded I/O Ports (EXIOP): Enables or disables expansion of I/O ports, allowing
I/O ports to be configured off-chip.
Bit 3
EXIOP Description
0 External I/O ports can be written and read
H'0FE9C to H'0FE9F become part of the external eight-bit three-state-access
area.*
1 External I/O ports cannot be written or read (Initial value)
(6) Bit 2—Pull-Up Transistor Control Register Enable (PCRE): Enables or disables reading
and writing of port B and C pull-up transistor control registers (PBPCR and PCPCR).
Bit 2
PCRE Description
0 Port B and C pull-up transistor control registers (PBPCR and PCPCR) cannot be
written or read
PBPCR and PCPCR addresses (H'0FE98 to H'0FE9B) become part of the external
eight-bit three-state-access area.*
1 Port B and C pull-up transistor control registers (PBPCR and (Initial value)
PCPCR) can be written and read
Rev. 3.0, 02/99, page 486 of 904

(7) Bit 1—Port B and C Enable (PBCE): Enables or disables reading and writing of ports B and
C, allowing these I/O ports to be reconfigured off-chip.
Bit 1
PBCE Description
0 On-chip I/O ports B and C cannot be written or read
The DR and DDR addresses of ports B and C (H'0FE94 to H'0FE97) become part
1 On-chip I/O ports B and C can be written and read (Initial value)
(8) Bit 0—Port 1 and 2 Enable (P12E): Enables or disables reading and writing of ports 1 and 2,
allowing these I/O ports to be reconfigured off-chip.
Bit 0
P12E Description
0 On-chip I/O ports 1 and 2 cannot be written or read
The DR and DDR addresses of ports 1 and 2 (H'0FE80 to H'0FE83) become part
1 On-chip I/O ports 1 and 2 can be written and read (Initial value)
Rev. 3.0, 02/99, page 487 of 904

16.3 Operation
16.3.1 Operation after Reset in Each Mode
Figures 16-2 to 16-8 illustrate operation in each mode after a reset.
(1) Mode 1: The external data bus space. H'0000 to H'EDFF are a 16-bit two-state-access area.
H'EE00 to H'FE7F are a 16-bit three-state-access area. When the on-chip RAM is enabled,
however, the on-chip RAM area is a 16-bit two-state-access area.
External Bus Width 16 bits
H'0000
External bus area
16 bits, 2 states
H'EDFF
H'EE00 16 bits, 3 states
H'EE7F
H'EE80 On-chip RAM area
16 bits, 2 states
H'F67F (16 bits, 3 states)
H'F680 On-chip RAM area
16 bits, 2 states
H'FE7F (16 bits, 3 states)
H'FE80 On-chip register area
H'FFFF 8 bits, 3 states
Figure 16-2 Bus Width and Bus Cycle Length after Reset (Mode 1)
(2) Mode 2: The external data bus space is eight bits wide. H'0000 to H'3FFF (on-chip ROM) are
a 16-bit two-state-access area. H'4000 to H'FE7F are an eight-bit three-state-access area. When
the on-chip RAM is enabled, however, the on-chip RAM area is a 16-bit two-state-access area.
Rev. 3.0, 02/99, page 488 of 904

H'0000 On-chip ROM area

16 bits, 2 states
H'3FFF
H'4000
External bus area
8 bits, 3 states
H'EE7F
16 bits, 2 states
16 bits, 2 states
H'FE80 On-chip register area
H'FFFF 8 bits, 3 states
(3) Mode 3: The external data bus space. H'00000 to H'0DFFF are a 16-bit two-state-access area.
H'0E000 to H'0FE7F and H'10000 to H'FFFFF are a 16-bit three-state-access area. When the on-
chip RAM is enabled, however, the on-chip RAM area is a 16-bit two-state-access area.

H'00000
External bus area
16 bits, 2 states
H'0DFFF
H'0E000 External bus area
H'0EE7F 16 bits, 3 states
H'0EE80 On-chip RAM area
16 bits, 2 states
H'0F67F (16 bits, 3 states)
H'0F680 On-chip RAM area
16 bits, 2 states
H'0FE7F (16 bits, 3 states)
H'0FE80 On-chip register area
H'0FFFF 8 bits, 3 states
H'10000
External bus area
16 bits, 3 states
H'FFFFF
Rev. 3.0, 02/99, page 489 of 904

(4) Mode 4: The external data bus space is 16 bits wide. H'00000 to H'03FFF and H'10000 to
H'2FFFF (on-chip ROM) are 16-bit two-state-access areas. H'04000 to H'0DFFF is a 16-bit two-
state access area. H'0E000 to H'0FE7F and H'30000 to H'FFFFF are a 16-bit three-state-access
area. When the on-chip RAM is enabled, however, the on-chip RAM area is a 16-bit two-state-
access area.

H'03FFF 16 bits, 2 states
H'04000 External bus area
H'0DFFF 16 bits, 2 states
H'0E000 External bus area
H'0EE7F 16 bits, 3 states
16 bits, 2 states
16 bits, 2 states
H'0FE7F (16 bits, 3 states)
On-chip register area
H'30000 External bus area
H'FFFFF 16 bits, 3 states
(5) Mode 5: The external data bus space uses a 16-bit bus width. After a reset, H'00000 to
H'FFFFF are an eight-bit three-state-access area because BCRE = 0 in the bus control register
(BCR). In this case, the upper half of the data bus (D15 to D8) is enabled (see Table 16-2 (2)).
When the on-chip RAM is enabled, however, the on-chip RAM area is a 16-bit two-state-access
area.
Rev. 3.0, 02/99, page 490 of 904

H'00000
External bus area
8 bits, 3 states
H'0EE7F
16 bits, 2 states
16 bits, 2 states
(8 bits, 3 states)
H'0FE7F
H'10000
External bus area
8 bits, 3 states
H'FFFFF
(6) Mode 6: The external data bus space. H'0000 to H'FE80 are an eight-bit three-state-access
area (BCRE = 0 in BCR). In this case, the upper half of the data bus (D15 to D8) is enabled (see
Table 16-2 (2)). When the on-chip RAM is enabled, however, the on-chip RAM area is a 16-bit
two-state-access area.
H'0000
External bus area

8 bits, 3 states
H'EE7F
16 bits, 2 states
16 bits, 2 states
H'FE80
On-chip register area
8 bits, 3 states
H'FFFF
Rev. 3.0, 02/99, page 491 of 904

(7) Mode 7: There is no external bus. H'00000 to H'03FFF and H'10000 to H'2FFFF (on-chip
ROM) are a 16-bit two-state-access area. When the on-chip RAM is enabled, the on-chip RAM
area is also a 16-bit two-state-access area.
H'00000
On-chip ROM area
16 bits, 2 states
H'03FFF

H'0F67F 16 bits, 2 states
H'0FE7F 16 bits, 2 states
H'10000
On-chip ROM area
16 bits, 2 states
H'2FFFF
Rev. 3.0, 02/99, page 492 of 904

16.3.2 Timing of Changes in Bus Areas and Bus Size
Changes in the bus areas and bus size take effect in the next bus cycle after the write cycle to
ARBT or AR3T.
T1 T2 T3
A19-A 0 ARBT, AR3T, or BCR address
Internal write
signal
Internal data Setting data

bus
Bus area Old setting New setting
Figure 16-9 Timing of Changes in Bus Controller Settings (Byte Write)
Rev. 3.0, 02/99, page 493 of 904

T1 T2 T3 T1 T2 T3
A19-A 0 ARBT address AR3T address
Internal write
signal
Internal data
ARBT setting data AR3T setting data
bus
Bus area Old setting Temporary setting New setting
Only ARBT is modified
Figure 16-10 Timing of Changes in Bus Controller Settings (Word Write)
Rev. 3.0, 02/99, page 494 of 904

16.3.3 I/O Port Expansion Function
Bus control register bits 4 to 0 can be set for I/O port expansion. This function enables ports 1, 2,
A, B, and C, which cannot be used in the bus expansion modes (modes 1 to 6 ), to be reconfigured
off-chip. Figure 16-11 shows an example of I/O port reconfiguration.
Address
decoder
A19-0
DDR
DR +5 V
74LS74 × 1/2
(DDR)
74LS02
PR
RD CK CLR RES
D Q
HWR
OE 74LS373 × 1/8
(DR)
D Q Port
G
D15-8 Data bus
74LS04
× 1/6 GND
OC S
Y A
74LS257
× 1/6
Figure 16-11 Example of I/O Port Reconfiguration (1 Bit)
Rev. 3.0, 02/99, page 495 of 904

16.4 Usage Notes
When using the bus controller, note the following points:
(1) Restrictions on AR3T and ARBT Settings: AR3T and ARBT settings should satisfy
equation (1).
AR3T ≤ ARBT + 1 ......................................................................................................... (1)
No eight-bit, two-state-access area is defined for the H8/539F. If AR3T > ARBT + 1, eight-bit
three-state access is performed.
(2) Possible Partitionings of the Address Space: The address space can be partitioned in eight
ways as follows:
1. Two areas: 16 bits, two states; 16 bits, three states

2. Two areas: 16 bits, two states; eight bits, three states
3. Two areas: 16 bits, three states; eight bits, three states
4. Three areas: 16 bits, two states; 16 bits, three states; eight bits, three states
1
5. One area: eight bits, three states *
2
6. Three areas: 16 bits, three states (page 0)* ; 16 bits, two states; 16 bits, three states
2
7. Three areas: 16 bits, three states (page 0)* ; 16 bits, two states; 8 bits, three states
2
8. Four areas: 16 bits, three states (page 0)* ; 16 bits, two states; 16 bits, three states; eight bits,
three states
Notes: 1. Possible only in modes 5 and 6 when BCRE = 0 in the bus control register (BCR).
2. Set by the 0P3T bit in BCR.
(3) Modification of ARBT, AR3T, and BCR: When ARBT, AR3T, and BCR settings are
modified, an invalid bus area may be created temporarily. This may prevent normal program
execution. Crashes can be avoided by one of the following methods:
1. Place routines that modify ARBT, AR3T, and BCR in on-chip ROM or RAM.
Perform the modification in an area that is not affected by the ARBT, AR3T, and BCR
settings. The modification can be followed by a jump to any area without crashing.
(Example 1)
2. Place a branch instruction after the instruction that modifies ARBT, AR3T, or BCR.
After the write to ARBT, AR3T, or BCR,* the instruction fetch from the temporary invalid bus
area is cleared by execution of the branch instruction, thus preventing a crash.
(Example 2)
Note: * To modify both ARBT and AR3T simultaneously, a word access instruction is
recommended.
Rev. 3.0, 02/99, page 496 of 904
On-chip ROM
or RAM
L1:MOV R2,@ARBT ARBT modification

RTS instruction (subroutine)
.
.
.
.
. MOV R2,@ARBT
. BRA L1 Crash-avoiding
branch instruction
MOV #EE,R2 L1:
ARBT modification
BSR L1
subroutine call Jump destination
is next instruction
Example 1: Placing the modifying subroutine Example 2: Placing a branch instruction after
in on-chip ROM or RAM the modifying instruction
Figure 16-12 Example of Program Structure for Modifying ARBT, AR3T, and BCR
Rev. 3.0, 02/99, page 497 of 904

(4) Access Types and Operation of Data Bus and Control Signals: Table 16-2 indicates how
the data bus and control signals operate in various types of access.
Table 16-2 (1) Data Bus and Control Signal Operation in Various Types of Access
(Mode 2)
Instruction Designations Data Bus Control Signals

External
Bus Operand Operand Access
No. Width Address Size Direction A0 D15 to D8 D7 to D0 5' +:5 /:5
1 8 bits Byte area Byte Write 0 Output Not used H L H
(port)
2 Write 1 Output H L H
3 Read 0 Input L H H
5 Word Write 0 Output H L H
1 Output H L H
1 Input L H H
Notes: 1. How to read the table:
1) External Bus width: external bus width determined by the operating mode.
2) Operand address: area containing the operand address specified in the instruction.
Examples: ARBT > operand address: byte area
ARBT < operand address: word area
3) Operand size: size of operand specified in the instruction.
Examples: MOV.B: byte size
MOV.W: word size
4) Access direction: as below.
Examples: MOV.B Rn, <EA>: write (CPU → <EA>)
MOV.B <EA>, Rn: read (<EA> → CPU)
2. When a byte area is addressed by an instruction with word operand size, the CPU
accesses memory twice, accessing the even byte first, then the odd byte. Instructions
that specify word-size operands should always specify an even operand address.
Rev. 3.0, 02/99, page 498 of 904

(Modes 1, 3, 4, 5, 6)

External
1 16 bits* Byte area* Byte Write 0 Output High H L H
(Modes 5 impedance
2 and 6, after 1 Output High H L H
reset)
impedance
3 Read 0 Input Don't care L H H
4 1 Input Don't care L H H
5 Word Write 0 Output High H L H
impedance
1 Output High H L H
impedance
1 Input Don't care L H H
1) External bus width: external bus width determined by the operating mode.
MOV.W: word size
2. When a byte area is addressed by an instruction with word operand size, the CPU
accesses memory twice, accessing the even byte first, then the odd byte. Instructions
that specify word-size operands should always specify an even operand address.
* Modes 5 and 6 have a 16-bit bus width, but an 8-bit bus width is set after a reset.
Rev. 3.0, 02/99, page 499 of 904

(Modes 1, 3, 4, 5, 6)

External
1 16 bits Word area Byte Write 0 Output Dummy H L H
data
2 1 Dummy Output H H L
data
4 1 Don't care Input L H H
5 Word Write 0 Output Output H L L
1     
6 Read 0 Input Input L H H
1     
1) External bus width: external bus width determined by the operating mode.
MOV.W: word size
2. Instructions that specify word-size operands should always specify an even operand
address.
Rev. 3.0, 02/99, page 500 of 904

Figures 16-13 and 16-14 show examples of usage of the bus controller in mode 4.
AR3T ≤ ARBT + 1
16 bits
Bus cycle Bus width
H'00000
On-chip ROM area 2 states 16 bits
H'03FFF
H'04000
External bus area 2 states 16 bits
H'0EE7F
H'0EE80
On-chip RAM area 2 states 16 bits
H'0FE7F
H'0FE80
On-chip register area 3 states 8 bits
H'0FFFF
H'10000
H'2FFFF
H'30000 2 states 16 bits
AR3T
External bus area
3 states 16 bits
ARBT
H'FFFFF
Mode 4
Figure 16-13 Example of Use of Bus Controller (Mode 4)
Rev. 3.0, 02/99, page 501 of 904

AR3T > ARBT + 1
16 bits
Bus cycle Bus width
H'00000

H'03FFF
H'04000
External bus area 2 states 16 bits
H'0F67F
H'0F680
On-chip RAM area 2 states 16 bits
H'0FE7F
H'0FE80
On-chip register area 3 states 8 bits
H'0FFFF
H'10000
H'2FFFF
H'30000
16 bits
ARBT
2 states
8 bits,
External bus area
3 states
8 bits
AR3T
3 states
H'FFFFF
Mode 4
Figure 16-14 Example of Use of Bus Controller (Mode 4)
Rev. 3.0, 02/99, page 502 of 904

Section 17 RAM (H8/539F)
17.1 Overview
The H8/539F has 4 kbytes of on-chip static RAM. The RAM is connected to the H8/500 CPU by a
16-bit data bus. The H8/500 CPU accesses both byte data and word data in two states, making the
RAM suitable for rapid data transfer and high-speed computation.
The on-chip RAM is assigned to addresses H'EE80 to H'FE7F. The RAM control register
(RAMCR) enables this area to be switched between on-chip RAM and external memory.
Figure 17-1 shows a block diagram of the on-chip RAM.
Rev. 3.0, 02/99, page 503 of 904

8
On-chip data bus (upper 8 bits)
On-chip data bus (lower 8 bits)
RAME1, 2
Bus interface and control section
2
H'EE80 H'EE81 RAMCR

H'EE82 H'EE83
H'EE84 H'EE85
On-chip RAM (4 kbytes)
H'FE7C H'FE7D
H'FE7E H'FE7F

(even address) (odd address)
Legend
RAMCR: RAM control register
Figure 17-1 RAM Block Diagram
The RAM is controlled by the RAM control register (RAMCR). Table 17-1 gives the address and
initial value of RAMCR.
Table 17-1 RAM Control Register

H'FF15 RAM control register RAMCR R/W Undetermined
Rev. 3.0, 02/99, page 504 of 904

17.2 RAM Control Register
The RAM control register (RAMCR) enables or disables access to the on-chip RAM and controls
RAM area overlapping. For details of RAM area overlapping, see section 19.2.4, "RAM Control
Register (RAMCR)."
Bit 7 6 5 4 3 2 1 0
RAME1 − RAME2 − − RAM2 RAM1 RAM0
Initial value 1 * 1 * * 0 0 0
R/W R/W − R/W − − R/W R/W R/W
RAM2 to RAM0
Reserved bits Specify the RAM area
overlapping flash memory
RAM enable bit 2
Enables or disables access to
on-chip RAM (H'EE80 to H'F67F)
Reserved bit
RAM Enable bit 1

Enables and disables access to on-chip RAM (H'F680 to H'FE7F)
Note: * Bit 6, 4 and 3 have undetermined values when read.
(1) Bits 7—and 5-RAM Enable 1 and 2 (RAME1, RAME2): These bits enable or disable
access to on-chip RAM.
Bit 7
RAME1 Description
0 On-chip RAM (H'F680 to H'FE7F) cannot be accessed
1 On-chip RAM (H'F680 to H'FE7F) can be accessed (Initial value)
Bit 5
RAME2 Description
0 On-chip RAM (H'EE80 to H'F67F) cannot be accessed
1 On-chip RAM (H'EE80 to H'F67F) can be accessed (Initial value)
The RAME1 and RAME2 bits are initialized on the rising edge of the reset signal. They are not
initialized in software standby mode. In modes 1 to 6, when the RAME1 and RAME2 bits are
cleared to 0 to disable access to on-chip RAM, addresses H'F680 to H'FE7F and H'EE80 to
H'F67F become an external memory area.
Rev. 3.0, 02/99, page 505 of 904

(2) Bits 6, 4, and 3—Reserved: Bit 6, 4 and 3 have undetermined values when read, and cannot
be modified.
(3) Bits 2 to 0: RAM2 to RAM0: Bits 2 to 0 are used in RAM emulation of flash memory. For
details, see section 19.2.4, RAM Control Register (RAMCR).
17.3 Operation
17.3.1 Expanded Modes (Modes 1 to 6)
In the expanded modes (modes 1 to 6), when bits RAME1 and RAME2 are set to 1, accesses to
addresses H'F680 to H'FE7F and H'EE80 to H'F67F are directed to the on-chip RAM. When bits
RAME1 and RAME2 are cleared to 0, accesses to addresses H'F680 to H'FE7F and H'EE80 to
H'F67F are directed to off-chip memory.
17.3.2 Single-Chip Mode (Mode 7)
In single-chip mode (mode 7), when bits RAME1 and RAME2 are set to 1, accesses to addresses
H'F680 to H'FE7F and H'EE80 to H'F67F are directed to the on-chip RAM. When bits RAME1
and RAME2 are cleared to 0, any type of access to addresses H'F680 to H'FE7F and H'EE80 to
H'F67F (instruction fetch or data read/write) causes an address error. For the exception handling
when an address error occurs, see section 4, "Exception Handling."
Rev. 3.0, 02/99, page 506 of 904

Section 18 RAM (H8/539F S-Mask and A-Mask Models)
18.1 Overview
The H8/539F S-mask and A-mask models have 4 kbytes of on-chip static RAM. The RAM is
connected to the H8/500 CPU by a 16-bit data bus. The H8/500 CPU accesses both byte data and
word data in two states, making the RAM suitable for rapid data transfer and high-speed
computation.
The on-chip RAM is assigned to addresses H'EE80 to H'FE7F. The RAM control register
(RAMCR) enables this area to be switched between on-chip RAM and external memory.
Figure 18-1 shows a block diagram of the on-chip RAM.
Rev. 3.0, 02/99, page 507 of 904

8
RAME1, 2
Bus interface and control section
2
H'EE80 H'EE81 RAMCR

H'EE82 H'EE83
H'EE84 H'EE85
On-chip RAM (4 kbytes)
H'FE7C H'FE7D
H'FE7E H'FE7F

Legend
RAMCR: RAM control register
Figure 18-1 RAM Block Diagram
The RAM is controlled by the RAM control register (RAMCR). Table 18-1 gives the address and
initial value of RAMCR.
Table 18-1 RAM Control Register

H'FF15 RAM control register RAMCR R/W Undetermined
Rev. 3.0, 02/99, page 508 of 904

18.2 RAM Control Register
RAM area overlapping. For details of RAM area overlapping, see section 20.2.3, "RAM Control
Register (RAMCR)."
Bit 7 6 5 4 3 2 1 0
RAME1 − RAME2 − − RAM2 RAM1 −
Initial value 1 * 1 * * 0 0 *
R/W R/W − R/W − − R/W R/W −
RAM2 and RAM1 Reserved bit
Reserved bits Specify the RAM area
overlapping flash memory
RAM enable bit 2
Reserved bit
RAM Enable bit 1

Enables and disables access to on-chip RAM (H'F680 to H'FE7F)
Note: * Bit 6, 4, 3 and 0 have undetermined values when read.
Bits 7 and 5—RAM Enable 1 and 2 (RAME1, RAME2): These bits enable or disable access to
on-chip RAM.
Bit 7
RAME1 Description
0 On-chip RAM (H'F680 to H'FE7F) cannot be accessed
1 On-chip RAM (H'F680 to H'FE7F) can be accessed (Initial value)
Bit 5
RAME2 Description
0 On-chip RAM (H'EE80 to H'F67F) cannot be accessed
1 On-chip RAM (H'EE80 to H'F67F) can be accessed (Initial value)
The RAME1 and RAME2 bits are initialized on the rising edge of the reset signal. They are not
initialized in software standby mode. In modes 1 to 6, when the RAME1 and RAME2 bits are
cleared to 0 to disable access to on-chip RAM, addresses H'F680 to H'FE7F and H'EE80 to
H'F67F become an external memory area.
Rev. 3.0, 02/99, page 509 of 904

Bits 6, 4, 3 and 0—Reserved: Bit 6, 4, 3 and 0 are reserved, and have undetermined values when
read. They cannot be modified.
Bits 2 and 1—RAM2 and RAM1: Bits 2 and 1 are used in RAM emulation of flash memory.
For details, see section 20.2.3, RAM Control Register (RAMCR).
18.3 Operation
18.3.1 Expanded Modes (Modes 1 to 6)
In the expanded modes (modes 1 to 6), when bits RAME1 and RAME2 are set to 1, accesses to
addresses H'F680 to H'FE7F and H'EE80 to H'F67F are directed to the on-chip RAM. When bits
RAME1 and RAME2 are cleared to 0, accesses to addresses H'F680 to H'FE7F and H'EE80 to
H'F67F are directed to off-chip memory.
18.3.2 Single-Chip Mode (Mode 7)
In single-chip mode (mode 7), when bits RAME1 and RAME2 are set to 1, accesses to addresses
H'F680 to H'FE7F and H'EE80 to H'F67F are directed to the on-chip RAM. When bits RAME1
and RAME2 are cleared to 0, any type of access to addresses H'F680 to H'FE7F and H'EE80 to
H'F67F (instruction fetch or data read/write) causes an address error. For the exception handling
when an address error occurs, see section 4, "Exception Handling."
Rev. 3.0, 02/99, page 510 of 904

(H8/539F) Dual power source system (VPP = 12 V)
19.1 Overview
19.1.1 Flash Memory Overview
Table 19-1 illustrates the principle of operation of the dual power source system H8/539F's on-
chip flash memory.
Like EPROM, flash memory is programmed by applying a high gate-to-drain voltage that draws
hot electrons generated in the vicinity of the drain into a floating gate. The threshold voltage of a
programmed memory cell is therefore higher than that of an erased cell. Cells are erased by
grounding the gate and applying a high voltage to the source, causing the electrons stored in the
floating gate to tunnel out. After erasure, the threshold voltage drops. A memory cell is read like
an EPROM cell, by driving the gate to the high level and detecting the drain current, which
depends on the threshold voltage. Erasing must be done carefully, because if a memory cell is
overerased, its threshold voltage may become negative, causing the cell to operate incorrectly.
Section 19.4.6 shows an optimal erase control flowchart and sample program.
Table 19-1 Principle of Memory Cell Operation
Program Erase Read

Memory Vg = VPP Vg = VCC
Vs = VPP Open
cell
Vd Vd
Memory Vd 0V Open Open Vd 0V

array
VPP 0V VCC
0V VPP 0V
0V 0V 0V
Rev. 3.0, 02/99, page 511 of 904

19.1.2 Mode Programming and ROM Address Space
As its on-chip ROM, the H8/539F has 128 kbytes of flash memory. ROM is connected to the
CPU by a 16-bit data bus. The CPU accesses both byte data and word data in two states.
The flash memory is assigned to addresses H'00000 to H'03FFF and H'10000 to H'2FFFF on the
memory map. The contents of flash memory addresses H'00000 to H'03FFF are the same as the
contents of addresses H'10000 to H'13FFF. The mode pins enable either on-chip flash memory or
external memory to be selected for this area. Table 19-2 summarizes the mode pin settings and
usage of the flash memory area.
Table 19-2 Mode Pin Settings and Flash Memory Area
Mode Pin Setting

Mode MD2 MD1 MD0 Flash Memory Area Usage
Mode 0 0 0 0 Illegal setting
Mode 1 0 0 1 External memory area
Mode 2* 0 1 0 On-chip flash memory area
Mode 4 1 0 0 On-chip flash memory area
Mode 7 1 1 1 On-chip flash memory area
Note: * Boot mode cannot be used in mode 2 in the dual power source H8/539F.
Neither boot mode nor user program mode can be used in mode 2 in the single power
source H8/539F (S-mask and A-mask models).
For details of the single power source system, see section 20, Flash Memory (H8/539F
S-Mask and A-Mask Models, Single Power Source).
Rev. 3.0, 02/99, page 512 of 904

19.1.3 Features
Features of the flash memory are listed below.
• Five flash memory operating modes

The flash memory has five operating modes: program mode, program-verify mode, erase
mode, erase-verify mode, and prewrite-verify mode.
• Block erase designation
Blocks to be programmed or erased in the flash memory address space can be selected by bit
settings. The address space includes a large-block area (seven 16-kbyte blocks and one 12-
kbyte block) and a small-block area (eight 512-byte blocks ).
• Program and erase time
Programming one byte of flash memory typically takes 50 µs. Erasing typically takes 1 s.
• Erase-program cycles
Flash memory contents can be erased and reprogrammed up to 100 times.
• On-board programming modes
These modes can be used to program, erase, and verify flash memory contents. There are two
modes: boot mode, and user programming mode.
• Automatic bit-rate alignment
In boot-mode data transfer, the H8/539F aligns its bit rate automatically to the host bit rate
(9600 bps, 4800 bps, 2400 bps).
• Flash memory emulation by RAM
Part of the RAM area can be overlapped onto flash memory, to emulate flash memory updates
in real time.
• PROM mode
As an alternative to on-board programming, the flash memory can be programmed and erased
in PROM mode, using a general-purpose PROM programmer.
Rev. 3.0, 02/99, page 513 of 904

Figure 19-1 shows a block diagram of the flash memory.
Internal data bus (upper)
8
Internal data bus (lower)
MD2
Operating
FLMCR Bus interface and control section MD1
mode
MD0
EBR1 H'0000 H'0001

H'0002 H'0003
EBR2
H'0004 H'0005
On-chip flash memory
(128 kbytes)
H'2FFFC H'2FFFD
H'2FFFE H'2FFFF
Legend
FLMCR: Flash memory control register
EBR1: Erase block register 1
Note: Memory at addresses H'10000 to H'13FFF can also be read from addresses
H'00000 to H'03FFF. The space comprising addresses H'10000 to H'13FFF
is an image of addresses H'00000 to H'03FFFF.
Figure 19-1 Flash Memory Block Diagram
Rev. 3.0, 02/99, page 514 of 904

Flash memory is controlled by the pins listed in table 19-3.
Table 19-3 Flash Memory Pins
Pin Name Abbreviation Input/Output Function

Programming power VPP Power supply Apply 12.0 V
Mode 2 MD2 Input H8/539F operating mode
programming
programming
programming
Transmit data TXD1 Output Serial transmit data output
Receive data RXD1 Input Serial receive data input
The transmit data and receive data pins are used in boot mode.
The flash memory is controlled by the registers listed in table 19-4.

3
Table 19-4 Flash Memory Registers*
Name Abbreviation R/W Initial Value Address

Flash memory control register FLMCR R/W H'00 or H'80 H'FEE0
Erase block register 1 EBR1 R/W H'00 H'FEE2
1 2
RAM control register* RAMCR R/W Undetermined* H'FF15
Flash memory emulation register FLMER R/W H'71 H'FEEC
Flash memory status register FLMSR R H'7F H'FEED
Notes: 1. The RAM control register enables or disables access to the on-chip RAM, but it is also
used in this chapter for RAM area setting in on-board programming mode.
2. Bits 6, 4, and 3 are reserved for system use. They cannot be written to, and will return
an undetermined value if read.
3. These registers and bits (bits 2 to 0 of RAMCR) are used only for flash memory control,
and are not present in mask and ZTAT versions. Registers and bits exclusively for
flash memory use should not be accessed in mask and ZTAT versions; if they are, a
read will return H'FF (or 1 in the case of RAMCR bits 2 to 0), and writes will be invalid.
Rev. 3.0, 02/99, page 515 of 904

19.2.1 Flash Memory Control Register (FLMCR)
The flash memory control register (FLMCR) is an eight-bit register that controls the flash memory
operating modes. Transitions to program mode, erase mode, program-verify mode, and erase-
verify mode are made by setting bits in this register. FLMCR is initialized to H'00 by a reset, in
the standby modes, and when 12 V is not applied to VPP. When 12 V is applied to VPP, a reset or
entry to a standby mode initializes FLMCR to H'80. The FLMCR bit structure is shown next.
It is not possible to set the EV, PV, E, or P bit, or any bit in the EBR1 or EBR2 register, to 1, until
the VPPE bit is set.
Bit 7 6 5 4 3 2 1 0
Vpp VppE − − EV PV E P
R/W R R/W − − R/W R/W R/W R/W
Program mode
Designates
transition to
or exit from
program mode
Erase mode
Designates transition
to or exit from erase
mode
Program-verify mode
Designates transition to
or exit from program-verify
mode
Erase-verify mode
Designates transition to
Reserved bits or exit from erase-verify
mode
Vpp enable
Designates enabling or disabling
of 12 V application to Vpp
Programming power
Status flag indicating that
12 V is applied to Vpp
Rev. 3.0, 02/99, page 516 of 904

Bit 7Programming Power (VPP): The programming power supply bit (VPP) indicates the
voltage level detected at the VPP pin as 1 or 0. For the threshold value, see high voltage application
criterion level VH in section 22.2.1, DC Characteristics. For further information, see note 3 in
section 19.7, "Flash Memory Programming and Erasing Precautions."
Bit 7
VPP Description
0 Cleared when 12 V is not applied to VPP (Initial value)
1 Set when 12 V is applied to VPP
VPP Enable (VPPE)* * * : Selects enabling or disabling of 12 V application to the VPP pin.
1 2 3
Bit 6
When programming and erasing, a wait of at least 5 µs is necessary after setting this bit to allow
on-chip oscillation to settle. The VPPE bit should only be cleared after the other bits (the P, E, PV,
and EV bits) have been cleared.
Bit 6
VPPE Description
0 On-chip power supply disabled (Initial value)
1 On-chip power supply enabled

Bits 5 to 4
Erase-Verify Mode (EV):* Selects transition to or exit from erase-verify mode.

1
Bit 3
Bit 3
EV Description
0 Exit from erase-verify mode (Initial value)
1 Transition to erase-verify mode
Erase-Verify Mode (PV):* Selects transition to or exit from program-verify mode.

1
Bit 2
Bit 2
PV Description
0 Exit from program-verify mode (Initial value)
1 Transition to program-verify mode
Rev. 3.0, 02/99, page 517 of 904

Erase Mode (E):* * Selects transition to or exit from erase mode.
1 4
Bit 1
Bit 1
E Description
0 Exit from erase mode (Initial value)
1 Transition to erase mode
Program Mode (P):* * Selects transition to or exit from program mode.

1 4
Bit 0
Bit 0
P Description
0 Exit from program mode (Initial value)
1 Transition to program mode
Notes: 1. Do not set two or more of these bits simultaneously.
Do not cut the VCC or VPP power while any of these bits is set.
2. Do not or clear the VPPE bit at the same time as another bit (the P, E, PV, or EV bit).
3. Do not set or clear the VPPE bit during execution of a program in flash memory. For
details, see item (3) in section 19.7, "Flash Memory Programming and Erasing
Precautions."
4. Set the P and E bits in accordance with the programming and erasing algorithms shown
in section 19.4, "Programming and Erasing Flash Memory." When one of these bits is
set, watchdog timer setting should be carried out beforehand to provide for the
possibility of program runaway. See section 19.7, "Flash Memory Programming and
Erasing Precautions" for notes on the use of these bits.
19.2.2 Erase Block Register 1 (EBR1)
Erase block register 1 (EBR1) is an eight-bit register that designates large flash-memory blocks for
erasure. EBR1 is initialized to H'00 by a reset, in the standby modes, and when 12 V is not
applied to VPP. When a bit in EBR1 is set to 1, the corresponding block is selected and can be
erased. Figure 19-2 shows a block map. No bits in the EBR1 or EBR2 register can be set to 1
until the VPPE bit is set to 1 in the FLMCR register.
Bit 7 6 5 4 3 2 1 0
LB7 LB6 LB5 LB4 LB3 LB2 LB1 LB0
Rev. 3.0, 02/99, page 518 of 904

Large Block 7 to 0 (LB7 to LB0): These bits select large blocks (LB7 to LB0) to be
Bits 7 to 0
erased.
Bits 7 to 0
LB7 to LB0 Description
0 Block LB7 to LB0 is not selected (Initial value)
1 Block LB7 to LB0 is selected
Erase block register 2 (EBR2) is an eight-bit register that selects small flash-memory blocks for
programming and erasure. EBR2 is initialized to H'00 by a reset, in the standby modes, and when
12 V is not applied to VPP. When a bit in EBR2 is set to 1, the corresponding block is selected for
programming and erasure. Figure 19-2 shows a block map.
Bit 7 6 5 4 3 2 1 0
SB7 SB6 SB5 SB4 SB3 SB2 SB1 SB0
Small Block 7 to 0 (SB7 to SB0): These bits select small blocks (SB7 to SB0) to be
Bits 7 to 0
programmed and erased.
Bits 7 to 0
SB7 to SB0 Description
0 Block SB7 to SB0 is not selected (Initial value)
1 Block SB7 to SB0 is selected
Rev. 3.0, 02/99, page 519 of 904

Page 1/2 Page 0
Corresponding
Addresses Addresses Addresses
Bit
H'10000 H'0000
H'0000−H'02FFF
LB7 (H'10000−H'12FFF) 12 kbyte(LB7)
H'12FFF H'2FFF
H'13000 H'3000
LB6 H'14000−H'17FFF 512 byte(SB0)
H'131FF H'31FF
H'13200 H'3200
LB5 H'18000−H'1BFFF 512 byte(SB1)
H'133FF H'33FF
H'13400 H'3400
LB4 H'1C000−H'1FFFF 512 byte(SB2)
Large block H'135FF H'35FF Mapping*
area H'13600 H'3600 area
(124 kbytes) LB3 H'20000−H'23FFF 512 byte(SB3) (16 kbytes)
H'137FF H'37FF
H'13800 H'3800
LB2 H'24000−H'27FFF 512 byte(SB4)
H'139FF H'39FF
H'13A00 H'3A00
LB1 H'28000−H'2BFFF 512 byte(SB5)
H'13BFF H'3BFF
H'13C00 H'3C00
LB0 H'2C000−H'2FFFF 512 byte(SB6)
H'13DFF H'3DFF
H'3000−H'31FF H'13E00 H'3E00
SB0 (H'13000−H'131FF) 512 byte(SB7)
H'13FFF H'3FFF
H'3200−H'33FF H'14000
SB1 (H'13200−H'133FF) 16 kbyte(LB6)
H'17FFF
H'3400−H'35FF H'18000
SB2 (H'13400−H'135FF) 16 kbyte(LB5)
Small block H'1BFFF Non-mapping
H'3600−H'37FF H'1C000
area SB3 16 kbyte(LB4) area
(4 kbytes) (H'13600−H'137FF) (112 kbytes)
H'1FFFF
H'3800−H39FF H'20000
SB4 (H'13800−H'139FF) 16 kbyte(LB3)
H'23FFF
H'3A00−H'3BFF H'24000
SB5 (H'13A00−H'13BFF) 16 kbyte(LB2)
H'27FFF
H'3C00−H'3DFF H'28000
SB6 16 kbyte(LB1)
(H'13C00−H'13DFF)
H'2BFFF
H'3E00−H'3FFF H'2C000
SB7 16 kbyte(LB0)
(H'13E00−H'13FFF)
H'2FFFF
Note: * The mapping area can be accessed from both page 0 and page 1.
If addresses for which only the page is different are specified (e.g. H'02FFF and H'12FFF),
the same memory will be accessed. Consequently, when performing programming or
erasing on this mapping area, only page 0 or page 1, but not both, should be specified.
When the RAM emulation function is used to overlap RAM onto a ROM area,
the overlapped page 0 RAM area is not mapped in page 1 (since RAM emulation can
only be used in page 0). In this case, a read access to page 1 will return the ROM contents.
Figure 19-2 Erase Block Map
Rev. 3.0, 02/99, page 520 of 904

19.2.4 RAM Control Register (RAMCR)
RAM area overlapping.
Bit 7 6 5 4 3 2 1 0
RAME − RAME2 − − RAM2 RAM1 RAM0
Initial value 1 * 1 * * 0 0 0
R/W R/W − R/W − − R/W R/W R/W
RAM2/1/0
Specify a flash-memory
area to be overlapped
by RAM
Reserved bits
RAM enable 2
Reserved bit
RAM enable 1
Enables or disables access to on-chip RAM
(H'F680 to H'FE7F)
Note: * Bit 6, 4, and 3 have undetermined values when read.
Bits 7 and 5RAM Enable 1 and 2 (RAME1, RAME2): When bit 7 or 5 is cleared to 0, access
to the respective on-chip RAM area is disabled. For details see section 17.2, "RAM Control
Register."
Reserved: Bit 6, 4, 3 have undetermined values when read. They cannot be

Bits 6, 4, and 3
modified.
RAM2 to RAM0: Bits 2 to 0 are used together with bits 7, 3, 2, and 1 of the flash
Bits 2 to 0
memory emulation register (FLMER) to specify a ROM area for which overlapping is to be
performed (see table 19-5). In modes 2, 4, and 7 (with on-chip flash memory enabled), the initial
value of these bits is 0, but they can be modified by writing 1*. In other modes these bits cannot
be modified and always read 0. They are initialized by a reset and in hardware standby mode.
They are not initialized in software standby mode.
Rev. 3.0, 02/99, page 521 of 904

Note: * Bits 2 to 0 of the RAM control register (RAMCR) can be written to in modes 2, 4, and 7.
(In the H8/538F it was necessary to apply 12 V as the program voltage VPP when
performing RAM emulation, but in the H8/539F RAM emulation can be performed
regardless of the VPP voltage.)
19.2.5 Flash Memory Emulation Register (FLMER)
The flash memory emulation register (FLMER) performs enabling and disabling of flash memory
RAM emulation and RAM area modification when RAM emulation is started.
Bit 7 6 5 4 3 2 1 0
OVLPE − − − A11E A10E A9E −
R/W R/W − − − R/W R/W R/W −
Reserved bits
A9E bit
Bits A11E to A9E
specify a RAM area
to be overlapped onto
flash memory
A10E bit
Bits A11E to A9E
specify a RAM area
flash memory
A11E bit
Bits A11E to A9E
specify a RAM area
flash memory
Reserved bit
Emulation RAM enable (overlap RAM enable)

Enables or disables overlapping of a part of RAM
onto a flash memory samll block area
Bit 7Emulation RAM Enable (OVLPE): Used with 3 to 1 to specify a RAM area (see table
19-5). When bit 7 is set, all flash memory blocks are protected from programming and erasing,
1
regardless of the values of bits 3 to 1. This state is referred to as emulation protection* . In this
state the flash memory will not enter program mode or erase mode even if the P or E bit is set in
the flash memory control register (FLMCR). Only transitions to verify modes are possible. Bit 7
must be cleared to 0 to enable flash memory to be actually programmed or eraed.
Rev. 3.0, 02/99, page 522 of 904

In modes 2, 4, and 7 (with on-chip flash memory enabled), the initial value of this bit is 0, but it
2
can be modified by writing 1* . In other modes this bit cannot be modified and always reads 0. It
is initialized by a reset and in hardware standby mode. It is not initialized in software standby
mode.
A11E to A9E: Bits 3 to 1 select the RAM area to be overlapped onto ROM when
Bits 3 to 1
performing RAM emulation of flash memory (see table 19-6).
In modes 2, 4, and 7 (with on-chip flash memory enabled), the initial value of these bits is 0, but
they can be modified by writing. In other modes, these bits cannot be modified and always read 0.
They are initialized by a reset and in hardware standby mode. They are not initialized in software
standby mode.
Notes: 1. For details of emulation protection, see section 19.4.8, "Protect Modes."
2. Bits 7, 3, 2, and 1 of the flash memory emulation register (FLMER) and bits 2 to 0 of
the RAM control register (RAMCR) can be written to in modes 2, 4, and 7.
19.2.6 Flash Memory Status Register (FLMSR)
The flash memory status register (FLMSR) is used to detect a flash memory error.
Bit 7 6 5 4 3 2 1 0
FLER − − − − − − −
R/W R − − − − − − −
Reserved bit
Flash memory error

Status flag indicating that an error was
detected during programming or erasing
Rev. 3.0, 02/99, page 523 of 904

Bit 7—Flash Memory Error (FLER): Indicates that an error occurred while flash was being
1
programmed or erased. When bit 7 is set, flash memory is placed in an error-mode.*
Bits 7
FLER Description
0 Flash memory is not write/erase-protected (Initial value)
1
(is not in error protect mode* )
Reset by 5(6 pin* or hardwer standby mode
3
1 Indicates that an error occurred while flash memory was being programmed or
1
erased, and error protection* is in effect
[Setting conditions]
•
2
Flash memory was read* while being programmed or erased (including vector
read or instruction fetch, but not including reading of a RAM area overlapped
onto flash memory).
• A hardware exception-handling sequence (other than a reset, invalid
instruction, trap instruction, or zero-divide exception) was executed just before
4
programming erasing.*
• The SLEEP instruction (for transition to sleep mode or software standby mode)
was executed during programming or erasing.
Note: 1. For details, see section 19.4.8, "Protect Modes."

2. The read data has undetermined values.
3. In the H8/538F a watchdog timer reset is included in the FLER bit clearing conditions,
but in the H8/539F only 5(6 pin input is applicable.
4. This is before stack and vector reads are performed in exception handling.
Rev. 3.0, 02/99, page 524 of 904

Table 19-5 ROM Area Setting
FLMER RAMCR Register

ROM Area Register Program
Bit 2* 1 Bit 1* 1 Bit 0* 1 Overlap
(Mapping RAM Bit 7* 1 /Erase
Function
Area) OVLPE RAM2 RAM1 RAM0 Protection
− 0 0/1 0/1 0/1 Disabled Enabled
H'3000-H'31FF 1 0 0 0 Enabled Enabled
H'3A00-H'3BFF 1 1 0 1 Enabled Enabled
H'3C00-H'3DFF 1 1 1 0 Enabled Enabled
H'3E00-H'3FFF 1 1 1 1 Enabled Enabled
2
Table 19-6 RAM Area* Setting
FLMER Register RAMCR Register

RAM Area* 2
(Mapping RAM Bit 3* 1 Bit 2* 1 Bit 1* 1 Bit 7* 1 Bit 5* 1
Area) A11E A10E A9E RAME1 RAME2
H'F000-H'F1FF 0 0 0 1 1
(512 byts)
H'F200-H'F3FF
0 0 1 1 1
(512 byts)
H'F400-H'F5FF
0 1 0 1 1
(512 byts)
H'F600-H'F7FF
0 1 1 1 1
(512 byts)
H'F800-H'F9FF
1 0 0 1 1
(512 byts)
H'FA00-H'FBFF
(512 byts) 1 0 1 1 1
H'FC00-H'FDFF
(512 byts) 1 1 0 1 1
Use prohibited * 3 1 1 1 1 1
Use prohibited * 4 0/1 0/1 0/1 0/1 * 4 0/1 * 4
Rev. 3.0, 02/99, page 525 of 904

Notes: 1. Bits 7, 3, 2, and 1 of the flash memory emulation register (FLMER) and bits 2 to 0 of the
RAM control register (RAMCR) can be written to in modes 2, 4, and 7.
2. RAM area overlapped onto flash memory
3. When A11E and A10E are both set to 1, A9E is always cleared to 0.
4. Use prohibited when RAME1=0 or RAME2=0. (Can be used when RAME1=RAME2=1.)
Example of Overlapping of ROM and RAM Areas
ROM area RAM area

H'3000 H'F000
SB0
H'31FF H'F1FF
H'3200 H'F200
to SB1 to
H'33FF H'F3FF
H'3400 H'F400
to SB2 to
ROM H'35FF H'F5FF RAM
small block H'3600 Selected H'F600 overlapping
SB0 to SB7 to Mapping RAM ROM to areas
(H'3000 to H'37FF SB3 area H'F7FF (H'F000 to
H'3FFF) H'3800 H'F800 H'FDFF)
to Selected to
SB4 RAM Actual RAM
H'39FF area H'F9FF
H'3A00 H'FA00
to to
H'3BFF
SB5 H'FBFF
H'3C00 H'FC00
to to
H'3DFF SB6
H'3E00 H'FDFF
to
SB7
H'3FFF
Rev. 3.0, 02/99, page 526 of 904

19.3 On-Board Programming Modes
When an on-board programming mode is selected, the on-chip flash memory can be programmed,
erased, and verified. There are two on-board programming modes: boot mode, and user program
mode. These modes are selected by inputs at the mode pins (MD2 to MD0) and VPP pin. Table 19-
7 indicates how to select the on-board programming modes. Boot mode cannot be used in the
H8/539F's mode 2 (on-chip ROM enabled). For information about turning VPP on and off, and VPP
and MD2 pin circuit examples, see section 19.7, Flash Memory Programming and Erasing
Precautions, and section 19.8, Notes on Mounting Board Development—Handling of VPP and MD2
Pins.
Table 19-7 On-Board Programming Mode Selection
Mode Selection VPP MD2 MD1 MD0 Notes

Boot mode Mode 4 12 V * 12 V * 0 0 0:VIL
Mode 7 12 V * 1 1 1:VIH
User program Mode 2 0 1 0
mode
Mode 4 1 0 0
Mode 7 1 1 1
Notes: * (1) For the timing of turning VPP on, see notes 6 to 8 in "Notes on Use of Boot Mode." Set
the 12 V application level to 12.0 ± 0.6 V.
(2) In boot mode, the mode control register (MDCR) can monitor the mode 4 or 7 status in
the same way as in normal mode.
19.3.1 Boot Mode
To use boot mode, a user program for programming and erasing the flash memory must be
provided in advance on the host machine (which may be a personal computer). Serial
communication interface channel 1 is used in asynchronous mode. If the H8/539F is placed in
boot mode, after it comes out of reset, a built-in boot program is activated. This program starts by
measuring the low period of data transmitted from the host and setting the bit rate register (BRR)
accordingly. The H8/539F's built-in serial communication interface (SCI) can then be used to
download the user program from the host machine. The user program is stored in on-chip RAM.
After the program has been stored, execution branches to the start address of the user program in
on-chip RAM (H'F380), and the program stored on RAM is executed to program and erase the
flash memory. Figure 19-4 shows the boot-mode execution procedure.
Rev. 3.0, 02/99, page 527 of 904

H8/539F
Receive data to be programmed

RXD1
HOST SCI
Transmit verification data
TXD1
Figure 19-3 Boot-Mode System Configuration
Rev. 3.0, 02/99, page 528 of 904

Boot-Mode Execution Procedure: Figure 19-4 shows the boot-mode execution procedure.
Start
1. Program the H8/539F pins for boot mode, and
start the H8/539F from a reset.
1 Program H8/539F pins for boot mode, 2. Set the host's data format to 8 bits + 1 stop bit,
and reset select the desired bit rate (2400, 4800, or 9600
bps), and transmit H'00 data continuously.
3. The H8/539F repeatedly measures the low period
2 Host transmits H'00 data continuously
at desired bit rate of the RXD1 pin and calculates the host's
asynchronous-communication bit rate.
4. When SCI bit-rate alignment is completed, the
H8/539F measures low period H8/539F transmits one H'00 data byte to indicate
of H'00 data transmitted from host completion of alignment.
3 5. The host should receive the byte transmitted from
H8/539F computes bit rate and the H8/539F to indicate that bit-rate alignment is
sets bit rate register completed, check that this byte is received
normally, then transmit one H'55 byte.
6. After transmitting H'55, the host transmits the byte
After completing bit-rate alignment, H8/539F length of the user program to be transferred to the
4 sends one H'00 data byte to host to indicate H8/539F. The byte length must be sent as two-
that alignment is completed byte data, most significant byte first and least
significant byte second. After that, the host
Host checks that this byte, indicating proceeds to transmit the user program. As
5 completion of bit-rate alignment, is received verification, the H8/539F echoes each byte of the
normally, then transmits one H'55 byte received byte-length data and user program back
to the host.
7. The H8/539F stores the received user program in
H8/539F receives two bytes indicating byte on-chip RAM in a 2.8-kbyte area from H'F380 to
6 length (N) of program to be downloaded
H'FE7F.
to on-chip RAM*1
8. Before executing the downloaded user program,
the H8/539F branches to the boot program area in
RAM (H'EE80 to H'F37F), then checks whether
H8/539F transfers one user program the flash memory already contains any
byte to RAM*2 programmed data. If so, all bocks are erased.
9. The H8/539F branches to address H'F380 in on-
H8/539F calculates number of bytes left chip RAM and executes the user program stored
7 to be transferred (N = N - 1) in the area from H'F380 to H'FE7F.
Notes: 1. The user can use 2.8 kbytes of RAM. The

All bytes transferred? No number of bytes transferred must not
(N = 0?) exceed 2.8 kbytes. Be sure to transmit the
byte length in two bytes, most significant
Yes
byte first and least significant byte second.
H8/539F branches to boot program area For example, if the byte length of the
in RAM (H'EE80 to H'F37F), program to be transferred is 256 bytes
then checks user area data in flash memory (H'0100), transmit H'01 as the most
significant byte, followed by H'00 as the
least significant byte.
8 No 2. The part of the user program that controls
All data = H'FF? the flash memory should be coded
according to the flash memory
Yes Erase all flash program/erase algorithms given later.
memory blocks*3 3. If a memory cell malfunctions and cannot
be erased, the H8/539F transmits one H'FF
byte to report an erase error, halts erasing,
9 H8/539F branches to H'F380 in RAM area and and halts further operations.
executes user program downloaded into RAM
Figure 19-4 Boot Mode Flowchart
Rev. 3.0, 02/99, page 529 of 904

Automatic Alignment of SCI Bit Rate
Start Stop
D0 D1 D2 D3 D4 D5 D6 D7
bit bit
This low period (9 bits) is measured (H'00 data)

High for at
least 1 bit
Figure 19-5 Measurement of Low Period in Data Transmitted from Host
When started in boot mode, the H8/539F measures the low period in asynchronous SCI data
transmitted from the host (figure 19-5). The data format is eight data bits, one stop bit, and no
parity bit. From the measured low period (nine bits), the H8/539F computes the host's bit rate.
After aligning its own bit rate, the H8/539F sends the host one byte of H'00 data to indicate that
bit-rate alignment is completed. The host should check that this alignment-completed indication is
received normally, then transmit one H'55 byte. If the host does not receive a normal alignment-
completed indication, the H8/539F should be reset, then restarted in boot mode to measure the low
period again. There may be some alignment error between the host's and H8/539F's bit rates,
depending on the host's bit rate and the H8/539F's system clock frequency. To have the SCI
1
operate normally, set the host's bit rate to 2400, 4800, or 9600 bps.* Table 19-8 lists typical host
bit rates and indicates the clock-frequency ranges over which the H8/539F can align its bit rate
2
automatically. Boot mode should be used within these frequency ranges.*
Table 19-8 System Clock Frequencies Permitting Automatic Bit-Rate Alignment by

H8/539F
System Clock Frequencies Permitting

Host Bit Rate Automatic Bit-Rate Alignment by H8/539F
9600 bps 8 MHz to 16 MHz
Notes: 1. The host's bit rate should be set only to 2400, 4800, or 9600 bps. Do not set it to other
values.
2. Though host bit rates and system clock frequencies which are not listed in table 18-8
may permit automatic bit-rate alignment by the H8/539F, they cause some alignment
error between the host's and H8/539F's bit rates. Therefore, the SCI cannot operate
normally after such bit-rate alignment. Boot mode should be used within those host bit
rate and system clock frequency ranges listed in table 19-7.
Rev. 3.0, 02/99, page 530 of 904

RAM Area Allocation in Boot Mode: In boot mode, the 1280 bytes from H'EE80 to H'F37F are
reserved for use by the boot program. The user program is transferred into the area from H'F380
to H'FE7F (2.75 kbytes). The boot program area is used during the transition to execution of the
user program transferred into RAM.
H'EE80
Boot
program Note: * This area is unavailable until transition
area* to user program execution (branch to
(1.25 kbytes) RAM area address H'F380).
Also note that the boot program remains
H'F380 in the boot program area (H'EE80 to
H'F37F) in RAM after the branch to the
user program.
User program
transfer area
(2.75 kbytes)
H'FE7F
Figure 19-6 RAM Areas in Boot Mode
Notes on Use of Boot Mode
1. When the H8/539F comes out of reset in boot mode, it measures the low period of the input at
the SCI's RXD1 pin. The reset should end with RXD1 high. After the reset ends, it takes about
100 states for the H8/539F to get ready to measure the low period of the RXD1 input.
2. In boot mode, if any data has been programmed into the flash memory (if all data are not
H'FF), all flash memory blocks are erased. Boot mode is for use when user program mode is
unavailable, e.g. the first time on-board programming is performed, or if the update program
activated in user program mode is accidentally erased.
3. Interrupts cannot be used while the flash memory is being programmed or erased.
4. The RXD1 and TXD1 lines should be pulled up on-board.
5. Before branching to the user program (at address H'F380 in the RAM area), the H8/539F
terminates transmit and receive operations by the on-chip SCI (by clearing the RE and TE bits
to 0 in the serial control register (SCR)), but the auto-aligned bit rate remains set in bit rate
register BRR1. The transmit data pin (TXD1) is in the high output state (in port 7, the P72DDR
and P72DR bits are set to 1).
When the branch to the user program occurs, the contents of general registers in the CPU are
undetermined. After the branch, the user program should begin by initializing general registers,
especially the stack pointer (SP), which is used implicitly in subroutine calls and at other
times. The stack pointer must be set to provide a stack area for use by the user program. The
other on-chip registers do not have specific initialization requirements.
Rev. 3.0, 02/99, page 531 of 904

6. In a transition to boot mode, a reset start can be performed after applying 12 V to the MD2 and
VPP pins in accordance with the mode setting conditions in table 19-6. The H8/539F latches
1
the mode pin state internally when the reset is cleared (low-to-high transition)* , and the boot
mode state is retained.
1
Boot mode can be exited by a reset clearance* after clearing 12 V application to the MD2 and
VPP pins, but the following points need to be noted.
(a) When switching from boot mode to normal mode (VPP ≠ 12 V, MD2 ≠ 12 V), the
microcontroller's internal boot mode state must first be cleared by reset input using the
5(6 pin.
In this case, the interval required between cutting VPP and reset clearance is the flash
2
memory read setup time (tFRS)* .
(b) If application of 12 V to the MD2 pin is cleared during boot mode, the microcontroller's
internal boot mode state will be retained and boot mode will continue unless reset input is
performed using the 5(6 pin.
If a watchdog timer reset occurs in the boot mode state, the microcontroller's internal mode
state will not be cleared, and the on-chip boot program will be restarted regardless of the
mode pin state.
(c) When switching to boot mode (when reset is cleared) and during a boot mode operation,
ensure that the program voltage VPP stays within the range 12 V ± 0.6 V. Boot mode
execution will not be performed correctly outside this range. Also, do not cut VPP during
2
boot program execution, or during flash memory programming or erasing* .
Notes: 1. With regard to mode pin input, the mode programming setup time (tMDS) must be
satisfied with respect to reset clearance timing. When 12 V is applied/cut at the MD2
pin, there will be a delay in the rise and fall waveforms due to the effect of the pull-
up/pull-down resistor, etc., connected at the MD2 pin. This delay must be confirmed in
practice in the design process. For the MD2 pin threshold value, see high voltage
application criterion level VH in section 22.2.1, DC Characteristics.
2. See note 3 in section 19.7. "Flash Memory Programming and Erasing Precautions" for
notes on VPP application/cutoff. For the VPP pin threshold value, see high voltage
application criterion level VH in section 22.2.1, DC Characteristics.
7. If the MD2 pin is changed from 0 V to 12 V or from 12 V to 0 V during a reset (while a low
level is being input at the 5(6 pin), the microcontroller operating mode is changed by the
momentary transition to the 5 V input level. Since the state of multiplexed address/port pins
and bus control output signals ($6, 5', +:5, /:5) changes as a result, use of these pins as
output signals during a reset must be inhibited outside the microcontroller.
8. When applying 12 V to the VPP and MD2 pins, ensure that the peak overshoot does not exceed
the maximum rating of 13 V. Also be sure to connect decoupling capacitors to the VPP and
MD2 pins. Circuit examples are shown in figure 19-24 in section 19.7, Flash Memory
Programming and Erasing Precautions, and in section 19.8, Notes on Mounting Board
Development—Handling of VPP and MD2 Pins.
Rev. 3.0, 02/99, page 532 of 904

19.3.2 User Program Mode
When set to user program mode, the H8/539F can erase and program its flash memory by
executing a user program. On-board updates of the on-chip flash memory can be carried out by
providing on-board circuits for supplying VPP and data, and storing an update program in part of
the program area.
To select user program mode, select a mode that enables the on-chip ROM (mode 2, 4, or 7) and
apply 12 V to the VPP pin. In this mode, the on-chip peripheral modules operate as they normally
would in mode 2, 4, or 7, except for the flash memory. A watchdog timer overflow, however,
cannot output a reset signal while 12 V is applied to VPP. The watchdog timer's reset output enable
bit (RSTOE) should not be set to 1.
The flash memory cannot be read while being erased, so the update program must either be stored
in external memory, or transferred temporarily to the RAM area and executed in RAM.
Example of User Program Mode Execution Procedure*: Figure 19-7 shows the procedure for
user program mode execution in RAM.
Note: * Do not apply 12 V to the VPP pin during normal operation. To prevent microcontroller
errors caused by accidental programming or erasing, apply 12 V to VPP only when the flash
memory is programmed or erased, or when flash memory is emulated by RAM.
Overprogramming or overerasing due to program runaway, etc., may prevent memory
cells from operating normally. While 12 V is applied, the watchdog timer should be
running and enabled to halt runaway program execution, so that program runaway will not
lead to overprogramming or overerasing.
Rev. 3.0, 02/99, page 533 of 904

In the case of a reset start, activation is possible from user program mode.
1
Procedure
MD2 to MD0= 010, 100, or 111
(MD2 = 0 to 5 V application) The user should write a program that executes operations 3 to 9
below to flash memory in advance.
2
1. Set the mode pins to a mode with on-chip ROM enabled
Reset start (mode 2, 4, or 7).
2. Activate the CPU with a reset. (Activation from user program

3 mode is possible by applying 12 V to the Vpp pin during the
reset, i.e. while the pin is low*.)
Transfer on-board update
program to RAM 3. Transfer the on-board update program to RAM.
4 4. Branch to the program transferred to RAM.
Branch to program in RAM 5. Apply 12V to the VPP pin.*

(Transition to user program mode)
5 6. After applying 12V to VPP, execute the on-board update

program in RAM. This updates the user application program
Vpp=12V
in the flash memory.
(user program mode)
7. After updating, After updating, clear the VPPE bit, switch the
VPP pin from 12 V to VCC, and exit user program mode.*
6 Switch VPP from 12V to VCC, and exit user program mode.*
Execute on-board
update program in RAM
8. After 12V is shut off from the Vpp pin, make sure that flash
(update flash memory) memory-read setup time (tFRS) has elapsed before executing
the program in the flash memory. For further details, see note
5 in section 19.7, "Flash Memory Programming and Erasing
7
Precautions" and section 22.2.4, "Flash Memory
Release Vpp Characteristics."
(exit user program mode)
9. A branch is made to the updated user application program in
the flash memory and this program is executed.
8
Wait until program in
flash memory is executed Note: * For further information about turning VPP on and off, see note 5 in
(flash-memory-read setup time) section 19.7, "Flash Memory Programming and Erasing Precautions."
9
Execute user application
program in flash memory
Figure 19-7 User Program Mode Operation (Example)
Rev. 3.0, 02/99, page 534 of 904

19.4 Programming and Erasing Flash Memory
The H8/539F's on-chip flash memory is programmed and erased by software, using the CPU.
The flash memory can operate in program mode, erase mode, program-verify mode, erase-verify
mode, or prewrite-verify mode. Transitions to these modes can be made by setting the P, E, PV,
and EV bits in the flash memory control register (FLMCR). A wait time of at least 5 µs should be
left after setting the VPPE bit when making a trasition to an operating mode. The area to be
programmed in flash memory (target block is specified by means of erase block registers 1 and 2
(EBR1, EBR2).
The flash memory cannot be read while being programmed or erased. The program that controls
the programming and erasing of the flash memory must be stored and executed in on-chip RAM or
in external memory. A description of each mode is given below, with recommended flowcharts
and sample programs for programming and erasing. Recommended programming and erasing
flowcharts adopt an algorithm which doubles the programming or erasing time successively. This
algorithm can decrease the number of repetitions and shorten the verify time, enabling high-speed
programming and erasing. The high-speed alogorithm is specially effective, when the H8/539F is
used at a low clock frequency.
Section 19.7, "Flash Memory Programming and Erasing Precautions," gives further notes on
programming and erasing. See section 22.2.4, Flash Memory Characteristics, for the wait time
after a bit is set or cleared in the flash memory control register (FLMCR).
19.4.1 Program Mode
To write data into the flash memory, follow the programming algorithm shown in figure 19-8.
This programming algorithm can write data without subjecting the device to voltage stress or
impairing the reliability of programmed data.
To program data, first write the data to the address to be programmed, as in writing to RAM. The
flash memory latches the address and data in an address latch and data latch. Next set the P bit in
FLMCR, selecting program mode. The programming duration is the time during which the P bit is
n-1
set. Programming duration should be set to increase by 2 times (n=1, 2, 3, 4, 5, 6) of the initial
setting value. A software timer should be used to provide an initial setting value of 10 to 15.8 µs.
Set n so that the total programming time does not exceed 1ms. Programming for too long a time,
due to program runaway for example, can cause device damage. Before selecting program mode,
set up the watchdog timer so as to prevent overprogramming.
Rev. 3.0, 02/99, page 535 of 904

19.4.2 Program-Verify Mode
In program-verify mode, after data has been programmed in program mode, the data is read to
check that it has been programmed correctly.
After the programming time has elapsed, exit programming mode (clear the P bit to 0) and select
program-verify mode (set the PV bit to 1). In program-verify mode, a program-verify voltage is
applied to the memory cells at the latched address. If the flash memory is read in this state, the
data at the latched address will be read. After selecting program-verify mode, wait 4 µs or more
before reading, then compare the programmed data with the verify data. If they agree, exit
program-verify mode and program the next address. If they do not agree, select program mode
again and repeat the same program and program-verify sequence. When repeating the program and
program-verify sequence for the same bit, set the total programming time to a maximum of 1ms.
Rev. 3.0, 02/99, page 536 of 904

19.4.3 Programming Flowchart and Sample Program
Flowchart for Programming One Byte
Start
Set VPPE bit
Wait (tvs3) µs *4
Set target block in EBR
n =1
Write data to flash memory

(Flash memory latches write
address and data) *1
Notes: 1. Write the data to be programed with a

Enable watchdog timer*2 byte transfer instruction.
2. Set the timer overflow interval to the
Select program mode shortest value (CKS2, CKS1, CKS0 all
(P bit = 1 in FLMCR) cleared to 0).
3. Read the memory data to be verified
Wait (x) µs *4 with a byte transfer instruction.
4. x:x= initial value x 2n-1 (n=1,2,3,4,5,6)
Clear P bit (exit program mode) (Set an initial value of 10 to 15.8µs)
tvs1: 4 µs or more
Disable watchdog timer tvs3: 5 µs or more
tFRS: When Vcc ≥ 4.5 V, 50 µs or more
Select program-verify mode When Vcc < 4.5 V, 100 µs or more
(PV bit = 1 in FLMCR)
Wait for at least tFRS before
Wait (tvs1) µ *4
reading flash memory after the
VppE bit is cleared.
N: 6 (set N so that total programming
Verify *3 NG time does not exceed 1 ms)
(read memory)
OK (programming completed) n=n+1
n ≤ N ? *4
NO (programming error)
YES (reprogram)
Clear PV bit
Clear PV bit
4
Wait (tVS1) µs *
Clear target block (EBR)
Clear VppE bit
Wait (tFRS) µs *4
Set return code

0: Normal, 1: Programming error (n > N)
End
Figure 19-8 Programming Flowchart

Rev. 3.0, 02/99, page 537 of 904
Sample Program for Programming One Byte: This program uses the following registers:
R0: Specifies program data as byte data./Return value (0: Normal, 1: Write error).
R1: Used to specify the program target block.
R2: Used for program address page specification.
R3: Used for program address specification.
After the values of R0 (program data), R1 (program target block), R2 (program address page), and
R3 (program address) have been specified, arbitrary data can be programmed at an arbitrary
address by calling the fwrite subroutine.
The wait time due to software looping after bit setting depends on the operating frequency. The
relevant operating frequency can be specified by setting the MHZ symbol value. In this program
the wait time (number of loops) is calculated on the assumption that the scb/f instruction is located
at an even address in two-state access space (on-chip RAM).
The read setup time (tFRS) after clearing the VPPE bit is the value for the case where VCC ≥ 4.5 V.
See section 22.2.4, "Flash Memory Characteristics," for the wait time after setting a bit in the flash
memory control register (FLMCR).
0001:; ***************************************************************************
0002:; * fwrite, src (Ver. 0.10)
0003:; * Sample program for programming one byte of H8/539F flash memory
0004:; *
0005:; ***************************************************************************
0006:;
0007:;
0008: MHZ .equ d'10 ; Depends on operating frequency (10 MHz)
0009: RAMSTR .equ H'EE80 ; Program transfer destination RAM address
0010:; Register addresses
0011: FLMCR .equ H'FEE0 ; Flash memory control register
0012: EBR .equ H'FEE2 ; Target block specification register
0013: TCSR .equ H'FF10 ; Timer control/status register
0014: WCR .equ H'FF14 ; Wait control register
0015:;
0016:;
0017: align H'2
0018: main: equ $
0019: ldc.b #H'00:8,tp ; Stack page register setting
Rev. 3.0, 02/99, page 538 of 904

0020: mov.w #H'FE80,sp ; Stack pointer setting
0021: ldc.b #H'00:8,ep ; Page register initialization
0022: ldc.b #H'00:8,dp ; Page register initialization
0023: ;
0024: mov.w #prog_start,R0; Transfer start address
0025: mov.w #prog_stop,R1; Transfer end address
0026: bsr tensou:16 ; Program transfer to RAM
0027:;
0028: ; Argument setting and subroutine call
0029: jsr @RAMSTR ; JMP SUB to RAM area program (prog_start)
0030: ; (All-mat constant write example)
0031:;
0032: main_end: ; End of write
0033: bra main_end
0034:;
0035:;
0036:; ***************************************************************************
0037:; * tensou SUB
0038:; * Copy RAM execution program to RAM
0039:; ***************************************************************************
0040: .align H'2
0041: tensou:equ $
0042: ;Arguments R0 Transfer start address
0043: ; R1 Transfer end address
0044: stm (R2-R3), @-sp ; save uesd registers
0045: ; R2 Transfer destination RAM address
0046: ; R3 Transfer data work
0047: mov:i #RAMSTR,R2 ; Transfer destination address setting
0048:tensou01:
0049:; mov.w @R0+,R3 ; ROM PROG DATA → R3
0050: mov.w R3,@R2+ ; R3 → RAM WRITE
0051: cmp.w R1,R0 ; R1:END R0:INCREASED ADDR.
0052: blt tensou01 ; R0=R1 → NEXT INSTRUCTION.
0053: ldm @spt,(R2-R3) ; Restore used registers
0054: rts ; Subroutine return
0055:;
0056:;
Rev. 3.0, 02/99, page 539 of 904

0057:; ***************************************************************************
0058:; ** Start of program for transfer to RAM **
0059:; ***************************************************************************
0060: .align H'2
0061:prog_start:.equ $ ;start of program for transfer to RAM
0062: ;
0063: ;
0064: ;
0065:;
0066:;
0067:; ***************************************************************************
0068:; all0_write SUB *
0069:; Flash memory ALL H'00 write *
0070:; ***************************************************************************
0071: .align H'2
0072:all0_write: .equ $
0073: ; Arguments R0 Return code 0: Normal
0074: ; 1: Write error
0075: stm(R1-R5),@-sp ; Save used registers
0076: ; R0 Program data
0077: ; R1 Target block specification
0078: ; R2 Program address page specification
0079: ; R3 Program address specification
0080: ; Wait loop counts
0081:;
0082: clr.b@WCR ; No wait state insertion
0083: ldc.w #H'0700,SR ; Disable interrupts during programming/erasing
0084:;
0085: mov.w #(d'5*MHZ/d'8),R3
0086: ; Set VPPE wait loop counter
0087: mov.b #H'40,@FLMCR ; Set VPPE bit
0088:all0_w01:
0089:scb/f R3,all0_w01 ; VPPE wait (5 µs or more)
0090:;
0092: mov.w #H'FFFF,R1 ; Target block specification
0093: mov.b #H'01,R2 ; Program address page specification
Rev. 3.0, 02/99, page 540 of 904

0094:all0_w02:
0095: mov.w #H'0000,R3 ; Program address
0096:all0_w03:
0097: mov.b #H'00,R0 ; Program data
0098: bsr fwrite ; 1-byte program
0099: cmp.w #H'0000,R0 ; Return code check
0100: bne all0_w05 ; If write error, end
0101:;
0102: cmp.w #H'FFFF,R3 ; Last address of page?
0103: beq all0_w04 ; If last address, next page
0104: add.w #H'01,R3 ; Increment program address
0105: bra allo_w03 ;
0106:all0_w04:
0107: cmp.t #H'02,R2 ; Last page?
0108: beg all0_w05 ; If last page, end
0109: add.b #H'01,R2: ; Page address + 1
0110: bra all0_w02 ;
0111:all0_w05:
0112: mov.w #(d'50*MHZ/d'8), R3
0113: ; Set VPPE clear wait counter
0114: clr.b @FLMCR ; Clear VPPE bit
0115:all0_w06:
0116: scb/f R3,all0_w06 ; VPPE clear wait (50 µs or more)
0117:;
0118: ldm @sp+,(R1-R5) ; Restore used registers
0120:all0_write_end: .equ $
0121:;
0122:;
0123:; ***************************************************************************
0124:; * fwrite SUB *
0125:; * To program one byte of flash memory (SUB) *
0126:; ***************************************************************************
0127: .align H'2
0128:fwrite: .equ $
0129: ; Arguments R0 Program data/return code
0130: ; Return code 0: Normal
Rev. 3.0, 02/99, page 541 of 904

0131: ; 1: Write error
0132: ;R1 Target block
0133: ;R2 Program address page
0134: ;R3 Program address
0136: ; R2 Decision count counter
0137: ; R3 Wait loop counts
0138: ; R4 Program address
0139: ; R5 P time loop count
0140: stc.b ep,@-sp ; Save used page registers
0141:;
0142: ldc.b R2,ep ; Program address page
0143: mov.w R3,R4 ; Program address
0144:;
0145: mov.w R1,@EBR ; Set target block in EBR1, EBR2
0146:;
0147: mov.w #H'0001,R2 ; Decision count counter = 1
0148: mov.w #((d'16*MHZ-d'4)/d'8),R5
0149:; ; P time loop count initial value (approx. 16 µs)
0150: mov.b R0,@R4 ; Dummy write (latch)
0151:fwrite 01:
0152: mov.w R5,R3 ; Set loop counter
0153: add.w R5,R5 ; P bit wait × 2
0154: mov.w #H'A57A,@TCSR; Set watchdog timer
0155:; nop ; Adjust so that scb/f wait is at even address
0156: ; If odd, insert NOP
0157: mov.b #H'41,@FLMCR ; Set P bit
0158: ; Adjust so that scb/f wait is at even address
0159:fwrite 02:
0160: scb/f R3,fwrite 02 ; P wait (initially 16 µs) programming time wait
0161: mov.b #H'40,@FLMCR ; Clear P bit
0162: mov.w #H'A500,@TCSR; Stop watchdog timer
0163:;
0164: mov.w #(d'4*MHZ/d'8)R3
0165: ; Set PV wait loop counter
0166: mov.b #H'44,@FLMCR ; Set PV bit
0167:fwrite 03:
Rev. 3.0, 02/99, page 542 of 904

0168: scb/f R3,fwrite 03 ; PV wait (4 µs or more)
0169: cmp.b @R4,R0 ; Compare with programmed data
0170: beg fwrite 05 ; Decision: If the same go to end processing
0171:;
0172: add.w #H'01,R2 ; R2 = R2 + 1
0173: cmp.w #H'0006,R2 ; Count decision (6 times)
0174: bhi fwrite 05 ; If count > 6, end
0175: mov.w #(d'4*MHZ/d'8),R3
0176: ; Set post-PV-clearing wait counter
0177: mov.b #H'40,@FLMCR ; Clear PV bit
0178:fwrite 04:
0179: scb/f R3,fwrite 04 ; Post-PV-clearing wait (4 µs or more)
0180: bra fwrite 01
0181:;
0182:fwrite 05:
0183: mov.w #(d'4*MHZ/d'8),R3
0184: ; Set post-PV-clearing wait counter
0185: mov.b #H'40,@FLMCR ; Clear PV bit
0186:fwrite 06:
0187: sob/f R3,fwrite 06 ; Post-PV-clearing wait (4 µs or more)
0188: clr.w @EBR ; Clear target block
0189:;
0190: clr.w R0 ; Set return value (R0) = OK
0191: cmp.w #H'0006,R2 ; Count decision
0192: bls fwrite 07 ; No count overflow
0193: mov.w #H'01, R0 ; Set return value (R0) = NG
0194:fwrite 07:
0195:;
0196: ldc.b @sp+,ep ; Restore used page register
0199:;
0200:; ***************************************************************************
0201:;
0202: ;
0203: ;
0204: ;
Rev. 3.0, 02/99, page 543 of 904

0205:prog_stop: .equ $ ;End of program for transfer to RAM
0206:;
0207:;
0208: .end
0209:
Notes: 1. The program code shown here illustrates an example of how to program or erase the
on-chip flash memory. It is not compatible with all chip models, so it cannot be used
unmodified. It is only intended as an example for program developers.
2. Always confirm program execution before actually using program code in an
application.
3. This program code may be changed without notice due to improvements, etc.
19.4.4 Erase Mode
To erase the flash memory, follow the erasing algorithm shown in figure 19-9. This erasing
algorithm can erase data without subjecting the device to voltage stress or impairing the reliability
of programmed data.
To erase flash memory, before starting to erase, first place all memory data in all blocks to be
erased in the programmed state (program all memory data to H'00). If all memory data is not in
the programmed state, follow the sequence described later to program the memory data to H'00.
Select the flash memory areas to be erased with erase block registers 1 and 2 (EBR1 and EBR2).
Next set the E bit in FLMCR, selecting erase mode. The erase time is the time during which the E
bit is set. To prevent overerasing, divide the first three times into 6.25 ms, 12.5 ms, and 25 ms
intervals, followed by 50 ms intervals repeated a maximum of 599 times, so that the total erase
time does not exceed 30s. Overerasing, due to program runaway for example, can give memory
cells a negative threshold voltage and cause them to operate incorrectly. Before selecting erase
mode, set up the watchdog timer so as to prevent overerasing.
19.4.5 Erase-Verify Mode
In program-verify mode, after data has been erased, it is read to check that it has been erased
correctly. After the erase time has elapsed, exit erase mode (clear the E bit to 0) and select erase-
verify mode (set the EV bit to 1). Before reading data in erase-verify mode, write H'FF dummy
data to the address to be read. As a result of this dummy write, the erase-verify voltage is applied
to the memory cells at the latched address. When the flash memory is read in this state, the data at
the latched address is read. After selecting erase-verify mode, wait at least 4 µs, plus at least 2 µs
for the dummy write to each address, before reading. If the read data has been successfully erased,
perform the dummy write and erase-verify for the next address. If the read data has not been
erased, select erase mode again and repeat the same erase and erase-verify sequence through the
last address, until all memory data has been erased H'FF. Do not repeat the erase and erase-verify
sequence more than 602 times, however.
Rev. 3.0, 02/99, page 544 of 904
19.4.6 Erasing Flowchart and Sample Program
Flowchart for Erasing One Block (ferase)
Start Notes: 1. Program all addresses to be erased by

following the prewrite flowchart.
2. x: Set to 6.25 ms, 12.5 ms, and 25
Set VppE bit ms the first three times, then fix at 50
ms from the fourth time onward.
Wait (tVPS) µs * 2 N: N = 602
Set N so that total erase time dose not
Mask specification of blocks that exceed 30 s.
cannot be erased in mode 2 * 3 tVPS: 5 µs or more
tFRS: When Vcc ≥ 4.5 V, 50 µs or more
Set erase block registers When Vcc < 4.5 V, 100 µs or more
(set 1 for erase target blocks)
Wait for at least tFRS before reading
prewrt * 1
flash memory after the VppE bit is
cleared.
Write 0 to block before erase target blocks
(prewrite) 3. In mode 2, do not specify a block which is
not in page 0 in the erase block registers.
4. See figure 19-10 (1), Multiple Block Prewrite
NG Flowchart.
Prewrite OK?
5. See figure 19-12, Erase Block Erase
Flowchart.
OK 6. See figure 19-13, Erase-Verify Flowchart.
n =1
Calculate time for one erase * 2
erase * 5
Erase target blocks
erasevf * 6
Erase-verify
NO
All erase target blocks erased?
(EBR1, EBR2 = 0?)
n=n+1
YES
Yes (Re-erase)
n ≤ N ?* 2
No (Erase error)
Return code setting

0: Normal, 1: Prewrite error, 2: Erase error
Clear erase terget blocks (EBR)
Claer VppE bit
Wait (tFRS) µs*2
End
Figure 19-9 Multiple-Block Erasing Flowchart
Rev. 3.0, 02/99, page 545 of 904

Flowchart for Prewriting Multiple Blocks (prewrt)
Start
Calculate block table start address
NO
Erase target block ?
YES
Set start address of erase target block to
prewrite address
prebyt
One-byte prewrite
NO
One-byte prewrite OK?
YES
Prewrite address + 1
NO
Last address of block?
YES
Block table + 1
NO
End of all blocks ?
YES
Set return code

0: Normal, 1: Prewrite error (n>N)
End
Figure 19-10 Multiple-Block Prewrite Flowchart
Rev. 3.0, 02/99, page 546 of 904

Flowchart for Prewriting One Byte (prebyt)
Start
n=1
Read flash memory data and write Notes: 1. Write the data with a byte transfer
inverted data * 1 instruction.
(Write one's complement data to latch 2. Set the timer overflow interval (CKS2 =
address and data) 0, CKS1 = 1, CKS0 = 0).
3. In prewrite-verify mode, VppE = 1, P = E
= PV = EV = 0, and 12 V is applied to
Enable watchdog timer * 2 the Vpp pin. Read the memory data with
a byte transfer instruction.
4. x: x=initial value x 2n-1 (n = 1,2,3,4,5,6)
Select program mode (Set an initial value of 10 to 15.8 µs)
(set P bit in FLMCR to 1) tVS1: 4 µs or more
N: 6 (Set N so that total programming
time does not exceed 1 ms)
Wait (X) µs * 4
Clear P bit (exit program mode)
Disable watchdog timer
Wait (tvs1) µs * 4
Prewrite verify * 3 NG
(read data = H'00?)
OK (prewrite completed)
n = n+ 1
No (programming error)
n ≤ N ? *4
YES (reprogram)
Set return code
0: Normal, 1: Programming error (n>N)
End
Figure 19-11 One Byte-Block Prewrite Flowchart
Rev. 3.0, 02/99, page 547 of 904

Flowchart for Erasing Erase Target Block (erase)
Start Notes: 1. Refer to table 19-19 and set the timer

overflow interval accordingly.
2. X: Set to 6.25 ms, 12.5 ms, and 25 ms the
Enable watchdog timer *1 first three times, then fix at 50 ms from
the fourth time onward.
N: N = 602
Select erase mode
(Set E bit in FLMCR to 1)
Wait (X) ms *2
Clear E bit (terminate erase)
Disable watchdog timer
End
Figure 19-12 Erase Target Block Erase Flowchart
Rev. 3.0, 02/99, page 548 of 904

Erase-Verify Flowchart (erasevf)
Start
Select erase-verify mode

(Set EV bit in FLMCR to 1) Notes: 1. tVS1: 4 µs or more
tVS2: 2 µs or more
2. For the erase-verity dummy write, write
Wait (tvs1) µs *1
H'FF with a byte trasfer instruction.
3. Read the data to be verified with a byte
Calculate block table start address transfer instruction.
4. When erasing two or more blocks, clear
the bits of erased blocks in the erase
block register, so that only unerased
Set start address of erase target block blocks will be erased again.
as erase-verify address
Dummy write to verify address *2

(Flash memory latches address)
Waite (tvs2) µs *1
Verify *3
(Read memory)
Address + 1→ address
NO
Last address of block ?
YES
(Erasing of one block completed)
Clear EBR bit of erased block *4
Block table + 1
NO (Next block)
End of all blocks ?
Clear EV bit
End
Figure 19-13 Multiple-BlockPrewrite Flowchart
Rev. 3.0, 02/99, page 549 of 904

Loop Counter Values in Programs and Watchdog Timer Overflow Settings: A wait time is
necessary after a bit is set or cleared in the flash memory control register (FLMCR). In the
program examples, wait times are provided by means of software loops. The software loop
counter value depends on the operating frequency, and whether the scb/f instruction is located at
an even address and in two-state access space, and whether wait state insertion is disabled. In these
program examples, the calculation assumes an even address, two-state access space, and no wait
state insertion. Examples of counter values for typical frequencies are shown in table 19-9.
The value set in TCSR to provide the watchdog timer overflow interval setting when erase mode
is selected depends on the operating frequency. TCSR set values for different operating
frequencies are shown in table 19-10.
As software loops are used, there is intrinsic error in the wait times, and the calculated value and
actual time may not be the same. Therefore, initial values should be set so that the total
programming time does not exceed 1 ms, and the total erase time does not exceed 30 s.
The set value for the watchdog timer is calculated on the basis of the number of instructions
including the programming time and erase time from the time the watchdog timer is started until it
stops. Therefore, no other instructions should be added between starting and stopping of the
watchdog timer in these program examples.
The loop counter value for each frequency is calculated as shown below.
Formulas: Formulas for calculating loop counter value in program
(1) Program time (P bit set) and calculation formula: When the scb/f instruction is in two-state
access space, and the branch destination is at an even address, the processing time is 4 states when
the register value = 0 (no branch) and 8 states when the register value ≥ 1 (branch). Thus the
calculation formula, with truncation of the decimal part, is as follows.
Loop counter value = ((Wait time (µs) × operating frequency (MHz)) states - 4 states)/8 states
(2) Erase time (E bit set) calculation formula: For the same access space as in (1) above, the
calculation formula is as follows.
Loop counter value = ((Wait time (µs) × operating frequency (MHz)) states - 14 states)/18 states.
(3) Wait time (after PV setting: t vs1), (after EV setting: tvs1), (after latching: tvs2) (after VPPE
clearing: tvps) calculation formula: With the same number of states as in (1) above, the
calculation formula, with rounding of the decimal part, is as follows.
Loop counter value = ((Wait time (µs) × operating frequency (MHz)) states-4 + 4 states)/8 states
Rev. 3.0, 02/99, page 550 of 904

Table 19-9 Example of Sample Software Loop Counter Values for Typical Operating
Frequencies
Operating Frequency
f = 16 MHz f = 10 MHz f = 8 MHz f = 2 MHz
Counter Counter Counter Counter
Set Value Set Value Set Value Set Value
Program time 15.8 µs H'001E H'0013 H'000F H'0003
(initial set value)
tVS1 4 µs H'0008 H'0005 H'0004 H'0001
tVS2 2 µs H'0004 H'0002 H'0002 H'0001
tVPS 5 µs H'000A H'0006 H'0005 H'0001
Erase time 6.25ms H'15B2 H'0D8F H'0AD9 H'02B5
(initial set value)
Table 19-10 Watchdog Timer Overflow Interval Settings when Erase Mode is set
Variable
Operating Frequency [MHz] TCSR Set Value
10 MHz ≤ frequency ≤ 16 MHz H'A57F
2 MHz ≤ frequency < 10 MHz H'A57E
Rev. 3.0, 02/99, page 551 of 904

Sample Multiple-Block Erase Program: This program uses the following registers.
R0: Specifies blocks to be erased (set as explained below)

/Return value (0: Normal, 1: Prewrite error, 2: Erase error)
R1: -/NG block (0: Normal, Other: NG block)
After a value is specified in R0 (erase block), an arbitrary block can be erased by calling the ferase
subroutine. After the ferase subroutine ends, the return value is returned in R0 and an NG block in
R1.
The wait time due to software looping after bit setting depends on the operating frequency. The
relevant operating frequency can be specified by setting the MHZ symbol value. In this program
the wait time (number of loops) is calculated on the assumption that the scb/f instruction is located
at an even address in two-state access space (on-chip RAM). The read setup time (tFRS) after VPPE
bit clearing used here is for the case where VCC ≥ 4.5 V. See section 22.2.4, Flash Memory
Characteristics, for the wait time after a bit is set in the flash memory control register (FLMCR).
Each bit in R0 corresponds to a bit in the erase block registers (EBR1, EBR2). A bit map of R0
and an example of the method of calling the subroutine are shown below.
A bit map of R0 and an example setting for erasing specific blocks are shown next.
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R0 LB7 LB6 LB5 LB4 LB3 LB2 LB1 LB0 SB7 SB6 SB5 SB4 SB3 SB2 SB1 SB0
Corresponds to EBR1 Corresponds to EBR2
Example: to erase blocks LB2, SB7, and SB0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R0 LB7 LB6 LB5 LB4 LB3 LB2 LB1 LB0 SB7 SB6 SB5 SB4 SB3 SB2 SB1 SB0
Corresponds to EBR1 Corresponds to EBR2
Setting 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 1
Ferase subroutine calling is performed as shown for the all_erase subroutine in list 1.
Rev. 3.0, 02/99, page 552 of 904

List 1: Sample Block Erase Program
0001:;****************************************************************************
0002:;* ferase, src (Ver. 0.13) *
0003:;* Sample program for H8/539F flash memory block erasing *
0004:;* *
0005:;****************************************************************************
0006:;
0007:;
0008:MHZ .equ d'16 ; Depends on operating frequency (16 MHz)
0009:RAMSTR .equ H'EE80 ; Program transfer destination RAM address
0011:FLMCR .equ H'FEE0 ; Flash memory control register
0012:EBR .equ H'FEE2 ; Target block specification register
0013:TCSR .equ H'FE10 ; Timer control/status register
0014:WCR .equ H'FE14 ; Wait control register
0015:MDCR .equ H'FE19 ; Mode control register
0016:;
0017:;
0018: .align H'2
0019:main:.equ $
0020: ldc.b #H'00:B,tp ; Stack page register setting
0022: ldc.b #H'00:8,ep ; Page register initialization
0023: ldc.b #H'00:8,dp ; Page register initialization
0024:;
0025: mov.w #prog_start,R0 ; Transfer start address
0026: mov.w #prog_stop,R1 ; Transfer end address
0028:;
0031: ; (All-mat erase example)
0032:;
0033:main_end: ; End of erase
0034: bra main_end
0035:;
0036:;
Rev. 3.0, 02/99, page 553 of 904

0037:;****************************************************************************
0038:;* tensou SUB *
0039:;* Copy RAM execution program to RAM *
0040:;****************************************************************************
0041: .align H'2
0042:tensou: .equ $
0043: ; Arguments R0 Transfer start address
0048: mov:i #RAMSTR ; Transfer destination address setting
0049:tensou 01:
0050: mov.w @R0+,R3 ; RAM PROG DATA → R3
0051: mov.w R3,@R2+ ; R3 → RAM WRITE
0053: blt tensou 01 ; R0=R1 → NEXT INSTRUCTION.
0056:;
0057:;
0058:;****************************************************************************
0059:;** Start of program for transfer to RAM **
0060:;****************************************************************************
0061: .align H'2
0062:prog_start..equ $ ; Start of program for transfer to RAM
0063: ;
0064: ;
0065: ;
0066:;
0067:;
0068:;****************************************************************************
0069:;** all_erase SUB *
0070:; Flash memory all-mat erase *
0071:;****************************************************************************
0072: .align H'2
0073:all_erase:.equ $
Rev. 3.0, 02/99, page 554 of 904

0074: ; Arguments
0075: ; R0-/Return code 0: Normal
0076: ; 1: Prewrite error
0077: ; 2: Erase error
0078: ; R1-/NG target block
0079:stm(R2-R5),@-sp ; Save used registers
0080: ; R0 Erase-verify target block
0082:;
0083: clr.b @WCR ; No wait state insertion
0084: ldc.w #H'0700,sr ; Disable interrupts during programming/erasing
0085:;
0086: mov.w #(d'5*MHZ/d'8),R2
0087: ; Set VPPE wait loop counter
0088: mov.b #H'40,@FLMCR ; Set VPPE bit
0089:all_e01:
0090: scb/f R2,all_e01 ; VPPE wait (5 µs or more)
0091:
0092: mov.w #H'FFFF,@EBR ; Erase target block specification
0093: bsr erasevf:16 ; Erase-verify
0094: mov.w @EBR,R0 ;
0095: tst.w R0 ; Unerased block check
0096: beq all_e02 ; If there is unerased block,
0098: mov.w @EBR,R0 ; Specify unerased block as target block
0099: bsr ferase ; Erase block
0100: ; Return R0 Return code (0, 1, 2)
0101: ; R1 NG target block
0102:all_e02
0103: mov.w #(d'50*MHZ/d'8),R2
0104: ; Set VPPE clear wait counter
0105: clr.b@FLMCR ; Clear VPPE bit
0106:all_e03
0107: scb/f R2,all_e03 ; VPPE clear wait (50 µs or more)
0108:
Rev. 3.0, 02/99, page 555 of 904

0111:all_erase_end: .equ $
0112:;
0113:;
0114:;****************************************************************************
0115:;* ferase SUB
0116:;* Flash memory block erase (SUB)
0117:;****************************************************************************
0118: .align H'2
0119:ferase:.equ $
0120: ; Arguments R0 Erase target block/return code
0124: ; R1 - / NG target block
0126: ; R0 E time loop count (lower)
0127: ; R1 E time loop count (upper)
0128: ; R2 Erase loop counter
0129: stc.b ep,@-sp ; Save used page register
0130:;
0131: cmp.b #H'c2,@MDCR ; Mode check
0132: bne ferase 01 ; If mode 2,
0133: and.w #H'80FF,R0 ; mask target blocks except page 0
0134:ferase 01:
0135: mov.w R0,@EBR ; Set target block in EBR1, EBR2
0136:;
0137: bsr prewrt:16 ; Target block prewrite subroutine
0138: tst.w R0 ; Return code check
0139: bne ferase 05
0140:;
0141: mov.w #((d'6250*MHZ-d'14)/d'18),R0
0142: ; E time loop count initial value (6.25 ms)
0143: clr.w R1 ; E time loop count (upper)
0144: mov.w #H'0001,R2
0145:ferase 02:
0146: bsr erase:16 ; Erase subroutine
0147: bsr erasevf:16 ; Erase-verify subroutine
Rev. 3.0, 02/99, page 556 of 904

0148:;
0149: tst.w @EBR
0150: beq ferase 04 ; If @EBR = 0, end
0151: add.w #H'01,R2
0152:;
0153: cmp.w #H'04,R2 ; Set loop counter
0154: bhs ferase 03
0155: add.w R0,R0 ; E time loop count (lower) × 2
0156: addx.w R1,R1 ; E time loop count (upper) × 2
0157:ferase 03:
0158:;
0159: cmp.w #d'602,R2
0160: bls ferase 02 ; If erase count > 602, NG end
0161: ; If erase count is NG (>602),
0162: mov.w #H'0002,R0 ; return code = erase error
0163: mov.w @EBR,R1 ; R1 = NG block
0164: bra ferase 05
0165:ferase 04:
0166: clr.w R0 ; Return code = OK
0167: clr.w R1 ; No NG block
0168:ferase 05
0169:;
0170: clr.w @EBR ; Clear target block
0174:;
0175:;
0176:;****************************************************************************
0177:; * prewrt SUB *
0178:; * Target block prewrite (SUB) *
0179:;****************************************************************************
0180: .align2
0181:prewrt: .equ $
0182: ; Arguments @EBR Erase target block
0183: ; R0 - /return code
Rev. 3.0, 02/99, page 557 of 904

0186: ; R1 - / NG target block
0188: ; R0 Argument - prewrite address page
0189: ; R1 Argument - prewrite address
0190: ; R2 Block table ADR
0191: ; R3 Target block bit number
0192: ; R4 Prewrite address
0193: clr.w R0
0194: mov.w #RAMSTR,R2 ; RAM program start address
0195: add.w #blockadr,R2 ; + block table start address
0196: sub.w #prog_start,R2 ; -> block table start address
0197: clr.w R3 ; Target block bit number
0198:prewrt 01:
0199: btst.w R3,@EBR
0200: beq prewrt 04 ; If R3 bit of @EBR= B'1, execute the following
0201: mov.w @R2,R4
0202: ldc.b R4,ep ; Set block start address page in ep
0203: mov.w @(H'02,R2),R4 ; Set block start address in R4
0204:prewrt 02:
0205: stc.b ep,R0 ; Set prewrite address page in argument R0
0206: mov.w R4,R1 ; Set prewrite address in argument R1
0207: bsr prebyt ; Prewrite (one byte) subroutine
0208:;
0209: tst.w R0
0210: bne prewrt 03 ; If prebyt return ≠ 0, end
0211: cmp.w @(H'04,R2),R4
0212: bhs prewrt 03 ; If R4 ≥ block end ADR, end
0213: add.w #H'01,R4 ; R4 = R4 + 1
0214: bra prewrt 02 ;
0215:prewrt 03:
0216:;
0217:prewrt 04:
0218: add.w #H'0006,R2 ; Block table next line address
0219:;
0220: tst.w R0
0221: bne prewrt 05 ; If prebyt return ≠ 0, end
Rev. 3.0, 02/99, page 558 of 904

0222: add.w #H'01,R3
0223: cmp.w #H'0F,R3
0224: bls prewrt 01 ; If target block bit number > 15, end
0225:prewrt 05:
0226: clr.w R1
0227: tst.w R0
0228: beq prewrt 06 ; If prebyt return ≠ 0, execute the following
0229: bset.w R3,R1 ; Set 1 in R3 bit of R1
0230:prewrt 06:
0231:;
0234:;
0235:;
0236:;****************************************************************************
0237:; * prebyt SUB *
0238:; * One-byte prewrite (SUB) *
0239:;****************************************************************************
0240: .align 2
0241:prebyt:.equ $
0242: ; Arguments R0 Prewrite address page/return code
0246: stm (R2-R5),@-sp ; Save used registers
0247: ; R2 Decision count counter
0250: ; R5 P time loop count
0252:;
0253: ldc.b R0,ep ; Prewrite address page
0254: mov.w R1,R4 ; Prewrite address
0255:;
0256: mov.w #H'0001,R2 ; Decision count counter = 1
0257: mov.w #((d'16*MHZ-d'4)/d'8),R5
0258: ; P time loop count initial value (approx. 16 µs)
Rev. 3.0, 02/99, page 559 of 904

0259:prebyt 01:
0260: clr.b @R4 ; Dummy write (H'00 compulsory latch)
0261: mov.w R5,R3 ; Set loop counter
0262: add.w R5,R5 ; P bit wait × 2
0263: mov.w #H'A57A,@TCSR ; Set watchdog timer
0264: nop ; Adjust so that scb/f wait is at even address
0265: mov.b #H'41,@FLMCR ; Set P bit
0266: ; Adjust so that scb/f wait is at even address
0267:prebyt 02:
0268: scb/f R3,prebyt 02 ; P wait (initially 16 µs) prewrite time wait
0269: mov.b #H'40,@FLMCR ; Reset P bit
0270: mov.w #H'A500,@TCSR ; Stop watchdog timer
0271:;
0272: mov.w #(d'4*MHZ/d'8),R3
0273: ; Set P reset wait loop counter
0274:prebyt 03:
0275: scb/f R3,prebyt 03 ; P bit reset wait (4 µs or more)
0276: tst.b@R4
0277: beq prebyt 04 ; Decision: If prewrite OK, go to end processing
0278: add.w #H'01,R2 ; R2 = R2 + 1
0279: cmp.w #H'0006,R2 ; Count decision (6 times)
0280: bhi prebyt 04 ; If count > 6, end
0281: bra prebyt 01
0282:;
0283:prebyt 04:
0284:;
0285: clr.w R0 ; Set return value (R0) = OK
0286: cmp.w #H'0006,R2 ; Count decision
0287: bls prebyt 05 ; If count overflow, execute the following
0288: mov.w #H'01,R0 ; Set return value (R0) = prewrite NG
0289:prebyt 05:
0290:;
0294:;
0295:;
Rev. 3.0, 02/99, page 560 of 904

0296:;****************************************************************************
0297:; * erase SUB *
0298:; * Flash memory erase (SUB) *
0299:;****************************************************************************
0300: .align 2
0301:erase: .equ $
0302: ; Arguments @EBR Erase target block
0303: ; R0 Erase wait loop count (lower)
0304: ; R1 Erase wait loop count (upper)
0306: ; R2 Erase wait loop count (lower)
0307: ; R3 Erase wait loop count (upper)
0308:;
0309: mov.w R0,R2 ; Erase wait loop count (lower)
0310: mov.w R1,R3 ; Erase wait loop count (upper)
0311: mov.w #H'A57F,@TCSR ; Set watchdog timer
0312: nop ; Adjust so that erase01: is at even address
0313: mov.b #H'42,@FLMCR ; Set E bit
0314: ; Adjust so that erase01: is at even address
0315:erase 01:
0316: nop ; nop instructions to increase wait time
0317: nop
0318: nop
0319: nop
0320: nop
0321: scb/f R2,erase 01 ; Erase time wait (initially 6.25 ms)
0322: scb/f R3,erase 01
0323: mov.b #H'40,@FLMCR ; Reset E bit
0324: mov.w #H'A500,@TCSR ; Stop watchdog timer
0325: mov.w #(d'4*MHZ/d'8),R2
0326: ; Set E reset wait loop counter
0327:erase 02:
0328: scb/f R2,erase 02 ; E bit reset wait (4 µs or more)
0329:;
0332:;
Rev. 3.0, 02/99, page 561 of 904

0333:;
0334:;****************************************************************************
0335:;* erasevf SUB *
0336:;* Erase-verify (SUB) *
0337:;****************************************************************************
0338: .align H'2
0339:erasevf:.equ $
0340: ; Arguments @EBR Erase target block/unerased block
0344: ; R4 Verify address
0347:;
0348: mov.w #(d'4*MHZ/d'8),R5
0349: ; Set EV wait loop counter
0350: mov.b #H'48,@FLMCR ; Set EV bit
0351:erasevf 01:
0352: scb/f R5,erasevf 01 ; EV wait (4 µs or more)
0353:;
0354: mov.w #RAMSTR,R2 ; RAM program start
0355: add.w #blockadr,R2 ; + block table relative address
0356: sub.w #prog_start,R2 ; -> block table start address
0357: clr.w R3 ; Target block bit number
0358:erasevf 02:
0359: btst.w R3,@ EBR
0360: beq erasevf 07 ; If R3 bit of @EBR= B'1, execute the following
0361: mov.w @R2,R4
0364:erasevf 03:
0365: mov.w #(d'2 *MHZ/d'8),R5
0366: ; Set post-latch wait loop counter
0367: mov.b #H'FF@R4 ; Dummy write (address latch)
0368:erasevf 04:
0369: scb/f R5,erasevf 04 ; Post-latch wait (2 µs or more)
Rev. 3.0, 02/99, page 562 of 904

0370:;
0371: cmp.b #H'FF,@R4 ; Verify
0372: bne erasevf 06 ; If target address is unerased, end
0373: cmp.w @(H'04,R2),R4
0374: bhs erasevf 05 ; If R4 >= block end ADR, end
0375: add.w #H'01,R4 ; R4 = R4 + 1
0376: bra erasevf 03 ;
0377:erasevf 05:
0378: bclr.w R3,@EBR ; Clear @EBR target block bit
0379:erasevf 06:
0380:;
0381:erasevf 07:
0383:
0384: add.w #H'01,R3
0385: cmp.b #H'0F,R3
0386: bls erasevf 02 ; If target block bit number > 15, end
0387:;
0388: mov.w #(d'4*MHZ/d'8),R5
0389: ; Set post-EV-clearing wait loop counter
0390: mov.b #H'40,@FLMCR ; Clear EV bit
0391:erasevf 08:
0392: scb/f R5,erasevf 08 ; Post-EV-clearing wait (4 µs or more)
0393:;
0397:;
0398:;
0399:;****************************************************************************
0400:; * blockadr DATA *
0401:; * Flash Memory Block Addresses *
0402:;****************************************************************************
0403: .align H'2
0404:blockadr: .equ $
0405: .data.w H'0001,H'3000,H'31FF ;SB0
0406: .data.w H'0001,H'3200,H'33FF ;SB1
Rev. 3.0, 02/99, page 563 of 904

0407: .data.w H'0001,H'3400,H'35FF ;SB2
0408: .data.w H'0001,H'3600,H'37FF ;SB3
0409: .data.w H'0001,H'3800,H'39FF ;SB4
0410: .data.w H'0001,H'3A00,H'3BFF ;SB5
0411: .data.w H'0001,H'3C00,H'3DFF ;SB6
0412: .data.w H'0001,H'3E00,H'3FFF ;SB7
0413:;
0414: .data.w H'0002,H'C000,H'FFFF ;LB0
0415: .data.w H'0002,H'8000,H'BFFF ;LB1
0416: .data.w H'0002,H'4000,H'7FFF ;LB2
0417: .data.w H'0002,H'0000,H'3FFF ;LB3
0418: .data.w H'0001,H'C000,H'FFFF ;LB4
0419: .data.w H'0001,H'8000,H'BFFF ;LB5
0420: .data.w H'0001,H'4000,H'7FFF ;LB6
0421: .data.w H'0001,H'0000,H'2FFF ;LB7
0422:;
0423:;****************************************************************************
0424:;
0425: ;
0426: ;
0427: ;
0428:prog_stop: .equ $ ; End of program for transfer to RAM
0429:;
0430:;
0431: .end
0432:
Notes: 1. The program code shown here illustrates an example of how to program or erase the
on-chip flash memory. It is not compatible with all chip models, so it cannot be used
unmodified. It is only intended as an example for program developers.
2. Always confirm program execution before actually using program code in an
application.
3. This program code may be changed without notice due to improvements, etc.
Rev. 3.0, 02/99, page 564 of 904

19.4.7 Prewrite-Verify Mode
Prewrite-verify mode is a verify mode used after zeroizing all bits to equalize their threshold
voltages before erasing them.
To program all bits, use the one-byte prewrite algorithm shown in figure 19-10. Use this
procedure to set all flash memory data to H'00 after programming. After the necessary
programming time has elapsed, exit program mode (by clearing the P bit to 0) and select prewrite-
verify mode (leave the P, E, PV, and EV bits all cleared to 0). In prewrite-verify mode, a
prewrite-verify voltage is applied to the memory cells at the read address. If the flash memory is
read in this state, the data at the read address will be read. After selecting prewrite-verify mode,
wait 4 µs before reading.
Note: For a sample prewriting program, see the prewrite subroutine in the sample erasing
program.
19.4.8 Protect Modes
Flash memory can be protected from programming and erasing by software or hardware methods.
These two protection modes are described below.
Software Protection: Prevents transitions to program mode and erase mode even if the P or E bit
is set in the flash memory control register (FLMCR). Details are as follows.
Function
1
Protection Description Program Erase Verify*
Block protect Individual blocks can be Disabled Disabled Enabled
program/erase-protected by the erase
block registers (EBR1 and EBR2). If
EBR1 and EBR2 are both set to H'00,
all blocks are program/erase-
protected.
3
Emulation When the OVLPE bit is set in the flash Disabled Disabled* Enabled
2
protect* memory emulation register (FMLER),
all blocks are protected from both
programming and erasing.
Notes: 1. Three modes: program-verify, erase-verify, and prewrite-verify.
2. Except in RAM areas overlapped onto flash memory.
3. All blocks are erase-disabled. It is not possible to specify individual blocks.
Hardware Protection: Suspends or disables the programming and erasing of flash memory, and
resets the flash memory control register (FLMCR) and erase block registers (EBR1 and EBR2).
The error-protect function permits the P and E bits to be set, but prevents transitions to program
mode and erase mode. Details of hardware protection are as follows.
Rev. 3.0, 02/99, page 565 of 904
Function
1
Protection Description Program Erase Verify*
2
Programing When VPP is not applied, FLMCR, Disabled Disabled* Disabled
voltage (VPP) EBR1, and EBR2 are initialized,
protect disabling programming and erasing.
To obtain this protection, VPP should
3
not exceed VCC.*
2
Reset and When a reset occurs (including a Disabled Disabled* Disabled
standby watchdog timer reset) or standby
protect mode is entered, FLMCR, EBR1, and
EBR2 are initialized, disabling
programming and erasing. Note that
5(6 input does not ensure a reset
unless the 5(6 pin is held low for at
least 20 ms at power-up (to enable the
oscillator to settle), or at least six
system clock cycles (6φ) during
4
operation.*
2
Error protect If an operational error is detected Disabled Disabled* Enabled
during programming or erasing of
flash memory (FLER = 1), the FLMCR,
EBR1, and EBR2 settings are
preserved, but programming or
erasing is aborted immediately. This
type of protection can be cleared only
by a reset by means of the 5(6 pin*
5
or hardware standby.
Notes: 1. Three modes: program-verify, erase-verify, and prewrite-verify.
2. All blocks are erase-disabled. It is not possible to specify individual blocks.
3. For details, see section 19.7, "Flash Memory Programming and Erasing Precautions."
4. See section 4.2.2, "Reset Sequence" and section 19.7, "Flash Memory Programming
and Erasing Precautions."
5. In the H8/538F, this includes the FLER bit clearing conditions and a watchdog timer
reset, but in the H8/539F only 5(6 pin reset input is applicable.
Error Protect: This protection mode is entered if one of the error conditions that set the FLER bit
1
in FLMSR* is detected while flash memory is being programmed or erased (while the P bit or E
3
bit is set in FLMCR* ). These conditions can occur if microcontroller operations do not follow the
programming or erasing algorithm. Error protect is a flash-memory state. It does not affect other
microcontroller operations.
In this state the settings of the flash memory control register (FLMCR) and erase block registers
2
(EBR1 and EBR2) are preserved,* but program mode or erase mode is terminated as soon as the
error is detected. While the FLER bit is set, it is not possible to enter program mode or erase
mode, even by setting the P bit or E bit in FLMCR again. The PV and EV bits in FLMCR remain
valid, however. Transitions to verify modes are possible in the error-protect state.
Rev. 3.0, 02/99, page 566 of 904
The error-protect state can be cleared only by a reset by means of the 5(6 pin or entry to
hardware standby mode.
Notes: 1. For the detailed conditions that set the FLER bit, see section 19.2.4, "RAM Control
Register (RAMCR)."
2. It is possible to write to the FLMCR, EBR1, and EBR2 registers. Note that a transition
to software standby mode in the error protect state initializes these registers.
2. Note that NMI input is disabled when the P bit or E bit is set. For details, see section
19.4.9, "NMI Input Masking."
Memory read
or verify mode Reset, or hardware standby,
or software standby
RD VF PR ER
FLER = 0
Reset or standby
Reset cleared and hardware (hardware protect)
standby cleared and software
P = 1 or E = 1 P = 0 and E = 0 standby cleared RD VF PR ER
Reset or INIT
hardware standby FLER = 0
Program mode Reset or

or erase mode hardware standby
Error occurs Reset or
RD VF PR ER hardware standby
FLER = 0 (software standby)
Error occurs Error-protect mode

(software standby)
RD: Memory read enabled Software RD VF PR ER
VF: Verify read enabled standby INIT
Error-protect mode
PR: Programming enabled FLER = 1
ER: Erase enabled RD VF PR ER
RD: Memory read disabled FLER = 1 Software standby
VF: Verify read disabled cleared
PR: Programming disabled
ER: Erase disabled
INIT: Initialized state of registers (FLMCR, EBR1, EBR2)
Figure 19-14 Flash Memory State Transitions

[In Modes 2, 4, and 7 (On-Chip ROM Enabled) when Programming Voltage (VPP) is
Applled]
The purpose of error-protect mode is to prevent overprogramming or overerasing damage to flash

memory by detecting abnormal conditions that occur if the programming or erasing algorithm is
not followed, or if a program crashes while the flash memory is being programmed or erased.
This protection function does not cover abnormal conditions other than the setting conditions of
the flash memory error bit (FLER), however. Also, if too much time elapses before the error-
protect state is reached, the flash memory may already have been damaged. This function
accordingly does not offer foolproof protection from damage to flash memory.
Rev. 3.0, 02/99, page 567 of 904

To prevent abnormal operations, when programming voltage (VPP) is applied, follow the
programming and erasing algorithms correctly, and keep microcontroller operations under
constant internal and external supervision, using the watchdog timer for example. If a transition to
error-protect mode occurs, the flash memory may contain incorrect data due to errors in
programming or erasing, or it may contain data that has been insufficiently programmed or erased
because of the suspension of these operations. Boot mode should be used to recover to a normal
state.
Overprogramming or overerasing may prevent normal start-up of boot mode.
19.4.9 NMI Input Masking
NMI input is disabled when flash memory is being programmed or erased (when the P or E bit is
set in FLMCR). NMI input is also disabled while the boot program is executing in boot mode,
1
until the branch to the on-chip RAM area takes place.* There are three reasons for this.
1. NMI input during programming or erasing might cause a violation of the programming or
erasing algorithm. Normal operation could not be assured.
2. In the NMI exception-handling sequence during programming or erasing, the vector would not
2
be read correctly.* The result might be a program runaway.
3. If NMI input occurred during boot program execution, the normal boot-mode sequence could
not be executed.
For these reasons, under certain conditions the H8/539F masks the normally nonmaskable NMI
input. This masking does not, however, ensure normal programming, erasing, and other
microcontroller operations. NMI requests should be disabled externally whenever VPP is applied.
NMI input is also disabled in the error-protect state and while the P or E bit remains set in the
flash memory control register (FLMCR) during emulation of flash memory using RAM.
Notes: 1. The disabled state lasts until the branch to the boot program area in on-chip RAM
(addresses H'EE80 to H'F37F) that takes place as soon as the transfer of the user
program is completed. After the branch to the RAM area, NMI input is enabled except
during programming or erasing. NMI interrupt requests must therefore be disabled
externally until the user program has completed initial programming (including the
vector table and the NMI interrupt-handling program).
2. In this case, the vector may not be read correctly for the following two reasons.
a. If flash memory is read while being programmed or erased (while the P or E bit
is set in FLMCR), correct read data will not be obtained. Undetermined values
are returned.
b. If the NMI entry in the vector table has not been programmed yet, NMI
exception handling will not be executed correctly.
Rev. 3.0, 02/99, page 568 of 904

19.5 Flash Memory Emulation by RAM
Erasing and programming flash memory takes time, which can make it difficult to tune parameters
and other data in real time. If necessary, real-time updates of flash memory can be emulated by
overlapping the small-block flash-memory area (H'3000 to H'3FFF) with part of the RAM. This
RAM reassignment is performed using bits 7, 3, 2, and 1 of the flash memory emulation register
(FLMER) and bits 2 to 0 of the RAM control register (RAMCR).
After a flash memory area has been overlapped by RAM, it can be accessed from two address
areas: the overlapped flash memory area (mapping RAM area), and the original RAM area (the
actual RAM area). Bits 7, 3, 2, and 1 of FLMER and bits 2 to 0 of RAMCR are valid in Modes 2,
4, and 7. In other modes, they always read 0 and the RAM area cannot be reassigned. When the
flash memory emulation function is used, bits 7 and 5 of RAMCR should both be set (RAME1 =
RAME2 = 1). Table 19-10 indicates how to assign a mapping RAM area. Bits 7 and 5 of
RAMCR should both be set (RAME1 = RAME2 = 1). Table 19-10 indicates how to assing a
mapping RAM area.
Flash Memory Emulation Register (FLMER)
Bit 7 6 5 4 3 2 1 0
OVLPE − − − A11E A10E A9E −
R/W R/W − − − R/W R/W R/W −
Rev. 3.0, 02/99, page 569 of 904


ROM Area Bit 7* Program
Bit 2* Bit 1* Bit 0*
(Mapping RAM Overlap /Erase
Area) OVLPE RAM2 RAM1 RAM0 Function Protection
− 0 0/1 0/1 0/1 Disabled Disabled
H'3000−H'31FF 1 0 0 0 Enabled Enabled
H'3A00−H'3BFF 1 1 0 1 Enabled Enabled
H'3C00−H'3DFF 1 1 1 0 Enabled Enabled
H'3E00−H'3FFF 1 1 1 1 Enabled Enabled
Note: * Bits 7 and 3 to 1 of the flash memory emulation register (FLMER) and bits 2 to 0 of the
RAM control register (RAMCR) are writeable in mode 2, 4, or 7. (In the H8/538F is was
necessary to apply 12 V to the program voltage pin VPP in order to perform RAM
emulation, but in the H8/539F RAM emulation is possible regardless of the VPP voltage.)
2

1 1 1 1 1
2 Bit 3* Bit 2* Bit 1* Bit 7* Bit 5*
ROM Area *
(Actual RAM Area) A11E A10E A9E RAME2 RAME1
H'F000−H'F1FF (512 bytes) 0 0 0 1 1
H'F200−H'F3FF (512 bytes) 0 0 1 1 1
H'F400−H'F5FF (512 bytes) 0 1 0 1 1
H'F600−H'F7FF (512 bytes) 0 1 1 1 1
H'F800−H'F9FF (512 bytes) 1 0 0 1 1
H'FA00−H'FBFF (512 bytes) 1 0 1 1 1
H'FC00−H'FDFF (512 bytes) 1 1 0 1 1
3
Use prohibited* 1 1 1 1 1
4 4 4
Use prohibited* 0/1 0/1 0/1 0/1* 0/1*
Rev. 3.0, 02/99, page 570 of 904

Notes: 1. Bits 7, 3, 2, and 1 of the flash memory emulation register (FLMER) and bits 2 to 0 of the
3. When A11E and A10E are both set to 1, A9E is always cleared to 0.
4. Use prohibited when RAME1 = 0 or RAME2 = 0. (Can be used when RAME1 =
RAME2 = 1.)
Example of Emulation of Real-Time Flash-Memory Updating
In the following example, RAM area H'F200 to H'F3FF is overlapped onto the SB5 flash memory
area (H'3A00 to H'3BFF).
H'3000 Procedure: 1. Overlap part of RAM (H'F200 to

H'F3FF) onto the area requiring
real-time updating (SB5). (Set
RAMCR bits 3 to 1 to 101, and
select the flash memory area to be
overlapped (SB5). Clear FLMER bit
Flash memory 7 to 0. Next, set FLMER bits 7, 3, 2,
space and 1 to 1001, and select the RAM
area to be used for overlapping.)
RAM overlapping starts when bit 7
(OVLPE) is set in FLMER.
2. FPerform real-time updates in the
Overlapped by RAM overlapping RAM.
3. After finalization of the update area,
H'3A00
* Mapping RAM area clear the RAM overlap (by clearing
Small-block
H'3BFF the OVLPE bit).
area (SB5)
H'3FFF 4. Program the data written in RAM
addresses H'F200 to H'F3FF into
H'EE80 the flash memory space.
H'F000 Note: * When part of RAM (H'F200 to H'F3FF)
H'F1FF is overlapped onto a small-block area in
H'F200 Actual RAM area flash memory, the overlapped flash
H'F3FF memory area cannot be accessed.
H'F400 Access is enabled when the overlap is
cleared.
On-chip RAM
area
H'FE7F
Figure 19-15 Example of RAM Overlapping
Rev. 3.0, 02/99, page 571 of 904

Notes on emulation RAM access
00000
*1
16 kbytes
Flash memory 03FFF
*2
04000
Mapping area *1
Page 0
0EE80
*2
0FE7F
Area used
RAM
in RAM emulation *2
ROM :03000 to 03FFF
RAM:0F000 to 0FDFF
10000
(16 kbytes) *1
Flash memory 13FFF
14000
Page 1 64 kbytes
(48 kbytes)
Flash memory
1FFFF
20000
Page 2 Flash memory 64 kbytes
2FFFF
Notes: 1. Area 00000 to 03FFF and 10000 to 13FFF are mapping areas. They can be accessed
from both page 0 and page 1.
2. When the RAM emulation function is used and RAM is overlapped onto a ROM area, the overlapped
page 0 RAM area is not mapped onto page 1. (RAM emulation can only be used in page 0.)
In this case, ROM contents be read by accessing page 1.
Figure 19-16 Notes on Emulation RAM Access
Rev. 3.0, 02/99, page 572 of 904

Notes on applying and releasing the programming voltage (VPP): As in on-board program
mode, care is required when applying and releasing VPP to prevent erroneous programming or
erasing. To prevent erroneous programming and erasing due to program runaway during VPP
application, in particular, the watchdog timer should be set when the P and E bits in the flash
memory control register (FLMCR) are set, even while the emulation function is being used.
For details, see section 19.7, "Flash Memory Programming and Erasing Precautions."
NMI input disabling conditions: When the emulation function is used, NMI input is disabled
when the P bit or E bit in the flash memory control register (FLMCR) is set, in the same way as
with normal programming and erasing.
The P and E bits are cleared by a reset (including a watchdog timer reset), in standby mode, and
when 12 V is not being applied to VPP.
Rev. 3.0, 02/99, page 573 of 904

19.6 PROM Mode
19.6.1 PROM Mode Setting
The on-chip flash memory of the H8/539F can be programmed and erased not only in the on-board
programming modes but also in PROM mode, using a general-purpose PROM programmer. In
PROM mode, make sure that the socket adapter listed in table 19-13 is used.
19.6.2 Socket Adapter and Memory Map
Programs can be written and verified by attaching a special 112-pin/32-pin socket adapter to the
general-purpose PROM programmer. Table 19-13 gives ordering information for the socket
adapter. Figure 19-18 shows a memory map in PROM mode.
Table 19-13 Socket Adapter
Microcontroller Package Socket Adapter

HD64F5389F 112-pin plastic QFP (FP-112) HS539FESH01H
MCU mode H8/539F PROM mode

H8/539F
H'00000 H'00000
On-chip ROM area
H'03FFF H'03FFF
H'10000
On-chip ROM area

H'13FFF
On-chip ROM area H'1FFFF
H'2FFFF
Figure 19-17 Memory Map in PROM Mode
Note: Use an appropriate tool when inserting the device in the IC socket and removing it. For
example, the tool shown in table 19-14 can be used.
Table 19-14 Example of Tool
Manufacturer Part Number

ENPLAS Corporation HP-100 (vacuum pen)
Rev. 3.0, 02/99, page 574 of 904

19.6.3 Operation in PROM Mode
The program/erase/verify specifications in PROM mode are the same as for the standard
HN28F101 flash memory. The H8/539F does not have a device recognition code, so the
programmer cannot read the device name automatically. Table 19-15 indicates how to select the
various operating modes in PROM mode. Table 19-15 indicates how to select the various
operating modes in PROM mode, and table 19-16 lists the commands used in PROM mode.
Table 19-15 Operating Mode Selection in PROM Mode
Pins
Mode VPP VCC &( 2( :( D7 to D0 A16 to A0
Read Read VCC VCC L L H Data output Address input
Output VCC VCC L H H High impedance
disable
Standby VCC VCC H X X High impedance
Command Read VPP VCC L L H Data output
write
Output VPP VCC L H H High impedance
disable
Standby VPP VCC H X X High impedance
Write VPP VCC L H L Data input
Legend
L: Low level
H: High level
VPP: VPP level
VCC: VCC level
X: Don't care
Rev. 3.0, 02/99, page 575 of 904

Table 19-16 PROM Mode Commands
1st Cycle 2nd Cycle

Command Cycles Mode Address Data Mode Address Data
Memory read 1 Write X H'00 Read RA Dout
Erase setup/erase 2 Write X H'20 Write X H'20
Erase-verify 2 Write EA H'A0 Read X EVD
Auto-erase setup/ 2 Write X H'30 Write X H'30
auto-erase
Program setup/ 2 Write X H'40 Write PA PD
program
Program-verify 2 Write X H'C0 Read X PVD
Reset 2 Write X H'FF Write X H'FF
PA: Program address
EA: Erase-verify address
RA: Read address
PD: Program data
PVD: Program-verify output data
EVD: Erase-verify output data
Rev. 3.0, 02/99, page 576 of 904

High-Speed, High-Reliability Programming: Unused areas of the H8/539F flash memory
contain H'FF data (initial value). The H8/539F flash memory uses a high-speed, high-reliability
programming procedure. This procedure provides enhanced programming speed without
subjecting the device to voltage stress and without sacrificing the reliability of programmed data.
Figure 19-19 shows the basic high-speed, high-reliability programming flowchart. Tables 19-17
and 19-18 list the electrical characteristics during programming.
Start
Set VPP = 12.0 V ±0.6 V
Address = 0
n=0
n+1→n
Program setup command
Program command
Wait (25 µs)
Program-verify command
Wait (6 µs)
Address + 1 → address
No Go
Verification?
Go No
n = 20?
No
Last address?
Yes
Yes
Set VPP = VCC
End Fail
Figure 19-18 High-Speed, High-Reliability Programming
Rev. 3.0, 02/99, page 577 of 904

High-Speed, High-Reliability Erasing: The H8/539F flash memory uses a high-speed, high-
reliability erasing procedure. This procedure provides enhanced erasing speed without subjecting
the device to voltage stress and without sacrificing data reliability . Figure 19-20 shows the basic
high-speed, high-reliability erasing flowchart. Tables 19-17 and 19-18 list the electrical
characteristics during programming.
Start
Program 0 data to all bits*
Address = 0
n=0
n+1→n
Erase setup/erase command
Wait (10 ms)
Erase-verify command
Wait (6 µs)
Address + 1 → address
No Go
Verification?
Go No
n = 3000?
No
Last address?
Yes
Yes
End Fail
Note: * Follow the high-speed, high-reliability programming flowchart in programming all bits.
Figure 19-19 High-Speed, High-Reliability Erasing

Rev. 3.0, 02/99, page 578 of 904
Table 19-17 DC Characteristics in PROM Mode
(Conditions: VCC = 5.0 V ±10%, VPP = 12.0 V ±0.6 V, VSS = 0 V, Ta = 25°C ±5°C)
Item Symbol Min Typ Max Unit Test Conditions

Input high O7 to O0, VIH 2.2  VCC + 0.3 V
voltage A16 to A0,
2(, &(, :(
Input low O7 to O0, VIL −0.3  0.8 V
voltage A16 to A0,
2(, 2(, :(
Output high O7 to O0 VOH 2.4   V IOH = −200 µA
voltage
Output low O7 to O0 VOL   0.45 V IOL = 1.6 mA
voltage
Input leakage O7 to O0, | ILI |   2 µA Vin = 0 to VCC V
current A16 to A0,
2(, 2(, :(
VCC current Read ICC  40 80 mA
Program ICC  40 80 mA
Erase ICC  40 80 mA
VPP current Read IPP   10 µA VPP = 5.0 V
 10 20 mA VPP = 12.6 V
Program IPP  20 40 mA
Erase IPP  20 40 mA
Note: For the absolute maximum ratings, see section 22.1, "Absolute Maximum Ratings."
Permanent damage to the chip may result if absolute maximum ratings are exceeded.
Set VPP below 13V taking into account the peak overshoot.
Rev. 3.0, 02/99, page 579 of 904

Table 19-18 AC Characteristics in PROM Mode
(Conditions: VCC = 5.0 V ±10%, VPP = 12.0 V ±0.6 V, VSS = 0 V, Ta = 25°C ±5°C)

Command write cycle tCWC 120   ns Figure 19-20
Address setup time tAS 0   ns Figure 19-21 *
Address hold time tAH 60   ns Figure 19-22
Data setup time tDS 50   ns
Data hold time tDH 10   ns
&( setup time tCES 0   ns
&( hold time tCEH 0   ns
VPP setup time tVPS 100   ns
VPP hold time tVPH 100   ns
:( programming pulse width tWEP 70   ns
:( programming pulse high tWEH 40   ns
time
2( setup time before command tOEWS 0   ns
write
2( setup time before verify tOERS 6   µs
Verify access time tVA   500 ns
2( setup time before status tOEPS 120   ns
polling
Status polling access time tSPA   120 ns
Program wait time tPPW 25   ns
Erase wait time tET 9  11 ms
Output disable time tDF 0  40 ns
Total auto-erase time tAET 0.5  30 s
Note: &(, &(, and :( should be high during transitions of VPP from 5 V to 12 V and from 12 V to
5 V.
* Input pulse level: 0.45 V to 2.4 V
Input rise time and fall time ≤ 10 ns
Timing reference levels: 0.8 V and 2.0 V for input; 0.8 V and 2.0 V for output
Rev. 3.0, 02/99, page 580 of 904

Auto-erase setup Auto-erase and status polling
VCC 5.0 V
12 V
VPP
5.0 V tVPS tVPH
Address
CE
tCEH tCES
OE tCES tCWC tOEPS

tOEWS tCES
tWEP tAET
tCEH
tWEP
WE tWEH
tDF
tDS tDH tSPA
tDH tDS
I/O7 Command Command

input input
Status polling
I/O0 to I/O6 Command Command

input input
Figure 19-20 Auto-Erase Timing
Program setup Program Program-verify

VCC 5.0 V
12 V
VPP
5.0 V tVPS
tVPH
Address Valid address
tAH
tAS
CE
tCEH
tCES
OE tCWC tCES
tCES tCEH
tWEP tPPW
tCEH tWEP tWEP tOERS
tOEWS
WE tWEH
tDH tDH tDH tVA tDF
tDS tDS tDS
I/O7 Command Data Command Valid data
input input input output
Command Data Command Valid data

I/O0 to I/O6 input input input output
Note: Program-verify data output values maybe intermediate between 1 and 0 if programming is insufficient.
Figure 19-21 High-Speed, High-Reliability Programming Timing
Rev. 3.0, 02/99, page 581 of 904

Erase setup Erase Erase-verify
VCC 5.0 V
12 V
VPP
5.0 V tVPS tVPH
Address Valid address

tAS tAH
CE
OE tOEWS tCEH tCES tCEH

tCWC
tCES tWEP tWEP tET tWEP tOERS
tCES
WE tCEH
tWEH tVA
tDH tDH tDH tDF
tDS tDS tDS
I/O0 to I/O7 Command Command Command Valid data

input input input output
Note: Erase-verify data output values maybe intermediate between 1 and 0 if erasing is insufficient.
Figure 19-22 Erase Timing
Rev. 3.0, 02/99, page 582 of 904

19.7 Flash Memory Programming and Erasing Precautions
The following points must be noted when using on-board programming mode, the emulation
function with RAM, and PROM mode.
(1) Program with the specified voltages and timing. The rated programming voltage (VPP) of
the flash memory is 12.0 V.
Applied voltages in excess of the rating can permanently damage the device. In particular, ensure
that the peak overshoot does not exceed the maximum rating of 13 V at the VPP and MD2 pins.
In PROM mode, VPP can be set to 12.0 V if HN28F101 is selected as the PROM programmer
setting. 12 V must not be applied to the S-mask model (single power source model), as this will
For information concerning the use of the S-mask model, see section 20, Flash Memory (H8/539F,
S-Mask Model, Single Power Source).
(2) Design a current margin into the programming voltage (VPP) power supply. Bypass
capacitors must be connected to the VPP pin. (See figures 19-24 and 19-28.) Ensure that VPP
remains within the range 12.0 ±0.6 V (11.4 V to 12.6 V) during programming and erasing.
Programming and erasing may become impossible outside this range. Connect decoupling
capacitors as close to the VPP pin as possible. When boot mode is used, also, decoupling
capacitors should be connected to the MD2 pin in the same way.
For details, see section 19.8, "Notes on Mounting Board DevelopmentHandling of VPP and
Mode MD2 Pins."
+5 V
Example of circuit when pull-up
resistor is inserted
Vpp
+12 V
RESO
H8/539F
(Duel Power System)
1.0 µF 0.01 µF
Note: This sample circuit cannot be used with the S-mask model (single power system).
Figure 19-23 Example of VPP Power Supply Circuit Design
Rev. 3.0, 02/99, page 583 of 904

(3) Precautions in applying and releasing the programming voltage (VPP) (See figures 19-22
to 19-24)
(a) Apply the programming voltage (VPP) after VCC has stabilized, and shut off VPP before VCC.
To avoid programming or erasing flash memory by mistake, VPP should only be applied and
released when the microcontroller is in a "stable operating condition" as described below.
Microcontroller stable operating condition
• The VCC voltage must be within the rated voltage range (VCC = 4.5 V to 5.5 V).
If the VCC voltage is turned on or off while VCC is not within its rated voltage range (VCC = 4.5
V to 5.5 V), since the microcontroller is unstable, the flash memory may be programmed or
erased by mistake. This can occur even if VCC = 0 V. Adequate power supply measures should
be taken, such as the insertion of a decoupling capacitor, to prevent fluctuation of the VCC
power supply when VPP is applied.
• Oscillation must have stabilized (following the elapse of the oscillation settling time).
When the VCC power is turned on, hold the 5(6 pin low for the duration of the oscillation
settling time (tOSC1 = 20 ms) before applying VPP. Do not apply or release VPP when
oscillation has been stopped or is unstable.
• In boot mode, VPP should be applied and released during a reset.
In boot mode, release a reset after the VPP and MD2 voltages have been stabilized at the
programming voltage level (12.0 V ±0.6 V).
For a reset during operation, apply or release VPP only after the 5(6 pin has been held low for
at least six system clock cycles (6φ).
• The VPPE, P, E, PV, and EV bits must be cleared in the flash memory control register
(FLMCR).
When applying or releasing VPP, make sure that the VPPE, P, E, PV, or EV bit is not set by
mistake.
• There must be no program runaway.
When VPP is applied, program execution must be supervised, e.g. by the watchdog timer.
These power-on and power-off timing requirements for VCC and VPP should also be satisfied in the
event of a power failure and in recovery from a power failure. If these requirements are not
satisfied, overprogramming or overerasing may occur due to program runaway, etc., which could
cause memory cells to malfunction.
(b) The VPP flag is set and cleared by a threshold decision on the voltage applied to the VPP
pin. The threshold level is approximately in the range from VCC +2 V to 11.4 V.
When this flag is set, it becomes possible to set the VPP enable bit (VPPE) in the flash memory
control register (FLMCR), even though the VPP voltage may not yet have settled in the
programming voltage range of 12.0 V ±0.6 V after VPP power is turned on. Do not actually
program or erase the flash memory until VPP has reached the programming voltage range.
Rev. 3.0, 02/99, page 584 of 904
The programming voltage range for programming and erasing flash memory is 12.0 V ±0.6 V
(11.4 V to 12.6 V). Programming and erasing cannot be performed correctly outside this range.
When not programming or erasing the flash memory, ensure that the VPP voltage does not exceed
the VCC voltage. This will prevent unintentional programming and erasing.
(c) After the programming voltage (VPP) is shut off, make sure that the flash memory read
setup time (tFRS)* has elapsed before reading the flash memory. When switching from boot
mode or user program mode to normal mode (VPP ≠ 12 V, MD ≠ 12 V), this setup time is required
as the interval before reading flash memory after clearing the VPPE bit. When switching from boot
mode to another mode, the mode programming setup time (tMDS) is required with respect to the
5(6 release timing.
Note: * The flash memory read setup time stipulates the period, from clearing of the VPPE bit until
flash memory is read (figure 22-21). Also, when using an external clock (EXTAL input),
after powering on and when returning from standby mode, the flash memory read setup
time must be allowed to elapse before flash memory is read (figure 22-22).
(d) Set the VPP enable bit (VPPE) before programming or erasing. Setting the VPPE bit makes it
possible to write to the flash memory control register (FLMCR) and the erase block registers
(EBR1 and EBR2).
Programming/
tVPS erasing possible tFRS
φ
tOSC1 min 0 µs
4.5 to 5.5 V
Vcc
12 ± 0.6 V
0 to Vcc V 0 to Vcc V
min 0 µs min 6φ
Vpp
12 ± 0.6 V
tMDS
MD2
min 0 µs
RES
VppE set
VppE cleared
VppE bit
Period during which flash memory access is prohibited
Period during which flash memory can be rewritten

(Execution of program in flash memory prohibited, and data reads other than verify operations prohibited)
Figure 19-24 Power-On and Power-Off Timing (Boot Mode)
Rev. 3.0, 02/99, page 585 of 904

Programming/
tVPS erasing possible tFRS
φ
tOSC1 min 0 µs
4.5 to 5.5 V
Vcc
12 ± 0.6 V
*1 *1
Vpp
MD2 to
MD0 tMDS
RES
VppE set
VppE cleared
VppE bit

Notes: 1. The level of the mode pins (MD2 to MD0) must be fixed from power-on to power-off by pulling the pins up or down.
Figure 19-25 Power-On and Power-Off Timing (User Program Mode)
Rev. 3.0, 02/99, page 586 of 904

Programming/ Programming/ Programming/ Programming/
erasing erasing erasing erasing
tVPS possible tFRS tVPS possible tFRS tVPS possible tFRS tVPS possible
φ
tOSC1
4.5 to 5.5 V
Vcc
12 ± 0.6 V
0 to Vcc V min 0 µs
Vpp min 6φ
12 ± 0.6 V
0 to Vcc V
MD2 tMDS
tMDS*2
min 0 µs
RES
VppE
VppE set cleared tFRS*2
VppE bit
Mode change*1 Boot mode Mode User User program mode User User
change*1 mode mode program
mode

Notes: 1. When entering boot mode or making a transition from boot mode to another mode, mode switching must be carried
out by means of input. The states of ports multiplexed as address pins and bus control output signals ( , ,
, ) change during this switchover interval (the interval during which the pin input is low), and therefore
these pins should not be used as output signals during this time.
2. When making a transition from boot mode to another mode, the flash memory read setup time t FRS and mode
programming setup t MDS must be satisfied with respect to clearance timing.
Figure 19-26 Mode Transition Timing

(Example: Boot Mode ⇒ User Mode ⇔ User Program Mode)
(4) Do not apply 12 V to the VPP pin during normal operation. To prevent program runaway
caused by accidental programming or erasing, apply 12 V to VPP only when the flash memory is
programmed or erased, or when flash memory is emulated by RAM. Overprogramming or
overerasing due to program runaway, etc., may prevent memory cells from operating normally.
While 12 V is applied, the watchdog timer should be running and enabled to halt runaway
program execution, so that program runaway will not lead to overprogramming or overerasing.
(5) Disable watchdog timer reset output (5(62 5(62)

5(62 while the programming voltage (VPP) is
applied. If 12 V is applied during watchdog timer reset output (while the 5(62 pin is low),
overcurrent flow will permanently destroy the reset output circuit. When 12 V is applied to the
VPP/5(62 pin, the reset output enable bit (RESOE) in the watchdog timer reset control/status
register (RSTCSR) should not be set to 1.
If a VCC pull-up resistor is connected to the VPP/5(62 pin externally, a diode must be inserted to
prevent reverse current to the VCC side when VPP is applied (figure 19-21).
Rev. 3.0, 02/99, page 587 of 904

5(62 pin is used as the watchdog timer reset output (when 12 V is not
(6) When the VPP/5(62
applied), the rise and fall of the reset output waveform will be delayed by any decoupling
5(62 pin, the VCC pull-up resistor, etc.
capacitors connected to the VPP/5(62
(7) Follow the recommended algorithm for programming and erasing flash memory. This
algorithm enables programming and erasing to be performed without subjecting the device to
voltage stress or sacrificing programmed data reliability.
When setting the program (P) bit or erase (E) bit in the flash memory control register (FLMCR),
the watchdog timer should be set beforehand to prevent program runaway.
(8) Do not set or clear the VPPE bit while a program is running in flash memory. Flash
memory data cannot be read normally when the VPPE bit is set or cleared. Also, although flash
memory data can be rewritten after waiting for the elapse of the VPP enable setup time (tVPS), flash
memory can only be accessed for the purpose of verification (verification during the program,
erase, or prewrite flow). Flash memory program execution and data reading should only be
performed after the elapse of the flash memory setup time after the VPPE bit is cleared.
In the same way, when using the function for emulation by RAM with 12 V applied to the VPP pin,
the flash memory read setup time must be provided after clearing the VPPE bit when executing a
program or reading data in flash memory. However, read and write accesses can be carried out in
flash memory space and the overlapped RAM area regardless of whether the VPPE bit is set or
cleared.
(9) Do not use interrupts while programming or erasing flash memory. When VPP is applied,
disable all interrupt requests, including NMI, to give the programming or erase operation
(including emulation by RAM) the highest priority.
(10) Before programming, check that the chip is correctly mounted in the PROM
programmer. Overcurrent damage to the device can result if the index marks on the PROM
programmer socket, socket adapter, and chip are not correctly aligned.
(11) Do not touch the socket adapter or chip while programming. Touching either of these
can cause contact faults and write errors.
Rev. 3.0, 02/99, page 588 of 904

19.8 Handling of VPP and Mode
Notes on Mounting Board Development
MD2 Pins
(1) The standard 12 V high voltage is applied to the VPP and mode MD2 pins when erasing or
programming flash memory. The voltage at these pins also includes overshoot and noise, and
the following points should be noted to ensure that the 13 V maximum rated voltage is not
exceeded. 12 V must not be applied to the S-mask or A-mask model (single power source), as this
may cause permanent damage to the chip.
For information concerning the use of the S-mask or A-mask model, see section 20, Flash
Memory (H8/539F, S-Mask and A-Mask Models, Single Power Source).
(a) Bypass capacitors should be inserted to eliminate overshoot and noise. These should be
positioned as close as possible to the chip's VPP and mode MD2 pins.
1.0 µF: Stabilizes fluctuations in the power supply low-frequency components, such as power
supply ripple.
0.01 µF: Bypasses high-frequency components such as induction noise.
(b) The VPP and mode MD2 pin wiring should be kept as short as possible to suppress
induction noise. When designing a new board, in particular, noise may be increased by jumper
wires, etc. In this case too, the power supply waveform should be monitored and measures taken
to prevent the maximum rating from being exceeded.
(c) The maximum rated voltage is based on the potential of the VSS pin. If the potential of this
pin oscillates due to current fluctuations, etc., the voltage of the VPP and mode MD2 pins may
exceed the maximum rated voltage. Careful attention must therefore be paid to stabilizing the
reference potential.
Note: When the user system's 12 V power supply is connected, attention must be paid to the
current capacity. A power supply with a small current capacity will not be able to handle
fluctuations in the chip's operating voltage, resulting in voltage drops and rises or
oscillation that may make it impossible to obtain the rated operating voltage. Caution is
required if the power supply has a large current capacity, or if the 12 V voltage is turned
on abruptly by means of a switch, etc., since a voltage exceeding the maximum rating may
be generated due to the inductance component of the power supply wiring or the power
supply characteristics.
Before using the power supply, check the power supply waveform to ensure that the above
problems will not arise.
(2) 12 V is applied to the VPP and mode MD2 pins when erasing or programming flash
memory. When these pins are pulled up to the VCC line in normal operation, diodes should be
inserted to prevent reverse current from flowing to the VCC line when 12 V is applied.
Rev. 3.0, 02/99, page 589 of 904

Note: If the mode MD2 pin to which 12 V is applied is to be set to 0 in normal operation, it
should be pulled down with a resistor.
VCC
VPP pin
12 V
VPP H8/539F
(dual power
system)
VCC
0.01 µF 1.0 µF
12 V
MD2
Mode pin
Mode pin
0.01 µF 1.0 µF
Adapter board
User system
Note: This sample circuit cannot be used with the S-mask or A-mask model (single power system).
Figure 19-27 Example of Mounting Board Design for H8/539F (dual power system)
When VPP Pin and Mode Pin Settings are 1)
(Connection to Adapter Board
Rev. 3.0, 02/99, page 590 of 904

(H8/539F, S-Mask and A-Mask Models:
Single Power Source)
20.1 Overview
20.1.1 Notes on S-Mask and A-Mask Models (Single Power Source)
There are three models of the H8/539F with on-chip flash memory: a dual power source model
and two single power source (S-mask and A-mask) models. Points to be noted when using the
H8/539F single power source S-mask and A-mask models are given below.
For the differences between the dual power source model and single power source (S-mask and A-
mask) models, see section 1.4.3, Differences in S-Mask and A-Mask Models.
(1) Voltage application
12 V must not be applied to the S-mask or A-mask model (single power source), as this will
The flash memory programming power source for the S-mask and A-mask models (single power
source) is VCC.
The programming power source for the dual power source model was the VPP pin (12 V), but there
is no VPP pin in the single power source models. In the S-mask and A-mask models the FWE pin
is provided at the same pin position as the VPP pin in the dual power source model, but FWE is not
a power source pin—it is used to control flash memory write enabling.
Also, in boot mode, 12 V must be applied to the MD2 pin in the dual power source model, but this
is not necessary in the S-mask or A-mask model (single power source).
The maximum rating of the FWE and MD2 pins in the S-mask and A-mask models (single power
source) is VCC +0.3 V. Applying a voltage in excess of the maximum rating will permanently
damage the device.
Do not select the HN28F101 programmer setting for the S-mask or A-mask model (single power
source). If this setting is made by mistake, 12.0 V will be applied to the FWE pin, permanently
damaging the device.
When using a PROM programmer to program the on-chip flash memory in the S-mask model
(single power source), use a PROM programmer that supports Hitachi microcomputer device
types with 128-kbyte on-chip flash memory.
Rev. 3.0, 02/99, page 591 of 904

(2) Product type names and markings
Table 20-1 shows examples of product type names and markings for the H8/539F (dual power
source model) and H8/539F S-mask and A-mask models (single power source), and the
differences in flash memory programming power source.
Table 20-1 Differences between H8/539F, H8/539F S-Mask, and A-Mask Model Markings
Dual Power Source Single Power Source Single Power Source

Model: Model: Model:
H8/539F H8/539F S-Mask Model H8/539F A-Mask Model
Product type HD64F5398F16 HD64F5398SF16 HD64F5398AF16
name
Sample
markings
H8/539 H8/539 H8/539
S A
HD64F5398F16 HD64F5398F16 HD64F5398F16
JAPAN JAPAN JAPAN
"S" is printed above the "A" is printed above the

type name type name
Flash VPP power source VCC power source VCC power source
memory (12.0 ±0.6 V) (5.0 ±10%) (5.0 ±10%)
programming
power source
20.1.2 Mode Pin Settings and ROM Space
The H8/539F has 128 kbytes of on-chip flash memory. The ROM is connected to the CPU by a
16-bit data bus. The CPU accesses flash memory in two states for both byte-size and word-size
instructions.
The flash memory is allocated to addresses H'00000-H'03FFF and H'10000-H'2FFFF in the

memory map. The contents of flash memory addresses H'00000-H'03FFF are the same as those of
addresses H'10000-H'13FFF. This space can be switched between on-chip flash memory space
and external memory space with a mode pin setting. Mode pin settings and corresponding flash
memory space designations are shown in table 20-1.
Rev. 3.0, 02/99, page 592 of 904

Table 20-1 Mode Pin Settings and ROM Space
Mode Pin Setting

Mode MD2 MD1 MD0 ROM Space Designation
Mode 0 0 0 0 Setting prohibited
Mode 1 0 0 1 External memory space
Mode 2* 0 1 0 On-chip flash memory space
Mode 4 1 0 0 On-chip flash memory space
Mode 7 1 1 1 On-chip flash memory space
Note: * Do not perform flash memory programming or erasing in mode 2.
When mode 2 is set, the FWE pin must be driven low.
20.1.3 Features
The features of the flash memory are summarized below.
Four flash memory operating states There are four flash memory operating states: program
mode, program-verify mode, erase mode, and erase-verify mode.
Erase block specification The flash memory space block to be erased can be specified by setting
the corresponding register bit. The flash memory is divided into three 32-kbyte blocks, one 28-
kbyte block, and four 1-kbyte blocks.
Programming/erase times The flash memory programming time is 10 ms (typ.) for simultaneous
32-byte programming, equivalent to 300 µs (typ.) per byte, and the erase time for one block is 100
ms (typ.).
Reprogramming capability The flash memory can be reprogrammed up to 100 times.
On-board programming modes There are two modes in which flash memory can be
programmed, erased, and verified on-board: boot mode and user program mode.
Automatic bit rate adjustment For data transfer in boot mode, the H8/539F's bit rate can be
automatically adjusted to match the transfer bit rate of the host (9600, 4800, or 2400 bps).
Flash memory emulation in RAM Flash memory programming can be emulated in real time by
overlapping a part of RAM onto flash memory.
PROM mode Flash memory can be programmed and erased in PROM mode, using a PROM
programmer, as well as in on-board programming mode.
Rev. 3.0, 02/99, page 593 of 904
Figure 20-1 shows a block diagram of the flash memory.
8
MD2*
Operating MD1
FLMCR Bus interface/controller MD0
mode
FWE*
EBR1 H'0000 H'0001
H'0002 H'0003
H'0004 H'0005
On-chip flash memory
(128 kbytes)
H'2FFFC H'2FFFD
H'2FFFE H'2FFFF
(Even address) (Odd address)
Legend
FLMCR: Flash memory control register
Note: Memory at addresses H'10000 to H'13FFF can also be read from addresses
H'00000 to H'03FFF.
Addresses H'10000 to H'13FFF comprise a mapping space for addresses
H'00000 to H'03FFFF.
* 12 V must on no account be applied to the S-mask or A-mask model (single power
source), as this will permanently damage the chip.
Figure 20-1 Block Diagram of Flash Memory
Rev. 3.0, 02/99, page 594 of 904

20.1.5 Pin Configuration
The flash memory is controlled by means of the pins shown in table 20-2.
Table 20-2 Flash Memory Pins
Pin Name Abbreviation I/O Function

Flash write enable FWE* Input Sets program mode
Mode 2 MD2* Input Sets H8/539F operating mode
Mode 1 MD1 Input Sets H8/539F operating mode
Mode 0 MD0 Input Sets H8/539F operating mode
Transmit data TXD1 Output Serial transmit data output
Receive data RXD1 Input Serial receive data input
Note: * 12 V must on no account be applied to the S-mask or A-mask model (single power source),
as this will permanently damage the chip.
The transfer data pin and receive data pin are used in boot mode.
The registers used to control the on-chip flash memory are shown in table 20-3.
2
Table 20-3 Flash Memory Registers*
Register Name Abbreviation R/W Initial Value Address

Flash memory control register FLMCR R/W H'00 or H'08 H'FEE0
1, 2
RAM control register* * RAMCR R/W Undefined H'FF15
Flash memory emulation register FLMER R/W H'73 H'FEEC
Flash memory status register FLMSR R H'7F H'FEED
Note: 1. The function of the RAM control register is to enable or disable access to the on-chip
RAM, but in this section it is used for RAM area setting in on-board programming mode.
2. These registers and bits (bits 2 to 0 of RAMCR) are used only for flash memory control,
and are not present in mask and ZTAT versions. Registers and bits exclusively for
flash memory use should not be accessed in mask and ZTAT versions; if they are, a
read will return H'FF (or 1 in the case of RAMCR bits 2 to 0), and writes will be invalid.
Rev. 3.0, 02/99, page 595 of 904

20.2.1 Flash Memory Control Register (FLMCR)
FLMCR is an 8-bit register used for flash memory operating mode control. Program-verify mode
or erase-verify mode is entered by setting SWE to 1 when FWE = 1, then setting the
corresponding bit. Program mode is entered by setting SWE to 1 when FWE = 1, then setting the
PSU bit, and finally setting the P bit. Erase mode is entered by setting SWE to 1 when FWE = 1,
then setting the ESU bit, and finally setting the E bit. FLMCR is initialized by a reset and in
standby mode. Its initial value is H'80 when a high level is input to the FWE pin, and H'00 when a
low level is input. When on-chip flash memory is disabled, a read will return H'00, and writes are
invalid.
Writes to bits ESU, PSU, EV, and PV in FLMCR are enabled only when FWE = 1 and SWE = 1;
writes to the E bit only when FWE = 1, SWE = 1, and ESU = 1; and writes to the P bit only when
FWE = 1, SWE = 1, and PSU = 1.
Rev. 3.0, 02/99, page 596 of 904

Bit 7 6 5 4 3 2 1 0
FWE SWE ESU PSU EV PV E P
Initial value 0/1 0 0 0 0 0 0 0
R/W R R/W R/W R/W R/W R/W R/W R/W
Program mode
Selects program
mode transition
or clearing
Erase mode
Selects erase mode
transition or clearing
Program-verify mode
Selects program-verify
mode transition or clearing
Erase-verify mode
Selects erase-verify mode
transition or clearing
Program setup
Prepares for a transition
to program mode
Erase setup
Prepares for a transition
to erase mode
Software write enable

Enables or disables
programming/erasing
Flash write enable

Sets hardware protection against
flash memory programming/erasing
Rev. 3.0, 02/99, page 597 of 904

Flash Write Enable (FWE): Sets hardware protection against flash memory
Bit 7
programming/erasing. See section 20.7, Flash Memory Programming and Erasing Precautions, for
more information on the use of this bit.
Bit 7
FWE Description
0 When a low level is applied to the FWE pin (hardware-protected state)
1 When a high level is applied to the FWE pin
Software Write Enable (SWE)* , * : Enables or disables flash memory programming and
1 2
Bit 6
erasing. This bit should be set before setting FLMCR bits 5 to 0 and EBR bits 7 to 0. (Do not set
the ESU, PSU, EV, PV, E, or P bit at the same time.)
Bit 6
SWE Description
0 Programming/erasing disabled (Initial value)
1 Programming/erasing enabled [Setting condition] When FWE = 1
Erase Setup (ESU)* : Prepares for a transition to erase mode. (Do not set the SWE, PSU,
1
Bit 5
EV, PV, E, or P bit at the same time.)
Bit 5
ESU Description
0 Erase setup cleared (Initial value)
1 Erase setup [Setting condition] When FWE = 1 and SWE = 1
Program Setup (PSU)* : Prepares for a transition to program mode. (Do not set the
1
Bit 4
SWE, ESU, EV, PV, E, or P bit at the same time.)
Bit 4
PSU Description
0 Program setup cleared (Initial value)
1 Program setup [Setting condition] When FWE = 1 and SWE = 1
Rev. 3.0, 02/99, page 598 of 904

Erase-Verify Mode (EV)* : Selects erase-verify mode transition or clearing. (Do not set
1
Bit 3
the SWE, ESU, PSU, PV, E, or P bit at the same time.)
Bit 3
EV Description
0 Erase-verify mode cleared (Initial value)
1 Transition to erase-verify mode [Setting condition] When FWE = 1 and SWE = 1
Program-Verify Mode (PV)* : Selects program-verify mode transition or clearing. (Do

1
Bit 2
not set the SWE, ESU, PSU, EV, E, or P bit at the same time.)
Bit 2
PV Description
0 Program-verify mode cleared (Initial value)
1 Transition to program-verify mode [Setting condition] When FWE = 1 and SWE = 1
Erase Mode (E)* , * : Selects erase mode transition or clearing. (Do not set the SWE,
1 3
Bit 1
ESU, PSU, EV, PV, or P bit at the same time.)
Bit 1
E Description
0 Erase mode cleared (Initial value)
1 Transition to erase mode [Setting condition] When FWE = 1, SWE = 1, and ESU =
1
Rev. 3.0, 02/99, page 599 of 904

Program Mode (P)* , * : Selects program mode transition or clearing. (Do not set the
1 3
Bit 0
SWE, ESU, PSU, EV, PV, or E bit at the same time.)
Bit 0
P Description
0 Program mode cleared (Initial value)
1 Transition to program mode [Setting condition] When FWE = 1, SWE = 1, and PSU
=1
Notes: 1. Do not set multiple bits simultaneously. Do not cut VCC when a bit is set.
2. The SWE bit must not be set or cleared at the same time as other bits (ESU, PSU, EV,
PV, E, or P).
3. P bit and E bit setting should be carried out in accordance with the program/erase
algorithm shown in section 20.4, Flash Memory Programming/Erasing. Before setting
either of these bits, a watchdog timer setting should be made to prevent program
runaway. See section 20.7, Flash Memory Programming and Erasing Precautions, for
more information on the use of these bits.
Rev. 3.0, 02/99, page 600 of 904

EBR1 is an 8-bit register that specifies the flash memory block to be erased. EBR1 is initialized to
H'00 by a reset, in standby mode, when a high level is not being input to the FWE pin, and when a
high level is input to the FWE pin while the SWE bit in FLMCR is cleared to 0. When a bit in
EBR1 is set to 1, the corresponding block can be erased. Other blocks are erase-protected. Only
one bit in EBR1 can be set at a time (do not set 1 simultaneously for multiple erase blocks). An
EBR1 bit cannot be set to 1 until the SWE bit is set to 1 in FLMCR. The erase block
configuration is shown in table 20-2. Erasing is performed one block at a time. To erase the
entire flash memory, individual blocks must be erased in succession.
Bit 7 6 5 4 3 2 1 0
EB7 EB6 EB5 EB4 EB3 EB2 EB1 EB0
Block 7 to Block 0 (EB7 to EB0): Setting one of these bits specifies the
Bits 7 to 0
corresponding block (EB7 to EB0) for erasure.
Bits 7 to 0
EB7 to EB0 Description
0 Corresponding block (EB7 to EB0) not selected (Initial value)
1 Corresponding block (EB7 to EB0) selected
Rev. 3.0, 02/99, page 601 of 904

Page 1/2 Page 0
Corresponding addresses addresses
Bit Addresses
H'10000 H'0000
H'00000-H'003FF
EB0 1 kbyte(EB0)
(H'10000-H'103FF)
H'103FF H'03FF
H'00400-H'007FF H'10400 H'0400
EB1 (H'10400-H'107FF) 1 kbyte(EB1)
H'107FF H'07FF Mapping*1
H'00800-H'00BFF H'10800 H'0800 area
EB2 1 kbyte(EB2) (16 kbytes)
(H'10800-H'10BFF)
H'10BFF H'0BFF
H'00C00-H'00FFF H'10C00 H'0C00
EB3 (H'10C00-H'10FFF) 1 kbyte(EB3)
Block H'10FFF H'0FFF
area H'11000 H'1000
H'01000-H'03FFF H'13FFF H'3FFF
(128 kbytes) EB4 (H'11000-H'17FFF) H'14000 28 kbytes(EB4*2)
H'17FFF
H'18000
EB5 H'18000-H'1FFFF 32 kbytes(EB5)
H'1FFFF Non-mapping
H'20000 area
EB6 H'20000-H'27FFF 32 kbytes(EB6) (112 kbytes)
H'27FFF
H'28000
EB7 H'28000-H'2FFFF 32 kbytes(EB7)
H'2FFFF
Notes: 1. The mapping area can be accessed from both page 0 and page 1. If addresses for which only
the page is different are specified (e.g. H'003FF and H'103FF), the same memory will be
accessed. Consequently, when performing programming or erasing on this mapping area,
(EB0 to EB3, but not EB4) only page 0 or page 1, but not both, should be specified.
When the RAM emulation function is used to overlap RAM onto a ROM area, the overlapped
page 0 RAM area is not mapped in page 1 (since RAM emulation can only be used in page 0).
In this case, a read access to page 1 will return the ROM contents.
2. The first part of the area (block EB4) includes a mapping area, but should be specified in
page 1 when erasing. In mode 2 (on-chip ROM enabled, minimum mode), user program mode
is prohibited. When mode 2 is set, the FWE pin must be set to 0.
Figure 20-2 Flash Memory Erase Blocks
Rev. 3.0, 02/99, page 602 of 904

20.2.3 RAM Control Register (RAMCR)
RAMCR controls enabling and disabling of access to on-chip RAM, and RAM area overlapping.
Bit 7 6 5 4 3 2 1 0
RAME1 - RAME2 - - RAM2 RAM1 -
Initial value 1 * 1 * * 0 0 *
R/W R/W - R/W - - R/W R/W -
Reserved bits
RAM2, RAM1
Specify a flash memory
to be overlapped
Reserved bits
RAM enable bit 2

Enables/disables access to on-chip
RAM addresses H'EE80-H'F67F
Reserved bit
RAM enable bit 1

Enables/disables access to on-chip
RAM addresses H'F680-H'FE7F
Note: * The value of bits 6, 4, 3, and 0 is undefined when RAMCR is read.
Bits 7 and 5—RAM Enable 1, RAM Enable 2 (RAME1, RAME2): When bits 7 and 5 are
cleared to 0, access to on-chip RAM is disabled. For details, see section 18.2, RAM Control
Register.
Reserved: These bits cannot be modified and will return an undefined value if
Bits 6, 4, 3, 0
read.
Bits 2 and 1RAM2, RAM1: Used together with bits 7, 3, and 2 in the flash memory emulation
register (FLMER) to select the ROM area to be overlapped (see table 20-4.) In modes 2, 4, and 7
1
(on-chip flash memory enabled), these bits have an initial value of 0 and can be modified* . In
other modes they cannot be modified and are always read as 0. These bits are initialized by a reset
and in hardware standby mode. They are not initialized in software standby mode.
Rev. 3.0, 02/99, page 603 of 904

Notes: 1. Bits 2 to 1 of the RAM control register (RAMCR) can be written to in modes 2, 4, and
7.
The H8/539F S-mask and A-mask models use a single 5 V power source, and do not
have a VPP pin. As with the regular H8/539F, the H8/539F S-mask and A-mask models
can perform RAM emulation in modes 2, 4, and 7 (on-chip flash memory enabled).
Flash memory programming must not performed in mode 2.
20.2.4 Flash Memory Emulation Register (FLMER)
FLMER performs enabling and disabling of flash memory RAM emulation and RAM area
modification when RAM emulation is started.
Bit 7 6 5 4 3 2 1 0
OVLPE - - - A11E A10E - -
R/W R/W - - - R/W R/W - -
Reserved bits
A10E bit
Bits A11E and A10E
specify a RAM area to
be overlapped onto
flash memory
A11E bit
Bits A11E and A10E
specify a RAM area to be
overlapped onto flash memory
Reserved bit
Emulation RAM enable (overlap RAM enable)

Enables or disables overlapping of a part of
RAM onto a flash memory small block area
Rev. 3.0, 02/99, page 604 of 904

Bit 7Emulation RAM Enable (OVLPE): Used with bits 3 and 2 to specify a RAM area (see
table 20-4). When bit 7 is set, all flash memory blocks are protected from programming and
1
erasing, regardless of the values of bits 3 and 2. This state is referred to as emulation protection* .
In this state the flash memory will not enter program mode or erase mode even if the P or E bit is
set in the flash memory control register (FLMCR). Only transitions to verify modes are possible.
Bit 7 must be cleared to 0 to enable flash memory to be actually programmed or erased.
In modes 2, 4, and 7 (with on-chip flash memory enabled), the initial value of this bit is 0, but it
2
can be modified by writing 1* . In other modes this bit cannot be modified and always reads 0. It
is initialized by a reset and in hardware standby mode. It is not initialized in software standby
mode. Flash memory programming must not performed in mode 2.
A11E, A10E: These bits specify a RAM area to be overlapped onto ROM when
Bits 3 and 2
performing flash memory emulation in RAM (see table 20-5).
In modes 2, 4, and 7 (with on-chip flash memory enabled), the initial value of these bits is 0, but
they can be modified. In other modes these bits cannot be modified and always read 0. They are
initialized by a reset and in hardware standby mode. They are not initialized in software standby
mode. Flash memory programming must not performed in mode 2.
Notes: 1. For details of emulation protection, see section 20.4.8, Protection Modes.
2. Bits 7, 3, and 2 of the flash memory emulation register (FLMER) and bits 2 and 1 of
the RAM control register (RAMCR) can be written to in modes 2, 4, and 7.
regardless of the VPP voltage. The H8/539F S-mask and A-mask models use a single 5
V power source, and do not have a VPP pin. As with the regular H8/539F, the H8/539F
S-mask and A-mask models can perform RAM emulation in modes 2, 4, and 7 (on-
chip flash memory enabled).)
Rev. 3.0, 02/99, page 605 of 904

20.2.5 Flash Memory Status Register (FLMSR)
FLMSR is used to detect flash memory errors.
Bit 7 6 5 4 3 2 1 0
FLER − − − − − − −
R/W R − − − − − − −
Reserved bit
Flash memory error (FLER)

Status flag indicating detection of an error
during flash memory programming or erasing
Rev. 3.0, 02/99, page 606 of 904

Flash Memory Error (FLER): Indicates that an error has occurred during flash memory
Bit 7
programming or erasing. When FLER is set to 1, flash memory enters error protection mode.
Bit 7
FLER Description
1
0 Flash memory program/erase protection (error protection* ) (Initial value)
is disabled
[Clearing condition]
5(6 pin reset* or hardware standby mode
3
1 An error has occurred during flash memory programming/erasing, and error

1
protection* has been enabled
[Setting conditions]
•
2
When flash memory is read* during programming/erasing (including a vector
read or instruction fetch, but excluding a read in a RAM area overlapped onto
flash memory space)
• Immediately after the start of exception handling during programming/erasing
(excluding reset, illegal instruction, trap instruction, and division-by-zero
4
exception handling)*
• When a SLEEP instruction (including software standby) is executed during
programming/erasing
•
5
When the bus is released during programming/erasing*
Notes: 1. For details of error protection, see section 20.4.8, Protection Modes.
2. An undefined value will be read in this case.
3. In the H8/538F, a watchdog timer reset is included in the FLER bit clearing conditions,
but only 5(6 pin reset input is applicable in the case of the H8/539F.
4. Before a stack or vector read is performed in exception handling.
5. Applies to the H8/539F S-mask and A-mask models. The bus release condition does
not apply to the H8/538F or H8/539F.
Bits 6 to 0 are reserved. They cannot be modified and are always read as 1.
Rev. 3.0, 02/99, page 607 of 904


ROM Area Register 1 1
1 Bit 2* Bit 1*
(Mapping RAM Bit 7* Overlap Program/Erase
Area) Function Protection
OVLPE RAM2 RAM1
− 0 0/1 0/1 Disabled Disabled
H'0000−H'03FF 1 0 0 Enabled Enabled
H'0800−H'0BFF 1 1 0 Enabled Enabled
H'0C00−H'0FFF 1 1 1 Enabled Enabled
2

2
ROM Area * 1 1 1 1
Bit 3* Bit 2* Bit 7* Bit 5*
(Mapping RAM
Area) A11E A10E RAME1 RAME2
H'F000−H'F3FF 0 0 1 1
(1024 bytes)
H'F400−H'F7FF 0 1 1 1
(1024 bytes)
H'F800−H'FBFF 1 0 1 1
(1024 bytes)
3
Use prohibited* 1 1 1 1
4
Use prohibited* 0/1 0/1 0 0
4
4
Notes: 1. Bits 7, 3, and 2 of the flash memory emulation register (FLMER) and bits 2 and 1 of the
S-mask and A-mask models can perform RAM emulation in modes 2, 4, and 7 (on-chip
flash memory enabled). Flash memory programming must not performed in mode 2.)
2. RAM area overlapped onto flash memory.
3. Use prohibited when A11E and A10E are both set to 1. (A10E cannot be set to 1 when
A11E is set to 1).
4. Use prohibited when RAME1 = 0 or RAME2 = 0. (Can only be used when RAME1 =
RAME2 = 1.)
Rev. 3.0, 02/99, page 608 of 904

Example of ROM Area/RAM Area Overlap
ROM area RAM area

H'0000 H'F000
to
EB0
H'03FF H'F3FF RAM
H'0400 H'F400 overlap
ROM to EB1 ROM Actual RAM to area
blocks H'07FF selection H'F7FF (H'F000 to
EB0 to EB3 H'0800 area H'F800 H'FBFF)
(H'0000 to to Mapping RAM RAM to
H'0FFF) H'0BFF EB2 selection
area H'FBFF
H'0C00
to EB3
H'0FFF
Rev. 3.0, 02/99, page 609 of 904

20.3 On-Board Programming Mode
When on-board programming mode is set, on-chip flash memory programming, erasing, and
verifying can be carried out. There are two operating modes in this modeboot mode and user
program modeset by the mode pins (MD2 to MD0) and the FWE pin. The pin settings for
entering each mode are shown in table 20-6. Boot mode and user program mode cannot be used in
H8/539F mode 2 (on-chip ROM enabled). For notes on FWE pin application and disconnection,
see section 20.7, Flash Memory Programming and Erasing Precautions.
Table 20-6 On-Board Programming Mode Settings

2 2
Mode Selection FWE* MD2* MD1 MD0 Notes
1 1
Boot mode Mode 4 1* 1 0 1* 0:VIL
1 1:VIH
Mode 7 1 1 0*
User program Mode 4 1 0 0
mode
Mode 7 1 1 1
Notes: 1. (1) For the high level application timing, see items (6) and (7) in Notes on Use of
Boot Mode.
(2) In boot mode, the input is the inverse of the MD0 setting.
(3) In boot mode, the mode control register (MDCR) can be used to monitor the
status of modes 4 and 7 in the same way as for normal mode.
2. 12 V must on no account be applied to the S-mask or A-mask model (single power
source), as this will permanently damage the chip.
20.3.1 Boot Mode
When boot mode is used, a user program for flash memory programming and erasing must be
prepared beforehand in the host personal computer, etc., and channel 1 of the SCI to be used must
be set to asynchronous mode. When the H8/539F is set to boot mode, after reset release the boot
program already incorporated in the H8/539F is activated, the low period of the data sent from the
host is first measured, and the bit rate register (BRR) value determined. It is then possible to
receive a user program from off-chip using the H8/539F's on-chip serial communication interface
(SCI), and the received user program is written into RAM.
Control then branches to the start address (H'F380) of the on-chip RAM, the program written in
RAM is executed, and flash memory programming/erasing can be carried out. Figure 20-3 shows
a system configuration diagram when using boot mode, and figure 20-4 shows the boot program
mode execution procedure.
Rev. 3.0, 02/99, page 610 of 904

H8/539F
Reception of programming data

RXD1
HOST SCI
Transmission of verify data
TXD1
Figure 20-3 System Configuration When Using Boot Mode
Rev. 3.0, 02/99, page 611 of 904

Boot Mode Execution Procedure
The boot mode execution procedure is shown below.
1. Set the H8/539F to boot mode and execute a

Start reset-start.
2. Set the host to the prescribed bit rate
(2400/4800/9600) and have it transmit H'00
1 Set pins to boot mode for H8/539F and data continuously using a transfer data format
execute reset-start of 8-bit data plus 1 stop bit.
3. The H8/539F repeatedly measures the low
period at the RXD1 pin and calculates the
2 Host transmits H'00 data continuously
at prescribed bit rate asynchronous communication bit rate used by
the host.
4. After SCI bit rate adjustment is completed, the
H8/539F measures low period of H8/539F transmits one H'00 data byte to
H'00 data transmitted by host indicate the end of adjustment.
3 5. On receiving the one-byte data indicating
H8/539F calculates bit rate and completion of bit rate adjustment, the host
sets value in bit rate register should confirm normal reception of this
indication and transmit one H'55 data byte.
6. After transmitting H'55, the host receives H'AA
After bit rate adjustment, H8/539F transmits and transmits the number of user program
4 one H'00 data byte to host to indicate bytes to be transferred. The number of bytes
end of adjustment should be sent as two bytes, upper byte
followed by lower byte. The host should then
Host confirms normal reception of bit rate transmit sequentially the program set by the
5 adjustment end indication, and user.
transmits one H'55 data byte The H8/539F transmits the received byte count
and user program sequentially to the host, one
byte at a time, as verify data (echo-back).
After receiving H'55, H8/539F transmits H'AA to 7. The H8/539F sequentially writes the received
6 host, and receives, as 2 bytes, number of program
user program to on-chip RAM area H'F380-
bytes (N) to be transferred to on-chip RAM *1
H'FE7F (2.8 kbytes).
8. Before executing the transferred user program,
the H8/539F branches to the RAM boot
H8/539F transfers user program to RAM *2 program area (H'EE80-H'F37F) and checks for
the presence of data written in the flash
memory. If data has been written in the flash
H8/539F calculates remaining bytes to be memory, the H8/539F erases all blocks.
7 transferred (N = N - 1) 9. The H8/539F transmits H'AA, then branches to
on-chip RAM address H'F380 and executes
the user program written in area H'F380-
No H'FE7F.
Transfer end byte count
(N = 0?)
Notes: 1. The size of the RAM area available to
Yes the user is 2.8 kbytes. The number of
bytes to be transferred must not exceed
H8/539F branches to RAM boot program area
2.8 kbytes. The transfer byte count
(H'EE80-H'F37F), then checks flash memory
user area data must be sent as two bytes, upper byte
followed by lower byte.
Example of transfer byte count: for 256
8 No bytes (H'0100), upper byte = H'01,
All data = H'FF? lower byte = H'00
2. The part of the user program that
Erase all flash controls the flash memory should be set
Yes
memory blocks *3 in the program in accordance with the
flash memory program/erase algorithm
described later in this section.
H8/539F transmits H'AA, then branches to 3. If a memory cell does not operate
9
RAM area address H'F380 and executes user normally and cannot be erased, the
program transferred to RAM H8/539F will transmit one H'FF byte as
Figure 20-4 Boot Mode Flowchart
Rev. 3.0, 02/99, page 612 of 904

Automatic SCI Bit Rate Adjustment
Start Stop
D0 D1 D2 D3 D4 D5 D6 D7
bit bit
Low period (9 bits) measured (H'00 data)

High period
(1 or more bits)
Figure 20-5 Measurement of Low Period of Host's Transmit Data
When boot mode is initiated, the H8/539F measures the low period of the asynchronous SCI
communication data transmitted continuously from the host (figure 20-5). The data format should
be set as 8-bit data, 1 stop bit, no parity. The H8/539F calculates the bit rate of the transmission
from the host from the measured low period (9 bits), and transmits one H'00 byte to the host to
indicate the end of bit rate adjustment. The host should confirm that this adjustment end
indication has been received normally, and transmit one H'55 byte to the H8/539F. If reception
cannot be performed normally, initiate boot mode again (reset), and repeat the above operations.
Depending on the host's transmission bit rate and the H8/539F's system clock frequency, there will
be a discrepancy between the bit rates of the host and the H8/539F. To ensure correct SCI
1
operation, the host's transfer bit rate should be set to 2400, 4800, or 9600 bps* . Table 20-7 shows
typical host transfer bit rates and system clock frequencies for which automatic adjustment of the
H8/539F bit rate is possible. The boot program should be executed within this system clock
2
range* .
Notes: 1. Use a host bit rate setting of 2400, 4800, or 9600 bps only. No other setting should be
used.
2. Although the H8/539F may also perform automatic bit rate adjustment with bit rate
and system clock combinations other than those shown in table 20-7, a degree of error
will arise between the bit rates of the host and the H8/539F, and subsequent transfer
will not be performed normally. Therefore, only a combination of bit rate and system
clock frequency within one of the ranges shown in table 20-7 can be used for boot
mode execution.
Table 20-7 System Clock Frequencies for which Automatic Adjustment of H8/539F Bit
Rate is Possible
System Clock Frequency for which

Host Bit Rate Automatic Adjustment of H8/539F Bit Rate is Possible
Rev. 3.0, 02/99, page 613 of 904

RAM Area Divisions in Boot Mode
In boot mode, the 1280-byte area from H'EE80 to H'F37F is reserved for boot program use, as
shown in figure 20-6. The area to which the user program is transferred is H'F380 to H'FE7F
(2.75 kbytes). The boot program area becomes available when a transition is made to the
execution state for the user program transferred to RAM.
H'EE80
Boot
program Note: * The boot program area cannot be used
area * until a transition is made to the execution
(1.25 kbytes) state for the user program transferred to
RAM (i.e. a branch is made to RAM
H'F380 address H'F380). Note also that the boot
program remains in the boot program
area in RAM (H'EE80−H'F37F) even
after control branches to the user program.
User program
transfer area
(2.75 kbytes)
H'FE7F
Figure 20-6 RAM Areas in Boot Mode
Notes on Use of Boot Mode:
1. When the H8/539F comes out of reset in boot mode, it measures the low period of the input at
the SCI's RXD1 pin. The reset should end with RXD1 high. After the reset ends, it takes about
100 states for the chip to get ready to measure the low period of the RXD1 input.
2. In boot mode, if any data has been programmed into the flash memory (if all data is not H'FF),
all flash memory blocks are erased. Boot mode is for use when user program mode is
unavailable, such as the first time on-board programming is performed, or if the program
activated in user program mode is accidentally erased.
3. Interrupts cannot be used while the flash memory is being programmed or erased.
4. The RXD1 and TXD1 lines should be pulled up on the board.
5. Before branching to the user program (RAM address H'F380), the H8/539F terminates transmit
and receive operations by the on-chip SCI (channel 1) (by clearing the RE and TE bits to 0 in
the serial control register (SCR)), but the adjusted bit rate value remains set in the bit rate
register (BRR). The transmit data output pin, TXD1, goes to the high-level output state
(P72DDR = 1 in the port 7 data direction register, P72DR = 1 in the port 7 data register).
Rev. 3.0, 02/99, page 614 of 904

The contents of the CPU's internal general registers are undefined at this time, so these registers
must be initialized immediately after branching to the user program. In particular, since the stack
pointer (SP) is used implicitly in subroutine calls, etc., a stack area must be specified for use by
the user program.
The initial values of other on-chip registers are not changed.
6. Boot mode can be entered by setting pins MD0 to MD2 and FWE in accordance with the mode
setting conditions shown in table 20.5, and then executing a reset-start.
1
On reset release (a low-to-high transition)* , the H8/539F latches the current mode pin states
internally and maintains the boot mode state. Boot mode can be cleared by driving the FWE
1
pin low, then executing reset release* , but the following points must be noted.
(a) When switching from boot mode to normal mode, the boot mode state within the chip must
first be cleared by reset input via the 5(6 pin. The 5(6 pin must be held low for at least
3
20 system clock cycles.*
(b) If input level at the MD0 and FWE pins is changed in boot mode, the boot mode state will
be maintained in the MCU, and boot mode continued, unless 5(6 pin reset input is
performed. Also, if a watchdog timer reset occurs in the boot mode state, the MCU's
internal state will not be cleared, and the on-chip boot program will be restarted regardless
of the stae of the mode pins.
(c) The FWE pin must not be driven low while the boot program is running or flash memory is
2
being programmed or erased* .
7. If the MD0 and FWE pin input levels are changed from 0 V to 5 V or from 5 V to 0 V during a
reset (while a low level is being input at the 5(6 pin), the MCU's operating mode will change.
As a result, the state of ports with multiplexed address functions and bus control output pins
($6, 5', +:5, /:5) will also change. Therefore, care must be taken to make pin settings to
prevent these pins from becoming output signal pins during a reset, or to prevent collision with
signals outside the MCU.
Notes: 1. Mode pin and FWE pin input must satisfy the mode programming setup time (tMDS)
with respect to the reset release timing.
2. For further information on FWE application and disconnection, see section 20.7, Flash
Memory Programming and Erasing Precautions.
3. See section 4.2.2, Reset Sequence, and section 20.7, Flash Memory Programming and
Erasing Precautions. The reset period during operation is a minimum of 6 system
clock cycles for the H8/538F and H8/539F, but a minimum of 20 system clock cycles
for the H8/539F S-mask and A-mask models.
Rev. 3.0, 02/99, page 615 of 904

20.3.2 User Program Mode
When set to user program mode, the H8/539F can program and erase its flash memory by
executing a user program. Therefore, on-board reprogramming of the on-chip flash memory can
be carried out by providing on-board means of FWE control and supply of programming data, and
storing a programming control program in part of the program area as necessary.
To select user program mode, select a mode that enables the on-chip flash memory (mode 4 or 7),
and apply a high level to the FWE pin. In this mode, on-chip supporting modules other than flash
memory operate as they normally would in modes 4 and 7.
The flash memory itself cannot be read while being programmed or erased, so the control program
that performs programming should be placed in external memory or transferred to RAM and
executed there. Flash memory programming and erasing should not be carried out in mode 2.
User Program Mode Execution Procedure*
The execution procedure when user program mode is entered during program execution in RAM
is shown below. It is also possible to start from user program mode in a reset-start.
Note: *. Do not apply a constant high level to the FWE pin. To prevent inadvertent programming
or erasing due to program runaway, etc., apply a high level to the FWE pin only when the
flash memory is programmed or erased (including execution of flash memory emulation
using RAM). Memory cells may not operate normally if overprogrammed or overerased
due to program runaway, etc. Also, while a high level is applied to the FWE pin, the
watchdog timer should be activated to prevent overprogramming or overerasing due to
program runaway, etc. Flash memory rewriting should not be carried out in mode 2.
Rev. 3.0, 02/99, page 616 of 904

1
Procedure
MD2 to MD0= 100, 111
A program that executes operations 3 to 8 below must be written into
flash memory by the user beforehand.
2
1. Set the mode pins to an on-chip ROM enabled mode (mode 4 or 7).
Reset start
2. Start the CPU with a reset. (The CPU can also be started from user
3 program mode by applying a high level to the FWE pin during the
reset, i.e. while the pin is low.*)
Transfer on-board
programming program to RAM
3. Transfer the on-board programming program to RAM.
4 4. Branch to the program in RAM.

Branch to program in RAM
5. Apply a high level to the FWE pin.*
(Transition to user program mode)
5
6. Check that the FWE pin is high, then execute the on-board
FWE = high
programming program in RAM. As a result, rewriting of the user
(user program mode)
application program in flash memory is performed.
6 7. After rewriting, clear the SWE bit. Drive the FWE pin from high to
Execute on-board low, and clear user program mode.*
programming program in
RAM (flash memory rewriting) 8. On completion of programming, branch to the user application
program in flash memory and run the program.
7 Note * For further information on FWE application and disconnection,
Clear SWE bit, see section 20.7, Flash Memory Programming and Erasing
then release FWE Precautions.
(user program mode clearing)
8
Execute user application
program in flash memory
Figure 20-7 Example of User Program Mode Operation
Rev. 3.0, 02/99, page 617 of 904

20.4 Flash Memory Programming/Erasing
A software method, using the CPU, is employed to program and erase flash memory in the on-
board programming modes. There are four flash memory operating modes: program mode, erase
mode, program-verify mode, and erase-verify mode. Transitions to these modes are made by
setting the PSU, ESU, P, E, PV, and EV bits in FLMCR. The state transitions permitted by the
various FLMCR bit settings are shown in figure 20-8.
The flash memory cannot be read while being programmed or erased. Therefore, the program
(user program) that controls flash memory programming/erasing should be located and executed
in on-chip RAM or external memory.
See section 20.7, Flash Memory Programming and Erasing Precautions, for points to note
concerning programming and erasing, and "Flash Memory Characteristics" in sections 23 and 24,
Electrical Characteristics, for the wait times after setting or clearing FLMCR bits.
Notes: 1. Operation is not guaranteed if setting/resetting of the SWE, ESU, PSU, EV, PV, E, and
P bits in FLMCR is executed by a program in flash memory.
2. When programming or erasing, set FWE to 1 (programming/erasing will not be
executed if FWE = 0).
20.4.1 Program Mode
When writing data or programs to flash memory, the program/program-verify flowchart shown in
figure 20-10 should be followed. Performing programming operations according to this flowchart
will enable data or programs to be written to flash memory without subjecting the device to
voltage stress or sacrificing program data reliability. Programming should be carried out 32 bytes
at a time.
The wait times (x, y, z, α, β, γ, ε, η) after bits are set or cleared in the flash memory control
register (FLMCR) and the maximum number of programming operations (N) are shown in "Flash
Memory Characteristics" in sections 23 and 24, Electrical Characteristics.
Following the elapse of (x) µs or more after the SWE bit is set to 1 in FLMCR, 32-byte data is
written consecutively to the write addresses. The value of the lower 8 bits of the first address
written to must be divisible by 32 (H'00, H'20, H'40, H'60, H'80, H'A0, H'C0, or H'E0). Thirty-
two consecutive byte data transfers are performed. The program address and program data are
latched in the flash memory. A 32-byte data transfer must be performed even if writing fewer
than 32 bytes; in this case, H'FF data must be written to the extra addresses.
Next, to prevent overprogramming in the event of program runaway, etc., the watchdog timer is
set. Set a value greater than (y + z + α + β) µs as the WDT overflow period. Next, preparation for
the program mode (program setup) is carried out by setting the PSU bit in FLMCR, and after the
elapse of (y) µs or more, the operating mode is switched to program mode by setting the P bit in
Rev. 3.0, 02/99, page 618 of 904

FLMCR. The time during which the P bit is set is the flash memory programming time. Make a
program setting so that the time for one programming operation is within the range of (z) µs.
20.4.2 Program-Verify Mode
In program-verify mode, the data written in program mode is read to check whether it has been
correctly written in the flash memory.
After the elapse of a given programming time, the programming mode is exited (the P bit in
FLMCR is cleared, then the PSU bit is cleared at least (α) µs later). The watchdog timer is cleared
after (β) µs or more has elapsed. The operating mode is then switched to program-verify mode by
setting the PV bit in FLMCR. Before reading in program-verify mode, a dummy write of H'FF
data should be made to the addresses to be read. The dummy write should be executed after the
elapse of (γ) µs or more. When the flash memory is read in this state (verify data is read in 16-bit
units), the data at the latched address is read. Wait at least (ε) µs after the dummy write before
performing this read operation. Next, the originally written data is compared with the verify data,
and reprogram data is computed (see figure 20-10) and transferred to RAM. After 32 bytes of
data have been verified, exit program-verify mode, wait for at least (η) µs, then clear the SWE bit
in FLMCR. If reprogramming is necessary, set program mode again, and repeat the
program/program-verify sequence as before. However, ensure that the program/program-verify
sequence is not repeated more than (N) times on the same bits.
Rev. 3.0, 02/99, page 619 of 904

*3
E=1
Erase setup state Erase mode
*1 E=0
Normal
mode
=1
U
ES
=0
U
ES
FWE=0 FWE=1
Erase-verify mode
*2 =1
EV
On-board
SWE=1 Software =0
programming mode EV
programming
Software programming
disable state SWE=0 enable state PS
U= *4
1
PS P=1
U=
0 Program setup state Program mode
P=0
PV
=1
PV
=0
Program-verify mode
Notes: 1. : Normal mode : On-board programming mode

2. Do not make a state transition by setting or clearing multiple bits simultaneously.
3. After a transition from erase mode to the erase setup state, do not enter erase
mode without passing through the software programming enable state.
4. After a transition from program mode to the program setup state, do not enter
program mode without passing through the software programming enable state.
Figure 20-8 Flash Memory Programming State Transitions Permitted by FLMCR Bit
Settings
Rev. 3.0, 02/99, page 620 of 904

20.4.3 Sample 32-Byte Programming Flowchart
32-Byte Programming Flowchart
Start *1
1. Programming should be performed in the
erased state. Do not perform additional Set SWE bit in FLMCR *6
programming. (Perform 32-byte Wait (x) µsec
programming on memory after all 32 bytes
Store 32-byte write data
have been erased.) in reprogram data area
2. Data transfer is performed by byte transfer
(word transfer is not possible). The first Programming operation counter n 1
address written to must be at a 32-byte
boundary with a lower 8-bit value of H'00, Consecutively write 32-byte data *2
in reprogram data area in RAM
H'20, H'40, H'60, H'80, H'A0, H'C0, or H'E0. to flash memory
A 32-byte data transfer must be performed
Enable WDT
even if writing fewer than 32 bytes; H'FF
data must be written to the extra addresses. Set PSU bit in FLMCR *6
3. Verify data is read in 16-bit (word) units. Wait (y) µsec
(Byte-unit reading is also possible.) Set P bit in FLMCR Start of programming

4. Reprogram data is determined by the Wait (z) µsec *6, *7
computation shown in the table below
Clear P bit in FLMCR End of programming
(comparison of data stored in the program Wait ( α) µsec *6
data area with verify data). Programming of
*6
reprogram data 0 bits is executed in the next Clear PSU bit in FLMCR
Wait (β) µsec
programming loop. Therefore, even bits for
which programming has been completed will Disable WDT
be programmed again if the result of the *6
Set PV bit in FLMCR
subsequent verify operation is NG. Wait (γ) µsec
5. An area for storing write data (32 bytes) and
Set verify start address
an area for storing reprogram data (32
bytes) must be provided in RAM. The Programming end flag 0
contents of the latter are rewritten in
accordance with the reprogram data *6
H'FFFF dummy write to verify address
computation. Wait (ε) µsec
6. The values of x, y, z, α, β, γ, ε, η and N are *3
Read verify data
shown in "Flash Memory Characteristics" in
sections 23 and 24, Electrical
Characteristics. Programming OK?
NG
7. The value of z depends on the number of Programming end flag 1 (unfinished)
OK
reprogramming loops (n). Details are given
in "Flash Memory Characteristics" in Reprogram data computation *4
sections 23 and 24, Electrical
Transfer computation result to *5
Characteristics. reprogram data area
Increment verify address
Write Verify Reprogram 32-byte data

Data Data Data Comments NO
verification completed?
0 0 1 Programming YES
*6
completed Clear PV bit in FLMCR
Wait (η) µsec
0 1 0 Programming incomplete;
reprogram Programming end flag = 0?
1 0 1 NO n n+1
YES
1 1 1 Still in erased state; n>N?
NO
no action YES
Clear SWE bit in FLMCR SWE in FLMCR
Note: The memory erased state is "1". Programming
is performed on "0" reprogram data. End of programming Programming failure
Figure 20-9 Programming Flowchart
Rev. 3.0, 02/99, page 621 of 904

Sample Program for Programming 32 Bytes
1. Registers and method used

After the values of the following registers (R1, R2, R3, R4) have been specified, arbitrary 32-
byte data can be written to an arbitrary 32-byte boundary address by calling the fwrites
subroutine.
R1: Page of address storing data to be written
R2: Address storing data to be written
R3: Page of programming address in flash memory
R4: Programming address in flash memory
2. Wait times after setting/clearing FLMCR bits
The number of software loops required to provide a specific wait time depends on the
operating frequency. The relevant operating frequency can be specified by setting the MHZ
symbol value.
3. In this program the wait time (number of loops) is calculated on the assumption that the scb/f
instruction jump destination is located at an even address in two-state access space (on-chip
RAM).
4. Programming should be performed only on flash memory in the erased state.
List 1: Sample Program for Programming 32 Bytes
1: ; ********************************************************************
2: ; * fwrites.src (Ver. 0.12) *
3: ; * Sample program for programming 32 bytes of H8/539FS flash memory *
4: ; * *
5: ; ********************************************************************
6: ;
7: ;
10: MAXWT .equ d'403 ; Maximum number of writes
15: ;
16: ;
17: .align H'2
18: main: .equ $
21: ldc.b #H'00:8,dp ; Data page register setting
22: ldc.b #H'00:8,ep ; Extension page register setting
23: ;
Rev. 3.0, 02/99, page 622 of 904

24: ;
25: ;
29: ;
32: ; (All-mat definition programming example)
33: ;
34: main_end: ; End of programming
35: bra main_end
36: ;
37: ;
38: ;*********************************************************************
39: ;* tensou SUB *
40: ;* Copy RAM execution program to RAM *
41: ;*********************************************************************
42: .align H'2
43: tensou: .equ $
46: stm (R0-R3),@-sp ; save used registers
49: mov.w #RAMSTR,R2 ; Transfer destination address setting
50: tensou01:
51: mov.w @R0+,R3 ; ROM PROG DATA ---> R3
52: mov.w R3,@R2+ ; R3 ---> RAM WRITE
54: blt tensou01 ; R0=R1 ->NEXT INSTRUCTION.
57: ;
58: ;
59: ;*********************************************************************
60: ;** Start of program for transfer to RAM **
61: ;*********************************************************************
62: .align H'2
63: prog_start: .equ $ ; start of program for transfer to RAM
64: ;
65: ;
66: ;
67: ;
68: ;
69: ;*********************************************************************
Rev. 3.0, 02/99, page 623 of 904

70: ; all0_write SUB *
71: ; Flash memory all-mat H'00 programming *
72: ;*********************************************************************
73: .align H'2
74: all0_write: .equ $
75: ; Arguments R0 Return code 0: Normal
76: ; 1: Programming error
77: ; 2: Initial value, etc., error
79: ; R1 Programming data page specification
80: ; R2 Programming data address specification
81: ; R3 Programming page specification
82: ; R4 Programming address specification
84: link FP,#-d'34 ; Reserve stack area
85: ;
86: mov.w FP,R2
87: subs.w #d'32,R2
88: mov.w R2,@(-34,FP) ;Save programming data start address
89: mov.w #d'15,R5
90: all0_w01:
91: clr.w @R2+ ;Zero-clear 32-byte programming data
92: scb/f R5,all0_w01
93: ;
94: clr.b @WCR ; No wait state inserted
95: ldc.w #H'0700,SR ; Disable interrupts during programming/erasing
96: ;
97: bset.b #d'6,@FLMCR ; Set SWE bit
98: mov.w #(d'10 * MHZ / d'8),R5
99: ; Set SWE wait loop counter
100: all0_w02:
101: scb/f R5,all0_w02 ;SWE wait (10 µs or more)
102: ;
104: clr.w R1 ; Set programming data page
105: mov.w @(-34,FP),R2 ; Set programming data address
106: mov.w #H'01,R3 ; Set programming page
107: all0_w03:
108: clr.w R4 ; Set start of page as programming address
109: all0_w04:
110: ;
111: bsr fwrites ;32-byte programming
112: ;
113: tst.w R0 ; Return code check
114: bne all0_w06 ; If error, end
115: ;
Rev. 3.0, 02/99, page 624 of 904

116: cmp.w #H'FFE0,R4 ; Last address of page?
117: bhs all0_w05 ; If last address, next page
118: adds.w #H'20,R4 ; Add 32 bytes of programming address
119: bra all0_w04 ;
120: all0_w05:
121: cmp.b #H'02,R3 ; Last page?
122: bhs all0_w06 ; If last page, end
123: adds.b #H'01,R3 ; Page address + 1
124: bra all0_w03 ;
125: all0_w06:
126: bclr.b #d'6,@FLMCR ; Clear SWE bit
127: mov.w #(d'0 * MHZ / d'8),R5
128: ; Set SWE clear wait counter
129: all0_w07:
130: scb/f R5,all0_w07 ;SWE clear wait (0 µs or more)
131: ;
132: unlk FP ; Release stack area
135: all0_write_end: .equ $
136: ;
137: ;
138: ;*********************************************************************
139: ;* fwrites SUB *
140: ;* Flash memory 32-byte programming (SUB) *
141: ;*********************************************************************
142: .align H'2
143: fwrites: .equ $
144: ; Arguments R0 - /return code 0: Normal
145: ; 1: Programming error
146: ; 2: Initial value, etc., error
147: ; R1 Programming data page
148: ; R2 Programming data address
149: ; R3 Programming page
150: ; R4 Programming address
152: ; R0 Repeat count (for PV)
153: ; R1 Programming counter
154: ; R2 Number of repeats, programming data address
155: ; R3 Reprogramming data address
156: ; R4 Programming address
158: stc.b ep,@-sp ; Save used page registers
159: link FP,#-d'72 ;Reserve stack area
160: ;
161: mov.w FP,R3
Rev. 3.0, 02/99, page 625 of 904

162: subs.w #d'32,R3
163: mov.w R3,@(-34,FP) ;Save reprogramming data address
164: ;
165: mov.w FP,R3
166: subs.w #d'66,R3
167: mov.w R3,@(-68,FP) ; Save programming data address
168: ldc.b @(5,FP),ep ; Programming source data page
169: mov.w @(6,FP),R4 ; Programming source data address
170: mov.w #d'15,R5
171: fwrites01:
172: mov.w @R4+,R2
173: mov.w R2,@(34,R3) ; Copy programming source data to reprogramming data
174: mov.w R2,@R3+ ; Copy programming source data to programming data
175: scb/f R5,fwrites01
176: ;*********************************************************************
177: ;
178: clr.w R1 ; Clear Programming counter
179: clr.w @(-70,FP) ; Clear Programming NG flag
180: fwrites02:
181: ;
182: bset.b #d'2,@FLMCR ; Set PV bit
183: mov.w #(d'4 * MHZ / d'8),R5
184: ; Set PV wait counter
185: fwrites03:
186: scb/f R5,fwrites03 ;PV wait (4 µs or more)
187: ;
188: mov.w @(-68,FP),R2 ; Set programming data address
189: mov.w @(-34,FP),R3 ; Set reprogramming data address
190: ldc.b @(9,FP),ep ; Programming address page
191: mov.w @(10,FP),R4 ; Programming address
192: mov.w #d'15,R0 ; Verify loop counter
193: fwrites04:
194: mov.w #H'FFFF,@R4 ; Dummy write (latch)
195: mov.w #(d'2 * MHZ / d'8),R5
196: ; Set counter for wait after latch
197: fwrites05:
198: scb/f R5,fwrites05 ; Wait after latch (2 µs or more)
199: mov.w @R4+,R5 ; Data read, address + 2
200: not.w R5 ; data inversion
201: mov.w R5,@(-72,FP) ; Set inverted data in calculation work area
202: or.w @R2,R5 ; Inverted data or programming data
203: mov.w R5,@R3+ ; Set reprogramming data, address + 2
204: mov.w @(-72,FP),R5 ; Calculation work area
205: and.w @R2+,R5 ; Inverted data and programming data
206: tst.w R5 ; In case of read data 0 and programming data 1
207: beq fwrites06
Rev. 3.0, 02/99, page 626 of 904

208: mov.w #H'1,@(-70,FP) ; Programming NG flag <-- NG
209: fwrites06:
210: scb/f R0,fwrites04 ;Verify loop counter (R0)=15-0
211: ;
212: bclr.b #d'2,@FLMCR ;Clear PV bit
213: mov.w #(d'4 * MHZ / d'8),R5
214: ;Set counter for wait after clearing PV
215: fwrites07:
216: scb/f R5,fwrites07 ; Wait after clearing PV (4 µs or more)
217: ;*********************************************************************
218: ;
219: mov.w @(-34,FP),R3 ; Reprogramming data address
220: mov.w #d'15,R5 ; repeat counter =16
221: fwrites08:
222: cmp.w #H'FFFF,@R3+ ; 32-byte reprogramming data all FF? R3+2
223: bne fwrites09 ; Decision: if not FF, go to reprogramming FF
224: scb/f R5,fwrites08 ;
225: bra fwrites17 ;If all FF, go to end processing
226: fwrites09:
227: add.w #H'01,R1 ; Programming counter (R1) + 1
228: cmp.w #MAXWT,R1 ; Count decision (max. programming time)
229: bhi fwrites17 ;If count> max. programming time, go to end processing
230: tst.w @(-70,FP) ; When programming NG flag ≠0
231: bne fwrites17 ; Go to end programming
232: ;*********************************************************************
233: ;
234: ; 32-byte dummy write (latch)
235: mov.w @(-34,FP),R3 ; Set reprogramming data address
236: ldc.b @(9,FP),ep ; Programming address page
237: mov.w @(10,FP),R4 ; Programming address p
238: mov.w #d'31,R5 ; Repeat count = 32
239: fwrites10:
240: mov.b @R3+,R2 ; Reprogramming data (byte unit), R3+1
241: mov.b R2,@R4+ ; Dummy write (byte unit), R4+1
242: scb/f R5,fwrites10 ; Repeat for 32 times
243: ;
244: mov.w #H'A57B,@TCSR ; Set WDT
245: bset.b #d'4,@FLMCR ; Set PSU bit
246: mov.w #(d'50 * MHZ / d'8),R5
247: ; Set PSU wait counter
248: fwrites11:
249: scb/f R5,fwrites11 ; PSU wait (50 µs or more)
250: ; ; P setting /P clearing (programming)
251: ;
252: mov.w #((d'150 * MHZ -d'4)/ d'8),R5
253: cmp.w #d'4,R1
Rev. 3.0, 02/99, page 627 of 904

254: ble fwrites12
255: mov.w #((d'500 * MHZ -d'4)/ d'8),R5
256: fwrites12:
257: ; Set P time loop counter
258: bra fwrites13 ;Adjust so that scb/f jump destination is even address
259: .align H'2 ;Adjust so that scb/f jump destination is even address
260: fwrites13:
261: ; nop ;Adjust so that scb/f jump destination is even address
262: ;If odd, insert NOP
263: bset.b #d'0,@FLMCR ; Set P bit
264: ;Adjust so that scb/f jump destination is even address
265: fwrites14:
266: scb/f R5,fwrites14 ;P wait (150/500µs)
267: bclr.b #d'0,@FLMCR ; Clear P bit
268: ;
269: mov.w #(d'10 * MHZ / d'8),R5
270: ; Set counter for wait after clearing P
271: fwrites15:
272: scb/f R5,fwrites15 ;Wait after clearing PS (10 µs or more)
273: ;
274: bclr.b #d'4,@FLMCR ;Clear PSU bit
275: mov.w #(d'10 * MHZ / d'8),R5
276: ;Set wait counter after clearing PSU
277: fwrites16:
278: scb/f R5,fwrites16 ;PSU clear wait (10 µs or more)
279: mov.w #H'A500,@TCSR ; Stop WDT
280: bra fwrites02
281: ;*********************************************************************
282: ;
283: fwrites17:
284: clr.w R0 ;Set return value (R0) = OK
285: cmp.w #MAXWT,R1 ;Programming time decision
286: bls fwrites18 ; Count not exceeded
287: mov.w #H'01,R0 ;Return value (R0)=count exceeded (programming NG)
288: fwrites18:
289: tst.w @(-70,FP) ;When programming NG flag ≠ 0
290: beq fwrites19 ;
291: mov.w #H'02,R0 ;Return value (R0) = initial value error
292: fwrites19:
293: ;
294: unlk FP ; Release stack area
295: ldc.b @sp+,ep ; Restore used page registers
298: ;
299: ;*********************************************************************
Rev. 3.0, 02/99, page 628 of 904

300: ;
301: ;
302: ;
303: ;
304: prog_stop: .equ $ ; End of program transfer to RAM
305: ;
306: ;
307: .end
308:
Notes: 1. The sample programs in this manual are provided to illustrate programming/erasing of
flash memory incorporated in an MCU. They do not make provisions for various kinds
of applications, and cannot be used as they are. They are intended solely for reference
in program development.
2. Program operation must be confirmed in actual use.
3. These programs are subject to change without notice due to improvements, etc.
Rev. 3.0, 02/99, page 629 of 904

20.4.4 Erase Mode
When erasing flash memory, the single-block erase flowchart shown in figure 20-10 (single-block
erase) should be followed for each block.
The wait times (x, y, z, α, β, γ, ε, η) after bits are set or cleared in the flash memory control
register (FLMCR) and the maximum number of erase operations (N) are shown in "Flash Memory
Characteristics" in sections 23 and 24, Electrical Characteristics.
To erase flash memory contents, make a 1-bit setting for the flash memory area to be erased in
erase block register 1 (EBR1) at least (x) µs after setting the SWE bit to 1 in FLMCR. To prevent
overprogramming in the event of program runaway, etc., the watchdog timer is set. Set a value
greater than (y + z + α + β) µs as the WDT overflow period. Next, preparation for erase mode
(erase setup) is carried out by setting the ESU bit in FLMCR, and after the elapse of (y) µs or
more, the operating mode is switched to erase mode by setting the E bit in FLMCR. The time
during which the E bit is set is the flash memory erase time. Ensure that the erase time does not
exceed (z) ms.
Note: With flash memory erasing in the H8/539F S-mask and A-mask models, preprogramming
(setting all memory data in the memory to be erased to all "0") is not necessary before
starting the erase procedure.
20.4.5 Erase-Verify Mode
In erase-verify mode, data is read after memory has been erased to check whether it has been
correctly erased.
After the elapse of a the erase time, erase mode is exited (the E bit in FLMCR is cleared, then the
ESU bit is cleared at least (α) µs later), the watchdog timer is cleared after (β) µs or more has
elapsed, and the operating mode is switched to erase-verify mode by setting the EV bit in
FLMCR. Before reading in erase-verify mode, a dummy write of H'FF data should be made to the
addresses to be read. The dummy write should be executed after the elapse of (y) µs or more.
When the flash memory is read in this state (verify data is read in 16-bit units), the data at the
latched address is read. Wait at least (ε) µs after the dummy write before performing this read
operation. If the read data has been erased (all "1"), a dummy write is performed to the next
address, and erase-verify is performed. If the read data is unerased, perform an erase-verify on the
next block. The erase-verify operation is carried out on all the erase blocks; the erase block
register bit for an erased block should be cleared to prevent excessive application of the erase
voltage. When verification is completed, exit erase-verify mode, and wait for at least (η) µs. If
erasure has been completed on all the erase blocks after completing erase-verify operations on all
these blocks, clear the SWE bit in FLMCR. If there are any unerased blocks, set erase mode
again, and repeat the erase/erase-verify sequence as before. However, ensure that the erase/erase-
verify sequence is not repeated more than (N) times.
Rev. 3.0, 02/99, page 630 of 904

20.4.6 Sample Flowchart for Erasing One Block
Flowchart for Erasing One Block
Start *1
Set SWE bit in FLMCR *2

Wait (x) µsec
Erase counter n 1
*4
Set EBR1 *5
*2
Set ESU bit in FLMCR
Wait (y) µsec
Enable WDT
Set E bit in FLMCR Start of erase

Wait (z) msec *2
Clear E bit in FLMCR Erase halted

Wait (α) µsec *2
Disable WDT
*2
Clear ESU bit in FLMCR
Wait (β) µsec
Clear EBR1
*2
Set EV bit in FLMCR
Wait (γ) µsec
Set block start address to

verify address
*2
H'FFFF dummy write to verify address
Wait (ε) µsec
Read verify data *3
NO
Verify data = H'FFFF?
OK YES
NO
Last address of block?
n n+1
YES
Increment address Clear EV bit in FLMCR *2 Clear EV bit in FLMCR *2
Wait (η) µsec Wait (η) µsec
NO
n>N?
YES
Clear SWE bit in FLMCR Clear SWE bit in FLMCR
End of erasing Erase failure
Notes: 1. No prewriting (setting all the data bits in the block to be erased to 0) is necessary.
2. The values of x, y, z, α, β, γ, ε, η, and N are listed in "Flash Memory Characteristics" in sections 23 and 24, Electrical Characteristics.
3. Verify data is read in 16-bit words. (Note that it can also be read in byte units.)
4. Set only bit 1 of EBR. Bits 2 and above should not be set.
5. Erase data in block units. To erase multiple blocks, erase the blocks sequentially, one block at a time.
Figure 20-10 Flowchart for Erasing One Block

Rev. 3.0, 02/99, page 631 of 904
Setting Loop Counter Values and WDT Overflow Intervals in the Program
A wait time is necessary after a bit is set or cleared in the flash memory control register (FLMCR).
In the program examples, wait times are provided by means of software loops. The software loop
counter value depends on the operating frequency, and whether the scb/f instruction is located at
an even address and in two-state access space, and whether wait state insertion is disabled. In
these program examples, the calculation assumes an even address, two-state access space, and no
wait state insertion.
The value set in TCSR to provide the watchdog timer overflow interval setting when erase mode
is selected depends on the operating frequency. TCSR set values for different operating
frequencies are shown in table 20-8.
As software loops are used, there is intrinsic error in the wait times, and the calculated value and
actual time may not be the same. Therefore, initial values should be set so that the total
programming time does not exceed tP s/byte (max.), and the total erase time does not exceed tE s
(max.). The total programming time, tP µs/byte (max.), and total erase time, tE s (max.), are
shown in "Flash Memory Characteristics" in sections 23 and 24, Electrical Characteristics.
The set value for the watchdog timer (WDT) is calculated on the basis of the number of
instructions including the programming time and erase time from the time the WDT is started until
it stops. Therefore, no other instructions should be added between starting and stopping of the
WDT in these program examples.
The loop counter value for each operating frequency is calculated as shown below.
Formulas:
Formulas for calculating loop counter value in program
(1) Program time (P bit setting) calculation formula When the scb/f instruction is at an even
address in two-state access space, the processing time is 4 states when the register value = 0 (no
branch) and 8 states when the register value ≥ 1 (branch). Thus the calculation formula, with
truncation of the decimal part, is as follows.
(Wait time (µs) × operating frequency (MHz)) states - 4 states

Loop counter value =
8 states
Rev. 3.0, 02/99, page 632 of 904

(2) Erase time (E bit setting) calculation formula For the same access space as in (1) above,
the calculation formula is as follows.
(Wait time (µs) × operating frequency (MHz)) states - 14 states

8 states
(3) Wait time (time after FLMCR bit setting/clearing other than P bit setting or E bit
setting) With the same number of states as in (1) above, the calculation formula, with rounding
of the decimal part, is as follows.
(Wait time (µs) × operating frequency (MHz)) states- 4 +4 states

8 states
Table 20-8 WDT Overflow Interval Setting when Erase Mode is Set
Variable
Operating Frequency [MHz] Value Set in TCSR
10 MHz to 16 MHz H'A57F
2 MHz to less than 10 MHz H'A57E
Sample Block Erase Program
(1) Registers and method used After the values of the following register (R0) has been
specified, an block can be erased by calling the ferases subroutine.
R0: Specification of block to be erased by EBR1 bit position in lower byte
(2) Wait times after setting/clearing FLMCR bits The number of software loops required to
provide a specific wait time depends on the operating frequency. The relevant operating
frequency can be specified by setting the MHZ symbol value.
(3) In this program the wait time (number of loops) is calculated on the assumption that the
scb/f instruction jump destination is located at an even address in two-state access space (on-
chip RAM).
Rev. 3.0, 02/99, page 633 of 904

List 2: Sample Block Erase Program
1: ; ********************************************************************
2: ; * ferases.src (Ver. 0.08) *
3: ; * Sample program for H8/539FS flash memory block erasing *
4: ; * *
5: ; *****************************************************************
6: ;
7: ;
10: MAXET .equ d'60 ; Maximum number of erases
11: ;
13: EBR1 .equ H'FEE2 ; Target block specification register
16: MDCR .equ H'FF19 ; Mode control register
17: ;
18: ;
19: .align H'2
20: main: .equ $
23: ldc.b #H'00:8,dp ; Data page register setting
24: ldc.b #H'00:8,ep ; Extension page register setting
25: ;
26: ;
27: ;
31: ;
34: ; (All-mat erase example)
35: ;
36: main_end: ; End of erase
37: bra main_end
38: ;
39: ;
Rev. 3.0, 02/99, page 634 of 904

40: ;*********************************************************************
41: ;* tensou SUB *
42: ;* Copy RAM execution program to RAM *
43: ;*********************************************************************
44: .align H'2
45: tensou: .equ $
48: stm (R0-R3),@-sp ; save used registers
51: mov.w #RAMSTR,R2 ; Transfer destination address setting
52: tensou01:
53: mov.w @R0+,R3 ; ROM PROG DATA ---> R3
54: mov.w R3,@R2+ ; R3 ---> RAM WRITE
56: blt tensou01 ; R0=R1 ->NEXT INSTRUCTION.
59: ;
60: ;
61: ;*********************************************************************
62: ;** Start of program for transfer to RAM **
63: ;*********************************************************************
64: .align H'2
65: prog_start: .equ $ ; start of program for transfer to RAM
66: ;
67: ;
68: ;
69: ;
70: ;
71: ;*********************************************************************
72: ; all_erase SUB
73: ; Flash memory all-mat erase *
74: ;*********************************************************************
75: .align H'2
76: all_erase: .equ $
77: ; Arguments
78: ; R0 Return code0: Normal
80 : ; R1/Erase NG block
82: ; R0 Erase-verify target block
84: ;
85: clr.b @WCR ; No wait state inserted
Rev. 3.0, 02/99, page 635 of 904
86: ldc.w #H'0700,sr ; Disable interrupts during programming/erasing
87: ;
88: bset.b #d'6,@FLMCR ; Set SWE bit
89: mov.w #(d'10 * MHZ / d'8),R2
90: ; Set SWE wait loop counter
91: all_e01:
92: scb/f R2,all_e01 ;SWE wait (10 µs or more)
93: ;
94: mov.w #H'00FF,R0 ; Erase target block specification
95: bsr erasevf:16 ; Erase-verify
96: tst.b R0 ; Unerased block check
97: beq all_e02 ; If there is unerased block,
98: bsr ferases ; Erase block
99: ; return R0 return code (0:normal,1:erase NG)
100: ; R1 Erase NG block
101: all_e02:
102: bclr.b #d'6,@FLMCR ; Clear SWE bit
103: mov.w #(d'0 * MHZ / d'8),R2
104: ; Set SWE clear wait counter
105: all_e03:
106: scb/f R2,all_e03 ; SWE clear wait (0 µs or more)
107: ;
110: all_erase_end: .equ $
111: ;
112: ;
113: ;*********************************************************************
114: ;* ferases SUB *
115: ;* Flash memory block erase (SUB) *
116: ;*********************************************************************
117: .align H'2
118: ferases: .equ $
119: ; Arguments R0 Erase target block/return code
121: ; 1: Erase error:
122: ; R1 / Erase NG block
123: ; stm (R2-R5),@-sp ; Save used registers
124: ; R1 Erase counter
125: ;
126: and.w #H'00FF,R0 ; Mask bits except EBR1
127: cmp.b #H'C2,@MDCR ; Mode check
128: bne ferases01 ;If mode 2
129: and.w #H'000F,R0 ; mask target blocks except page 0
130: ferases01:
131: ;
Rev. 3.0, 02/99, page 636 of 904

132: mov.w #H'0001,R1
133: ferases02:
134: bsr erases:16 ; Multiple-block erase subroutine
135: ; R0 Erase target block
136: ; R1 Erase count
137: bsr erasevf:16 ; Erase-verify subrutine
138: ; R0 Erase target block/unerased block
139: tst.b R0
140: beq ferases03 ; If all erasing completed, go to re-erase
141: add.w #H'01,R1
142: cmp.w #MAXET,R1
143: bls ferases02 ; If erase count ≤ max rease count, go to end
144: ferases03:
145: ;
146: mov.w R0,R1 ; Set NG block in R1
147: tst.w R0 ; Are there unerased blocks
148: beq ferases04 ; If so,
149: mov.w #H'0001,R0 ; return code = error code
150: ferases04:
151: ;
152: ; ldm @sp+,(R2-R5) ; Restore used registers
154: ;
155: ;
156: ;*********************************************************************
157: ;* erases SUB *
158: ;* Flash memory multiple-block erase (SUB) *
159: ;*********************************************************************
160: .align 2
161: erases: .equ $
162: ; Arguments R0 Erase target block
163: ; R1 Erase count (not used at present)
165: ; R2 Block bit number
166: ; R3 Wait loop count 1
167: ; R4 Wait loop count 2
168: ;
169: clr.w R2 ;Block bit number
170: erases01:
171: btst.w R2,R0 ;R0 bit R2 number
172: beq erases07 ;If not erase target block but in EBR1
173: bset.b R2,@EBR1 ;Set target block bit in EBR1
174: ;
175: mov.w #H'A57F,@TCSR ; Set WDT
176: bset.b #d'5,@FLMCR ; Set ESU bit
177: mov.w #(d'200 * MHZ / d'8),R3
Rev. 3.0, 02/99, page 637 of 904

178: ;Set ESU wait counter
179: erases02:
180: scb/f R3,erases02 ;ESU wait (200 µs or more)
181: ;
182: ;E setting /E clearing(ERASE)
183: mov.w #((d'5000 * MHZ - d'14)/ d'18 / H'10000),R3
184: mov.w #((d'5000 * MHZ - d'14)/ d'18 & H'FFFF),R4
185: ;Set E time loop count (5.0 ms)
186: ;
187: bra erases03 ; Adjust so that scb/f jump destination is even address
188: .align H'2 ; Adjust so that scb/f jump destination is even address
189: erases03:
190: ; nop ; Adjust so that scb/f jump destination is even address
191: ; If odd, insert NOP
192: bset.b #d'1,@FLMCR ;Set E bit
193: ;Adjust so that scb/f jump destination is even address
194: erases04:
195: nop ;nop to increase wait time
196: nop ;
197: nop ;
198: nop ;
199: nop ;
200: scb/f R4,erases04
201: scb/f R3,erases04 ; Erase timr wait (5.0 ms)
202: bclr.b #d'1,@FLMCR ; Clear E bit
203: ;
204: mov.w #(d'10 * MHZ / d'8),R3
205: ; Set wait counter after clearing E
206: erases05:
207: scb/f R3,erases05 ; Wait after clearing E (10 µs or more)
208: ;
209: bclr.b #d'5,@FLMCR ;Clear ESU bit
210: mov.w #(d'10 * MHZ / d'8),R3
211: ; Set wait counter after clearing ESU
212: erases06:
213: scb/f R3,erases06 ;ESU wait(10µs or more)
214: mov.w #H'A500,@TCSR ;Stop WDT
215: clr.b @EBR1 ; Clear erase target block
216: ;
217: erases07:
218: add.w #H'01,R2 ;Block bit number +1
219: cmp.w #d'7,R2 ;
220: bls erases01 ;If end of all blocks(0 to 7) end
221: ;
222: ldm @sp+,(R2-R4) ;Restore used registers
223: rts ;
Rev. 3.0, 02/99, page 638 of 904

224: ;
225: ;
226: ;*********************************************************************
227: ;* erasevf SUB *
228: ;* Erase-verify (SUB) *
229: ;*********************************************************************
230: .align H'2
231: erasevf: .equ $
232: ; Arguments @EBR Erase target block/unerased block
236: ; R4 Verify address
239: ;
240: bset.b #d'3,@FLMCR ; Set EV bit
241: mov.w #(d'20 * MHZ / d'8),R5
242: ; Set EV wait loop counter
243: erasevf01:
244: scb/f R5,erasevf01 ;EV wait(20µs or more)
245: ;
246: mov.w #RAMSTR,R2 ; RAM program start
247: add.w #blockadr,R2 ; + block table relative address
248: sub.w #prog_start,R2 ; - transfer program start address
249: ; -> block table start address
250: clr.w R3 ; Target block bit number =0
251: erasevf02:
252: btst.w R3,R0
253: beq erasevf07 ;If R0 R3 bit=B'1, execute the following
254: mov.w @R2,R4
257: erasevf03:
258: mov.w #H'FFFF,@R4 ; Dummy write (address latch)
259: mov.w #(d'2 * MHZ / d'8),R5
260: ;Set loop counter for wait after latch
261: erasevf04:
262: scb/f R5,erasevf04 ;Wait after latch(3µs or more)
263: ;
264: cmp.w #H'FFFF,@R4 ; Verify
265: bne erasevf06 ; If target address is unerased, end
266: cmp.w @(H'04,R2),R4
267: bhs erasevf05 ; If R4 >= block end ADR, end
268: add.w #H'02,R4 ;R4 = R4 + 2
269: bra erasevf03 ;
Rev. 3.0, 02/99, page 639 of 904

270: erasevf05:
271: bclr.w R3,R0 ; Clear R0(EBR1) target block bit
272: erasevf06:
273: ;
274: erasevf07:
276: ;
277: add.w #H'01,R3
278: cmp.b #H'07,R3
279: bls erasevf02 ; ; If target block bit number > 7, end
280: ;
281: bclr.b #d'3,@FLMCR ; Clear EV bit
282: mov.w #(d'5 * MHZ / d'8),R5
283: ; Set post-EV-clearing wait loop counter
284: erasevf08:
285: scb/f R5,erasevf08 ; Wait after clearing (5µs or more)
286: ;
287: ldc.b @sp+,ep ; Restore used page registers
290: ;
291: ;
292: ;*********************************************************************
293: ;* blockadr DATA *
294: ;* *
295: ;*********************************************************************
296: .align H'2
297: blockadr: .equ $
298: .data.w H'0001,H'0000,H'03FE ;EB0
299: .data.w H'0001,H'0400,H'07FE ;EB1
300: .data.w H'0001,H'0800,H'0BFE ;EB2
301: .data.w H'0001,H'0C00,H'0FFE ;EB3
302: .data.w H'0001,H'1000,H'7FFE ;EB4
303: .data.w H'0001,H'8000,H'FFFE ;EB5
304: .data.w H'0002,H'0000,H'7FFE ;EB6
305: .data.w H'0002,H'8000,H'FFFE ;EB7
306: ;
307: ;*********************************************************************
308: ;
309: ;
310: ;
311: ;
312: prog_stop: .equ $ ; End of program transfer to RAM
313: ;
314: ;
315: .end
Rev. 3.0, 02/99, page 640 of 904

316:
Notes: 1. The sample programs in this manual are provided to illustrate programming/erasing of
flash memory incorporated in an MCU. They do not make provisions for various kinds
of applications, and cannot be used as they are. They are intended solely for reference
in program development.
2. Program operation must be confirmed in actual use.
3. These programs are subject to change without notice due to improvements, etc.
Rev. 3.0, 02/99, page 641 of 904

20.4.7 Protection Modes
There are two modes for flash memory program/erase protection: hardware protection and
software protection. These protection modes are described below.
(1) Software Protection With software protection, setting the P or E bit in the flash memory
control register (FLMCR) does not cause a transition to program mode or erase mode.
Details of software protection are given below.
Function
1
Item Description Program Erase Verify*
Block Erase protection can be set for possible Not possible possible
specification individual blocks by settings in the
protection erase block register (EBR1).
However, protection against
programming is disabled. Setting
EBR1 to H'00 places all blocks in the
erase-protected state.
3
Emulation Setting the OVLPE bit in the flash Not possible Not possible* possible
2
protection* memory emulation register (FLMER)
enables program/erase protection for
all blocks.
Notes: 1. Two modes: program-verify and erase-verify.
2. Excluding a RAM area overlapping flash memory.
3. All blocks are unerasable and block-by-block specification is not possible.
Rev. 3.0, 02/99, page 642 of 904

(2) Hardware Protection Hardware protection refers to a state in which programming/erasing of
flash memory is forcibly aborted or disabled. At this time, the flash memory control register
(FLMCR) and erase block register (EBR1) settings are cleared. In the case of error protection, the
P bit and E bit can be set, but a transition is not made to program mode or erase mode.
Details of the hardware protection state are given below.
Function
1
Item Description Program Erase Verify*
2
FWE pin When a high level is not being Not possible Not possible* Not possible
protection applied to the FWE pin, FLMCR and
EBR1 are initialized, and the
program/erase-protected state is
3
entered.*
2
Reset/standby In a reset (including a watchdog timer Not possible Not possible* Not possible
protection reset) and in standby mode, FLMCR
and EBR1 are initialized, and the
program/erase-protected state is
entered. In a reset via the 5(6 pin,
the reset state is not reliably entered
unless the 5(6 pin is held low for at
least 20 ms (oscillation settling time)
after powering on . In the case of a
reset during operation, the 5(6 pin
must be held low for a minimum of 20
4
system clock cycles (20φ).*
2
Error If abnormal MCU operation is Not possible Not possible* Not possible
protection detected during flash memory
programming or erasing (error
occurrence: FLER = 1), error
protection is enabled. FLMCR and
EBR1 settings are retained but
programming/erasing is aborted at
the point at which the error occurred.
Error protection is released only by a
5(6 pin reset* and in hardware
5
standby mode.
Notes: 1. Two modes: program-verify and erase-verify.
2. All blocks are unerasable and block-by-block specification is not possible.
3. For details, see section 20.7, Flash Memory Programming and Erasing Precautions.
4. See section 4.2.2, Reset Sequence, and section 20.7, Flash Memory Programming and
Erasing Precautions. The reset period during operation is a minimum of 6 system clock
cycles for the H8/538F and H8/539F, but a minimum of 20 system clock cycles for the
H8/539F S-mask and A-mask models.
5. In the H8/538F, a watchdog timer reset is included in the FLER bit clearing conditions,
but only 5(6 pin reset input is applicable in the case of the H8/539F.
Rev. 3.0, 02/99, page 643 of 904

1
Error Protection A flash memory error is detected (the FLER bit is set in FLMSR* ) when
abnormal MCU operation (operation not in accordance with the program/erase algorithm) occurs
3
during flash memory programming or erasing (when the P or E bit is set in FLMCR* ). Flash
memory then enters the error protection state (this indicates the flash memory operating status and
does not affect the operation of the MCU).
2
In this state, FLMCR and EBR1 settings* are retained, but program mode or erase mode is
aborted at the point at which the error occurred. Program mode or erase mode cannot be entered
by re-setting the P or E bit in FLMCR. However, PV and EV bit setting is enabled, and a
transition can be made to verify mode.
The error protection state is released only by a 5(6 pin reset and in hardware standby mode.
Notes: 1. For details of FLER bit setting conditions, see section 20.2.3, RAM Control Register
(RAMCR).
2. FLMCR and EBR1 can be written to. However, registers will be initialized if a
transition is made to software standby mode in the error protection state.
3. Note that NMI input is disabled when the P or E bit is set. For details see section
20.4.8, NMI Input Disabling Conditions.
Memory read
verify mode Reset or hardware standby or
software standby
RD VF PR ER
FLER = 0
Reset release and Reset or standby
hardware standby release and (hardware protection)
P = 1 or E = 1 P = 0 and E = 0 software standby release
RD VF PR ER
Reset or INIT
hardware standby FLER = 0
Program mode Reset or

Erase mode hardware standby
Reset or
RD VF PR ER Error occurrence
hardware standby
FLER = 0 (software standby)
Error occurrence Error protection mode

(software standby)
RD: Memory read possible Software RD VF PR ER
VF: Verify-read possible standby INIT
Error protection mode
PR: Programming possible FLER = 1
ER: Erasing possible RD VF
RD: Memory read not possible FLER = 1 Software standby
VF: Verify-read not possible release
PR: Programming not possible
ER: Erasing not possible
INIT: Register (FLMCR, EBR1, EBR2) initialization state
Figure 20-11 Flash Memory State Transitions

(Modes 4 and 7 (on-chip ROM enabled), high level applied to FWE pin)
Rev. 3.0, 02/99, page 644 of 904
The error protection mode is provided to prevent damage to the flash memory due to
overprogramming or overerasing by detecting MCU runaway or abnormal operation not in
accordance with the program/erase algorithm during flash memory programming or erasing,
However, the error protection function is invalid for abnormal operations other than the FLER bit
setting conditions. Also, if a certain time has elapsed before this protection state is entered,
damage may already have been caused to the flash memory. Consequently, this function cannot
provide complete protection against damage to flash memory.
To prevent such abnormal operations, therefore, it is necessary to ensure correct operation in

accordance with the program/erase algorithm, with the flash write enable (FWE) voltage applied,
and to conduct constant monitoring for MCU errors, internally and externally, using the watchdog
timer or other means. There may also be cases where the flash memory is in an erroneous
programming or erroneous erasing state at the point of transition to this protection mode, or where
programming or erasing is not properly carried out because of an abort. In cases such as these, a
forced recovery (program rewrite) must be executed using boot mode. However, it may also
happen that boot mode cannot be normally initiated because of overprogramming or overerasing.
20.4.8 NMI Input Disabling Conditions
NMI input is disabled when flash memory is being programmed or erased (while the P or E bit is
set in FLMCR) and while the boot program is executing in boot mode (until a branch is made to
1
the on-chip RAM area* ), to give priority to the program or erase operation. There are three
reasons for this:
1. NMI input during programming or erasing might cause a violation of the programming or
erasing algorithm, with the result that normal operation could not be assured.
2. In the NMI exception handling sequence during programming or erasing, the vector would not
2
be read correctly* , possibly resulting in MCU runaway.
3. If NMI input occurred during boot program execution, it would not be possible to execute the
normal boot mode sequence.
For these reasons, in the H8/539F's on-board programming modes alone there are conditions for
disabling NMI input, as an exception to the general rule. However, this provision does not
guarantee normal erasing and programming or MCU operation. All requests, including NMI,
must therefore be restricted inside and outside the MCU during FWE application. NMI input is
also disabled in the error protection state and while the P or E bit remains set in FLMCR during
flash memory emulation in RAM.
Rev. 3.0, 02/99, page 645 of 904

Notes: 1. This is the interval until a branch is made to the boot program area (H'EE80H'F37F)
in the on-chip RAM. (This branch takes place immediately after transfer of the user
program is completed.) Consequently, after the branch to the RAM area, NMI input is
enabled except during programming and erasing. Interrupt requests must therefore be
disabled inside and outside the MCU until the user program has completed initial
programming (including the vector table and the NMI interrupt handling routine).
2. The vector may not be read correctly in this case for the following two reasons:
a. If flash memory is read while being programmed or erased (while the P or E bit
is set in FLMCR), correct read data will not be obtained (undetermined values
will be returned).
b. If the NMI entry in the vector table has not been programmed yet, NMI
exception handling will not be executed correctly.
Rev. 3.0, 02/99, page 646 of 904

20.5 Flash Memory Emulation in RAM
As flash memory programming and erasing takes time, it may be difficult to carry out tuning by
writing parameters and other data in real time. In this case, real-time programming of flash
memory can be emulated by overlapping an actual RAM area onto a small block area in flash
memory (H'0000H'0FFF).
This RAM area overlapping is executed by means of bits 7, 3, and 2 in the flash memory
emulation register (FLMER) and bits 2 and 1 in the RAM control register (RAMCR). After RAM
overlapping, access is possible both from the area overlapped onto flash memory (mapping RAM
area) and from the original RAM area (actual RAM area).
Bits 7, 3, and 2 in FLMER and bits 2 and 1 in RAMCR are valid in modes 2, 4, and 7. Flash
memory programming must not be performed in mode 2. In other modes, a read will always
return 0 and RAM area overlapping cannot be carried out. When the flash memory emulation
function is used, RAMCR bits 7 and 5 should both be set (RAME1 = 1 and RAME2 = 1). The
mapping RAM area setting method is shown in tables 20-9 and 20-10.
Flash Memory Emulation Register (FLMER)
Bit 7 6 5 4 3 2 1 0
OVLPE − − − A11E A10E − −
R/W R/W − − − R/W R/W − −
Rev. 3.0, 02/99, page 647 of 904


ROM Area Register
Bit 2* Bit 1*
(Mapping RAM Bit 7* Overlap Program/Erase
Area) Function Protection
OVLPE RAM2 RAM1
− 0 0/1 0/1 Disabled Disabled
H'0800−H'0BFF 1 1 0 Enabled Enabled
H'0C00−H'0FFF 1 1 1 Enabled Enabled
Note: * Bits 7, 3, and 2 of the flash memory emulation register (FLMER) and bits 2 and 1 of the
RAM control register (RAMCR) are writeable in mode 2, 4, or 7. (In the H8/538F is was
necessary to apply 12 V to the program voltage pin VPP in order to perform RAM emulation,
but in the H8/539F RAM emulation is possible regardless of the VPP voltage. The H8/539F
(S-mask model) has a single 5 V power source and no VPP pin. The H8/539F (S-mask
model) supports RAM emulation in mode 2, 4, or 7 (on-chip flash memory enabled), as
does the H8/539F. Do not program the flash memory in mode 2.
2

2
ROM Area * 1 1 1 1
Bit 3* Bit 2* Bit 7* Bit 5*
(Mapping RAM
Area) A11E A10E RAME1 RAME2
H'F000−H'F3FF 0 0 1 1
(1024 bytes)
H'F400−H'F7FF 0 1 1 1
(1024 bytes)
H'F800−H'FBFF 1 0 1 1
(1024 bytes)
3
Use prohibited* 1 1 1 1
4
4
4
Rev. 3.0, 02/99, page 648 of 904

Notes: 1. Bits 7, 3, and 2 of the flash memory emulation register (FLMER) and bits 2 and 1 of the
S-mask and A-mask models can perform RAM emulation in modes 2, 4, and 7 (on-chip
flash memory enabled).)
3. Use prohibited when A11E and A10E are both set to 1. (When A11E and A10E are
both set to 1, the state is the same as when A11E is 1 and A10E is 0.)
4. Use prohibited when RAME1 = 0 or RAME2 = 0. (Can only be used when RAME1 =
RAME2 = 1.)
Rev. 3.0, 02/99, page 649 of 904

Example of Emulation of Real-Time Flash Memory Programming
In the following example, RAM area H'F000 to H'F3FF is overlapped onto flash memory area
EB2 (H'0800 to H'0BFF).
H'0000 Procedure: 1. Part of RAM (H'F000−H'F3FF) is

overlapped onto the area (EB2)
requiring real-time programming.
(RAMCR bits 2 and 1 are set to 1, 0,
Block and the flash memory area to be
area overlapped (EB2) is selected.) Bit 7
Flash memory of FLMER is cleared to 0. Next, bits
space 7, 3, and 2 of FLMER are set to 1, 0,
0, and the RAM area to be used for
overlapping is selected.
RAM overlapping begins as soon as
FLMER bit 7 (OVLPE) is set.
2. Real-time programming is performed
Overlapping RAM using the overlapping RAM.
H'0800 3. The programmed data is checked,
* Mapping RAM area
EB2 area H'0BFF then RAM overlapping is cleared (the
H'0FFF OVLPE bit is cleared.)
4. The data written in RAM area
H'EE80 H'F000−H'F3FF is written to flash
memory space.
Note: * When part of RAM (H'F000−H'F3FF) is
H'F000
overlapped onto a flash memory small
(Actual RAM area)
H'F3FF block area, the flash memory in the
H'F400 overlapped area cannot be accessed. It
can be accessed by clearing the overlap.
On-chip RAM
area
H'FE7F
Figure 20-12 Example of RAM Overlap Operation
Rev. 3.0, 02/99, page 650 of 904

Notes on Use of Emulation in RAM
(1) Notes on emulation RAM access
*2
00000
*1 16 kbytes
Flash memory 03FFF
04000
Mapping area *1
Page 0
0EE80
*2
0FE7F
Area used
RAM
in RAM emulation *2
ROM :00000 to 00FFF
RAM:0F000 to 0FBFF
10000
(16 kbytes) *1
Flash memory 13FFF
14000
Page 1 64 kbytes
(48 kbytes)
Flash memory
1FFFF
20000
Page 2 Flash memory 64 kbytes
2FFFF
Notes: 1. Areas 00000 to 03FFF and 10000 to 13FFF are mapping areas. They can be accessed from both page 0 and
page 1.
2. When the RAM emulation function is used and RAM is overlapped onto a ROM area, the overlapped page 0
RAM area is not mapped onto page 1. (RAM emulation can only be used in page 0.) In this case, ROM
contents can be read by accessing page 1.
Figure 20-13 Notes on Emulation RAM Access
Rev. 3.0, 02/99, page 651 of 904

(2) Flash write enable (FWE) application and releasing
As in on-board program mode, care is required when applying and releasing FWE to prevent
erroneous programming or erasing. To prevent erroneous programming and erasing due to
program runaway during FWE application, in particular, the watchdog timer should be set when
the P or E bit is set in the flash memory control register (FLMCR), even while the emulation
function is being used. For details, see section 20.7, Flash Memory Programming and Erasing
Precautions.
(3) NMI input disabling conditions
When the emulation function is used, NMI input is disabled when the P bit or E bit is set to 1 in
FLMCR, in the same way as with normal programming and erasing.
The P and E bits are cleared by a reset (including a watchdog timer reset), in standby mode, when
a high level is not being input to the FWE pin, or when the SWE bit in FLMCR is 0 while a high
level is being applied to the FWE pin.
Rev. 3.0, 02/99, page 652 of 904

20.6 PROM Mode
20.6.1 PROM Mode Setting
The H8/539F S-mask and A-mask models, in which the on-chip ROM is flash memory, have a
PROM mode as well as the on-board programming modes for programming and erasing flash
memory. In PROM mode, the on-chip ROM can be freely programmed using a PROM
programmer that supports Hitachi microcomputer device types with 128-kbyte on-chip flash
memory.
PROM mode requires the use of the socket adapter shown in table 20-11. For notes on the use of
PROM mode, see section 20.6.9, Notes on Memory Programming, and section 20.7, Flash
Memory Programming and Erasing Precautions.
20.6.2 Socket Adapter and Memory Map
For program writing and verification, a special-purpose 112-to-32-pin adapter is mounted on the
PROM programmer. The socket adapter product code is given in table 20-11.
Figure 20-15 shows the memory map in PROM mode.
Table 20-11 Socket Adapter Product Code
Socket Adapter
Product Code Package Product Code Device Type
HD64F5389FS 112-pin plastic QFP (FP-112) HS538FESH01H* Hitachi microcomputer with
128-kbyte on-chip flash
memory
Note: * The same socket adapter is used for the H8/539F dual power source model, but the Hitachi
128-kbyte on-chip flash memory microcomputer device type must be selected. Selecting
HN28F101 may cause permanent damage to the chip.
Rev. 3.0, 02/99, page 653 of 904

MCU mode H8/539F PROM mode
H8/539F
H'00000 H'00000
On-chip ROM area
H'03FFF H'03FFF
H'10000
On-chip ROM area

H'13FFF
On-chip ROM area H'1FFFF
H'2FFFF
Figure 20-14 Memory Map in PROM Mode
Note: An appropriate tool should be used to insert the adapter into, and remove it from, the IC
socket. A sample tool is shown in table 20-12.
Table 20-12 Sample Tool
Manufacturer Model
ENPLAS Corporation HP-100 (vacuum pen)
20.6.3 PROM Mode Operation
The PROM mode program/erase/verify specifications are the Hitachi 128-kbyte on-chip flash
memory microcomputer device type specifications.
Table 20-13 shows how the different operating modes are set when using PROM mode, and table
20-14 lists the commands used in PROM mode. Details of each mode are given below.
Memory Read Mode

Memory read mode supports byte reads.
Auto-Program Mode
Auto-program mode supports programming of 128 bytes at a time. Status polling is used to
confirm the end of auto-programming.
Auto-Erase Mode
Auto-erase mode supports automatic erasing of the entire flash memory. Status polling is used to
confirm the end of auto-erasing.
Rev. 3.0, 02/99, page 654 of 904

Status Read Mode
Status polling is used for auto-programming and auto-erasing, and normal termination can be
confirmed by reading the I/O6 signal. In status read mode, error information is output if an error
occurs.
Table 20-13 Settings for Operating Modes In PROM Mode
Pin Names
Mode FWE &( 2( :( D0 to D7 A0 to A17
Read VCC or 0 L L H Data output Ain
Output disable VCC or 0 L H H Hiz X
Command write VCC or 0 L H L Data input *Ain
Chip disable VCC or 0 H X X Hiz X
Legend
L: Low level
H: High level
X: Undefined
Hi-z: High impedance
Notes: 1. Chip disable is not a standby state; internally, it is an operation state.
2. *Ain indicates that there is also address input in auto-program mode.
3. For the command write when making a transition to auto-program or auto-erase mode,
set the FWE pin to VCC (V).
Table 20-14 PROM Mode Commands
1st Cycle 2nd Cycle

Command Cycles Mode Address Data Mode Address Data
Memory read mode 1 write X H'00 read RA Dout
Auto-program mode 129 write X H'40 write WA Din
Auto-erase mode 2 write X H'20 write X H'20
Status read mode 2 write X H'71 write X H'71
RA: Read address
Din: Program data
WA: Program address
Dout: Read data
Notes: 1. In auto-program mode, 129 cycles are required for command writing by a simultaneous
128-byte write.
Rev. 3.0, 02/99, page 655 of 904

Table 20-15 DC Characteristics in Memory Read Mode
(Conditions: VCC = 5.0 V ± 10%, VSS = 0 V, Ta = 25°C ± 5°C)

Input high O7 to O0, VIH 2.2  VCC + 0.3 V
voltage A16 to A0
Input low O7 to O0, VIL -0.3  0.8 V
voltage A16 to A0
Schmitt trigger 2(, &(, :( VT- 1.0  2.5 V
input voltage
VT+ 2.0  3.5 V
VT- -VT+ 0.4   V
Output high O7 to O0 VOH 2.4   V IOH = -200 µA
voltage
Output low O7 to O0 VOL   0.45 V IOL = 1.6 mA
voltage
Input leakage O7 to O0, | ILI |   2 µA Vin = 0 to VCC V
current A16 to A0
VCC current Reading ICC  40 65 mA
Programming ICC  50 85 mA
Erasing ICC  50 85 mA
Note: For the absolute maximum ratings, see section 23.1, Absolute Maximum Ratings (H8/539F
S-Mask model).
Exceeding the absolute maximum ratings may cause permanent damage to the chip.
20.6.4 Memory Read Mode
Table 20-16 shows the AC characteristics in a transition to memory read mode.
Figure 20-16 shows the timing waveforms in a transition to memory read mode.
Table 20-17 shows the AC characteristics in a memory contents read.
Figures 20-17 and 20-18 show the timing waveforms in a memory contents read.
Table 20-18 shows the AC characteristics in a transition from memory read mode to another
mode.
Figure 20-19 shows the timing waveforms in a transition from memory read mode to another
mode.
Rev. 3.0, 02/99, page 656 of 904

Table 20-16 AC Characteristics in Memory Read Mode Transition
(Conditions: VCC = 5.0 V ±10%, VSS = 0 V, Ta = 25°C ±5°C)
Item Symbol Min Max Unit Notes

Command write cycle tnxtc 20  µs
&( hold time tceh 0  ns
&( setup time tces 0  ns
Data hold time tdh 50  ns
Data setup time tds 50  ns
Write pulse width twep 70  ns
:( rise time tr  30 ns
:( fall time tf  30 ns
Command write Read mode

ADDRESS ADDRESS STABLE
twep tceh
CE
tnxtc
OE
tces
WE
tf tr
DATA DATA DATA
tdh
tds VCC = 5.0 V ±10%
Note: Command data is latched on the rising edge of WE.
Figure 20-15 Timing Waveforms for Memory Read Mode Transition
Rev. 3.0, 02/99, page 657 of 904

Table 20-17 AC Characteristics in Memory Contents Read

Access time tacc  20 µs
&( output delay time tce  150 ns
2( output delay time toe  150 ns
Output disable delay time tdf  100 ns
Data output hold time toh 5  ns
ADDRESS ADDRESS STABLE ADDRESS STABLE
CE VIL
tacc
OE VIL
WE VIH
tacc toh toh
DATA
DATA DATA
VCC = 5.0 V ±10%
Figure 20-16 &(,

&( 2( Enable State Read
ADDRESS ADDRESS STABLE ADDRESS STABLE
tce tce
CE
OE
toe toe
WE tacc
tacc tdf tdf VIH
DATA DATA DATA
toh toh
VCC = 5.0 V ±10%
Figure 20-17 &(,

&( 2( Clocked Read
Rev. 3.0, 02/99, page 658 of 904

Table 20-18 AC Characteristics in Transition from Memory Read Mode to Another Mode

Dta setup time tds 50  ns
xx mode command write

CE
twep tceh
OE
tnxtc tces
WE
tf tr
DATA DATA H'XX
tdh
tds
Note: Do not enable WE and OE simultaneously. VCC = 5.0 V ±10%
Figure 20-18 Transition from Memory Read Mode to Another Mode
Rev. 3.0, 02/99, page 659 of 904

20.6.5 Auto-Program Mode
Table 20-19 shows the AC characteristics in auto-program mode.
Figure 20-20 shows the timing waveforms in auto-program mode
Table 20-19 AC Characteristics in Auto-Program Mode

Status polling start time twsts 1  ms
Status polling access time tspa  150 ns
Address setup time tas 0  ns
Address hold time tah 60  ns
Memory write time twrite 1 3000 ms
Write setup time tpns 100  ns
Write end setup time tpnh 100  ns
Rev. 3.0, 02/99, page 660 of 904

FWE
tpns tpnh
CE tas tah
tceh
OE tnxtc
tnxtc
twep
WE Data transfer
tces
1 byte 128byte twsts tspa
twrite(1 to 3000msec)
Programming operation
tf tr end identification signal
I/O7
tds tdh
Programming normal
end identification signal
I/O6
Programming wait
DATA H'40 DATA DATA I/O0 to 5=0
VCC = 5.0 V ±10%
Figure 20-19 Auto-Program Mode Timing Waveforms
Notes on Use of Auto-Program Mode
(1) In auto-program mode, 128 bytes are programmed simultaneously. This should be carried out
by executing 128 consecutive byte transfers.
(2) A 128-byte data transfer is necessary even when programming fewer than 128 bytes. In this
case, H'FF data must be written to the extra addresses.
(3) If a value other than an effective address is input, processing will switch to a memory write
operation but a write error will be flagged.
(4) Memory address transfer is performed in the second cycle (figure 20-20). Do not perform
transfer after the second cycle.
(5) Do not perform a command write during a programming operation.
(6) Perform one auto-programming operation for a 128-byte block for each address.
Characteristics are not guaranteed for two or more programming operations.
(7) Confirm normal end of auto-programming by checking I/O6. Alternatively, status read mode
can also be used for this purpose.
Rev. 3.0, 02/99, page 661 of 904

20.6.6 Auto-Erase Mode
Table 20-20 shows the AC characteristics in auto-erase mode.
Figure 20-21 shows the timing waveforms in auto-erase mode.
Table 20-20 AC Characteristics in Auto-Erase Mode

Status polling start time tests 1  ms
Status polling access time tspa  150 ns
Memory write time terase 100 40000 ms
Write setup time tens 100  ns
Write end setup time tenh 100  ns
Rev. 3.0, 02/99, page 662 of 904

FWE
tens tenh
ADDRESS
tces tceh
CE
OE tnxtc tnxtc tspa
twep
WE
terase(100 to 40000msec) tnxtc
tf tr
tds
Erase end
identification signal
I/O7 tdh
Erase normal end

confirmation signal
I/O6
DATA H'20 H'20 I/O0 to 5=0
VCC = 5.0 V ±10%
Figure 20-20 Auto-Erase Mode Timing Waveforms
Notes on Use of Auto-Erase Mode
(1) Auto-erase mode supports only total memory erasing.

(2) Do not perform a command write during auto-erasing.
(3) Confirm normal end of auto-erasing by checking I/O6. Alternatively, status read mode can
also be used for this purpose.
Rev. 3.0, 02/99, page 663 of 904

20.6.7 Status Read Mode
Table 20-21 shows the AC characteristics in status read mode.
Figure 20-22 shows the timing waveforms in status read mode.
Table 20-22 shows status read mode return codes.
Table 20-21 AC Characteristics in Status Read Mode

2( output delay time toe  150 ns
Disable delay time tdf  100 ns
&( output delay time tce  150 ns
ADDRESS
CE
tce tnxtc
OE tnxtc tnxtc
twep twep
WE tces tceh tces tceh toe tdf
tf tr tf tr
tds tdh tds tdh
DATA H'71 H'71 DATA
VCC = 5.0 V ±10%
Figure 20-21 Status Read Mode Timing Waveforms

Rev. 3.0, 02/99, page 664 of 904
Table 20-22 Status Read Mode Return Codes
Pin Name I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0
Attribute Normal end Command Programming Erase error   Programming Effective

identification error error or erase count address error
exceeded
Indications Normal end: 0 Command Programming Erase   Count Effective

Abnormal end: 1 error: 1 error: 1 error: 1 exceeded: 1 address error: 1
Otherwise: 0 Otherwise: 0 Otherwise: 0 Otherwise: 0 Otherwise: 0
Note on Use of Status Read Mode
After exiting auto-program mode or auto-erase mode, status read mode must be executed without
dropping the power supply.
The return code is undefined immediately after powering on, or if the power supply is dropped.
20.6.8 PROM Mode Transition Time
Commands cannot be accepted during the oscillation settling period or the PROM mode setup
period. A transition is made to memory read mode after the PROM mode setup time.
Table 20-23 Stipulated Transition Times to Command Wait State

Standby release (oscillation toscl 20  msec
setting time)
PROM mode setup time tbmv 10  msec
VCC hold time tdwn 0  msec
Rev. 3.0, 02/99, page 665 of 904

VCC
toscl tbmv tdwn
Memory read mode Auto-program mode Command wait state

Command wait state Auto-erase mode Nomal/abnormal Don't Care
RES
end determination
Don't Care
FWE
Note: The FWE input pin level should be set to VCC. When not performing auto-programing or auto-erasing, drive the FWE pin low.
Figure 20-22 Oscillation Settling Time and Boot Program Transfer Time
20.6.9 Notes on Memory Programming
(1) When programming addresses which have previously been programmed, carry out auto-
erasing before auto-programming.
Programming of previously
programmed addresses
Auto-erase (whole chip)
Auto-program
End
Figure 20-23 Programming of Previously Programmed Addresses
(2) When performing programming using a PROM programmer on a chip that has been
programmed/erased in an on-board programming mode, auto-erasing is recommended before
carrying out auto-programming.
Notes: 1. The memory is initially in the erased state when the device is shipped by Hitachi. For
other chips for which the erasure history is unknown, it is recommended that auto-
erasing be executed to check and supplement the initialization (erase) level.
2. In PROM mode, auto-programming should be performed once only on a 128-byte
programming unit block. Additional programming cannot be performed on a
Rev. 3.0, 02/99, page 666 of 904
previously programmed 128-byte programming unit block. Programming should be
carried out using auto-programming after an auto-erase.
20.7 Flash Memory Programming and Erasing Precautions

Precautions concerning the use of on-board programming mode, the RAM emulation function, and
PROM mode are summarized below.
(1) Use the specified voltages and timing for programming and erasing. Applied voltages in
excess of the rating can permanently damage the device. Note, in particular, that the maximum
ratings for the FWE pin and the VPP and MD2 pins are different for the H8/539F S-mask and A-
mask models (single power source) and the H8/539F (dual power source).
Use a PROM programmer that supports the Hitachi microcomputer device type with 128-kbyte
on-chip flash memory.
Do not select the HN28F101 setting for the PROM programmer. An incorrect setting will result in
application of 12.0 V to the FWE pin, damaging the device.
(2) Powering on and off (see figures 20-25 to 20-27) Do not apply a high level to the FWE pin
until VCC has stabilized. Also, drive the FWE pin low before turning off VCC.
When applying or disconnecting VCC power, fix the FWE pin low and place the flash memory in
the hardware protection state.
The power-on and power-off timing requirements should also be satisfied in the event of a power
failure and subsequent recovery. Failure to do so may result in overprogramming or overerasing
due to MCU runaway, and loss of normal memory cell operation.
(3) FWE application/disconnection (see figures 20-25 to 20-27) FWE application should be
carried out when MCU operation is in a stable condition. If MCU operation is not stable, fix the
FWE pin low and set the protection state.
The following points must be observed concerning FWE application and disconnection to prevent
unintentional programming or erasing of flash memory:
• Apply FWE when the VCC voltage has stabilized within its rated voltage range.
If FWE is applied when the MCU's VCC power supply is not within its rated voltage range (VCC
= 4.5 V to 5.5 V), MCU operation will be unstable and flash memory may be erroneously
programmed or erased.
• Apply FWE when oscillation has stabilized (after the elapse of the oscillation settling time).
When VCC power is turned on, hold the 5(6 pin low for the duration of the oscillation settling
time (tOSC1 = 20 ms) before applying FWE. Do not apply FWE when oscillation has stopped
or is unstable.
Rev. 3.0, 02/99, page 667 of 904

• In boot mode, apply and disconnect FWE during a reset.
In a transition to boot mode, FWE = 1 input and MD2 to MD0 setting should be performed
while the 5(6 input is low. FWE and MD2 to MD0 pin input must satisfy the mode
programming setup time (tMDS) with respect to the reset release timing. When making a
transition from boot mode to another mode, also, a mode programming setup time is necessary
with respect to the 5(6 release timing.
In a reset during operation, the 5(6 pin must be held low for a minimum of 20 system clock
cycles (20 φ).
• In user program mode, FWE can be switched between high and low level regardless of 5(6
input.
FWE input can also be switched during execution of a program in flash memory.
• Do not apply FWE if program runaway has occurred.
During FWE application, the program execution state must be monitored using the watchdog
timer or some other means.
• Disconnect FWE only when the SWE, ESU, PSU, EV, PV, E, and P bits in FLMCR are
cleared.
Make sure that the SWE, ESU, PSU, EV, PV, E, and P bits are not set by mistake when
applying or disconnecting FWE.
(4) Do not apply a constant high level to the FWE pin. To prevent erroneous programming or
erasing due to program runaway, etc., apply a high level to the FWE pin only when programming
or erasing flash memory (including execution of flash memory emulation using RAM). A system
configuration in which a high level is constantly applied to the FWE pin should be avoided. Also,
while a high level is applied to the FWE pin, the watchdog timer should be activated to prevent
overprogramming or overerasing due to program runaway, etc.
(5) Use the recommended algorithm when programming and erasing flash memory. The
recommended algorithm enables programming and erasing to be carried out without subjecting the
device to voltage stress or sacrificing program data reliability. When setting the program (P) or
erase (E) bit in FLMCR, the watchdog timer should be set beforehand as a precaution against
program runaway, etc.
(6) Do not set or clear the SWE bit during execution of a program in flash memory. Clear
the SWE bit before executing a program or reading data in flash memory. When the SWE bit is
set, data in flash memory can be rewritten, but flash memory should only be accessed for verify
operations (verification during programming/erasing).
Similarly, when using the RAM emulation function while a high level is being input to the FWE
pin, the SWE bit must be cleared before executing a program or reading data in flash memory.
However, the RAM area overlapping flash memory space can be read and written to regardless of
whether the SWE bit is set or cleared.
Rev. 3.0, 02/99, page 668 of 904

(7) Do not use interrupts while flash memory is being programmed or erased. All interrupt
requests, including NMI, should be disabled during FWE application to give priority to
program/erase operations (including emulation in RAM).
(8) Do not perform additional programming. Erase the memory before reprogramming. In on-
board programming, perform only one programming operation on a 32-byte programming unit
block. In PROM mode, too, perform only one programming operation on a 128-byte
programming unit block. Programming should be carried out with the entire programming unit
block erased.
(9) Before programming, check that the chip is correctly mounted in the PROM
programmer. Overcurrent damage to the device can result if the index marks on the PROM
programmer socket, socket adapter, and chip are not correctly aligned.
(10) Do not touch the socket adapter or chip during programming. Touching either of these
can cause contact faults and write errors.
Programming/
Wait time: x erasing possible
φ
tOSC1 min 0 µs
4.5 V
VCC 4.5 V
FWE
tMDS
min 0 µs
*1
MD2 to 0
tMDS
RES
SWE set
SWE cleared
SWE bit

(x: Wait time after setting SWE bit *2)
Period during which flash memory can be programed
Notes: 1. Except when swiching modes, the level of the mode pins (MD2 to MD0) must be fixed from
power-on until power-off by pulling the pins up or down.
2. See "Flash Memory Characteristics" in sections 23 and 24, Electrical Characteristics.
Figure 20-24 Power-On/Off Timing (Boot Mode)
Rev. 3.0, 02/99, page 669 of 904

Programming/
Wait time: x erasing possible
φ
tOSC1 min 0 µs
4.5 V 4.5 V
VCC
FWE
*1
MD2 to 0
tMDS
RES
SWE set
SWE cleared
SWE bit

Notes: 1. Except when swiching modes, the level of the mode pins (MD2 to MD0) must be fixed from
power -on until power-off by pulling the pins up or down.
Figure 20-25 Power-On/Off Timing (User Program Mode)
Rev. 3.0, 02/99, page 670 of 904

Programming/ Programming/ Programming/ Programming/
erasing erasing erasing erasing
Wait time: x possible Wait time: x possible Wait time: x possible Wait time: x possible
φ
tOSC1
VCC 4.5 V
min 0 µs
FWE
tMDS *2
tMDS
MD2 to 0
tMDS
tRESW
RES
SWE set SWE

cleared
FWE bit
Mode change*1 Boot mode Mode User User program mode User User
change*1 mode mode program
mode

Notes: 1. When entering boot mode or making a transition from boot mode to another mode, mode
switching must be carried out by means of RES input. The state of ports with multiplexed
address functions and bus control output pins (AS, RD, HWR, LWR) will change during this
switchover interval (the interval during which the RES pin input is low), and therefore these pins
should not be used as output signals during this time.
2. When making a transition from boot mode to another mode, the mode programming setup time
tMDS must be satisfied with respect to RES clearance timing.
Figure 20-26 Mode Transition Timing

(Example: Boot Mode => User Mode <=> User Program Mode)
Rev. 3.0, 02/99, page 671 of 904

Section 21 Power-Down State
21.1 Overview
TheH8/539F has a power-down state that greatly reduces power consumption by halting CPU
functions. The power-down state includes three modes: sleep mode, software standby mode, and
hardware standby mode. Table 21-1 indicates the methods of entering and exiting the power-down
modes.
Table 21-1 Power-Down Mode Transition Conditions
State
Entering CPU Peripheral Exiting
Mode Procedure Clock CPU Registers Functions RAM I/O Ports Methods
Sleep Execute Active Halted Held Active Held Held • Interrupt
mode SLEEP • 5(6
instruction • 67%<
Software Set SSBY bit Halted Halted Held Halted and Held Held • NMI
standby in SBYCR to 1, initialized • 5(6
mode then execute • 67%<
SLEEP
instruction
Hardware Low input at Halted Halted Not held Halted Held High • 67%<
standby 67%< pin impedance & 5(6
mode
Legend
SBYCR: Software standby control register
SSBY: Software standby bit
21.2 Sleep Mode

This section describes sleep mode.
21.2.1 Transition to Sleep Mode
Execution of the SLEEP instruction causes a transition from the program execution state to sleep
mode. Immediately after executing the SLEEP instruction the H8/500 CPU halts, but the contents
of its internal registers remain unchanged. The on-chip peripheral modules do not halt in sleep
mode.
Rev. 3.0, 02/99, page 673 of 904

21.2.2 Exit from Sleep Mode
The chip exits sleep mode when it receives an interrupt request, or a low input at the 5(6 or
67%< pin.
(1) Exit by Interrupt: An interrupt terminates sleep mode and starts the interrupt-handling
routine or data transfer controller (DTC). The chip does not exit sleep mode if the interrupt
priority level is equal to or less than the level set in the H8/500 CPU's status register (SR), or if the
interrupt is disabled in an on-chip peripheral module.
(2) Exit by 5(6 Input: When the 5(6 signal goes low, the chip exits from sleep mode to the
reset state.
(3) Exit by 67%< Input: When the 67%< signal goes low, the chip exits from sleep mode to
hardware standby mode.
21.3 Software Standby Mode

This section describes software standby mode.
21.3.1 Transition to Software Standby Mode
If software sets the standby bit (SSBY) to 1 in the software standby control register (SBYCR),
then executes the SLEEP instruction, the chip enters software standby mode. Table 21-2 gives
register information about SBYCR.
In software standby mode current dissipation is reduced to an extremely low level because the
CPU and on-chip peripheral modules all halt. The on-chip peripheral modules are reset. As long
as the specified voltage is supplied, however, CPU register contents, on-chip RAM data, and I/O
port states are held.
Table 21-2 Standby Control Register

H'FF1A Software standby control register SBYCR R/W H'7F
Rev. 3.0, 02/99, page 674 of 904

21.3.2 Software Standby Control Register
The software standby control register (SBYCR) is an eight-bit register that must be set in order to
enter software standby mode. The bit structure is described next.
Bit 7 6 5 4 3 2 1 0
SSBY − − − − − − −
R/W R/W − − − − − − −
Reserved bits
Software standby bit

Enables transition to software standby mode
(1) Bit 7—Software Standby (SSBY): Enables transition to software standby mode.
Bit 7
SSBY Description
0 SLEEP instruction causes transition to sleep mode. (Initial value)
1 SLEEP instruction causes transition to software standby mode
The SSBY bit cannot be set to 1 while the timer enable bit (TME) is set to 1 in the timer
control/status register (TCSR) of the watchdog timer (WDT). Before entering software standby
mode, software must clear the TME bit to 0.
The SSBY bit is automatically cleared to 0 when the chip recovers from software standby mode
by NMI or reset, or enters hardware standby mode.
Rev. 3.0, 02/99, page 675 of 904

21.3.3 Exit from Software Standby Mode
The chip can be brought out of software standby mode by input at the NMI, 5(6, or 67%< pin.
(1) Recovery by NMI: To recover from software standby mode by NMI input, software must set
clock select bits 2 to 0 (CKS2 to CKS0) in the watchdog timer's timer control/status register
(TCSR) beforehand to select the oscillator setting time*, and must also select the desired NMI
input edge.
When an NMI interrupt request signal is input, the clock oscillator begins operating. At first clock
pulses are supplied only to the watchdog timer. The watchdog timer receives the supplied clock
and starts counting. After the oscillator settling time selected by bits CKS2 to CKS0 in the
control/status register (TCSR), the watchdog timer overflows. After the watchdog timer
overflows, the clock is supplied to the entire chip, software standby mode ends, and the NMI
exception-handling sequence begins.
(2) Recovery by 5(6 Input: When software standby mode is exited by 5(6 input, clock pulses
are supplied to the entire chip as soon as the clock oscillator starts. The clock oscillator starts
when the 5(6 signal goes low. After the oscillator settling time, when the 5(6 signal goes high,
the CPU begins executing the reset sequence. The 5(6 signal must be held low long enough for
the clock to stabilize.
(3) Recovery by 67%< Input: When the 67%< signal goes low, the chip exits from software
standby mode to hardware standby mode.
Note: * When using an external clock, the watchdog timer's timer control/status register (TCSR)
should be set so as to secure the external clock output settling delay time (tDEXT).
Rev. 3.0, 02/99, page 676 of 904

21.3.4 Sample Application of Software Standby Mode
Figure 21-1 illustrates NMI timing for software standby mode.
(1) With the nonmaskable interrupt edge bit (NMIEG) in the NMI control register (NMICR)
cleared to 0 (falling edge), NMI goes low.
(2) The NMIEG bit is set to 1.
(3) Software sets the SSBY bit to 1, then executes the SLEEP instruction. The chip enters
(4) When the NMI signal goes high, the chip exits software standby mode.
Clock
oscillator
(1) (4)
NMI
NMIEG
bit (2) Oscillator
settling time
SSBY (3)
bit
NMI interrupt Software standby Oscillator settling NMI interrupt

handler mode time (tOSC2) set handler
(power-down state) in WDT
NMIEG ← 1
SSBY ← 1
WDT count WDT count
SLEEP starts overflows
instruction
Clock oscillator starts
Figure 21-1 NMI Timing for Software Standby Mode (Example)
21.3.5 Note
The I/O ports are not initialized in software standby mode. If a port is in the high output state, it
remains in that state and power reduction is lessened by the amount of current output.
Rev. 3.0, 02/99, page 677 of 904

21.4 Hardware Standby Mode
This section describes hardware standby mode.
21.4.1 Transition to Hardware Standby Mode
Regardless of its current state, the chip enters hardware standby mode whenever the 67%< pin
goes low. Hardware standby mode reduces power consumption drastically by halting the CPU
and stopping all functions of the on-chip peripheral modules. The on-chip peripheral modules are
reset, but as long as the specified voltage is supplied, on-chip RAM contents are held. To hold
RAM contents, the RAME bit in the RAM control register (RAMCR) should be cleared to 0. I/O
ports are placed in the high-impedance state.
21.4.2 Recovery from Hardware Standby Mode
Recovery from the hardware standby mode requires inputs on both the 67%< and 5(6 lines.
When 67%< goes high, the clock oscillator begins running. 5(6 should be low at this time. After
the oscillator settling time, when the 5(6 signal goes high, the H8/500 CPU begins executing the
reset sequence. The H8/500 CPU then returns to the program execution state, ending hardware
standby mode.
Rev. 3.0, 02/99, page 678 of 904

21.4.3 Timing for Hardware Standby Mode
Figure 21-2 shows the timing relationships in hardware standby mode.
Clock
oscillator
RES
STBY
Hardware standby mode Oscillator

(power-down state) settling time
(tOSC1)
Restart
Note: The relationship VCC=AVCC should also be maintained in the power-down state.
If AVCC is left open, the analog/digital interface inside the chip will be undetermined,
current dissipation will increase, and other problems will arise regarding reliability.
Figure 21-2 Hardware Standby Mode Timing
Rev. 3.0, 02/99, page 679 of 904

21.5 φ Clock Output Prohibit Function
21.5.1 Overview
The φ pin outputs the system clock. The φ pin can drive one TTL load and a 90-pF capacitive load.
21.5.2 Register Description
Table 21-3 summarizes the φ control register.
Table 21-3 φ Control Registers

H'FE9A φ control register φCR R/W Undefined*
Note: * In standby mode, φCR is initialized to H'FF.
(1) φ Control Register: The φ control register (φCR) is an eight-bit register that enables or
disables output of the system clock (φ).
Bit 7 6 5 4 3 2 1 0
φOE − − − − − − −
Initial value Undefined* 1 1 1 1 1 1 1

R/W R/W R R R R R R R
Note: * The φOE bit is initialized to 1 in standby mode. It is not initialized by a reset.
Rev. 3.0, 02/99, page 680 of 904

φ Output Enable (φ
Bit 7—φ φOE): Enables or disables output of the system clock (φ).
When the φOE bit is cleared to 0, the φ pin goes to the high-impedance state.
(1) H8/539F (Dual Power Source Model) Limitations: Do not disable system clock output
except in single-chip mode (mode 7). When using a mode with on-chip ROM disabled (mode 1,
3, 5, or 6), standby mode must be entered at power-on, so that the φOE bit is set to 1. Also note
that the φOE bit must be set to 1 before accessing the external space. If system clock (φ) output is
disabled in an expanded mode (modes 1-6), external data input and output will not be performed
correctly. For details, see section 3.6, Notes on Use of Externally Expanded Modes of H8/539F
(Dual Power Source Model).
(2) H8/539F S-Mask and A-Mask Models (Single Power Source Model) Limitations:After
applying power to the H8/539F S-mask or A-mask model (single power source model), switch to
the hardware standby mode in all modes (modes 1 to 7). For details, see 3.7 Notes on H8/539F S-
Mask and A-Mask Models (Single Power Source), Power-On Timing.
Bit 7
φOE Description
0 System clock (φ) output is disabled
1 System clock (φ) output is enabled
21.5.3 φPin Status in Different Processing Modes
Table 21.4 shows the φpin status in the various processing modes.
Table 21.4 φPin Status in Different Processing Modes
Processing Mode φOE=1 φOE=0

Hardware standby High impedance High impedance
Software standby Fixed high High impedance
Sleep mode φ output High impedance
Normal operation φ output High impedance
Rev. 3.0, 02/99, page 681 of 904

Section 22 Electrical Characteristics (H8/539F)
Dual Power Source System (VPP = 12 V)
22.1 Absolute Maximum Ratings

Table 22-1 lists the absolute maximum ratings.
Table 22-1 Absolute Maximum Ratings
Item Symbol Value Unit

Power supply voltage VCC –0.3 to +7.0 V
Programming voltage VPP –0.3 to +13.0 V
Input voltage (MD2) Vin –0.3 to + 13.0 V
Input voltage (except ports 8, 9 and MD2) Vin –0.3 to VCC + 0.3 V
Input voltage (ports 8 and 9) Vin –0.3 to AVCC + 0.3 V
Reference voltage VREF –0.3 to AVCC + 0.3 V
Analog power supply voltage AVCC –0.3 to +7.0 V
Analog input voltage VAN –0.3 to AVCC + 0.3 V
Operating temperature Topr Regular specifications: –20 to +75 °C
Wide-range specifications: –40 to +85
Storage temperature Tstg –55 to +125 °C
Note: Permanent damage to the chip may result if absolute maximum ratings are exceeded.
Ensure that the voltage applied to the Vpp and MD2 pins, including the peak overshoot,
does not exceed 13 V. (Also be sure to connect a decoupling capacitor to the Vpp and
MD2 pins.)
Rev. 3.0, 02/99, page 683 of 904

22.2 Electrical Characteristics
22.2.1 DC Characteristics
Tables 22-2 lists the DC characteristics. Table 22-3 lists the permissible output currents.
Table 22-2 DC Characteristics
Conditions: VCC = 5.0 V ±10%, AVCC = 5.0 V ±10%, VREF = 5.0 V ±10% (VREF ≤ AVCC),
VSS = AVSS = 0 V, Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range
specifications)
Test
Item Symbol Min Typ Max Unit Conditions
Input high 5(6, 67%<, VIH VCC – 0.7 — VCC + 0.3 V
voltage MD2–MD0
EXTAL VCC × 0.7 — VCC + 0.3 V
Ports 8 and 9 2.2 — AVCC + 0.3 V
Other input pins 2.2 — VCC + 0.3 V
(except ports 4
and 5)
Input low 5(6, 67%<, VIL –0.3 — 0.4 V
voltage MD2–MD0
Other input pins –0.3 — 0.8 V
(except ports 4
and 5)
–
Schmitt trigger Ports 4 and 5 VT 1.0 — 2.5 V
input voltages VT
+
2.0 — 3.5 V
+ –
VT – VT 0.4 — — V
Input 5(62/VPP | |in | — — 20 mA VCC+0.5V<Vin≤12.6V
leakage current — — 10.0 µA 0.5V≤Vin≤VCC+0.5V
MD2 — — 50.0 µA VCC+0.5V<Vin≤12.6V
— — 10.0 µA 0.5V≤Vin≤VCC+0.5V
5(6, 67%<, NMI, — — 1.0 µA Vin = 0.5 to
MD0–MD2 VCC – 0.5 V
Ports 8 and 9 — — 1.0 µA Vin = 0.5 to
AVCC – 0.5 V
Leakage Ports 1 to 7 and A | ISTI | — — 1.0 µA Vin = 0.5 to
current in3- to C VCC – 0.5 V
state (off-state)
Input pull-up Ports B and C –IP 50 — 300 µA Vin = 0 V
transistor
current
Rev. 3.0, 02/99, page 684 of 904

Table 22-2 DC Characteristics (cont)
Conditions: VCC = 5.0 V ±10%, AVCC = 5.0 V ±10%, VREF = 5.0 V ±10%, (VREF ≤ AVCC),
specifications)

Output high All output pins VOH VCC – 0.5 — — V IOH =
voltage –200 µA
3.5 — — V IOH = –1 mA
Output low All output pins VOL — — 0.4 V IOL = 1.6 mA
voltage (except 5(62)
Ports 3 and 5 — — 1.0 V IOL = 8 mA
— — 1.2 V IOL = 10 mA
5(62 — — 0.4 V IOL = 2.6 mA
High voltage 5(62/VPP, MD2 VH VCC + 2.0 — 11.4 V VCC =
(12V)* applied 4.5 to 5.5 V
criterion
Input 5(62/VPP Cin — — 100 pF Vin = 0 V
capacitance NMI, MD2 — — 50 pF f = 1 MHz
All input pins except — — 20 pF Ta = 25°C
5(62/VPP, NMI,
and MD2
Current Normal operation ICC — 65 100 mA f = 16 MHz
dissipation Sleep mode — 40 60 mA f = 16 MHz
Standby mode — 0.01 5.0 µA Ta ≤ 50°C
— — 20.0 µA 50°C < Ta
Analog power During A/D AICC — 1.2 2.0 mA
supply current conversion
Idle — 0.01 5.0 µA
Reference During A/D AICC — 0.2 0.5 mA
current conversion
Idle — 0.01 5.0 µA
Note: * The high voltage applied criterion is as shown in the table, but in boot mode and for flash
memory programming and erasing, a value of 12.0 ±0.6 V should be set.
Rev. 3.0, 02/99, page 685 of 904

specifications)

VPP current Read IPP — — 10 µA VPP = 5.0 V
— 10 20 mA VPP = 12.6 V
Program — 20 40 mA
Erase — 20 40 mA
RAM standby voltage VRAM 2.0 — — V
Notes: 1. Never leave the AVCC, AVSS, and VREF pins open. If the A/D converter is not used,
connect AVCC and VREF to VCC and connect AVSS to VSS.
2. Current dissipation values are for VIHmin = VCC – 0.5 V and VILmax = 0.5 V with all output
pins unloaded and the on-chip pull-up transistors in the off state.
Table 22-3 Permissible Output Currents
Condition: VCC = 5.0 V ±10%, AVCC = 5.0 V ±10%, VREF = 5.0 V ±10% (VREF ≤ AVCC),
specifications)
Condition
Item Symbol Min Typ Max Unit
Permissible output low Ports 3 and 5 IOL — — 10 mA
current (per pin) 5(62 — — 3.0 mA
Other output pins — — 2.0 mA
Permissible output low Total of 14 pins in ΣIOL — — 40 mA
current (total) ports 3 and 5
Total of all output pins, — — 80 mA
including the above
Permissible output high Per pin -IOH — — 2.0 mA
current
Permissible output high Total of all output pins Σ-IOH — — 25 mA
current
Notes: 1. To protect chip reliability, do not exceed the output current values in table 22-3.
2. When driving a Darlington pair or LED, always insert a current-limiting resistor in the
output line, as shown in figures 22-1 and 22-2.
Rev. 3.0, 02/99, page 686 of 904

H8/539F
2 kΩ
Port 3 or 5
Darlington pair
Figure 22-1 Darlington Pair Drive Circuit (Example)
H8/539F
V CC
600 Ω
Port 3 or 5
LED
Figure 22-2 LED Drive Circuit (Example)
22.2.2 AC Characteristics
The AC characteristics of the H8/539F are described below. Bus timing parameters are listed in
table 22-4. Control signal timing parameters are listed in table 22-5. Timing parameters of the
on-chip peripheral modules are listed in table 22-6.
Rev. 3.0, 02/99, page 687 of 904

Table 22-4 Bus Timing
Condition: VCC = 5.0 V ±10%, AVCC = 5.0 V ±10%, VREF = 5.0 V ±10%, VSS = AVSS = 0 V, Ta
= –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range specifications)
Condition
16 MHz
Test
Item Symbol Min Max Unit Conditions
Clock cycle time tCYC 62.5 500 ns Fig. 22-4,
Fig. 22-5
Clock low pulse width tCL 20 — ns
Clock high pulse width tCH 20 — ns
Clock rise time tCr — 15 ns
Clock fall time tCf — 15 ns
Address delay time tAD — 25 ns
Address hold time tAH 10 — ns
Address strobe delay time 1 tASD1 — 25 ns
Address strobe delay time 2 tASD2 — 25 ns
Read strobe delay time 1 tRDD1 — 25 ns
Read strobe delay time 2 tRDD2 — 25 ns
Write strobe delay time 1 tWRD1 — 25 ns
Write data strobe pulse width 1 tWRW1 50 — ns
Write data strobe pulse width 2 tWRW2 170 — ns
Address setup time 1 tAS1 10 — ns
Read data setup time tRDS 20 — ns
Read data hold time tRDH 0 — ns
Read data access time 1 tACC1 — 60 ns
Read data access time 2 tACC2 — 120 ns
Rev. 3.0, 02/99, page 688 of 904

Table 22-4 Bus Timing (cont)
Condition
16 MHz
Test
Write data delay time tWDD — 55 ns Fig. 22-4,
Fig. 22-5
Write data setup time tWDS 2 — ns
Write data hold time tWDH 10 — ns
Wait setup time tWTS 25 — ns Fig. 22-6
Wait hold time tWTH 10 — ns
Bus request setup time tBRQS 30 — ns Fig. 22-10
Bus acknowledge delay time 1 tBACD1 — 30 ns
Bus acknowledge delay time 2 tBACD2 — 30 ns
Bus-floating delay time tBZD — tBACD1 ns
Rev. 3.0, 02/99, page 689 of 904

Table 22-5 Control Signal Timing
Condition
16 MHz
Test
5(6 setup time tRESS 200 — ns Fig. 22-7
5(6 pulse width tRESW 6.0 — tcyc
Mode programming setup time* tMDS 4.0 — tcyc
5(62 output delay time tRESD — 200 ns Fig. 22-8
R(62 output pulse width tRESOW 132 — tcyc
NMI setup time tNMIS 150 — ns Fig. 22-9
NMI hold time tNMIH 10 — ns
,540 setup time tIRQ0S 50 — ns
,541 to ,543 setup time tIRQ1S 50 — ns
,541 to ,543 hold time tIRQ1H 10 — ns
NMI pulse width (for recovery tNMIW 200 — ns
from software standby mode)
Clock oscillator settling time at tOSC1 20 — ms Fig. 22-11
reset (crystal)
Clock oscillator settling time in tOSC2 10 — ms Fig. 21-1
software standby (crystal)
External clock output settling tDEXT 500 — µs Fig. 22-12
delay time (When inputting
external clock from the EXTAL
pin)
Note:* In boot mode, the input high voltage to MD2 should satisfy the high voltage (12V) applied
criterion (VH max).
Rev. 3.0, 02/99, page 690 of 904

Table 22-6 Timing of On-Chip Supporting Modules
Condition
16 MHz Test
Item Item Symbol Min Max Unit Conditions
IPU Timer output delay time tTOCD — 100 ns Fig. 22-15
Timer input setup time tTICS 50 — ns
Timer clock input setup time tTCKS 50 — ns Fig. 22-16
Timer clock pulse width tTCKW 1.5 — tCYC
SCI Input clock cycle Asyn- tSCYC 4 — tCYC Fig. 22-17
chronous
Clocked 6 — tCYC
syn-
chronous
Input clock pulse width tSCKW 0.4 0.6 tSCYC
Transmit data delay time tTXD — 100 ns Fig. 22-18
Receive data setup time tRXS 100 — ns
(clocked synchronous)
Receive data hold time tRXH 100 — ns
Ports Output data delay time tPWD — 50 ns Fig. 22-13
Receive data setup time tPRS 50 — ns
Receive data hold time tPRH 50 — ns
PWM output delay time tPWDD — 100 ns Fig.22-14
Rev. 3.0, 02/99, page 691 of 904

5V
RL
H8/539F C = 90 pF: P1, P2, PA, PB,

output pin PC, φ, AS, RD,
HWR, LWR
C = 30 pF: P3, P4, P5, P6,
P7
C RH RL = 2.4 kΩ
RH = 12 kΩ
Input/output timing
measurement levels
• Low: 0.8 V
• High: 2.0 V
Figure 22-3 Output Load Circuit
Rev. 3.0, 02/99, page 692 of 904

22.2.3 A/D Conversion Characteristics
Table 22-7 lists the A/D conversion characteristics of the H8/539F. Table 22-8 lists the
permissible signal-source impedance for the A/D converter.
Table 22-7 A/D Converter Characteristics
specifications)
Condition
16 MHz
Item Min Typ Max Unit
Resolution 10 10 10 Bits
Conversion time — — 8.38 µs
Analog input capacitance — — 20 pF
Nonlinearity error — — ±2.0 LSB
Offset error — — ±2.0 LSB
Full-scale error — — ±2.0 LSB
Quantization error — — ±1/2 LSB
Absolute accuracy — — ±2.5 LSB
Table 22-8 A/D Converter Characteristics: Allowable Signal-Source Impedance
specifications)
Item Conditions Min Typ Max Unit

Allowable signal-source 8.38 µs ≤ conversion time < 13.4 µs — — 5 kΩ
impedance
Conditions other than above — — 10
Rev. 3.0, 02/99, page 693 of 904

22.2.4 Flash Memory Characteristics
Table 22-9 lists the flash memory characteristics of the H8/539F.
Table 22-9 Flash Memory Characteristics
Conditions: VCC = 4.5 to 5.5 V, AVCC = 4.5 to 5.5 V, VREF = 4.5 to 5.5 V, VSS = AVSS = 0V,
VPP = 12.0 ±0.6V, Ta = –20 to +75°C (regular specifications), Ta = –40 to 85°C (wide-range
specifications)
Test
1, 2
Programming time* * tP — 50 1000 µs/byte
1, 3
Erase time* * tE — 1 30 s
Number of writing /
NWEC — — 100 times
erasing count
1
Verify-setup time 1* tvs1 4 — — µs
1
Verify- setup time 2* tvs2 2 — — µs
VPP enable setup time tVPS 5 — — µs
Flash-memory-read tFRS 50 — — µs VCC ≥ 4.5V Fig.22-19
4
setup time* Fig.22-20
Notes: 1. Set the times following the programming/erasing algorithm shown in section 19, "Flash
Memory."
2. The programming time is the time during which a byte is programmed or the P bit in the
flash memory control register (FLMCR) is set. It does not include the program-verify
time.
3. The erase time is the time during which all blocks (128 kbytes) are erased or the E bit in
the flash memory control register (FLMCR) is set. It does not include the prewriting time
before erasure or erase-verify time.
4. After power-on when using an external clock source, after return from standby mode, or
after clearing the VPP enable bit, make sure that this read setup time has elapsed before
reading flash memory.
Rev. 3.0, 02/99, page 694 of 904

22.3 Operational Timing
This section shows timing diagrams of H8/539F operations.
22.3.1 Bus Timing
This section gives the following bus timing diagrams:
1. Basic bus cycle: two-state access

Figure 22-4 shows the timing of the external two-state access cycle.
2. Basic bus cycle: three-state access
Figure 22-5 shows the timing of the external three-state access cycle.
3. Basic bus cycle: three-state access with one wait state
Figure 22-6 shows the timing of the external three-state access cycle with one wait state
inserted.
Rev. 3.0, 02/99, page 695 of 904

T1 T2
t cyc
t CH t CL
φ
t Cf t Cr
t AD
A19 −A 0
t ASD1 t ASD2 t AH
AS
t AS1
t RDD1 t RDD2 t AH
RD (read)
t AS1
t ACC1 t RDS t RDH
D15 −D 0 (read)
t WRD1 t WRD2 t AH
t WRW1
HWR, LWR
(write) t AS2
t WDD t WDH
D15 −D0 (write)
Figure 22-4 Basic Bus Cycle: Two-State Access
Rev. 3.0, 02/99, page 696 of 904

T1 T2 T3
A 19 -A 0
AS
RD
(read)
t ACC2
D15 -D0
(read)
t WRD3
t WRW2
HWR, LWR
(write) t AS3
t WDS
D15 -D0
(write)
Figure 22-5 Basic Bus Cycle: Three-State Access
Rev. 3.0, 02/99, page 697 of 904

T1 T2 TW T3
A19 − A 0
AS
RD
(read)
D15−D0
(read)
HWR, LWR
(write)
D15−D0
(write)
t WTS t WTH t WTS t WTH
WAIT
Figure 22-6 Basic Bus Cycle: Three-State Access with One Wait State
Rev. 3.0, 02/99, page 698 of 904

22.3.2 Control Signal Timing
This section gives the following control signal timing diagrams:
1. Reset input timing

Figure 22-7 shows the reset input timing.
2. Reset output timing
Figure 22-8 shows the reset output timing.
3. Interrupt input timing
Figure 22-9 shows the input timing for NMI, IRQ0, and IRQ1 to IRQ3.
4. Bus-release mode timing
Figure 22-10 shows the bus-release mode timing.
t RESS t RESS
RES
t MDS* t RESW
MD2−MD0
Note: *In boot mode, the high-level input at the MD2 pin must satisfy the high-voltage
(12 V) application criterion (VHmax).
Figure 22-7 Reset Input Timing
tRESD tRESD
RESO
tRESOW
Figure 22-8 Reset Output Timing
Rev. 3.0, 02/99, page 699 of 904

φ
t NMIS t NMIH
NMI
t IRQ1S t IRQ1H
IRQ1−IRQ3
t IRQ0S
IRQ0
Figure 22-9 Interrupt Input Timing
tBRQS t BRQS
BREQ
t BACD1 t BACD2
BACK
t BZD t BZD
A19-A0,
AS, RD,
HWR,
LWR
Figure 22-10 Bus-Release Mode Timing
Rev. 3.0, 02/99, page 700 of 904

22.3.3 Clock Timing
This section gives the following H8/539F clock timing diagram:
1. Oscillator settling timing

Figure 22-11 shows the oscillator settling timing.
2. External clock output settling delay timing
Figure 22-12 shows the external clock output settling delay timing.
VCC
STBY
t OSC1 t OSC1
RES
Figure 22-11 Oscillator Settling Timing
4.5V
VCC
VIH
STBY
EXTAL
RES
tDEXT*
Note: * t DEXT includes 6 tcyc (min.) RES pulse width.
Figure 22-12 External clock Output Settling Delay Timing
Rev. 3.0, 02/99, page 701 of 904

22.3.4 I/O Port Timing
This section gives the following H8/539F I/O port input/output timing diagram:
1. I/O port input/output timing

Figure 22-13 shows the I/O port input/output timing.
T1 T2 T3
t PRS t PRH
Ports 1 to C
(read)
t PWD
Ports 1 to 7
and A to C
(write)
Figure 22-13 I/O Port Input/Output Timing
22.3.5 PWM Timer Output Timing
This section gives the following H8/539F PWM timer output timing diagram.
1. PWM timer output timing

Figure 22-14 shows the PWM timer output timing.
TCNT Compare-match
t PWDD
PW1 to 3
Figure 22-14 PWM Timer Output Timing
Rev. 3.0, 02/99, page 702 of 904

22.3.6 IPU Timing
This section gives the following H8/539F IPU timing diagrams:
1. IPU input/output timing

Figure 22-15 shows the IPU input/output timing.
2. IPU external clock input timing
Figure 22-16 shows the IPU external clock input timing.
t TOCD
Output
compare* 1
t TICS
Input
capture* 2
Notes: 1. T1OC1 to T5OC2 and T1IOC1 to T7IOC2

2. T1IOC1 to T7IOC2
Figure 22-15 IPU Input/Output Timing
t TCKS
TCLK1−TCLK3
t TCKW t TCKW
Figure 22-16 IPU Clock Input Timing
Rev. 3.0, 02/99, page 703 of 904

22.3.7 SCI Input/Output Timing
This section gives the following H8/539F SCI timing diagrams:
1. SCI input clock timing

Figure 22-17 shows the SCI input clock timing.
2. SCI input/output timing (clocked synchronous mode)
Figure 22-18 shows the SCI input/output timing in clocked synchronous mode.
t SCKW
SCK1, SCK2
t scyc
Figure 22-17 SCK Input Clock Timing
t scyc
SCK1, SCK2
t TXD
TXD1, TXD2
(transmit data)
t RXS t RXH
RXD1, RXD2
(receive data)
Figure 22-18 SCI Input/Output Timing

(Clocked Synchronous Mode)
Rev. 3.0, 02/99, page 704 of 904

22.3.8 Flash Memory Read Timing
This section gives the following H8/539F on-chip flash memory read timing diagrams:
1. Flash memory read timing (after clearing VPPE bit)

Figure 22-19 shows the flash memory read timing after VPP power-off.
2. Flash memory read timing (when using external clock)
Figure 22-20 shows the flash memory read timing after VCC power-on and exit from standby
mode when an external clock is input from the EXTAL pin.
11.4V
VPP
VCC+2V
VPPE bit
(Flash memory
control register)
tFRS
RD
(On-chip ROM read signal)
Figure 22-19 Flash Memory Read Timing (After Clearing VPPE Bit)
Rev. 3.0, 02/99, page 705 of 904

4.5V
VCC
VIH
STBY
EXTAL
RES
tFRS
FRS**
RD
(On-chip ROM read signal)
Note: * tFRS includes 6 tcyc (min.) RES pulse width.
Figure 22-20 Flash Memory Read Timing (When Using External Clock)
Rev. 3.0, 02/99, page 706 of 904

(H8/539F S-Mask model)
23.1 Absolute Maximum Ratings (H8/539F S-Mask model)


1
Programming voltage (FWE)* Vin –0.3 to VCC + 0.3 V
1
Input voltage (MD2)* Vin –0.3 to VCC + 0.3 V
Input voltage (except ports 8 and 9) Vin –0.3 to VCC + 0.3 V
2
Operating temperature Topr Regular specifications: –20 to +75* °C
2
Wide-range specifications: –40 to +85*
Notes: Permanent damage to the chip may result if absolute maximum ratings are exceeded.
1. 12 V must not be applied to the S-mask model (single power source), as this may
2. The operating temperature range during flash memory programming and erasing is: Ta
= 0 to +70°C.
23.2 Electrical Characteristics (H8/539F S-Mask Model)
Tables 23-2 and lists the DC characteristics. Table 23-3 lists the permissible output currents.
Rev. 3.0, 02/99, page 707 of 904

Conditions: VCC = 5.0 V ±10%, AVCC = 5.0 V ±10%, VREF = 5.0 V ±10% (VREF ≤ AVCC), VSS
= AVSS = 0 V, Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range
specifications)
Test
Input high 5(6, 67%<, MD2– VIH VCC – 0.7  VCC + 0.3 V
voltage MD0, FEW
EXTAL VCC × 0.7  VCC + 0.3 V
Ports 8 and 9 2.2  AVCC + 0.3 V
Other input pins 2.2  VCC + 0.3 V
(except ports 4
and 5)
Input low 5(6, 67%<, VIL –0.3  0.4 V
voltage MD2–MD0, FEW
Other input –0.3  0.8 V
pins(except ports 4
and 5)
Schmitt trigger Ports 4 and 5 VT
–
1.0  2.5 V
input voltages VT
+
2.0  3.5 V
VT
+
– VT
–
0.4   V
Input leakage FWE | |in |   10 µA Vin = 0.5 to
current VCC – 0.5 V
MD2   1.0 µA Vin = 0.5 to
VCC – 0.5 V
5(6, 67%<, NMI,   1.0 µA Vin = 0.5 to
Ports 8 and 9   1.0 µA Vin = 0.5 to
AVCC – 0.5 V
Leakage Ports 1 to 7 | ISTI |   1.0 µA Vin = 0.5 to
current in3- and A to C VCC – 0.5 V
state(off-state)
Input pull-up Ports B and C –IP 50  300 µA Vin = 0 V
transistor
current
Rev. 3.0, 02/99, page 708 of 904

specifications)

Output high All output pins VOH VCC – 0.5   V IOH = –200 µA
voltage 3.5   V IOH = –1 mA
Output low All output pins VOL   0.4 V IOL = 1.6 mA
voltage
Ports 3 and 5   1.0 V IOL = 8 mA
  1.2 V IOL = 10 mA
Input FWE Cin   60 pF Vin = 0 V
capacitance NMI, MD   50 pF f = 1 MHz
2
All input pins   20 pF Ta = 25°C

except FEW, NMI,
and MD2
Current Normal operation ICC  65 100 mA f = 16 MHz
dissipation
Sleep mode  40 60 mA f = 16 MHz
Standby mode  0.01 5.0 µA Ta ≤ 50°C
  20.0 µA 50°C < Ta
Analog power During A/D AICC  1.2 2.0 mA
supply conversion
current Idle  0.01 5.0 µA
Reference During A/D AICC  0.6 0.8 mA
current conversion
Idle  0.01 5.0 µA
Rev. 3.0, 02/99, page 709 of 904

specifications)

RAM standby voltage VRAM 2.0   V
pins unloaded and the on-chip pull-up transistors in the off state. (When read is
operating in flash memory).
3. The current dissipation value in flash memory programming and erasing (Ta = 0 to +
70°C) is 20 mA (max.) (preliminary) higher than in normal operation.
Table 23-3 Permissible Output Currents (H8/539F S-Mask Model)
Condition: VCC = 5.0 V ±10%, AVCC = 5.0 V ±10%, VREF = 5.0 V ±10% (VREF ≤ AVCC), VSS = AVSS
= 0 V, Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range specifications)
Condition
Permissible output low Ports 3 and 5 IOL   10 mA
current (per pin)
Other output pins   2.0 mA
Permissible output low Total of 14 pins in ΣIOL   40 mA
Total of all output pins   80 mA
including the above,
Permissible output high All output pins -IOH   2.0 mA
current (per pin)
Permissible output high Total of all output pins Σ-IOH   25 mA
Current
Rev. 3.0, 02/99, page 710 of 904

H8/539F
2 kΩ
Port 3 or 5
Darlington pair
H8/539F
V CC
600 Ω
Port 3 or 5
LED
Rev. 3.0, 02/99, page 711 of 904

23.2.2 AC Characteristics (H8/539F S-Mask Model)
Condition
16 MHz
Test
Clock low pulse width tCL 20  ns Fig. 23-5
Clock high pulse width tCH 20  ns

Clock rise time tCr  15 ns
Clock fall time tCf  15 ns
Address delay time tAD  25 ns
Address hold time tAH 10  ns
Address strobe delay time 1 tASD1  25 ns
Read strobe delay time 1 tRDD1  25 ns
Write strobe delay time 1 tWRD1  25 ns
Write data strobe pulse width 1 tWRW1 50  ns
Address setup time 1 tAS1 10  ns
Read data setup time tRDS 20  ns
Read data hold time tRDH 0  ns
Rev. 3.0, 02/99, page 712 of 904

Condition
16 MHz Test
Read data access time 1 tACC1  60 ns Fig. 23-4
Fig. 23-5
Read data access time 2 tACC2  120 ns
Write data delay time tWDD  55 ns
Write data setup time tWDS 2  ns
Write data hold time tWDH 10  ns
Wait setup time tWTS 25  ns Fig. 23-6
Wait hold time tWTH 10  ns
Bus request setup time tBRQS 30  ns Fig. 23-9
Bus acknowledge delay time 1 tBACD1  30 ns
Bus-floating delay time tBZD  tBACD1 ns
Rev. 3.0, 02/99, page 713 of 904

Table 23-5 Control Signal Timing (H8/539F S-Mask Model)
Condition
16 MHz
Test
5(6 setup time tRESS 200  ns Fig. 23-7
5(6 pulse width tRESW 20  tcyc
Mode programming setup time tMDS 4.0  tcyc
NMI setup time tNMIS 150  ns Fig. 23-8
NMI hold time tNMIH 10  ns
,540 setup time tIRQ0S 50  ns
,541–3 setup time tIRQ1S 50  ns
,541–3 hold time tIRQ1H 10  ns
NMI pulse width (for recovery tNMIW 200  ns
Clock oscillator settling time at tOSC1 20  ms Fig. 23-10
reset (crystal)
Clock oscillator settling time in tOSC2 10  ms Fig. 21-1
External clock output settling tDEXT 500  µs Fig. 23-11
pin)
Rev. 3.0, 02/99, page 714 of 904

Table 23-6 Timing of On-Chip Supporting Modules (H8/539F S-Mask Model)
16 MHz
Item Item Symbol Min Max Unit
IPU Timer output delay Time tTOCD  100 ns Fig. 23-14
Timer input setup Time tTICS 50  ns
Timer clock input setup time tTCKS 50  ns Fig. 23-15
Timer clock pulse Width tTCKW 1.5  tCYC
PWM output delay time tPWDD  100 ns Fig.23-13
SCI Input clock cycle Asyn- tSCYC 4  tCYC Fig. 23-16
chronous
Clocked syn- 6  tCYC
chronous
Input clock pulse Width tSCKW 0.4 0.6 tSCYC
Transmit data delay Time tTXD  100 ns Fig. 23-17
Receive data setup time (clocked tRXS 100  ns
synchronous)
Receive data hold time (clocked tRXH 100  ns
synchronous)
Ports Output data delay Time tPWD  50 ns Fig. 23-12
Receive data setup time (clocked tPRS 50  ns
synchronous)
Receive data hold time (clocked tPRH 50  ns
synchronous)
Rev. 3.0, 02/99, page 715 of 904

5V
RL
H8/539F C = 90 pF: P1, P2, PA, PB,

HWR, LWR
C = 30 pF: P3, P4, P5, P6,
P7
C RH RL = 2.4 kΩ
RH = 12 kΩ
Input/output timing
measurement levels
• Low: 0.8 V
• High: 2.0 V
Rev. 3.0, 02/99, page 716 of 904

23.2.3 A/D Conversion Characteristics (H8/539F S-Mask Model)
specifications)
Condition
16 MHz
Conversion time   8.38 µs
Analog input capacitance   20 pF
Nonlinearity error   ±2.0 LSB
Offset error   ±2.0 LSB
Full-scale error   ±2.0 LSB
Quantization error   ±1/2 LSB
Absolute accuracy   ±2.5 LSB
specifications)

Allowable signal-source 8.38 µs ≤ conversion time < 13.4 µs   5 kΩ
impedance
Conditions other than above   10
Rev. 3.0, 02/99, page 717 of 904

23.2.4 Flash Memory Characteristics (H8/539F S-Mask Model)
Ta = 0 to +70°C (regular specifications), Ta = 0 to 70°C (wide-range specifications)
Test
1, 2,
Programming time* * *
4
tP  10 200 ms/32 byte
1,
Erase time* * *
3, 5
tE  100 300 ms/block
Number of writing / erasing count NWEC   100 times
Programming Wait time after SWE-bit set*
1
x 10   µs
time
Waite time after PSU-bit set*
1
y 50   µs
1,
Wait time after P-bit set* *
4
z 150  500 µs
Wait time after P-bit clear*
1
α 10   µs
Wait time after PSU-bit clear*
1
β 10   µs
Wait time after PV-bit set*
1
γ 4   µs
Wait time after H'FF dummy write*
1
ε 2   µs
Wait time after PV-bit clear*
1
η 4   µs
Maximum number of programs* *
1, 4
N   403 times
Erase time Wait time after SWE-bit set*
1
x 10   µs
Waite time after ESU-bit set*
1
y 200   µs
1,
Wait time after E-bit set* *
5
z   5 ms
Wait time after E-bit clear*
1
α 10   µs
Wait time after ESU-bit clear*
1
β 10   µs
Wait time after EV-bit set*
1
γ 20   µs
1
ε 2   µs
Wait time after EV-bit clear*
1
η 5   µs
1,
Maximum number of erasures* *
5
N   60 times
Notes: 1. Make the time settings in accordance with the program/erase algorithm.
2. The programming time for 32 bytes. (Indicates the total time for which the P bit in the
flash memory control register (FLMCR) is set. The program/verify time is not included.)
3. The time required to erase one block. (Indicates the time for which the E bit in the flash
memory control register (FLMCR) is set. The erase/verify time is not included.)
Rev. 3.0, 02/99, page 718 of 904

4. To specify the programming time maximum value (tP(max)) in the 32-byte programming
flow, set the maximum number of writes (N) to the maximum value (403).
Also, the wait time after P bit setting (z) is switched based on the number of writes as
shown below.
If the number of writes counter is at 1 to 4, z = 150 µs.
5. Erase time maximum value (tE(max)) = wait time after E bit setting (z) x maximum
number of erases (N)
23.3 Operational Timing (H8/539F S-Mask Model)

23.3.1 Bus Timing

inserted.
Rev. 3.0, 02/99, page 719 of 904

T1 T2
t cyc
t CH t CL
φ
t Cf t Cr
t AD
A19−A0
t ASD1 t ASD2 t AH
AS
t AS1
t RDD1 t RDD2 t AH
RD (read)
t AS1
t ACC1 t RDS t RDH
D15−D0 (read)
t WRD1 t WRD2 t AH
t WRW1
HWR, LWR
(write) t AS2
t WDD t WDH
D15−D0 (write)
Rev. 3.0, 02/99, page 720 of 904

(H8/539F S-Mask Model)
T1 T2 T3
A19−A0
AS
RD
(read)
t ACC2
D15−D0
(read)
t WRD3
t WRW2
HWR, LWR
(write) t AS3
t WDS
D15−D0
(write)
Rev. 3.0, 02/99, page 721 of 904

T1 T2 TW T3
A19−A0
AS
RD
(read)
D15−D0
(read)
HWR, LWR
(write)
D15−D0
(write)
WAIT
Rev. 3.0, 02/99, page 722 of 904

23.3.2 Control Signal Timing (H8/539F S-Mask Model)

Figure 23-8 shows the input timing for NMI, ,540, and ,541 to ,543.
t RESS t RESS
RES
t MDS t RESW
MD2−MD0 ,
FWE*
Note: * The FWE input timing shown is for entering and exiting boot mode.
Rev. 3.0, 02/99, page 723 of 904

(H8/539F S-Mask Model)
t NMIS t NMIH
NMI
t IRQ1S t IRQ1H
IRQ1−IRQ3
t IRQ0S
IRQ0
tBRQS t BRQS
BREQ
t BACD1 t BACD2
BACK
t BZD t BZD
A19−A0,
AS, RD,
HWR,
LWR
Rev. 3.0, 02/99, page 724 of 904

23.3.3 Clock Timing (H8/539F S-Mask Model)

VCC
STBY
t OSC1 t OSC1
RES
4.5V
VCC
VIH
STBY
EXTAL
RES
tDEXT*
Note: * tDEXT includes 20 tcyc (min.) RES pulse width.
Rev. 3.0, 02/99, page 725 of 904

23.3.4 I/O Port Timing (H8/539F S-Mask Model)

T1 T2 T3
t PRS t PRH
Ports 1 to C
(read)
t PWD
Ports 1 to 7
and A to C
(write)

TCNT Compare-match
t PWDD
PW1 to 3
Rev. 3.0, 02/99, page 726 of 904

23.3.6 IPU Timing (H8/569F S-Mask Model)

t TOCD
Output
compare* 1
t TICS
Input
capture* 2

2. T1IOC1 to T7IOC2
t TCKS
TCLK1-TCLK3
t TCKW t TCKW
Rev. 3.0, 02/99, page 727 of 904

23.3.7 SCI Input/Output Timing (H8/569F S-Mask Model)

t SCKW
SCK1, SCK2
t scyc
t scyc
SCK1, SCK2
t TXD
TXD1, TXD2
(transmit data)
t RXS t RXH
RXD1, RXD2
(receive data)

Rev. 3.0, 02/99, page 728 of 904

(H8/539F A-Mask model)
24.1 Absolute Maximum Ratings (H8/539F A-Mask model)


1
Programming voltage (FWE)* Vin –0.3 to VCC + 0.3 V
1
Input voltage (MD2) * Vin –0.3 to VCC + 0.3 V
Input voltage (except ports 8 and 9) Vin –0.3 to VCC + 0.3 V
2
Operating temperature Topr Regular specifications: –20 to +75* °C
2
Wide-range specifications: –40 to +85*
Notes: Permanent damage to the chip may result if absolute maximum ratings are exceeded.
1. 12 V must not be applied to the A-mask model (single power source), as this may
2. The operating temperature range during flash memory programming and erasing is: Ta
= 0 to +70°C.
Rev. 3.0, 02/99, page 729 of 904

24.2 Electrical Characteristics (H8/539F A-Mask Model)
Tables 24-2 and lists the DC characteristics. Table 24-3 lists the permissible output currents.
Conditions: VCC = 5.0 V ±10%, AVCC = 5.0 V ±10%, VREF = 5.0 V ±10% (VREF ≤ AVCC), VSS
= AVSS = 0 V, Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range
specifications)
Test
Input high 5(6, 67%<, VIH VCC – 0.7  VCC + 0.3 V
EXTAL VCC × 0.7  VCC + 0.3 V
Ports 8 and 9 2.2  AVCC + 0.3 V
Other input pins 2.2  VCC + 0.3 V
(except ports 4
and 5)
Input low 5(6, 67%<, VIL –0.3  0.4 V
Other input –0.3  0.8 V
pins(except ports 4
and 5)
Schmitt trigger Ports 4 and 5 VT
–
1.0  2.5 V
input voltages VT
+
2.0  3.5 V
VT
+
– VT
–
0.4   V
Input leakage FWE | Iin |   10 µA Vin = 0.5 to
current VCC – 0.5 V
MD2   1.0 µA Vin = 0.5 to
VCC – 0.5 V
5(6, 67%<, NMI,   1.0 µA Vin = 0.5 to
Ports 8 and 9   1.0 µA Vin = 0.5 to
AVCC – 0.5 V
Leakage Ports 1 to 7 | ISTI |   1.0 µA Vin = 0.5 to
current in3- and A to C VCC – 0.5 V
state(off-state)
Input pull-up Ports B and C –IP 50  300 µA Vin = 0 V
transistor
current
Rev. 3.0, 02/99, page 730 of 904

specifications)

Output high All output pins VOH VCC – 0.5   V IOH = –200 µA
voltage 3.5   V IOH = –1 mA
Output low All output pins VOL   0.4 V IOL = 1.6 mA
voltage
Ports 3 and 5   1.0 V IOL = 8 mA
  1.2 V IOL = 10 mA
Input FWE Cin   60 pF Vin = 0 V
capacitance NMI, MD   50 pF f = 1 MHz
2
All input pins   20 pF Ta = 25°C

except FEW, NMI,
and MD2
Current Normal operation ICC  45 70 mA f = 16 MHz
dissipation
Sleep mode  25 45 mA f = 16 MHz
Standby mode  0.01 5.0 µA Ta ≤ 50°C
  20.0 µA 50°C < Ta
Analog power During A/D AICC  1.2 2.0 mA
supply conversion
current Idle  0.01 5.0 µA
Reference During A/D AICC  0.6 0.8 mA
current conversion
Idle  0.01 5.0 µA
Rev. 3.0, 02/99, page 731 of 904

specifications)

RAM standby voltage VRAM 2.0   V
pins unloaded and the on-chip pull-up transistors in the off state. (When read is
operating in flash memory).
3. The current dissipation value in flash memory programming and erasing (Ta = 0 to +
70°C) is 20 mA (max.) (preliminary) higher than in normal operation.
Table 24-3 Permissible Output Currents (H8/539F A-Mask Model)
Condition: VCC = 5.0 V ±10%, AVCC = 5.0 V ±10%, VREF = 5.0 V ±10% (VREF ≤ AVCC), VSS = AVSS
= 0 V, Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range specifications)
Condition
Permissible output low Ports 3 and 5 IOL   10 mA
current (per pin)
Other output pins   2.0 mA
Permissible output low Total of 14 pins in ΣIOL   40 mA
Total of all output pins   80 mA
including the above,
Permissible output high All output pins -IOH   2.0 mA
current (per pin)
Permissible output high Total of all output pins Σ-IOH   25 mA
Current
Rev. 3.0, 02/99, page 732 of 904

H8/539F
2 kΩ
Port 3 or 5
Darlington pair
H8/539F
V CC
600 Ω
Port 3 or 5
LED
Rev. 3.0, 02/99, page 733 of 904

24.2.2 AC Characteristics (H8/539F A-Mask Model)
Condition: VCC = 5.0 V ±10%, AVCC = 5.0 V ±10%, VREF = 5.0 V ±10%, VSS = AVSS = 0 V,
Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range specifications)
Condition
16 MHz
Test
Clock low pulse width tCL 15  ns Fig. 24-5
Clock high pulse width tCH 15  ns

Clock rise time tCr  15 ns
Clock fall time tCf  15 ns
Address delay time tAD  35 ns
Address hold time tAH 5  ns
Read data setup time tRDS 40  ns
Read data hold time tRDH 0  ns
Rev. 3.0, 02/99, page 734 of 904

Condition: VCC = 5.0 V ±10%, AVCC = 5.0 V ±10%, VREF = 5.0 V ±10%, VSS = AVSS = 0 V,
Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range specifications)
Condition
16 MHz
Test
Read data access time 1 tACC1  30 ns Fig. 24-4
Fig. 24-5
Read data access time 2 tACC2  90 ns
Write data delay time tWDD  55 ns
Write data setup time tWDS 2  ns
Write data hold time tWDH 10  ns
Wait setup time tWTS 40  ns Fig. 24-6
Wait hold time tWTH 10  ns
Bus request setup time tBRQS 30  ns Fig. 24-9
Bus-floating delay time tBZD  tBACD1 ns
Rev. 3.0, 02/99, page 735 of 904

Table 24-5 Control Signal Timing (H8/539F A-Mask Model)
Condition
16 MHz
Test
5(6 setup time tRESS 200  ns Fig. 24-7
5(6 pulse width tRESW 20  tcyc
Mode programming setup time tMDS 4.0  tcyc
NMI setup time tNMIS 150  ns Fig. 24-8
NMI hold time tNMIH 10  ns
,540 setup time tIRQ0S 50  ns
,541 to ,543 setup time tIRQ1S 50  ns
,541 to ,543 hold time tIRQ1H 10  ns
NMI pulse width (for recovery tNMIW 200  ns
Clock oscillator settling time at tOSC1 20  ms Fig. 24-10
reset (crystal)
Clock oscillator settling time in tOSC2 10  ms Fig. 21-1
External clock output settling tDEXT 500  µs Fig. 24-11
pin)
Rev. 3.0, 02/99, page 736 of 904

Table 24-6 Timing of On-Chip Supporting Modules (H8/539F A-Mask Model)
16 MHz
Item Item Symbol Min Max Unit
IPU Timer output delay Time tTOCD  100 ns Fig. 24-14
Timer input setup Time tTICS 50  ns
Timer clock input setup time tTCKS 50  ns Fig. 24-15
Timer clock pulse Width tTCKW 1.5  tCYC
PWM output delay time tPWDD  100 ns Fig.24-13
SCI Input clock cycle Asyn- tSCYC 4  tCYC Fig. 24-16
chronous
Clocked syn- 6  tCYC
chronous
Input clock pulse Width tSCKW 0.4 0.6 tSCYC
Transmit data delay Time tTXD  100 ns Fig. 24-17
Receive data setup time (clocked tRXS 100  ns
synchronous)
Receive data hold time (clocked tRXH 100  ns
synchronous)
Ports Output data delay Time tPWD  50 ns Fig. 24-12
Receive data setup time (clocked tPRS 50  ns
synchronous)
Receive data hold time (clocked tPRH 50  ns
synchronous)
Rev. 3.0, 02/99, page 737 of 904

5V
RL
H8/539F C = 90 pF: P1, P2, PA, PB,

HWR, LWR
C = 30 pF: P3, P4, P5, P6,
P7
C RH RL = 2.4 kΩ
RH = 12 kΩ
Input/output timing
measurement levels
• Low: 0.8 V
• High: 2.0 V
24.2.3 A/D Conversion Characteristics (H8/539F A-Mask Model)
Rev. 3.0, 02/99, page 738 of 904

specifications)
Condition
16 MHz
Conversion time   8.38 µs
Analog input capacitance   20 pF
Nonlinearity error   ±2.0 LSB
Offset error   ±2.0 LSB
Full-scale error   ±2.0 LSB
Quantization error   ±1/2 LSB
Absolute accuracy   ±2.5 LSB
specifications)

Allowable signal-source 8.38 µs ≤ conversion time < 13.4 µs   5 kΩ
impedance
Conditions other than above   10
24.2.4 Flash Memory Characteristics (H8/539F A-Mask Model)
Rev. 3.0, 02/99, page 739 of 904

Ta = 0 to +70°C (regular specifications), Ta = 0 to 70°C (wide-range specifications)
Test
1, 2,
Programming time* * *
4
tP  10 200 ms/32 byte
1,
Erase time* * *
3, 5
tE  100 300 ms/block
Number of writing / erasing count NWEC   100 times
Programming Wait time after SWE-bit set*
1
x 10   µs
time
Waite time after PSU-bit set*
1
y 50   µs
1,
Wait time after P-bit set* *
4
z   200 µs
Wait time after P-bit clear*
1
α 10   µs
Wait time after PSU-bit clear*
1
β 10   µs
Wait time after PV-bit set*
1
γ 4   µs
1
ε 2   µs
Wait time after PV-bit clear*
1
η 4   µs
1,
Maximum number of programs* *
4
N   1000 times
Erase time Wait time after SWE-bit set*
1
x 10   µs
Waite time after ESU-bit set*
1
y 200   µs
1,
Wait time after E-bit set* *
5
z   5 ms
Wait time after E-bit clear*
1
α 10   µs
Wait time after ESU-bit clear*
1
β 10   µs
Wait time after EV-bit set*
1
γ 20   µs
1
ε 2   µs
Wait time after EV-bit clear*
1
η 5   µs
Maximum number of erasures* *
1, 5
N   60 times
Notes: 1. Make the time settings in accordance with the program/erase algorithm.
2. The programming time for 32 bytes. (Indicates the total time for which the P bit in the
flash memory control register (FLMCR) is set. The program/verify time is not included.)
3. The time required to erase one block. (Indicates the time for which the E bit in the flash
memory control register (FLMCR) is set. The erase/verify time is not included.)
4. To specify the programming time maximum value (tP(max)) in the 32-byte programming
flow, set the maximum number of writes (N) to the maximum value (403).
Also, the wait time after P bit setting (z) is switched based on the number of writes as
shown below.
5. Erase time maximum value (tE(max)) = wait time after E bit setting (z) x maximum
number of erases (N)
Rev. 3.0, 02/99, page 740 of 904

24.3 Operational Timing (H8/539F A-Mask Model)
24.3.1 Bus Timing

inserted.
Rev. 3.0, 02/99, page 741 of 904

T1 T2
t cyc
t CH t CL
φ
t Cf t Cr
t AD
A19−A0
t ASD1 t ASD2 t AH
AS
t AS1
t RDD1 t RDD2 t AH
RD (read)
t AS1
t ACC1 t RDS t RDH
D15−D0 (read)
t WRD1 t WRD2 t AH
t WRW1
HWR, LWR
(write) t AS2
t WDD t WDH
D15−D0 (write)
Rev. 3.0, 02/99, page 742 of 904

T1 T2 T3
A19−A0
AS
RD
(read)
t ACC2
D15−D0
(read)
t WRD3
t WRW2
HWR, LWR
(write) t AS3
t WDS
D15−D0
(write)
Rev. 3.0, 02/99, page 743 of 904

T1 T2 TW T3
A19−A0
AS
RD
(read)
D15−D0
(read)
HWR, LWR
(write)
D15−D0
(write)
WAIT
Rev. 3.0, 02/99, page 744 of 904

24.3.2 Control Signal Timing (H8/539F A-Mask Model)

Figure 24-8 shows the input timing for NMI, ,540, and ,541 to ,543.
t RESS t RESS
RES
t MDS t RESW
MD2−MD0 ,
FWE*
Note: * The FWE input timing shown is for entering and exiting boot mode.
t NMIS t NMIH
NMI
t IRQ1S t IRQ1H
IRQ1−IRQ3
t IRQ0S
IRQ0
Rev. 3.0, 02/99, page 745 of 904

φ
tBRQS t BRQS
BREQ
t BACD1 t BACD2
BACK
t BZD t BZD
A19−A0,
AS, RD,
HWR,
LWR
Rev. 3.0, 02/99, page 746 of 904

24.3.3 Clock Timing (H8/539F A-Mask Model)

VCC
STBY
t OSC1 t OSC1
RES
4.5V
VCC
VIH
STBY
EXTAL
RES
tDEXT*
Note: * tDEXT includes 20 tcyc (min.) RES pulse width.
Rev. 3.0, 02/99, page 747 of 904

24.3.4 I/O Port Timing (H8/539F A-Mask Model)

T1 T2 T3
t PRS t PRH
Ports 1 to C
(read)
t PWD
Ports 1 to 7
and A to C
(write)

TCNT Compare-match
t PWDD
PW1 to 3
Rev. 3.0, 02/99, page 748 of 904

24.3.6 IPU Timing (H8/569F A-Mask Model)

t TOCD
Output
compare* 1
t TICS
Input
capture* 2

2. T1IOC1 to T7IOC2
t TCKS
TCLK1-TCLK3
t TCKW t TCKW
Rev. 3.0, 02/99, page 749 of 904

24.3.7 SCI Input/Output Timing (H8/569F A-Mask Model)

t SCKW
SCK1, SCK2
t scyc
t scyc
SCK1, SCK2
t TXD
TXD1, TXD2
(transmit data)
t RXS t RXH
RXD1, RXD2
(receive data)

Rev. 3.0, 02/99, page 750 of 904

Appendix A Instruction Set
A.1 Instruction List

Operand Notation
Rd General register (destination)

Rs General register (source)
Rn General register
(EAd) Destination operand
(EAs) Source operand
CCR Condition code register
N N (negative) bit in CCR
Z Z (zero) bit in CCR
V V (overflow) bit in CCR
C C (carry) bit in CCR
CR Control register
PC Program counter
CP Code page register
SP Stack pointer
FP Frame pointer
#IMM Immediate data
disp Displacement
+ Add
− Subtract
× Multiply
÷ Divide
∧ Logical AND
∨ Logical OR
⊕ Exclusive logical OR
→ Move
↔ Exchange
¬ Logical NOT
Rev. 3.0, 02/99, page 751 of 904

Condition Code Notation
↔
Changed according to execution result

0 Cleared to 0
 Previous value remains unchanged
Varies depending on conditions
Rev. 3.0, 02/99, page 752 of 904

Size CCR Bits
Mnemonic Operation
B/W N Z V C
(EAs) → Rd −
↔
MOV:G B/W 0
Rs → (EAd)
#IMM → (EAd)
#IMM → Rd −
↔ ↔
↔ ↔
MOV:E (short format) B 0
MOV: F @(d:8,FP) → Rd B/W 0 −
Data transfer instructions
Rs → @(d:8,FP) (short format)

#IMM → Rd −
↔ ↔ ↔
↔ ↔ ↔
MOV:I (short format) W 0
MOV:L (@aa:8) → Rd (short format) B/W 0 −
MOV:S Rs → (@aa:8) (short format) B/W 0 −
LDM @SP+ → Rn (register list) W − − − −
STM Rn (register list) → @−SP W − − − −
XCH Rs ↔ Rd W − − − −
Rd (upper byte) ↔ Rd (lower byte) −
↔
SWAP B 0
(MOVTPE) Not available in H8/539F
(MOVFPE) Not available in H8/539F
Rd+ (EAs) → Rd
↔ ↔
↔ ↔
↔ ↔
↔ ↔
ADD:G B/W
ADD:Q (EAd) +#IMM → (EAd) B/W
(#IMM = ±1, ±2) (short format)
ADDS Rd+ (EAs) → Rd B/W − − − −
(Rd is always word size)
Rd+ (EAs) +C → Rd
↔
↔ ↔ ↔
↔ ↔ ↔
ADDX B/W
Arithmetic instructions
DADD (Rd) 10+ (Rs) 10+C → (Rd) 10 B − −

Rd− (EAs) → Rd
↔
SUB B/W
SUBS Rd− (EAs) → Rd B/W − − − −
Rd− (EAs) − C → Rd
↔
↔ ↔ ↔
↔ ↔
SUBX B/W
DSUB (Rd) 10− (Rs) 10−C → (Rd) 10 B − −
Rd × (EAs) → Rd 8×8
↔
MULXU B/W 0 0
(unsigned) 16 × 16
Rd ÷ (EAs) → Rd 16 ÷ 8
↔
DIVXU B/W 0
(unsigned) 32 ÷16
Rd − (EAs), set CCR flags
↔
CMP:G B/W
(EAd) − #IMM, set CCR flags
Rev. 3.0, 02/99, page 753 of 904

Size CCR Bits
Mnemonic Operation
B/W N Z V C
Rd − #IMM, set CCR flags
↔ ↔ ↔
↔ ↔ ↔ ↔ ↔ ↔
↔ ↔
↔ ↔
CMP:E (short format) B
CMP:I Rd − #IMM, set CCR flags (short format) W
Arithmetic instructions
EXTS (<Bit 7> of <Rd>) → (<bits 15 to 8> of <Rd>) B 0 0

EXTU 0 → (<bits 15 to 8> of <Rd>) B 0 0 0
(EAd) − 0, set CCR flags
↔ ↔
TST B/W 0 0
0− (EAd) → (EAd)
↔
NEG B/W 0
CLR 0 → (EAd) B/W 0 1 0 0
(EAd) − 0, set CCR flags
↔
TAS B 0 0
(1) 2 → (<bit 7> of <EAd>)
↔
SHAL MSB LSB B/W
C 0
↔
SHAR MSB LSB B/W 0
0
↔
SHLL B/W 0
MSB LSB
C 0
↔
Shift instructions
SHLR B/W 0 0
MSB LSB
0 C
↔
↔
ROTL MSB LSB B/W 0
C
↔
ROTR MSB LSB B/W 0

C
↔
ROTXL MSB LSB B/W 0

C
↔
ROTXR MSB LSB B/W 0

C
Rev. 3.0, 02/99, page 754 of 904

Size CCR Bits
Mnemonic Operation
B/W N Z V C
Rd ∧ (EAs) → Rd −
Bit manipulation instructions Logic instructions
↔ ↔ ↔ ↔
↔ ↔ ↔ ↔ ↔
AND B/W 0
OR Rd ∨ (EAs) → Rd B/W 0 −
XOR Rd ⊕ (EAs) → Rd B/W 0 −
NOT ¬ (EAd) → (EAd) B/W 0 −
BSET ¬ (<Bit No.> of <EAd>) → Z B/W − − −
1 → (<Bit No.> of <EAd>)
BCLR ¬ (<Bit No.> of <EAd>) → Z − − −
↔
B/W
0 → (<Bit No.> of <EAd>)
¬ (<Bit No.> of <EAd>) → Z − − −
↔ ↔
BTST B/W
BNOT ¬ (<Bit No.> of <EAd>) → Z B/W − − −
→ (<Bit No.> of <EAd>)
Bcc If condition is true then − − − − −
PC + disp → PC
else next;
Mnemonic Description Condition

BRA (BT) Always (true) True
BRN (BF) Never (false) False
BHI High C∨Z=0
BLS Low or same C∨Z=1
Bcc (BHS) Carry clear C=0
(high or same)
Branch instructions
BCS (BLO) Carry set (low) C=1

BNE Not equal Z=0
BEQ Equal Z=1
BVC Overflow clear V=0
BVS Overflow set V=1
BPL Plus N=0
BMI Minus N=1
BGE Greater or equal N ⊕V = 0
BLT Less than N ⊕V = 1
BGT Greater than Z ∨ (N ⊕ V) = 0
BLE Less or equal Z ∨ (N ⊕ V) = 1
Rev. 3.0, 02/99, page 755 of 904

Size CCR Bits
Mnemonic Operation
B/W N Z V C
JMP Effective address → PC − − − − −
PJMP Effective address → CP, PC − − − − −
BSR PC → @ − SP − − − − −
PC + disp → PC
JSR PC → @ − SP − − − − −
Effective address → PC
PJSR PC → @ − SP − − − − −
CP → @ − SP
Effective address → CP, PC
RTS @SP + → PC − − − − −
Branch instructions
PRTS @SP + → CP − − − − −
@SP + → PC
RTD @SP + → PC − − − − −
SP + #IMM → SP
PRTD @SP + → CP − − − − −
@SP + → PC
SP + #IMM → SP
SCB If condition is true then next; − − − − −
SCB/F else Rn − 1 → Rn;
SCB/NE If Rn = −1 then next
SCB/EQ else PC + disp → PC;

SCB/F False
SCB/NE Not equal Z=0
SCB/EQ Equal Z=1
Rev. 3.0, 02/99, page 756 of 904

Size CCR Bits
Mnemonic Operation
B/W N Z V C
TRAPA PC → @−SP − − − − −
(If Max. mode then CP → @−SP)
SR → @−SP
(If Max. mode then <vector> → CP)
<Vector> → PC
TRAP/VS If V bit = 1 then TRAP − − − − −
else next;
System control instructions
@SP + → SR −
↔
RTE
(If Max. mode then @SP + → CP)
@SP + → PC
LINK FP (R6) → @ − SP − − − − −
SP → FP (R6)
SP + #IMM → SP
UNLK FP (R6) → SP − − − − −
@SP + → FP
SLEEP Normal operating mode → power-down state − − − − −
LDC (EAs) → CR B/W*
STC CR → (EAd) B/W* − − − −
ANDC CR ∧ #IMM → CR B/W*
ORC CR ∨ #IMM → CR B/W*
XORC CR ⊕ #IMM → CR B/W*
NOP PC + 1 → PC − − − − −
Note: * Depends on the control register.
Rev. 3.0, 02/99, page 757 of 904

A.2 Machine-Language Instruction Codes
Tables A-1 (a) to (d) indicate the machine-language code for each instruction.
How to Read Tables A-1 (a) to (d): The general format consists of an effective address (EA)
field followed by an operation code (OP) field.
Effective adress field Operation code field
1 2 3 4 5 6
Bytes 2, 3, 5, and 6 are not present in all instructions.
Address (high) Address (low)
Data (low)
3
dispL
Effective Address (EA) Field
Data (high)
Effective
Address
2
address (EA)
dispH
Data
disp
field
Operation code
0000Sz101
0001Sz101
00000100
00001100
1010Szrrr
1101Szrrr
1110Szrrr
@(d:16,Rn) 1111Szrrr
1011Szrrr
1100Szrrr
(OP) field
1
Addres-
sing Mode
@(d:8,Rn)
@aa:16
Operation Code (OP) Field

@aa:8
#xx:16
@Rn+
@−Rn
#xx:8
@Rn
Instruction
Rn
4 5 6
MOV:G.B <EAs>,Rd 2 2 3 4 2 2 3 4 3 10000rdrdrd
MOV:G.W <EAs>,Rd 2 2 3 4 2 2 3 4 4 10000rdrdrd
Data transfer
MOV:G.B Rs,<EAd> 2 3 4 2 2 3 4 10010rsrsrs

MOV:G.W Rs,<EAd> 2 3 4 2 2 3 4 10010rsrsrs
MOV:G.B #xx:8,<EAd> 3 4 5 3 3 4 5 00000110 Data
MOV:G.W #xx:16,<EAd> 4 5 6 4 4 5 6 00000111 Data (high) Data (low)
LDM.W @SP+, <register list> 2 00000010 Register list
Shading indicates addressing

Byte length of instruction modes that cannot be specified
in the instruction.
In special-format instructions the operation code field precedes the effective address field.
Rev. 3.0, 02/99, page 758 of 904

The following notation is used in the tables:
• Sz: operand size designation (byte or word)

Sz = 0: byte size
Sz = 1: word size
• rrr: general register number field
rrr Sz = 0 (byte) Sz = 1 (word)
15 8 7 0 15 0
000 Not used R0 R0
001 Not used R1 R1
010 Not used R2 R2
011 Not used R3 R3
100 Not used R4 R4
101 Not used R5 R5
110 Not used R6 R6
111 Not used R7 R7
• ccc: control register number field

ccc Sz = 0 (byte) Sz = 1 (word)
000 (disallowed*) 15 0
SR
15 8 7 0
001 Not used CCR (disallowed*)
010 (disallowed*) (disallowed*)
011 Not used BR (disallowed*)
100 Not used EP (disallowed*)
101 Not used DP (disallowed*)
110 (disallowed*) (disallowed*)
111 Not used TP (disallowed*)
Note: * Do not use combinations marked as disallowed, since they may cause incorrect operation.
Rev. 3.0, 02/99, page 759 of 904

• d: direction of transfer
d = 0: load
d = 1: store
• Register list: a byte in which bits indicate general registers as follows.
Bit 7 6 5 4 3 2 1 0
R7 R6 R5 R4 R3 R2 R1 R0
• #VEC: four bits specifying a vector number from 0 to 15. These vector numbers designate
vector addresses as follows:
Vector Address
#VEC Minimum Mode Maximum Mode
0 H'0020-H'0021 H'0040-H'0043
1 H'0022-H'0023 H'0044-H'0047
2 H'0024-H'0025 H'0048-H'004B
3 H'0026-H'0027 H'004C-H'004F
4 H'0028-H'0029 H'0050-H'0053
5 H'002A-H'002B H'0054-H'0057
6 H'002C-H'002D H'0058-H'005B
7 H'002E-H'002F H'005C-H'005F
8 H'0030-H'0031 H'0060-H'0063
9 H'0032-H'0033 H'0064-H'0067
A H'0034-H'0035 H'0068-H'006B
B H'0036-H'0037 H'006C-H'006F
C H'0038-H'0039 H'0070-H'0073
D H'003A-H'003B H'0074-H'0077
E H'003C-H'003D H'0078-H'007B
F H'003E-H'003F H'007C-H'007F
Rev. 3.0, 02/99, page 760 of 904

Examples of Machine-Language Instruction Codes
Example 1: ADD:G.B @R0, R1
EA Field OP Field Remarks

Table A-1 1101Szrrr 00100rdrdrd ADD:G.B @Rs, Rd instruction code
Instruction code 11010000 00100001 Sz = 0 (byte)
Rs = R0, Rd = R1
H'D021
Example 2: ADD:G.W @H'11:8, R1
EA Field OP Field Remarks

Table A-1 0000Sz101 00010001 00100rdrdrd ADD:G.W @aa:8, Rd
instruction code
Instruction code 00001101 00010001 00100001 Sz = 1 (word)
aa = H'11, Rd = R1
H'0D1121
Rev. 3.0, 02/99, page 761 of 904

Table A-1 (a) Machine-Language Instruction Codes [General Format] (1)
Data (low)
3
dispL
Data (high)
Address
2
dispH
Data
disp
0000Sz101
0001Sz101
00000100
00001100
1010Szrrr
1101Szrrr
1110Szrrr
1011Szrrr
1100Szrrr
1
Addres-
sing Mode
@(d:8,Rn)
@aa:16
@aa:8
#xx:16
@Rn+
@−Rn
#xx:8
@Rn
Instruction
Rn
4 5 6
MOV:G.B <EAs>,Rd 2 2 3 4 2 2 3 4 3 10000rdrdrd
MOV:G.W <EAs>,Rd 2 2 3 4 2 2 3 4 4 10000rdrdrd
MOV:G.B Rs,<EAd> 2 3 4 2 2 3 4 10010rsrsrs
MOV:G.W Rs,<EAd> 2 3 4 2 2 3 4 10010rsrsrs
MOV:G.B #xx:8,<EAd> 3 4 5 3 3 4 5 00000110 Data
MOV:G.W #xx:8,<EAd> 3 4 5 3 3 4 5 00000110 Data
Data transfer
MOV:G.W #xx:16,<EAd> 4 5 6 4 4 5 6 00000111 Data (high) Data (low)

LDM.W @SP+, <register list> 2 00000010 Register list
STM.W <register list> @−SP 2 00010010 Register list
XCH.W Rs,Rd 2 10010rdrdrd
SWAP.B Rd 2 00010000
(MOVTPE.B Rs,<EAd>)*1 3 4 5 3 3 4 5 00000000 10010rs rs rs
(MOVFPE.B <EAs>,Rd)*1 3 4 5 3 3 4 5 00000000 10000rdrdrd
ADD:G.B <EAs>,Rd 2 2 3 4 2 2 3 4 3 00100rdrdrd
ADD:G.W <EAs>,Rd 2 2 3 4 2 2 3 4 4 00100rdrdrd
ADD:Q.B #1,<EAd>*2 2 2 3 4 2 2 3 4 00001000
ADD:Q.W #1,<EAd>*2 2 2 3 4 2 2 3 4 00001000
Arithmetic operations
ADD:Q.B #2,<EAd>*2 2 2 3 4 2 2 3 4 00001001

ADD:Q.W #2,<EAd>*2 2 2 3 4 2 2 3 4 00001001
ADD:Q.B #−1,<EAd>*2 2 2 3 4 2 2 3 4 00001100
ADD:Q.W #−1,<EAd>*2 2 2 3 4 2 2 3 4 00001100
ADD:Q.B #−2,<EAd>*2 2 2 3 4 2 2 3 4 00001101
ADD:Q.W #−2,<EAd>*2 2 2 3 4 2 2 3 4 00001101
ADDS.B <EAs>,Rd 2 2 3 4 2 2 3 4 3 00101rdrdrd
ADDS.W <EAs>,Rd 2 2 3 4 2 2 3 4 4 00101rdrdrd
ADDX.B <EAs>,Rd 2 2 3 4 2 2 3 4 3 10100rdrdrd
ADDX.W <EAs>,Rd 2 2 3 4 2 2 3 4 4 10100rdrdrd
Notes: 1. Not available in the H8/539F.

2. Short format.
Rev. 3.0, 02/99, page 762 of 904

Table A-1 (a) Machine-Language Instruction Codes [General Format] (cont) (2)
Data (low)
3
dispL
Data (high)
Address
2
dispH
Data
disp
0000Sz101
0001Sz101
00000100
00001100
1010Szrrr
1101Szrrr
1110Szrrr
1011Szrrr
1100Szrrr
1
Addres-
sing Mode
@(d:8,Rn)
@aa:16
@aa:8
#xx:16
@Rn+
@-Rn
#xx:8
@Rn
Instruction
Rn
4 5 6
DADD.B Rs,Rd 3 00000000 10100rdrdrd
SUB.B <EAs>,Rd 2 2 3 4 2 2 3 4 3 00110rdrdrd
SUB.W <EAs>,Rd 2 2 3 4 2 2 3 4 4 00110rdrdrd
SUBS.B <EAs>,Rd 2 2 3 4 2 2 3 4 3 00111rdrdrd
SUBS.W <EAs>,Rd 2 2 3 4 2 2 3 4 4 00111rdrdrd
SUBX.B <EAs>,Rd 2 2 3 4 2 2 3 4 3 10110rdrdrd
SUBX.W <EAs>,Rd 2 2 3 4 2 2 3 4 4 10110rdrdrd
DSUB.B Rs,Rd 3 00000000 10110rdrdrd
MULXU.B <EAs>,Rd 2 2 3 4 2 2 3 4 3 10101rdrdrd
MULXU.W <EAs>,Rd 2 2 3 4 2 2 3 4 4 10101rdrdrd
Arithmetic operations
DIVXU.B <EAs>,Rd 2 2 3 4 2 2 3 4 3 10111rdrdrd

DIVXU.W <EAs>,Rd 2 2 3 4 2 2 3 4 4 10111rdrdrd
CMP:G.B <EAs>,Rd 2 2 3 4 2 2 3 4 3 01110rdrdrd
CMP:G.W <EAs>,Rd 2 2 3 4 2 2 3 4 4 01110rdrdrd
CMP:G.B #xx,<EAd> 3 4 5 3 3 4 5 00000100 Data
CMP:G.W #xx,<EAd> 4 5 6 4 4 5 6 00000101 Data (high) Data (low)
EXTS.B Rd 2 00010001
EXTU.B Rd 2 00010010
TST.B <EAd> 2 2 3 4 2 2 3 4 00010110
TST.W <EAd> 2 2 3 4 2 2 3 4 00010110
NEG.B <EAd> 2 2 3 4 2 2 3 4 00010100
NEG.W <EAd> 2 2 3 4 2 2 3 4 00010100
CLR.B <EAd> 2 2 3 4 2 2 3 4 00010011
CLR.W <EAd> 2 2 3 4 2 2 3 4 00010011
TAS.B <EAd> 2 2 3 4 2 2 3 4 00010111
Rev. 3.0, 02/99, page 763 of 904

Data (low)
3
dispL
Data (high)
Address
2
dispH
Data
disp
0000Sz101
0001Sz101
00000100
00001100
1010Szrrr
1101Szrrr
1110Szrrr
1011Szrrr
1100Szrrr
1
Addres-
sing Mode
@(d:8,Rn)
@aa:16
@aa:8
#xx:16
@Rn+
@−Rn
#xx:8
@Rn
Instruction
Rn
4 5 6
SHAL.B <EAd> 2 2 3 4 2 2 3 4 00011000
SHAL.W <EAd> 2 2 3 4 2 2 3 4 00011000
SHAR.B <EAd> 2 2 3 4 2 2 3 4 00011001
SHAR.W <EAd> 2 2 3 4 2 2 3 4 00011001
SHLL.B <EAd> 2 2 3 4 2 2 3 4 00011010
SHLL.W <EAd> 2 2 3 4 2 2 3 4 00011010
SHLR.B <EAd> 2 2 3 4 2 2 3 4 00011011
Shift
SHLR.W <EAd> 2 2 3 4 2 2 3 4 00011011

ROTL.B <EAd> 2 2 3 4 2 2 3 4 00011100
ROTL.W <EAd> 2 2 3 4 2 2 3 4 00011100
ROTR.B <EAd> 2 2 3 4 2 2 3 4 00011101
ROTR.W <EAd> 2 2 3 4 2 2 3 4 00011101
ROTXL.B <EAd> 2 2 3 4 2 2 3 4 00011110
ROTXL.W <EAd> 2 2 3 4 2 2 3 4 00011110
ROTXR.B <EAd> 2 2 3 4 2 2 3 4 00011111
ROTXR.W <EAd> 2 2 3 4 2 2 3 4 00011111
AND.B <EAs>,Rd 2 2 3 4 2 2 3 4 3 01010rdrdrd
AND.W <EAs>,Rd 2 2 3 4 2 2 3 4 4 01010rdrdrd
Logic operations
OR.B <EAs>,Rd 2 2 3 4 2 2 3 4 3 01000rdrdrd

OR.W <EAs>,Rd 2 2 3 4 2 2 3 4 4 01000rdrdrd
XOR.B <EAs>,Rd 2 2 3 4 2 2 3 4 3 01100rdrdrd
XOR.W <EAs>,Rd 2 2 3 4 2 2 3 4 4 01100rdrdrd
NOT.B <EAd> 2 2 3 4 2 2 3 4 00010101
NOT.W <EAd> 2 2 3 4 2 2 3 4 00010101
Rev. 3.0, 02/99, page 764 of 904

Data (low)
3
dispL
Data (high)
Address
2
dispH
Data
disp
0000Sz101
0001Sz101
00000100
00001100
1010Szrrr
1101Szrrr
1110Szrrr
1011Szrrr
1100Szrrr
1
Addres-
sing Mode
@(d:8,Rn)
@aa:16
@aa:8
#xx:16
@Rn+
@−Rn
#xx:8
@Rn
Instruction
Rn
4 5 6
BSET.B #xx,<EAd> 2 2 3 4 2 2 3 4 1100 data
BSET.W #xx,<EAd> 2 2 3 4 2 2 3 4 1100 data
BSET.B Rs,<EAd> 2 2 3 4 2 2 3 4 01001rs rsrs
BSET.W Rs,<EAd> 2 2 3 4 2 2 3 4 01001rsrsrs
BCLR.B #xx,<EAd> 2 2 3 4 2 2 3 4 1101 data
BCLR.W #xx,<EAd> 2 2 3 4 2 2 3 4 1101 data
Bit operations
BCLR.B Rs,<EAd> 2 2 3 4 2 2 3 4 01011rsrsrs

BCLR.W Rs,<EAd> 2 2 3 4 2 2 3 4 01011rsrsrs
BTST.B #xx,<EAd> 2 2 3 4 2 2 3 4 1111 data
BTST.W #xx,<EAd> 2 2 3 4 2 2 3 4 1111 data
BTST.B Rs,<EAd> 2 2 3 4 2 2 3 4 01111rsrsrs
BTST.W Rs,<EAd> 2 2 3 4 2 2 3 4 01111rsrsrs
BNOT.B #xx,<EAd> 2 2 3 4 2 2 3 4 1110 data
BNOT.W #xx,<EAd> 2 2 3 4 2 2 3 4 1110 data
BNOT.B Rs,<EAd> 2 2 3 4 2 2 3 4 01101rsrsrs
BNOT.W Rs,<EAd> 2 2 3 4 2 2 3 4 01101rsrsrs
LDC.B <EAs>,CR 2 2 3 4 2 2 3 4 3 10001ccc
LDC.W <EAs>,CR 2 2 3 4 2 2 3 4 4 10001ccc
STC.B CR,<EAd> 2 2 3 4 2 2 3 4 10011ccc
System control
STC.W CR,<EAd> 2 2 3 4 2 2 3 4 10011ccc

ANDC.B #xx:8, CR 3 01011ccc
ANDC.W #xx:16, CR 4 01011ccc
ORC.B #xx:8, CR 3 01001ccc
ORC.W #xx16, CR 4 01001ccc
XORC.B #xx:8, CR 3 01101ccc
XORC.W #xx:16, CR 4 01101ccc
Rev. 3.0, 02/99, page 765 of 904

Table A-1 (b) Machine-Language Instruction Codes [Special Format: Short Format]
Machine-Language Code
Byte
Instruction Length 1 2 3 4
MOV:E.B #xx:8, Rd 2 01010rdrdrd Data
MOV:I.W #xx:16, Rd 3 01011rdrdrd Data (high) Data (low)
MOV:L.B @aa:8, Rd 2 01100rdrdrd Address (low)
MOV:L.W @aa:8, Rd 2 01101rdrdrd Address (low)
MOV:S.B Rs, @aa:8 2 01110rsrsrs Address (low)
MOV:S.W Rs, @aa:8 2 01111rsrsrs Address (low)
MOV:F.B @(d:8,R6), Rd 2 10000rdrdrd disp
MOV:F.W @(d:8,R6), Rd 2 10001rdrdrd disp
MOV:F.B Rs, @(d:8, R6) 2 10010rsrsrs disp
MOV:F.W Rs, @(d:8, R6) 2 10011rsrsrs disp
CMP:E #xx8, Rd 2 01000rdrdrd Data
CMP:I #xx16, Rd 3 01001rdrdrd Data (high) Data (low)
Rev. 3.0, 02/99, page 766 of 904

Table A-1 (c) Machine-Language Instruction Codes
[Special Format: Branch Instructions] (1)
Byte
Bcc d:8 BRA (BT) 2 00100000 disp
BRN (BF) 00100001 disp
BHI 00100010 disp
BLS 00100011 disp
BCC (BHS) 00100100 disp
BCS (BLO) 00100101 disp
BNE 00100110 disp
BEQ 00100111 disp
BVC 00101000 disp
BVS 00101001 disp
BPL 00101010 disp
BMI 00101011 disp
BGE 00101100 disp
BLT 00101101 disp
BGT 00101110 disp
BLE 00101111 disp
Bcc d:16 BRA (BT) 3 00110000 disp H disp L
BRN (BF) 00110001 disp H disp L
BHI 00110010 disp H disp L
BLS 00110011 disp H disp L
BCC (BHS) 00110100 disp H disp L
BCS (BLO) 00110101 disp H disp L
BNE 00110110 disp H disp L
BEQ 00110111 disp H disp L
BVC 00111000 disp H disp L
BVS 00111001 disp H disp L
BPL 00111010 disp H disp L
BMI 00111011 disp H disp L
BGE 00111100 disp H disp L
Rev. 3.0, 02/99, page 767 of 904

Table A-1 (c) Machine-Language Instruction Codes
[Special Format: Branch Instructions] (2)
Byte
Bcc d:16 BLT 3 00111101 disp H disp L
BGT 00111110 disp H disp L
BLE 00111111 disp H disp L
JMP @Rn 2 00010001 11010rrr
JMP @aa:16 3 00010000 Address (high) Address (low)
JMP @(d:8, Rn) 3 00010001 11100rrr disp
JMP @(d:16, Rn) 4 00010001 11110rrr disp H disp L
BSR d:8 2 00001110 disp
BSR d:16 3 00011110 disp H disp L
JSR @Rn 2 00010001 11011rrr
JSR @aa:16 3 00011000 Address (high) Address (low)
JSR @(d:8, Rn) 3 00010001 11101rrr disp
JSR @(d:16, Rn) 4 00010001 11111rrr disp H disp L
RTS 1 00011001
RTD #xx:8 2 00010100 Data
RTD #xx:16 3 00011100 Data (high) Data (low)
SCB/cc Rn,disp SCB/F 3 00000001 10111rrr disp
SCB/NE 00000110 10111rrr disp
SCB/EQ 00000111 10111rrr disp
PJMP @aa:24 4 00010011 Page Address (high) Address (low)
PJMP @Rn 2 00010001 11000rrr
PJSR @aa:24 4 00000011 Page Address (high) Address (low)
PJSR @Rn 2 00010001 11001rrr
PRTS 2 00010001 00011001
PRTD #xx:8 3 00010001 00010100 Data
PRTD #xx:16 4 00010001 00011100 Data (high) Data (low)
Rev. 3.0, 02/99, page 768 of 904

Table A-1 (d) Machine-Language Instruction Codes
[Special Format: System Control Instructions]
Byte
TRAPA #xx 2 00001000 0001 #VEC
TRAP/VS 1 00001001
PTE 1 00001010
LINK FP,#xx:8 2 00010111 Data
LINK FP,#xx:16 3 00011111 Data (high) Data (low)
UNLK FP 1 00001111
SLEEP 1 00011010
NOP 1 00000000
Rev. 3.0, 02/99, page 769 of 904

Table A-2 First Byte of Instruction Code
LO
HI 0 1 2 3 4 5 6 7 8 9 A B C D E F
NOP SCB/F LDM PJSR #xx:8 @aa:8.B SCB/NE SCB/EQ TRAPA TRAP/VS RTE #xx:16 @aa:8.W BSR UNLK
0
Table A-6 @aa:24 Table A-5 Table A-4 Table A-6 Table A-6 Table A-5 Table A-4 d:8
JMP Table A-6* STM PJMP RTD @aa:16.B LINK JSR RTS SLEEP RTD @aa:16.W BSR LINK
1
@aa:24 #xx:8 Table A-4 #xx:8 #xx:16 Table A-4 d:16 #xx:16
BRA BRN BHI BLS Bcc BCS BNE BEQ BVC BVS BPL BMI BGE BLT BGT BLE
Rev. 3.0, 02/99, page 770 of 904

A.3 Operation Code Map
2
d:8
BRA BRN BHI BLS Bcc BCS BNE BEQ BVC BVS BPL BMI BGE BLT BGT BLE
3
d:16
CMP:E #xx:8, Rn CMP:I #xx:16, Rn

4
R0 R1 R2 R3 R4 R5 R6 R7 R0 R1 R2 R3 R4 R5 R6 R7
MOV:E #xx:8,Rn MOV:I #xx:16,Rn
5
6 MOV:L.B @aa:8,Rn MOV:L.W @aa:8,Rn
7 MOV:S.B Rn,@aa:8 MOV:S.W Rn,@aa:8
8 MOV:F.B @(d:8,R6),Rn MOV:F.W @(d:8,R6),Rn
9 MOV:F.B Rn,@(d:8,R6) MOV:F.W Rn,@(d:8,R6)
A Rn (byte) Table A-3 Rn (word) Table A-3
B @-Rn (byte) Table A-4 (word) Table A-4

@-Rn
C @Rn+ (byte) Table A-4 @Rn+ (word) Table A-4
D @Rn (byte) Table A-4 @Rn (word) Table A-4
E @(d:8,Rn) (byte) Table A-4 @(d:8,Rn) (word) Table A-4
F @(d:16,Rn) (byte) Table A-4 @(d:16,Rn) (word) Table A-4
Note: * References to tables A-3 to A-6 indicate the table giving the second or a subsequent byte of the machine-language code.
H'11 is the first byte of the machine-language code of the following instructions:
JMP, JSR, PJMP, and PJSR in register indirect addressing mode;
JMP and JSR in register indirect addressing mode with displacement;
PRTS and PRTD.
effective adress (EA) and operation code (OP) fields but not the effective address extension.
Tables A-2 to A-6 show a map of the machine-language instruction codes. The map includes the
Table A-3 Second Byte of Axxx Instruction Codes
LO
HI 0 1 2 3 4 5 6 7 8 9 A B C D E F
Table A-6* ADD:Q ADD:Q ADD:Q ADD:Q
0 #2
#1 #−1 #−2
SWAP EXTS EXTU CLR NEG NOT TST TAS SHAL SHAR SHLL SHLR ROTL ROTR ROTXL ROTXR
1
ADD ADDS
2
SUB SUBS
3
OR BSET (register indirect specification of bit number)
4
AND BCLR (register indirect specification of bit number)

5
XOR BNOT (register indirect specification of bit number)
6
7 CMP BTST (register indirect specification of bit number)
8 MOV LDC
9 XCH STC
A ADDX MULXU
Rev. 3.0, 02/99, page 771 of 904
B SUBX DIVXU
C BSET (direct specification of bit number)

b0 b1 b2 b3 b4 b5 b6 b7 b8 b9 b10 b11 b12 b13 b14 b15
D BCLR (direct specification of bit number)
E BNOT (direct specification of bit number)
F BTST (direct specification of bit number)
Note: * Prefix code of the DADD and DSUB instructions. Table A-6 gives the third byte of the instruction code.
Rev. 3.0, 02/99, page 772 of 904 Table A-4 Second Byte of 05xx, 15xx, 0Dxx, 1Dxx, Bxxx, Cxxx, Dxxx, Exxx, and Fxxx Instruction Codes
LO
HI 0 1 2 3 4 5 6 7 8 9 A B C D E F
Table A-6* CMP CMP MOV MOV ADD:Q ADD:Q ADD:Q ADD:Q
0 #1 #2
#xx:8 #xx:16 #xx:8 #xx:16 #−1 #−2
CLR NEG NOT TST TAS SHAL SHAR SHLL SHLR ROTL ROTR ROTXL ROTXR
1
ADD ADDS
2
SUB SUBS
3
OR BSET (register indirect specification of bit number)
4
AND BCLR (register indirect specification of bit number)
5
XOR BNOT (register indirect specification of bit number)
6
7 CMP BTST (register indirect specification of bit number)
8 MOV (load) LDC
9 MOV (store) STC
A ADDX MULXU
B SUBX DIVXU
C BSET (direct specification of bit number)

b0 b1 b2 b3 b4 b5 b6 b7 b8 b9 b10 b11 b12 b13 b14 b15
D BCLR (direct specification of bit number)
E BNOT (direct specification of bit number)
F BTST (direct specification of bit number)
Note: * Prefix code of the DADD and DSUB instructions. Table A-6 gives the third byte of the instruction code.
Table A-5 Second Byte of 04xx and 0Cxx Instruction Codes
LO
HI 0 1 2 3 4 5 6 7 8 9 A B C D E F
ADD ADDS
2
SUB SUBS
3
OR ORC
4
5 AND ANDC
XOR XORC
6
7 CMP
8 MOV LDC
A ADDX MULXU
Rev. 3.0, 02/99, page 773 of 904
B SUBX DIVXU
F
Rev. 3.0, 02/99, page 774 of 904 Table A-6 Second or Third Byte of 11xx, 01xx, 06xx, 07xx, and xx00xx Instruction Codes
LO
HI 0 1 2 3 4 5 6 7 8 9 A B C D E F
0
PRTD PRTS PRTD
1
#xx:8 #xx:16
7
(MOVFPE)*
8
R0 R1 R2 R3 R4 R5 R6 R7
9 (MOVTPE)*
A DADD
B DSUB SCB
R0 R1 R2 R3 R4 R5 R6 R7
C PJMP @Rn PJSR @Rn
D JMP @Rn JSR @Rn
E JMP @ (d:8,Rn) JSR @ (d:8,Rn)
JMP @ (d:16,Rn) JSR @ (d:16,Rn)

F
Note: * Not available in the H8/539F.

A.4 Number of States Required for Execution
Tables A-7 (1) to (6) indicate the number of states required to execute each instruction in each
addressing mode. These tables are read as explained below. The values of I, J, and K are used to
calculate the number of execution states when the instruction is fetched from an external address
or an operand is written or read at an external address. Formulas for calculating the number of
states are given on the next page.
How to Read Table A-7
J + K is the number of instruction fetches Addressing Mode
@(d:16,Rn)
I is the total number of bytes
@(d:8,Rn)
written or read when the operand
@aa:16
@aa:8
#xx:16
@Rn+
@−Rn
is in memory
#xx:8
@Rn
Rn
Instruction I K 1 1 2 3 1 1 2 3 2 3
J
ADD.B 1 1 2 5 5 6 5 6 5 6 3
ADD.W 2 1 2 5 5 6 5 6 5 6 4
ADD:Q.B 2 1 2 7 7 8 7 8 7 8
ADD:Q.W 4 1 2 7 7 8 7 8 7 8
DADD 2 4
Shading in the I column indicates that Shading in these columns

the instruction cannot have a memory indicates addressing modes
operand. that cannot be specified for
the instruction.
Rev. 3.0, 02/99, page 775 of 904

Calculation of Number of States Required for Execution: One state is one cycle of the system
clock (φ). When φ = 10 MHz, one state is 100 ns.
Instruction Fetch Operand Read/Write Formula

16-bit-bus, 16-bit-bus, 2-state-access (value in table A-7) + (value in table A-8)
2-state-access area area or general register
16-bit-bus, 3-state-access Byte (value in table A-7) + (value in
area table A-8) + I
Word (value in table A-7) + (value in
table A-8) + I/2
8-bit-bus, 2-state-access Byte (value in table A-7) + (value
area or on-chip supporting intable A-8) + I
module Word (value in table A-7) + (value
intable A-8) + 2I
16-bit-bus, 16-bit-bus, 2-state-access (value in table A-7) + (value in table A-8) +
3-state-access area area or general register (J + K)/2
area table A-8) + I + (J + K)/2
Word (value in table A-7) + (value in
table A-8) + (I + J + K)/2
area or on-chip supporting table A-8) + I + (J + K)/2
module Word (value in table A-7) + (value in
table A-8) + 2I + (J + K)/2
8-bit-bus, 16-bit-bus, 2-state-access (value in table A-7) + 2 + (J + K)
3-state-access area area or general register
16-bit-bus, 3-state-access Byte (value in table A-7) + I + 2 (J + K)
area
Word (value in table A-7) + I/2 + 2 (J + K)
8-bit-bus, 2-state-access Byte (value in table A-7) + I + 2 (J + K)
area or on-chip supporting
Word (value in table A-7) + 2 (I + J + K)
module
Notes: 1. When an instruction is fetched from the 16-bit-bus access area, the number of states
differs by 1 or 2 depending on whether the instruction is stored at an even or odd
address. This point should be noted in software timing routines and other situations in
which the precise number of states must be known.
2. If wait states or Tp states are inserted in access to the 3-state-access area, add the
necessary number of states.
3. When an instruction is fetched from the 16-bit-bus 3-state-access area, fractions in the
term (J + K)/2 should be rounded up.
Rev. 3.0, 02/99, page 776 of 904

Examples of Calculation of Number of States Required for Execution
Example 1: Instruction fetched from 16-bit-bus, 2-state-access area
Formula
Assembler Notation (Value in Table
Operand Start A-7) + (Value in Execution
Read/Write Address Address Code Mnemonic Table A-8 (b)) States
16-bit-bus, Even H'0100 D821 ADD @R0,R1 5+1 6
2-state-
Odd H'0101 D821 ADD @R0,R1 5+0 5
access area
or general
register
Formula
Branch Assembler Notation (Value in Table
Operand destination A-7) + (Value in Execution
Read/Write Address Address Code Mnemonic Table A-8 (a)) + 2I States
On-chip Even H'FC00 11D8 JSR @R0 9+0+2×2 13
supporting
Odd H'FC01 11D8 JSR @R0 9+1+2×2 14
module or
8-bit-bus,
3-state-
access area
(word)
Formula
Assembler Notation
Operand (Value in Table Execution
Read/Write Address Code Mnemonic A-7) + 2 (J + K) States
16-bit-bus, H'9002 D821 ADD @R0,R1 5 + 2 × (1 + 1) 9
2-state-access
area or general
register
Rev. 3.0, 02/99, page 777 of 904

Formula
(Value in Table
Assembler Notation A-7) + (Value in
Operand Start Table A-8 (b)) + Execution
Read/Write Address Address Code Mnemonic (J + K)/2 States
16-bit-bus, Even H'0100 D821 ADD @R0,R1 5 + 1 + (1 + 1)/2 7
2-state-
Odd H'0101 D821 ADD @R0,R1 5 + 0 + (1 + 1)/2 6
access area
or general
register
Rev. 3.0, 02/99, page 778 of 904

Table A-7 Number of States Required for Instruction Execution (1)
Addressing Mode
@(d:16,Rn)
@(d:8,Rn)
@aa:16
@aa:8
#xx:16
@Rn+
@−Rn
#xx:8
@Rn
Rn
Instruction I K 1 1 2 3 1 1 2 3 2 3
J
ADD:G.B <EAs>,Rd 1 1 2 5 5 6 5 6 5 6 3
ADD:G.W <EAs>,Rd 2 1 2 5 5 6 5 6 5 6 4
ADD:Q.B #xx, <EAd> 2 1 2 7 7 8 7 8 7 8
ADD:Q.W #xx, <EAd> 4 1 2 7 7 8 7 8 7 8
ADDS.B <EAs>, Rd 1 1 3 5 5 6 5 6 5 6 3
ADDS.W <EAs>, Rd 2 1 3 5 5 6 5 6 5 6 4
ADDX.B <EAs>, Rd 1 1 2 5 5 6 5 6 5 6 3
ADDX.W <EAs>, Rd 2 1 2 5 5 6 5 6 5 6 4
AND.B <EAs>, Rd 1 1 2 5 5 6 5 6 5 6 3
AND.W <EAs>, Rd 2 1 2 5 5 6 5 6 5 6 4
ANDC #xx,CR 1 5 9
BCLR.B #xx, <EAd> * 2 1 4 7 7 8 7 8 7 8
BCLR.W #xx, <EAd> * 4 1 4 7 7 8 7 8 7 8
BNOT.B #xx, <EAd> * 2 1 4 7 7 8 7 8 7 8
BNOT.W #xx, <EAd> * 4 1 4 7 7 8 7 8 7 8
BSET.B #xx, <EAd> * 2 1 4 7 7 8 7 8 7 8
BSET.W #xx, <EAd> * 4 1 4 7 7 8 7 8 7 8
BTST.B #xx, <EAd> * 1 1 3 5 5 6 5 6 5 6
BTST.W #xx, <EAd> * 2 1 3 5 5 6 5 6 5 6
CLR.B <EAd> 1 1 2 5 5 6 5 6 5 6
CLR.W <EAd> 2 1 2 5 5 6 5 6 5 6
CMP:G.B <EAs>,Rd 1 1 2 5 5 6 5 6 5 6 3
CMP:G.W <EAs>,Rd 2 1 2 5 5 6 5 6 5 6 4
CMP:G.B #xx:8, <EA> 1 2 6 6 7 6 7 6 7
CMP:G.B #xx:16, <EA> 2 3 7 7 8 7 8 7 8
Note: * Rs can also be specified for the source operand.
Rev. 3.0, 02/99, page 779 of 904

Addressing Mode
@(d:16,Rn)
@(d:8,Rn)
@aa:16
@aa:8
#xx:16
@Rn+
@−Rn
#xx:8
@Rn
Rn
Instruction I K 1 1 2 3 1 1 2 3 2 3
J
CMP:E #xx:8,Rd 0 2
CMP:I #xx:16,Rd 0 3
DADD Rs,Rd 2 4
DIVXU.B <EAs>,Rd 1 1 20 23 23 24 23 24 23 24 21
DIVXU.W <EAs>,Rd 2 1 26 29 29 30 29 30 29 30 28
DSUB Rs,Rd 2 4
EXTS Rd 1 3
EXTU Rd 1 3
LDC.B <EAs>,CR 1 1 3 6 6 7 6 7 6 7 4
LDC.W <EAs>,CR 2 1 4 7 7 8 7 8 7 8 6
MOV:G.B 1 1 2 5 5 6 5 6 5 6 3
MOV:G.W 2 1 2 5 5 6 5 6 5 6 4
MOV:G.B #xx:8,<EAd> 1 2 7 7 8 7 8 7 8
MOV:G.W #xx:16,<EAd> 2 3 8 8 9 8 9 8 9
MOV:E #xx:8,Rd 0 2
MOV:I #xx:16,Rd 0 3
MOV:L.B @aa:8,Rd 1 0 5
MOV:L.W @aa:8,Rd 2 0 5
MOV:S.B Rs,@aa:8 1 0 5
MOV:S.W Rs,@aa:8 2 0 5
MOV:F.B @(d:8,R6),Rd 1 0 5
MOV:F.W @(d:8,R6),Rd 2 0 5
MOV:F.B Rs,@(d:8,R6) 1 0 5
MOV:FW Rs,@(d:8,R6) 2 0 5
Rev. 3.0, 02/99, page 780 of 904

Addressing Mode
@(d:16,Rn)
@(d:8,Rn)
@aa:16
@aa:8
#xx:16
@Rn+
@−Rn
#xx:8
@Rn
Rn
Instruction I K 1 1 2 3 1 1 2 3 2 3
J
(MOVFPE <EAs>,Rd)* 0 2 13 13 14 13 14 13 14
20 20 21 20 21 20 21
(MOVTPE Rs,<EA>)* 0 2 13 13 14 13 14 13 14
20 20 21 20 21 20 21
MULXU.B <EAs>,Rd 1 1 16 19 19 20 19 20 19 20 18
MULXU.W <EAs>,Rd 2 1 23 25 25 26 25 26 25 26 25
NEG.B <EAd> 2 1 2 7 7 8 7 8 7 8
NEG.W <EAd> 4 1 2 7 7 8 7 8 7 8
NOT.B <EAd> 2 1 2 7 7 8 7 8 7 8
NOT.W <EAd> 4 1 2 7 7 8 7 8 7 8
OR.B <EAs>,Rd 1 1 2 5 5 6 5 6 5 6 3
OR.W <EAs>,Rd 2 1 2 5 5 6 5 6 5 6 4
ORC #xx,CR 1 5 9
ROTL.B <EAd> 2 1 2 7 7 8 7 8 7 8
ROTL.W <EAd> 4 1 2 7 7 8 7 8 7 8
ROTR.B <EAd> 2 1 2 7 7 8 7 8 7 8
ROTR.W <EAd> 4 1 2 7 7 8 7 8 7 8
ROTXL.B <EAd> 2 1 2 7 7 8 7 8 7 8
ROTXL.W <EAd> 4 1 2 7 7 8 7 8 7 8
ROTXR.B <EAd> 2 1 2 7 7 8 7 8 7 8
ROTXR.W <EAd> 4 1 2 7 7 8 7 8 7 8
SHAL.B <EAd> 2 1 2 7 7 8 7 8 7 8
SHAL.W <EAd> 4 1 2 7 7 8 7 8 7 8
SHAR.B <EAd> 2 1 2 7 7 8 7 8 7 8
SHAR.W <EAd> 4 1 2 7 7 8 7 8 7 8
SHILL.B <EAd> 2 1 2 7 7 8 7 8 7 8
SHLL.W <EAd> 4 1 2 7 7 8 7 8 7 8
Note: * Not available in the H8/539F.
Rev. 3.0, 02/99, page 781 of 904

Addressing Mode
@(d:16,Rn)
@(d:8,Rn)
@aa:16
@aa:8
#xx:16
@Rn+
@−Rn
#xx:8
@Rn
Rn
Instruction I K 1 1 2 3 1 1 2 3 2 3
J
SHLR.B <EAd> 2 1 2 7 7 8 7 8 7 8
SHLR.W <EAd> 4 1 2 7 7 8 7 8 7 8
STC.B CR,<EAd> 1 1 4 7 7 8 7 8 7 8
STC.W CR,<EAd> 2 1 4 7 7 8 7 8 7 8
SUB.B <EAs>,Rd 1 1 2 5 5 6 5 6 5 6 3
SUB.W <EAs>,Rd 2 1 2 5 5 6 5 6 5 6 4
SUBS.B <EAs>,Rd 1 1 3 5 5 6 5 6 5 6 3
SUBS.W <EAs>,Rd 2 1 3 5 5 6 5 6 5 6 4
SUBX.B <EAs>,Rd 1 1 2 5 5 6 5 6 5 6 3
SUBX.W <EAs>,Rd 2 1 2 5 5 6 5 6 5 6 4
SWAP Rd 1 3
TAS <EAd> 2 1 4 7 7 8 7 8 7 8
TST.B <EAd> 1 1 2 5 5 6 5 6 5 6
TST.W <EAd> 2 1 2 5 5 6 5 6 5 6
XCH Rs,Rd 1 4
XOR.B <EAs>,Rd 1 1 2 5 6 5 5 6 5 6 3
XOR.W <EAs>,Rd 2 1 2 5 6 5 5 6 5 6 4
XORC #xx,CR 1 5 9
*
6
DIVXU.B zero divide, minimum mode 1 20 23 23 24 23 24 23 24 21
7
10
DIVXU.B zero divide, maximum mode 1 25 28 28 29 28 29 28 29 21
11
6
DIVXU.W zero divide, minimum mode 1 20 23 23 24 23 24 23 24 27
8
10
DIVXU.W zero divide, maximum mode 1 25 28 28 29 28 29 28 29 27
12
DIVXU.B overflow 1 1 8 11 11 12 11 12 11 12 9
DIVXU.W overflow 2 1 8 11 11 12 11 12 11 12 10
Note: * Register operand or immediate data
Memory operand
Rev. 3.0, 02/99, page 782 of 904

Instruction (Condition) Execution States I J+K

Bcc d:8 Condition false, branch not taken 3 2
Condition true, branch taken 7 5
Bcc d:16 Condition false, branch not taken 3 3
Condition true, branch taken 7 6
BSR d:8 9 2 4
d:16 9 2 5
JMP @aa:16 7 5
@Rn 6 5
@(d:8,Rn) 7 5
@(d:16,Rn) 8 6
JSR @aa:16 9 2 5
@Rn 9 2 5
@(d:8,Rn) 9 2 5
@(d:16,Rn) 10 2 6
LDM 6 + 4n* 2n 2
LINK #xx:8 6 2 2
#xx:16 7 2 3
NOP 2 1
RTD #xx:8 9 2 4
#xx:16 9 2 5
RTE Minimum mode 13 4 4
Maximum mode 15 6 4
RTS 8 2 4
SCB Condition true, branch not taken 3 3
Count = −1, branch not taken 4 3
Other conditions, branch taken 8 6
SLEEP Until transition to sleep mode 2 0
STM 6 + 3n* 2n 2
TRAPA Minimum mode 17 6 4
Maximum mode 22 10 4
Note: * n: number of registers in register list
Rev. 3.0, 02/99, page 783 of 904

Instruction Condition Execution States I J+K

TRAP/VS V = 0, branch not taken 3 1
V = 1, branch taken, minimum mode 18 6 4
V = 1, branch taken, maximum mode 23 10 4
UNLK 5 2 1
PJMP @aa:24 9 6
@Rn 8 5
PJSR @aa:24 15 4 6
@Rn 13 4 5
PRTS 12 4 5
PRTD #xx:8 13 4 5
#xx:16 13 4 6
Table A-8 (a) Correction Values (Branch Instructions)
Instruction Branch Address Correction
BSR,JMP,JSR,RTS,RTD,RTE, Even 0
TRAPA,PJMP,PJSR,PRTS,PRTD Odd 1
Even 0
Bcc,SCB,TRAP/VS (if branch is taken)
Odd 1
Table A-8 (b) Correction Values (General Instructions, for Each Addressing Mode)
Start @(d:8, @(d:16,

Instruction Rn @Rn @−Rn @Rn+ @aa:8 @aa:16 #xx:8 #xx:16
Address Rn Rn
MOV.B #xx:8 <EA> Even 1 1 1 1 1 1 1
MOVTPE,MOVFPE Odd 1 1 1 1 1 1 1
MOV.W #xx:16 <EA> Even 2 0 2 2 2 0 2
Odd 0 2 0 0 0 2 0
All other insructions Even 0 1 0 1 1 1 0 1 0 0
Odd 0 0 1 0 0 0 1 0 0 0
Rev. 3.0, 02/99, page 784 of 904

A.5 Instruction Set
A.5.1 Features
Features of the H8/500 CPU instruction set are as follows:
• General-register architecture
• Highly orthogonal instruction set
• 1.5-address instructions
• C-oriented instruction set
A.5.2 Instruction Types
The H8/500 CPU instruction set consists of 63 instructions. Table A-9 classifies the instruction
set.
Table A-9 Instruction Types
Number of
Type Instructions Instructions
Data transfer MOV LDM STM XCH SWAP MOVTPE MOVFPE 7
Arithmetic operations ADD SUB ADDS SUBS ADDX SUBX DADD DSUB 17
MULXU DIVXU CMP EXTS EXTU TST NEG CLR
TAS
Logic operations AND OR XOR NOT 4
Shift SHAL SHAR SHLL SHLR ROTL ROTR ROTXL 8
ROTXR
Bit manipulation BSET BCLR BTST BNOT 4
Branch Bcc* JMP PJMP BSR JSR PJSR RTS PRTS RTD 11
PRTD SCB(/F/NE/EQ)
System control TRAPA TRAP/VS RTE SLEEP LDC STC ANDC ORC 12
XORC NOP LINK UNLK
Note: * Bcc is the generic designation for a conditional branch instruction.
Rev. 3.0, 02/99, page 785 of 904

A.5.3 Basic Instruction Formats
There are two kinds of basic instruction format, general and special.
(1) General Format: This format consists of an effective address (EA) field, an effective address
extension field, and an operation code (OP) field. The effective address is placed before the
operation code because this results in faster execution of the instruction. Table A-10 describes the
three fields of the general instruction format.
Effective address Effective address extension Operation code
Table A-10 Fields in General Instruction Format
Name Byte Length Description

EA field 1 Information used to calculate the effective address
EA extension 0-2 Byte length is defined in EA field
Displacement value, immediate data, or absolute
address
OP field 1-3 Defines the operation carried out on the operand
Some instructions (DADD, DSUB, MOVFPE, MOVTPE)
have an extended format in which the operand code is
receded by a one-byte prefix code (example 1)
Example 1: Instruction with prefix code: DADD instruction
Effective address Prefix code Operation code
1 0 1 0 0 r r r 0 0 0 0 0 0 0 0 1 0 1 0 0 r r r
(2) Special Format: In this format the operation code comes first, followed by the effective
address field and effective address extension. This format is used in branching instructions,
system control instructions, and some short-format instructions that can be executed faster if the
operation is specified before the operand. Table A-11 describes the three fields of the special
instruction format.
Operation code Effective address Effective address extension
Rev. 3.0, 02/99, page 786 of 904

Table A-11 Fields in Special Instruction Format
Name Byte Length Description

OP field 1-2 Defines the operation performed by the instruction
EA field and EA 0-3 Information used to calculate an effective address
extension
A.5.4 Data Transfer Instructions
There are seven data transfer instructions. The function of each instruction is described next.
(1) MOV Instruction: Transfers data between two general registers, or between a general register
and memory. Can also transfer immediate data to a general register or memory.
Operation: (EAs) → (EAd),

#IMM → (EAd)
Registers (CPU) Memory
Rs
(EAd)
Example: MOV:G.W Rs, EAd
Instructions and Operand Sizes: The following table lists the possible combinations.
Size
Instruction B/W B W
MOV:G O
MOV:E O
MOV:F O
MOV:I O
MOV:L O
MOV:S O
B: Byte
W: Word
Rev. 3.0, 02/99, page 787 of 904

(2) LDM Instruction (W): Loads data saved on the stack into one or more registers. Multiple
registers can be loaded simultaneously.
Operation: @SP+ (stack) → Rn (register list)
R0
R1
SP
R2 R0
R3 R1
R2
(Old SP)
Example: LDM R0−R2, @SP+
Instructions and Operand Sizes: The operand size is always word size.
(3) STM Instruction (W): Saves data onto the stack. Multiple registers can be saved
simultaneously.
Operation: Rn (register list) → @SP+ (stack)
R0 SP
R1
R2 R0
R3 R1
R2
(Old SP)
Example: STM @SP+, R0−R2
Rev. 3.0, 02/99, page 788 of 904

(4) XCH Instruction (W): Exchanges data between two general registers.
Operation: Rs → Rd, Rd → Rs
Registers (CPU)
R0 A R0 B
R1 R1
R2 B R2 A
R3 R3
<Before execution> <After execution>
Example: XCH R0, R2
(5) SWAP Instruction (B): Exchanges data between the upper and lower bytes of a general
register.
Operation: Rd (upper byte) ↔ Rd (lower byte)
Registers (CPU)
R0 A B R0 B A
R1 R1
R2 R2
R3 R3
<Before execution> <After execution>
Example: SWAP R0
Instructions and Operand Sizes: The operand size is always byte size.
Rev. 3.0, 02/99, page 789 of 904

(6) MOVTPE Instruction (B): Transfers general register contents to memory in synchronization
with the E clock. (Note: The H8/539F does not output an E clock).
Operation: Rn → (EAd)
Rs
(EAd)
Example: MOVTPE Rs, EAd
(7) MOVFPE Instruction (B): Transfers memory contents to a general register in

synchronization with the E clock. (Note: The H8/539F does not output an E clock).
Operation: (EAs) → Rd
Rd
(EAs)
Example: MOVFPE EAs, Rd
Rev. 3.0, 02/99, page 790 of 904

A.5.5 Arithmetic Instructions
There are 17 arithmetic instructions. The function of each instruction is described next.
(1) ADD Instruction (B/W)
(2) SUB Instruction (B/W)
(3) ADDS Instruction (B/W)
(4) SUBS Instruction (B/W)
These instructions perform addition and subtraction on data in two general registers, data in a
general register and memory, data in a general register and immediate data, or data in memory and
immediate data.
Operation: Rd ± (EAs) → Rd, (EAd) ± #IMM → (EAd)
Registers (CPU)
Rd A
ALU A+1
Example: ADD.W #1, Rd
Instructions and Operand Sizes: Byte or word operand size can be selected.
(5) ADDX Instruction (B/W)
(6) SUBX Instruction (B/W)
These instructions perform addition and subtraction with carry on data in two general registers,
data in a general register and memory, or data in a general register and immediate data.
Rev. 3.0, 02/99, page 791 of 904

Operation: Rd ± (EAs) ± C → Rd
Registers (CPU)
Rd A
CCR C 1
ALU A+1+C
Example: ADDX.W #1, Rd
(7) DADD Instruction (B)
(8) DSUB Instruction (B)
These instructions perform decimal addition and subtraction on data in two general registers.
Operation: (Rd)10 ± (Rs)10 ± C → (Rd)10
Registers (CPU)
Rd A
Rs B
CCR C
ALU (A + B + C) 10
Example: DADD Rs, Rd
Rev. 3.0, 02/99, page 792 of 904

(9) MULXU Instruction (B/W): Performs 8-bit ´ 8-bit or 16-bit ´ 16-bit unsigned multiplication
on data in a general register and data in another general register or memory, or on data in a general
register and immediate data.
Operation: Rd × (EAs) → Rd
Registers (CPU)
Rd A Rd Result
Rs B Rs B
<After execution>
ALU A× B
Example: MULXU.B Rs, Rd
(10) DIVXU Instruction (B/W): Performs 16-bit ÷ 8-bit or 32-bit ÷ 16-bit unsigned division on
data in a general register and data in another general register or memory, or on data in a general
register and immediate data.
Operation: Rd ÷ (EAs) → Rd
Registers (CPU) Result
Rd A Rd
Rs B Rs B
<After execution>
ALU A÷ B
Example: DIVXU.B Rs, Rd
Rev. 3.0, 02/99, page 793 of 904

(11) CMP Instruction: Compares data in a general register with data in another general register
or memory, or with immediate data, or compares immediate data with data in memory.
Operation: Rd − (EAs), (EAd) − #IMM
Registers (CPU)
Rd A Left unchanged
Rs B
ALU A−B CCR

O, Z, N, V
Example: CMP:G.B Rs, Rd
Instructions and Operand Sizes: The following table lists the possible combinations.
Size
Instruction B/W B W
CMP:G O
CMP:E O
CMP:I O
B: Byte
W: Word
Rev. 3.0, 02/99, page 794 of 904

(12) EXTS Instruction (B): Converts byte data in a general register to word data by extending the
sign bit.
Operation: (<bit 7> of <Rd>) → (<bits 15 to 8> of <Rd>)
Registers (CPU)
15 87 0
R0 Don't care 1 0 1 1 0 1 0 1
(Before execution)
15 87 0
R0 1 1 1 1 1 1 1 1 1 0 1 1 0 1 0 1
(After execution) Sign extension
Example: EXTS R0
(13) EXTU Instruction (B): Converts byte data in a general register to word data by padding with
zero bits.
Operation: 0 → (<bits 15 to 8> of <Rd>)
Registers (CPU)
15 87 0
R0 Don't care 1 0 1 1 0 1 0 1
(Before execution)
15 87 0
R0 0 0 0 0 0 0 0 0 1 0 1 1 0 1 0 1
(After execution) Zero extension
Example: EXTU R0
Rev. 3.0, 02/99, page 795 of 904

(14) TST Instruction (B/W): Compares general register or memory contents with zero.
Operation: (EAd) − 0
Registers (CPU)
R0 A Left unchanged
ALU A−0 CCR

N, Z
Example: TST.W R0
(15) NEG Instruction (B/W): Obtains the two's complement of general register or memory
contents.
Operation: 0 − (EAd) → (EAd)
Registers (CPU)
R0 A R0 2's complement
0
<After execution>
ALU 0−A
Example: NEG.W R0
Rev. 3.0, 02/99, page 796 of 904

(16) CLR Instruction (B/W): Clears general register or memory contents to zero.
Operation: 0 → (EAd)
Registers (CPU)
15 0
R0 Don't care
(before execution)
15 0
R0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
(after execution) Cleared to zero
Example: CLR.W R0
(17) TAS Instruction (B): Tests general register or memory contents, then sets the most
significant bit (bit 7) to 1.
Operation: (EAd) − 0, (1)2 → (<bit 7> of <EAd>)
Registers (CPU)
R0 A
ALU A-0 CCR

N, Z
15 87 0
R0 Don't care 1 * * * * * * *
(after execution) Set to 1
Example: TAS R0
Rev. 3.0, 02/99, page 797 of 904

A.5.6 Logic Instructions
There are four logic instructions. The function of each instruction is described next.
(1) AND Instruction (B/W): Performs a logical AND operation on a general register and another
general register, memory, or immediate data.
Operation: Rd ∧ (EAs) → Rd
Registers (CPU) Result
Rd A Rd
Rs B Rs B
<After execution>
ALU A∧B
Example: AND.B Rs, Rd
(2) OR Instruction (B/W): Performs a logical OR operation on a general register and another
general register, memory, or immediate data.
Operation: Rd ∨ (EAs) → Rd
Registers (CPU)
Rd A Rd Result
Rs B Rs B
ALU A ∨B <After execution>
Example: OR.W Rs, Rd
Rev. 3.0, 02/99, page 798 of 904

(3) XOR Instruction (B/W): Performs a logical exclusive OR operation on a general register and
another general register, memory, or immediate data.
Operation: Rd ⊕ (EAs) → Rd
Registers (CPU)
Rd A Rd Result
Rs B Rs B
<After execution>
ALU A + B
Example: XOR.W Rs, Rd
(4) NOT Instruction (B/W): Takes the one's complement of general register or memory contents.
Operation: ¬ (EAd) → (EAd)
Registers (CPU)
Rd A Rd 1's complement
ALU ¬A <After execution>
Example: NOT.W Rd
Rev. 3.0, 02/99, page 799 of 904

A.5.7 Shift Instructions
There are eight shift instructions. The function of each instruction is described next.
(1) SHAL Instruction (B/W)
(2) SHAR Instruction (B/W)
These instructions perform an arithmetic shift operation on general register or memory contents.
Operation: (EAd) arithmetic shift → (EAd)
MSB LSB
C (CCR) (0)2
Example: SHAL.W Rd
MSB LSB
C(CCR)
Example: SHAR.W Rd
(3) SHLL Instruction (B/W)
(4) SHLR Instruction (B/W)
These instructions perform a logic shift operation on general register or memory contents.
Rev. 3.0, 02/99, page 800 of 904

Operation: (EAd) logic shift → (EAd)
MSB LSB
C (CCR) (0)2
Example: SHLL.W Rd
MSB LSB
(0)2 C(CCR)
Example: SHLR.W Rd
(5) ROTL Instruction (B/W)
(6) ROTR Instruction (B/W)
These instructions rotate general register or memory contents.
Operation: (EAd) rotate → (EAd)
MSB LSB
C (CCR)
Example: ROTL.W Rd
MSB LSB
C(CCR)
Example: ROTR.W Rd
(7) ROTXL Instruction (B/W)
(8) ROTXR Instruction (B/W)
These instructions rotate general register or memory contents through the carry bit.
Rev. 3.0, 02/99, page 801 of 904

Operation: (EAd) rotate through carry → (EAd)
MSB LSB
C (CCR)
Example: ROTXL .W Rd
MSB LSB
C (CCR)
Example: ROTXR.W Rd
A.5.8 Bit Manipulation Instructions
There are four bit manipulation instructions. The function of each instruction is described next.
(1) BSET Instruction (B/W): Tests a specified bit in a general register or memory, then sets the
bit to 1. The bit is specified by immediate data or a bit number in a general register.
Operation: ¬(<bit-No.> of <EAd>) → Z

1 → (<bit-No.> of <EAd>)
Registers (CPU)
14 14
R1 A R1 1
1 <After execution>
ALU ¬A Z (CCR)
Example: BSET.W H'E, R1
Rev. 3.0, 02/99, page 802 of 904

(2) BCLR Instruction (B/W): Tests a specified bit in a general register or memory, then clears
the bit to 0. The bit is specified by immediate data or a bit number in a general register.

0 → (<bit-No.> of <EAd>)
Registers (CPU)
14 14
R1 A R1 0
0 <After execution>
ALU ¬A Z (CCR)
Example: BCLR.W H'E, R1
(3) BNOT Instruction (B/W): Tests a specified bit in a general register or memory, then inverts
the bit. The bit is specified by immediate data or a bit number in a general register.
Operation: ¬(<bit-No.> of <EAd>) → Z → (<bit-No.> of <EAd>)
Registers (CPU) ¬A
14 14
R1 A R1
<After execution>
ALU ¬A Z (CCR)
Example: BNOT.W H'E, R1
Rev. 3.0, 02/99, page 803 of 904

(4) BTST Instruction (B/W): Tests a specified bit in a general register or memory. The bit is
specified by immediate data or a bit number in a general register.
Registers (CPU)
14
R1 A Left unchanged
ALU ¬A Z (CCR)
Example: BTST.W H'E, R1
A.5.9 Branch Instructions
There are 11 branch instructions. The function of each instruction is described next.
−): Branches if the condition specified in the instruction is true.

(1) Bcc Instruction (−
Operation: If condition is true then

PC + disp → PC
else next;
Start of next
instruction
BRA
BRA instruction
disp
Old PC
disp
PC + disp → PC
LABEL New PC
Start
instruction
Example: BRA LABEL
Note: This instruction cannot branch across a page boundary.
Rev. 3.0, 02/99, page 804 of 904

Addressing of Branch Destination: Specified by an eight-bit or 16-bit displacement.

BRA (BT) Always (true) True
BRN (BF) Never (false) False
BHI High C∨Z=0
BLS Low or same C∨Z=1
BCC (BHS) Carry clear (high or same) C=0
BCS (BLO) Carry set (low) C=1
BNE Not equal Z=0
BEQ Equal Z=1
BVC Overflow clear V=0
BVS Oveflow set V=1
BPL Plus N=0
BMI Minus N=1
BGE Greater or equal N⊕V=0
BLT Less than N⊕V=1
BGT Greater than Z ∨ (N ⊕ V) = 0
BLE Less or equal Z ∨ (N ⊕ V) = 1
−): Branches unconditionally to a specified address in the same page.

(2) JMP Instruction (−
Operation: <EA> → PC
JMP
JMP instruction
@LABEL:16
Start of
instruction @LABEL: 16 → PC
LABEL New PC
Example: JMP @LABEL
Addressing of Branch Destination: Register indirect, register indirect with eight-bit or 16-bit
displacement, or 16-bit direct addressing.

Rev. 3.0, 02/99, page 805 of 904
−): Branches unconditionally to a specified address in a specified page.
(3) PJMP Instruction (−
Operation: <EA> → CP, PC
PJMP
PJMP instruction
@R2
R2 High
R3 Low
Start of
instruction R3→PC R2→CP
New CP, PC
Example: PJMP @R2
Addressing of Branch Destination: Register indirect or 24-bit direct addressing.
Note: This instruction is invalid in minimum mode.
−): Branches to a subroutine at a specified address in the same page.

(4) BSR Instruction (−
Operation: PC → @-SP, PC + disp → PC
Start of next
instruction BSR
BSR instruction
disp
Old PC
disp
PC + disp → PC
LABEL New PC
New SP
Start of Old PC
instruction Old SP
Example: BSR LABEL
Addressing of Branch Destination: Specified by an eight-bit or 16-bit displacement.
Rev. 3.0, 02/99, page 806 of 904

−): Branches to a subroutine at a specified address in the same page.
(5) JSR Instruction (−
Operation: PC → @-SP, <EA> → PC
Start of next JSR

instruction JSR instruction
@R2
Old PC
@R2 → PC
New PC
Start of
instruction New SP
Old PC
Old SP
Example: JSR @R2
Addressing of Branch Destination: Register indirect, register indirect with eight-bit or 16-bit
displacement, or 16-bit direct addressing.
−): Branches to a subroutine at a specified address in a specified page.

(6) PJSR Instruction (−
Operation: PC → @-SP, CP → @-SP, <EA> → PC
Start of next PJSR R2 High

instruction PJSR instruction
@R2 R3 Low
Old CP, PC
R3 → PC R2 → CP
New CP, PC
Start of
New TP:SP
instruction Old PC
Old PC
Old TP:SP
Example: PJSR @R2
Addressing of Branch Destination: Register indirect or 24-bit direct addressing.
Note: This instruction is invalid in minimum mode.
Rev. 3.0, 02/99, page 807 of 904

−): Returns from a subroutine in the same page.
(7) RTS Instruction (−
Operation: @SP+ → PC
Start of next JSR

instruction JSR instruction
@R2
New PC
RTS Old PC
Old SP
New PC
New SP
Example: RTS
RTS can return from a subroutine called by a BSR or JSR instruction.
−): Returns from a subroutine in another page.

(8) PRTS Instruction (−
Operation: @SP+ → PC, @SP+ → CP
Start of next PJSR

PJSR instruction
instruction @R2
New CP, PC
PRTS Old CP, PC
Old TP:SP
New CP
New PC
New TP:SP
Example: PRTS
PRTS can return from a subroutine called by a PJSR instruction.
Rev. 3.0, 02/99, page 808 of 904

−): Returns from a subroutine in the same page and adjusts the stack
(9) RTD Instruction (−
pointer.
Operation: @SP+ → PC, SP + #IMM → SP
Start of next JSR

JSR instruction
instruction @R2
New PC
RTD Old PC
#xx:8
Old SP
New PC
SP+#xx:8
New SP
Example: RTD #xx:8
RTD can return from a subroutine called by a BSR or JSR instruction. The stack-pointer
adjustment is specified by eight-bit or 16-bit immediate data.
Note: The immediate data must have an even value. If the stack pointer is set to an odd address,
an address error will occur when the stack is accessed.
Rev. 3.0, 02/99, page 809 of 904

−): Returns from a subroutine in another page and adjusts the stack
(10) PRTD Instruction (−
pointer.
Operation: @SP+ → PC, @SP+ → CP, SP + #IMM → SP
Start of next PJSR

instruction PJSR instruction
@R2
New CP, PC
PRTD Old CP, PC

#xx:8
Old SP
New CP
New PC
SP+#xx:8
New SP
Example: PRTD #xx:8
PRTD can return from a subroutine called by a BSR or JSR instruction. The stack-pointer
adjustment is specified by eight-bit or 16-bit immediate data.
Note: The immediate data must have an even value. If the stack pointer is set to an odd address,
an address error will occur when the stack is accessed.
Rev. 3.0, 02/99, page 810 of 904

(11) SCB Instruction: This is a loop instruction. The termination condition is specified by CCR
and a loop counter.
Operation: If condition is true then next;

else Rn − 1 → Rn
If Rn = −1 then next;
else PC + disp → PC
Start of next
instruction SCB/F SCB/F
instruction
disp
Old PC
disp
PC+disp → PC
LABEL R2 Loop counter
Start of instruction −1 1
R2−1
= end of loop
Example: SCB/F R2, LABEL
Addressing of Branch Destination: Specified by an eight-bit displacement.
Description
Instruction Function Condition
SCB/F False −
SCB/NE Not Equal Z=0
SCB/EQ Equal Z=1
Rev. 3.0, 02/99, page 811 of 904

A.5.10 System Control Instructions
There are 12 system control instructions. The function of each instruction is described next.
−): Generates a trap exception with a specified vector number.

(1) TRAPA Instruction (−
Operation: PC → @−SP, (maximum mode: CP → @−SP), SR → @−SP,

<vector> → PC, (maximum mode: <vector> → CP)
H'0028 PCH
TRAPA #4 vector
H'0029 PCL
Start of next TRAPA

instruction #4
Old PC
New PC
Start of
New SP
instruction Old SR SR
Old PC
Old SP
Example: TRAPA #4
Rev. 3.0, 02/99, page 812 of 904

−): Generates a trap exception if the V bit is set to 1.
(2) TRAP/VS Instruction (−
Operation: If V bit of CCR = 1 then;

PC → @−SP, (maximum mode: CP → @-SP), SR → @−SP,
<vector> → PC, (maximum mode: <vector> → CP)
else next;
H'0008 PCH
TRAP/VS vector
H'0009 PCL
Start of next
instruction TRAPA
Old PC
New PC
Start of New SP
instruction Old SR SR
Old PC (V = 1)
Old SP
Example: TRAP/VS
Rev. 3.0, 02/99, page 813 of 904

−): Returns from an exception-handling routine.
(3) RTE Instruction (−
Operation: @SP+ → PC,

(maximum mode: @SP+ → CP),
@SP+ → SR
H'0028 PCH
TRAPA #4 vector
H'0029 PCL
Start of next TRAPA

instruction #4
New PC
RTE
Old SP
New SR SR
New PC
New SP
Example: RTE
Rev. 3.0, 02/99, page 814 of 904

−): Creates a stack frame.
(4) LINK Instruction (−
Operation: FP (R6) → @−SP,

SP → FP (R6),
SP + #IMM → SP
LINK
LINK instruction
disp
Old SP + #IMM → SP
R6 Old FP
New SP Area C (FP − 6) R7 Old SP
Stack frame
Area B (FP − 4) created by
Area A (FP − 2) LINK <Before execution>
New FP Old FP instruction
Old SP Data 1 R6 New FP
Old FP Initial SP (= FP) R7 New SP
Initial SP Return PC
(= FP) <After execution>
Example: LINK FP, #−6
Stack Frame Area: Specified by eight-bit or 16-bit immediate data.
Rev. 3.0, 02/99, page 815 of 904

−): Releases a stack frame created by the LINK instruction.
(5) UNLK Instruction (−
Operation: FP (R6) → SP,

@SP+ → FP (R6)
UNLK UNLK instruction
@SP+ → FP
R6 Old FP
Old SP Area C (FP − 6) R7 Old SP
Stack frame
Area B (FP − 4) released
Area A (FP − 2) by UNLK <Before execution>
Old FP New FP instruction
New SP Data 1 R6 New FP

New FP Initial SP (= FP) R7 New SP
Initial SP Return PC
(= FP) <After execution>
Example: UNLK FP
−): Causes a transition to a power-down state.

(6) SLEEP Instruction (−
(7) LDC Instruction (B/W): Moves immediate data or general register or memory contents into a
specified control register.
Operation: (EAs) → CR
General register Page registers
CP
R1 DP
TP
Example: LDC.B R1, DP
Instructions and Operand Sizes: The operand size depends on the control register.
Rev. 3.0, 02/99, page 816 of 904

(8) STC Instruction (B/W): Moves specified control register data to a general register or
memory.
Operation: CR → (EAd)
General register Page registers
CP
R1 DP DP
TP
Example: STC.B DP, R1
(9) ANDC Instruction (B/W): Logically ANDs a control register with immediate data.
Operation: CR ∧ #IMM → CR
General register Status register
R1 SR
ALU SR ∧ R1
Example: ANDC.W R1, SR
Rev. 3.0, 02/99, page 817 of 904

(10) ORC Instruction (B/W): Logically ORs a control register with immediate data.
Operation: CR ∨ #IMM → CR
R1 SR
ALU SR ∨ R1
Example: ORC.W R1, SR
(11) XORC Instruction (B/W): Logically exclusive-ORs a control register with immediate data.
Operation: CR ⊕ #IMM → CR
R1 SR
ALU SR + R1
Example: XORC.W R1, SR
−): Only increments the program counter.

(12) NOP Instruction (−
Operation: PC + 1 → PC
Rev. 3.0, 02/99, page 818 of 904

A.5.11 Short-Format Instructions
The ADD, CMP, and MOV instructions have special short formats. The short formats are a byte
shorter than the corresponding general formats, and most of them execute one state faster. Table
A-12 lists these short formats together with the equivalent general formats.
Table A-12 Short-Format Instructions and Equivalent General Formats
Short-Format Execution Equivalent General- Execution

2 2
Instruction Length States* Format Instruction Length States*
1
ADD: Q #xx, Rd* 2 2 ADD: G #xx: 8, Rd 3 3
CMP: E #xx: 8, Rd 2 2 CMP: G.B #xx: 8, Rd 3 3
CMP: I #xx: 16, Rd 3 3 CMP: G.W #xx: 16, Rd 4 4
MOV: E #xx: 8, Rd 2 2 MOV: G.B #xx: 8, Rd 3 3
MOV: I #xx: 16, Rd 3 3 MOV: G.W #xx: 16, Rd 4 4
MOV: L @aa: 8, Rd 2 5 MOV: G @aa: 8, Rd 3 5
MOV: S Rs, @aa: 8 2 5 MOV: G Rs, @aa: 8 3 5
MOV: F @ (d; 8, R6), Rd 2 5 MOV: G @ (d: 8, R6), Rd 3 5
MOV: F Rs, @ (d: 8, R6) 2 5 MOV: G Rs, @ (d: 8, R6) 3 5
Notes: 1. The ADD:Q instruction accepts other destination operands in addition to a general
register.
2. Number of execution states for access to on-chip memory.
Rev. 3.0, 02/99, page 819 of 904

Appendix B Initial Values of CPU Registers
Table B-1 Register Values after Reset Exception Handling
Initial Value
Register
Minimum Mode Maximum Mode
15 0
R0
R1
R2
R3 Undetermined Undetermined
R4
R5
R6 (FP)
R7 (SP)
15 0
Loaded from Loaded from
PC vector table vector table
SR
H'070* H'070*
CCR
* The last four bits * The last four bits

15 8 7 0 (N, V, Z, and C) (N, V, Z, and C)
T − − − − I2 I1 I0 − − − − N V Z C are undetermined. are undetermined.
7 0
CP CP: loaded from
vector table
DP Undetermined
DP, EP, and TP:
EP
undetermined
TP
7 0
BR Undetermined Undetermined
Rev. 3.0, 02/99, page 820 of 904

Appendix C On-Chip Registers
C.1 H8/539F Dual power source model

Bit Names
Address Module Register Initial
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Name Name Value
H'FE80 Port 1 P1DDR P17DDR P16DDR P15DDR P14DDR P13DDR P12DDR P11DDR P10DDR H'00
H'FE82 Port 1 P1DR P17 P16 P15 P14 P13 P12 P11 P10 H'00
H'FE84 Port 3 P3DDR   P35DDR P34DDR P33DDR P32DDR P31DDR P30DDR H'C0
H'FE86 Port 3 P3DR   P35 P34 P33 P32 P31 P30 H'C0
H'FE89 Port 6 P6DDR    P64DDR P63DDR P62DDR P61DDR P60DDR H'E0
H'FE8A Port 5 P5DR P57 P56 P55 P54 P53 P52 P51 P50 H'00
H'FE8B Port 6 P6DR    P64 P63 P62 P61 P60 H'E0
H'FE8C Port 7 P7DDR P77DDR P76DDR P75DDR P74DDR P73DDR P72DDR P71DDR P70DDR H'00
H'FE8D         H'FF
H'FE8E Port 7 P7DR P77 P76 P75 P74 P73 P72 P71 P70 H'00
H'FE8F Port 8 P8DR     P83 P82 P81 P80 Undeter-

mined
(continued on next page)
Rev. 3.0, 02/99, page 821 of 904

H8/539F Dual power source model
Bit Names
Name Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value
H'FE90         H'FF
H'FE91 Port A PADDR  PA6DDR PA5DDR PA4DDR PA3DDR PA2DDR PA1DDR PA0DDR H'80
H'FE92 Port 9 P9DR P97 P96 P95 P94 P93 P92 P91 P90 Undeter-
mined
H'FE93 Port A PADR  PA6 PA5 PA4 PA3 PA2 PA1 PA0 H'80
H'FE94 Port B PBDDR PB7DDR PB6DDR PB5DD PB4DDR PB3DDR PB2DDR PB1DDR PB0DDR H'00
R
H'FE95 Port C PCDDR PC7DDR PC6DDR PC5DD PC4DDR PC3DDR PC2DDR PC1DDR PC0DDR H'00
R
H'FE96 Port B PBDR PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 H'00
H'FE97 Port C PCDR PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 H'00
H'FE98 Port B PBPCR PB7PON PB6PON PB5PON PB4PON PB3PON PB2PON PB1PON PB0PON H'00
H'FE99 Port C PCPCR PC7PON PC6PON PC5PON PC4PON PC3PON PC2PON PC1PON PC0PON H'00
H'FE9A φCR φCR φOE        Unde-

fined*
H'FE9B         H'FF
H'FE9C         H'FF
H'FE9D         H'FF
H'FE9E         H'FF
H'FE9F         H'FF
Note: * Initialized to H'FF in standby mode.
Rev. 3.0, 02/99, page 822 of 904

Bit Names
H'FEA0 A/D ADDR0H AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 H'00
H'FEA1 ADDR0L AD1 AD0       H'00
H'FEA2 ADDR1H AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 H'00
H'FEA3 ADDR1L AD1 AD0       H'00
H'FEA5 ADDR2L AD1 AD0       H'00
H'FEA7 ADDR3L AD1 AD0       H'00
H'FEA9 ADDR4L AD1 AD0       H'00
H'FEAA ADDR5H AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 H'00
H'FEAB ADDR5L AD1 AD0       H'00
H'FEAC ADDR6H AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 H'00
H'FEAD ADDR6L AD1 AD0       H'00
H'FEAE ADDR7H AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 H'00
H'FEAF ADDR7L AD1 AD0       H'00

Legend
A/D: A/D converter
Rev. 3.0, 02/99, page 823 of 904

Bit Names
H'FEB0 A/D ADDR8H AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 H'00
H'FEB1 ADDR8L AD1 AD0       H'00
H'FEB2 ADDR9H AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 H'00
H'FEB3 ADDR9L AD1 AD0       H'00
H'FEB4 ADDRAH AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 H'00
H'FEB5 ADDRAL AD1 AD0       H'00
H'FEB6 ADDRBH AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 H'00
H'FEB7 ADDRBL AD1 AD0       H'00
H'FEB8 ADCSR ADF ADIE ADM1 ADM0 CH3 CH2 CH1 CH0 H'00
H'FEB9 ADCR TRGE CKS ADST      H'1F
H'FEBA         H'FF
H'FEBB         H'FF
H'FEBC         H'FF
H'FEBD         H'FF
H'FEBE         H'FF
H'FEBF         H'FF
Legend
A/D: A/D converter
Rev. 3.0, 02/99, page 824 of 904

Bit Names
H'FEC0 SCI3 SMR C/$ CHR PE O/( STOP MP CKS1 CKS0 H'00
H'FEC1 BRR H'FF
H'FEC2 SCR TIE RIE TE RE MPIE TEIE CKE1 CKE0 H'00
H'FEC3 TDR H'FF
H'FEC4 SSR TDRE RDRF ORER FER PER TEND MPB MPBT H'84F
H'FEC5 RDR H'00
H'FEC6         H'FF
H'FEC7         Undeter-
mined
H'FEC9 BRR H'FF
H'FECA SCR TIE RIE TE RE MPIE TEIE CKE1 CKE0 H'00
H'FECB TDR H'FF
H'FECC SSR TDRE RDRF ORER FER PER TEND MPB MPBT H'84
H'FECD RDR H'00
H'FECE         H'FF
H'FECF         Undeter-
mined
Legend
SCI1: Serial communication interface 1
Rev. 3.0, 02/99, page 825 of 904

Bit Names
H'FED0 SCI2 SMR C/$ CHR PE O/( STOP MP CKS1 CKS0 H'00
H'FED1 BRR H'FF
H'FED2 SCR TIE RIE TE RE MPIE TEIE CKE1 CKE0 H'00
H'FED3 TDR H'FF
H'FED4 SSR TDRE RDRF ORER FER PER TEND MPB MPBT H'84
H'FED5 RDR H'00
H'FED6         H'FF
H'FED7         Undeter-
mined
H'FED8         H'FF
H'FED9         H'FF
H'FEDA Port A PACR  TXD3E RXD3E  SCK3E PW3E PW2E PW1E H'90
H'FEDB Port 6/7 P67CR PW2E PW1E      PW3E H'3E
H'FEDC A/D ADTRGR EXTRG        H'FF
H'FEDD         H'FF
H'FEDE INTC IRQFR     IRQ3F IRQ2F IRQ1F  H'F1
H'FEDF BSC BCR BCRE 0P3T  P9AE EXIOP PCRE PBCE P12E H'3F*
Legend
INTC: Interrupt controller
BSC: Bus controller
A/D: A/D converter
Note: * Initial value in modes 5 and 6. In modes 1 to 4 and mode 7 the initial value is H'BF.
Rev. 3.0, 02/99, page 826 of 904

Bit Names
H'FEE0 Flash FLMCR VPP VPPE   EV PV E P H'00*
memory
H'FEE1         H'FF
H'FEE2 EBR1 LB7 LB6 LB5 LB4 LB3 LB2 LB1 LB0 H'00
H'FEE3 EBR2 SB7 SB6 SB5 SB4 SB3 SB2 SB1 SB0 H'00
H'FEE4         H'FF
H'FEE5         H'FF
H'FEE6         H'FF
H'FEE7         H'FF
H'FEE8         H'FF
H'FEE9         H'FF
H'FEEA         H'FF
H'FEEB         H'FF
H'FEEC Flash FLMER OVLPE    A11E A10E A9E  H'71

memory
H'FEED FLMSR FLER        H'7F
H'FEEE         H'FF
H'FEEF         H'FF
Note: * When 12 V is being applied to the VPP pin, the initial value is H'80.
Rev. 3.0, 02/99, page 827 of 904

Bit Names
Name Name Value
H'FEF0 PWM1 TCR OE OS    CKS2 CKS1 CKS0 H'38
H'FEF1 DTR H'FF
H'FEF2 TCNT H'00
H'FEF3         H'FF
H'FEF5 DTR H'FF
H'FEF6 TCNT H'00
H'FEF7         H'FF
H'FEF9 DTR H'FF
H'FEFA TCNT H'00
H'FEFB         H'FF
H'FEFC         H'FF
H'FEFD         H'FF
H'FEFE         H'FF
H'FEFF         H'FF
Legend
PWM1: Pulse width modulation timer 1
Rev. 3.0, 02/99, page 828 of 904

Bit Names
H'FF00 INTC IPRA 0 0 H'00
H'FF01 IPRB 0 0 H'00
H'FF02 IPRC 0 0 H'00
H'FF03 IPRD 0 0 H'00
H'FF04 IPRE 0 0 H'00
H'FF05 IPRF 0 0 H'00
H'FF06 DTC         Undeter-

mined
H'FF07         Undeter-
mined
H'FF08 DTEA 0 ADI (IRQ0) IRQ0 0 IRQ3 IRQ2 IRQ1 H'00
H'FF09 DTEB 0 T1CMI1,2 T1IMI2 T1IMI1 0 T1CMI3,4 T1IMI4 T1IMI3 H'00
H'FF0A DTEC 0 T2CMI1,2 T2IMI2 T2IMI1 0 T3CMI1,2 T3IMI2 T3IMI1 H'00
H'FF0B DTED 0 T4CMI1,2 T4IMI2 T4IMI1 0 T5CMI1,2 T5IMI2 T5IMI1 H'00
H'FF0C DTEE 0 0 T6IMI2 T6IMI1 0 0 T7IMI2 T7IMI1 H'00
H'FF0D DTEF 0 TI1 RI1 0 0 TI2 RI2 0 H'00
H'FF0E         Undeter-
mined
H'FF0F         Undeter-
mined
Legend
DTC: Data transfer controller
Rev. 3.0, 02/99, page 829 of 904

Bit Names
Name Name Value
 
1
H'FF10 WDT (TCSR)* OVF WT/,7 TME CKS2 CKS1 CKS0 H'18
1
H'FF11 TCNT* H'00
H'FF12         H'FF
H'FF13         H'FF
H'FF14 WSC WCR     WMS1 WMS0 WC1 WC0 H'F3
H'FF15 RAM RAMCR RAME1  RAME2   RAM2 RAM1 RAM0 Undeter-

mined
H'FF16 BSC ARBT H'FF

2
H'FF17 AR3T H'0E*
H'FF18         H'FF
H'FF19 SYSC MDCR      MDS2 MDS1 MDS0 Undeter-

mined
H'FF1A SBYCR SSBY        H'7F
H'FF1B BRCR        BRLE H'FE
H'FF1C NMICR        NMIEG H'FE
H'FF1D IRQCR     IRQ3E IRQ2E IRQ1E IRQ0E H'F0
H'FF1E (Write CR)
H'FF1F RSTCSR WRST RSTOE       H'3F

Legend
WDT: Watchdog timer
WSC: Wait-state controller
RAMCR:RAM controller
BSC: Bus controller
Notes: 1. These registers are write-protected by a password. See section 13.2.4 , "Notes on
Register Access" for details.
2. Initial value in modes 5 and 6. In modes 1 to 4 and mode 7 the initial value is H'EE.
Rev. 3.0, 02/99, page 830 of 904

Bit Names
H'FF20 IPU T1CRH   CKEG1 CKEG0 TPSC3 TPSC2 TPSC1 TPSC0 H'C0
Channel 1
H'FF21 T1CRL  CCLR2 CCLR1 CCLR0 IEG21 IEG20 IEG11 IEG10 H'80
H'FF22 T1SRAH    OVIE CMIE2 CMIE1 IMIE2 IMIE1 H'E0
H'FF23 T1SRAL    OVF CMF2 CMF1 IMF2 IMF1 H'E0
H'FF24 T1OERA DOE21 DOE20 DOE11 DOE10 GOE21 GOE20 GOE11 GOE10 H'00
H'FF25 TMDRA MD6-7 MD4-7 MD3-5 MD2-6 SYNC3 SYNC2 SYNC1 SYNC0 H'00
H'FF26 T1CNTH* H'00
H'FF27 T1CNTL* H'00
H'FF28 T1GR1H* H'FF
H'FF29 T1GR1L* H'FF
H'FF2A T1GR2H* H'FF
H'FF2B T1GR2L* H'FF
H'FF2C T1DR1H* H'FF
H'FF2D T1DR1L* H'FF
H'FF2E T1DR2H* H'FF
H'FF2F T1DR2L* H'FF

Legend
IPU: 16-bit integrated timer pulse unit
Note: * These registers support 16-bit access.
Rev. 3.0, 02/99, page 831 of 904

Bit Names
H'FF30 IPU TSTR  STR7 STR6 STR5 STR4 STR3 STR2 STR1 H'80
Channel 1
H'FF31 T1CRA     IEG41 IEG40 IEG31 IEG30 H'F0
H'FF32 T1SRBH     CMIE4 CMIE3 IMIE4 IMIE3 H'F0
H'FF33 T1SRBL     CMF4 CMF3 IMF4 IMF3 H'F0
H'FF34 T1OERB DOE41 DOE40 DOE31 DOE30 GOE41 GOE40 GOE31 GOE30 H'00
H'FF35 TMDRB   MDF PWM4 PWM3 PWM2 PWM1 PWM0 H'C0
H'FF36         H'FF
H'FF37         H'FF
H'FF38 T1GR3H* H'FF
H'FF39 T1GR3L* H'FF
H'FF3A T1GR4H* H'FF
H'FF3B T1GR4L* H'FF
H'FF3C T1DR3H* H'FF
H'FF3D T1DR3L* H'FF
H'FF3E T1DR4H* H'FF
H'FF3F T1DR4L* H'FF

Legend
Rev. 3.0, 02/99, page 832 of 904

Bit Names
Channel 2
H'FF41 T2CRL   CCLR1 CCLR0 IEG21 IEG20 IEG11 IEG10 H'C0
H'FF42 T2SRH    OVIE CMIE2 CMIE1 IMIE2 IMIE1 H'E0
H'FF43 T2SRL    OVF CMF2 CMF1 IMF2 IMF1 H'E0
H'FF44 T2OER DOE21 DOE20 DOE11 DOE10 GOE21 GOE20 GOE11 GOE10 H'00
H'FF45         H'FF
H'FF46 T2CNTH* H'00
H'FF47 T2CNTL* H'00
H'FF48 T2GR1H* H'FF
H'FF49 T2GR1L* H'FF
H'FF4A T2GR2H* H'FF
H'FF4B T2GR2L* H'FF
H'FF4C T2DR1H* H'FF
H'FF4D T2DR1L* H'FF
H'FF4E T2DR2H* H'FF
H'FF4F T2DR2L* H'FF

Legend
Rev. 3.0, 02/99, page 833 of 904

Bit Names
Channel 3
H'FF55         H'FF
H'FF56 T3CNTH* H'00
H'FF57 T3CNTL* H'00
H'FF58 T3GR1H* H'FF
H'FF59 T3GR1L* H'FF
H'FF5A T3GR2H* H'FF
H'FF5B T3GR2L* H'FF
H'FF5C T3DR1H* H'FF
H'FF5D T3DR1L* H'FF
H'FF5E T3DR2H* H'FF
H'FF5F T3DR2L* H'FF

Legend
Rev. 3.0, 02/99, page 834 of 904

Bit Names
Channel 3
H'FF65         H'FF
H'FF66 T4CNTH* H'00
H'FF67 T4CNTL* H'00
H'FF68 T4GR1H* H'FF
H'FF69 T4GR1L* H'FF
H'FF6A T4GR2H* H'FF
H'FF6B T4GR2L* H'FF
H'FF6C T4DR1H* H'FF
H'FF6D T4DR1L* H'FF
H'FF6E T4DR2H* H'FF
H'FF6F T4DR2L* H'FF

Legend
Rev. 3.0, 02/99, page 835 of 904

Bit Names
Channel 5
H'FF75         H'FF
H'FF76 T5CNTH* H'00
H'FF77 T5CNTL* H'00
H'FF78 T5GR1H* H'FF
H'FF79 T5GR1L* H'FF
H'FF7A T5GR2H* H'FF
H'FF7B T5GR2L* H'FF
H'FF7C T5DR1H* H'FF
H'FF7D T5DR1L* H'FF
H'FF7E T5DR2H* H'FF
H'FF7F T5DR2L* H'FF

Legend
Rev. 3.0, 02/99, page 836 of 904

Bit Names
Channel 6
H'FF82 T6SRH      OVIE IMIE2 IMIE1 H'F8
H'FF83 T6SRL      OVF IMF2 IMF1 H'F8
H'FF84 T6OER     GOE21 GOE20 GOE11 GOE10 H'F0
H'FF85         H'FF
H'FF86 T6CNTH* H'00
H'FF87 T6CNTL* H'00
H'FF88 T6GR1H* H'FF
H'FF89 T6GR1L* H'FF
H'FF8A T6GR2H* H'FF
H'FF8B T6GR2L* H'FF
H'FF8C         H'FF
H'FF8D         H'FF
H'FF8E         H'FF
H'FF8F         H'FF
Legend
Rev. 3.0, 02/99, page 837 of 904

Bit Names
Channel 7
H'FF95         H'FF
H'FF96 T7CNTH* H'00
H'FF97 T7CNTL* H'00
H'FF98 T7GR1H* H'FF
H'FF99 T7GR1L* H'FF
H'FF9A T7GR2H* H'FF
H'FF9B T7GR2L* H'FF
H'FF9C         H'FF
H'FF9D         H'FF
H'FF9E         H'FF
H'FF9F         H'FF
Legend
Rev. 3.0, 02/99, page 838 of 904

Bit Names
H'FFA0 MULT MLTCR CLR S_ON    SIGN MUL MAC H'38
H'FFA1 MLTBR         H'00
H'FFA2 MLTMAR         H'00
H'FFA3 MLTAR         H'00
H'FFA4         H'FF
H'FFA5         H'FF
H'FFA6         H'FF
H'FFA7         H'FF
H'FFA8         H'FF
H'FFA9         H'FF
H'FFAA         H'FF
H'FFAB         H'FF
H'FFAC         H'FF
H'FEED         H'FF
H'FFAE         H'FF
H'FFAF         H'FF
Legend
MULT: Multiplier
Rev. 3.0, 02/99, page 839 of 904

Bit Names
H'FFB0 MULT CA H'00
H'FFB1 (CA) H'00
H'FFB2 CB H'00
H'FFB3 (CB) H'00
H'FFB4 CC H'00
H'FFB5 (CC) H'00
H'FFB6 XH Undeter-
mined
H'FFB7 (XH) Undeter-

mined
H'FFB8 H Undeter-
mined
H'FFB9 (H) Undeter-

mined
H'FFBA L Undeter-
mined
H'FFBB (L) Undeter-

mined
H'FFBC MR H'00
H'FFBD (MR) H'00
H'FFBE MMR H'00
H'FFBF (MMR) H'00

Legend
MULT: Multiplier
Rev. 3.0, 02/99, page 840 of 904

C.2 H8/539F S-Mask and A-Mask Models
Bit Names
H'FE84 Port 3 P3DDR   P35DDR P34DDR P33DDR P32DDR P31DDR P30DDR H'C0
H'FE86 Port 3 P3DR   P35 P34 P33 P32 P31 P30 H'C0
H'FE89 Port 6 P6DDR    P64DDR P63DDR P62DDR P61DDR P60DDR H'E0
H'FE8A Port 5 P5DR P57 P56 P55 P54 P53 P52 P51 P50 H'00
H'FE8B Port 6 P6DR    P64 P63 P62 P61 P60 H'E0
H'FE8C Port 7 P7DDR P77DDR P76DDR P75DDR P74DDR P73DDR P72DDR P71DDR P70DDR H'00
H'FE8D         H'FF
H'FE8E Port 7 P7DR P77 P76 P75 P74 P73 P72 P71 P70 H'00
H'FE8F Port 8 P8DR     P83 P82 P81 P80 Undeter-

mined
Rev. 3.0, 02/99, page 841 of 904

H8/539F S-Mask and A-Mask Models
Bit Names
H'FE90         H'FF
H'FE91 Port A PADDR  PA6DDR PA5DDR PA4DDR PA3DDR PA2DDR PA1DDR PA0DDR H'80
H'FE92 Port 9 P9DR P97 P96 P95 P94 P93 P92 P91 P90 Undeter-
mined
H'FE93 Port A PADR  PA6 PA5 PA4 PA3 PA2 PA1 PA0 H'80
H'FE94 Port B PBDDR PB7DDR PB6DDR PB5DDR PB4DDR PB3DDR PB2DDR PB1DDR PB0DDR H'00
H'FE95 Port C PCDDR PC7DDR PC6DDR PC5DDR PC4DDR PC3DDR PC2DDR PC1DDR PC0DDR H'00
H'FE96 Port B PBDR PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 H'00
H'FE97 Port C PCDR PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 H'00
H'FE98 Port B PBPCR PB7PON PB6PON PB5PON PB4PON PB3PON PB2PON PB1PON PB0PON H'00
H'FE99 Port C PCPCR PC7PON PC6PON PC5PON PC4PON PC3PON PC2PON PC1PON PC0PON H'00
H'FE9A φCR φCR φOE        Unde-

fined*
H'FE9B         H'FF
H'FE9C         H'FF
H'FE9D         H'FF
H'FE9E         H'FF
H'FE9F         H'FF

Note: * Initialized to H'FF in standby mode.
Rev. 3.0, 02/99, page 842 of 904

Bit Names
H'FEA0 A/D ADDR0H AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 H'00
H'FEA1 ADDR0L AD1 AD0       H'00
H'FEA3 ADDR1L AD1 AD0       H'00
H'FEA5 ADDR2L AD1 AD0       H'00
H'FEA7 ADDR3L AD1 AD0       H'00
H'FEA9 ADDR4L AD1 AD0       H'00
H'FEAA ADDR5H AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 H'00
H'FEAB ADDR5L AD1 AD0       H'00
H'FEAC ADDR6H AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 H'00
H'FEAD ADDR6L AD1 AD0       H'00
H'FEAE ADDR7H AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 H'00
H'FEAF ADDR7L AD1 AD0       H'00

Legend
A/D: A/D converter
Rev. 3.0, 02/99, page 843 of 904

Bit Names
H'FEB0 A/D ADDR8H AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 H'00
H'FEB1 ADDR8L AD1 AD0       H'00
H'FEB2 ADDR9H AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 H'00
H'FEB3 ADDR9L AD1 AD0       H'00
H'FEB4 ADDRAH AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 H'00
H'FEB5 ADDRAL AD1 AD0       H'00
H'FEB6 ADDRBH AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 H'00
H'FEB7 ADDRBL AD1 AD0       H'00
H'FEB8 ADCSR ADF ADIE ADM1 ADM0 CH3 CH2 CH1 CH0 H'00
H'FEB9 ADCR TRGE CKS ADST      H'1F
H'FEBA         H'FF
H'FEBB         H'FF
H'FEBC         H'FF
H'FEBD         H'FF
H'FEBE         H'FF
H'FEBF         H'FF
Legend
A/D: A/D converter
Rev. 3.0, 02/99, page 844 of 904

Bit Names
H'FEC1 BRR H'FF
H'FEC2 SCR TIE RIE TE RE MPIE TEIE CKE1 CKE0 H'00
H'FEC3 TDR H'FF
H'FEC4 SSR TDRE RDRF ORER FER PER TEND MPB MPBT H'84F
H'FEC5 RDR H'00
H'FEC6         H'FF
H'FEC7         Undeter-
mined
H'FEC9 BRR H'FF
H'FECA SCR TIE RIE TE RE MPIE TEIE CKE1 CKE0 H'00
H'FECB TDR H'FF
H'FECC SSR TDRE RDRF ORER FER PER TEND MPB MPBT H'84
H'FECD RDR H'00
H'FECE         H'FF
H'FECF         Undeter-
mined
Legend
Rev. 3.0, 02/99, page 845 of 904

Bit Names
H'FED0 SCI2 SMR C/$ CHR PE O/( STOP MP CKS1 CKS0 H'00
H'FED1 BRR H'FF
H'FED2 SCR TIE RIE TE RE MPIE TEIE CKE1 CKE0 H'00
H'FED3 TDR H'FF
H'FED4 SSR TDRE RDRF ORER FER PER TEND MPB MPBT H'84
H'FED5 RDR H'00
H'FED6         H'FF
H'FED7         Undeter-
mined
H'FED8         H'FF
H'FED9         H'FF
H'FEDA Port A PACR  TXD3E RXD3E  SCK3E PW3E PW2E PW1E H'90
H'FEDB Port 6/7 P67CR PW2E PW1E      PW3E H'3E
H'FEDC A/D ADTRGR EXTRG        H'FF
H'FEDD         H'FF
H'FEDE INTC IRQFR     IRQ3F IRQ2F IRQ1F  H'F1
H'FEDF BSC BCR BCRE 0P3T  P9AE EXIOP PCRE PBCE P12E H'3F*
Legend
BSC: Bus controller
A/D: A/D converter
Note: * Initial value in modes 5 and 6. In modes 1 to 4 and mode 7 the initial value is H'BF.
Rev. 3.0, 02/99, page 846 of 904

Bit Names
H'FEE0 Flash FLMCR FWE SWE ESU PSU EV PV E P H'00*
memory
H'FEE1         H'FF
H'FEE2 EBR1 EB7 EB6 EB5 EB4 EB3 EB2 EB1 EB0 H'00
H'FEE3          H'FF
H'FEE4         H'FF
H'FEE5         H'FF
H'FEE6         H'FF
H'FEE7         H'FF
H'FEE8         H'FF
H'FEE9         H'FF
H'FEEA         H'FF
H'FEEB         H'FF
H'FEEC Flash FLMER OVLPE    A11E A10E   H'73

memory
H'FEED FLMSR FLER        H'7F
H'FEEE         H'FF
H'FEEF         H'FF
Note: * When a high level is being applied to the FWE to the FWE pin, the initial value is H'80
Rev. 3.0, 02/99, page 847 of 904

Bit Names
H'FEF1 DTR H'FF
H'FEF2 TCNT H'00
H'FEF3         H'FF
H'FEF5 DTR H'FF
H'FEF6 TCNT H'00
H'FEF7         H'FF
H'FEF9 DTR H'FF
H'FEFA TCNT H'00
H'FEFB         H'FF
H'FEFC         H'FF
H'FEFD         H'FF
H'FEFE         H'FF
H'FEFF         H'FF
Legend
Rev. 3.0, 02/99, page 848 of 904

Bit Names
H'FF00 INTC IPRA 0 0 H'00
H'FF01 IPRB 0 0 H'00
H'FF02 IPRC 0 0 H'00
H'FF03 IPRD 0 0 H'00
H'FF04 IPRE 0 0 H'00
H'FF05 IPRF 0 0 H'00
H'FF06 DTC         Undeter-

mined
H'FF07         Undeter-
mined
H'FF08 DTEA 0 ADI (IRQ0) IRQ0 0 IRQ3 IRQ2 IRQ1 H'00
H'FF09 DTEB 0 T1CMI1,2 T1IMI2 T1IMI1 0 T1CMI3,4 T1IMI4 T1IMI3 H'00
H'FF0A DTEC 0 T2CMI1,2 T2IMI2 T2IMI1 0 T3CMI1,2 T3IMI2 T3IMI1 H'00
H'FF0B DTED 0 T4CMI1,2 T4IMI2 T4IMI1 0 T5CMI1,2 T5IMI2 T5IMI1 H'00
H'FF0C DTEE 0 0 T6IMI2 T6IMI1 0 0 T7IMI2 T7IMI1 H'00
H'FF0D DTEF 0 TI1 RI1 0 0 TI2 RI2 0 H'00
H'FF0E         Undeter-
mined
H'FF0F         Undeter-
mined
Legend
DTC: Data transfer controller
Rev. 3.0, 02/99, page 849 of 904

Bit Names
 
1
H'FF10 WDT (TCSR)* OVF WT/,7 TME CKS2 CKS1 CKS0 H'18
1
H'FF11 TCNT* H'00
H'FF12         H'FF
H'FF13         H'FF
H'FF14 WSC WCR     WMS1 WMS0 WC1 WC0 H'F3
H'FF15 RAM RAMCR RAME1  RAME2   RAM2 RAM1  Undeter-

mined
H'FF16 BSC ARBT H'FF

2
H'FF17 AR3T H'0E*
H'FF18         H'FF
H'FF19 SYSC MDCR      MDS2 MDS1 MDS0 Undeter-

mined
H'FF1A SBYCR SSBY        H'7F
H'FF1B BRCR        BRLE H'FE
H'FF1C NMICR        NMIEG H'FE
H'FF1D IRQCR     IRQ3E IRQ2E IRQ1E IRQ0E H'F0
H'FF1E (Write CR)
H'FF1F RSTCSR WRST RSTOE       H'3F

Legend
WDT: Watchdog timer
WSC: Wait-state controller
RAMCR: RAM controller
BSC: Bus controller
Notes: 1. These registers are write-protected by a password. See section 13.2.4 , "Notes on
Register Access" for details.
2. Initial value in modes 5 and 6. In modes 1 to 4 and mode 7 the initial value is H'EE.
Rev. 3.0, 02/99, page 850 of 904

Bit Names
Channel 1
H'FF21 T1CRL  CCLR2 CCLR1 CCLR0 IEG21 IEG20 IEG11 IEG10 H'80
H'FF22 T1SRAH    OVIE CMIE2 CMIE1 IMIE2 IMIE1 H'E0
H'FF23 T1SRAL    OVF CMF2 CMF1 IMF2 IMF1 H'E0
H'FF24 T1OERA DOE21 DOE20 DOE11 DOE10 GOE21 GOE20 GOE11 GOE10 H'00
H'FF25 TMDRA MD6-7 MD4-7 MD3-5 MD2-6 SYNC3 SYNC2 SYNC1 SYNC0 H'00
H'FF26 T1CNTH* H'00
H'FF27 T1CNTL* H'00
H'FF28 T1GR1H* H'FF
H'FF29 T1GR1L* H'FF
H'FF2A T1GR2H* H'FF
H'FF2B T1GR2L* H'FF
H'FF2C T1DR1H* H'FF
H'FF2D T1DR1L* H'FF
H'FF2E T1DR2H* H'FF
H'FF2F T1DR2L* H'FF

Legend
Rev. 3.0, 02/99, page 851 of 904

Bit Names
H'FF30 IPU TSTR  STR7 STR6 STR5 STR4 STR3 STR2 STR1 H'80
Channel 1
H'FF31 T1CRA     IEG41 IEG40 IEG31 IEG30 H'F0
H'FF32 T1SRBH     CMIE4 CMIE3 IMIE4 IMIE3 H'F0
H'FF33 T1SRBL     CMF4 CMF3 IMF4 IMF3 H'F0
H'FF34 T1OERB DOE41 DOE40 DOE31 DOE30 GOE41 GOE40 GOE31 GOE30 H'00
H'FF35 TMDRB   MDF PWM4 PWM3 PWM2 PWM1 PWM0 H'C0
H'FF36         H'FF
H'FF37         H'FF
H'FF38 T1GR3H* H'FF
H'FF39 T1GR3L* H'FF
H'FF3A T1GR4H* H'FF
H'FF3B T1GR4L* H'FF
H'FF3C T1DR3H* H'FF
H'FF3D T1DR3L* H'FF
H'FF3E T1DR4H* H'FF
H'FF3F T1DR4L* H'FF

Legend
Rev. 3.0, 02/99, page 852 of 904

Bit Names
(low) Name Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value
Channel 2
H'FF45         H'FF
H'FF46 T2CNTH* H'00
H'FF47 T2CNTL* H'00
H'FF48 T2GR1H* H'FF
H'FF49 T2GR1L* H'FF
H'FF4A T2GR2H* H'FF
H'FF4B T2GR2L* H'FF
H'FF4C T2DR1H* H'FF
H'FF4D T2DR1L* H'FF
H'FF4E T2DR2H* H'FF
H'FF4F T2DR2L* H'FF

Legend
Rev. 3.0, 02/99, page 853 of 904

Bit Names
Channel 3
H'FF55         H'FF
H'FF56 T3CNTH* H'00
H'FF57 T3CNTL* H'00
H'FF58 T3GR1H* H'FF
H'FF59 T3GR1L* H'FF
H'FF5A T3GR2H* H'FF
H'FF5B T3GR2L* H'FF
H'FF5C T3DR1H* H'FF
H'FF5D T3DR1L* H'FF
H'FF5E T3DR2H* H'FF
H'FF5F T3DR2L* H'FF

Legend
Rev. 3.0, 02/99, page 854 of 904

Bit Names
Channel 4
H'FF65         H'FF
H'FF66 T4CNTH* H'00
H'FF67 T4CNTL* H'00
H'FF68 T4GR1H* H'FF
H'FF69 T4GR1L* H'FF
H'FF6A T4GR2H* H'FF
H'FF6B T4GR2L* H'FF
H'FF6C T4DR1H* H'FF
H'FF6D T4DR1L* H'FF
H'FF6E T4DR2H* H'FF
H'FF6F T4DR2L* H'FF

Legend
Rev. 3.0, 02/99, page 855 of 904

Bit Names
Channel 5
H'FF75         H'FF
H'FF76 T5CNTH* H'00
H'FF77 T5CNTL* H'00
H'FF78 T5GR1H* H'FF
H'FF79 T5GR1L* H'FF
H'FF7A T5GR2H* H'FF
H'FF7B T5GR2L* H'FF
H'FF7C T5DR1H* H'FF
H'FF7D T5DR1L* H'FF
H'FF7E T5DR2H* H'FF
H'FF7F T5DR2L* H'FF

Legend
Rev. 3.0, 02/99, page 856 of 904

Bit Names
Channel 6
H'FF85         H'FF
H'FF86 T6CNTH* H'00
H'FF87 T6CNTL* H'00
H'FF88 T6GR1H* H'FF
H'FF89 T6GR1L* H'FF
H'FF8A T6GR2H* H'FF
H'FF8B T6GR2L* H'FF
H'FF8C         H'FF
H'FF8D         H'FF
H'FF8E         H'FF
H'FF8F         H'FF
Legend
Rev. 3.0, 02/99, page 857 of 904

Bit Names
Channel 7
H'FF95         H'FF
H'FF96 T7CNTH* H'00
H'FF97 T7CNTL* H'00
H'FF98 T7GR1H* H'FF
H'FF99 T7GR1L* H'FF
H'FF9A T7GR2H* H'FF
H'FF9B T7GR2L* H'FF
H'FF9C         H'FF
H'FF9D         H'FF
H'FF9E         H'FF
H'FF9F         H'FF
Legend
Rev. 3.0, 02/99, page 858 of 904

Bit Names
H'FFA0 MULT MLTCR CLR S_ON    SIGN MUL MAC H'38
H'FFA1 MLTBR         H'00
H'FFA2 MLTMAR         H'00
H'FFA3 MLTAR         H'00
H'FFA4         H'FF
H'FFA5         H'FF
H'FFA6         H'FF
H'FFA7         H'FF
H'FFA8         H'FF
H'FFA9         H'FF
H'FFAA         H'FF
H'FFAB         H'FF
H'FFAC         H'FF
H'FEED         H'FF
H'FFAE         H'FF
H'FFAF         H'FF
Legend
MULT: Multiplier
Rev. 3.0, 02/99, page 859 of 904

Bit Names
H'FFB0 MULT CA H'00
H'FFB1 (CA) H'00
H'FFB2 CB H'00
H'FFB3 (CB) H'00
H'FFB4 CC H'00
H'FFB5 (CC) H'00
H'FFB6 XH Undeter-
mined
H'FFB7 (XH) Undeter-

mined
H'FFB8 H Undeter-
mined
H'FFB9 (H) Undeter-

mined
H'FFBA L Undeter-
mined
H'FFBB (L) Undeter-

mined
H'FFBC MR H'00
H'FFBD (MR) H'00
H'FFBE MMR H'00
H'FFBF (MMR) H'00

Legend
MULT: Multiplier
Rev. 3.0, 02/99, page 860 of 904

Appendix D Pin Function Selection
D.1 Port 3 Function Selection

Table D-1 IPU and P3DDR Settings and Selected Functions of P30 /T1OC1
DOE11, 10 (T1OERA) 00 01, 10, 11

P30DDR 0 1 Don't care
Selected function P30 input port P30 output port T1OC1 output
DOE21, 20 (T1OERA) 00 01, 10, 11

DOE31, 30 (T1OERB) 00 01, 10, 11

DOE41, 40 (T1OERB) 00 01, 10, 11

DOE11, 10 (T2OER) 00 01, 10, 11

Rev. 3.0, 02/99, page 861 of 904

DOE21, 20 (T2OER) 00 01, 10, 11


Table D-7 IPU and P4DDR Settings and Selected Functions of P40 /T4IOC1
GOE11, 10 (T4OER) 00 Don't care 01, 10, 11

IEG11, 10 (T4CRL) 00 01, 10, 11 00
P40DDR 0 1 0 1 0 1
Selected function P40 input P40 output P40 input P40 output T4IOC1 output
port port port port
T4IOC1 input

IEG21, 20 (T4CRL) 00 01, 10, 11 00
P41DDR 0 1 0 1 0 1
port port port port
T4IOC2 input

IEG11, 10 (T5CRL) 00 01, 10, 11 00
P42DDR 0 1 0 1 0 1
port port port port
T5IOC1 input
Rev. 3.0, 02/99, page 862 of 904


IEG21, 20 (T5CRL) 00 01, 10, 11 00
P43DDR 0 1 0 1 0 1
port port port port
T5IOC2 input

IEG11, 10 (T6CRL) 00 01, 10, 11 00
P44DDR 0 1 0 1 0 1
port port port port
T6IOC1 input

IEG21, 20 (T6CRL) 00 01, 10, 11 00
P45DDR 0 1 0 1 0 1
port port port port
T6IOC2 input

IEG11, 10 (T7CRL) 00 01, 10, 11 00
P46DDR 0 1 0 1 0 1
port port port port
T7IOC1 input
Rev. 3.0, 02/99, page 863 of 904


IEG21, 20 (T7CRL) 00 01, 10, 11 00
P47DDR 0 1 0 1 0 1
port port port port
T7IOC2 input

GOE11, 10 (T1OERA) 00 Don't care 01, 10, 11

IEG11, 10 (T1CRAL) 00 01, 10, 11 00
P50DDR 0 1 0 1 0 1
port port port port
T1IOC1 input

IEG21, 20 (T1CRAL) 00 01, 10, 11 00
P51DDR 0 1 0 1 0 1
port port port port
T1IOC2 input
Rev. 3.0, 02/99, page 864 of 904

GOE31, 30 (T1OERB) 00 Don't care 01, 10, 11

IEG31, 30 (T1CRB) 00 01, 10, 11 00
P52DDR 0 1 0 1 0 1
port port port port
T1IOC3 input

IEG41, 40 (T1CRB) 00 01, 10, 11 00
P53DDR 0 1 0 1 0 1
port port port port
T1IOC4 input

IEG11, 10 (T2CRL) 00 01, 10, 11 00
P54DDR 0 1 0 1 0 1
port port port port
T2IOC1 input

IEG21, 20 (T2CRL) 00 01, 10, 11 00
P55DDR 0 1 0 1 0 1
port port port port
T2IOC2 input
Rev. 3.0, 02/99, page 865 of 904


IEG11, 10 (T3CRL) 00 01, 10, 11 00
P56DDR 0 1 0 1 0 1
port port port port
T3IOC1 input

IEG21, 20 (T3CRL) 00 01, 10, 11 00
P57DDR 0 1 0 1 0 1
port port port port
T3IOC2 input
Rev. 3.0, 02/99, page 866 of 904

Table D-23 P67CR, PWM3, IRQCR, and P6DDR Settings and Selected Functions of
,542/PW3
P60/,54
PW3E (P67CR) 0 1
OE (TCR: PWM3) * 0 1
IRQ2E (IRQCR) 0 1 0 1 0 1
P61DDR 0 1 0 1 0 1 0 1 0 1 0 1
Selected function P60 P60 IRQ2 input P60 P60 IRQ2 input PW3 output PW3 output
input output input output and IRQ2
P60 P60 P60 P60
port port port port input
input output input output
port port port port
,543
Table D-24 IRQCR and P6DDR Settings and Selected Functions of P6 1/,54
IRQ3E (IRQCR) 0 1
P61DDR 0 1 0 1
Selected function P61 input port P61 output port P61 input port P61 output port
IRQ3 input
Table D-25 IPU and P6DDR Settings and Selected Functions of P62 /TCLK1
TPSC3−0 (TCRH) 0000−1100, 1110, 1111 1101

P62DDR 0 1 0 1
TCLK1 input
TPSC3−0 (TCRH) 0000−1101, 1111 1110

P63DDR 0 1 0 1
TCLK2 input
Rev. 3.0, 02/99, page 867 of 904

TPSC3−0 (TCRH) 0000−1110 1111

P64DDR 0 1 0 1
TCLK3 input

,540
Table D-28 IRQCR and P7DDR Settings and Selected Functions of P7 0/,54
IRQ0E (IRQCR) 0 1
P70DDR 0 1 0 1
IRQ0 input
Table D-29 IRQCR and A/D Converter, and P7DDR Settings and Selected Functions of
,541/$'75*
P71/,54 $'75*
TRGE (ADCR: A/D) 0 0 1 1

IRQ1E (IRQCR) 0 1 0 1
P71DDR 0 1 0 1 0 1 0 1
Selected function *1 *2 *1 *2 *1 *2 *1 *2
IRQ1 input ADTRG input IRQ1 and
ADTRG input
Notes: 1. P71 input port
2. P71 output port
Table D-30 SCI1 and P7DDR Settings and Selected Functions of P72 /TXD1
TE (SCR: SCI1) 0 1
P72DDR 0 1 0 1
Selected function P72 input port P72 output port TXD1 output
Rev. 3.0, 02/99, page 868 of 904

Table D-31 SCI1 and P7DDR Settings and Selected Functions of P73 /RXD1
RE (SCR: SCI1) 0 1
P73DDR 0 1 0 1
Selected function P73 input port P73 output port RXD1 input
Table D-32 SCI2 and P7DDR Settings and Selected Functions of P74 /TXD2
TE (SCR: SCI2) 0 1
P74DDR 0 1 0 1
Selected function P74 input port P74 output port TXD2 output
Table D-33 SCI2 and P7DDR Settings and Selected Functions of P75 /RXD2
RE (SCR: SCI2) 0 1
P75DDR 0 1 0 1
Selected function P75 input port P75 output port RXD2 input
Table D-34 P67CR, PWM1, SCI1, and P7DDR Settings and Selected Functions of
P76/SCK1/PW1
PW1E (P67CR) 0 1
C/A (SMR: SCI1) 0 1 * *
CKE1 (SMR: SCI1) 0 1 0 1 0 1 0 1
CKE0 (SMR: SCI1) 0 1 * * * * * * *
P76DDR 0 1 * * * * 0 1 0 1 * *
Selected function P76 P76 SCK1 SCK1 SCK1 SCK1 P76 P76 P76 P76 PW1 PW1
input output output input output input input output input output output output
port port port port port port and
and and SCK1
SCK1 SCK1 input
input input
Rev. 3.0, 02/99, page 869 of 904

Table D-35 P67CR, PWM2, SCI2, and P7DDR Settings and Selected Functions of
P72/SCK2/PW2
PW2E (P67CR) 0 1
C/A (SMR: SCI2) 0 1 * *
CKE1 (SMR: SCI2) 0 1 0 1 0 1 0 1
CKE0 (SMR: SCI2) 0 1 * * * * * * *
P77DDR 0 1 * * * * 0 1 0 1 * *
Selected function P77 P77 SCK2 SCK2 SCK2 SCK2 P77 P77 P77 P77 PW2 PW2
input output output input output input input output input output output output
port port port port port port and
and and SCK2
SCK7 SCK7 input
input input
D.6 Port A Function Selection

Table D-36 Operating Mode, PACR, IPU, PWM3, and PADDR Settings, and Selected
Functions of PA0/A16/T4OC1/PW1
Operating mode Modes 1, 2, 6, 7 Mode Mode 4

3 or 5
PW1E (PACR) 0 1 * 0 1
OE (TCR: PWM1) * 0 1 * * 0 1
DOE11, 10 (T4OER) 00 01,10, * * * * * *
11
PA0DDR 0 1 * 0 1 * * 0 1 0 1 *
Selected function PA0 PA0 T4OC1 PA0 PA0 PW1 A16 PA0 A16 PA0 PA0 PW1
input output output input output output address input address input output output
port port port port bus port bus port port
Rev. 3.0, 02/99, page 870 of 904


3 or 5
PW2E (PACR) 0 1 * 0 1
OE (TCR: PWM2) * 0 1 * * 0 1
DOE21, 20 00 01,10, * * * * * *
(T4OER) 11
PA1DDR 0 1 * 0 1 * * 0 1 0 1 *

3 or 5
PW3E (PACR) 0 1 * 0 1
OE (TCR: PWM3) * 0 1 * * 0 1
DOE11, 10 (T5OER) 00 01,10, * * * * * *
11
PA2DDR 0 1 * 0 1 * * 0 1 0 1 *
Rev. 3.0, 02/99, page 871 of 904

Table D-39 (1) Operating Mode, PACR, IPU, SCI3, and PADDR Settings, and Selected
Functions of PA3/A19/T5OC2/SCK3
Operating mode Modes 1, 2, 6, 7 Mode 3

or 5
SCK3E (PACR) 0 1 *
C/A (SMR: SCI3) * 0 *
CKE1 (SMR: SCI3) * 0 1 *
CKE0 (SMR: SCI3) * 0 1 0 1 *
DOE11, 10 (T5OER) 00 01,10, * * * * *
11
PA3DDR 0 1 * 0 1 * * * *
Selected function PA3 PA3 T5OC2 PA3 PA3 SCK3 SCK3 SCK3 A19
input port output output input port output output input input address
port port bus
Table D-39 (2) Operating Mode, PACR, IPU, SCI3, and PADDR Settings, and Selected
Functions of PA3/A19/T5OC2/SCK3
Operating mode Mode 4

SCK3E (PACR) 0 1
C/A (SMR: SCI3) * 0
CKE1 (SMR: SCI3) * 0 1
CKE0 (SMR: SCI3) * 0 1 0 1
DOE11, 10 (T5OER) * * * * *
PA3DDR 0 1 0 1 * * *
Selected function PA3 input A19 address PA3 input PA3 output SCK3 SCK3 SCK3
port bus port port output input input
Table D-40 Operating Mode, WCR and PADDR Settings, and Selected Functions of
:$,7
PA4/:$,7
Operating Mode Modes 1 to 6 Mode 7

WMS1 (WCR) 0 1 Don't care
PA4DDR 0 1 0 1 0 1
Selected function PA4 input PA4 output WAIT input PA4 input PA4 output
port port port port
Rev. 3.0, 02/99, page 872 of 904

Table D-41 (1) Operating Mode, PACR, BRCR, IPU, SCI3, and PADDR Settings, and
%5(4/RXD
%5(4
Selected Functions of PA5/T3OC1/%5(4 3
Operating mode Modes 1 to 6

RXD3E (PACR) 0 1 1
RE (SCR: SCI3) * 0 1
BRLE (BRCR) 0 1 0 1 0 1
DOE11, 10 (T3OER) 00 01,10, * 00 01,10, * * *
11 11
PA5DDR 0 1 * * 0 1 * * * *
Selected function PA5 PA5 T3OC1 %5(4 PA5 PA5 T3OC1 %5(4 RXD3 %5(4
input output output input input output output input input input
port port port port and
RXD3
input
%5(4/RXD
%5(4
Selected Functions of PA5/T3OC1/%5(4 3

RXD3E (PACR) 0 1 1
RE (SCR: SCI3) * 0 1
BRLE (BRCR) * * *
DOE11, 10 (T3OER) 00 01,10,11 00 01,10,11 *
PA5DDR 0 1 * 0 1 * *
Selected function PA5 input PA5 output T3OC1 PA5 input PA5 output T3OC1 RXD3
port port output port port output input
Rev. 3.0, 02/99, page 873 of 904

%$&./TXD
%$&.
Selected Functions of PA6/T3OC2/%$&. 3
Operating mode Modes 1 to 6

TXD3E (PACR) 0 1 1
TE (SCR: SCI3) * 0 1
BRLE (BRCR) 0 1 0 1 0 1
DOE21, 20 (T3OER) 00 01,10,11 * * * * *
PA6DDR 0 1 * * 0 1 * * *
Selected function PA6 PA6 T3OC2 %$&. PA6 PA6 %$&. TXD3 %$&.
input output output output input output output output output
port port port port
Note: For the H8/538, refer to the case where TXD3E = 0.
%$&./TXD
%$&.
Selected Functions of PA6/T3OC2/%$&. 3

TXD3E (PACR) 0 1 1
TE (SCR: SCI3) * 0 1
BRLE (BRCR) * * *
DOE21, 20 (T3OER) 00 01,10,11 * *
PA6DDR 0 1 * 0 1 *
Selected function PA6 input PA6 output T3OC2 PA6 input PA6 output TXD3 output
port port output port port
Rev. 3.0, 02/99, page 874 of 904

Appendix E I/O Port Block Diagrams
Port 1
Modes 1 to 6
Write to P1DDR
Write to P1DR
Read P1DR
Read external
address
Write to external
address
Read/write
control Reset
CLR
Q D
P1nDDR
CK
Internal data bus (PDB8 to PDB15)

Output multiplexer
CLR
P1n Q D
P1nDR
CK
(n = 0−7)
Input multiplexer
Figure E-1 Port 1 Block Diagram
Rev. 3.0, 02/99, page 875 of 904

Port 2
Mode 1, 3, 4, 5,
or 6
Write to P2DDR
Write to P2DR
Read P2DR
Read external
address
Write to external
address
Read/write
control Reset
CLR
Q D
P2nDDR
CK

Output multiplexer
CLR
P2n Q D
P2nDR
CK
(n = 0−7)
Input multiplexer
Rev. 3.0, 02/99, page 876 of 904

Port 3
IPU output
enable
Write to P3DDR
Write to P3DR
Port 3 direction Read P3DR
control
Reset
CLR
Q D
P3nDDR

CK
Output multiplexer
CLR
P3n Q D
P3nDR
CK
(n = 0−5)
Input multiplexer
IPU compare match output

(T1OC1, to T2OC 4 , T2OC1, T2OC2 )
Rev. 3.0, 02/99, page 877 of 904

Port 4
IPU output
enable
IPU input
capture enable
Port 4 direction
control Write to P4DDR
Write to P4DR
Read P4DR
Reset
CLR
Q D
P4nDDR

CK
Output multiplexer
CLR
P4n Q D
P4nDR
CK
(n = 0−7)
Input multiplexer
IPU compare match output (T4IOC1,T4IOC2 ,
T5IOC1, T5IOC2 , T6IOC1, T6IOC2 ,
T7IOC1, T7IOC2 )
IPU input capture (T4IOC1 ,T4IOC2 ,
T5IOC1, T5IOC2 , T6IOC1, T6IOC2 ,
T7IOC1, T7IOC2 )
Rev. 3.0, 02/99, page 878 of 904

Port 5
IPU output
enable
IPU input
capture enable
Port 5 direction
control Write to P5DDR
Write to P5DR
Read P5DR
Reset
CLR
Q D
P5nDDR

CK
Output multiplexer
CLR
P5n Q D
P5nDR
CK
(n = 0−7)
Input multiplexer
(T1IOC1 to T1IOC4 , T2IOC1 ,
T2IOC 2 , T3IOC1 , T3IOC2 )
IPU input capture
(T1IOC1 to T1IOC4 , T2IOC1 ,
T2IOC , T3IOC1 , T3IOC 2 )
Rev. 3.0, 02/99, page 879 of 904

Port 6
PW3E
Write P6DDR
Write P6DR
Port 6 direction Read P6DR
control
IRQ2 input
enable
CLR
Q D
P60DDR

CK
Output multiplexer
CLR
P60 Q D
P60DR
CK
Input multiplexer
PW3 output
Edge detector
IRQ2 input
Figure E-6 Port 6 Block Diagram (1)
Rev. 3.0, 02/99, page 880 of 904

Port 6
IRQ3 input enable
Write to P6DDR
Write to P6DR
Read P6DR
Reset
CLR
Q D
P6nDDR

CK
CLR
P61 Q D
P6nDR
CK
Input multiplexer
Edge detector
IRQ3 input
Rev. 3.0, 02/99, page 881 of 904

Port 6
IPU external clock

input enable
Write to P6DDR
Write to P6DR
Read P6DR
Reset
CLR
Q D
P6nDDR

CK
CLR
P6n Q D
P6nDR
CK
(n = 2−4)
Input multiplexer
IPU external clock input

(TCLK1 to TCLK 3)
Rev. 3.0, 02/99, page 882 of 904

Port 7
IRQ0 input enable
Write to P7DDR
Write to P7DR
Read P7DR
Reset
CLR
Q D
P70DDR

CK
CLR
P70 Q D
P70DR
CK
Input multiplexer
IRQ0 input
Rev. 3.0, 02/99, page 883 of 904

Port 7
IRQ1 input enable
ADTRG input enable
Write to P7DDR
Write to P7DR
Read P7DR
Reset
CLR
Q D
P71DDR

CK
CLR
P71 Q D
P71DR
CK
Input multiplexer
IRQ1 input
ADTRG input
Edge detector
Rev. 3.0, 02/99, page 884 of 904

Port 7
SCI transmit
enable
Port 7 direction Write to P7DDR

control
Write to P7DR
Read P7DR
Reset
CLR
Q D
P7nDDR

CK
Output multiplexer
CLR
P7n Q D
P7nDR
CK
(n = 2, 4)
Input multiplexer
SCI transmit data output
(TXD1, TXD2)
Rev. 3.0, 02/99, page 885 of 904

Port 7
SCI receive
enable
Port 7 direction Write to P7DDR

control
Write to P7DR
Read P7DR
Reset
CLR
Q D
P7nDDR

CK
CLR
P7n Q D
P7nDR
CK
(n = 3, 5)
Input multiplexer
SCI receive data input

(RXD1, RXD2)
Rev. 3.0, 02/99, page 886 of 904

Port 7
Port 7 direction
control SCI serial clock
input enable
SCI serial clock

output enable
PWM enable
PWM output enable
P7DDR write
P7DR write
P7DR read
Reset
CLR
Q D
P7nDDR

CK
Output
multiplexer
CLR
P7n Q D
P7nDR
CK
(n = 6, 7)
Input multiplexer
SCI serial clock output
(SCK1, SCK2)
PWM output (PW1, PW2)
SCI serial clock input

(SCK1, SCK2)
Rev. 3.0, 02/99, page 887 of 904

Port 8
A/D converter
input sampling
Read P8DR

P8n
(n = 0−3)
A/D converter analog input

(AN8 to AN11)
Port 9
A/D converter
input sampling
Read P9DR
P9n
(n = 0−7)
A/D converter analog input

(AN0 to AN7)
Rev. 3.0, 02/99, page 888 of 904

Port A
Mode 1, 2, 6, or 7
Mode 4
Port A direction
control Mode 3 or 5
Software standby mode
Bus released
IPU output enable

(T4OC1, T4OC2, T5OC1)
PWM enable
PWM output enable
PADDR write
PADR write
PADR read
Reset
CLR
Q D
PAnDDR
Internal address bus (PAB16 to PAB19)

CK

PAn CLR
Q D
PAnDR
(n = 0−2) CK
Output
multiplexer
Input multiplexer

(T4OC1, T4OC2, T5OC1)
PWM output (PW1 to PW3)
Figure E-16 Port A Block Diagram (1)
Rev. 3.0, 02/99, page 889 of 904

H8/539 Port A
Mode 1, 2, 6, or 7
Mode 4
Port A direction
controller Mode 3 or 5
Software standby mode
Bus release
IPU output enable

(T5OC2)
SCK serial clock enable
SCK serial clock output enable
SCK serial clock input enable
PADDR write
PADR write
PADR read
Reset
CLR
Q D
PAnDDR
Internal address bus (PAB16 to PAB19)

CK

PA3 CLR
Q D
PAnDR
CK
Output
multiplexer
Input multiplexer
IPU compare-match output

(T5OC2)
SCK serial clock output (SCK3)
SCK serial clock input (SCK3)
Rev. 3.0, 02/99, page 890 of 904

Port A
WAIT input enable
Write to PADDR
Port A direction Write to PADR
control Read PADR
Reset
CLR
Q D
PA4DDR
CK

CLR
PA4 Q D
PA4DR
CK
Input multiplexer
WAIT input
Rev. 3.0, 02/99, page 891 of 904

Port A
Modes 1 to 6
Bus release enable
IPU output enable (T3OC1)

RXD3 enable
RXD3 input enable
Port A direction Write to PADDR
control Write to PADR
Read PADR
Reset
CLR
Q D
PA5DDR
CK

CLR
PA5 Q D
PA5DR
CK
Output
multiplexer
Input multiplexer

(T3OC1)
BREQ input
Rev. 3.0, 02/99, page 892 of 904

Port A
Modes 1 to 6
Bus release enable
Port A direction
control
IPU output enable (T3OC2)
TXD3 enable
TXD3 output enable
Write to PADDR
Write to PADR
Read PADR
Reset
CLR
Q D
PA6DDR
CK

PA6 CLR
Q D
PA6DR
CK
Output multiplexer
Input multiplexer
BACK output

(T3OC2)
TXD3 output
Rev. 3.0, 02/99, page 893 of 904

Port B
Mode 1, 3, 5, or 6
Software standby
mode
Mode 2 or 4
Bus released
Mode 7
Write to PBPCR
Port B direction Write to PBDDR
control
Write to PBDR
Read PBDR
Reset
CLR
Q D
Input pull-up control PBnPCR
CK
CLR
Q D
PBnDDR
CK

PBn CLR
Q D
PBnDR
Output multiplexer
(n = 0−7) CK
Input multiplexer
Figure E-21 Port B Block Diagram
Rev. 3.0, 02/99, page 894 of 904

Port C
Mode 1, 3, 5, or 6
Software standby
mode
Mode 2 or 4
Bus released
Mode 7
Write to PBCPCR
Port C direction Write to PCDDR
control
Write to PCDR
Read PCDR
Reset
CLR
Q D
Input pull-up control PCnPCR
CK
CLR
Q D
PCnDDR
CK

PCn CLR
Q D
PCnDR
Output multiplexer
(n = 0−7) CK
Input multiplexer
Figure E-22 Port C Block Diagram
Rev. 3.0, 02/99, page 895 of 904

Appendix F Memory Maps
Expanded Minimum Modes

H'0000 H'0000
Vector table Vector table
H'00FF H'00FF
H'0100 H'0100
On-chip ROM
memory space
H'3FFF
H'4000 External
H'EE7F H'EE7F memory space
H'EE80 H'EE80
On-chip RAM On-chip RAM
H'FE7F (4 kbytes) H'FE7F (4 kbytes)
H'FE80 On-chip registers H'FE80 On-chip registers
H'FFFF H'FFFF
Expanded Maximum Modes Single-Chip Mode

Modes 3 and 5 Mode 4 Mode 7
H'00000 H'00000 H'00000

Vector table Vector table H'001FF Vector table
H'001FF H'001FF
H'00200
H'00200 H'00200 On-chip ROM
H'03FFF
(16 kbytes)
H'04000
On-chip ROM
External (16 kbytes) H'0EE7F
memory space H'0EE80 On-chip RAM
Page 0 Page 0 (4 kbytes)
H'03FFF
H'0FE7F
H'04000 External memory H'0FE80 On-chip registers
H'0EE7F H'0EE7F space
H'0FFFF (384 bytes)
H'0EE80 On-chip RAM H'0EE80
On-chip RAM H'10000
(4 kbytes) (4 kbytes) On-chip ROM
H'0FE7F H'0FE7F (64 kbytes)
H'0FE80 On-chip registers H'0FE80 On-chip registers H'1FFFF
H'20000 On-chip ROM
(384 bytes) H'0FFFF (384 bytes)
H'0FFFF (64 kbytes)
H'10000 H'10000 H'2FFFF
External On-chip ROM
Page 1 Page 1
memory space (64 kbytes)
H'1FFFF
H'1FFFF
H'20000
H'20000 On-chip ROM
(64 kbytes)
Pages H'2FFFF Pages
2 to 15 H'30000 2 to 15
External
memory space
H'FFFFF H'FFFFF
Rev. 3.0, 02/99, page 896 of 904

Appendix G Pin States
G.1 States of I/O Ports

Table G-1 States of I/O Ports
Program
Execution
Hardware Software Bus Mode
Standby Standby Sleep Release (normal
Pin Name Mode Reset Mode Mode Mode Mode operation)
φ  Clock T H Clock Clock Clock
output output output output
5', $6, 1−6 H T T H T 5', $6,
+:5, /:5 +:5, /:5
7 H T T H H 
P17−P10 1−6 T T T T T D15−D8
7 keep keep keep I/O port
P27−P20 1, 3−5, 6 T T T T T D7−D0
2, 7 keep keep keep I/O port
P35−P30
1
1−7 T T keep* keep keep I/O port
P47−P40
P57−P50
P64−P60
P77−P70
P84−P80 1−7 T T T T T Input port
P97−P90
PA6−PA4
2 3 4
1−7 T T keep* keep* keep* I/O port or
control
input/output
PA3−PA0 3, 5 L T T L T A19−A16
1
1, 2, 4, 6, 7 T keep* keep keep I/O port
PB7–PB0 1, 3, 5, 6 L T T L T A15−A0
PC7–PC0
2, 4, 7 T keep keep keep I/O port
Legend
H: High, L: Low, T: High-impedance state
keep: Input pins are in the high-impedance state; output pins maintain their previous state.
Notes: 1. The on-chip supporting modules are reset, so these pins become input or output pins
according to their DDR and DR bits.
2. If PA5 is set for %$&. output, it goes to the high-impedance state.
3. %5(4 can be received, and %$&. is high.
Rev. 3.0, 02/99, page 897 of 904
4. %$&. is low.
and the lower half (D7 to D0) is disabled. After the BCRE bit in the bus control register
(BCR) has been set to 1 by software, the bus width can be changed to 16 bits (D15 to
D0) by a byte area top register (ARBT) setting. In modes 1, 3, and 4, the external bus
space has a 16-bit bus width (D15 to D0) after a reset, but this can be changed to 8 bits
by an ARBT setting. In this case, the upper half of the data bus (D15 to D8) is enabled,
and the lower half (D7 to D0) is disabled. For details of the settings, see section 16, Bus
Controller.
Rev. 3.0, 02/99, page 898 of 904

G.2 Pin States at Reset
(1) Modes 1 and 6: Figure G-1 is a timing diagram for the case in which 5(6 goes low during
three-state access in mode 1 or 6. As soon as 5(6 goes low, all ports are initialized to the input
state. $6, 5', /:5, and +:5 go high, and D15 to D0 go to the high-impedance state. A15 to A0
are initialized to the low state 1.5 system clock cycles (1.5φ) after the low level of 5(6 is sampled.
RES is sampled here
3-state external access

T1 T2 T3
RES
Internal reset
signal
A15−A0 H'0000
AS, RD
LWR, HWR
High impedance
D15−D0
High impedance
I/O ports
1.5φ
Figure G-1 Reset during Three-State Access (Modes 1 and 6)
Rev. 3.0, 02/99, page 899 of 904

(2) Mode 2: Figure G-2 is a timing diagram for the case in which 5(6 goes low during three-state
access in mode 2. As soon as 5(6 goes low, all ports are initialized to the input state. $6, 5',
/:5, and +:5 go high, and D15 to D8 go to the high-impedance state. A15 to A0 are initialized as
soon as 5(6 goes low, and become input ports.
RES is sampled here

T1 T2 T3
φ
RES
Internal reset
signal
High impedance
A15−A0
AS, RD
HWR
High impedance
D15−D8
High impedance
I/O ports
Figure G-2 Reset during Three-State Access (Mode 2)
Rev. 3.0, 02/99, page 900 of 904

(3) Modes 3 and 5: Figure G-3 is a timing diagram for the case in which 5(6 goes low during
three-state access in mode 3 or 5. As soon as 5(6 goes low, all ports are initialized to the input
state. $6, 5', /:5, and +:5 go high, and D15 to D0 go to the high-impedance state. A19 to A0
are initialized to the low state 1.5 system clock cycles (1.5φ) after the low level of 5(6 is sampled.
RES is sampled here

T1 T2 T3
RES
Internal reset
signal
A19−A0 H'0000
AS, RD
LWR, HWR
High impedance
D15−D0
High impedance
I/O ports
1.5φ
Figure G-3 Reset during Three-State Access (Modes 3 and 5)
Rev. 3.0, 02/99, page 901 of 904

(4) Mode 4: Figure G-4 is a timing diagram for the case in which 5(6 goes low during three-state
access in mode 4. As soon as 5(6 goes low, all ports are initialized to the input state. $6, 5',
/:5, and +:5 go high, and D15 to D0 go to the high-impedance state. A19 to A0 are initialized as
soon as 5(6 goes low, and become input ports.
RES is sampled here

T1 T2 T3
φ
RES
Internal reset
signal
High impedance
A19−A0
AS, RD
LWR, HWR
High impedance
D15−D0
High impedance
I/O ports
Figure G-4 Reset during Three-State Access (Mode 4)
Rev. 3.0, 02/99, page 902 of 904

(5) Mode 7: Figure G-5 is a timing diagram for the case in which 5(6 goes low in mode 7. As
soon as 5(6 goes low, all ports are initialized to the input state.
RES is sampled here
RES
Internal reset
signal
High impedance
I/O ports
Figure G-5 Resetting of I/O Ports (Mode 7)
Rev. 3.0, 02/99, page 903 of 904

Appendix H Package Dimensions
Figure H-1 shows the FP-112 package dimensions of the H8/539F.
Unit: mm
23.2 ± 0.3
20
84 57
85 56
23.2 ± 0.3
0.65
112 29
1 28
*0.32 ± 0.08
3.05 Max
*0.17 ± 0.05
0.15 ± 0.04
0.30 ± 0.06 0.13 M

2.70
1.23 1.6
0° – 8°
0.10 +0.15
–0.10
0.8 ± 0.3
0.10
Hitachi Code FP-112

JEDEC —
*Dimension including the plating thickness EIAJ Conforms
Base material dimension Weight (reference value) 2.4 g
Figure H-1 Package Dimensions (FP-112)
Rev. 3.0, 02/99, page 904 of 904

 Hardware Manual
H8/539F-ZTAT
Publication Date: 1st Edition, January 1997
3rd Edition, February 1999
Published by: Electronic Devices Sales & Marketing Group
Semiconductor & Integrated Circuits Group
Hitachi, Ltd.
Edited by: Technical Documentation Group
UL Media Co., Ltd.
Copyright © Hitachi, Ltd., 1997. All rights reserved. Printed in Japan.

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Keep safety first in your circuit designs!

Notes regarding these materials

The H8/539F is an original Hitachi high-performance single-chip microcontroller with a high-

Notes: 1. F-ZTAI (Flexible-ZTAT) is a trademark of Hitachi, Ltd.

Rev. 3.0, 02/99, page v of 904

Portions of H8/539F Manual Describing Points of Difference

H8/539F H8/539F S-Mask H8/539F A-Mask

Rev. 3.0, 02/99, page vi of 904

Section 1 Overview ...........................................................................................1

Section 2 CPU ...................................................................................................33

Rev. 3.0, 02/99, page vii of 904

Section 3 MCU Operating Modes..................................................................... 71

Rev. 3.0, 02/99, page viii of 904

Section 5 H8 Multiplier (H8MULT) .................................................................99

Section 6 Interrupt Controller ........................................................................... 119

Section 7 Data Transfer Controller ................................................................... 139

Section 8 Wait-State Controller.........................................................................159

Section 9 Clock Pulse Generator .......................................................................169

Section 10 I/O Ports...........................................................................................175

Section 11 16-Bit Integrated-Timer Pulse Unit.................................................253

Section 12 PWM Timers ................................................................................... 363

Section 13 Watchdog Timer.............................................................................. 373

Section 14 Serial Communication Interface...................................................... 389

Section 15 A/D Converter .................................................................................449

Section 16 Bus Controller .................................................................................479

Section 17 RAM (H8/539F).............................................................................. 503

Section 18 RAM (H8/539F S-Mask and A-Mask Models)............................... 507

Section 19 Flash Memory (H8/539F) Dual power source system

Section 20 Flash Memory

Section 21 Power-Down State........................................................................... 673

Rev. 3.0, 02/99, page xviii of 904

Section 23 Electrical Characteristics (H8/539F S-Mask model).......................707

Section 24 Electrical Characteristics (H8/539F A-Mask model) ......................729

Appendix A Instruction Set............................................................................... 751

Appendix B Initial Values of CPU Registers.................................................... 820

Appendix C On-Chip Registers......................................................................... 821

Appendix D Pin Function Selection.................................................................. 861

Appendix E I/O Port Block Diagrams............................................................... 875

Appendix F Memory Maps ............................................................................... 896

Appendix H Package Dimensions .....................................................................904

Rev. 3.0, 02/99, page xxi of 904

Note: * ZTAT™ is a trademark of Hitachi, Ltd.

Table 1-1 lists the main features of the H8/539F.

Rev. 3.0, 02/99, page 1 of 904

Two operating modes

Highly orthogonal instruction set

Register and memory addressing modes

Instruction set optimized for C language

Memory • RAM: 4-kbyte high-speed on-chip RAM

Rev. 3.0, 02/99, page 2 of 904

Clock source can be selected independently for each channel

Two counting modes

Three types of pulse output

Automatic measurement functions

Serial • Asynchronous or clocked synchronous mode (selectable)