Unit 4 - Logic Gates

Digital Electronic Systems Unit 4
Logic Gates
The term gate is used to describe a circuit that performs a basic logic operation. All gates
have both inputs and outputs. The number of inputs can vary depending on the gate in
question but there is generally only one output.
As discussed in unit 1, there are three primary logic gates from which, by various
combinations, all other gates can be made. These are the NOT Gate (inverter), the AND Gate
and the OR Gate. This unit revisits these gates and proceeds to introduce a number of other
gates.
NOT Gate (Inverter)
The NOT gate has a single input and a single output. The gate very simply inverts the input.
The symbol and truth table for the NOT gate are shown below.
Symbol
Input A
Output F
The circle on the symbol indicates that the output F is the inverse (or complement) of the
input A.
Truth Table
A
0
1
F
1
0
The above table is known as a truth table. In this table, every possible combination of input
is written in order and the output is determined for each input. There are 2 n possible
combinations in the case of an n-input gate. In other words, there are two possible
combinations in the case of a one-input gate, four possible combinations of input in the case
of a two-input gate etc..
Boolean Expression
or verbally
FA
F = A bar
Boolean algebra is the mathematics of digital systems. A letter designates a variable and a
bar over a letter designates the inverse (or complement) of the variable. More generally, a bar
over a quantity designates the inverse (or complement) of that quantity.
AND Gate
The AND gate has multiple inputs and a single output. The output of any AND gate is HIGH
only when all of its inputs are HIGH.
Symbol
Input A
Output F
Input B
In this case the output is HIGH (or logic level 1) only if the inputs A and B are HIGH (or
logic level 1). Thus we can write a table defining all the possible states that might occur for
this two input AND gate.
Truth Table
A
0
0
1
1
B
0
1
0
1
F
0
0
0
1
Boolean Expression
F= A. B
or verbally
F = A and B
The AND gate performs Boolean Multiplication as illustrated in the timing diagram below.
Boolean multiplication follows the same rules as binary multiplication, as discussed in unit 2.
Timing Diagram
INPUT A
INPUT B
OUTPUT
Timing Diagram for an AND gate
3-Input AND Gate

Symbol
Input A
Output F
Input B
Input C
Truth Table
A
0
0
0
0
1
1
1
1
B
0
0
1
1
0
0
1
1
C
0
1
0
1
0
1
0
1
F
0
0
0
0
0
0
0
1
As can be seen when we have a three input AND gate the same rule applies as did for the two
input gate, i.e. ALL the inputs must be HIGH if we are to achieve a HIGH on the output.
Boolean Expression
F= A. B . C
Or more commonly, it is written as
F = ABC
In boolean expressions, when variables are written next to each other with no symbol in
between, it is implicitly assumed that they are ANDed.
OR Gate
The OR gate can have two or more inputs. The output of an OR gate is HIGH when one or
more of the inputs are HIGH.
Symbol
Input A
Output F
Input B
Truth Table
A
0
0
1
1
B
0
1
0
1
F
0
1
1
1
Boolean Expression
F= A+ B
Or verbally
F = A or B
The OR gate performs Boolean Addition - not to be confused with binary addition as
discussed in unit 2.
Timing Diagram
INPUT A
INPUT B
OUTPUT
Timing Diagram for an OR gate
3-Input OR Gate
Symbol
Input A
Input B
Output F
Input C
Truth Table
A
0
0
0
0
1
1
1
1
B
0
0
1
1
0
0
1
1
C
0
1
0
1
0
1
0
1
F
0
1
1
1
1
1
1
1
Again it can be seen from the table that the output is LOW only when all the inputs are LOW.
Boolean Expression
F = A+ B + C
Now that the three basic gates have been considered, they can be combined to generate other
operations.
NAND Gate
This is a combination of the AND gate and the NOT gate in that order.
Symbol
Input A
Output F
Input B
Input A
AB
Output F AB
Input B
Both representations are equivalent. Note that the bubble (o) in the top symbol indicates
the presence of an inverter on the output line. The top representation is more common. The
bottom representation indicates how a NAND gate may be broken down.
Truth Table
A
0
0
1
1
B
0
1
0
1
F
1
1
1
0
Boolean Expression
F AB
Or more commonly,
F AB
As can be seen from the table, the inputs are ANDed together and then NOTed (inverted) to
give the final output. The timing diagram shown below illustrates this.
Timing Diagram
INPUT A
INPUT B
OUTPUT
Timing Diagram for a NAND gate
NOR Gate
This is a combination of the OR gate and the NOT gate in that order.
Symbol
Input A
Output F
Input B
Input A
A+B
Output F A B
Input B
Both representations are equivalent. Note that the bubble (o) in the top symbol indicates
the presence of an inverter on the output line. The top representation is more common. The
bottom representation indicates how a NOR gate may be broken down.
Truth Table
A
0
0
1
1
B
0
1
0
1
F
1
0
0
0
Boolean Expression
F AB
As can be seen from the table, the inputs are ORed together and then NOTed (inverted) to
give the final output. The timing diagram shown below illustrates this.
Timing Diagram
INPUT A
INPUT B
OUTPUT
Timing Diagram for a NOR gate
XOR Gate (Exclusive OR)

Another gate which is made up of the AND, OR and NOT gates and which is commonly used
is an XOR gate. XOR gates connected to form an adder circuit allow a computer to perform
addition, subtraction, multiplication and division in its Arithmetic Logic Unit (ALU).
Shown below is its basic layout.
Logic Diagram
Input A
A.B
Input B
Output
F A.B A.B
A
A.B
Again this is too large to be commonly used so it is summarised into a small logic symbol,
which is shown below.
Symbol
Input A
Output F
Input B
The truth table for this symbol is shown below. It can be seen that the output goes HIGH
only when the inputs differ. If both inputs go HIGH the output goes LOW. If both inputs go
LOW the output goes LOW.
Truth Table
A
0
0
1
1
B
0
1
0
1
F
0
1
1
0
Timing Diagram
INPUT A
INPUT B
OUTPUT
Timing Diagram for an EXCLUSIVE OR (XOR) gate
Boolean Expression
The formula that describes the function of this gate is as follows.
F ABAB
This is more commonly expressed in Boolean algebra by a dedicated symbol an addition

sign enclosed in a circle, as follows:
F AB
XNOR Gate (Exclusive NOR)

This is a combination of the XOR gate and the NOT gate (Inverter) in that order.
Symbol
Input A
Output F
Input B
Truth Table
A
0
0
1
1
B
0
1
0
1
F
1
0
0
1
As can be seen from the truth table, the inputs are XORed together and then NOTed
(inverted) to give the final output.
9
Boolean Expression
F AB
Timing Diagram
INPUT A
INPUT B
OUTPUT
Timing Diagram for an Exclusive NOR (XNOR) Gate
Direct applications of the basic logic operations

(Terminology - A Bit is a Binary Digit. A byte is made up of 8 bits. )
Logic gates are the building blocks of computers. Most of the functions in a computer, with
the exception of certain types of memory, are implemented with logic gates used on a very
large scale. For example, a microprocessor, which is the main part of a computer, is made up
of hundreds and thousands of logic gates.
Application 1 - Computers need to selectively manipulate certain bits in one or more bytes of
data. Selective bit manipulations are achieved using a mask. For example, to clear (make all
0s) the right four bits in a data byte, but keep the information in the left four bits, the data
byte is ANDed with 11110000. Notice that any bit ANDed with zero will be 0 and any bit
ANDed with one will remain the same.
Ex 1: What is the resulting byte if 101010112 is ANDed with the mask 111100002?
Application 2 : Another mask operation that is used in computer programming selectively
makes certain bits in a data byte equal to 1 while not affecting any other bit. This is called
setting (setting a bit to 1). This is achieved using the OR operation. A mask is used that
contains a 1 in any position where a data bit is to be set.
Ex 2: How would one force the most significant bit in a data byte to equal 1, but leave all of
the other bits unchanged?
10
Active low inputs

An active low input is represented by either a small circle at the input point to a gate or by a
bar over the input variable on a data sheet. This small circle represents a NOT gate
(inverter).
Consider for example CS - chip select, an active low input to an integrated circuit. Chip
select is enabled only when the input voltage is low. The bar indicates that the input is
active low.
Shown below is an example of an AND gate with active low inputs.
Input A
Output F
Input B
Input A
A
Output F A.B
Input B
Truth Table
A
0
0
1
1
B
0
1
0
1
F
1
0
0
0
Timing Diagram
INPUT A
INPUT B
OUTPUT
Timing diagram for an AND

gate with active low inputs.
11

Unit 4 - Logic Gates

Uploaded by

Copyright:

Available Formats

Unit 4 - Logic Gates

Uploaded by

Document Information

Original Description:

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

Unit 4 - Logic Gates

Uploaded by

Copyright:

Available Formats

Digital Electronic Systems Unit 4

Digital Electronic Systems Unit 4

Timing Diagram for an AND gate

Digital Electronic Systems Unit 4

3-Input AND Gate

Digital Electronic Systems Unit 4

Timing Diagram for an OR gate

Digital Electronic Systems Unit 4

Digital Electronic Systems Unit 4

Timing Diagram for a NAND gate

Digital Electronic Systems Unit 4

Timing Diagram for a NOR gate

Digital Electronic Systems Unit 4

XOR Gate (Exclusive OR)

Digital Electronic Systems Unit 4

Timing Diagram for an EXCLUSIVE OR (XOR) gate

This is more commonly expressed in Boolean algebra by a dedicated symbol an addition

XNOR Gate (Exclusive NOR)

Digital Electronic Systems Unit 4

Timing Diagram for an Exclusive NOR (XNOR) Gate

Direct applications of the basic logic operations

Digital Electronic Systems Unit 4

Active low inputs

Timing diagram for an AND

You might also like