KIK614441 IC Part1

KIK614441
Integrated Circuit Technology

part 1
The Digital Revolution
ENIAC - The First Electronic

Computer (1949)
The Babbage Difference Engine (1832)
25,000 parts ; cost 17,470
Rabaey Digital Integrated Circuits 2nd
The Digital Revolution

First IC
Bipolar logic
1960s
ECL 3-input Gate
Motorola 1966
First transistor Bell Labs, 1948

Intel 4004
Micro-Processor
1971
1000 transistors
1 MHz operation
Intel Pentium IV
Microprocessor
Moore's Law
In 1965, Gordon Moore
noted that the number of
transistors on a chip
doubled every 18 to 24
months.
He made a prediction that
semiconductor
technology will double its
effectiveness every 18
months
http://www.extremetech.com/extreme/203490-moores-law-is-dead-long-live-moores-law
https://humanswlord.files.wordpress.com/2014/01/moores-law-graph-gif.png
Other Device
Cell
Phone
Small
Signal RF
Digital Cellular Market

(Phones Shipped)
Power
RF
Power
Management
1996 1997 1998 1999 2000

Units
48M 86M 162M 260M 435M
Analog
Baseband
Digital Baseband
(DSP + MCU)
Design Abstraction
SYSTEM
MODULE
+
GATE
CIRCUIT
DEVICE
G
S
n+
D
n+
IC Manufacture
http://www.ibtimes.co.uk/ibms-ultra-powerful-computer-chip-puts-moores-law-back-track-1510060
Sedra/Smith, Microelectronic Circuits 5/e, 2004 Oxford University Press.
Sand to Silicon Wafer
http://www.fullman.com/semiconductors/semiconductors.html
SEMICONDUCTORS:
Here, there, and everywhere!
3.1. Intrinsic Semiconductors

silicon atom
four valence
electrons
requires four more
to complete
outermost shell
each pair of shared
forms a covalent
bond
the atoms form a
lattice structure
Figure 3.1 Two-dimensional representation of the silicon

crystal. The circles represent the inner core of silicon atoms,
with +4 indicating its positive charge of +4q, which is
neutralized by the charge of the four valence electrons.
Observe how the covalent bonds are formed by sharing of the
valence electrons. At 0K, all bonds are intact and no free
electrons are available for current conduction.
The process of freeing electrons, creating holes, and filling

3.1.
Intrinsic
Semiconductors
them
facilitates
current flow
silicon at low temps

all covalent bonds are intact
no electrons are available for conduction
conducitivity is zero
silicon at room temp
some covalent bonds break, freeing an electron and
creating hole, due to thermal energy
some electrons will wander from their parent atoms,
becoming available for conduction
conductivity is greater than zero
Figure 3.2: At room temperature, some of the covalent bonds

are broken by thermal generation. Each broken bond gives
rise to a free electron and a hole, both of which become
available for current conduction.
3.1: Intrinsic Semiconductors
silicon at low temps:

all covalent bonds are intact
no electrons are available for
conduction
conducitivity is zero
silicon at room temp:

sufficient thermal energy
exists to break some covalent
bonds, freeing an electron
and creating hole
a free electron may wander
freeing electrons,
from its parentcreating
atom
a hole will attract neighboring
electrons
the process of
holes, and filling them facilitates current
flow
3.2. Doped Semiconductors

p-type semiconductor
Silicon is doped with
element having a
valence of 3.
To increase the
concentration of
holes (p).
One example is
boron, which is an
acceptor.
n-type semiconductor
element having a
valence of 5.
To increase the
concentration of free
electrons (n).
One example is
phosophorus, which
is a donor.
3.2. Doped Semiconductors

p-type semiconductor
element having a
valence of 3.
To increase the
concentration of
holes (p).
One example is
boron.
n-type semiconductor
element having a
valence of 5.
To increase the
concentration of free
electrons (n).
One example is
phosophorus, which
is a donor.
Figure 3.5: An electric field E established in a bar of silicon

causes the holes3.3.1.
to drift Drift
in the Current
direction of E and the free
electrons to drift in the opposite direction. Both the hole and
electron drift currents are in the direction of E.
Q: What happens when an electrical field (E) is

applied to a semiconductor crystal?
A: Holes are accelerated in the direction of E,
free electrons are repelled. HOLES
Q: How is the velocity of theseELECTRONS
holes defined?
p hole mobility
n electron mobility
vpdrift pE
vndrift nE
E electric field
E electric field
Figure 4.1 Physical structure of the enhancement-type NMOS transistor: (a) perspective view; (b) cross-section. Typically L = 0.1 to 3
m, W = 0.2 to 100 m, and the thickness of the oxide layer (tox) is in the range of 2 to 50 nm.
Microelectronic Circuits - Fifth Edition, Sedra/Smith
Figure 4.2 The enhancement-type NMOS transistor with a positive voltage applied to the gate. An n channel is
induced at the top of the substrate beneath the gate.
Figure 4.3 An NMOS transistor with vGS > Vt and with a small vDS applied. The device acts as a resistance whose
value is determined by vGS. Specifically, the channel conductance is proportional to vGS Vt and thus iD is
proportional to (vGS Vt) vDS. Note that the depletion region is not shown (for simplicity).
Figure 4.4 The iDvDS characteristics of the MOSFET in Fig. 4.3 when the voltage applied between drain and
source, vDS, is kept small. The device operates as a linear resistor whose value is controlled by vGS.
Figure 4.6 The drain current iD versus the drain-to-source voltage vDS for an enhancement-type NMOS
transistor operated with vGS > Vt.
Figure 4.9 Cross-section of a CMOS integrated circuit. Note that the PMOS transistor is formed in a separate
n-type region, known as an n well. Another arrangement is also possible in which an n-type body is used and
the n device is formed in a p well. Not shown are the connections made to the p-type body and to the n well; the
latter functions as the body terminal for the p-channel device.
Cross-sectional diagram of an nand p-MOSFET
A CMOS inverter schematic and its

layout
A set of photomasks for the n-well

CMOS inverter
Note that each layer requires a separate plate: (a), (d),

(e), and (f) dark-field masks; (b), (c), and (g) clear-field
masks.
N-Channel MOSFET: Physical

View
MOSFETs (metal-oxide-semiconductor field-effect transistors) are four-terminal

voltage-controlled switches.
Current flows between the diffusion terminals if the voltage on the gate terminal
is large enough to create a conducting channel, otherwise the mosfet is off
and the diffusion terminals are not connected.
MIT Open Course Ware 6.004 Computation Structures
N-Channel MOSFET: Electrical

View
The four terminals of a Field Effect Transistor (gate, source, drain and bulk)
connect to conductors that generate a set of electric fields in the channel region
which depend on the relative voltages of each terminal.
FETs Come in Two Flavors
NFET: n-type source/drain diffusions

in a p-type substrate. Positive
threshold voltage; inversion forms
ntype channel
PFET: p-type source/drain diffusions

in a n-type substrate. Negative
threshold voltage; inversion forms ptype channel.
The use of both NFETs and PFETs complimentary transistor types is a key
to CMOS (complementary MOS) logic families.
CMOS Recipe
If we follow two rules when constructing CMOS circuits, we can

model the behavior of the mosfets as simple voltage-controlled
switches:
Rule #1: only use NFETs in pulldown circuits
Rule #2: only use PFETs in pullup circuits
CMOS Inverter VTC
Complementary Pullups and

Pulldown
We want complementary pullup and

pulldown logic, i.e., the pulldown
should be on when the pullup is off
and vice versa.
pullup
pulldown
f (output)
On
Off
Driven 1
Off
On
Driven 0
On
On
Driven X
Off
Off
NC
Since theres plenty of capacitance on

the output node, when the output
becomes disconnected it
remembers its previous voltage -- at
least for a while. The memory is the
load capacitors charge. Leakage
currents will cause eventual decay of
the charge (thats why DRAMs need
to be refreshed!).
CMOS Complements
NAND Gate
Current technology:= 14nm
COST for an older 45nm process:

$3500 per 300mm wafer
300mm round wafer = (150e-3)2 = .07m2
NAND gate = (82)(16)(45e-9)2=2.66e-12m2
2.6e10 NAND gates/wafer (= 100 billion FETS!)
marginal cost of NAND gate: 132n$
CMOS Image Sensor
It is composed of an array of identical pixels. Each pixel has a photodiode (a pn junction photodiode), that converts incident light into photocurrent, and an
addressing transistor that acts as a switch, as shown in Fig. 19a. A Yaddressing or scan register is used to address the sensor line by line, by
activating the in-pixel addressing transistor. An X-addressing or scan register is
used to address the pixels on one line, one after another. Some of the readout
circuits need to convert the photocurrent into electric charge or voltage and to
read it off the array.
S. M. Sze, M. K. Lee, Semiconductor Devices Physics and Technology
MOSFET Transistor Fabrication Steps
Basic CMOS Process Flow

0. Wafer Prep: Laser Scribe, Clean, gettering, 0th
layer Alignment Marks
1. N-Well and P-Well Diffusion
2. Active Area
3. Polysilicon Gate
4. Lightly Doped Drain (LDD)
5. Source-Drain Implant/Diffusion
6. Salicide Formation/Contact Holes
7. Tungsten plugs + First Level Metallization
8. Additional Metal Layers
9. Passivation Layer and Bonding Pads
1. N-Well Diffusion
2. Active Area
3. Poly Gate
4. n+ Source-Drain Diffusion
5. p+ Source-Drain Diffusion
6. Contact Holes
7. First Level Metallization
Cross-Section and Top Down

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KIK614441

Integrated Circuit Technology

The Digital Revolution

ENIAC - The First Electronic

The Digital Revolution

First transistor Bell Labs, 1948

Rabaey Digital Integrated Circuits 2nd

Digital Cellular Market

1996 1997 1998 1999 2000

48M 86M 162M 260M 435M

Rabaey Digital Integrated Circuits 2nd

Rabaey Digital Integrated Circuits 2nd

Sedra/Smith, Microelectronic Circuits 5/e, 2004 Oxford University Press.

Sand to Silicon Wafer

3.1. Intrinsic Semiconductors

Figure 3.1 Two-dimensional representation of the silicon

The process of freeing electrons, creating holes, and filling

silicon at low temps

Figure 3.2: At room temperature, some of the covalent bonds

3.1: Intrinsic Semiconductors

silicon at low temps:

silicon at room temp:

3.2. Doped Semiconductors

3.2. Doped Semiconductors

Figure 3.5: An electric field E established in a bar of silicon

Q: What happens when an electrical field (E) is

Microelectronic Circuits - Fifth Edition, Sedra/Smith

Microelectronic Circuits - Fifth Edition, Sedra/Smith

Microelectronic Circuits - Fifth Edition, Sedra/Smith

Microelectronic Circuits - Fifth Edition, Sedra/Smith

Microelectronic Circuits - Fifth Edition, Sedra/Smith

Microelectronic Circuits - Fifth Edition, Sedra/Smith

Cross-sectional diagram of an nand p-MOSFET

Sedra/Smith, Microelectronic Circuits 5/e, 2004 Oxford University Press.

A CMOS inverter schematic and its

Sedra/Smith, Microelectronic Circuits 5/e, 2004 Oxford University Press.

A set of photomasks for the n-well

Note that each layer requires a separate plate: (a), (d),

Sedra/Smith, Microelectronic Circuits 5/e, 2004 Oxford University Press.

N-Channel MOSFET: Physical

MOSFETs (metal-oxide-semiconductor field-effect transistors) are four-terminal

MIT Open Course Ware 6.004 Computation Structures

N-Channel MOSFET: Electrical

FETs Come in Two Flavors

NFET: n-type source/drain diffusions

PFET: p-type source/drain diffusions

If we follow two rules when constructing CMOS circuits, we can

MIT Open Course Ware 6.004 Computation Structures

CMOS Inverter VTC

MIT Open Course Ware 6.004 Computation Structures

Complementary Pullups and

We want complementary pullup and

Since theres plenty of capacitance on

MIT Open Course Ware 6.004 Computation Structures

MIT Open Course Ware 6.004 Computation Structures

COST for an older 45nm process:

MIT Open Course Ware 6.004 Computation Structures

CMOS Image Sensor

MOSFET Transistor Fabrication Steps