Dept of Electronics and Communication, VVCE

Ovonic Unified Memory [1]
CHAPTER 1
INTRODUCTION
We are now living in a world driven by various electronic equipments. Semiconductors form the
fundamental building blocks of the modern electronic world providing the brains and the memory of
products all around us from washing machines to super computers. Semi conductors consist of array of
transistors with each transistor being a simple switch between electrical 0 and 1.Now often bundled
together in there 10’s of millions they form highly complex, intelligent, reliable semiconductor chips,
which are small and cheap enough for proliferation into products all around us. Identification of new
materials has been, and still is, the primary means in the development of next generation
semiconductors. For the past 30 years, relentless scaling of CMOS IC technology to smaller dimensions
has enabled the continual introduction of complex microelectronics system functions.
However, this trend is not likely to continue indefinitely beyond the semiconductor technology
roadmap. As silicon technology approaches its material limit, and as we reach the end of the roadmap,
an understanding of emerging research devices will be of foremost importance in the identification of
new materials to address the corresponding technological requirements. If scaling is to continue to and
below the 65nm node, alternatives to CMOS designs will be needed to provide a path to device scaling
beyond the end of the roadmap. However, these emerging research technologies will be faced with an
uphill technology challenge. For digital applications, these challenges include exponentially increasing
the leakage current (gate, channel , and source/drain junctions), short channel effects, etc. while for
analogue or RF applications, among the challenges are sustained linearity, low noise figure , power
added efficiency and transistor matching. One of the fundamental approaches to manage this challenge
is using new materials to build the next generation transistors.
Dept of Electronics and Communication, VVCE

1.1 Review of memory basics
Every computer system contains a variety of devices to store the instructions and data required
for its operation. These storage devices plus the algorithms needed to control or manage the stored
information constitute the memory system of the computer. In general, it is desirable that processors
should have immediate and interrupted access to memory, so the time required to transfer information
between the processor and memory should be such that the processor can operate at, close to, its
maximum speed. Unfortunately, memories that operate at speeds comparable to processors speed are
very costly. It is not feasible to employ a single memory using just one type of technology. Instead the
stored information is distributed in complex fashion over a variety of different memory units with very
different physical characteristics
The memory components of a computer can be subdivided into three main groups:
Internal processor memory: This usually comprises of a small set of high speed registers used
as working registers for temporary storage of instructions and data.
Main memory: This is a relatively large fast memory used for program and data storage during
computer operation. It is characterized by the fact that location in the main memory can be directly
accessed by the CPU instruction set. The principal technologies used for main memory are
semiconductor integrated circuits and ferrite cores.
Secondary memory: This is generally much larger in capacity but also much slower than main
memory. It is used for storing system programs and large data files and the likes which are not
continually required by the CPU; it also serves as an overflow memory when the capacity of the main
memory when the capacity of the main memory is exceeded. Information in secondary storage is usually
accessed directly via special programs that first transfer the required information to main memory.
Representative technologies used for secondary memory are magnetic disks and tapes.
The major objective in designing any memory is to provide adequate storage capacity with an
acceptable level of performance at a reasonable cost.

1.2 Memory device characteristics
The computer architect is faced with a bewildering variety of memory devices to use. However;
all memories are based on a relatively small number of physical phenomena and employ relatively few
organizational principles. The characteristics and the underlying physical principles of some specific
representative technologies are also discussed.
Cost: The cost of a memory unit is almost meaningfully measured by the purchase or lease price
to the user of the complete unit. The price should include not only the cost of the information storage
cells themselves but also the cost of the peripheral equipment or access circuitry essential to the
operation of the memory.
Access time and access rate: The performance of a memory device is primarily determined by
the rate at which information can be read from or written into the memory. A convenient performance
measure is the average time required to read a fixed amount of information from the memory. This is
termed read access time. The write access time is defined similarly; it is typically but not always equal
to the read access time. Access time depends on the physical characteristics of the storage medium, and
also on the type of access mechanism used. It is usually calculated from the time a read request is
received by the memory and to the time at which all the requested information has been made available
at the memory output terminals. The access rate of the memory is defined is the inverse of the access
time.
Clearly low cost and high access rate are desirable memory characteristics; unfortunately they
appear to be largely compatible. Memory units with high access rates are generally expensive, while low
cost memory are relatively slow.
Access mode-random and serial: An important property of a memory device is the order or
sequence in which information can be accessed. If locations may be accessed in any order and the access
time is independent of the location being accessed, the memory is termed as a random access memory.
Ferrite core memory and semiconductor memory are usually of this type. Memories where
storage locations can be accessed only in a certain predetermined sequence are called serial access
memories. Magnetic tape units and magnetic bubble memories employ serial access methods. In a
random access memory each storage location can be accessed independently of the other locations.

There is, in effect, a separate access mechanism, or read-write, for every location. In serial memories, on
the other hand, the access mechanism is shared among different locations. It must be assigned to
different locations at different times. This is accomplished by moving the stored information ,the read
write head or both. Many serial access memories operate by continually moving the storage locations
around a closed path or track. A particular location can be accessed only when it passes the fixed read
write head; thus the time required to access a particular location depends on the relative location of the
read/write head when the access request is received. Since every location has its own addressing
mechanism, random access memory tends to be more costly than the serial type. In serial type memory,
however the time required to bring the desired location into correspondence with a read/write head
increases the effective access time, so access tends to be slower than the random access. Thus the access
mode employed contributes significantly to the inverse relation between cost and access time.
Some memory devices such as magnetic disks and drums contain large number of independently
rotating tracks. If each track has its own read-write head, the track may be accessed randomly, although
access within track in serial. In such cases the access mode is sometimes called semi random or direct
access. It should be noted that the access is a function of the memory technology used.
Permanence of storage: The physical processes involved in storage are sometimes inherently
unstable, so that the stored information may be lost over a period of time unless appropriate action is
taken. There are important memory characteristics that can destroy information:
1. Destructive read out
2. Dynamic volatility
3. Volatility
Ferrite core memories have the property that the method of reading the memory alters, i.e.,
destroys, the stored information; this phenomenon is called destructive read out(DRO). Memories in
which reading does not affect the stored data are said to have nondestructive readout (NRDO). In DRO
memories, each read operation must be followed by a write operation followed by a write operation that
restores the original state of the memory. This restoration is usually carried out by automatically using a
buffer register.

Certain memory devices have the property that a stored 1 tends to become a 0, or vice versa, due
to some physical decay processes. Over a period of time, a stored charge tends to leak away, causing a
loss of information unless the stored charge is restored. This process of restoring is called refreshing.
Memories which require periodic refreshing are called dynamic memories, as opposed to static
memories, which require no refreshing. Most memories that using magnetic storage techniques are
static. Refreshing in dynamic memories can be carried out in the same way data is restored in a DRO
memory. The contents of every location are transferred systematically to a buffer register and then
returned, in suitably amplified form, to their original locations. Another physical process that can
destroy the contents of a memory is the failure of power supply. A memory is said to be volatile if the
stored information can be destroyed by a power failure. Most semiconductor memories are volatile,
while most magnetic memories are non volatile.
Cycle time and data transfer rate: The access time of a memory is defined as the time between
the receipt of a read request and the delivery of the requested information to its external output
terminals. In dynamic memories, it may not be possible to initiate another memory access until a restore
or refresh operation has been carried out. This means that the minimum time that must elapse between
the initiations of two different accesses by the memory can be greater than the access time: this rather
loosely defined time is called the cycle time of the memory. It is generally convenient to assume the
cycle time as the time needed to complete any read or write operation in the memory. Hence the
maximum amount of information that can be transferred to or from the memory every second is the
reciprocal of cycle time. This quantity is called the data transfer rate or band width.
1.3 MOORE’S LAW
Moore's Law describes a long-term trend in the history of computing hardware, in which the
number of transistors that can be placed inexpensively on an integrated circuit has doubled
approximately every two years. The law is named for Intel co-founder Gordon . E. Moore, who
introduced it in a 1965 paper. It has since been used in the semi conduct or industry to guide long term
planning and to set targets for research and development. Rather than being a naturally-occurring "law"
that cannot be controlled, however, Moore's Law is effectively a business practice in which the
advancement of transistor counts occurs at a fixed rate. The capabilities of many digital electronic

devices are strongly linked to Moore's law: processing speed, memory capacity, sensors and even the
number and size of pixels in digital cameras. All of these are improving at (roughly) exponential rates as
well. This has dramatically increased the usefulness of digital electronics in nearly every segment of the
world economy. Moore's law precisely describes a driving force of technological and social change in
the late 20th and early 21st centuries.
Looking forward, maintaining the pace of Moore's law scaling is increasingly difficult The
challenging areas include electrical, physical and reliability characteristics of the memory cell. However,
through innovative device design, introduction of new materials and memory error management, we
anticipate that floating gate flash memories are economically viable beyond 45nm to 32 nm. It is
difficult to maintain the Moore’s Law curve using the transistor technology alone. As the process
complexity increase to address the fundamental limits of Physics, Moore’s law can only continue
through innovations, in terms of new memory structures and new materials.
Figure. 1.1 Graphical description of Moore’s law

CHAPTER 2
Ovonic Unified Memory : ANSWER TO

MOORE’S LAW PROBLEM
Most nonvolatile memory devices are Flash memory chips, so-called because of the ability to
write them individually while erasing them in chunks. This type of device is ubiquitous in today’s cell
phones, digital cameras, media cards, etc. But Flash memory suffers from several short comings that
limit its market potential. Primarily, writing data to a Flash memory is too slow for Flash to rival its
DRAM cousins. Secondly, Flash memories can only be reprogrammed a limited number of times,
typically on the order of a million. While this may be enough for certain applications, programming
limitations make Flash memory ill-suited for general computing or intense data manipulation
applications . Perhaps most importantly, the nonvolatile memory industry recognizes that current flash
memory technology will soon face a crisis: along with the rest of computer technology, flash chips must
shrink to remain profitable, but the physics of the barrier oxide used in current flash technology prevents
memory cells from being shrunk much further . Both NOR and NAND flash rely on memory structures
which become increasingly difficult to shrink at smaller lithography’s . As a consequence, a number of
different nonvolatile memory technologies are emerging as potential alternatives to replace Flash, most
prominently used non-volatile memory is Ovonic Unified Memory ( OUM) also called as Phase Change
Memory (PCM).
PCM, however, is based on a physical state change of a chalcogenide material, commonly

referred to as GST. Chalcogenide films have already been proven to have stable characteristics to a 5nm
node. As the PCM memory cell shrinks, the volume of GST material involved in the state change
shrinks resulting in reduced power consumption or higher write performance. This unique feature of
PCM technology supports the promise of scalability beyond that of other memory technologies.
There is a growing need for nonvolatile memory technology for high density stand alone
embedded CMOS application with faster write speed and higher endurance than existing nonvolatile
memories. OUM is a promising technology to meet this need. R.G. Neale , D.L. Nelson, and Gordon . E.
Moore originally reported a phase-change memory array based on chalcogenide materials in 1970.
Improvements in phase-change materials technology subsequently paved the way for development of

commercially available rewriteable CDs and DVD optical memory disks. These advances, coupled with
significant technology scaling and better understanding of the fundamental electrical device operation,
have motivated development of OUM technology at the present day technology node.
OUM is the non volatile memory that utilizes a reversible structural phase change between
amorphous and polycrystalline states in a GeSbTe chalcogenide alloy material. This transition is
accomplished by heating a small volume of the material with a write current pulse and results in a
considerable change in alloy resistivity. The amorphous phase has high resistance and is defined as the
RESET state. The low resistance polycrystalline phase is defined as the SET state.
The two structural states of the chalcogenide alloy, as shown in Figure 2.1, are an amorphous
state and a polycrystalline state. Relative to the amorphous state, the polycrystalline state shows a
dramatic increase in free electron density, similar to a metal . This difference in free electron density
gives rise to a difference in reflectivity and resistivity. In the case of the rewriteable CD and DVD disk
technology, a laser is used to heat the material to change states. Directing a low-power laser at the
material and detecting the difference in reflectivity between the two phases read the state of the memory.
F igure. 2.1
Transmission
Electron Microscope
images of two phases
of GeSbTe alloy
Ovonyx, Inc.,
under license from
Energy Conversion
Devices, Inc., is working with several commercial partners to develop a solid-state nonvolatile memory
technology using the chalcogenide phase change material. To implement a memory the device is
incorporated as a two terminal resistor element with standard CMOS processing. Resistive heating is
used to change the phase of the chalcogenide material. Depending upon the temperature profile applied,
the material is either melted by taking it above the melting temperature (Tm) to form the amorphous
state , or crystallized by holding it at a lower temperature (Tx) for a slightly longer period of time. The

time needed to program either state is 400 ns. Multiple resistance states between these two extremes
have been demonstrated , enabling multi-bit storage per memory cell. However, current development
activities are focused on single-bit applications. Once programmed, the memory state of the cell is
determined by reading its resistance.
2.1 THEORY OF OPERATION
Phase change chalcogenides exhibit a reversible phase change phenomenon when changed from
the amorphous phase to the crystalline phase. In the amorphous phase, the material is highly disordered
—there is an absence of regular order to the crystal-line lattice. In this phase, the material demonstrates
high resistivity and high refractivity. In contrast, in the polycrystalline phase, the material has a regular
crystalline structure and exhibits low refractivity and low resistivity.
Phase Change Memory (PCM) is a term used to describe a class of non-volatile memory devices
that employ a reversible phase change in materials to store information. Matter exist in various phases
such as solid, liquid, gas, condensate and plasma. PCM exploits differences in the electrical resistivity of
a material in different phases. The PCM technology being developed by Intel uses a class of materials
known as chalcogenides (“kal-koj--uh-nyde”). Chalcogenides are alloys that contain an element in the
Oxygen/Sulphur family of the Periodic Table . Numonyx PCM is using an alloy of Germanium ,
Antimony and Tellurium (Ge2Sb2Te5), known more commonly as “GST”. Most companies performing
research and development in PCM today are using GST or closely related alloys.
2.2 PCM ATTRIBUTES AND CAPABILITIES

Phase Change Memory blends the attributes commonly associated with NOR-type flash ,memory
NAND-type flash memory, and RAM or EEPROM. These attributes are summarized in the chart in the
figure 2.2 [Next page]

Figure. 2.2 PCM Attributes: This new class of non-volatile memory brings together the best
attributes of NOR, NAND and RAM.
Bit-alterable : Like RAM or EEPROM, PCM is bit alterable. Flash technology requires a
separate erase step in order to change information. Information stored in bit-alterable memory can be
switched from a one to zero or zero to a one without a separate erase step.
Non-volatile : Just like flash, PCM is nonvolatile. RAM, of course, requires a constant power
supply, such as a battery backup system, to retain information. DRAM technologies also suffer from
susceptibility to so-called “soft errors” or random bit corruption caused by alpha particles or cosmic
radiation. Early testing results conducted by Intel on multimegabit PCM arrays for long term data
retention show excellent results.
Read speed : Like RAM and flash, the technology features fast random access times. This
enables the execution of code directly from the memory, without an intermediate copy to RAM. The
read latency of PCM is comparable to single bit per cell of NOR flash, while the read bandwidth can
match DRAM. In contrast, NAND flash suffers from long random access times on the order of 10s of
microseconds that prevent direct code execution.

Write/erase speed : PCM is capable of achieving write speeds like NAND, but with lower
latency and with no separate erase step required. NOR flash features moderate write speeds but long
erase times. As with RAM, no separate erase step is required with PCM, but the write speed(bandwidth
and latency) does not match the capability of RAM today. The capability of PCM is expected, however,
however, to improve with each process generation as the PCM cell area decreases.
Scaling : Scaling is the fifth area where PCM will offer a difference. Both NOR and NAND rely
on memory structures which are difficult to shrink . This is due to gate thickness remaining constant and
the need for operation voltage of more than 10V while the operation of CMOS logic has been scaled to
1V or even less. This scaling effect is often referred to as Moore’s Law, where memory densities double
with each smaller generation. With PCM, as the memory cell shrinks, the volume of GST material
shrinks as well, providing a truly scalable solution.
2.3 THE SOLUTION
Phase Change Memory is a promising memory technology that has recently experienced a
resurgence of interest. PCM employs a reversible phase change phenomenon to store information
through a resistance change in different phases of a material. PCM offers a combination of some of the
best attributes of NOR flash, AND flash, EEPROM and RAM in a single memory device. These
capabilities uniquely combined with the potential for lower memory subsystem costs could potentially
create new applications and memory architectures in a wide range of systems.

CHAPTER 3
OVONIC UNIFIED MEMORY (OUM)
3.1 EVOLUTION
The use of phase-change chalcogenide alloy films to store data electrically and optically was first
reported in 1968 and in 1972, respectively. Early phase-change memory devices used tellurium-rich,
multi-component chalcogenide alloys with a typical composition ofTe81Ge15Sb2S2. Both the optical
and electrical memory devices were programmed by application of an energy pulse of appropriate
magnitude and duration. A short pulse of energy was used to melt the material, which was then allowed
to cool quickly enough to “freeze in” the glassy, structurally disordered state. To reverse the process, a
somewhat lower- amplitude, longer-duration pulse was used to heat a previously vitrified region of the
alloy to a temperature below the melting point, at which crystallization could occur rapidly . Differences
in electrical resistivity and the optical constants between the amorphous and polycrystalline phases were
used to store data .During the 1970s and 1980s, significant research efforts by many industrial and
academic groups were focused on understanding the fundamental properties of chalcogenide alloy
amorphous semiconductors. Prototype optical memory disks and electronic memory device arrays also
were announced, beginning in the early 1970s. Rapidly crystallizing chalcogenide alloys were later
reported by several optical memory research groups. These new material compositions, derived from the
Ge-Te-Sb ternary system, did not phase segregate upon crystallization like the earlier Te-rich alloys, but
instead exhibited congruent crystallization with no large-scale atomic motion .In the 1990s, researchers
at Energy Conversion Devices Inc. and Ovonyx Inc. developed new, thermally optimized phase-change
memory device structures that exploited rapidly crystallizing chalcogenide alloy materials to achieve
increased programming speed and reduced programming current. These devices could be programmed
in 20 ns—about six orders of magnitude faster than the early phase-change memory cells, and their
much lower programming current requirements permitted the design of memory arrays using memory
bit access devices(transistors or diodes) fabricated at minimum litho-graphic dimensions. Ovonyx is
now commercializing its phase-change memory technology called Ovonic Unified Memory(OUM)

through a number of license agreements and joint development programs with semiconductor device
manufacturers.
In February 2000, Intel and Ovonyx announced a collaboration and licensing agreement that
spawned the modern age of research & development in PCM. In December of 2000, STMicroelectronics
(“ST”) and Ovonyx also began a collaboration. By 2003, the three companies had joined forces to
accelerate progress on the technology by avoiding duplication in basic, pre-competitive R&D and
through expanding the research scope. In 2005, ST and Intel agreed to co-develop a 90 nm PCM
technology. In 2006, BAE Systems offered a radiation-hardened 4 Mb Chalcogenide RAM based on it
is claimed, cost advantages over conventional solid-state memories such as DRAM or Flash due to its
thin-film nature, very small active storage media, and simple device structure.
Figure. 3.1 BAE Systems' elegant radiation-hardened 4 Mb C-RAM
Numonyx is already marketing limited quantities of phase-change memory based on 90-nm cells
and hopes to have samples of a 45-nm device available this year. In September 2008, Samsung
announced it had begun selling phase-change random access memory, or PRAM, with 512-megabit
capacity for mobile devices. Samsung said its device can erase 64000 words of data in 80 milliseconds,
more than 10 times as fast as flash. The company says it expects PRAM to become one of its core
memory products. Other companies, including IBM and Philips, are also developing phase-change
memory.
Numonyx expects to commercialise phase-change memory, and by the middle of the next
decade, hopes to make it increase its storage capacity to render it competitive with flash as a solid-state
drive replacement.

3.2 CHALCOGENIDES
Figure. 3.2 The highlighted elements form the basis of Chalcogenides
The crystalline and amorphous states of chalcogenide have dramatically different electrical
resistivity, and this forms the basis by which data are stored. The amorphous ,high resistance state is
used to represent a binary 0, and the crystalline, low resistance state represents a 1. Chalcogenide is the
same material used in re-writable optical media(such as CD-RW and DVD-RW). In those instances, the
material's optical properties are manipulated , rather than its electrical resistivity , as chalcogenide's
refractive index also changes with the state of the material. The term “chalcogen” refers to the Group VI
elements of the periodic table.“Chalcogenide” refers to alloys containing at least one Group VI element
such as the alloy of germanium, antimony, and tellurium discussed here. Energy Conversion Devices,
Inc. has used this particular alloy to develop a phase-change memory technology used in commercially
available re-writeable CD and DVD disks. This phase-change technology uses a thermally activated,

rapid, reversible change in the structure of the alloy to store data. Since the binary information is
represented by two different phases of material it is inherently non-volatile ,requiring no energy to keep
the material in either of its two stable structural states .Used in a binary mode, the two structural states
of the chalcogenide alloy, are an amorphous state (no long-range order of atoms) and a polycrystalline
state(composed of many crystals, each having atoms placed in a repetitive order). Relative to the
amorphous state, the polycrystalline state shows a dramatic increase in free electron density (similar to a
metal). This difference in free electron density gives rise to a difference in reflectivity and, more
importantly, resistivity. In the case of the rewriteable CD and DVD disk technology, this difference in
reflectivity is used to read the state of each memory bit by directing a low-power laser at the material
and detecting the amount of light reflected.
3.3 Storage Mechanism: The Amorphous–Crystalline Structural

Phase Change
Glassy materials are produced by rapidly super cooling a liquid below its melting point to a
temperature at which the atomic motion necessary for crystallization cannot readily occur. Chalcogenide
alloys - materials containing one or more elements from Group VI of the periodic table—are typically
good glass formers, in large part because the Group VI elements form pre-dominantly two fold-
coordinated covalent chemical bonds that can produce linear, tangled, polymer like clusters in the melt.
This increases the viscosity of the liquid, inhibiting the atomic motion necessary for crystallization.
Many amorphous chalcogenide alloys have been reported in the literature. The Ge2Sb2Te5 (GST 225)
chalcogenide alloy currently used in OUM memory devices melts at approximately 610 C۫ and has a
glass-transition temperature of 350C۫. In order to crystallize an amorphous region of GST 225, the
material must be heated to a temperature some what below the melting point and held at this temperature
for a time sufficient to allow the crystallization to occur. The compositional dependence of
crystallization kinetics in the GeSbTe ternary system has been extensively studied and reported in the
literature. OUM cells based on GST 225 that can be programmed (crystallized) to the “SET” state in <20
ns have been reported.

Figure 3.3 Schematic temperature–time relationship during programming
In a phase-change rewriteable memory device. Tm and Tx are the amorphization and

crystallization temperatures ,respectively. The SET and RESET states of the memory correspond to a
stored binary 1 or binary 0.
The basic device operation can be explained from the temperature versus time graph in figure
3.3. During the amorphizing reset pulse, the temperature of the programmed volume of phase change
material exceeds the melting point which eliminates the polycrystalline order in the material. When the
reset pulse is terminated the device quenches to freeze in the disordered structural state. The quench
time is determined by the thermal environment of the device and the fall time of the pulse. The
crystallizing set pulse is of lower amplitude and of sufficient duration to maintain the device temperature
in the rapid crystallization range for a time sufficient for crystal growth.
• For R/W CD’s and DVD’s heat is supplied by use of a laser.
• For integrated circuits heat is supplied by resistors.

3.4 ELECTRONIC PROPERTIES OF CRYSTALLINE AND

AMORPHOUS GST ALLOYS
Two special electronic properties of chalcogenide amorphous semiconductor alloys are required
for the operation of OUM memory—the strong dependence of electrical resistivity on the structural state
of the material and the high-field threshold switching phenomenon. Polycrystalline GST alloy has a
resistivity of ~25 mΩcm, while resistivity in the vitreous state is three orders of magnitude higher—
sufficient to enable good memory read capability. Both structural states of the alloy are semiconductors
with comparable energy band gaps. The band gap Eg is 0.7 eV in the amorphous state and 0.5eV in the
poly-crystalline state. The conductivity activation energy Ea is ~0.3 eV for the amorphous state and 0.02
eV for the polycrystalline state. In addition, the amorphous phase exhibits a very low, trap-limited hole
mobility of ~2×10^-5cm2/Vs, while the polycrystalline phase shows band-type mobility of ~10 cm2/ V
s. These large differences come about because of disorder-induced localized electronic states as
originally described by Mott and by Cohen, Fritzsche, and Ovshinsky (CFO) and later by Kastner,
Adler, and Fritzsche. When chalcogenide alloy semiconductors are amorphized, electronic energy levels
originating in the valence and conduction bands are pulled into what was originally the empty energy
band gap of the crystalline material. As described by Mott–CFO, these new gap states are localized
spatially and do not extend throughout the material. Consequently, carriers move through the amorphous
material either by hopping among the localized states or by being successively thermally excited to
spatially extended band states and then being trapped into localized states. This gives rise to a mobility
gap—a range of energy between the valence and conduction bands in which carriers have small, trap-
limited mobility. The later work by Kastner, Adler, and Fritzsche explained the observation that Ea≈
Eg/2 in terms of a large density of special negatively and positively charged traps that also result from
structural disorder in amorphous chalcogenide alloys. Kastner et al argued that charged traps (valence
alternation pairs)act like compensating dopant levels in a conventional crystalline semiconductor ,
effectively forcing the Fermi level to lie near the mid gap between the energy levels of the two types of
traps .In the polycrystalline state, crystal vacancies are proposed to give rise to acceptor-like states that
move the Fermi level close to the valence-band edge. This Fermi level position , plus the loss of the
disorder produced trapping states, gives rise to the nearly degenerate p-type high conductivity of the
polycrystalline state. Thus, the phase-change memory cell uses a reversible change in long-range atomic

order (the amorphous-to-crystalline phase change) to modulate both the Fermi level position in the
chalcogenide alloy and the carrier mobility to change the cell’s resistance.
Figure 3.4 Corresponding Electron Diffraction patterns
The Electron diffraction pattern reveals the following insights about both phases:
Table. 3.1 Difference between amorphous and polycrystalline phase
3.5 THRESHOLD SWITCHING
Threshold switching, also first reported by Ovshinsky in 1968, is the other property of
chalcogenide alloys exploited in phase-change memory, and it is also a consequence of disorder-induced
localized states. In the amorphous phase, the chalcogenide alloy material has a high electrical resistance
at low electric fields. With increasing voltage, conductivity is initially ohmic , but it begins to grow
exponentially when the field exceeds 10^5 V/cm. When a particular threshold voltage, Vth, is exceeded,
the material switches rapidly into a highly conductive “dynamic ON state.” The dynamic ON state is
maintained so long as a sufficient holding current is passing through the device. This transient high-
conductivity state is electronic in origin and does not involve a structural transformation from the
amorphous to the low-resistance crystalline state, since it also has been observed in molten chalcogenide
semiconductors .Threshold switching has been explained in terms of electric-field-induced filling of the

charged valence alternation pair traps, which alters the recombination kinetics. In the phase-change
memory, threshold switching provides a means to deliver the required programming current needed to
program a bit in the high-resistance state at low voltage. From a high-resistance (“RESET”) state, an
OUM bit is programmed into a low resistance(“SET”) state by applying programming voltage in excess
of Vth, allowing the bit to enter the dynamic ON state. Current then is allowed to flow for a length of
time sufficient to ensure crystallization. The device can then be programmed to the RESET state by
applying a short, somewhat larger current pulse to a bit in the polycrystalline state. The reset pulse only
needs to be of sufficient magnitude and duration to melt the programmed volume of chalcogenide alloy
and to have a fast enough falling edge to permit the molten programmed volume of material to cool fast
enough to vitrify. The duration of the reset pulse can be short, since the material in the programmed
volume can be heated to the melting point in a few nanoseconds.
Figur. 3.5 Basic Threshold crossover mechanism
Figure. 3.6 Application of threshold crossing in OUM memory device

CHAPTER 4
OUM MEMORY STRUCTURE

In PCM, we are exploiting the difference in resistivity between the two phases of the material.
This phase change is induced in the material through intense localized Joule heating caused by current
injection. The end phase of the material is modulated by the magnitude of the injected current, the
applied voltage, and the time of the operation .Figure 4.1 shows a block diagram of a basic PCM storage
element. As shown, a layer of chalcogenide is sandwiched between a top electrode and a bottom
electrode. A resistive heating element extends from the bottom electrode and contacts a layer of the
chalcogenide material. Current injected into the junction of the chalcogenide and the heater induces the
phase change through Joule heating.
Figure . 4.1 Block diagram of a OUM cell
 The OUM cell is programmed by application of a current pulse at a voltage above the switching
threshold.
 The programming pulse drives the memory cell into a high or low resistance state, depending on
current magnitude.
 Information stored in the cell is read out by measurement of the cell’s resistance.
 OUM devices are programmed by electrically altering the structure (amorphous or crystalline) of
a small volume of chalcogenide alloy.

 Thermal insulators are also attached to the memory structure in order to avoid data lose due to
destruction of material at high temperature .
 To read data a low voltage is applied current determined by resistance of memory element.
Amorphous state = High resistance = Low current
Crystalline state = Low resistance = High current
 To write data into the cell ,the chalcogenide is heated past the melting point and then rapidly
cooled to make it amorphous. To make it crystalline, it is heated to just below its melting point
and held there for approximately 50ns, giving the atoms time to position themselves in their
crystal locations.
4.1 Technology and performance
Figure. 4.2 Relationship between resistance and Pulse Width
The figure 4.2 above shows device resistance versus write pulse width. The reset resistance
saturates when the pulse width is long enough to achieve melting of the phase change material. The set
pulse adequately crystallizes the bit in 50 ns with a RESET/SET resistance ratio of greater than 100.

4.2 R-I Characteristics
Figure. 4.3 R-I Characteristics

The above figure 4.3 shows the device read resistance resulting from application of the
programming current pulse amplitude. Starting in the set condition, moving from left to right, the device
continues to remain in SET state as the amplitude is increased. Further increase in the pulse amplitude
begins to reset the device with still further increase resetting the device to a standard amorphous
resistance. Beginning again with a device initially in the RESET state, low amplitude pulses at voltages
less than Vth do not set the device. Once Vth is surpassed, the device switches to the dynamic on state
and programmed resistance is dramatically reduced as crystallization of the material is achieved. Further
increase in programming current further crystallizes the material, which drops the resistance to a
minimum value. As the programming pulse amplitude is increased further, resetting again is exhibited as
in the case above. Devices can be safely reset above the saturation point for margin. Importantly, the
right side of the curve exhibits direct overwrite capability, where a particular resistance value can be
obtained from a programming pulse, irrespective of the prior state of the material. The slope of the right
side of the curve is the device design parameter and can be adjusted to enable a multi- state memory cell.

4.3 RETENTION AND ENDURANCE
The retention offered by OUM is excellent and can be seen in Figure 4.4 below showing very
small deviation even after 10^12 cycles. This extremely stable nature of its operation makes it the best
choice for a long term memory solution.
The demonstrated Endurance of OUM is 10^13, whereas that of conventional FLASH memory is
of the order of 10^6. Excellent data retention has been reported on large arrays .

Figure. 4.4 Resistance variation wrt. Number of cycles
Device endurance has been demonstrated beyond 1E12set/reset cycles. An example is shown in
Fig 4.4 with 30 ns reset and 50 ns set pulses. A RESET/SET resistance ratio > 60 was observed over the
entire range. Cycling out to1E13 set/reset cycles has been evaluated on some devices . Failure
mechanisms at this level of cycling have been identified, and efforts are underway to extend the
endurance
Cycling performance of the SET and RESET state of the memory element indicates that no
degradation in dynamic range was observed up to 1.25E12cycles, and cycling was stopped.
Figure. 4.5 Temperature dependence of OUM

The Figure 4.5 above shows the Temperature dependence of programming characteristics. The
high resistance, “Reset,” state shows activated, semiconductor like behavior while the low resistance,
“Set,” state shows essentially temperature independent metallic behavior.
4.4 TECHNOLOGY CAPABILITIES

Direct write capability (no erase before write) as well as byte function (no block flash erase)
makes it RAM like, easing significantly system implementation
 For flash, changing a byte involves saving the current data, erasig a whole block
(>100 mSec) and writing back old data + new byte (total ~1 sec)
 For PCM, changing a byte involves writing the new data: (total < 100 nSec, c
an be less than 50 nSec with new alloy)
 Demonstrated endurance of 10^13 cycles
With read current > 10 μA, read speed is expected to be comparable to NOR and DRAM
Stability of the RESET state against unintended thermal crystallization has been investigated in
individual cells and in array devices . The data show that crystallization in intrinsic bits follows an
Arrhenius behavior at elevated temperature with an activation energy of 2.6 eV allowing a data retention
capability to 10 years at 110 degrees C.
The following figure 4.6 below shows the relationship between the period of operation and the
percentage probability of device failure (on Y Axis) accrued over time (on X Axis). The point worth
having a glance is that the unit of time is in year, and as it is visible from graph, the device has an
excellent life as failure occurrence is negligible.
Figure. 4.6 Graph shows the predicted failure %

Radiation hardness of phase-change memory is excellent. Measurements of total dose radiation

response indicate that exposure to > 1 Mrad (Si) of Co-60 gamma radiation had no detectable impact on
stored data or device functionality.
CHAPTER 5
INTEGRATION WITH CMOS
Under contract to the Space Vehicles Directorate of the Air Force Research Laboratory (AFRL),
BAE SYSTEMS and Ovonyx began the current program in August of 2001 to integrate the
chalcogenide-based memory element into a radiation-hardened CMOS process. The initial goal of this
effort was to develop the processes necessary to connect the memory element to CMOS transistors and
metal wiring, without degrading the operation of either the memory elements or the transistors. It also
was desired to maximize the potential memory density of the technology by placing the memory
element directly above the transistors and below the first level of metal as shown in a simplified diagram
in Figure 5.1

Figure 5.1 An OUM cell integrated with a CMOS transistor

To accomplish this process integration task, it was necessary to design a test chip with
appropriate structures. This vehicle was called the Access Device Test Chip (ADTC) since each memory
cell requires an access device (transistor) in addition to the chalcogenide memory element. Such a
memory cell, comprised of one access transistor and one chalcogenide resistor, is here in referred to as a
1T1R cell. The ADTC included 272 macros, each with2 columns of 10 probe pads. Of these, 163
macros were borrowed from existing BAE SYSTEMS’ test structures and used to verify normal
transistor operation. There were 109 new macros designed to address the memory element features.
These included sheet resistance and contact resistance measurement structures, discrete memory
elements of various sizes and configurations, and two 16-bit 1T1R memory arrays .Short loop (partial
flow) experiments were processed using subsets of the full ADTC mask set. These experiments were
used to optimize the process steps used to connect the bottom electrode of the memory element to
underlying tungsten studs and to connect an additional tungsten stud level between Metal 1 and the top
electrode of the memory element. A full flow experiment was then processed to demonstrate integrated
transistors and memory elements.
Figure 5.2 I-V Characteristics

Figure 5.2 shows the I-V characteristic for a 1T1R memory cell successfully fabricated using the
ADTC vehicle. The voltage is applied to one of the two terminals of the chalcogenide resistor,

and the access transistor (biased on) is between the other resistor terminal and ground. The high
resistance amorphous material shows very little current below a threshold voltage (VT) of 1.2V.In this
same region the low resistance polycrystalline material shows a significantly higher current. The state of
the memory cell is read using the difference in I-V characteristics below VT. Above VT, both materials
display identical I-V characteristics, with a dynamic resistance (RDYNAMIC) of ˜1k. In itself, this
transition to a low resistance electrical state does not change the structural phase of the material.
However, it does allow for heating of the material to program it to the low resistance state (1) or the high
resistance state (0). Extrapolation of the portion of the I-V curve that is above VT to the X-axis yields a
point referred to as a holding voltage (VH).The applied voltage must be reduced below VH to exit the
programming mode.
Figure. 5.3 Relationship between Resistance and Current

Figure 5.3 shows the operation of a 1T1R memory, again with the access transistor biased on.
The plotted resistance values were measured below VT, while the current used to program these
resistances were measured above VT. Similar to the previously demonstrated stand-alone memory
elements, these devices require approximately 0.6 mA to set to the low resistance state(RSET) and 1.2
mA to reset to the high resistance state (RRESET). The circuit was verified to be electrically open with
the access transistor biased off.

Figure 5.4 Relationship between Drain Current and Gate Voltage of 1T1R Cell
Figure 5.4 shows the total dose (X-ray) response of N-channel transistors processed through the
chalcogenide memory flow. The small threshold voltage shift is typical of BAE SYSTEMS’ standard
radiation-hardened transistor processing. All other measured parameters (drive current, threshold
voltage, electrical channel length , contact resistance, etc.) were also typical of product manufactured
without the memory element.
CHAPTER 6
DISTINCTIVE ADVANTAGES, LIMITATIONS,

RISK FACTORS & APPLICATIONS
6.1 ADVANTAGES
Cost/Bit reduction
 Small active storage medium
 Small cell size – small die size
 Simple manufacturing process – low step count
 Simple planar device structure
 Low voltage – single supply
 Reduced assembly and test costs

Near Ideal Memory Quality

 Non-volatile
 High endurance – >1013 demonstrated
 Long data retention – >10 years
 Static – no refresh overhead penalty
 Random accessible – read and write
 Direct overwrite capability
 Low standby current (<1μA)
 Large dynamic range for data (>40X)
 Actively driven digit-line during read
 Good array efficiency expected
 No charge loss failure mechanisms
 High switching speed
 Non-destructive read
Highly Scalable
 Performance improves with scaling
 Only lithography limited
 Low voltage operation
 Multi-state demonstrated
 3D multi-layer potential with thin films
 Small storage active medium
 Higher Density, Ease of Integration.
RADIATION IMMUNITY
One very important advantage offered by OUM over other conventional memory types, is
irradiation immunity .FLASH memory stores the bits in the form of connections between the floating
gate and the control gate. FLASH which is otherwise nonvolatile, can loose its data in the presence of
radiations which are very common considering Medical and Space applications. The memory element is

exposed to ionizing radiation which have the ability to eject an electron thereby causing disruption of the
links which form the basis of memory storage in the flash memory.OUM however offers the distinctive
advantage over all other memory types owing to its Radiation Immunity characteristics. As the bits are
not stored in form of charge or links but in form of two definitive phases, Crystalline and amorphous,
which are seldom affected by the presence of High energy radiations. Hence OUM can be safely
employed in all Medical and Space application.
6.2 RISK FACTORS

 Reset current < min W switch current
 Standard CMOS process integration
 Alloy optimization for robust high temp operation and speed
 Cycle life endurance consistency
 Endurance testing to 1014–DRAM
 Defect density and failure mechanisms
6.3 TECHNOLOGY CHALLENGES

 Reduction of programming current for lower voltage and lower power operation.
 Increased set/reset resistance and decreased read current/set current margin with
 scaling → impact on read performance/margin.
 Management of proximity heating with declining cell space → disturb risk.
6.4 Market Applications of Phase Change Memory (PCM)

Target products for PCM technology address both stand alone memory and embedded memory.
Product applications include:
 NOR Flash Memory - PCM is a direct replacement for this very popular type of nonvolatile
memory (NVM) used primarily for code storage. PCM also offers the performance capability of
execute In Place (XIP) operation as NOR flash for improved system level performance, but with

improved cycle life, reduced programming time, lower power, smaller cell size, reduced
manufacturing cost and enhanced scalability.
 Unified Memory - PCM, with its unique NVM performance attributes, has the ability to create a
new class of NVM that combines the capability of other dissimilar memory technologies
(volatile and non-volatile) into a single solution. In particular, PCM’s capability of direct bit
overwrite (no erase required) and high speed R/W performance coupled with high cycle life
endurance, allows it to replace a previous dual chip solution of DRAM and Flash with a single
unified memory solution for lower cost, reduced power and smaller form factor.
 DRAM (Dynamic Random Access Memory) - PCM can displace a significant amount of DRAM
in both mobile and PC/server applications. PCM today already offers a cell size smaller than
DRAM and with PCM’s inherent enhanced scalability over DRAM, the cost advantage of PCM
will increase with time. As more volatile DRAM is displaced by non-volatile PCM, significant
power savings will be realized, providing extended battery life in mobile applications and
significantly reduced power consumption in PC and server applications. Initially, PCM will not
be targeted as a direct replacement for all DRAM, but rather to displace a large percentage of
DRAM in applications that don’t require the infinite DRAM cycle endurance and can benefit the
most from the dramatically reduced power consumption of PCM.
 NAND Flash Memory is the largest growth area of NVM due primarily to its very low cost and
continued steep declining cost curve. However, as NAND Flash scales, the random R/W speed
performance and cycle endurance continues to degrade, accentuating the need and size of a
buffer memory where PCM would be an ideal memory solution. Longer term, when/if NAND
Flash cost reduction slows down due to scaling limits (such as reaching a finite number of
electrons), there have been innovative proposals to incorporate PCM in multi-layer cross point
architectures to be competitive, even in the lowest cost NVM applications.
 Embedded Memory in microprocessors, microcontrollers and System-on-a-Chip (SOC)
applications, PCM’s competitive advantage in this very important and growing segment of the
semiconductor device market comes from its scalability, small cell size, and ease of integration
into existing process flows for logic devices. PCM’s capability to be embedded in these devices
enables the high level of integration of memory and logic functions that will be necessary for
both high-performance computing and for a wide range of low-cost embedded microcontroller,
microprocessor, and SOC applications in consumer and automotive electronic devices.

 Field Programmable Logic Devices (FPLDs) and Field Programmable Gate Arrays (FPGAs)
are an important segment of the MOS logic market. These devices are widely used in networking
infrastructure, video games, computer chipsets, etc. The ability to use PCM technology will
permit the manufacture of nonvolatile, high cycle-life reprogrammable devices. This will provide
a key competitive advantage over mask-programmable, one-time programmable, volatile SRAM
reprogrammable, and Flash reprogrammable solutions.
 Radiation-hard applications are a natural fit for PCM due to the atomic structural nature of
memory data storage. Unlike charge-storage based memory technologies, PCM stores the phase
of a material, which is effectively immune to radiation. Thus, PCM is an ideal candidate for
military, space, and other radiation sensitive applications.Beyond this initial non-volatile
memory solution, there are a number of other opportunities presented by the integration of
phase-change material with CMOS technologies. These can be categorized as generally digital or
analog in nature .
Digital Applications.
A universal memory solution that meets requirements for both volatile and non-volatile
applications would greatly simplify the system engineering task for both commercial and military space
applications. The primary focus for enhancements of a chalcogenide RAM to achieve universal memory
goals would be an increase in memory write endurance to >1e14 writes and a reduction in the speed of
the device to <50 ns (write) and <20ns (read). This would be accomplished with a combination of design
and process improvements. Another application for chalcogenide within the digital electronics product
set is a reconfigurable logic device such as Field Programmable Gate Array (FPGA).Reconfigurable
systems utilize SRAM-based or fused-based circuits. Chalcogenide memory cells appear to be ideal
candidates to replace SRAM cells, providing the advantages of both instant reconfiguration and non-
volatility. Embedded chalcogenide provides a third digital application. Memory cells or FPGA elements
may be inserted into processors, Application Specific Integrated Circuits(ASICs), or System-on-a-chip
(SOC) applications. Chalcogenide is suited to be the first technology to provide both an embedded non-
volatile memory and are configurable component mixed with high performance elements that can adapt

to the latest interface or algorithms .This would provide an important option for space systems when
design and interface decisions must remain flexible over the lifetime of the systems.
Analog Applications.
Current research is focused on the highest and lowest resistance states of the chalcogenide
material. However ,devices can be programmed to intermediate resistance states . this provides a unique
opportunity for analog or linear applications of the technology An area of analog research tied to the
memory program is the application of the multi-state capability of chalcogenide. By incrementally
stepping the voltage used to program the element, each memory cell can represent multiple bits. For
instance, four steps would be needed to represent two bits. This unique feature could be applied to
creating denser memories without reduction in feature size. Because the technology is based on
resistance change, an obvious application would be programmable trim resistors .Numerous linear and
power devices are optimized for performance using resistance trimming. Not only would embedded
chalcogenide resistors simplify production and increase reliability, but also would permit re-trimming
(and re optimization)later in the operational life of the device. Finally, there is an opportunity to explore
whole new methods of storing and processing analog signals. The direct-digital-to-analog applications .
(analog memory, analog-to-digital converters) provides perhaps the highest payoff area of research for
next-generation space surveillance systems.
CONCLUSION
Phase Change Memory is a promising memory technology that has recently experienced a
resurgence of interest. PCM employs a reversible phase change phenomenon to store information
through a resistance change in different phases of a material.
Unlike conventional flash memory Ovonic unified memory can be randomly addressed. OUM
cell can be written 10trillion times when compared with conventional flash memory. The computers
using OUM would not be subjected to critical data loss when the system hangs up or when power is
abruptly lost as are present day computers using DRAM and SRAM. OUM requires fewer steps in an IC
manufacturing process resulting in reduced cycle times , fewer defects, and greater manufacturing
flexibility. These properties essentially make OUM an ideal commercial memory.
PCM offers a combination of some of the best attributes of NOR flash, NAND flash, EEPROM
and RAM in a single memory device. These capabilities uniquely combined with the potential for lower

memory subsystem costs could potentially create new applications and memory architectures in a wide
range of systems
Current commercial technologies do not satisfy the density, radiation tolerance, or endurance
requirements for space applications. OUM technology offers great potential for low power operation and
radiation tolerance, which assures its compatibility in space applications. OUM has direct applications in
all products presently using solid state memory, including computers, cell phones , graphics-3D
rendering, GPS, video conferencing, multimedia, Internet networking and interfacing, digital TV,
telecom , PDA, digital voice recorders, modems, DVD, networking (ATM),Ethernet, and pagers. OUM
offers a way to realize full system-on-chip capability through integrating unified memory, linear, and
logic on the same silicon chip.
Phase Change Memory (PCM) technology directly addresses the needs of today’s electronic
systems thus becoming a leading edge in memory technology.
REFERENCES
 S.R. Ovshinsky, S.J. Hudgens, W. Czubatyj, D.A. Strand, and G.C. Wicker,
“Electrically erasable phase change memory,” U.S. Patent No. 5,166,758 (November 24, 1992).
 J. Maimon, E. Spall, R. Quinn, S Schnur, “Chalcogenide-Based Non-Volatile

Memory Technology” NVMTS (Nonvolatile Memory Technology Symposium,2000).
 J. Maimon, K. Hunt, J. Rogers, L. Burcin, and K. Knowles, Proc. NVTMS Conf.
(2002).
 www.ovonyx.com ; Tyler A. Lowrey, Stephen J. Hudgens, Wally Czubatyj,
Charles H. Dennison, Sergey A. Kostylev, and Guy Wicker “Characteristics of
OUM Phase Change Materials and Devices for High Density Nonvolatile
Commodity and Embedded Memory Applications” Mat. Res. Soc. Symp. Proc.

Vol.803 2004.
 J. Maimon, E. Spall, R. Quinn, S Schnur, “Chalcogenide-Based Non-Volatile

Memory Technology” NVMTS (Nonvolatile Memory Technology Symposium,
2000).
 Pirovano, A. Redaelli, A. Pellizzer, F. Ottogalli, F. Tosi, M. Ielmini, D. Lacaita,

A.L. Bez, R. Reliability study of phase-change nonvolatile memories. IEEE
Transactions on Device and Materials Reliability. Sept. 2004,
 IEEE SPECTRUM, March 2003
 www.wikipedia.org [http://en.wikipedia.org/wiki/Ovonic_Unified_Memory]
 Numonyx Phase Change Memory: A new memory to enable new memory usage models.

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Ovonic Unified Memory [1]