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    Assignment No 1

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    Ehtasham Ul Hassan
    This document contains an assignment from the NFC Institute of Engineering & Technology for their EE-401 Microprocessor Based Systems course. The assignment contains 31 questions about microprocessor architecture, memory addressing modes, and instruction types for students to answer. It provides details on submitting the answers including being handwritten or typed, submitting in groups, and the due date of February 24th, 2016 between 12-1pm. The teacher is listed as Engineer Zeeshan Raza.

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    Assignment No 1

    Uploaded by

    Ehtasham Ul Hassan
    416 views2 pages
    This document contains an assignment from the NFC Institute of Engineering & Technology for their EE-401 Microprocessor Based Systems course. The assignment contains 31 questions about microprocessor architecture, memory addressing modes, and instruction types for students to answer. It provides details on submitting the answers including being handwritten or typed, submitting in groups, and the due date of February 24th, 2016 between 12-1pm. The teacher is listed as Engineer Zeeshan Raza.

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    This document contains an assignment from the NFC Institute of Engineering & Technology for their EE-401 Microprocessor Based Systems course. The assignment contains 31 questions about microprocessor architecture, memory addressing modes, and instruction types for students to answer. It provides details on submitting the answers including being handwritten or typed, submitting in groups, and the due date of February 24th, 2016 between 12-1pm. The teacher is listed as Engineer Zeeshan Raza.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    416 views2 pages

    Assignment No 1

    Uploaded by

    Ehtasham Ul Hassan
    This document contains an assignment from the NFC Institute of Engineering & Technology for their EE-401 Microprocessor Based Systems course. The assignment contains 31 questions about microprocessor architecture, memory addressing modes, and instruction types for students to answer. It provides details on submitting the answers including being handwritten or typed, submitting in groups, and the due date of February 24th, 2016 between 12-1pm. The teacher is listed as Engineer Zeeshan Raza.

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    © All Rights Reserved
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    NFC Institute of Engineering & Technology, Multan

    Department of Electrical Engineering


    Subject : Microprocessor Based System

    2K13-EE

    ASSIGNMENT NO 1

    EE-401

    Date: 18-2-16

    Study logically the answers of following questions


    1.
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    24.

    25.
    26.

    27.

    What are program-visible registers?


    Which register holds a count for some instructions?
    The carry flag bit is set by what arithmetic operations?
    Will an overflow occur if a signed FFH is added to a signed 01H?
    A number that contains 3 one bits is said to have parity?
    Which flag bit controls the INTR pin on the microprocessor?
    Which microprocessors contain an FS segment register?
    In the real mode, show the starting and ending addresses of each segment located by the following
    Segment register values (a) EOOOH (b) ABOOH
    Find the memory address of the next instruction executed by the microprocessor, when operated
    in the real mode, for the following CS:IP combinations CS = l000H and IP = 2000H
    Which register or registers are used as an offset address for string instruction destinations in
    the 80486 microprocessor?
    Determine the memory location addressed by the following real mode 80386 register combinations:
    DS = 2000H and EAX = 00003000H
    Protected mode memory addressing allows access to which area of the memory in the Pentium
    microprocessor?
    What is the purpose of the segment register in protected mode memory addressing?
    For an 80286 descriptor that contains a base address of AOOOOOH and a limit of 1000H, what
    starting and ending locations are addressed by this descriptor?
    For a Pentium descriptor that contains a base address of 00280000H, a limit of 000 I OH, and
    G = 1, what starting and ending locations are addressed by this descriptor?
    If DS = 0105H, in a protected mode system, which entry, table, and requested privilege level
    are selected?
    Which register locates the global descriptor table?
    . How is the local descriptor table addressed in the memory system?
    If the microprocessor sends linear address 00200000H to the paging mechanism, which
    paging directory entry is accessed, and which page table entry is accessed'?
    List the 16-bit registers used for register addressing
    What is wrong with the MOV BL,CX instruction?
    Select an instruction for each of the following tasks:
    (a) move a 12H into AL
    (b) nove a 1200A2H into EBX
    What assembly language directive indicates the start of the CODE segment?
    Suppose that DS = 0200H, BX = 0300H, and DI = 400H. Determine the memory address accessed
    by each of the following instructions, assuming real mode operation:
    (a) MOV AL,[1234H]
    (b) MOV EAX.[BX]
    What is wrong with a MOV [BX].[DI] instruction?
    Suppose that DS = 1000H, SS = 2000H, BP = 1000H, and DI = 0100H. Determine the memory
    address accessed by each of the following, assuming real mode operation:
    (a) MOV AL,[BP+DI]
    (b) MOV CX,[DI]
    Suppose thai DS = i200ii, "DX = UIUOI:, and S: = 3250II. Determine :he address accessed

    NFC Institute of Engineering & Technology, Multan


    Department of Electrical Engineering
    Subject : Microprocessor Based System

    2K13-EE

    EE-401

    28. by each of the following instructions assuming real mode operation:


    (a) MOV [IOOH],DL
    (b) MOV [SI+lOOH],EAX
    29. Suppose that DS = 1300H, SS = 1400H, BP = l500H, and SI = 0100H. Determine the address
    Accessed by each of the following instructions, assuming real mode operation
    (a) MOV EAX,[BP+200H]
    (b) MOV AL,[BP+SI-200Hl
    30. How many bytes of memory store a far direct jump instruction? What is stored in each of the bytes?
    31. What is the difference between an intersegment jump and an intrasegment jump?
    Note

    Assignment should be handwritten or typed but in your own words


    Students groups as we have defined will submit this assignment
    Viva may be expected
    Submission date is 24-02-16 at 12 pm -01 pm

    Subject Teacher
    Engr. Zeeshan Raza

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