Lab Manual EC All

Basic Electronics
LIST OF EXPERIMENT
 Study of operation of all Logic Gates.
 Study of binary adders.

o Half Adder
o Full Adder
 Two Bit Binary Parallel Adder.
 Study of 2 Bit Binary Subtractor (Half Subtractor).
 Study of Binary to Gray Code Conversion.
 Study of Gray to Binary Code Conversion.
 Study of Binary to Excess -3 Code Conversion.
 To study Operational amplifier as a Differential amplifier.
 To study Operational amplifier as Inverting amplifier.
 To study Operational amplifier as a Non-inverting amplifier.

Experiment 1
Objective :
Study of operation of all Logic Gates
Equipments Needed
Components Quantity
1. IC 7408 2 input AND Gate. 1
2. IC 7432 2 input OR Gate. 1
3. IC 7400 2 input NAND Gate. 1
4. IC 7402 2 input NOR Gate 1
5. IC 74136 2 input EX-OR Gate 1
6. IC 7404 NOT Gate. 1
Logic diagrams and IC Pin diagrams
Truth Tables:
Input 1 Input 2 Output Input1 Input2 Output

X Y O X Y O
0 0 0 0 0 1
0 1 0 0 1 1
1 0 0 1 0 1
1 1 1 1 1 0
AND Gate NAND Gate
Input1 Input2 Output Input1 Input2 Output

X Y O X Y O
0 0 0 0 0 1
0 1 1 0 1 0
1 0 1 1 0 0
1 1 1 1 1 0
OR Gate NOR Gate

Input1 Input2 Output
X Y O
0 0 0
0 1 1 Input Output
1 0 1 1 0
1 1 0 0 1
EX-OR Gate NOT Gate
Procedure
AND Gate
1. Connect +5 V to pin no. 14 of IC 7408 and connect ground to pin no.7. (refer IC pin diagram)
2. Apply 0 (0 V) to pin no. 1 and 2 of IC 7408 shown in figure as per Truth Table
3. Connect output of AND Gate i.e pin no.3 to input of logic probe or 8 bits LED display.
4. Switch on the instrument
5. Observe output of Gate on 8 bits LED display
6. Outputs can also be observed on oscilloscope
7. Repeat steps 2, 3, 4 for different input combination
8. Verify Truth Table
NAND Gate
1. Connect +5 V to pin no. 14 of IC 7400 and ground to pin no. 7.(Refer IC pin diagram)
2. Apply 0 (0 V) to pin no. 1 & 2 of IC 7400 shown in figure as per Truth Table
3. Connect output of NAND Gate i.e pin no.3 to input of logic probe or 8 bits LED display.

OR Gate
3. Connect output of OR Gate i.e pin no.3 to input of logic probe or 8 bits LED display.
4. Repeat step 4, 5, 6 of NAND Gate.
NOR Gate
3. Connect output of NOR Gate i.e pin no.3 to input of logic probe or 8 bits LED display.
EX-OR Gate
3. Connect output of EX-OR Gate i.e pin no.3 to input of logic probe or 8 bits LED display.
NOT Gate
Experiment 2
Objective :
Study of binary adders
A. Half Adder
B. Full Adder
A. Half Adder
Equipments Needed
Components Quantity
2. IC 74136 2 input EX-OR Gate. 1
Logic diagram : Truth Table
Input1 Input2 Carry Sum
X Y C S
0 0 0 0
0 1 0 1
1 0 0 1
1 1 1 0
Procedure
1. Make connections as shown in figure
2. Connect +5V to pin no. 14 and ground to pin no.7 of IC 7408 and IC 74136. See
IC Pin diagram.
5. Observe outputs S and C on 8 bits LED display
7. Repeat steps 4,5,6,7 for other input combinations
8. Verify Truth Table.
B. FULL Adder
Equipments Needed
Components Quantity
2. IC 7432 2 input OR Gate 1

Logic diagram :
Truth Table :
Input Input Input Output

Carry Carry Sum
X Y Ci Co S
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1
Procedure
Same as above
Observation and Result

Full adder can be implemented using two half Adder. Adders are studied and Truth
Tables are verified.
Experiment 3
Objective :
Two Bit Binary Parallel Adder

Equipments Needed
Components Quantity
2. IC 7404 2 input NOT Gate 1
Logic diagram :
Truth Table :
Input 1 Input 2 Input 1 Input 2 Carry Sum Sum
Sr. No. Bit 1 Bit 2 Bit 1 Bit 2
Al A0 B1 B0 C0 S1 S0
1 0 0 0 1 0 0 1
2 0 1 0 1 0 1 0
3 0 1 1 1 1 0 0
4 0 0 1 0 1 0 0
5 1 0 1 1 1 0 1
Procedure
2. Connect +5V to pin no. 14 and ground to pin no.7 of IC 7408 and IC 74136.
3. See IC Pin diagram.
4. Connect 0 (0V) and 1 (+5 V) to inputs A1, A0, B1, B0 of adder shown as per Truth Table.
5. Observe outputs S1, S0 and C0 on 8 bits LED display
Experiment 4
Objective :
Study of 2 Bit Binary Subtractor (Half Subtractor).
Equipments Needed
Components Quantity
Logic diagram :
Truth Table :
Input 1 Input 2 Borrow Difference

X Y B D
0 0 0 0
0 1 1 1
1 0 0 1
1 1 0 0
Procedure
2. Connect +5V to pin no. 14 and ground to pin no.7.
4. Connect 0 (0V) and 1 (+5 V) to inputs X and Y of subtractor shown as per Truth Table.
5. Observe outputs on 8 bits LED display
Experiment 5
Objective :
Study of Binary to Gray Code Conversion
Equipments Needed
Components Quantity
Logic diagram :
Truth Table :
Binary Code Gray Code

B3 B2 B1 B0 G3 G2 G1 G0
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 0 0 0 1 1
0 0 1 1 0 0 1 0
0 1 0 0 0 1 1 0
0 1 0 1 0 1 1 1
0 1 1 0 0 1 0 1
0 1 1 1 0 1 0 0
1 0 0 0 1 1 0 0
1 0 0 1 1 1 0 1
1 0 1 0 1 1 1 1
1 0 1 1 1 1 1 0
1 1 0 0 1 0 1 0
1 1 0 1 1 0 1 1
1 1 1 0 1 0 0 1
1 1 1 1 1 0 0 0
Procedure
4. Apply 0 (0V) and 1 (+5 V) to binary inputs B3, B2, B1, B0 shown as per Truth Table.
5. Observe outputs G3, G2, B1, G0,on 8 bits LED display

Binary to gray code conversion is studied. Most significant bit of binary as well as
gray code is same as far as 4 bit code is concerned.
Experiment 6
Objective :
Study of Gray to Binary Code Conversion
Equipments Needed
Components Quantity
Logic diagram :
Truth Table
Gray Code Binary Code

G3 G2 G1 G0 B3 B2 B1 B0
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 1 0 0 1 0
0 0 1 0 0 0 1 1
0 1 1 0 0 1 0 0
0 1 1 1 0 1 0 1
0 1 0 1 0 1 1 0
0 1 0 0 0 1 1 1
1 1 0 0 1 0 0 0
1 1 0 1 1 0 0 1
1 1 1 1 1 0 1 0
1 1 1 0 1 0 1 1
1 0 1 0 1 1 0 0
1 0 1 1 1 1 0 1
1 0 0 1 1 1 1 0
1 0 0 0 1 1 1 1
Procedure
4. Apply 0 (0V) and 1 (+5 V) to gray code inputs G3, G2, G1, G0 shown as per Truth Table.
6. Observe output on 8 bits LED display
7 Outputs can also be observed on oscilloscope
Experiment 7
Objective :
Study of Binary to Excess -3 Code Conversion
Equipments Needed
Components Quantity
Logic diagram :
Procedure
9.. Verify Truth Table.
Truth Table:
B3 B2 B1 B0 E3 E2 El E0
0 0 0 0 0 0 1 1
0 0 0 1 0 1 0 0
0 0 1 0 0 1 0 1
0 0 1 1 0 1 1 0
0 1 0 0 0 1 1 1
0 1 0 1 1 0 0 0
0 1 1 0 1 0 0 1
0 1 1 1 1 0 1 0
1 0 0 0 1 0 1 1
1 0 0 1 1 1 0 0
1 0 1 0 1 1 0 1
1 0 1 1 1 1 1 0
1 1 0 0 1 1 1 1
EXPERIMENT 8
Objective :
To study Operational amplifier as a Differential amplifier.
Apparatus required :
1. Analog board of AB42.
2. DC power supplies +12V and -12V from external source or ST2612 Analog Lab.
3. Variable DC supplies (+5V and +12V)
4. Digital multi-meter.
5. 2 mm. patch cords.
Circuit diagram :
Procedure :
 Connect +12V, -12V DC power supplies at their indicated position from external source or ST2612
Analog Lab.
1. Set the value of feedback resistance RF equals to 10K with the help of potentiometer observing
its value at socket’s ‘E’ and ‘F’.
2. Set the value of resistance ROM equals to 10 K with the help of potentiometer observing its value
at socket’s ‘H’ and ‘Vin2’.
3. Connect a patch cord between test point B & H; and F & G, Vin2 & ground to configure a
Differential Amplifier.
4. Switch ON the power supplies.
5. Connect the +5V supply at socket ‘Vin1’; that is inverting input for Op-amp. Keep this supply at
constant +5V.
6. Connect the Variable +12V supply at socket ‘A’; that is noninverting input for op-amp. Set the supply
voltage at 1V.
7. Calculate the value of output by using Eq.3;
Vout = Rf/R1 (Vinl- Vin2)
8. Where Vin1 is the input at socket ‘A’ noninverting terminal, and Vin2 is the input at socket ‘Vin1’ inverting
terminal.
9. Connect the multimeter’s probes at socket ‘Vout’ and Ground.
10. Note the output voltage and Verify the difference between calculated and measured output voltage.
11. Increase the input voltage at noninverting terminal (socket ‘A’) with the margin of 1V up to 10 V whilst
keeping input voltage at inverting terminal at constant +5V.
12. Repeat the above steps from 7 to 10.
 The Differential output of two AC signal can be observe

1. If the inputs which are given in the input terminals are at same frequency and have 180 phase shift.
2. Then the difference between both signal will appear at the output
3. It is difficult to get the inputs which have same frequency, thus this bridges are used at measuring the
differential voltage at AC Bridges.
Note :
1. Try to make given circuits on the bread board strip given on the Analog Board to practice and understand
its connections.
Observation table :
S. No. VIN1 VIN2 VOUT VOUT

(Calculated) (Measured)
Conclusion : The calculated and measured output are almost the same.
EXPERIMENT 9
Objective :
To study Operational amplifier as Inverting amplifier.
2. DC power supplies +12V and -12V
3. Function generator
4. Oscilloscope
Circuit diagram :
Procedure :
Analog Lab.
1. Set the value of feedback resistance RF equals to 10K with the help of potentiometer R F observing its value at
sockets ‘E’ and ‘F’.
2. Set the value of resistance R OM equals to 5 K with the help of potentiometer R OM observing its value at socket
‘H’ and ‘Vin2’.
3. Connect a patch cord between sockets ‘F’ & ‘G’; and ‘Vin2’ & ground to configure the Inverting amplifier.
4. Connect Function generator’s probe at the socket ‘Vinl’; to apply 1Vpp, 1 KHz, sine wave signal at input.
5. Observe the input amplitude on oscilloscope CHII.
6. Calculate the output for the given value of input using Eq.1
Vout = - (Rf / R1) Vin.
7. Observe the output waveform between socket ‘Vout’ and Ground on oscilloscope CHI.
8. Note the output voltage and Verify the difference between calculated and measured output voltage
9. Note the phase shift between the output and input waveform.
10. Repeat the above procedure for different value of feedback resistance RF.
11. Repeat the above procedure for different value of input voltage ‘Vin’.
Note : To see the phase shift between input and output signal its necessary to connect both, input and output
signal at the oscilloscope channels.
Observation table :
Phase
S. VIN RF RF / VOUT VOUT
shift
No. R1 (Measured)
(Calculated) (φ)
Conclusion :
1. The calculated and measured output is almost the same.
2. The Phase shift between input and output signal is 180
EXPERIMENT 10
Objective :
To study Operational amplifier as a Non-inverting amplifier.
3. Oscilloscope
Circuit diagram :
Procedure :
Analog Lab.
1. Set the value of feedback resistance RF equals to 10K with the help of potentiometer RF
observing its value at sockets ‘E’ and ‘F’.
2. Connect a patch cord between sockets ‘F’ & ‘G’; and ‘Vin1’ & ground to configure the
Noninverting amplifier.
3. Connect Function generator’s probe at the socket ‘H’; to apply 1Vpp, 1 KHz, sine wave signal at
noninverting input terminal.
Vout = (1+Rf / R1) Vin
7. Note the output voltage and Verify the difference between calculated and
measured output voltage
8. Note the phase shift between the output and input wavefrom.
Note : To see the phase shift between input and output signal its necessary to connect both input and output signal
at the oscilloscope channels.
Observation table :
Phase
S. VIN RF 1+(RF VOUT VOUT
shift
No. /R1) (Measured)
(Calculated) (φ)
Conclusion :
2. The Phase shift between input and output signal is 0.
Electronics and Instrumentation Lab manual
LIST OF EXPERIMENTS
1. To measure the value of unknown inductance with the help of Maxwell's inductance
bridge
2. To measure the value of unknown capacitance with the help of shering bridge
3. To study of weign bridge oscillator and effect on output frequency with variation in
RCcombination
4. To study the characteristics of photo voltaic cell
5. To study and observe the characteristic of PIN Photo diode
6. To study the characteristic of platinum RTD
7. To study the operation of analog to digital converter
8. To study and observe the functional verification of a weighted resistor digital to analog
converter
EXPERIMENT NO : 1
AIM
To measure the value of unknown inductance with the help of Maxwell's inductance bridge
Apparatus required
Analog board
Dc power supply
function generator
2mm patch cord
Digital multimeter
Theory
This is the simplest method of comparing two inductance and to determine the values off
unknown inductance.Its first arm consist of a non inductive resistance R1 second arm consist of
a standard inducter in series with the noninductive resistance R3 is used for resistance balance
control third arm consist of an unknown inductors with internal resistance Rx The balance can
be obtained by varying resistance R2 of third arm
L1 = inductor with unknown inductance

Rx= internal resistance
L3= standard inductor
R1,R3= non inductive resistance
At balance
Z1 Zx=Z2 Z3
the value of Lx can be calculated by the formula
Lx =LR/R
The value of R can be calculated by the formula
R = RR/R
Where Lis the value of unknown inductor and R is internal resistaance
PROCEDURE
1. Connect external power supply

2. Connect function generator probe in between Vin terminals
3. Make connection as shown in figure
4. Set 5Vpp,1 Khz input sinusoidal signal of function generator
5. Rotate the potentiometer R2 to find null or minimum sound is generated
6. Switch off the power supply and function generator
7. Take the reading of potentiometer resistance R2 between test points TP2 and TP3
8. calculate the value of inductance Lxi and Rxi by there formula
9. Take the reading of unknown internal resistance Rx1 at socket a and test point Tp2
10 Repeat the above steps for different values of Lx and Rx
OBSERVATION TABLE
S NO RI R2 L3 LX=L3R2/R1 Rx=R2R3/R1
1
2
3
CALCULATION
Measured value of R2 is .............ohm
Now measure the value of Lx by the formula
LX=L3R2/R1
Measured value of resistance Rx by the multimeter between socket .........ohm

Now measure the values of Rx by the formula
Rx=R2R3/R1
Result
The inductance for Lx is measured to be =.............micro henry
The internal resistance is =.................ohm
EXPERIMENT NO :2
Aim
To measure the value of unknown capacitance with the help of shering bridge
Apparatus required
Analog board
DC power supply
Function generator
2mm patch cord
Digital multimeter
Theory
This bridge is the simplest method of comparing Two capacitance and to determine
unknown capacitance In first arm Zx consist of an unknown capacitor cx in series with the
resistance Rx and second arm consist of capacitor c3 and third arm consist of variable
resistance R2 and forth arm consist of a parallel combinaation of resistance R 1 and capacitor c1
The balance can be obtained by varying the resistance R2of third arm
At balance
Z1Zx=Z2Z3
The value of Rx can be calculated by formula
RX=R2C1/C3 The value of Cx can be calculated by the formula
Cx =R1C3/R2
Procedure
1. Connect external powerr supply
2. connect functioon generator probe in between vin termminals
3. Make connectioon as shown in figure
4. Set 5Vpp,1 Khz input sinusoidal signal of function generatorr
5. Rotate the potentiometer R2 to find null or minimum sound is generated

6. Switch off the power supply and function generatorr
7. Take the readingg of potentiometer resistance R2 between test points TP2 and TP3
8. calculate the value of capacitance Cxi and Rxi by there formula
9. Take the reading of unknown internal resistance Rx1 at socket a and test point Tp2
10. Repeat the above steps for different values of Cx and Rx
Observaation table
S no R1 C1 C R RX=R2C1/C3 CX= R1C3/R2
1
2
3
Measured value of R2 is ...............ohm /k ohm
Now measure the value of Cx by the formula

CX= R1C3/R2
Now measure the value of Rx by the formula
RX=R2C1/C3
Result
The capacitance of capacitor CX= ...........micro farad
The effective resistance Rx= ...................ohm /K ohm
EXPERIMENT NO 3
Aim
To study of weign bridge oscillator and effect on output frequency with variation in RC
combination
Apparatus required
experiment kit
connecting probes
DC power supply
2 mm patch cord
Theory
The weign bridge is one of the simplest and best known oscillators and is used
extensively in circuits for audio applications Figure I shows the basic Wien bridge circuit
configuration On the positive side This circuit has only a few components and good frequency
stability
Because of this simplicity and stability it is most commonly used audio frequency oscillator
The bridge has a series RC network in one arm and parallel RC network in the adjoining arm
In the remaining two arms of the bridge resistor R1 and Rf are connected
The phase angle criterion for oscilaation is that the total phase shift around the circuit must be
zero
This condition occures only when the bridge is balanced that is at resonance.The frequency of
oscillation Fo is exactly the resonant frequency of the balanced Wien bridge and is given by
F0 =0.159/RC
Procedure
1. Connect +12 v,-12 v DC power supply at their indicated position from external source
2. Connect a 2mm patch cord between test point 1 and H
3. Switch on the power supply
4. Vary Rf pot to make gain (Rf/R1)greater than 2
5. Record the value of output frequency at test point G
6. Compare measured frequency with theoritically calculated value
7. Vaary the gain pot of 470K to adjust the gain of the amplifier in case of clipped wave
form
8. Switch off the power supply
9. Connect a 2mm patch cord between test point A and B ,D and E
10. Repeat the above steps from step 3 to 8
11. switch off the power suppy

connect a 2 mm patch cord between test point B and C ,E and F
Result
weign bridge oscillator is studied and wave form is observed
EXPERIMENT NO : 4
AIM
To study the characteristics of photo voltaic cell
APPARATUS REQUIRED
experiment kit,connecting probes,digital multimeter
Theory
The photo voltaic cell is a two layer device,It generate a voltage by electron/hole pair
production when the junction is exposed to light.these diffuse across the junction to set up
voltage. A current will flow if a resistance is placed across the terminal optimized for energy
production are often called solar cells This is an important class of photo detectors. They
generate a voltage proportional to EM radiation intensity. They are called photo voltaic cells
because of their voltage generating characteristic
when light falls on them. They in fact convert the EM energy into electrical energy. They are
active transducers ie they do not need an external source to power them instead they generating
voltage
The cell is a diode constructing a pn junction between appropriately doped semiconductors

Photons striking cell pass through the thin p doped under layer and are absorbed by electrons
in lower layer causing a difference of potential to develop across the junction. All photo
voltaic cell have low but finite internal resistance .When connected in circuit having some load
resistance
photo voltaic the cell voltage is reduced some what from rated value
The photo voltaic cell can operate satisfactorily in temperature range of 100 to 125 c
The temperature changes have little effect on short circuited current but affect the open
circuited voltage considerably The main advantage of the photo voltaic cell as name implies
are its stability to generate a voltage without any form of bias and its extremely fast responses
This means that it can be used as an energy converter directly.
PROCEDURE
6. Connect the circuit as shown in figure
7. The socket C of wire wound pot to +12 v
7. The socket A of Wire wound pot to 0v
8. The socket B of wire wound pot to input of powerr amplifier
9. The out put of power amplifier to input of Lamp filament
10. The other input of filament lamp to +ve input of Moving coil meterr '
11. The -ve input of moving coil meter to 0 v

12. Output of photo voltaic cell to 0v through a digital multimeter connected as an
ammeter at 2 mA range to measure short circuit current of photo voltaic cell
13. switch ON the power supply & set the 10 K ohm wire wound pot to minimum zero
output voltage from power amplifier
14. Place the opaque box over the plastic enclosure to exclude all the ambient light Take
reading of photo voltaic cell short circuit output current as indicated on digital
multimeter as lamp voltage is increased in 1 v steps record the result in below table
OBSERVATION TABLE
Lamp filament 0 1 2 3 4 5 6 7 8 9 10
voltage
Short circuit output

current (Micro A)
Open circuit output
voltage
 Switch off the power supply &set the digital multimeter as voltmeter at 2/20 v dc
range to read the open circuit output voltage
 Switch on thee power supply and take the reading adding result to above table
 switch off the power supply
 Plot the graphs off photo voltaic cell short circuit current & open circuit voltage against
lamp filament voltage
RESULT
characteristic of photo voltaic cell is plotted
EXPERIMENT NO :5
Aim
To study and observe the characteristic of PIN Photo diode

Apparatus required
experiment kit,connecting probes
Theory
PIN photodiode differs from a standard PN photodiode by having layer of intrinsic

silicon.The intrinsic (I) region between normal P&N junction.The main improvement of
introuduction of I region is reducing capacitance of junction resulting improvement of
introuduction of I region is reducing capacitance of junction resulting in fast response time
When photodiode is reverse biased The reverse saturation current is depend upon the
intensity of incident light The photodiode Vs light relation ship is linear over wide range in
order to maintaine linearity the bias volatage should be kept constant The output resistance
of photodiode is very high of the order of tens of mega ohms the DC resistance is the diode
leakage resistance and that too is very high This DC resistance depends upon the light
intensity.
Procedure
4. Connect the circuit as shown in the figure
5. socket c of wire wound pot to +12 v
2. socket A of wire wound pot to input of power amplifier
3. socket B of wire wound pot to input of power amplifier
Output of power amplifier to input of filament lamp
Other input of filament lamp to + ve input of moving coil meter
Connect -ve input of moving coil meter to 0v
Output of PIN photot diode to input of current amplifier this is used to measure the current
output of PIN photodiode
Output of current amplifier to input of DC amplifier
connect a digital multimeter as voltmeter on 20v dc range betwen output of DC amplifier and
0v to measure the output voltage of DC amplifier
Place opaque box over the plastic enclosure to enclosure to exclude all ambient light
Switch on the power supply and set the 10 k ohm wire wound pot.To minimum input at DC
amplifier
Take reading of Amplifier output voltage on digital multimeter as lamp voltage is increased in
1v steps record the result in below table
Lamp filament voltagee 0 1 2 3 4 5 6 7 8 9

(v)
PIN Photodiode DC
amplifier output voltage
(v)
PIN Photodiode Buffer
output voltage (V)
Switch off the power supply
Change the current Amplifier to Buffer to measure output of PIN photo diode Take the reading
of PIN Photodiode output voltage as the lamp voltage is increased in 1v steps record the result
in table 4 remember to adjust the offset of DC amplifier is giving zero output for zero input
Plot the graph between PIN photodiode current amplifier output voltage,buffer amplifier
output voltage &Lamp filament voltage.It should resemble the one given below
Result
chaaracterisic of PIN photodiode is studied
EXPERIMENT NO :6
Aim
To study the characteristic of platinum RTD
Apparatus required
Experiment kit connecting probes digital multimeter
Theory
The variation in resistance of metal with variation in temperature is the basis of of temprature
measuremet in platinum rtd The metal generally used is platinum or tungsten Platinum is
especially suited for this purpose.as it can show limited susceptibility to contaminaation all
metal produce a positive change in resistance with temprature This of course is the main
function of an RTD.This implies that a metal with high value off resistance should be used for
RTD the requirment of the conductor material to be used in RTD are
The change in resistance of material per unit change in temperature should be as large as
possible
The material should have high value of resistance so that minimum volume of material is used
for the construction of RTD
The resistance of material should have continoous and stable relation ship with temperature
Platinum or tungsten wire is wound on a former to give a resistance in range of 10 K ohm
depending upon application
Procedure
1. connect the circuit as shown in figure
2. The socket 'c'of slide potentiometer to +5v
3. The socket 'b' of slide potentiometer to output of platinum RTD connect digital
multimeter as
4. voltameter on 200 mv orr 2v DC range in between output of platinum RTD &ground
5. Set the 10 K slider resistance midway
6. Switch on the instrument check the output of IC temperature sensor for ambient
temperature by temperorily connecting DMM in 20 v DC range and find out the
resissstance in ohm for this particular temperaturee
7. Say for example ambient is 250c then platinum RTD reading as per chart is 109.73
8. Switch on the power supply adjust the slider control of the 10 K ohm resistance to the
voltage drop across the platinum RTD is 109mv as indicatied by DMM This
calliberate the platinum RTD for an ambient temperature of 250c since the resistance
at 250c will be 109 ohms Note that the voltage reading across the RTD in mV is the
same as the RTD resistance jin ohms,since current flowing must be 0.109/109=1 mA
9 Connect the +12V supply to Heater element input and note the values of the voltage across
the RTD with the voltmeter to its 200mV or 2 Vrange (this representing the RTD resistance )
and the output voltage from the IC temperature sensor with the voltmeter set to its 20 v range
(this representing the temperature of the RTD ) after each minute given in below table
Time (minutes) 0 1 2 3 4 5 6 7 8 9
RTD
Temperaaature
RTD resistance (OHM )
Switch of the power supply and disconnect heater element supply (+12)
Convert RTD temperature into 0c & add in above table
Plot the graph of RTD resistance in ohm against temperature in 0c .It should resemble the one
given below
T
emperature Vs resistance Table
0 100.00 30 111.67
1 100.39 31 112.06
2 100.78 32 112.44
3 101.17 33 112.83
4 101.56 34 113.22
5 101.95 35 113.61
6 102.34 36 114.99
7 102.73 37 114..77
8 103.12 38 115.15
9 103.51 39 115.15
10 103.90 40 115.54
11 104.29 41 115.93
12 104.68 42 116.31
13 105.07 43 116.70
14 105.46 44 117.08
15 105.85 45 117.47
16 106.23 46 117.86
17 106.62 47 118.24
18 107.01 48 118.63
19 107.40 49 119.01
20 107.79 50 119.40
21 108.18 51 119.78
22 108.57 52 120.17
23 108.57 53 120.55
24 109.34 54 120.94
25 109.73 55 121.32
26 110.12 56 121.70
27 110.51 57 122.09
28 110.89 58 122.47
29 111.28 59 122.86
60 123.24
EXPERIMENT NO : 7
Aim
To study the operation of analog to digital converter
Apparatus required
Experiment kit,connecting probes,oscilloscope

Theory
The analog to digital conversion is a logical process that requires conceptually two
steps the quantizing and the coding. Quantization is the process that performs the
transformation of continuous signal in a set of discrete level soon afterward we combine
through the coding each discrete levels with a digital word
.The digital to analog converter performs the conversion in n steps where n is the
converter settlement in bits .The working principle of this converter is analogous to that of
weighing an object on laboratory balance using standard weights as reference according to the
binary sequence ¼,1/8,1/16............1/n Kilograms
to perform accurately we start with largest weight and go on decreasing order to one of
smallest value
PROCEDURE
7. Connect the power supply to the trainer
8. Make the connection as shown in the figure
9. Connect the dc supply to the Vi of the converter
10. Keep the DC pot in counter clock wise position
11. Place the reset/count switch in reset position
12. Switch ON the power supply Keep the DC pot at mid position
13. To start conversion place the switch in count position the LED lit accroadding to
binary sequence
14. When the signal from the digital to analog converter goes over the input signal the
counter stops and LEDs show the binary conversion
15. Vary the DC pot and observe thee corresponding digital output. The converter will
follow the changes in analog signal without resetting the converter in upward direction
because the counter is configured as up counter only but to observe the converted
output when the input is decreased you have to reset the converter
16. Observe on the oscilloscope the typical steps signal at the D/A output
17. Observe input voltage using digital multimeter and observe output LED
18. Repeat the test with the different values of input signal.
Result
Analog to digital conversion is studied
EXPERIMENT NO : 8
AIM
To study and observe the functional verification of a weighted resistor digital to analog
converter
APPARATUS REQUIRED
experiment kit,connecting probes ,digital multimeter
THEORY
The simplest digital to analog converter is obtained by means of a summing circuit with input
resistance whose value depends on the bit weight that are associated to. We obtain in this way
the weighted resistors converter The switches s3-s0 are driven from the digital information so
that every resistance is connected to reference voltage v ref or to ground in accordance with
the fact that the corresponding bit is at logical level 1 or 0
PROCEDURE
 Connect the power supply to the board
 Connect the D0-D3 of the logic switches to the corresponding jacks B0-B3 of the
converter
set the switches S0-S3 to logic level 0
 Connect the v Ref socket to +5v connect a multimeter as voltmeter for DC to the output
v0of the converters
 Switch the logic switches in binary progression &measure &recorded the output voltage
in corresponding of every combination of the input code
 With input code s3 s2 s1 s0=0000 the output voltage v0 has to be null eventually little
deviation against zero are due to operational amplifier offset
 Switch off the power supply
Result
Digital to analog converter is studied and output is verified

1. Study of Diode in DC circuits.
2. Study of Light Emitting Diode in DC circuits.
3. Study of HalfWave Rectifier.
4. Study of FullWave Rectifier

1. Conventional FullWave Rectifier
i. 2.Bridge Rectifier .
5. Study of Zener Diode as a Voltage Regulator.
6. Study of Transistor series Voltage Regulator.
7. Study of Transistor Shunt Voltage Regulator.
8. Study of Low Pass Filter.
9. Study of High Pass Filter.
10. Study of Band Pass Filter.

Experiment 1
Objective :
Study of Diode in DC circuits
Equipments Needed :
Component Quantity
1. Potentiometer 1 K1
2. Diode KH4007 2
Circuit diagram :
Procedure :
1. Make connections as shown in diagram.
2. Connect +12V supply from DC power supply block to 1 and 2.
3. Connect terminal 3 to 4.
4. Connect voltmeter across D1.
5. Connect ammeter between terminal 6 and 7.
6. Turn potentiometer to minimum resistance value.
7. Switch on the instrument.
8. Vary potentiometer and note down reading of voltmeter and ammeter.
9. Repeat above steps for diode D2.
Observation :
Current in forward biased diode increases exponentially up to cut-in voltage (0.687V)
and linearly after wards.
Experiment 2
Objective :
Study of Light Emitting Diode in DC circuits
Equipments Needed :
Component Quantity
1. Potentiometer 1K1
2. LED 2
Circuit diagram :
Procedure :
2. Connect + 12V supply from DC power supply block to 1 and 2.
3. Connect terminal 3 to 4.
4. Connect voltmeter across D1.
5. Connect ammeter between terminal 6 and 7.
6. Turn potentiometer to minimum resistance value.
8. Vary potentiometer and note down reading of voltmeter and ammeter.
9. Repeat above steps for diode D2.
Observation :
Current in forward biased LED increases exponentially up to cut-in voltage (1.4V)
and linearly afterwards.
Experiment 3
Objective :
Study of HalfWave Rectifier
Equipments Needed :
Component Quantity
1. Resistance 1 K1
2. Diode KH4007 1
3. Capacitor 47μF 1
Circuit diagram :
Procedure :
2. Connect 9V AC from AC voltage block to terminals 1 and 2.
3. Disconnect capacitor C from the circuit.
5. Connect terminals 3 and 4 to oscilloscope and observe output.
6. Now connect capacitor C at its place and observe output on oscilloscope.
Experiment 4
Objective :
Study of FullWave Rectifier
1. Conventional FullWave Rectifier
2. Bridge Rectifier
Equipments Needed :
Component Quantity
1. Resistors 1 K1
2. Diodes KH4007 4
Circuit diagram :
Procedure :
1. Make connection as shown in diagram 1.
2. Connect 9V -0V -9V AC from AC voltage block to terminals 1, 2 and 3.
3. Disconnect capacitor C from the circuit.
5. Connect terminals 4 and 5 to oscilloscope and observe output.
6. Now connect capacitor C at its place and observe output on oscilloscope.
7. Repeat above steps for bridge rectifier as shown in diagram 2.
Experiment 5
Objective :
Study of Zener Diode as a Voltage Regulator
Equipments Needed :
Component Quantity
1. Resistance 52Ω 1W 1
2. Potentiometer
1K1
100K1
3. Zener Diode 5.6 V 1
Procedure :
3. Connect voltmeter 1 across terminal 3 and ground to measure input voltage.
4. Connect ohm meter 2 across terminal 5 and ground to measure output voltage.
5. Vary potentiometer P2 and set the value of resistance between terminal 5 and
ground to 2 K.
6. Connect terminal 4 and 5.
7. Connect voltmeter 2 across terminal 5 and ground to measure output volt.
8. Switch on the supply.
9 Vary the Input voltage with the potentiometer P1 in steps between 6V to 8V andmeasure the
corresponding values of voltmeter 2.
10. Connect ohmmeter between terminal 5 and ground.
11. Disconnect terminal 4 and 5.
12. Connect voltmeter between terminal 5 and ground.
13. Set the potentiometer P2 so that the value of resistance between terminal 5 and
ground is minimum.
15. Adjust input voltage V1 equal to 9V with the potentiometer P1.
16. Vary the load resistance RL with the potentiometer P2 from its minimum value
to maximum value and measure the output voltage across terminal 5 and ground.
Observations :
1. In first case when input voltage is varied keeping load resistance constant
(2K), regulated 5.6 V across load is obtained.
2. In Second case when load resistance is varied keeping input voltage constant
(9V), regulated 5.6V across load is obtained.
Experiment 6
Objective :
Study of Transistor series Voltage Regulator
Equipments Needed :
Component Quantity
1. Resistor
200 1
100 1
2. Potentiometer
1K1
100K1
3. NPN Transistor STN 3904 1
4. Zener Diode 5.6 V 1
Procedure :
4. Connect ohmmeter 2 across terminal 6 and ground to measure output voltage.
5. Vary potentiometer P2 and set the value of resistance between terminal 6 and
ground to 500ohm.
8. Connect voltmeter between terminal 6 and ground.
9. Vary the input voltage with the potentiometer P1 in steps between 6.5V to 9.5V
and measure the corresponding values of voltmeter 2.
10. Measure voltage VBE between terminals 4 and 5, terminal 4 and ground (zener
voltage) at every step.
ground is 100 ohm (minimum).
15. Vary the load resistance RL with potentiometer P2 from its minimum value to
maximum value and measure output voltage.
16. Measure the zener voltage between terminals 4 and ground, voltage V BE across
terminals 4 and 5 at every step.
Experiment 7
Objective :
Study of Transistor Shunt Voltage Regulator
Equipments Needed :
Component Quantity
1. Resistance
2001
52 (lW) 1
2. Potentiometer 1K2
3. NPN transistor STN 3904 1
4. Zener diode 5.6 V 1
Circuit diagram :
Procedure :
4. Connect voltmeter 2 across terminal 7 and ground to measure output voltage.
5. Vary potentiometer P2 and set the resistance between point 7 and ground to 400
ohm.
8. Connect a voltmeter between terminal 7 and ground.

9. Vary the input voltage with potentiometer P1 in steps between 7V to 10V and
measure the corresponding values of voltmeter 2.
10. Also measure the zener voltage between terminals 4 and 5 and V BE between the
terminals 5 and ground at every step.
ground will be 200 .
15. Vary the load resistance RL with the potentiometer P2 from its minimum to
maximum value and measure the corresponding values of output voltage in
voltmeter 2.
16. Measure zener voltage between terminals 4 and 5 and voltage V BE between the
terminals 5 and ground at every step.
Experiment 8
Objective :
Study of Low Pass Filter
Equipments Needed :
Component Quantity
1. Resistors 10K2
2. Pot 100K1
3. Capacitor 0.01μF 1
4. IC 741 1
Circuit diagram :
Procedure :
2. Connect + 12V to pin no 7 and -12V to pin no 4 of IC741. See IC pin diagram.
3. Set the potentiometer at 15.9K.
4. Connect a sine wave of amplitude 1Vp-p, 100Hz from function generator block
to the Vin input of low pass filter as shown in the figure.
6. Observe the Vout output on the oscilloscope. A sine wave of 2Vp-p of
corresponding frequency is observed on oscilloscope, since the gain of low pass
filter is 2.
7. Vary the frequency of input signal and observe Vout on oscilloscope.
Experiment 9
Objective :
Study of High Pass Filter
Equipments Needed :
Component Quantity
2. Pot 100K1
4. IC 741 1
Circuit diagram :
Procedure :
2. Connect +12V to pin no 7 and -12V to pin no 4 of IC741 See IC pin diagram.
3. Set the potentiometer at 15.9K.
4. Connect a sine wave of amplitude 1Vp-p, 10 KHz from function generator block
to the Vin input of high pass filter as shown in the figure.
corresponding frequency is observed on oscilloscope, since the gain of high pass
filter is 2.
7. Decrease the frequency of input signal and observe Vout on oscilloscope.
Experiment 10
Objective :
Study of Band Pass Filter
Equipments Needed :
Component Quantity
2. Pot 100K2
3. Capacitor 0.0lμF 1
5. IC 741 2
Circuit diagram :
Procedure :
2. Connect + 12V to pin no 7 and -12V to pin no 4 of IC741. See IC pin diagram.
3. Set the potentiometer P1 at 15.9Kμ.
4. Set the potentiometer P2 at 7.9Kμ.
5. Connect a sine wave of amplitude 1Vp-p, 1 KHz from function generator block
to the Vin input of band pass filter as shown in the figure.
corresponding frequency is observed on oscilloscope, since the gain of band
pass filter is 2.
8. Increase the frequency of input signal till the observed output on oscilloscope
reduces to 0.707 times of mid band value.
9. Decrease the frequency of Input signal till the observed output on oscilloscope
reduces to 0.707 time of its mid band value.
NETWORK ANALYSIS LAB
Index
Exp. no Experiment Title
1
To verify Kirchhoff’s current law & Kirchhoff’s voltage law
2
To verify Maximum Power Transfer theorem
3
To verify Norton’s theorem.
4
To verify Thevenin’s theorem.
5
To verify Superposition theorem.
6
To verify Millman’s theorem
7
To verify Reciprocity Theorem.
8
To measure the Z – parameter for SINGLE and CASCADED TWO PORT
NETWORK.
9
To measure the Y – parameter for SINGLE and CASCADED TWO PORT
NETWORK.
10
To verify ABCD Parameter for SINGLE and CASCADED TWO PORT
NETWORK.
EXPERIMENT NO. 01
AIM: To verify Kirchhoff’s current law & Kirchhoff’s voltage law.
APPARATUS: Experimental Kit, Connecting Probes.

THEORY: In simple circuit, the current and voltages are calculated with the help of
ohm’s law. But in actual practice, where we have complex circuit with several resistors,
voltage sources and current sources, it becomes difficult to calculate the
current and voltage. In these situations KVL & KCL are used.
KIRCHHOFF’S CURRENT LAW:
This law states, “The algebraic sum of various current meeting at a
node in a closed electrical circuit is zero.”
Current flowing towards the node is taken as negative.
KIRCHHOFF’S VOLTAGE LAW:
This law states, “In a closed loop, the algebraic sum of e.m.f.s is equal to the product
of the resistances and respective current flowing through them.”
CIRCUIT DIAGRAM:
Fig. (1)
Fig. (2)
Fig. (3)
PROCEDURE:
CASE 1: For the calculation of current I1:

 Connect the circuit as shown in fig. (1)
 Connect the current meter (mA) across B & C points.
 Point C & D will remain open.
 Apply KVL to closed mesh ABCA.
5I1 + 10I1 = 2.5
15I1 = 2.5
I1 = 166.66 mA (Calculated value)
 Measure current I1 from current meter (measured value).
 Compare the calculated and measured value.
CASE 2: For the calculation of current I2:

 Connect the circuit as shown in fig. (2).
 Connect the current meter (mA) across C & D points.
 Point C & B will remain open.
 Apply KVL to closed mesh ADCA.
22 I2 +33 I2 = 2.5
55 I2 = 2.5
I2 = 45.45 mA (Calculated value)
 Measure current I2 from current meter (measured value).
 Compare the calculated and measured value.

CASE 3: For the calculation of total current I:
13. Connect the circuit as shown in fig. (3).
14. Connect B, C & D points.
15. Connect the current meter (mA) between the negative terminal of the battery
and point C.
Total Current I = I1 + I2
I = 212.11 mA (Calculated value)
16. Measure current I from current meter (measured value).
17. Compare the calculated and measured value.
OBSERVATION TABLE:
Current Through Total Current Verification of
S. No. Input Voltage
ABCA ADCA (i) Voltages
01.
02.
03.
04.
CALCULATIONS:
RESULT:
PRECAUTIONS:
8. The positive & negative terminals of the power supply should not be connected
together.
9. Supply for the experimental kit should be switched ON only after the
connections are verified.
10. Avoid parallax error.
11. Check the polarities of the meter before the observations are noted down.
EXPERIMENT NO. 02
AIM: To verify Maximum Power Transfer theorem.
THEORY: When the load is connected across a voltage source, power is transferred from
source to load. The amount of power transferred depends on the load resistance.
This theorem states, “Maximum power is transferred from source to load when the
load resistance is made equal to the internal resistance of the source.”
This theorem is applicable to A.C. as well as D.C. power.
CIRCUIT DIAGRAM:
PROCEDURE:
12. Connect 12V regulated power supply in the circuit.
13. Connect Ri and RL in the circuit. Also connect current meter and voltmeter in
the circuit.
14. Now increase the value of load resistance RL (potentiometer) in steps and note
down the corresponding voltage and current. Calculate the power:
P=V I
15. At a particular point when the load resistance is made equal to the internal
resistance of the source i.e., Ri , maximum power is transferred from source to
load.
16. Plot the graph between power and load resistance.
OBSERVATION TABLE:
Ri = 100 Ω Ri =……….Ω
S.NO.
I (mA) V (Volts) P (watts) I (mA) V (Volts) P (watts)
GRAPH:
RESULT:
PRECAUTIONS:
together.
EXPERIMENT NO. 03
AIM: To verify Norton’s theorem.

THEORY: This theorem states, “Any linear, bilateral network containing a number of
e.m.f. sources and resistances can be replaced by an equivalent circuit having a current
source IN in parallel with a resistance RN.”
Where, IN is the short circuit current flowing through the output terminals and RN
is the resistance measured across the output terminals with all other sources replaced by
their internal resistances, if any.
The load current is given by:
CIRCUIT DIAGRAM:
PROCEDURE:
17. Open the load and measure the voltage across X and Y (fig. 2).
18. Open circuit voltage VOC across R4 = …….V.
19. Now short circuit the voltage source with RL open (fig 3).
20. Now disconnect the voltage source and short A and B points as shown in fig 3.
21. Now the measure the resistance at X and Y i.e. RN.
Short Circuit Current:
IN = =……….mA.
Now the circuit may be replaced as:
IN=……….mA.
RN=……….Ω.
For RL= 25 Ω
=……….mA.
For RL= 50 Ω
=……….mA.
For RL= 75 Ω
=……….mA.
22. Measure the current through RL.
23. Compare calculated and measured values.

OBSERVATION TABLE:
RL= 25Ω RL= 50Ω RL= 100Ω
S. No.
IL (mA) IL (mA) IL (mA)
CACULATIONS:
RESULT:
PRECAUTIONS:
together.
EXPERIMENT NO. 04
AIM: To verify Thevenin’s theorem.

THEORY: Sometimes it is necessary to find a particular branch current in a circuit as
the resistance of that branch is varied while all other resistances, voltage sources and the
current sources remain the same.
This theorem states that,” Any two terminal network containing a number of e.m.f.
sources and resistances can be replaced by an equivalent series circuit having a voltage
source VTH in series with a resistance RTH.”
Where, VTH = Open circuit voltage between two terminals.
RTH = The resistance between two terminals of the circuit obtained by looking in at
the terminals with removed and voltage sources replaced by their internal resistances, if
any.
The load current is given by:
IL =
CIRCUIT DIAGRAM:
Fig. 01
Fig. 02
Fig. 03
Fig. 04
PROCEDURE:
24. Connect the circuit as shown in fig 1. Measure the values of load current at
different load resistance. It is IL1, IL2 & IL3.
25. Connect the circuit as shown in fig. 2. Disconnect the load resistor (RL) from
output terminals and measure the open circuit voltage (VTH) by connecting
analog voltmeter. Open circuit voltage will appear across 100Ω resistor:
V=
26. For measurement of Thevenin’s resistance across open circuit terminals X-Y,
disconnect the 12V voltage source and short the voltage source open circuit
terminals A-B as shown in fig. 3. Connect the digital multimeter across
terminal X-Y. Find the value of RTH.
Now measure the resistance across X and Y.
RTH =
27. Now, above circuit between X & Y can be replaced by Thevenin’s equivalent
circuit as shown in fig 4.
VTH = 1.8 V
RTH = 173.4 Ω
For RL = 25 Ω
IL1 = = ……….mA
For RL = 50 Ω
IL1 = = ……….mA
For RL = 75 Ω
IL1 = = ……….mA
28. Compare the calculated and measured values.

OBSERVATION TABLE:
S. No. Measured Value Calculated Value
RL = 25 Ω
RL = 50 Ω
RL = 75 Ω
RTH
VTH
RESULT:
PRECAUTIONS:
together.
EXPERIMENT NO. 05
AIM: To verify Superposition theorem.
THEORY: When there is only one source of e.m.f. or only one current source, then it is
very easy to calculate the current or the voltage. But in a complex circuit where there are
a number of sources acting simultaneously, then it is very difficult to calculate the current
or the voltages. In these situations superposition theorem is used.
The theorem states that, “If a number of current or voltage sources are acting
simultaneously in a linear network, the resultant current in any branch is the algebraic sum
of the currents that would be produced in it, when each source acts alone replacing all other
sources by their internal resistances.”
CIRCUIT DIAGRAM:
Fig. 01
Fig. 02
Fig. 03
PROCEDURE:
29. Connect the circuit as shown in fig 1. Measure the current i1, i2 and i3.
30. Connect the circuit as shown in fig. 2. Consider only one voltage source at a
time, first 12V. Short the second 5V source. Measure the current i1’, i2’ and i3’
(One ammeter is connected at a time, other ammeter is shorted).
31. Connect the circuit as shown in fig. 3. Consider only 5V voltage source. Short
the second 12V source. Measure the current i1’’, i2’’ and i3’’.
32. Calculate the value of i1’ , i2’ , i3’, i1’’, i2’’ and i3’’.
33. Compare the calculated and measured values.
OBSERVATION TABLE:
Sr. No. Measured Value Calculated Value
i1’
i2’
i3’
i1’’
i2’’
i3’’
i1
i2
i3
CALCULATIONS:
Consider only one voltage source at a time, first 12V.
RT = 50 + = 50 + 8.33 = 58.33 Ω
ITH =
IT = i1’
i3’ =
i2’ = i1’ - i3’ =……….

Therefore,
i1’ =……….
i2’=……….
i3’=……….
Now, considering 5V voltage source only:
RT = 50 + = 50 + 8.33 = 58.33 Ω
ITH =
IT = i3’’
i3’ =
i1’ = i3’ - i2’ =……….
Therefore,
i1’ =……….
i2’=……….
i3’=……….
According to superposition theorem,
Current through resistance R1 = i1’ - i1’’ =……….
Current through resistance R2 = i2’ – i2’’ =……….
Current through resistance R3 = i3’ – i3’’ =……….
RESULT:
PRECAUTIONS:
together.
EXPERIMENT NO. 06
AIM: To verify Millman’s theorem.

THEORY: This theorem states, “If several voltage sources in series with admittance are
connected in parallel as shown in figure, the equivalent circuit can be shown as a
combination of an equivalent voltage source (Veq) in series with an impedance Req.”
Here, Req =
Where, R = Resistance
Veq =
(From fig. 1)
Req =
Req =
Req = 100 Ω
Veq =
Veq =
IRL (For 220 Ω) =
IRL (For 300 Ω) =
IRL (For 400 Ω) =
CIRCUIT DIAGRAM:
Fig. No. 01
PROCEDURE:
34. Introduce the supplies (12V, 15V, 18V) in series with the resistance 300Ω by
shorting the dotted lines through patch chords as shown in fig. (1).
35. Switch ON the instrument using ON/OFF toggle switch provided on the front
panel.
36. Measure the Veq (equivalent voltage) with voltmeter as shown in fig. (1).
37. Now connect the current meter in series with load (RL).
38. Observe the different readings of current (IR) by introducing different load
resistances (RL = 220, 300 & 400 Ω) in the output by connecting dotted lines
through patch chord as shown in fig. (1). Compare the observed values with
the calculated values as given above. There may be a slight difference due to
tolerance resistance of resistance (± 10%).
OBSERVATION TABLE:
S. No. RL V IPRACTICAL
01.
02.
03.
GRAPH:
RESULT:
PRECAUTIONS:
together.
EXPERIMENT NO. 07
AIM: To verify Reciprocity Theorem.

THEORY: This theorem states, “In any linear, Bilateral network connecting one or more
generators, the ratio of voltage (V) introduced in one mesh to the current (I) in any second
mesh is the same as the ratio obtained if the position of the voltage and current are
interchanged, other e.m.f. being removed.”
CIRCUIT DIAGRAM:
Fig. 1(a)
Fig. 1(b)
Fig. 2(a)
Fig. 2(b)
PROCEDURE:
39. Connect the circuit as shown in fig 1(a).
40. Switch ON the instrument.
41. Note down the value of current I3.
42. Switch OFF the instrument and interchange the position of the voltage source
and current meter as shown in fig 1(b). Again switch ON the instrument.
43. Note down the value of current I1.

44. We observe that the value of current I3 is equal to the value of current I1. This
proves the RECIPROCITY THEOREM.
45. Similarly we can prove the theorem for the combinations of resistors.
OBSERVATION TABLE:
Circuit 1 Circuit 2
S. No.
I3 (mA) I1(mA) I1 (mA) I3 (mA)
01.
02.
03.
CALCULATIONS:
RESULT:
PRECAUTIONS:
together.
EXPERIMENT NO. 08
AIM: To measure the Z – parameter for SINGLE and CASCADED TWO PORT
NETWORK.

THEORY: A given two port network, with some degree of complexity, can be built up
from simple two port networks, whose ports are interconnected in certain ways.
Conversely, a two port network can be designed by combining two port structures as
building blocks.
There are a number of ways in which two port networks can be interconnected.
The simplest possible interconnection is termed as Cascade or Tandem connection. Two
port networks are said to be cascaded if the output of first becomes the input of the
second.
CIRCUIT DIAGRAM:
Fig. 01
Fig. 02
PROCEDURE:
46. Connect the circuit as shown in fig 1. It means, connect the variable voltage
supply to the input terminals of the network – I.
47. Vary the input voltage to 10V (V1) and measure the open circuited output
voltage (V2). Note down the input current through current meter.
V1 = Input voltage = 10V
V2 = Output voltage
I1 = Input current (Observed from current meter)
I2 = 0 (because output is open circuited)
48. Now short the output terminals and measure input current
V1’ = Input voltage = 10V
V2’ = 0
I1’ = Input current
I2’ = Output current

49. With these values calculate Z – Parameter for SINGLE TWO PORT
NETWORK.
Z11 = I2 = 0) Ω Z12 = I2 = 0) Ω
Z21 = I1 = 0) Z22 = I1 = 0)
50. Now connect the output of the first network to the input of the second network.
51. Apply variable voltage to the input terminals and adjust the voltage to 10V.
52. Now record.
V1 = Input voltage
V2 = Output voltage
I1 = Input current
I2 = Output current = 0
53. Interchange output and input terminals and measure the input voltage and
current and output voltage.
With these values calculate Z – parameter for cascaded network (repeat step 4).
OBSERVATION TABLE:
CALCULATIONS:
Z11 = I2 = 0) Ω Z21 = I2 = 0) Ω
Z21 = I1 = 0) Z22 = I1 = 0)
RESULT:
PRECAUTIONS:
together.
EXPERIMENT NO. 09
AIM: To measure the Y – parameter for SINGLE and CASCADED TWO PORT
NETWORK.

THEORY: A given two port network, with some degree of complexity, can be built up
Conversely, a two port network can be designed by combining two port structures as
building blocks.
The simplest possible interconnection is termed as Cascade or Tandem connection. Two
port networks are said to be cascaded if the output of first becomes the input of the
second.
CIRCUIT DIAGRAM:
Fig. 01
Fig. 02
PROCEDURE:
54. Connect the circuit as shown in fig 1. It means, connect the variable voltage
supply to the input terminals of the network – I.
55. Vary the input voltage to 10V (V1) and measure the open circuited output
voltage (V2). Note down the input current through current meter.
V2 = Output voltage
I1 = Input current (Observed from current meter)
56. Now short the output terminals and measure input current I1’.
V1’ = Input voltage = 10V
V2’ = 0
I1’ = Input current = 0.0062 A

I2’ = Output current = 0.004 A
57. With these values calculate Z – Parameter for SINGLE TWO PORT
NETWORK.
Y11 = V2 = 0) Ω Y12 = V2 = 0) Ω
Y21 = V1 = 0) Y22 = V1 = 0)
59. Apply variable voltage to the input terminals and adjust the voltage to 10V.
60. Now record.
V1 = Input voltage
V2 = Output voltage = 5012 V
I1 = Input current = 0.0062 A
61. Interchange output and input terminals and measure the input voltage and
With these values calculate Z – parameter for cascaded network (repeat step 4).
OBSERVATION TABLE:
S. No. RL= 25Ω RL= 50Ω RL= 50Ω
IL (mA) IL (mA) IL (mA)
CALCULATIONS:
Z11 = I2 = 0) Ω Z21 = I2 = 0) Ω
Z21 = I1 = 0) Z22 = I1 = 0)
RESULT:
PRECAUTIONS:
together.
EXPERIMENT NO.10
AIM: To verify ABCD Parameter for SINGLE and CASCADED TWO PORT
NETWORK.

THEORY: A given two port network, with some network of complexity, can be built up
Conversely, a two-port network can be designed by simple two port structures as
building blocks.
The simplest possible connection is termed as Cascade or Tandem connection. Two port
networks are said to be cascaded if the output of first becomes the input of second.
CIRCUIT DIAGRAM:
Fig. 01
Fig. 02
PROCEDURE:
62. Connect the circuit as shown in figure 1. It means connect the variable voltage
supply too the input terminal of the network – I.
63. Vary the input voltage to 10V (V1) and measure open circuited output voltage
(V2). Note down the input current through current meter.
V2 = Output voltage
I1 = Input current (observed from current meter)
64. Now short the output terminals and measure Input current I1’.
V1’ = Input voltage
V2’ = 0
I1’ = Input current
I2’ = Output current
65. With these values calculate ABCD Parameters for single port network.
A= (I2=0) B= (V2=0) Ω
C= (I2=0) D= (V2=0)
67. Apply variable voltage to the input terminals and adjust voltage to 10V.
68. Now record
V1 = Input voltage
V2 = Output voltage
I1 = Input current
69. Interchange output and input terminals and measure the input voltage,
70. With these values calculate ABCD parameters for cascaded network (repeat
step 4).
OBSERVATION TABLE:
CALCULATION (ABCD parameters):
A= (I2=0) B= (V2=0) Ω
C= (I2=0) D= (V2=0)
RESULT:
PRECAUTIONS:
together.
Digital Electronics
LIST OF EXPERIMENT
(1)Study of operation of all Logic Gates.

(2)Study of binary adders
A. Half Adder
B. Full Adder
C.Two Bit Binary Parallel Adder.
(3)Study of 2 Bit Binary Subtractor (Half Subtractor).
(4)Study of Binary to Gray Code Conversion.
(5)Study of Gray to Binary Code Conversion.
(6)Study of Binary to Excess -3 Code Conversion.
(7)Study of Characteristics of various types of Flip-Flops.
(8)Study of Crystal Oscillator.
(9)Study of 4 bit Binary up down Counter.
(10)Study of Johnson Counter.

Experiment 1
Objective :
Study of operation of all Logic Gates
Equipments Needed
Components Quantity
5. IC 74136 2 input EX-OR Gate 1
6. IC 7404 NOT Gate. 1
Logic diagrams and IC Pin diagrams
Truth Tables:
Input 1 Input 2 Output Input1 Input2 Output

X Y O X Y O
0 0 0 0 0 1
0 1 0 0 1 1
1 0 0 1 0 1
1 1 1 1 1 0
AND Gate NAND Gate
Input1 Input2 Output Input1 Input2 Output

X Y O X Y O
0 0 0 0 0 1
0 1 1 0 1 0
1 0 1 1 0 0
1 1 1 1 1 0
OR Gate NOR Gate

Input1 Input2 Output
X Y O
0 0 0
0 1 1 Input Output
1 0 1 1 0
1 1 0 0 1
EX-OR Gate NOT Gate
Procedure
AND Gate
9. Connect +5 V to pin no. 14 of IC 7408 and connect ground to pin no.7. (refer IC pin diagram)
11. Connect output of AND Gate i.e pin no.3 to input of logic probe or 8 bits LED display.
NAND Gate
11. Connect output of NAND Gate i.e pin no.3 to input of logic probe or 8 bits LED display.

OR Gate
11. Connect output of OR Gate i.e pin no.3 to input of logic probe or 8 bits LED display.
NOR Gate
11. Connect output of NOR Gate i.e pin no.3 to input of logic probe or 8 bits LED display.
EX-OR Gate
NOT Gate
Experiment 2
Objective :
Study of binary adders
A. Half Adder
B. Full Adder
C. Two Bit Binary Parallel Adder
A. Half Adder
Equipments Needed
Components Quantity
Logic diagram : Truth Table
Input1 Input2 Carry Sum
X Y C S
0 0 0 0
0 1 0 1
1 0 0 1
1 1 1 0
Procedure
4. Connect +5V to pin no. 14 and ground to pin no.7 of IC 7408 and IC 74136. See
IC Pin diagram.
12. Observe outputs S and C on 8 bits LED display
B. FULL Adder
Equipments Needed
Components Quantity
2. IC 7432 2 input OR Gate 1

Logic diagram :
Truth Table :
Input Input Input Output

Carry Carry Sum
X Y Ci Co S
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1
Procedure
Same as above
C. 2 Bit Binary Parallel Adder

Equipments Needed
Components Quantity
Logic diagram :
Truth Table :
Input 1 Input 2 Input 1 Input 2 Carry Sum Sum
Sr. No. Bit 1 Bit 2 Bit 1 Bit 2
Al A0 B1 B0 C0 S1 S0
1 0 0 0 1 0 0 1
2 0 1 0 1 0 1 0
3 0 1 1 1 1 0 0
4 0 0 1 0 1 0 0
5 1 0 1 1 1 0 1
Procedure
5. Connect +5V to pin no. 14 and ground to pin no.7 of IC 7408 and IC 74136.
4. Connect 0 (0V) and 1 (+5 V) to inputs A1, A0, B1, B0 of adder shown as per Truth Table.
13. Observe outputs S1, S0 and C0 on 8 bits LED display

Full adder can be implemented using two half Adder. Adders are studied and Truth
Tables are verified.
Experiment 3
Objective :
Study of 2 Bit Binary Subtractor (Half Subtractor).
Equipments Needed
Components Quantity
Logic diagram :
Truth Table :
Input 1 Input 2 Borrow Difference

X Y B D
0 0 0 0
0 1 1 1
1 0 0 1
1 1 0 0
Procedure
4. Connect 0 (0V) and 1 (+5 V) to inputs X and Y of subtractor shown as per Truth Table.
Experiment 4
Objective :
Study of Binary to Gray Code Conversion
Equipments Needed
Components Quantity
Logic diagram :
Truth Table :
Binary Code Gray Code

B3 B2 B1 B0 G3 G2 G1 G0
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 0 0 0 1 1
0 0 1 1 0 0 1 0
0 1 0 0 0 1 1 0
0 1 0 1 0 1 1 1
0 1 1 0 0 1 0 1
0 1 1 1 0 1 0 0
1 0 0 0 1 1 0 0
1 0 0 1 1 1 0 1
1 0 1 0 1 1 1 1
1 0 1 1 1 1 1 0
1 1 0 0 1 0 1 0
1 1 0 1 1 0 1 1
1 1 1 0 1 0 0 1
1 1 1 1 1 0 0 0
Procedure
13. Observe outputs G3, G2, B1, G0,on 8 bits LED display

Binary to gray code conversion is studied. Most significant bit of binary as well as
gray code is same as far as 4 bit code is concerned.
Experiment 5
Objective :
Study of Gray to Binary Code Conversion
Equipments Needed
Components Quantity
Logic diagram :
Truth Table
Gray Code Binary Code

G3 G2 G1 G0 B3 B2 B1 B0
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 1 0 0 1 0
0 0 1 0 0 0 1 1
0 1 1 0 0 1 0 0
0 1 1 1 0 1 0 1
0 1 0 1 0 1 1 0
0 1 0 0 0 1 1 1
1 1 0 0 1 0 0 0
1 1 0 1 1 0 0 1
1 1 1 1 1 0 1 0
1 1 1 0 1 0 1 1
1 0 1 0 1 1 0 0
1 0 1 1 1 1 0 1
1 0 0 1 1 1 1 0
1 0 0 0 1 1 1 1
Procedure
4. Apply 0 (0V) and 1 (+5 V) to gray code inputs G3, G2, G1, G0 shown as per Truth Table.
6. Observe output on 8 bits LED display
7 Outputs can also be observed on oscilloscope
Experiment 6
Objective :
Study of Binary to Excess -3 Code Conversion
Equipments Needed
Components Quantity
Logic diagram :
Procedure
Truth Table:
B3 B2 B1 B0 E3 E2 El E0
0 0 0 0 0 0 1 1
0 0 0 1 0 1 0 0
0 0 1 0 0 1 0 1
0 0 1 1 0 1 1 0
0 1 0 0 0 1 1 1
0 1 0 1 1 0 0 0
0 1 1 0 1 0 0 1
0 1 1 1 1 0 1 0
1 0 0 0 1 0 1 1
1 0 0 1 1 1 0 0
1 0 1 0 1 1 0 1
1 0 1 1 1 1 1 0
1 1 0 0 1 1 1 1
Experiment 7
Objective :
Study of Characteristics of various types of Flip-Flops
Equipments Needed
Components Quantity
2. IC 7400 2 input NAND Gate 1
Logic diagram :
Truth Table
Clocked RS Flip Flop JK flip flop

Present Input Input Present
State 1 2 Next State state Input Input Next State
Q S R Q( t +1) Q J K Q ( t+ 1
0 0 0 0 0 0 0 0
0 0 1 0 0 0 1 0
0 1 0 1 0 1 0 1
0 1 1 In determinant 0 1 1 1
1 0 0 1 1 0 0 1
1 0 1 0 1 0 1 0
1 1 0 1 1 1 0 1
1 1 1 In determinant 1 1 1 0
T Flip Flop D Flip Flop

Present Present
state Input Next state state Input Next state
Q T Q ( t- 1) Q T Q ( t+ 1)
0 0 0 0 0 0
0 1 1 0 1 1
1 0 1 1 0 0
1 1 0 1 1 1
Procedure
3. Connect pulsar switch output (Y) to clock input CP of flip-flop
4. Connect input l or 0 to inputs of flip-flops as per Truth Table shown.
6. Press pulsar switch to get output
7 Observe outputs on 8 bits LED display
Observations
1. Indeterminate state of RS flip-flop is determined in JK flip-flop
2. Toggle state in JK flip-flop is eliminated in master slave flip-flop.
Experiment 8
Objective :
Study of Crystal Oscillator
Equipments Needed
Components Quantity
1. Resistance 330R 3
2. Crystal 1 MHz 1
3. Capacitor
0.01 µf 1
100 PF 1
4. IC 7404 Hex Inverter 1
Logic diagram
Procedure
2. Connect +5V to pin no. 14 and ground to pin no.7..
4. Measure the frequency
5. Compare with frequency of crystal

Crystal oscillator frequency depends solely on crystal dimensions and independent of
any other parameter
Experiment 9
Objective :
Study of 4 bit Binary up down Counter
Equipments Needed
Components Quantity
1. IC 74107 2 input JK Flip Flop. 2
2. IC 7400 2 input NAND Gate 2
Logic diagram :
Procedure
3. Connect +5V to the UP terminal of Counter and ground to DOWN terminal
4. Connect ground to clear input of flip flop.
5. Disconnect ground from clear input of flip flop.
6. Connect Y output of pulsar switch to clock input of flip-flop
13. Press pulsar switch 15 times and observe change in output. It will follow
sequence as shown in Truth Table for UP counter
14. Connect + 5V to DOWN terminal and ground to UP terminal
15. Repeat steps 6,7 and 8 to counter for count down
Truth Table :
Up Counter Down Counter
A4 A3 A2 A1 A4 A3 A2 Al
0 0 0 0 1 1 1 1
0 0 0 1 1 1 1 0
0 0 1 0 1 1 0 1
0 0 1 1 1 1 0 0
0 1 0 0 1 0 1 1
0 1 0 1 1 0 1 0
0 1 1 0 1 0 0 1
0 1 1 1 1 0 0 0
1 0 0 0 0 1 1 1
1 0 0 1 0 1 1 0
1 0 1 0 0 1 0 1
1 0 1 1 0 1 0 0
1 1 0 0 0 0 1 1
1 1 0 1 0 0 1 0
1 1 1 0 0 0 0 1
1 1 1 1 0 0 0
Experiment 10
Objective :
Study of Johnson Counter
Equipments Needed
Components Quantity
1. IC 7474 D Flip Flop. 2
2. IC 7408 2 input AND Gate 2
Logic diagram :
Truth Table
Sr. No. Flip flop

output A B C E AND Gate required for output
1. 0 0 0 0 A'E'
2. 1 0 0 0 AB'
3. 1 1 0 0 BC'
4. 1 1 1 0 CE'
5. 1 1 1 1 AE
6. 0 1 1 1 A'B
7. 0 0 1 1 B'C
8. 0 0 0 1 C'E
Procedure
3. Connect ground to clear input of flip flop.
4. Connect A output of pulsar switch to clock input of flip-flops.
8. Press pulsar switch 7 times and observe change in output. It will follow
sequence as shown in Truth Table for UP counter
10. AND and NOT Gates can be used to make product terms of last column and can
be observed on 8 bits LED display to know when a particular combination occurs.
Result :
Johnson counter gives 2k distinguishable states with k flip-flop
LIST OF EXPERIMENT
1 To study Operational amplifier as a Differential amplifier.

2. To study Operational amplifier as Inverting amplifier.
3. To study Operational amplifier as a Non-inverting amplifier.
4. To study the Active Low pass filter and to evaluate .
5. To study the Active High pass filter and to evaluate.
6. To study Wien Bridge Oscillator and effect on output frequency with
variation in RC combination.
7. To study the operation of Colpitt Oscillator.
8. Study of Monostable Multivibrator.
9. Study of BistableMultivibrator.
10. Study of Astable multivibrator
EXPERIMENT 1
Objective :
To study Operational amplifier as a Differential amplifier.
72. DC power supplies +12V and -12V from external source or ST2612 Analog Lab.
73. Variable DC supplies (+5V and +12V)
Circuit diagram :
Procedure :
Analog Lab.
1. Set the value of feedback resistance RF equals to 10K with the help of potentiometer observing
its value at socket’s ‘E’ and ‘F’.
2. Set the value of resistance ROM equals to 10 K with the help of potentiometer observing its value
at socket’s ‘H’ and ‘Vin2’.
3. Connect a patch cord between test point B & H; and F & G, Vin2 & ground to configure a
Differential Amplifier.
4. Switch ON the power supplies.
5. Connect the +5V supply at socket ‘Vin1’; that is inverting input for Op-amp. Keep this supply at
constant +5V.
6. Connect the Variable +12V supply at socket ‘A’; that is noninverting input for op-amp. Set the supply
voltage at 1V.
7. Calculate the value of output by using Eq.3;
Vout = Rf/R1 (Vinl- Vin2)
8. Where Vin1 is the input at socket ‘A’ noninverting terminal, and Vin2 is the input at socket ‘Vin1’ inverting
terminal.
9. Connect the multimeter’s probes at socket ‘Vout’ and Ground.
10. Note the output voltage and Verify the difference between calculated and measured output voltage.
11. Increase the input voltage at noninverting terminal (socket ‘A’) with the margin of 1V up to 10 V whilst
keeping input voltage at inverting terminal at constant +5V.
12. Repeat the above steps from 7 to 10.
 The Differential output of two AC signal can be observe

6. If the inputs which are given in the input terminals are at same frequency and have 180 phase shift.
7. Then the difference between both signal will appear at the output
8. It is difficult to get the inputs which have same frequency, thus this bridges are used at measuring the
differential voltage at AC Bridges.
Note :
4. Try to make given circuits on the bread board strip given on the Analog Board to practice and understand
its connections.
Observation table :
S. No. VIN1 VIN2 VOUT VOUT

(Calculated) (Measured)
Conclusion : The calculated and measured output are almost the same.
EXPERIMENT 2
Objective :
To study Operational amplifier as Inverting amplifier.
22. Oscilloscope
Circuit diagram :
Procedure :
Analog Lab.
1. Set the value of feedback resistance RF equals to 10K with the help of potentiometer R F observing its value at
sockets ‘E’ and ‘F’.
2. Set the value of resistance R OM equals to 5 K with the help of potentiometer R OM observing its value at socket
‘H’ and ‘Vin2’.
3. Connect a patch cord between sockets ‘F’ & ‘G’; and ‘Vin2’ & ground to configure the Inverting amplifier.
4. Connect Function generator’s probe at the socket ‘Vinl’; to apply 1Vpp, 1 KHz, sine wave signal at input.
Vout = - (Rf / R1) Vin.
8. Note the output voltage and Verify the difference between calculated and measured output voltage
9. Note the phase shift between the output and input waveform.
Note : To see the phase shift between input and output signal its necessary to connect both, input and output
signal at the oscilloscope channels.
Observation table :
Phase
S. VIN RF RF / VOUT VOUT
shift
No. R1 (Measured)
(Calculated) (φ)
Conclusion :
4. The Phase shift between input and output signal is 180
EXPERIMENT 3
Objective :
To study Operational amplifier as a Non-inverting amplifier.
17. Oscilloscope
Circuit diagram :
Procedure :
Analog Lab.
1. Set the value of feedback resistance RF equals to 10K with the help of potentiometer RF
observing its value at sockets ‘E’ and ‘F’.
2. Connect a patch cord between sockets ‘F’ & ‘G’; and ‘Vin1’ & ground to configure the
Noninverting amplifier.
3. Connect Function generator’s probe at the socket ‘H’; to apply 1Vpp, 1 KHz, sine wave signal at
noninverting input terminal.
Vout = (1+Rf / R1) Vin
7. Note the output voltage and Verify the difference between calculated and
measured output voltage
8. Note the phase shift between the output and input wavefrom.
Note : To see the phase shift between input and output signal its necessary to connect both input and output signal
at the oscilloscope channels.
Observation table :
Phase
S. VIN RF 1+(RF VOUT VOUT
shift
No. /R1) (Measured)
(Calculated) (φ)
Conclusion :
2. The Phase shift between input and output signal is 0.
EXPERIMENT 4
Object :
To study the Active Low pass filter and to evaluate :
 High cutoff frequency of Low pass filter.
 Pass band gain of Low pass filter.
 Plot the frequency response of Low pass filter.
Apparatus Required :
2. DC power supplies +12V, 12V from external source or ST2612 Analog Lab.
3. Function generator or ST2612 Analog Lab.
4. Oscilloscope
5. Digital Multimeter
6. 2 mm patch cords.
Circuit Diagram :
Circuit used to study Active Low pass filter shown in Fig 3.
Procedure :
1. Connect Ohmmeter between Test point Vin and Test point 1. Adjust resistance value to 1.59K by varying the
potentiometer 22K of Low pass filter to set the high cutoff frequency (fH) at 10K.
2. Connect +12V and 12V DC power supplies at their indicated position from external source or ST2612
Analog Lab.
3. Switch ON the power supply.
4. Connect a sinusoidal signal of amplitude 1V (p-p) of frequency 1KHz to Vin of Low pass filter from external
source or ST2612 Analog Lab.
5. Observe output on oscilloscope by connecting Test point Vout to oscilloscope.
6. Increase the frequency of input signal step by step and observe the effect on output Vout on oscilloscope.
7. Tabulate values of Vout, gain, gain (db) at different values of input frequency shown in observation Table.
Observation Table :
Input
Sr. Gain(db) = 20
frequency Vout |Vout / Vin| = gain
No. Log |vout / vin|
(Hz)
1 500
2 1K
3 5K
4 10 K (fH)
5 15 K
6 20 K
7 30 K
8. Plot the frequency response of low pass filter using the data obtained at different input frequencies.
9. Perform the same procedure at different Cutoff frequencies as shown below:
fH high cutoff
Resistance () Capacitance (uF)
frequency (Hz)
800 0.01 20K
1.59 K 0.01 10K
15.9 K 0.01 1K
Theoretical Calculations :
Calculate all the following values
1. Pass band gain of Low pass filter AF = 1 + RF / R1
2. Pass band gain (db) = 20 log |Vout / Vin|
3. 3 db frequency fH = 1/2RC
4. Gain at 3 db frequency fH = 0.707 * AF
5. Gain (db) at 3 db frequency fH = 20 log |Vout / Vin| where
Vout = (2)1/2 * Vin
6. Roll off rate = 20db/decade
Results :
Theoretical Practical
Pass band gain(Af)
Pass band gain(Af) in db
3db frequency fH
Gain at 3db frequency (fH ) in db

EXPERIMENT 5
Object :
To study the Active High pass filter and to evaluate :
1. Low cutoff frequency of Low pass filter.
2. Pass band gain of High pass filter.
3. Plot the frequency response of High pass filter.
4. Oscilloscope
Circuit Diagram :
Circuit used to study Active High pass filter shown in Fig 4.
Procedure :
1. Connect Ohmmeter between Vin and Testpoint 3. Adjust resistance value to 15.9K by varying the
potentiometer 22K of High pass filter to set the Low cutoff frequency (fL) at 1K.
Analog Lab.
4. Connect a sinusoidal signal of amplitude 1V (p-p) of frequency
100 Hz to the Test point Vin of high pass filter from external source or ST2612 Analog Lab.
5. Observe output on oscilloscope by connecting Testpoint Vout to oscilloscope.
7. Tabulate different values of Vout, gain, gain (db) at different values of input frequency shown in observation
Table.
Observation Table :
Input
Sr. Gain(db) = 20
(Hz)
1 100
2 200
3 500
4 1K(fL)
5 5K
6 10 K
7 15 K
8 20 K
8. Plot the frequency response of high pass filter using the data obtained at different input frequencies.
Resistance () Capacitance (uF) 3 db frequency (Hz)
800 0.01 20K
1.59 K 0.01 10K
15.9 K 0.01 1K
23. Low cutoff frequency fL = 1/2RC
24. Gain at Low cutoff frequency fL = 0.707 * AF
25. Gain (db) at Low cutoff frequency fH = 20 log |Vout / Vin| where
Vout = (2)1/2 * Vin
Results :
Pass band gain(Af)
Low cutoff frequency (fL)
Gain at 3db frequency (fL ) in db

EXPERIMENT 6
Objective :
To study Wien Bridge Oscillator and effect on output frequency with variation in RC combination.
2. DC power supplies -12V, +12V from external source or ST2612 Analog Lab.
3. 2mm patch cords.
Circuit diagram :
Circuit used to study Wien Bridge Oscillator is shown in Fig 2.
Procedure :
 To study Wien Bridge oscillator proceed as follows :
1. Connect +12V,-12V dc power supplies at their indicated position from external source or ST2612 Analog
Lab.
2. Connect a 2mm patch cord between test point I and H.
4. Vary Rf Pot to make gain (Rf / Rl) greater than 2.
5. Record the value of output frequency at test point G.
6. Compare measured frequency with the theoretically calculated value.
7. Vary gain Pot of 470K to adjust gain of the amplifier in case of clipped waveform.
8. Switch OFF the power supply.
9. Connect a 2 mm patch cord between test points A and B, D and E.
10. Repeat the above steps from step 3 to 8.
11. Switch OFF the power supply
12. Connect a 2 mm patch cord between test points B and C, E and F.
Experiment 7
Object: To study the operation of Colpitt Oscillator.
Apparatus required:
1. Analog board AB-67.
2. DC power supplies +12V from external source or ST-2612 Analog Lab.
3. Oscilloscope.
4. 2mm Patch cords.
Circuit diagram:
Circuit used to study the operation of Colpitt Oscillator is as shown in Fig.2.
Procedure:
 To study Colpitt oscillator proceed as follows :-
1. Connect +12V dc power supplies at their indicated position from external source or ST-2612 Analog Lab.
2. Connect a patch cord between points a and b and another patch chord between points d and g1.
4. Connect oscilloscope between points f and g2 on AB–67 board.
5. Record the value of output frequency on oscilloscope.
6. Calculate the resonant frequency using equation 1.
7. Compare measured frequency with the theoretically calculated value.
8. Switch off the supply.
9. Remove the patch chord connected between points a and b and connect it between points a and c.
10. Remove the patch chord connected between points d and g1 and connect it between points e and g2.
11. Follow the procedure from point 4 to 8.
12. Connect +5V supply instead of +12V supply and follow the procedure from point 2 to point 11.
Result:
When patch chord connected across C1 and C2
Practically calculated Output frequency(on CRO): …………………….
Theoretically calculated values
Cequ : ……………………………………... ( use eq.2 )
Resonant frequency (fr) : ………………….. ( use eq.1 )
Output voltage amplitude : …………………… Vp-p
When patch chord connected across C3 and C4
Practically calculated Output frequency(on CRO): …………………….
Theoretically calculated values
Cequ : ……………………………………... ( use eq.2 )
Resonant frequency (fr) : ………………….. ( use eq.1 )
Output voltage amplitude : …………………… Vp-p
Record above results separately for +12V input voltage and +5V input voltage and note down the .
Experiment 9
Objective :
Study of Monostable Multivibrator
Equipments Needed :
Component Quantity
1. Resistance
1K2
15 2
47.5 1
2. Transistor 2N3904 2
3. Switch 1p-2w 1
4. Capacitor
100 μF 1
1μF 1
Procedure :
1. Make connections as shown in Diagram
2. Connect indicated power supply from the DC power supply block.
3. Open switch SW 1 .
4. Switch on the trainer.
5. Connect terminal 4 to CRO output will be 0 V.
6. Close switch to trigger multivibrator.
7. Output will be + 5V for time period T= 0.69C 1R1 Sec and low afterwards.
Experiment 09
Objective :
Study of BistableMultivibrator
Equipments Needed
Component Quantity
1. Resistance
1K2
15 K2
47.5 K2
3. Switch 1p-2w 1
4. Capacitor 1μFD 2
Circuit diagram :
Figure
Procedure :
1. Make connections as shown in diagram
2. Connect indicated Power supply from the DC power supply block.
4. Trigger terminal T1 using switch SW 1.
5. Connect terminal 4 to CRO output will be + 5V.
6. Output will remain same till next trigger is given to T2.
7. Trigger terminal T2 using switch SW1
8. Output will be 0V.
9. Output will remain same till next trigger is given to T1.
Experiment 10
Objective :
Study of Astable multivibrator
Equipments Needed :
Component Quantity
1. Resistance
1K2
10K2
Circuit diagram :
Figure
Procedure :
1. Make Connections as shown in diagram.
2. Connect indicated power supply from the DC power supply block.
4. Connect terminal 4 to CRO.
5. Output will be 5 Vp-p.
6. Total time period of output wave will be 0.69 (R1C1+R2C2).
MANUAL
OF
ANALOG COMMUNICATION

Experiment 1
AMPLITUDE MODULATION &DEMODULATION
AIM: To study the function of Amplitude Modulation & Demodulation (under modulation,
perfect modulation & over modulation) and also to calculated the modulation index.
APPARATUS:
1. Amplitude Modulation & Demodulation trainer kit.

2. C.R.O (20MHz)
3. Function generator (1MHz).
4. Connecting cords & probes.
CIRCUIT DIAGRAM:
Amplitude modulation circuit diagram
Demodulation circuit diagram
THEORY:
Amplitude modulation can be produced by a circuit where the output is product of
two input signals. Multiplication produces sum and difference frequencies and thus the side
frequencies of the AM wave. Two general methods exist for achieving this multiplication, one
involves a linear relation between voltage and current in a device and the second uses a linear
device. A linear form of modulation of modulation causes a current I, of one frequency to pass
through an impedance Z, whose magnitude varies at a second frequency. The voltage across
this varying impedance is then given by
E = I sinω1t * z sinω2t
The above equation is the output is a result of multiplication of two frequencies. If
one of them is carrier frequency and the other is the modulating frequency the result is an
AM waveform.
The circuit diagram of the amplitude modulation, the carrier is fed to the transistor Q1 of its
base. This produces a collector current in Q1 of carrier frequency. The impedance in the
collector circuit of Q1 is decided in the transistor Q2. Modulating signal is fed to the base Q2
which changes the impedance offered by Q2 at the modulation frequency output is taken
through a transformer coupling. When the modulating is zero Q2 offers a
fixed impedance in the collector circuit of Q2, so that the output is a constant unmodulated
carrier. As the modulating signal is applied to Q2 the impedance changes and the amplitude of
carrier at output also changes in accordance with the equ(5). Thus an amplitude modulated
carrier is obtained at the output. In a communication system a high frequency carrier is
modulated by the low frequency signal. The modulated carrier is transmitted by the transmitter
antenna. At the receiver we have to recover the information
back from the modulated carrier. The process of separation of signal from the carrier is called
demodulation or detection. the demodulation circuit diagram is a linear diode detector. In this
circuit the linear portion of dynamic characteristics of diode is used and hence the circuit is a
linear detector. It consists of a half wave rectifier followed by a capacitor input filter. Input to
the circuit is an AM wave with a high frequency carrier and
a low frequency envelope corresponding to the signal. The diode cuts-off the negative going
portion of the AM wave. Capacitor ‘C’ charges up to the peak of the carrier cycle through the
low resistance rd and then during negative half cycle tries to discharge through relatively high
resistance RL. Capacitor value is so chosen that this discharge is very small in time between
carrier half cycles. Hence the capacitor voltage tends to follow the envelope of the carrier and
the voltage available across RL is simply the
modulation envelope superimposed on a constant level. A dc level in the output comes because
the current through diode flows in the form of pulses occurring at the peak of each carrier
cycle. When the input to detector circuit is a AM waveform then the one of the component in
VR cannot be assumed to be constant all the time. Actually it is constant over a few cycles of
carrier in which time it is assumed that modulating signal being low frequency would not have
changed appreciably. Due to this reason the measurement of detection efficiency can be done
on an un modulated carrier because VR would be expected to be constant.
PROCEDURE:-
1. The circuit should be connected first, only then the power supply should be switched on.
2. Measure the frequency & amplitude (p-p) of the fixed carrier signal present on the kit.
3. Connect the circuit as per the given circuit diagram.
4. Apply fixed frequency carrier signal to carrier input terminals.
5. Apply modulating signal from function generator of 1VP-P of 500Hz.
6. Note down and trace the modulated signal envelop on the CRO screen.
7.Find the modulation index by measuring Vmax and Vmin from the modulated (detected/
traced) envelope.
M=(Vmax –Vmin)/(Vmax+Vmin)
8. Repeat the steps 5,6 & 7 by changing the frequency or/& amplitude of the modulating signal
so as to observe over modulation, under modulating and perfect modulation.
9. For demodulation, apply the modulated signal (A.M) as an input to the demodulator and
verify the demodulated output with respect to the applied modulating signals and their
respective outputs.
Experiment 2
FREQUENCY MODULATION & DEMODULATION
AIM: To study the functioning of frequency modulation & demodulation and to calculate the
modulation index.
APPARATUS:
1. Frequency modulation & demodulation trainer kit.
2. C.R.O (20MHz)
3. Function generator (1MHz).
4. Connecting chords & probes.
CIRCUIT DIAGRAM:
FREQUENCY MODULATION CIRCUIT DIAGRAM:
FREQUENCY DEMODULATION CIRCUIT DIAGRAM:
THEORY:
This kit consists of wired circuitry of:
1. AF generator.
2. Regulated power supply
3. Modulator.
4. Demodulator.
1.AF Generator:
This is an op-amp placed wein bridge oscillator. A FET input quad Op-Amp (ICTL084) is used
here to generate low frequency signals of 500 Hz and 5KHz to use as modulating signal. In this
experiment, a switch is provided to change the frequency. Required amplification is provided
to avoid loading effect.
2. Regulated power supply:
This consists of bridge rectifier, capacitor filters and three terminal regulators to provide
required dc
voltages in the circuit i.e. +15 V, -15 V, +5V .
3. Modulator:
This has been developed using XR-2206 integrated circuit. The IC XR-2206 is a monolithic
Function generator; the output waveforms can be both amplitude and frequency modulated by
an external voltage. Frequency of operation can be selected externally over a range of 0.01
MHz. The circuit is ideally suited for communications, instrumentations and function generator
applications requiring sinusoidal tone,
AM, FM or FSK generation. In this experiment, IC XC-2206 is connected to generate sine
wave, which is used as a carrier signal. The amplitude of carrier signal is 5vPP of 100 KHz
frequencies.
4. Demodulator:
This had been developed using LM4565 integrated circuit. The IC LM565 is a general-purpose
phase locked loop containing a stable, highly linear voltage controlled oscillator for low
distortion FM demodulation.
The VCO free running frequency f0 is adjusted to the center frequency of input frequency
modulated signal i.e. carrier frequency which is of 100 KHz. When FM signal is connected to
the demodulator input,the deviation in the input signal (FM signal) frequency which creates a
DC error voltage at output of the phase comparator which is proportional to the change of
frequency δf. This error voltage pulls the VCO to
the new point. This error voltage will be the demodulated version of the frequency modulated
input signal.
PROCEDURE:
1. Switch on the power supply of the kit (without making any connections).
2. Measure the frequency of the carrier signal at the FM output terminal with input terminals
open and plot
the same on graph.
4. Apply the modulating signal of 500HZ with 1Vp-p.
5. Trace the modulated wave on the C.R.O & plot the same on graph.
6. Find the modulation index by measuring minimum and maximum frequency deviations from
the carrier
frequency using the CRO.
modulating signal frequency
maximumFrequency deviation
7. Repeat the steps 5& 6 by changing the amplitude and /or frequency of the modulating
Signal.
8. For demodulation apply the modulated signal as an input to demodulator circuit and
compare the
demodulated signal with the input modulating signal & also draw the same on the graph.
OUTPUT WAVEFORMS
EXPERIMENT-3
AIM: To study . DSB-SC Generator.
APPARATUS:
1. DSB-SC trainer kit
2. C.R.O (20MHz)
3. Connecting cords and probes
4. Function generator (1MHz)
CIRCUIT DIAGRAM:
THEORY:
1. RF Generator:
Colpitts oscillator using FET is used here to generate RF signal of approximately 100 KHz
Frequency to use as carrier signal in this experiment. Adjustments for Amplitude and
Frequency are provided in panel for ease of operation.
2. AF Generator:
Low Frequency signal of approximately 5KHz is generated using OP-AMP based wein bridge
oscillator. IC TL 084 is used as an active component, TL 084 is FET input general purpose
quad OP-AMP integrated circuit. One of the OP-AMP has been used as amplifier to improve
signal level. Facility is provided to change output voltage.
3. Regulated Power Supply:
This consists of bridge rectifier, capacitor filters and three terminal regulators to provide
required dc voltage in the circuit i.e. +12v, -8v @ 150 ma each.
4. Modulator:
The IC MC 1496 is used as Modulator in this experiment. MC 1496 is a monolithic integrated
circuit balanced modulator/Demodulator, is versatile and can be used up to 200 Mhz.
Multiplier: A balanced modulator is essentially a multiplier. The output of the MC 1496
balanced modulator is proportional to the product of the two input signals. If you apply the
same sinusoidal signal to both inputs of a ballooned modulator, the output will be the square of
the input signal AM-DSB/SC: If you use two sinusoidal signals with deferent frequencies at
the two inputs of a balanced modulator (multiplier) you can produce AMDSB/ SC modulation.
This is generally accomplished using a high- frequency “carrier” sinusoid and a lower
frequency “modulation” waveform (such as an audio signal from microphone). The figure 1.1
is a plot of a DSB-SC waveform, this figure is the graph of a 100KHz and a 5 KHz sinusoid
multiplied together. Figure 1.2shows the circuit that you will use for this experiment using MC
1496 balanced modulator/demodulator.
PROCEDURE:-
I-Generation of DSB-SC
1. For the same circuit apply the modulating signal(AF) frequency in between 1Khz to 5Khz
having 0.4 VP-P and a carrier signal(RF) of 100KHz having
a 0.1 VP-P .
2. Adjust the RF carrier null potentiometer to observe a DSB-SC waveform at
the output terminal on CRO and plot the same.
3. Repeat the above process by varying the amplitude and frequency of AF but RF maintained
constant.
OUT PUT WAVE
EXPERIMENT 4
Aim
Single sideband AM reception
Procedure
1. Ensure at the following initial condition exist on the board.

a) Audio i/p select switch INT position;
b) MODE switch in DSB position
c) O/p amplifier’s gain preset in fully clockwise position.
d) SPEAKER switches in OFF position.
2. Turn off power to the ST2201board
3. Turn off audio oscillator block’s amplitude preset to its fully clockwise (MAX) position,
and examine the bloke’s o/p (t.p.14) on an oscilloscope.

This is the audio frequency sine wave which will be as our modulating signal. Note that the
sine wave’s frequency can be adjusted from about 300 Hz to approximately 3.4 kHz, by
adjusting the audio oscillator’s frequency preset.

Note also that the amplitude of this audio modulating signal can be reduced to zero.
4. Monitor, in turn, the two i/p to the BALANCED MODULAR AND BPF ckt 1 block, at
t.p.1 and t.p.9 note that:
a) The signal at t.p.1 is the audio frequency sine wave from the audio oscillator block.
This is the modulating i/p to our double side band modulator.
b) Test point 9 carries a sine wave of frequency of 1 MHz and amplitude 12mv, pk/pk
approx. this is the carrier i/p to our double side band modulator.
5. Next examine the o/p of the balanced modulator and BPF ckt 1 block (at t.p.3), together
with the modulating signal at t.p.1 trig ger the oscilloscope on the t.p.1 signal.
Check that the waveforms as shown in fig.24

The o/p from the BM & BPF ckt 1 block (t.p.3) is a double sideband. AM waveform, which
has been formed by amplitude modulating 1 MHz carrier sine wave with the audio frequency
sine wave from the audio oscillator?

The frequency spectrum of this AM waveform is as shown below in fig 25, where fm is the
frequency of the audio modulating signal:
6. To determine the depth of modulation, measure the maximum amplitude (Vmax) and the
min amplitude (Vmin) of the AM waveform at t.p.3, and use the following formula:

%modulation= (Vmax-Vmin)/ (Vmax=Vmin)
Where, Vmax & Vmin are the maximum & minimum amplitude shown in fig. 24.
7. Now vary the amplitude and frequency of the audio frequency sine wave, by adjusting the
amplitudes and frequency present in the audio oscillator block. Note the effect that varying
each preset has on the amplitude modulated waveform. The amplitude and frequency
amplitude two side band can be reduced to zero by reducing the amplitude of the modulating
audio signal to zero. Do this by turning the amplitude preset to its min position, and note that
the signal at t.p.3 becomes and unmodulated sine wave of frequency 1 MHz, indicating that
only the carrier component now remains same. Return the amplitude preset to its max position.
Now turn the balance preset in the BM & BPF ckt1 block, until the signal at t.p.3 is as shown
in fig26
The balance preset varies the amount of the 1 MHz carrier component which is passed from the
modulator’s o/p.
By adjusting the preset until the peaks of the waveform (A, B, C and so on) has the same
amplitude, we are removing the carrier component altogether.
We say that carrier has been balanced out (suppressed) to leave only the two side bands.
Note that once the carrier has been vanished out the amplitude of the t.p.3’s waveform should
be zero at min points X, Y etc .if this is not the case; it is because one of the two side bands is
being amplified more than the other. To remove this problem, band pass filter in the BM &
BPF ckt 1 block must be adjusted so that it passes both side bands equally. This is achieved by
carefully trimming transformer T1, until the waveforms amplitude is as close to zero as
possible at the min points.
The waveform at t.p.3 is known as D.S.B.-S.C. waveform, and its frequency spectrum is as
shown in fig. 27
Note that now only the two sidebands remain, the carrier component has been removed.

8. Change the amplitude and frequency of the modulating audio signal (by adjusting the audio
oscillator block’s amplitude & frequency presets), and note the effect that these changes on the
DSBSC waveform. The amplitude of the two sidebands can be reduced to zero by reducing the
amplitude of the modulating audio signal to zero. Do these by turning the amplitude present to
its min position, and note that the monitored signal becomes DC levels, indicating that there
are now no frequency components present. Return the amplitude preset to its maximum
position.
9. Examine the o/p from the o/p amplifier block (t.p.13), together with the audio modulating
signal (t.p.1), triggering the scope with the audio modulating signal. Note that the DSBSC
waveform appears amplified slightly, at t.p.13. as we will see later, it is the o/p amplifier’s o/p
signal which will be transmitted to the receiver
10. By using the optional audio i/p modules the human voice can be used as the
modulating signal, instead of using ST2201’s audio oscillator block.

If you have an audio in/p module, connect the module o/p to the external audio i/p on the
ST2201 board, and put the audio i/p select switch in the EXT position.

The i/p signal to the audio i/p module may be taken from an external microphone or from a
cassette recorder, by choosing the appropriate switch setting on the module

EXPERIMENT 5
Double sideband AM reception
Aim. Double sideband AM reception
Ensure that the following initial condition exist on the ST2201 board.
a) Audio oscillator amplitude preset in fully clock wise position.
b) Audio i/p select switch in INT position.
c) Balance preset in BM & BPF ckt 1 block, fully clock wise position.
d) MODE switch in DSB position.
e) O/p amplifier gains preset in fully counter clock wise position.
f) TX o/p select switch in INT position.
g) Audio amplifiers volume preset in fully counter clock wise position.
h) Speaker switches in on position.
i) On-board antenna in vertical position, and fully extended.
3. Ensure that the following initial condition exist on the ST2202 board:
a) RX i/p selects switch in ANT position.
b) RF amplifiers tuned ckt selects switch in INT position.
c) RF amplifier’s gain preset in fully clockwise position.
d) AGC switch in IN position.
e) Detector switch in diode position.
f) Audio amplifier’s volume preset in fully counter clock wise position.
g) Speaker switches in on position.
h) Beat frequency oscillator switch in OFF position.
i) On-board antenna in vertical position, and fully extended.
4. Turn on power to the modules.
5. On the ST2202 module, slowly turn the audio amplifiers volume preset clock wise, until
sound can be heard from on-board loudspeaker.

Next, turn the venire tuning dial until a broadcast station can be heard clearly and adjust the
volume control to a comfortable level.

Note: - if desired, headphones (supplied with the module) may be used instead of the on-board
loudspeaker. To use the headphones, simply plugged the headphone jack in to the audio
amplifiers block headphone shocked and adjust controlled blocks volume preset.

6. The first stage, or “front end” of the ST2202, AM receiver is the RF amplifier stage. This is
a wide bandwidth tuned amplifier stages, which is tuned in to the wanted station by means of
the tuning dial.

Once it has been tuned in to the wanted station, the RF amplifier, having little selectivity, will
not only amplify, but also those frequencies which are closed to the wanted frequencies. As we
will see later, these nearby frequency will be removed by subsequent
stage of the receiver, to leave only the wanted signal. Examine the envelop of the signal at RF
amplifiers o/p (at t.p.12), with an a.c. coupled oscilloscope channel. Note that:
a) The amplifiers o/p signal is very small in amplitude (a few tens of mv at the most).
This is because one stage of amplification is not sufficient to bring the signals amplitude up to
a responsible level.
b) Only a very small amount of amplitude modulation can be detected, if any. This is
because there are many unwanted frequencies getting through to the amplifier o/p, which tend
to “drown out” the wanted AM signal.
You may notice that the waveform itself drifts up and down on scope display, indicating that
the waveforms average level in changing. This is due to the operation of the AGC ckt, which
will be explained later.
7. The next stage of the receiver mixer stage, which mixes the RF amplifier’s o/p with the o/p
of a local oscillator. The frequency of the local oscillator is also tuned by means of the tuning
diode, and is arranged so that its frequency is always 455khz above the signals frequency that
RF amplifier is tuned to. This fixed frequency difference is always present, irrespective of the
position of the tuning diode, and is arranged so that its frequency is always 455 kHz above the
signal frequency that the RF amplifier is tuned to, and is known as intermediate frequency (IF
for short) this frequency relationship is shown below, for some arbitrary position of the tuning
dial.

Examine the o/p of the local oscillator block, and checked that its frequency various as the
tuning dial is turned. Retime the receiver to the radio station.

8. The operation of the mixer stage is basically to shift the wanted signal down to the IF
frequency, irrespective of the position of the tuning dial. This is achieved in two stages.
a) By mixing the local oscillator o/p sine wave with the o/p from there RF amplifier
block. This produces three frequency components:
The local oscillator frequency = (fsig+ IF)
The sum of the original two frequencies, fsum= (2fsig+ IF)
The difference between two original frequencies, fdif = (fsig+IF-fsig) = IF
These three frequencies component are shown in fig 29

b) By strongly attenuating all components except the difference frequency, IF this is
done by putting a narrow bandwidth BPF on the mixer o/p.
The end result of this process is that the carrier frequency of the selected AM station is shifted
down to 455 kHz, and the side band of the AM signal is now either side of 455 kHz.
9. Note that, since the mixer BPF is not highly selected, it will not completely remove the
local oscillator and sum freq. component from the mixer’s o/p. this is the case particularly with
the local oscillator component, which is much larger in amplitude then the sum and difference
component.
Examine the o/p of the mixer block (t.p.20) with an ac coupled oscilloscope channel, and note
that the main freq. component present changes at tuning dial are turned. This is the local
oscillator component, which still dominates the mixer o/p, in spite of being attenuated by the
mixer’s BPF.
10. Tuned in to a strong broadcast station again and note that the monitored signal
shows little, if any, sign modulation. This is because the wanted component, which is now at
the IF freq. of 455 kHz, is still very small in comparison to the local oscillator component.
What we need to do now is to preferentially amplify freq. around 455 kHz, without amplifying
the higher freq. local oscillator and sum components. This selective is achieved by using two
IF amplifier stages, IF amplifier 1 and IF amplifier 2, which are designed to amplify strongly
narrowband of freq. around 455 kHz, without amplifying freq. on either side of this
narrowband.

Examine the o/p of the IF amplifier at t.p.24 with in ac coupled oscilloscope channel, and note
that:
a) The overall amplitude of the signal is much larger that signal amplitude at the mixer
o/p, indicating that voltage amplification has occurred.
b) The dominant component of the signal is now at 455 kHz, irrespective of any
particular station you have tuned in to. This implies that the wanted signal, at the IF freq., has
been amplified to a level where it dominates over the unwanted components.
c) Envelop of the signals is modulated and in amplitude, according to the sound
information being transmitted by the station you tuned in to.
11. Examine the o/p of the IF amplifier 2t.p.28 within ac coupled oscilloscope
channel, noting that the amplitude of the signal has been further amplified by this second IF
amplifier stage.
IF amplifier 2 has once again preferentially amplified signal around the freq. (455 kHz), so
that:
a) The unwanted local oscillator and sum components from the mixer are now so small
in comparison, that they can be ignored totally.
b) Freq. closed to IF, which are due to station close to the wanted station, are also
strongly attenuated.
The resulting signal at the o/p of the IF amplifier 2 t.p28 is therefore composed almost entirely
of 455 kHz carrier, and the AM sidebands either sides of it carrying the wanted audio
information.
12. The next step is to extract this audio information from the amplitude variation
of the signal at the o/p of IF amplifier 2. This operation is performed by the diode detector
block, whose o/p follows the changes in the amplitude of the signal at its input.
To see how this works, examine the o/p of the diode detector block t.p.31, together with the o/p
from. IF freq amplifier2 at t.p. 28.
Note that the signal at the diode detector’s output:

a) Follows the amplitude variations of the incoming signal as required.
b) Contains some ripple at the IF freq. of 455khz, and
c) The signal has a positive DC offset, equal to half the average peak to peak amplitude
of the incoming signal. We will see how we make use of this offset later on, when we look at
Automatic Gain Control (AGC).
13. The final stage of the receiver is the audio amplifier bock contains a simple
LPF which passes only audio freq. and removes the high-freq. ripple from the diode detector
o/p signal. This filtered audio signal is applied to the i/p of an audio power amplifier, which
drives on board loudspeaker .The final result is the sound you are listening to.
The audio signal which drives the loudspeaker can be monitored at t.p.39 compare this signal
with that the diode detector o/p(t.p.31) and note how the audio amplifier block LPF has cleaned
up the audio signal.
14. Now that we have examined the basic principle of operation of the ST2202
receiver for the reception and demodulation of AM broadcast signal, we will try receiving the
AM signal from ST2201 transmitter.
On the ST2201 module examine the o/p signal of transmitter t.p.13 together with the audio
modulating signal t.p.1, triggering the scope with signal.
15. On the ST2201 module turned the volume preset until you can hear the tone of
the audio oscillator o/p signal from the loudspeaker on the board.
16. On the ST2201/ST2202 receiver, adjust the volume preset so that the receiver
‘s o/p can be clearly heard then adjust the receiver’s tuning dial until the tone generated at the
transmitter is also clearly audible at the receiver.
The ST2201/ST2202 receiver is now tuned into AM signal generated by the ST2201
transmitter. Briefly check that the waveforms, at the o/p of the following receiver block,
Receiver block, are as expected:
RF amplifier t.p.12
Mixer t.p.20
IF amplifier 1 t.p. 24
IF amplifier2 t.p.28
Diode detector t.p.31
Audio amplifier t.p.39
17. By using the optional audio i/p module ST2108, the human voice can be used
as transmitter’s audio modulating signal, instead of using ST2201.
The i/p signal to the audio i/p module may be taken from an external microphone or from a
cassette recorder by choosing the appropriate switch setting the module.

EXPERIMENT 6
PHASE LOCKED LOOP
AIM: To study the characteristics of PLL.
APPARATUS:
1. PLL Trainer Kit
2. C R O (20MHz)
PLL BLOCK DIAGRAM:

PLL CIRCUIT DIAGRAM:

THEORY:
Phase Locked Loop is a versatile electronic servo system that compares the phase and
frequency of a given signal with an internally generated reference signal. It is used in various
applications like frequency multiplication, FM detector, AM modulator & De modulator and
FSK etc.
Free running frequency (f0):
When there is no input signal applied to pin no:2 of PLL, it is in free running mode and the free
running
frequency is determined by the circuit elements Rt and Ct and is given by
F0 = 0.3/(RtCt) where Rt is the timing resistor
Ct is the timing capacitor
Lock range of PLL (fL):
Lock range of PLL is in the range of frequencies in which PLL will remain lock, and this is
given by
fL = ± 8f0 /VCC Where f0 is the free running frequency
VCC = VCC –(- VCC)
= 2 VCC
PROCEDURE:
Free running frequency:
1. Switch on the trainer and measure the output of the regulated power supplies i.e., +12V and
±5V
2. Observe the output of the square wave generator-using oscilloscope and measure the
frequency range.
The frequency range should be around 1KHz to 10KHz.
3. Calculate the free running frequency range of the circuit for different values of timing
capacitor and
Rt.
4. Connect 0.1μF capacitor (CC) to the circuit and open the loop by removing short between
pin 4 and 5 .
Measure the minimum and maximum free running frequencies obtainable at the output of the
PLL (Pin
4)by varying the pot. Compare your results with your calculation from step 3 (theoretical
value).
Simultaneously you can observe the output signal using CRO.
EXPERIMENT 7
SYNCHRONOUS DETECTOR
AIM :- To generate SSB using phase method and demodulation of SSB signal using
Synchronous detector.
APPARATUS:- 1.SSBtrainer kit

2. C.R.O (20MHz)
3. Function Generator (1MHz).
THEORY
Single side band signal generation using Phase shift method and demodulation of SSB signal
using
Synchronous detector.This exp consists of
1.R.F generator.
2.A.F generator.
3.Two balanced modulators.
4.Synchronous detector
5.Summer
6.Subtractor
1. RF generator:
Colpitts oscillator using FET is used here to generate RF signal of approximately 100KHz
frequency to use as carrier signal in this experiment. Phase shift network is included in the
same block to produce another carrier signal of same frequency with 900 out of phase. An
individual controls are provided to vary the output voltage. Facility is provided to adjust phase
of the output signal.
2. AF generator:
This is a sine cosine generator using OP-OMP. IC TL 084 is used as an active component, TL
084 is a FET input general purpose quad op-amp integrated circuit. A three position switch is
provided to select output frequency. An individual controls are provided to vary the output
voltage. AGC control is provided to adjust the signal shape.
3. Balanced Modulator :
This has been developed using MC 1496 IC, is a monolithic integrated circuit Balanced
modulator/demodulator, is versatile and can be used up to 200MHz. These modulators are used
in this experiment to produce DSB_SC signals. Control is provided to balance the output.
4. Synchronous detector:
The base band signal m(t) can be uniquely recovered from a DSB-SC signal s(t)
by first multiplying s(t) with a locally generated sine wave carrier and then low pass
filtering the product. It is assumed that the local oscillator signal is exactly coherent or
synchronous, in both frequency and phase with the carrier wave c(t) used in the
balanced modulator to generate s(t). This method of demodulation is known as coherent

detection or synchronous detection.
In this unit IC MC 1496 is used as synchronous demodulator. The MC 1496 is a monolithic
balanced modulator/ balanced demodulator, is versatile and can be used up to 200MHz. On
board generated carrier is used as synchronous signal.
5. Summer and subtractors:

These circuits are simple summing and subtracting amplifiers using OP-AMP. IC TL084 is
used as an active component, TL 084 is a FET input General purpose quad OP-AMP integrated
circuit. The phase shift method makes use of two balanced modulators and two phase shift
networks as shown in figure. One of the modulators receives the carrier signal shifted by 900
and the modulating signal with 00 (sine ) phase shift, where as the other receives modulating
signal shifted by 900 ( cosine ) and the carrier ( RF) signal
with 00 phase shift voltage. Both modulators produce an output consisting only of sidebands. It
will be shown that both upper sidebands leads the reference voltage by 900, and the other lags
it by 900. The two lower side bands are thus out of phase and when combined in the adder,
they cancel each other. The upper side bands are in phase at the adder and therefore they add
together and gives SSB upper side band signal. When they combined in the subtractor, the
upper side bands are cancel because in phase and lower side bands add together and gives SSB
lower side band signal.
PROCEDURE:-
SSB MODULATION
2. Switch on the kit and measure the output of regulated power supplies positive and
negative voltages.
3. Observe the outputs of RF generators using CRO.Where one output is 00phase the
another is 900 phase shifted(or) is a sine wave and shifted w.r.t other (or) is a cosine
wave.
4. Adjust the RF output frequency as 100 KHz and amplitude as ≥ 0.2 Vp-p (Potentiometers
are provided to
vary the output amplitude & frequency).
5. Observe the two outputs of AF generator using CRO.
6. Select the required frequency (2k, 4k, 6k) form the switch positions for AF.
7. Adjust the gain of the oscillator by varying the AGC potentiometer and keep the
amplitude of 10Vp-p.
8. Measure and record the above seen signals & their frequencies on CRO.
9. Set the amplitude of R.F signal to 0.2Vp-p and A.F signal amplitude to 8Vp-p and
Connect AF-00 and RF-900 to inputs of balanced modulator A and observe DSBSC(
A) output on CRO. Connect AF-900 and RF-00 to inputs of balanced modulator
B and observe the DSB-SC (B)out put on CRO and plot the same on graph.
10. To get SSB lower side band signal connect balanced modulator outputs (DSB-SC)
to subtractor and observe the output wave form on CRO and plot the same on
graph.
11. To get SSB upper side band signal, connect the output of balanced modulator
outputs to summer circuit and observe the output waveform on CRO and plot the
same on graph.
12. Calculate theoretical frequency of SSB (LSB & USB) and compare it with
practical value.
USB = RF frequency + AF frequency.
LSB = RF frequency – AF frequency.
SSB DEMODULATION
1. Connect the SSB signal from the summer or subtractor at SSB signal input terminal of
synchronous
detector.
2. Connect RF signal (00) at RF input terminal of the synchronous detector.
Observe the detector output on CRO and compare it with the modulating signal (AF Signal)
and plot the
same on graph.
EXPERIMENT 8
PULSE AMPLITUDE MODULATION & DEMODULATION
Aim: To generate the Pulse Amplitude modulated and demodulated signals.

Apparatus required:
1.PAM trainer kit
2. C.R.O (20MHz)
Theory:
PAM is the simplest form of data modulation .The amplitude of uniformly spaced pulses is
varied in proportion to the corresponding sample values of a continuous message m (t).
A PAM waveform consists of a sequence of flat-topped pulses. The amplitude of each pulse
corresponds to the value of the message signal x (t) at the leading edge of the pulse.
The pulse amplitude modulation is the process in which the amplitudes of regularity spaced
rectangular pulses vary with the instantaneous sample values of a continuous message signal in
a one-one fashion. A PAM wave is represented mathematically as,
S (t) = å [1+Ka x (nTs)] P (t-nTs)
N= -¥
Where
x (nTs) ==> represents the nth sample of the message signal x(t)
Analog Communications Bapatla Engineering College Bapatla
46
K= ==> is the sampling period.
Ka ==> a constant called amplitude sensitivity
P (t) ==>denotes a pulse
PAM is of two types

1) Double polarity PAM ==> This is the PAM wave which consists of both positive and
negative
pulses shown as
2) Single polarity PAM ==> This consists of PAM wave of only either negative (or)
Positive pulses. In this the fixed dc level is added to the signal to ensure single polarity signal.
It is represented as
Circuit Diagram:
Pulse
Amplitude Modulation Circuit
Demodulation Circuit
Procedure:
1. Connect the circuit as per the circuit diagram shown in the fig 3
2. Set the modulating frequency to 1KHz and sampling frequency to 12KHz
3. Observe the o/p on CRO i.e. PAM wave.
4. Measure the levels of Emax & Emin.
5. Feed the modulated wave to the low pass filter as in fig 4.
6. The output observed on CRO will be the demodulated wave.
7. Note down the amplitude (p-p) and time period of the demodulated wave. Vary the
amplitude and frequency of modulating signal. Observe and note down the changes in
output.
8. Plot the wave forms on graph sheet.
EXPERIMENT 9
EFFECT OF NOISE ON COMMUNICATION CHANEL
AIM : Study the effect of the noise on communication channel
APPARATUS: 1. Double sideband AM Transmitter and Receiver Trainer Kit.

2.CRO
3. CRO probes
4. Connecting probes
CIRCUIT DIAGRAM:
PROCEDURE: MODULATION:
1. Ensure that the following initial conditions exist on the board.
a). Audio input select switch in INT position.
b). Mode switch in DSB position.
c). Output Amplifier gain preset in fully clockwise position.
d). speaker switch in OFF position.
2. Turn on power to ST2201 board.
3. Turn the Audio oscillator blocks Amplitude preset to it’s fully clockwise position and
examine
the blocks output (TP14) on CRO. This is the audio frequency sine wave which will be as
output
Modulating signal.
4. Turn the balance preset in Balanced Modulator and band pass filler circuit 1 block, to its
fully
clockwise position. It is the block that we will be used to perform double side band amplitude
modulation.
5. Monitor the waveforms at TP1 and TP9 signal at TP1 is modulating signal and signal at TP9
is
carrier signal to DSB-AM and observe the waveform at TP3 together with modulating signal,
wave at TP3 is DSB-AM signal.
DEMODULATION
1. Ensure that the following initial conditions exist on the board ST220I.
a) Tx output selector switch in antenna position.
b) Audio amplifiers volume preset in fully counter clock wise position and speaker
switch is in ON position.
2. Ensure that the following initial conditions exist on the board ST2202
c) Rx input select switch in antenna position.
d) RF amplifiers tuned circuit select switch in INT position.
e) RF amplifiers gain preset in fully clock wise position.
f) AGC switch in OUT position.
g) Detector switch in product position.
h) Audio amplifiers volume preset in fully counter clock wise position and speaker
switch is in ON position. i) Beat frequency oscillator switch in ON position.
3) Transmit the DSB-AM wave to the ST2202 receiver by selecting The Tx output select
switch in the ANT position.
4. Monitor the detected modulating signal ay TP37.Observe the Variations by varying the
amplitude and frequency of the modulating signal in ST2201.
5. Observe the effect of noise which is created externally on Amplitude modulated and
demodulated signals. Distortion in the modulating signals with noise.
EXPERIMENT 10
Pre-Emphasis & De-Emphasis
Aim:
I) To observe the effects of pre-emphasis on given input signal.
ii) To observe the effects of De-emphasis on given input signal.
Apparatus Required:
Transistor (BC 107)
Resistors 10 KΩ, 7.5 KΩ, 6.8 KΩ 1 each
Capacitors 10 nF0.1 μF
CRO 20MHZ 1
Function Generator 1MHZ 1
Regulated Power Supply
Theory:
The noise has a effect on the higher modulating frequencies than on the lower ones.
Thus, if the higher frequencies were artificially boosted at the transmitter and correspondingly cut at the
receiver, an improvement in noise immunity could be expected, there by increasing the SNR ratio. This
boosting of the higher modulating frequencies at the transmitter is known as
pre-emphasis and the compensation at the receiver is called de-emphasis.
Circuit Diagrams:
For Pre-emphasis:
For De-emphasis:
Procedure:
1. Connect the circuit as per circuit diagram as shown in Fig.1.
2. Apply the sinusoidal signal of amplitude 20mV as input signal to pre emphasis circuit.
3. Then by increasing the input signal frequency from 500Hz to 20KHz, observe the output
voltage (vo) and calculate gain (20 log (vo/vi).
4. Plot the graph between gain Vs frequency.
5. Repeat above steps 2 to 4 for de-emphasis circuit (shown in Fig.2). by applying the
sinusoidal signal of 5V as input signal
Experiment 1
Study Matrix Variables and Arithmetic Operators

Another useful Matlab command is 'whos', which will report the names and dimensions of all
variables currently in Matlab's memory. After typing the command at the prompt we see:
>> whos
Name Size Bytes Class
x 1x1 8 double array
Grand total is 1 elements using 8 bytes
The important thing to note right now is that the size is given as '1x1'. Matlab is really
designed to work with vectors and matrices, and a scalar variable is just a special case of a 1x1
dimensional vector. To assign a vector containing the first 5 integers to the variable x, we
could type this command:
>> x = [1 2 3 2^2 2*3-1]
x =
1 2 3 4 5
We won't have much occasion to operate on matrices that are higher dimension, but if you
wanted to create a 2-D matrix you could use a command something like:
>> A = [1 2 3; 4 5 6]
A =
1 2 3
4 5 6
To create larger vectors than the toy examples above (say, the integers up to 100), we would
need to type a lot of numbers. Not surprisingly, there are easier ways built in to create vectors.
To create the same 5-element vector we did above, we could also type:
>> x = [1:5]
x =
1 2 3 4 5
The colon operator creates vectors of equally spaced elements given a beginning point, and
maximum ending point and the step size in between elements. Specifically, [b:s:e] creates
the vector [b b+s b+2*s ... e]. If no step size is specified (as in the example above), a step
of 1 is assumed. So, the command [1:2:10] would create the vector of odd integers less than
10, [1 3 5 7 9] and the command [1:3:10] would create the vector of elements [1 4 7
10].
Let's create the vector of odd elements mentioned above:

>> x_odd = [1:2:10]
x_odd =
1 3 5 7 9
You can access any element by indexing the vector name with parenthesis (indexing starts
from one, not from zero as in many other programming languages). For instance, to access the
3rd element, we would type:
>> x_odd(3)
ans =
5
We can also access a range of elements (a subset of the original vector) by using the colon
operator and giving a starting and ending index.
>> x_odd(2:4)
ans =
3 5 7
If we want to do simple arithmetic on a vector and a scalar, the expected things happen,
>> 3+[1 2 3]
ans =
4 5 6
>> 3*[1 2 3]
ans =
3 6 9
and the addition or subtraction of matrices is possible as long as they are the same size:
>> [1 2 3]+[4 5 6]
ans =
5 7 9
The operators '*' and '/'
actually represent matrix multiplication and division which is not
typically what we will need in this course. However, a common task will be to form a
new vector by multiplying (or dividing) the elements of two vectors together, and the special
operators '.*' and './' serve that purpose.
>> [1 2 3].*[4 5 6]
ans =
4 10 18
>> [1 2 3]./[4 5 6]
ans =
0.2500 0.4000 0.5000
Beware that the operator '^' is a shortcut for repeated matrix multiplications ('*'), whereas the
operator '.^' is the shortcut for repeated element-by-element multiplications ('.*'). So, to
square all of the elements in a vector, we would use
>> [1 2 3].^2
ans =
1 4 9
Experiment 2
Write the MATLAB code for Matrices.

Matricies can be entered either in the MATLAB editor or by the carrot prompt by using
brackets to define the matrix and semicolons to separate matrix rows. For example, by entering
»A=[1 2 3;4 5 6;7 8 0]
we get the MATLAB output on screen as
A =
1 2 3
4 5 6
7 8 0
If we want to find the transpose of matrix A we simply type at the prompt

»B=A’
where the ‘ indicates transposition The resultant screen output is
B =
1 4 7
2 5 8
3 6 0
Taking the matrix inverse of A is simple as typing
»inv(A)
which yields the screen output (nearly instantaneously)
ans =
-1.7778 0.8889 -0.1111
1.5556 -0.7778 0.2222
-0.1111 0.2222 -0.1111
Experiment 3
Write the MATLAB code for polynomials

Suppose we had two polynomials and we wanted to multiply them and find the roots of the
resultant expression. If the two polynomials were
x2+3x+2 and x2+x-12
we would define the polynomials in MATLAB by typing
»A=[1 3 2];
»B=[1 1 -12];
where the polynomials are expressed as vectors where the vector elements represent the
polynomial coefficients in descending order. We can multiply the 2 polynomials algebraically
in MATLAB by using the convolution function or
»C=conv(A,B)
which yields
»C =
1 4 -7 -34 -24
The screen output displays the coefficients of the resultant polynomial in descending order.
This means that the product of the 2 polynomials is given by
x4+4x3-7x2-34x-24
To find the roots of the resultant polynomial we simply type
»roots(C)
which yields the 4 roots as
ans =
3.0000
-4.0000
-2.0000
-1.0000
Experiment 4
Write the MATLAB code for plotting sin and cos function.
. If we wanted to plot
y=sin(x) and z=.01x2 from -15 to 15 in increments of .05 only the following 4 MATLAB
statements would be required
»x=-15:.05:15;
»y=sin(x);
»z=x.^2/100;
»plot(x,y,x,z)
The unenhanced screen output for such a set of commands appears in Fig. 1. Of course since
MATLAB grpahical output is in the PICT format it can be copied to the clipboard and pasted
into any Macintosh application.
Plotting With MATLAB is Easy

Experiment 5
Write the MATLAB code for plotting square wave.
»t = 0:.1:10;
»y = sin(t) + sin(3*t)/3 + sin(5*t)/5 + sin(7*t)/7 + sin(9*t)/9;
»plot(t,y)
The resultant unenhanced MATLAB output is shown below.
MATLAB Output square wave

Experiment 6
Evaluate the function using MATLAB
over the range

-2¾x¾2, -2¾y¾3
All we have to do is use the following 3 MATLAB statements to get a 3 dimensional plot (with
all the hidden line algorithms transparent to the user) of the function.
»[x,y]=meshdom(-2:.2:2,-2:.2:3);
»z=x.*exp(-x.^2-y.^2);
»mesh(z)
- MATLAB 3 Dimensional Plot

Experiment 7
Write the MATLAB code for plotting Signal Processing

Noisy signals can be analyzed with MATLAB. For example, we can make 750 gaussian
distributed random numbers with zero mean and unity standard deviation with the statements
»rand(‘normal’)
»y=rand(750,1);
We can then analyze and display the frequency content of the 750 random numbers with a
MATLAB histogram statement or
»[n,x]=hist(y);
»plot(x,n,’+’)
As expected, the MATLAB output, shown in Fig. 4, demonstrates that the 750 random
numbers follow the standard “bell-shaped” curve or well known gaussian distribution.
Figure 4 - MATLAB Can Make Histograms

As was mentioned in the introduction, MATLAB comes with very powerful algorithms. The
next example shows a simple use of the FFT (Fast Fourier Transform) function. A common use
of the FFT is to find the frequency components buried in a noisy time domain signal. Consider
data sampled at 1000 Hz. We can form a signal containing 50 Hz and 120 Hz and corrupt it
with gaussian noise (zero mean and unity standard deviation) with the following 5 MATLAB
statements.
»t=0:.001:.5;
»x=sin(2*pi*50*t)+sin(2*pi*120*t);
»rand(‘normal’)
»y=x+2*rand(t);
»plot(y(1:50))
Figure 5 - Noisy Signal in Time Domain

It is difficult, if not impossible, to identify the frequency components by looking at the original
signal in the time domain. Converting to the frequency domain, the discrete Fourier transform
of the noisy signal y is found by taking the FFT. In MATLAB code this means
»Y=fft(y);
The power spectral density, a measurement of the energy at various frequencies, is:
»Pyy=Y.*conj(Y);
We can plot the power spectral density by forming a frequency axis for the first 256 points (the
other 256 points are symmetric) with the MATLAB statements
»f=1000*(0:255)/512;
»plot(f,Pyy(1:256))
From the resultant output in Fig. 6 we can clearly see the frequency components at 50 Hz and
120 Hz of the signal.
- Frequency Domain Output

Experiment 8
Write the MATLAB code for Control Analysis
MATLAB can also be used in the analysis of control systems from both a modern and classical
point of view. We can find and plot the root locus of the transfer function
for gains 0 to 10 in steps of .5 with the following MATLAB statements

»num = [.2 .3 1];
»den1 = [1 .4 1];
»den2 = [1 .5];
»den = conv(den1,den2);
»k = 0:.5:10;
»r = rlocus(num,den,k);
»plot(r,’x’), title(‘Root-locus’),xlabel(‘Real part’),ylabel(‘Imag part’)
The resultant root locus is shown in Fig. 7.
Root Locus Example With MATLAB

We could find the step response for the same system by typing the additional statements
»[a,b,c,d] = tf2ss(num,den)
»t = 0:.3:15;
»y = step(a,b,c,d,1,t);
»plot(t,y),title(‘Step response’),xlabel(‘time(sec)’)
yielding the output
Step Response Output

Another example of the control system analysis capability of MATLAB consider a second
order quadratic transfer function with natural frequency 1 rad/sec and damping of .2. The
MATLAB program required to display the magnitude characteristics is shown below and the
resultant output is displayed in Fig. 9.
»[a,b,c,d]=ord2(1,.2);
»w=logspace(-1,1);
»[mag,phase]=bode(a,b,c,d,1,w);
»mag1=20*log10(mag);
»semilogx(w,mag1)
Sample Magnitude Bode Plot For Quadratic Transfer Function

Experiment 9
Write the MATLAB code for Linear Convolution
Given a pair of sequences, use discrete convolution to find the response to the input x[n] of the
linear time-invariant system with impulse response h[n].
x[n]= square wave with amplitude 1
y[n]= triangle wave with amplitude 2
i. Use PLOT command to plot the input and impulse response
ii. Compute the convolution by hand, use MATLAB to plot the results
iii. Write a MATLAB function to compute the convolution of the two finite-length
sequences and plot the results.
For length N input vector x, the DFT is a length N vector X, with elements
N
X(k) = sum x(n)*exp(-j*2*pi*(k-1)*(n-1)/N), 1 <= k <= N.
n=1
iv. Use CONV command to verify the results from b.
Experiment 10
Write the MATLAB code for Time Vectors

Most toolbox functions require you to begin with a vector representing a time base. Consider
generating data with a 1000 Hz sample frequency, for example. An appropriate time vector is
t = (0:0.001:1)';
where the MATLAB colon operator creates a 1001-element row vector that represents time running
from 0 to 1 s in steps of 1 ms. The transpose operator (') changes the row vector into a column; the
semicolon (;) tells MATLAB to compute, but not display the result.
Given t, you can create a sample signal y consisting of two sinusoids, one at 50 Hz and one at 120 Hz
with twice the amplitude.
y = sin(2*pi*50*t) + 2*sin(2*pi*120*t);
The new variable y, formed from vector t, is also 1001 elements long. You can add normally
distributed white noise to the signal and plot the first 50 points using
randn('state',0);
yn = y + 0.5*randn(size(t));
plot(t(1:50),yn(1:50))
LABORATORY EXPERIMENTS
MICROPROCESSER
1. To Add Two Binary Numbers Each 8 Byte Long

2. To Find The Largest Number In A Given String
3. To Sort A String Of Bytes In Descending Order
4. To Calculate The Number Of Bytes In A String Of Data
5. To Move A Block Of Data Upward
6. To Do ASCII Multiplication
7. To Divide A Strong Of Unpacked ASCII Digits
8. 8155 In I/O Mode Using All Te Ports
9. 8155 For Memory Operation
10. To Do Decimal Addition Of Two Numbers
Program-1:
To ADD two binary numbers each 8byte long:
Address Op code Mnemonic Comments

0400 F8 CLC clear carry flag.
0401 B9 04 00 MOV CX,0004 Load Counter register with

no. of
times addition to be
performed.
0404 BE 00 05 MOV SI,0500 Load source index Reg.

with
starting address of Ist
Binary no.
0407 BF 08 05 MOV DI,0508 Load destination index

Reg. With
Dest.
040A 8B 04 (1) MOV AX,(SI) Load data bytes.
040C 11 05 ADC (DI),AX Add the contents (MS

Bytes) of
0508, 0509 with the
contents of
0500+0501 and store the
result in
location 0508 onwards.
040E 46 INC SI Point at 0502 LOCN
040F 46 INC SI (Next relevant source

LOCN)
0410 47 INC DI Point at Next relevant

LOCN
0411 47 INC DI 0504.
0412 49 DEC CX Decrement the counter.
0413 75 F5 JNZ(1) If not zero then continue

addition.
0415 F4 HLT Else , Halt.
For Example: After Execution
0500 : 01 0508 : 0A 0508 : 0B

0501 : 02 0509 : 0B 0509 : 0D
0502 : 03 050A : 0C 050A : 0F
0503 : 04 050B : 0E 050B : 12
0504 : 05 050C : 0F 050C : 14

0505 : 06 050D : 10 050A : 16
0506 : 07 050E : 11 050A : 18
0507 : 08 050F : 12 050A : 1A
Program-:2
To Find the maximum no. in a given string (16 byte long) and store it in location 0510.

0400 BE 00 05 MOV SI,0500 Load source index Reg. with
starting address of string.
0403 B9 10 00 MOV CX,00 10 Initialize counter Reg.
0406 B4 00 MOV AH,00 Initialize the 8 bit Acc.
0408 3A 24 CMP AH,[SI] The first data byte of the string with'00
'
040A 73 02 JAE 040E If both bytes match then branch to (1)
040C 8A 24 CMP AH,[SI] Else move the content of

(0500) in to 8 bit ACC
040E 46 INC SI Point at Next Address of string
040F E0 F7 LOOP NZ 0408 Decrement the counter value, if

not zero,continue processing
0411 88 24 MOV [SI],AH Max no. in 0510 Adderss.
0413 F4 HLT Halt

For Example After Execution
0500 : 01 0508 : 12 0510 : 15
0501 : 02 0509 : 08
0502 : 03 050A : 09
0503 : 04 050B : 0A
0504 : 05 050C : 0B
0505 : 06 050D : 0E
0506 : 15 050E : 0C
0507 : 07 050F : 0D
Program-3:
To sort a string of a no. of bytes in descending order:

0400 BE 00 05 MOV SI,0500 Initialize SI Reg. With Mem LOCN
0500
0403 8B 1C MOV BX,[SI] BX has the no of bytes
0405 4B DEC BX Decrement the no. of bytes by one
0406 8B 0C MOV CX,[SI] Also CX has the no. of bytes in

LOCNS 0500
and 0501
0408 49 DEC BX Decrement the no. of bytes by one
0409 BE 02 05 MOV SI,0502 initialize SI Reg. With starting

address
of the string
040C 8A 04 MOV AL,[SI] Move the first data byte of the string
in to
AL
040E 46 INC SI Point at Next byte of the string.
040F 3A 04 COMP AL,[SI] compare the two byte of string.
0411 73 06 JAE 0419 If the two bytes are equal.

0413 86 04 XCHG AL,[SI] Else
0415 4E DEC SI Second byte is less than first byte
and swap the two byte
0416 88 04 MOV [SI],AL
0418 46 INC SI Point at Next LOCN of string.
0419 E2 F1 LOOP 040C Loop if CX is not zero
041B 4B DEC BX At this juncture, first storing will be
over
041C BE 00 05 MOV SI,0500 compare with the rest of the no.
041F 75 F5 JNZ 0406
0421 F4 HLT Halt
For Example After Execution
0500 : 05 0502 : 28
0501 : 00 0503 : 25
0502 : 20 0504 : 20
0503 : 25 0505 : 15
0504 : 28 0506 : 07
0505 : 15
0506 : 07
Program-4:
ASCII Multiplication
To multiply an ASCII string of eight numbers by a single ASCII
digit. The result is a string of unpacked BCD digits.

0400 BE 00 05 MOV SI,0500 Initialize SI Reg. With Mem LOCN
0500
0403 BF 08 05 MOV DI,0508 Load DI Reg. With starting address
of result LOCNS
0406 B2 34 MOV DL,34 Load DL with the multiplier ASCII
digit.
0408 B9 08 00 MOV CX,0008 Load Counter register with no. of
bytes in the string.
040B C6 05 00 MOV [DI],00
040E 80 E2 0F ANDL,0F MS nibble of multiplier is zeroed.
0411 8A 04 MOV AL,[SI] Move the first ASCII no. of the
string in to
AL
0413 46 INC SI Point at Next byte of the string.
0414 80 E0 0F AND AL,0F MS nibble of multiplier is zeroed.
0417 F6 E2 MUI DL Perform the function AX=AL*DL
0419 D4 0A AAM Perform the function AH=AL/0A

041B 02 05 ADD AL,[DI] The content of AL
041D 37 AAA Added with 00 which are in first
Dest.
041E 88 05 MOV [DI],00 Point at Next LOCN of string.
0420 47 INC DI Point at Next relevant LOCN
0421 88 25 MOV [DI],AH contents of AH
0423 49 DEC CX Decrement the counter.
0424 75 EB JNZ 0411 If not zero, continue multiply and

storing
unpacked BCD digits ELSE.
0426 F4 HLT Halt.
For Examples After Execution
(Unpacked BCD Digits)

0500 : 31
0508 : 04
0501 : 32
0509 : 08
0502 : 33
050A : 02
0503 : 34
050B : 07
0504 : 35
050C : 01
0505 : 36
050D : 06
0506 : 31
050E : 06
0507 : 32
050F : 08
Program-5:
To Divide a String of Unpacked ASCII Digits:
Address Op Code Mnemonic Comments

0400 B2 36 MOV DL, 36 DL having the divisor, a single 8
bit ASCII Digit.
0402 BE 00 05 MOV SL, 0500 Load SI with the starting address

of ASCII string.
0405 BF 08 05 MOV DI, 0508 Load DI with the starting address

of the result LOCNS.
0408 B9 08 00 MOV CX, 0008 Initialize the counter Reg. with
the no. of bytes in the string.
040B 80 E2 0F AND DL, 0F MS nibble of DL contents is

zeroed.
040E 32E4 XOR AH,AH Initialize the 8 bit ACC (=00)
0410 AC (1) LODSB Load AL with the contents of

address accessed by SI reg. and
increment SI reg. i.e. point at the
next address LOCN.
0411 80 E0 0F AND AL,OF MS nibble of AL contents is also

zeroed.
0414 D5 0A AAD Perform the fn. AL=(AH * OA)

+
AL), AH = 00.
0416 F6 F2 DIV DL Perform the fn. AD/DL AL =

Quotient and AH = reminder.
0418 AA STOSB The contents of AL are stored in

the Address pointed to by the DI
reg. and next address LOCN in
DI reg. is pointed (i.e. current
address LOCN of DI reg. is
incremented by one).
0419 E0 F5 LOOP NZ 0410 Continue dividing the unpacked

ASCII digits if the contents of C
are not zeroed; else.
041B F4 HLT Halt.
For Example
After Execution
0500 : 31 0508 : 00
0501 : 32 0509 : 02
0502 : 33 050A : 00
0503 : 34 050B : 05
0504 : 35 050C : 07
0505 : 36 050D : 06
0506 : 31 050E : 00
0507 : 32 050F : 02
Program - 6 :
To calculate the no. of bytes in a string starting from 0502 up to an

identifier (data byte) placed in AL reg. The actual count will be in
LOCN 0500 & 0501.
0400 BE 00 05 MOV SI, 0500 Load SI reg. with the starting
Address where the result is to
be
stored.
0403 B9 FF FF MOV CX, FFFF Initialize the counter

register.
0406 BF 02 05 MOV DI, 0502 Load DI reg. with the startin

address of string.
0409 B0 03 MOV AL, 03 Store the identifier in ASL.
040B F2 AE REPNE SCASB Data byte accessed by DI

reg.
compared with identifier
without
altering either of the contents,
this comparing continuous
with
the incrementing of DI
contents
(Address LOCN) till the two
bytes match. With each
scanning
the contents of CX go on
decrement by one.
040D F7 D1 NOT CX Z’S complemented CX &

Move
CX 89 OC MOV (si),CX
040F
contents into 0500.
0411 F4 HLT Halt.
For Example
Let (509) = 03 Let (0502) = 03
Then after executing the program CX = 0008 & (0500) = 08

(0501) = 00
Program - 7 :
A Data string of no. of bytes (to be specified in CX reg.) is located

from the starting
address 0500. This data string is to be converted to its equivalent 2' S
complement
Form and the result is to be stored from 0600 on wards.
0400 BE 00 05 MOV SI, 0500 Load SI reg., with the starting

address of data string.
0403 BF 00 06 MOV DI, 0600 Load DI with the starting
address
of result LOCNS.
0406 B9 10 00 MOV CX, 0010 Load CX with the no. of

bytes in
the string.
0409 AC (1) LODSB Load AL with Data byte

accessed
by SI reg. and increment the
address LOCN in SI reg.
040A F6 D8 NEG AL The contents of AL are 2’s

complemented.
040C AA STOSB Store AL contents in LOCN

pointed to by DI ref. &
increment
the current Location in DI
reg.
040D E0 FA Loop NZ 0409 If CX = 0000, continue 2’s
complementing the data in
string
else;
040F F4 HLT Halt.
For Example
After Execution
0500 : 01 0600 : FF
0501 : 02 0601 : FE
0502 : 03 0602 : FD
0503 : 04 0603 : FC
0404 : 05 0604 : FB
0405 : 06 0605 : FA
0406 : 07 0606 : F9
0407 : 08 0607 : F8
0408 : 09 0608 : F7
0409 : 0A 0609 : F6
040A : 0B 060A : F5
040B : 0C 060B : F4
040C : 0D 060C : F3
040D : 0E 060D : F2
040E : 0F 060E : F1
040F : 10 060F : F0
Program 8 :
Serial Port Programming
This following program will character from PC and displayed on LCD.

The baud rate parameters to be set are same as described earlier in this
chapter. Use Hyper Terminal communication software on your PC
which is mentioned in Serial Communication.
This program receives the character from PC and displays it on LCD.
Address Op-Code Mnemonic Operand Comments

0400 B0 B7 MOV AL, B7 Control word format of 8253
0402 E6 03 OUT 03, AL
0404 B0 13 MOV AL, 13 Count is given to set the

Baud rate at 4800
0406 E6 02 OUT 02, AL
0408 B0 00 MOV AL, 00
040A E6 02 OUT 02, AL
040C B0 4E MOV AL, 4E Mode instruction format in

asynchronous mode
040E E6 51 OUT 51, AL
0410 B0 05 MOV AL,05 Command instruction format

. make transit enable and
Receive enable high.
0412 E6 51 OUT 51, AL

0414 9A 7C F0 00 F0 LM:CALL F000:F07C Clear the display.
0419 B3 80 MOV BL, 80 Delete the first line.
041B 9A 78 F0 00 F0 CALL F000:F078
0420 B9 14 00 MOV CX, 14
0423 E4 51 L1: IN AL, 51 Check for Rx RDY signal.
0425 24 02 AND AL,02
0427 74 FA JE 0423
0429 E4 50 IN AL,50 Character is received from

PC terminal & displayed
Into LCD modulator in
First line.
042B 9A 48 F0 00 F0 CALL F000:F048
0430 E2 F1 LOOP 0423
0432 B3 C0 MOV BL,C0 Delete second line.
0434 9A 78 F0 00 F0 CALL F000:F078
0439 B9 14 00 MOV CX,0014
043C E4 51 L2: IN AL,51 Check for Rx RDY signal.
043E 2402 AND AL,02
0440 74FA JE 043C
0442 E4 50 IN AL,50 received the character in

Second line
0444 9A 48 F0 00 F0 CALL F000:F048

0449 E2 F1 LOOP 043C
044B E9 C6 FF JMP 0414
Excute using ‘G’ 000:0400 and press any key on the PC keyboard, same will be displayed
on the LCD display of the M86-02
Program-9:
The following example will transmits characters to PC and

simultaneously
display on LCD.
Address Op Code Mnemonic Operand Comments
0400 B0 B7 MOV AL,B7 control word

format for
8253
0402 E6 03 OUT 03,AL
0404 B0 13 MOV AL,13 count is given to
set the baud
rate at 4800
0406 E6 02 OUT 02,AL
0408 B0 00 MOV AL,00
040A E6 02 OUT 02,AL
040C B0 4E MOV AL,4E mode

instruction
format in
asynchronous
mode
040E E6 51 OUT 51,AL
0410 B0 05 MOV AL,05 ;make transmit

enable and
receive enable
high
0412 E6 51 OUT 51,AL
0414 9A 7CF0 00 F0 L3: CALL F000:F07C clear the display
0419 B9 14 00 MOV CX,0014

041C B3 80 MOV BL,80 delete the
first line
041E 9A 78 F0 00 F0 CALL F000:F078
0423 51 L2: PUSH CX
0424 9A 50 F0 00 F0 CALL F000:F050 call for the read key in

alphabetical key
code and
transfer into
subprogram
0429 9A 58 F0 00 F0 CALL F000:F048 key in code enter

into LCD
modulator.
042E 9A 48 F0 00 F0 CALL F000:F048
0433 50 PUSH AX
0434 E4 51 L1: IN AL,51
0436 24 01 AND AL,01 check for TxRDY

signal
0438 74 FA JE 0434
043A 58 POP AX
043B E6 50 OUT 50,AL transmit the character

to
Terminal
043D 59 POP CX
043E E2 E3 LOOP 0423
0440 B9 14 00 MOV CX,0014
0443 B3 80 MOV BL,80 delete the first

line
0445 9A 78 F0 00 F0 CALL F000:F078

044A 51 L5: PUSH CX
044B 9A 50 F0 00 F0 CALL F000:F050 call for the read

key in
0450 9A 58 F0 00 F0 CALL F000:F058 call the

alphabetical key
Code transfer into
Subprogram
0455 9A 48 F0 00 F0 CALL F000:F048 key in code enter

into
LCD modulator
045A 50 PUSH AX
045B E4 51 L4: IN AL,51 check for TxRDY

signal
045D 24 01 AND AL,01
045F 74 FA JE 045B
0461 58 POP AX
0462 E6 50 OUT 50,AL Transmit the

character to
CRT terminal
0464 59 POP CX
0465 E2 E3 LOOP 044A
0467 E9 AA FF JMP 0414
Execute using ‘G’ command from 0000:0400 and press any key of the
M86-02 keyboard, the same will be displayed on the LCD and on the screen of PC.
Program 10
8259 Interrupt Controller

The following program illustrates the use of IRQ0 of 8259. Whenever
user made Pin
18 of 8259 OR Pin 1 of Connector CN6 is made low. The 0000:400
program
branches to 2000 address.
Address Op Code Mnemonic Operand Comments
0400 B8 00 00 MOV AX,0000 data segment is initialize to
zero
0403 8E D8 MOV DS,AX
0405 B8 00 20 MOV AX,2000 interrupt location is
defined
0408 89 06 00 00 MOV [0000],AX
040C B8 00 00 MOV AX,0000
040F 89 06 02 00 MOV [0002],AX
0413 B0 17 MOV AL,17 ICW1 Command
0415 E6 30 OUT 30,AL
0417 B0 00 MOV AL,00 ICW2 Command
0419 E6 31 OUT 31,AL
041B B0 01 MOV AL,01 ICW4 Command
0413 E6 31 OUT 31,AL
041F B0 FE MOV AL,FE unmask IRQ0
0421 E6 31 OUT 31,AL
0423 9A 7C F0 00 F0 CALL F0000:F07C clear display
0428 B3 80 MOV BL,80 input parameter of

subprogram is stored
in BL,
clear 1st line
042A 9A 78 F0 00 F0 CALL F000:F078

042F B080 MOV AL,80 write all the
commands in AL
into LCD modulator
0431 9A 44 F0 00 F0 CALL F000:F044
0436 0E PUSH CS
0437 1F POP DS
0438 B3 00 06 MOV SI,600 starting addr of table

is stored
into SI
043B B9 0F 00 MOV CX,000F store table checking

length in
CX
043E FC L1: CLD clear direction flag
043F AC L0 DSB
0440 9A 48 F0 00 F0 CALL F000:F048 input AL data into

LCD
Modulator
0445 E2 F7 LOOP LA
0447 FB STI set interrupt flag
0448 E9 FD FF JMP 0448 Interrupt sub-routine

at
0000:2000
2000 9A 7C F0 00 F0 CALL F000:F07C clear the display
2005 B3 80 MOV BL,80 delete the first line
2007 9A 78 F0 00 F0 CALL F000:F078

200C B0 86 MOV AL,86 write all the
commands in
AL into LCD
modulator
200E 9A 44 F0 00 F0 CALL F000:F044
2013 0E PUSH CS
2014 1F POP DS
2015 BE 21 06 MOV SI,621 addr of table is

stored in SI
2018 B9 0D 00 MOV CX,0D table length stored in CX
201B FC L3: CLD
201C AC L0 DSB
201D 9A 48 F0 00 F0 CALL F000:F048 input AL data into

LCD
Modulator
2022 E2 F7 LOOP 201B
2024 CF IRET return to the

execution
Program
0600 57 41 49 54 49 4E 47 20 Waiting For
IRQ0
46 4F 52 20 49 4E 54 FF Interrupt
0621 49 52 30 20 49 4E 54
45 52 52 55 50 54
Lab Manual
of Glob
CMOS & VLSI us
Design
Group Of Institution
Steps To Operate XILINX Software
Step 1 Click on the icon of xilinx software
Step 2 Go to file menu and click on “New Project”.
Step 3 Give the project name
Step 4 Click on “Next Button”.
Step 5 Select the family device and package name with the help of
manual Then click on “Next” button.
Step 6 Click on “New Source” then select “VHDL Modual” .Write the file
name in the window and then click on “Next” button.
Step 7 Enter the port name &select the direction of the port.Then Click on
“Next” button three times.
Step 8 Click on “Finish”button.
Step 9 Enter the necessary coding between “Begin” and “End behaviour”statement.
Step 10 Click on “Synthesis” icon in process window.
Step 11 Click on “User Contraints” then assign the package pin.
Step 12 Now when “Xilinx pace window” opens, give location of input &output
pin with the help of manual.
Step 13 Save the aforesid settings by going to “File” icon on Task Bar. Then click
on”Genreate File (Programming Fle)” .Now“Inpact
Window” will open .
Step 14 Now click on “Configure Devices” and select “Using Slave Serial Mode”.
Step 15 Click on “Finish” button then “Add Device” window will open.Now select
the file .Then the “Impact” window will open.Right click on device and click
on “Program” button. In case the program has succeeded ,message
indicating the same will be displayed else “Programme Failed” will be
displayed .
Step 16 If the Programe had failed repeat step 1 to 14 till its succedes Now start
feeding inputs for the gate for which the necessary coding has been written in
step 9 and measure the out put.Depending upon the necessary coding written
for diifernt types of gates (AND,NAND,OR EXOR,EXNOR etc),its input
/outputs characteristics can be verified.
Experiment List
1. Write VHDL code for OR Gate.

2. Write VHDL code for AND Gate.
3. Write VHDL code for Xor Gate
4. Write VHDL code for MUX Gate
5. Write VHDL code for DECODER Gate
6. Write VHDL code for ADDER Gate
7. Write VHDL code for Comparator Gate
8. Write VHDL code for Multiplier
9. Write VHDL code for D FLIP FLOP
10.Write VHDL code for J K FLIP FLOP
Aim-Write the VHDL code for OR GATE
Theory - The OR gate is a logic gate that gives an output of '0' only when all of its
inputs are '0'. Thus, its output is '1' whenever at least one of its inputs is '1'.
Mathematically, Q = A + B.
1-Behavior Code ss
library ieee;
use ieee.std_logic_1164.all;
--------------------------------------
entity OR_ent is
port( x: in std_logic;
y: in std_logic;
F: out std_logic
);
end OR_ent;
---------------------------------------
architecture OR_arch of OR_ent is

begin
process(x, y)
begin
-- compare to truth table
if ((x='0') and (y='0')) then
F <= '0';
else
F <= '1';
end if;
end process;
end OR_arch;
2-Data Flow Code

architecture OR_beh of OR_ent is
begin
F <= x or y;
end OR_beh;
Write VHDL code for AND Gate
Theory- The AND gate is a logic gate that gives an output of '1' only when all of its inputs are
'1'. Thus, its output is '0' whenever at least one of its inputs is '0'. Mathematically, Q = A · B.
library ieee;
--------------------------------------------------
entity AND_ent is
y: in std_logic;
F: out std_logic
);
end AND_ent;
--------------------------------------------------
architecture behav1 of AND_ent is
begin
process(x, y)
begin
if ((x='1') and (y='1')) then
F <= '1';
else
F <= '0';
end if;
end process;
end behav1;
architecture behav2 of AND_ent is

begin
F <= x and y;
end behav2;
Write VHDL code for Xor Gate
Theory - The EXOR gate (for 'EXclusive OR' gate) is a logic gate that gives an
output of '1' when only one of its inputs is '1'.
library ieee;
--------------------------------------
entity XOR_ent is
y: in std_logic;
F: out std_logic
);
end XOR_ent;
--------------------------------------
architecture behv1 of XOR_ent is

begin
process(x, y)
begin
if (x/=y) then
F <= '1';
else
F <= '0';
end if;
end process;
end behv1;
architecture behv2 of XOR_ent is

begin
F <= x xor y;
end behv2;
Write VHDL code for MUX Gate

A multiplexer or mux is a device that performs multiplexing; it selects one of
many analog or digital input signals and forwards the selected input into a
single line. A multiplexer of 2n inputs has n select lines, which are used to
select which input line to send to the output.
library ieee;
-------------------------------------------------
entity Mux is
port( I3: in std_logic_vector(2 downto 0);
I2: in std_logic_vector(2 downto 0);
S: in std_logic_vector(1 downto 0);
O: out std_logic_vector(2 downto 0)
);
end Mux;
-------------------------------------------------
architecture behv1 of Mux is

beginss
process(I3,I2,I1,I0,S)
begin
-- use case statement

case S is
when "00" => O <= I0;
when "01" => O <= I1;
when "10" => O <= I2;
when "11" => O <= I3;
when others => O <= "ZZZ";
end case;
end process;
end behv1;
architecture behv2 of Mux is

begin
-- use when.. else statement

O <= I0 when S="00" else
I1 when S="01" else
I2 when S="10" else
I3 when S="11" else
"ZZZ";
end behv2;
Write VHDL code for DECODER Gate
library ieee;
-------------------------------------------------
entity DECODER is
port( I: in std_logic_vector(1 downto 0);
O: out std_logic_vector(3 downto 0)
);
end DECODER;
-------------------------------------------------
architecture behv of DECODER is

begin
process (I)
begin
-- use case statement
case I is
when "00" => O <= "0001";
when "01" => O <= "0010";
when "10" => O <= "0100";
when "11" => O <= "1000";
when others => O <= "XXXX";
end case;
end process;
end behv;
architecture when_else of DECODER is

begin
O <= "0001" when I = "00" else

"0010" when I = "01" else
"0100" when I = "10" else
"1000" when I = "11" else
"XXXX";
end when_else;
Write VHDL code for ADDER Gate
ibrary ieee;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
--------------------------------------------------------
entity ADDER is
generic(n: natural :=2);

port( A: in std_logic_vector(n-1 downto 0);
B: in std_logic_vector(n-1 downto 0);
carry: out std_logic;
sum: out std_logic_vector(n-1 downto 0)
);
end ADDER;
--------------------------------------------------------
architecture behv of ADDER is

-- define a temparary signal to store the result
signal result: std_logic_vector(n downto 0);
begin
-- the 3rd bit should be carry
result <= ('0' & A)+('0' & B);

sum <= result(n-1 downto 0);
carry <= result(n);
end behv;
Write VHDL code for Comparator Gate

library ieee;
---------------------------------------------------
entity Comparator is

less: out std_logic;
equal: out std_logic;
greater: out std_logic
);
end Comparator;
---------------------------------------------------
architecture behv of Comparator is
begin
process(A,B)
begin
if (A<B) then
less <= '1';
equal <= '0';
greater <= '0';
elsif (A=B) then
less <= '0';
equal <= '1';
greater <= '0';
else
less <= '0';
equal <= '0';
greater <= '1';
end if;
end process;
end behv;
Write VHDL code for Multiplier

library ieee;
-- two 4-bit inputs and one 8-bit outputs

entity multiplier is
port( num1, num2: in std_logic_vector(1 downto 0);
product: out std_logic_vector(3 downto 0)
);
end multiplier;
architecture behv of multiplier is
begin
process(num1, num2)
variable num1_reg: std_logic_vector(2 downto 0);

variable product_reg: std_logic_vector(5 downto 0);
begin
num1_reg := '0' & num1;

product_reg := "0000" & num2;
-- use variables doing computation

-- algorithm is to repeat shifting/adding
for i in 1 to 3 loop
if product_reg(0)='1' then
product_reg(5 downto 3) := product_reg(5 downto 3)
+ num1_reg(2 downto 0);
end if;
product_reg(5 downto 0) := '0' & product_reg(5 downto 1);
end loop;
-- assign the result of computation back to output signal

product <= product_reg(3 downto 0);
end process;
end behv;
Write VHDL code for D FLIP FLOP

library ieee ;
use work.all;
entity dff is
port( data_in: in std_logic;
clock: in std_logic;
data_out: out std_logic
);
end dff;
architecture behv of dff is

begin
process(data_in, clock)
begin
-- clock rising edge
if (clock='1' and clock'event) then

data_out <= data_in;
end if;
end process;
end behv;
Write VHDL code for J K FLIP FLOP.

library ieee;
entity JK_FF is
port ( clock: in std_logic;
J, K: in std_logic;
reset: in std_logic;
Q, Qbar: out std_logic
);
end JK_FF;
architecture behv of JK_FF is
-- define the useful signals here
signal state: std_logic;

signal input: std_logic_vector(1 downto 0);
begin
-- combine inputs into vector

input <= J & K;
p: process(clock, reset) is
begin
if (reset='1') then
state <= '0';
elsif (rising_edge(clock)) then
-- compare to the truth table

case (input) is
when "11" =>
state <= not state;
when "10" =>
state <= '1';
when "01" =>
state <= '0';
when others =>
null;
end case;
end if;
end process;
Q <= state;
Qbar <= not state;
end behv;
Software Lab
Experiment list
1. Write VHDL code for Counter

2. Write VHDL code for GCD calculator
3. Write VHDL code for Shift Register
4. Write VHDL code for RAM Module
5. Write VHDL code for N-bit counter
6. Write VHDL CODE FOR TRAFFIC CONTROLLER
7. Write VHDL code for Comparator Gate
8. Write VHDL code for Multiplier
9. Write VHDL code for D FLIP FLOP
10.Write VHDL code for J K FLIP FLOP
Write VHDL code for Counter
Counter
library ieee ;
entity counter is

port( clock: in std_logic;
clear: in std_logic;
count: in std_logic;
Q: out std_logic_vector(n-1 downto 0)
);
end counter;
architecture behv of counter is
signal Pre_Q: std_logic_vector(n-1 downto 0);
begin
-- behavior describe the counter
process(clock, count, clear)

begin
if clear = '1' then
Pre_Q <= Pre_Q - Pre_Q;
elsif (clock='1' and clock'event) then
if count = '1' then
Pre_Q <= Pre_Q + 1;
end if;
end if;
end process;
-- concurrent assignment statement

Q <= Pre_Q;
end behv;
Write VHDL code for GCD calculator

GCD calculator
library ieee;
use work.all;
-----------------------------------------------------
entity gcd1 is
port( Data_X: in unsigned(3 downto 0);
Data_Y: in unsigned(3 downto 0);
Data_out: out unsigned(3 downto 0)
);
end gcd1;
architecture behv of gcd1 is

begin
process(Data_X, Data_Y)
variable tmp_X, tmp_Y: unsigned(3 downto 0);
begin
tmp_X := Data_X;
tmp_Y := Data_Y;
if (tmp_X/=tmp_Y) then
if (tmp_X < tmp_Y) then
tmp_Y := tmp_Y - tmp_X;
else
tmp_X := tmp_X - tmp_Y;
end if;
else
Data_out <= tmp_X;
end if;
end loop;
end process;
end behv;
Write VHDL code for Shift Register

Shift Register
library ieee ;
---------------------------------------------------
entity shift_reg is
port( I: in std_logic;
shift: in std_logic;
Q: out std_logic
);
end shift_reg;
---------------------------------------------------
architecture behv of shift_reg is
-- initialize the declared signal

signal S: std_logic_vector(2 downto 0):="111";
begin
process(I, clock, shift, S)

begin
-- everything happens upon the clock changing
if clock'event and clock='1' then
if shift = '1' then
S <= I & S(2 downto 1);
end if;
end if;
end process;
-- concurrent assignment
Q <= S(0);
end behv;
Write VHDL code for RAM Module

RAM Module
library ieee;
--------------------------------------------------------------
entity SRAM is
generic( width: integer:=4;
depth: integer:=4;
addr: integer:=2);
port( Clock: in std_logic;
Enable: in std_logic;
Read: in std_logic;
Write: in std_logic;
Read_Addr: in std_logic_vector(addr-1 downto 0);
Write_Addr: in std_logic_vector(addr-1 downto 0);
Data_in: in std_logic_vector(width-1 downto 0);
Data_out: out std_logic_vector(width-1 downto 0)
);
end SRAM;
--------------------------------------------------------------
architecture behav of SRAM is

-- use array to define the bunch of internal temparary signals
type ram_type is array (0 to depth-1) of

std_logic_vector(width-1 downto 0);
signal tmp_ram: ram_type;
begin
-- Read Functional Section

process(Clock, Read)
begin
if (Clock'event and Clock='1') then
if Enable='1' then
if Read='1' then
-- buildin function conv_integer change the type
-- from std_logic_vector to integer
Data_out <= tmp_ram(conv_integer(Read_Addr));
else
Data_out <= (Data_out'range => 'Z');
end if;
end if;
end if;
end process;
-- Write Functional Section

process(Clock, Write)
begin
if (Clock'event and Clock='1') then
if Enable='1' then
if Write='1' then
tmp_ram(conv_integer(Write_Addr)) <= Data_in;
end if;
end if;
end if;
end process;
end behav;
-----------------------------------
Write VHDL code for N-bit counter
N-bit counter
library ieee ;
----------------------------------------------------
entity counter is

port( clock: in std_logic;
clear: in std_logic;
count: in std_logic;
Q: out std_logic_vector(n-1 downto 0)
);
end counter;
----------------------------------------------------
architecture behv of counter is
signal Pre_Q: std_logic_vector(n-1 downto 0);
begin
-- behavior describe the counter

process(clock, count, clear)
begin
if clear = '1' then
Pre_Q <= Pre_Q - Pre_Q;
elsif (clock='1' and clock'event) then
if count = '1' then
Pre_Q <= Pre_Q + 1;
end if;
end if;
end process;
-- concurrent assignment statement

Q <= Pre_Q;
end behv;
Write VHDL CODE FOR TRAFFIC CONTROLLER

library ieee;_
entity traffic_light is
port (clk, sa, sb: in bit;
ra, rb, ga, gb, ya, yb: inout bit);
end traffic_light;
architecture behave of traffic_light is
signal state, nextstate: integer range 0 to 12;
type light is (r, y, g);
signal lighta, lightb: light;
begin
process(state, sa, sb)_
begin
ra <= '0'; rb <= '0'; ga <= '0'; gb <= '0'; ya <= '0'; yb <=
'0';
case state is
when 0 to 4 => ga <= '1'; rb <= '1'; nextstate <= state+1;
when 5 => ga <= '1'; rb <= '1'; if sb = '1' then nextstate
<= 6; end if;
when 6 => ya <= '1'; rb <= '1'; nextstate <= 7;
when 7 to 10 => ra <= '1'; gb <= '1'; nextstate <= state+1;
when 11 => ra <= '1'; gb <= '1';
if (sa='1' or sb='0') then nextstate <= 12; end if;
when 12 => ra <= '1'; yb <= '1'; nextstate <= 0;
end case;
end process;
process(clk)_
begin
if clk = '1' then state <= nextstate; end if;
end process;
lighta <= r when ra='1' else y when ya='1' else g when
Write VHDL code for Comparator Gate

library ieee;
---------------------------------------------------
entity Comparator is

less: out std_logic;
equal: out std_logic;
greater: out std_logic
);
end Comparator;
---------------------------------------------------
architecture behv of Comparator is
begin
process(A,B)
begin
if (A<B) then
less <= '1';
equal <= '0';
greater <= '0';
elsif (A=B) then
less <= '0';
equal <= '1';
greater <= '0';
else
less <= '0';
equal <= '0';
greater <= '1';
end if;
end process;
end behv;
Write VHDL code for Multiplier

library ieee;
-- two 4-bit inputs and one 8-bit outputs

entity multiplier is
port( num1, num2: in std_logic_vector(1 downto 0);
product: out std_logic_vector(3 downto 0)
);
end multiplier;
architecture behv of multiplier is
begin
process(num1, num2)
variable num1_reg: std_logic_vector(2 downto 0);

variable product_reg: std_logic_vector(5 downto 0);
begin
num1_reg := '0' & num1;

product_reg := "0000" & num2;
-- use variables doing computation

-- algorithm is to repeat shifting/adding
if product_reg(0)='1' then
product_reg(5 downto 3) := product_reg(5 downto 3)
+ num1_reg(2 downto 0);
end if;
product_reg(5 downto 0) := '0' & product_reg(5 downto 1);
end loop;
-- assign the result of computation back to output signal

product <= product_reg(3 downto 0);
end process;
end behv;
Write VHDL code for D FLIP FLOP

library ieee ;
use work.all;
entity dff is
port( data_in: in std_logic;
data_out: out std_logic
);
end dff;
architecture behv of dff is

begin
process(data_in, clock)
begin
-- clock rising edge
if (clock='1' and clock'event) then

data_out <= data_in;
end if;
end process;
end behv;
Write VHDL code for J K FLIP FLOP.
library ieee;
entity JK_FF is
port ( clock: in std_logic;
J, K: in std_logic;
reset: in std_logic;
Q, Qbar: out std_logic
);
end JK_FF;
architecture behv of JK_FF is
-- define the useful signals here
signal state: std_logic;

signal input: std_logic_vector(1 downto 0);
begin
-- combine inputs into vector

input <= J & K;
p: process(clock, reset) is
begin
if (reset='1') then
state <= '0';
elsif (rising_edge(clock)) then
-- compare to the truth table

case (input) is
when "11" =>
state <= not state;
when "10" =>
state <= '1';
when "01" =>
state <= '0';
when others =>
null;
end case;
end if;
end process;
Q <= state;
Qbar <= not state;
end behv;
MATLAB
List of Experiment
1. Cascade realization of filter from coefficients
2. Create analog low-pass filter
3. Bilinear or biquadratic transform SISO system given by a zero/poles representation
4. Cepstrum calculation
5. Response of Butterworth filter
6. Calculating
a. fft — fast Fourier transform.
b. ifft — inverse fast Fourier transform.
7. Evaluate response of Chebyshev type 1 filter
8. Evaluate response of type 2 Chebyshev filter
9. Evaluate chirp z-transform algorithm
10. Evaluate discrete Fourier transform
Experiment 1
Aim — Cascade realization of filter from coefficients
Description
Creates cascade realization of filter from a matrix of coefficients (utility function).
Calling Sequence
[cels]=casc(x,z)
Parameters
x
(4xN)-matrix where each column is a cascade element, the first two column entries
being the numerator coefficients and the second two column entries being the
denominator coefficients
string representing the cascade variable

cels
resulting cascade representation
Programe
x=[1,2,3;4,5,6;7,8,9;10,11,12]
cels=casc(x,'z')
Out put
cels=casc(x,'z')
cels =
2 2 2
1 + 4z + z 2 + 5z + z 3 + 6z + z
---------- ---------- ----------
2 2 2
7 + 10z + z 8 + 11z + z 9 + 12z + z
Experiment 2
Aim
analpf — create analog low-pass filter
Description
Creates analog low-pass filter with cut-off frequency at omega.
hs=gain*poly(zers,'s')/poly(pols,'s')
Calling Sequence
[hs,pols,zers,gain]=analpf(n,fdesign,rp,omega)
Parameters
n
positive integer : filter order
fdesign
string : filter design method : 'butt' or 'cheb1' or 'cheb2' or 'ellip'
rp
2-vector of error values for cheb1, cheb2 and ellip filters where only rp(1) is used for
cheb1 case, only rp(2) is used for cheb2 case, and rp(1) and rp(2) are both used for
ellip case. 0<rp(1),rp(2)<1
for cheb1 filters 1-rp(1)<ripple<1 in passband
for cheb2 filters 0<ripple<rp(2) in stopband
for ellip filters 1-rp(1)<ripple<1 in passband 0<ripple<rp(2) in stopband
omega
cut-off frequency of low-pass filter in Hertz
hs
rational polynomial transfer function
pols
poles of transfer function
zers
zeros of transfer function
gain
gain of transfer function

Programe
//Evaluate magnitude response of continuous-time system
hs=analpf(4,'cheb1',[.1 0],5)
fr=0:.1:15;
hf=freq(hs(2),hs(3),%i*fr);
hm=abs(hf);
plot(fr,hm)
Output
Experiment 3
Aim
bilt — bilinear or biquadratic transform SISO system given by a zero/poles representation
Description
Function for calculating the gain poles and zeros which result from a bilinear transform or from
a biquadratic transform. Used by the functions iir and trans.
Calling Sequence
[npl,nzr,ngn] = bilt(pl,zr,gn,num,den)
Parameters
pl
a vector, the poles of the given system.
zr
a vector, the zeros of the given system.
num
a polynomial with degree equal to the degree of den, the numerator of the transform.
den
a polynomial with degree 1 or 2, the denominator of the transform.
npl
a vector, the poles of the transformed system.
nzr
a vector, the zeros of the transformed system.
ngn
a scalar, the gain of the transformed system.
Programe
Hlp=iir(3,'lp','ellip',[0.1 0],[.08 .03]);
pl=roots(Hlp.den);
zr=roots(Hlp.num);
gn=coeff(Hlp.num,degree(Hlp.num))/coeff(Hlp.den,degree(Hlp.den));
z=poly(0,'z');
a=0.3;
num=z-a;
den=1-a*z;
[npl,nzr,ngn] = bilt(pl,zr,gn,num,den)
Hlpt=ngn*poly(nzr,'z','r')/poly(npl,'z','r')
//comparison with horner
horner(Hlp,num/den)
Output
ans =
0.0244986 - 0.0129599z - 0.0129599z2 + 0.0244986z3
------------------------------------------------
- 0.6858669 + 2.2482477 z2 - 2.5393033z + z3
Experiment 4
Aim
cepstrum — cepstrum calculation
Description
fresp = cepstrum(w,mag) returns a frequency response fresp(i) whose magnitude at
frequency w(i) equals mag(i) and such that the phase of freq corresponds to a stable and
minimum phase system. w needs not to be sorted, but minimal entry should not be close to zero
and all the entries of w should be different.
Calling Sequence
fresp = cepstrum(w,mag)
Parameters
w
positive real vector of frequencies (rad/sec)
mag
real vector of magnitudes (same size as w)
fresp
complex vector
Programe
w=0.1:0.1:5;mag=1+abs(sin(w));
fresp=cepstrum(w,mag);
plot2d([w',w'],[mag(:),abs(fresp)])
Output
Experiment 5
Aim
buttmag — response of Butterworth filter
Description
Squared magnitude response of a Butterworth filter omegac = cutoff frequency ; sample =
sample of frequencies
Calling Sequence
[h]=buttmag(order,omegac,sample)
Parameters
order
integer : filter order
omegac
real : cut-off frequency in Hertz
sample
vector of frequency where buttmag is evaluated
Butterworth filter values at sample points
Description
squared magnitude response of a Butterworth filter omegac = cutoff frequency ; sample =
sample of frequencies
Programe
//squared magnitude response of Butterworth filter

h=buttmag(13,300,1:1000);
mag=20*log(h)'/log(10);
plot2d((1:1000)',mag,[2],"011"," ",[0,-180,1000,20])
Output
Experiment 6
Aim
Calculating
fft — fast Fourier transform.
ifft — inverse fast Fourier transform.
Description
Short syntax
direct
x=fft(a,-1) or x=fft(a) gives a direct transform.
single variate
If a is a vector a single variate direct FFT is computed that is:
x(k)=sum over m from 1 to n of a(m)*exp(-2i*pi*(m-1)*(k-1)/n)
for k varying from 1 to n (n=size of vector a).
(the -1 argument refers to the sign of the exponent..., NOT to "inverse"),
multivariate
If a is a matrix or or a multidimensionnal array a multivariate direct FFT is performed.
inverse
a=fft(x,1) or a=ifft(x)performs the inverse transform normalized by 1/n.
single variate
If a is a vector a single variate inverse FFT is computed
multivariate
If a is a matrix or or a multidimensionnal array a multivariate inverse FFT is

performed.
Long syntax for multidimensional FFT
x=fft(a,-1,dim,incr) allows to perform an multidimensional fft.

If a is a real or complex vector implicitly indexed by j1,j2,..,jp i.e.
a(j1,j2,..,jp) where j1 lies in 1:dim(1), j2 in 1:dim(2),... one gets a p-variate
FFT by calling p times fft as follows
incrk=1; x=a; for k=1:p x=fft(x ,-1,dim(k),incrk)

incrk=incrk*dim(k) end
where dimk is the dimension of the current variable w.r.t which one is integrating and
incrk is the increment which separates two successive jk elements in a.
In particular,if a is an mxn matrix, x=fft(a,-1) is equivalent to the two instructions:
a1=fft(a,-1,m,1) and x=fft(a1,-1,n,m).
Calling Sequence
x=fft(a ,-1) or x=fft(a)
x=fft(a,1) or x=ifft(a)
x=fft(a,-1,dim,incr)
x=fft(a,1,dim,incr)
Parameters
x
real or complex vector. Real or complex matrix (2-dim fft)
real or complex vector, matrix or multidimensionnal array.
dim
integer
incr
integer
Programe
//Comparison with explicit formula

//----------------------------------
a=[1;2;3];n=size(a,'*');
norm(1/n*exp(2*%i*%pi*(0:n-1)'.*.(0:n-1)/n)*a -fft(a,1))
norm(exp(-2*%i*%pi*(0:n-1)'.*.(0:n-1)/n)*a -fft(a,-1))
//Frequency components of a signal

//----------------------------------
// build a noides signal sampled at 1000hz containing to pure frequencies
// at 50 and 70 Hz
sample_rate=1000;
t = 0:1/sample_rate:0.6;
N=size(t,'*'); //number of samples
s=sin(2*%pi*50*t)+sin(2*%pi*70*t+%pi/4)+grand(1,N,'nor',0,1);
y=fft(s);
//the fft response is symetric we retain only the first N/2 points
f=sample_rate*(0:(N/2))/N; //associated frequency vector
n=size(f,'*')
clf()
plot2d(f,abs(y(1:n)))
Output
Experiment 7
Aim
cheb1mag — response of Chebyshev type 1 filter
Description
Square magnitude response of a type 1 Chebyshev filter.
omegac=passband edge.
epsilonsuch that 1/(1+epsilon^2)=passband ripple.
samplevector of frequencies where the square magnitude is desired.
Calling Sequence
[h2]=cheb1mag(n,omegac,epsilon,sample)
Parameters
n
integer : filter order
omegac
real : cut-off frequency
epsilon
real : ripple in pass band
sample
vector of frequencies where cheb1mag is evaluated
h2
Chebyshev I filter values at sample points
Examples
//Chebyshev; ripple in the passband

n=13;epsilon=0.2;omegac=3;sample=0:0.05:10;
h=cheb1mag(n,omegac,epsilon,sample);
plot2d(sample,h)
xtitle('','frequencies','magnitude')
Output
Experiment 8
Aim
cheb2mag — response of type 2 Chebyshev filter
Description
Square magnitude response of a type 2 Chebyshev filter.
omegar = stopband edge, sample = vector of frequencies where the square magnitude h2 is
desired.
Calling Sequence
[h2]=cheb2mag(n,omegar,A,sample)
Parameters
n
integer ; filter order
omegar
real scalar : cut-off frequency
attenuation in stop band
sample
vector of frequencies where cheb2mag is evaluated
h2
vector of Chebyshev II filter values at sample points

Programe
//Chebyshev; ripple in the stopband

n=10;omegar=6;A=1/0.2;sample=0.0001:0.05:10;
h2=cheb2mag(n,omegar,A,sample);
plot(sample,log(h2)/log(10),'frequencies','magnitude in dB')
//Plotting of frequency edges
minval=(-maxi(-log(h2)))/log(10);
plot2d([omegar;omegar],[minval;0],[2],"000");
//Computation of the attenuation in dB at the stopband edge
attenuation=-log(A*A)/log(10);
plot2d(sample',attenuation*ones(sample)',[5],"000")
Output
Experiment 9
Aim
czt — chirp z-transform algorithm
Description
chirp z-transform algorithm which calcultes the z-transform on a spiral in the z-plane at the
points [a*exp(j*theta)][w^kexp(j*k*phi)] for k=0,1,...,m-1.
Calling Sequence
[czx]=czt(x,m,w,phi,a,theta)
Parameters
x
input data sequence
czt is evaluated at m points in z-plane
magnitude multiplier
phi
phase increment
initial magnitude
theta
initial phase
czx
chirp z-transform output
Examples
a=.7*exp(%i*%pi/6);
[ffr,bds]=xgetech(); //preserve current context
rect=[-1.2,-1.2*sqrt(2),1.2,1.2*sqrt(2)];
t=2*%pi*(0:179)/179;xsetech([0,0,0.5,1]);
plot2d(sin(t)',cos(t)',[2],"012",' ',rect)
plot2d([0 real(a)]',[0 imag(a)]',[3],"000")
xsegs([-1.0,0;1.0,0],[0,-1.0;0,1.0])
w0=.93*exp(-%i*%pi/15);w=exp(-(0:9)*log(w0));z=a*w;
zr=real(z);zi=imag(z);
plot2d(zr',zi',[5],"000")
xsetech([0.5,0,0.5,1]);
plot2d(sin(t)',cos(t)',[2],"012",' ',rect)
plot2d([0 real(a)]',[0 imag(a)]',[-1],"000")
xsegs([-1.0,0;1.0,0],[0,-1.0;0,1.0])
w0=w0/(.93*.93);w=exp(-(0:9)*log(w0));z=a*w;
zr=real(z);zi=imag(z);
plot2d(zr',zi',[5],"000")
xsetech(ffr,bds); //restore context
Output
Experiment 10
Aim
dft — discrete Fourier transform
Description
Function which computes dft of vector x.
Calling Sequence
[xf]=dft(x,flag);
Parameters
x
input vector
flag
indicates dft (flag=-1) or idft (flag=1)
xf
output vector
Examples
n=8;omega = exp(-2*%pi*%i/n);
j=0:n-1;F=omega.^(j'*j); //Fourier matrix
x=1:8;x=x(:);
F*x
fft(x,-1)
dft(x,-1)
inv(F)*x
fft(x,1)
dft(x,1)
Output
>F*x
ans =
36.
- 4. + 9.6568542i
- 4. + 4.i
- 4. + 1.6568542i
- 4. - 1.021D-14i
- 4. - 1.6568542i
- 4. - 4.i
- 4. - 9.6568542i
-->fft(x,-1)
ans =
36.
- 4. + 9.6568542i
- 4. + 4.i
- 4. + 1.6568542i
- 4.
- 4. - 1.6568542i
- 4. - 4.i
- 4. - 9.6568542i
-->dft(x,-1)
ans =
36.
- 4. + 9.6568542i
- 4. + 4.i
- 4. + 1.6568542i
- 4. - 3.919D-15i
- 4. - 1.6568542i
- 4. - 4.i
- 4. - 9.6568542i
-->inv(F)*x
ans =
4.5 - 1.762D-15i
- 0.5 - 1.2071068i
- 0.5 - 0.5i
- 0.5 - 0.2071068i
- 0.5 + 4.996D-16i
- 0.5 + 0.2071068i
- 0.5 + 0.5i
- 0.5 + 1.2071068i
-->fft(x,1)
ans =
4.5
- 0.5 - 1.2071068i
- 0.5 - 0.5i
- 0.5 - 0.2071068i
- 0.5
- 0.5 + 0.2071068i
- 0.5 + 0.5i
- 0.5 + 1.2071068i
-->dft(x,1)
ans =
4.5
- 0.5 - 1.2071068i
- 0.5 - 0.5i
- 0.5 - 0.2071068i
- 0.5 + 4.899D-16i
- 0.5 + 0.2071068i
- 0.5 + 0.5i
- 0.5 + 1.2071068i
MICROWAVE ENGINEERING
EXPERIMENT NO:I
Experiment 1
Objective :
Study of characteristics of the Reflex Klystron Tube and to determine its
electronic tuning range
1 Klystron Power Supply

2 Klystron tube with Klystron mount
3 Isolator
4 Frequency meter
5 Variable attenuator
6 Detector mount
7 Wave guide stand
8 SWR meter and Oscilloscope
9 BNC cable
Theory :
The Reflex Klystron makes the use of velocity modulation to transform a continuous
electron beam into microwave power. Electrons emitted from the cathode are accelerated &
passed through the positive resonator towards negative reflector, which retards and finally,
reflects the electrons and the electrons turn back through the resonator. Suppose an rf-field
exists between the resonators the electrons traveling forward will be accelerated or
retarded, as the voltage at the resonator changes in amplitude.
Schematics Diagram of Klystron 2K25

The accelerated electrons leave the resonator at an increased velocity and the retarded
electrons leave at the reduced velocity. The electrons leaving the r esonator will need different
time to return, due to change in velocities. As a result, returning electrons group together
in bunches, as the electron bunches pass through resonator, they interact with voltage at
resonator grids. If the bunches pass the grid at such a time that the electrons are slowed
down by the voltage then energy will be delivered to the resonator; and Klystron will
oscillate. Figure 4 shows the relationship between output power, frequency and reflector
voltages.
Square Wave modulation of the Klystron:
The frequency is primarily determined by the dimensions of resonant cavity.

Hence, by changing the volume of resonator, mechanical tuning of klystron is
possible. Also, a small frequency change can be obtained by adjusting the reflector
voltage. This is called Electronic Tuning The same result can be obtained, if the modulation
voltage is applied on the reflector voltage as shown in the figure 5
Procedure :
Carrier Wave Operation :
1. Connect the components and equipments as shown in
Setup for study of Klystron Tube
2. Set the Variable Attenuator at the maximum position (at no attenuation).

3. Set the mode switch of klystron Power Supply to CW position, beam voltage
control knob to full anti-clock wise and reflector voltage control knob to fully
clock wise and the meter select to Beam position.
4. Keep SWR meter at 50dB attenuation and coarse and fine potentiometers on
mid position and crystal impedance at 200ohm.
5. Keep SWR/dB switch at dB position.
6. Set the multi-meter in DC microampere range.
7. Switch 'On' the klystron Power Supply & cooling fan for klystron tube.
8. Set the meter select to beam voltage position and rotate beam voltage knob
clockwise slowly. Observe beam current on the meter by changing the meter
switch to beam current position. 'The beam current should not increase more
than 25mA.
9. Change the reflector voltage slowly and observe the reading on the SWR meter.
Set the voltage for maximum reading in the meter. If no reading is obtained,
change the plunger position of klystron mount and detector mount. Select the
appropriate range on SWR Meter. Now replace SWR meter to multi-meter.
10. Tune the plunger of klystron mount for the maximum output.
11. Rotate the knob of frequency meter slowly and stop at that position, when there
is less output current on multi-meter. Read directly the frequency between two horizontal line
and vertical line markers. If micro meter type frequency meter is used, read micrometer
frequency and find the frequency from its calibration
chart.
Square Wave Operation :
 Connect the equipments and components as shown in fig.
2 Set Micrometer of variable attenuator for no attenuation.

3. Set the range switch of SWR meter at appropriate position, crystal selector
switch to 200ohm impedance position, mode select to normal position.
4. Now in KPS Set Modulation selector switch to AM- Mod. Position. Beam
voltage control knob to fully anticlockwise position. Reflector voltage control
knob to the fully clockwise position and meter select switch to 'beam' position.
5. Switch ‘On’ the Klystron Power Supply, SWR meter and cooling fan.
6. Change the beam voltage knob clockwise up to 300V.
7. Keep the AM amplitude knob and AM frequency knob at the mid-position.
8. Rotate the reflector voltage knob to get reading in SWR meter.
9. Rotate the AM amplitude knob to get the maximum output in SWR meter.
10. Maximize the reading by adjusting the frequency control knob of AM.
11. If necessary, change the range switch of SWR meter if the Reading in SWR
meter is grater than 0.0db or less than -10dB in normal Mode respectively.
Further the output can also be reduced by Variable Attenuator for setting the
output for any particular position.
12. Connect oscilloscope in place of SWR Meter and observe the square wave
across detector mount.
Mode Study on Oscilloscope :
3. Set up the components and equipments as shown in
2. Set Mode selector switch to FM-Mode position with FM amplitude and FM
frequency knob at mid position. Keep beam voltage control knob fully
anticlockwise and reflector voltage knob to fully clockwise.
3. Keep the time/division scale of Oscilloscope around 100Hz frequency
measurement and volt/ div to lower scale.
4. Switch ‘On’ the klystron Power Supply and oscilloscope.
5. Keep the meter switch of klystron Power Supply to beam voltage position and
set beam voltage to 300V by beam voltage control knob.
6. Keep amplitude knob of FM modulator to maximum position and rotate the
reflector voltage anti-clockwise to get modes as shown in figure 9 on the
oscilloscope. The horizontal axis represents reflector voltage axis, and vertical
axis represents output power.
7. By changing the reflector voltage and amplitude of FM modulation, any mode
of Klystron tube can be seen on an Oscilloscope.
EXPERIMENT NO:II
Objective :
To determine the frequency & wavelength in a rectangular waveguide working

in TE10 mode

2 Klystron tube
3 Isolator
4 Frequency meter
6 Slotted section
7 Tunable probe
8 Wave guide stand
9 SWR meter
10 Matched termination.
EXPERIMENT NO:III
Objective :
To determine the Standing Wave-Ratio and Reflection Coefficient
2 Klystron tube
3 SWR meter
4 Isolator
5 Frequency meter
7 Slotted line
8 Tunable probe
9 Wave guide stand
10 Matched Termination
11 BNC cable
12 S-S tuner
Theory :
It is a ratio of maximum voltage to minimum voltage along a transmission line is
called SWR, as ratio of maximum to minimum current. SWR is measure of
mismatchbetween load and line. The electromagnetic field at any point of transmission
line may be considered as the sum of two traveling waves: the 'Incident Wave' propagates
from generator and the reflected wave propagates towards the generator. The reflected wave
is set up by reflection of incident wave from a discontinuity on the line or from the load
impedance. The magnitude and phase of reflected wave depends upon amplitude and
phase of .the reflecting impedance. The superposition of two traveling waves, gives rise
to standing wave along with the line. The maximum field strength is found where two
waves are in phase and minimum where the line adds in opposite phase. The distance
between two successive minimum (and maximum) is half the guide wavelength on the
line. The ratio of electrical field strength of reflected and incident
wave is called reflection between maximum and minimum field strength along the
line.
a. Measurement of low and medium SWR
i. For low SWR set the S.S. tuner probe for no penetration position.
ii. Move the probe along with slotted line to get maximum reading in
SWR Meter in dB.
iii. Adjust the SWR Meter gain control knob or variable attenuator until
the meter indicates 0.0dB in normal modes. SWR for 0.0dB is 1.0
by keeping switch at SWR we can read it directly.
iv. Keep all the Control knobs as it is, move the probe to next minimum
gain position.
v. Keep SWR /dB switch at SWR position.
vi. Read the SWR from display and record it.
vii. Repeat the above step for change of S.S. Tuner probe penetration &
record the corresponding SWR.
viii. If the SWR is grater than 10dB, then you have to use the following
procedure.
b. Measurement of High SWR (Double Minimum Method)

EXPERIMENT NO:IV
Objective :
To measure an unknown Impedance with Smith chart
1 Klystron Tube 2K25
3 Klystron Mount
4 Isolator
5 Frequency meter
7 Slotted Line
8 Tunable Probe
9 SWR meter
10 Wave guide stand
11 S.S. Tuner
12 Matched Termination.
Procedure :
1. Set up the equipments as shown in the.

2. Set the variable attenuator at no attenuation position.
3. Connect S.S. tuner and matched termination after slotted line.
EXPERIMENT NO:V
Objective :
Study of V-I characteristics of Gunn Diode
1. Gunn oscillator
2. Gun Power Supply
3. PIN modulator
4. Isolator
5. Frequency meter
6. Variable attenuator
7. Detector mount
8. Wave guide stands
9. SWR Meter
10. Cables and accessories.
Theory :
The Gunn Oscillator is based on negative differential conductivity effect in bulk
semiconductors, which has two conduction bands minima separated by an energy gap
(greater than thermal agitation energies). A disturbance at the cathode gives rise to high
field region, which travels towards the anode. When this high field domain reaches the anode,
it disappears and another domain is formed at the cathode and starts moving towards anode
and so on. The time required for domain to travel from cathode to anode (transit time)
gives oscillation frequency.
In a Gunn Oscillator, the Gunn diode is placed in a resonant cavity. In this case the
Oscillation frequency is determined by cavity dimension. Although Gunn oscillator can be
amplitude modulated with the bias voltage. We have used separate PIN modulator through
PIN diode for square wave modulation.
A measure of the square wave modulation capability is the modulation depth i.e. the
output ratio between, ‘On’ and ‘Off’ state.
Procedure :
1. Set the components and equipment as shown in the
2. Initially set the variable attenuator for maximum attenuation.
5. Set the micrometer of Gunn Oscillator for required frequency of operation.
6. Switch ‘On’ the Gunn Power Supply SWR Meter and cooling fan.
7. Measure the Gunn diode current corresponding to the various voltage controlled
by Gunn bias knob through the panel, do not exceed the bias voltage above 10
volts.
8. Plot the voltage and current reading on the graph as shown in
9. Measure the threshold voltage which, corresponds to maximum current.
Note : Do not keep Gunn bias knob position at threshold position for more than 10-15
seconds. Otherwise due to excessive heating, Gunn Diode may burn.
EXPERIMENT NO:VI
Objective :
Study of the following characteristic of Gunn Diode
1. Output power and frequency as a function of Bias Voltage.
2. Square wave modulation through PIN diode.
1. Gunn oscillator
2. Gun Power Supply
3. PIN modulator
4. Isolator
5. Frequency meter
7. Detector Mount
8. Wave guide stands
9. SWR meter
10. Cables and accessories.
Procedure :
1. Set the components and equipment as shown in the

2. Initially set the variable attenuator for maximum attenuation (for no
attenuation).
5. Set the micrometer of Gunn oscillator for required frequency of operation
6. Switch on the Gunn Power Supply, SWR Meter.
a. Out Put Power and Frequency as a Function of Bias Voltage.
i. Increase the Gunn bias control knob upto 10V.
ii. Rotate PIN bias knob to around maximum position.
iii. Tune the output in the SWR meter through frequency control knob of
modulation.
iv. If necessary change the range dB switch of SWR meter to higher or
lower dB position to get reading on SWR meter display. Any level can
be set through variable attenuator and gain control knob of SWR
meter.
v. Measure the frequency using frequency meter and detune it.
vi. Reduce the Gunn bias voltage from 10V in the interval of 0.5V or 1.0V
and note down corresponding reading of output at SWR meter in dB
and corresponding frequency by frequency meter. (Do not keep Gunn
bias knob position at threshold position for more than 10-15 seconds.
Otherwise due to excessive heating, Gunn Diode may burn).
vii. Draw the power vs. Voltage curve and Frequency vs. Voltage curve
and plot the graph.
viii. Measure the pushing factor (MHz /Volt) which is frequency sensitivity
against variation in bias voltage for an oscillator. The pushing factor
should be measured around 8 volt bias. For example
b. Square Wave Modulation
i. Move the Gunn bias voltage Knob slowly so that panel meter of Gunn
Power Supply reads 10V.
ii. Keep the Gunn Power Supply in Internal modulation mode.
iii. Tune the PIN modulator bias voltage and frequency knob for
maximum detected output on the oscilloscope.
iv. Coincide the bottom of square wave in oscilloscope to some reference
level and note down the micrometer reading of variable attenuator.
v. Now with the help of variable attenuator coincide the top of square
wave to same reference level and note down the micrometer reading.
vi. Now Connect detector mount to SWR Meter and note down the dB
reading in SWR Meter for both the micrometer reading of the variable
attenuator.
vii. The difference of both dB reading of SWR meter gives the modulation
depth of PIN modulator.
EXPERIMENT NO:VII
Objective :
Study of Magic Tee
1. Microwave source
2. Isolator
4. Frequency meter
5. Slotted line
6. Tunable probe
7. Magic Tee
8. Matched termination
9. Wave guide stand
10. Detector mount
11. SWR meter and accessories.
Theory :
The device magic Tee is a-combination of the E and H plane Tee. Arm 3, the H- arm
forms an H plane Tee and arm 4, the E-arm forms an E plane Tee in combination with
arm 1 and 2 a side or collinear arms. If power is fed into arm 3 (H-arm) the electric field
divides equally between arm 1 and 2 in the same phase, and no electrical field exists in arm
4. Reciprocity demands no coupling in port 3 (H-arm). If power is fed in arm 4 (E-arm),
it divides equally into arm 1 and 2 but out of phase with no power to arm 3. Further, if
the power is fed from arm 1 and 2, it is added in arm 3 (H-arm), and
it is subtracted in E-arm, i.e. arm 4.
Procedure :
1. SWR Measurement of the Ports
a. Set up the components and equipments as shown in figure keeping E arm

towards slotted line and matched termination to other ports.
b. Energize the microwave source for particular frequency of operation and
tune the detector mount for maximum output.
c. Measure the SWR of E-arm as described in measurement of SWR for low
and medium value.
d. Connect another arm to slotted line and terminate the other port with
matched termination. Measure the SWR as above. Similarly, SWR of any
port can be measured.
2. Measurement of Isolation and Coupling Coefficient
a. Remove the tunable probe and Magic Tee from the slotted line and
connect the detector mount to slotted line.
b. Energize the microwave source for particular frequency of operation and
tune the detector mount for maximum output.
c. With the help of variable attenuator and gain control knob of SWR meter,
set any power level in the SWR meter and note down. Let it be P3.
d. Without disturbing the position of variable attenuator and gain control
knob, carefully place the Magic Tee after slotted line keeping H-arm
connected to slotted line, detector to E arm and matched termination to
arm 1 and 2. Note down the reading of SWR meter. Let it be P4.
e. Determine the isolation between port 3 and 4 as P3-P4 in dB.
f. Determine the coupling coefficient from equation given in the theory part.
g. The same experiment can be repeated for other ports also.
h. Repeat the above experiment for other frequencies.
EXPERIMENT NO:VIII
Objective :
Study of Isolator and Circulators

1. Microwave source
2. Power Supply for source
3. Isolators
4. Circulators
5. Frequency meter
7. Slotted line
8. Tunable probe
9. Detector mount
10. SWR meter
11. Test isolation and
12. Circulation and accessories
Theory :
Isolator : An isolator is a two-port device that transfers energy from input to
output with little attenuation and from output to input with very high attenuation.
. Insertion loss
The ratio of power supplied by a source to the input port to the power detected
by a detector in the coupling arm, i.e. output arm with other port terminated in
the matched load, is defined as insertion loss or forward loss. .
2. Isolation
It is the ratio of power fed to input arm to the power detected at not coupled port
with other port terminated in the matched load
3. Input VSWR
The input VSWR of an isolator or circulator is the ratio of voltage maximum to
voltage minimum of the standing wave existing on the line when one port of it
terminates the line and other have matched termination.
Note : When port which is not coupled to input port is terminated by matched
termination it marks as Isolator. (Two port device).
Procedure :
1. Input VSWR Measurement
a. Set up the components and equipments as shown in the with
input port of isolator or circulator towards slotted line and matched load on
other ports of it
b. Energize the microwave source for particular operation of frequency.

c. With the help of slotted line, probe and SWR meter. Find SWR, of the
isolator or circulator as described for low and medium SWR
measurements.
d. The above procedure can be repeated for other ports or for other
frequencies.
2. Measurement of Insertion Loss and Isolation.
a. Remove the probe and isolator or circulator from slotted line and connect
the detector mount to the slotted section. The output of the detector mount
should be connected SWR meter.
b. Energize the microwave source for maximum output particular frequency
of operation. Tune the detector mount for maximum output in the SWR
Meter.
c. Set any reference level of power in SWR meter with the help of variable
attenuator and gain control knob of SWR meter. Let it be P1.
d. Carefully remove the detector mount from slotted line without disturbing
the position of set up. Insert the isolator/circulator between slotted line
and detector mount. Keeping input port to slotted line and detector at its
output port. A matched termination should be placed a third port in case
of circulator.
e. Record the reading in the SWR meter. If necessary change range -dB
switch to high or lower position and 10dB change for one step change of
switch position. Let it be P2.
f. Compute insertion loss on P1 – P2 in dB.
g. For measurement of isolation, the isolator or circulator has to be
connected in reverse i.e. output port to slotted line and detector to input
port with another port terminated by matched termination (in case
circulator) after setting a reference level without isolator or circulator in
the set up as described in insertion loss measurement. Let same P1 level is
set.
h. Record the reading of SWR meter inserting the isolator or circulator as
given in step 7. Let it be P3.
i. Compute isolation as P1 - P3 in dB.
j. The same experiment can be done for other ports of circulator.
k. Repeat the above experiment for other frequencies if required.
EXPERIMENT NO:IX
Objective :
Study of Attenuators
1 Microwave source
2 Isolator
3 Frequency meter
5 Slotted line
6 Tunable probe
7 Detector mount
8 Matched termination
9 SWR meter.
Theory :
The attenuators are two port bi-directional devices which attenuate power when
inserted into the transmission line
Where
P1 = Power absorbed or detected by the load without the attenuator in the line.
P2 = Power absorbed/detected by the load with attenuator in line.
The attenuators consist of a rectangular wave guide with a resistive vane inside it to
absorb microwave power according to their position with respect to side wall of the wave-
guide. As electric field is maximum, at center in TE10 mode, the attenuation willbe
maximum if the vane is placed at center of the wave-guide. Moving from center toward the
side wall, attenuation decreases in the fixed attenuator, the vane position is fixed where as in a
variable attenuator, its position can be changed by help of micrometer or by other
methods.
Following characteristics of attenuators can be studied
1. Input SWR.
2. Insertion loss (in case of variable attenuator).
3. Amount of attenuation offered into the lines.
4. Frequency sensitivity i.e. variation of attenuation at any fixed position of vane
and frequency is changed.
Procedure :
1. Input SWR Measurement
a. Connect the equipments as shown in the figure 39
b. Energize the microwave source for maximum power at any frequency of
operation.
c. Measure the SWR with the help of tunable probe, Slotted line and SWR
meter as described in the experiment of measurement of low and medium
SWR.
d. Repeat the above step for other frequencies if required.
2. Insertion Loss /Attenuation Measurement

a. Remove the tunable probe, attenuator and matched termination from the
slotted section in the above set up.
b. Connect the detector mount to the slotted line, and tune the detector
mount also for maximum deflection on SWR meter (Detector mount's
output should be connected to SWR meter).
c. Set any reference level on the SWR meter with the help of gain control
knob of SWR meter. Let it be P1. Now connect the attenuator in between
slotted line & detector mount.
d. Set the variable attenuator to zero attenuation position and record the
reading of SWR meter. Let it be P2. Then the insertion loss of test
attenuator will be P1 - P2 dB.
e. Now, change the micrometer reading and record the SWR meter reading
in dB. Find out Attenuation value for different position of micrometer
reading and record the readings to plot a graph.
f. In the same way you can test the fixed attenuator which can give you only
the single attenuation value.
g. Now change the operating frequency and all the step can be repeated for
finding frequency sensitivity of variable attenuator.
EXPERIMENT NO:X
Objective :
Study the Phase Shifter

1. Microwave source
2. Isolator
4. Frequency meter
5. Slotted section
6. Tunable probe
7. Phase shifter
8. Precision Movable short
9. SWR Meter
10. Cables and accessories
Theory :
A phase shifter consists of a piece of Wave-guide and a dielectric material inside the
wave-guide placed parallel to Electric vector of TE10 mode. The phase changes as piece of
dielectric material is moved from edge of wave-guide towards the center of the wave-
guide.
Procedure :
1. Set up the equipment as shown in the
2. First connect the Matched termination at the end of slotted line.

3. Energize the microwave source for maximum output at particular frequency of
operation.
4. Find out the g (guide wavelength) with help of tunable probe Slotted line and
SWR meter. It is the twice the distance between two minimas on the slotted line.
5. Now connect the precision movable short at the place of matched termination &
find out the minima for this setup.
6. Note and record the reference minima position of precision movable shortfrom
its micrometer. Let it be X
7. Remove carefully the movable short from the slotted line without disturbing its
current position. Place the phase shifter to the slotted line with its micrometer
reading at zero and then place the movable short to the other port.
8. The reference minima will shift from its previous position, rotate the micrometer
of movable precision short to get the reference minima again and note the micrometer
reading of movable short.
9. Now Open the phase shifter in suitable steps & record the corresponding
micrometer reading of movable short. Measure the phase shift as per the given
example.
CNTL
List of Experiment
To measure the Attenuation of line .

To measure input impedance of the line .
To measure the phase displacement between the current & voltage at
input of line .
To measure the frequency characteristic of the line.
Study of stationary waves .
To measure signal phase shift along the line .
To measure fault localisation within line.
Study of line under pulsed condition.
To measure the characteristic of a line
To study the Active High pass filter and to evaluate
C.N.T.L. LAB
EXPERIMENT NO:I
I.AIM
To measure the Attenuation of line
II.APPARATUS REQUIRED
C.N.T.L training kit, connecting probes, C.R.O Multimeter
III.THEORY
The ohmic resistance R & the conductance G are responsible for energy desputation in
the form of heat,These losses which determine the attenuation characteristics are expressed in
terms of attenuation “ a “and can be calculated by
a = 20 log (v2/V1)
IV.PROCEDURE
4. Adjust Ri and Rl for 18 ohm and 68 ohm respectively with help of DMM
5. Make connection as shown in fig
6. Set the sine wave frequency to approx 100 Khz and level to 0.4v
7. Oscilloscope ch I shows applied input ch II shows output
8. Measure signal level at input and at 25,50 75 and 100m length
9. Tabulate as under
)
Length (m) Vi ( input V2 (output )
25 .4v
50 .4v
75 .32v
100 .31v
7. Now calculate the attenuation in db at various lengths by the formula given below
a= 20 log v2/v1
8. The attenuation is approx -2db at 100 m
9. Try the same with open ended line and short ended line
V.RESULT
Attenuation of line is measured and is -2 db at 100m
C.N.T.L. LAB
EXPERIMENT NO:II
I.AIM
To measure input impedance of the line
C.N.T.L training kit,connecting probes,C.R.O Multimeter
III.THEORY
The input impedance of the line depends on the feature like the ohmic resistance the
conductance the inductance and the capacitance It also related to the resistance that loads the
line at the opposite end and to both the frequency and voltage of the signal.The purpose of the
first part of the test is to measure the input impedance of the line under different load condition
1.line terminated with matched load
8. open line
9. Short circuited line
IV.PROCEDURE
1) Adjust Ri and Rl for 18 ohm and 68 ohm respectively with help of DMM
2)Make connection as shown in fig
3)A 1 ohm resistance in series between the generator and the transmission line as
shown in fig allows to measure the value of i/p current
4)Set the sine wave frequency to approx 100 Khz and level to 0.4v p-p
5)Oscilloscope ch I shows applied input ch II shows output
10. Take the reading of vi and vm acress 1 ohm on oscilloscope
11. Calculate the input impedance according to the following formula
Z in =Vin/I =Vin/Vm
12. Change the frequency to 1 Mhz and note the value of vin and vm at this frequency
13. Note down these result.The input impedance at 100 Khz is around 80 ohm and at 1 Mhz
is around 50 ohm
Repeat the experiment with shorted and open line and use the following formula to
compute the impedance when line is open circuited Zoc and when short circuited Zsc
V.RESULT
Input impedance of line is measured at 100 Khz and 1 Mhz
C.N.T.L. LAB
EXPERIMENT NO:III
I.AIM
To measure the phase displacement between the current & voltage at input of line
III.THEORY
The Phase displacement between the current & voltage at input of line under the different load
condition viz Matched line open line and short circuited line
IV.PROCEDURE
1)Adjust Ri and Rl for 18 ohm and 68 ohm respectively with help of DMM

5) Set the oscilloscope to XY mode
6) Observe suitable Lissageous pattern on cro By adjusting v/div of each channel
7)The Lissajous pattern allows measuring the phase displacement between the two
signals through the ratio of the semi axis of the ellipse
8)The phase displacement is approx 15 0 at 100 Khz
V.RESULT
The phase displacement between the current & voltage at input of line is measured as 15 0
C.N.T.L. LAB
EXPERIMENT NO:IV
I.AIM
To measure the frequency characteristic of the line
III.THEORY
When the frequency of the i/p signal increases the line attenuation due to both the ohmic
resistance R and the conductance c Progressively increases because of the Skin effect Starting
from a given frequency onwards the line attenuation increases.The cut off frequency of the
line is defined as the frequency at which the attenuation reaches the level of -3db compared to
the low frequency level -3db is approximately down to 70%
The purpose of this test to measure the cutoff frequency for the coaxial line privided in st 2266
This measurement is provided with terminated line
IV.PROCEDURE
5) At this point ch I is reading 2 div deflection and ch II is reading 1.6 div (this due to
fix attenuation of the line )
10. Now vary the frequency of generator gradually keeping the input amplitude constant
(observe ch I and maintain 2 div deflection by adjusting AMP VAR controll ) till the
waveform at the end of 100 m line falls -(1.4 div of chII on the oscilloscope )
11. Note this frequency on the oscilloscope This frequency is known as the cutt off
frequency
12. For the cable used in this trainer this frequency is approximately 3.5 Mhz
V.RESULT
The cut off frequency is measured
C.N.T.L. LAB
EXPERIMENT NO:V
I.AIM
Study of stationary waves
III.THEORY
A line that has not been terminated with a load equal to its characteristic impedance is subject
to a reflection phenomenon of the power from the remote end the amount of the reflected
power depends on the amount of mismatch between the characteristic impedance of the line
and load impedance.In the extreme cases of short circuited line (RL= 0 ) and open line .a
situation of total reflection occure for either the current wave or the voltage wave .The study of
this test is to establishment of the stationary wave within the line
IV.PROCEDURE
1) Adjust Ri and Rl for 18 ohm and 68 ohm respectively with help of DMM
3)Set oscilloscope to 0.1 V/div for both channels
4)Adjust the sine generator for an o/p of 0.2 vpp 2 div Deflection on ch I ) aqnd at
frequency `100 Khz
Observe the peak to peak voltage on ch II at 100 m and at intermediate socket at 75 m
50m & 25m and 0m
5)Tabulate result as under
Distance
Vp-p
0m
2.0v
25m
2.0v
50m
1.9v
75m
1.8v
100m
1.6v
6) Calculate the stationary wave ratio 's' by the following formula
s= Vmax/Vmin
For 100 Khz s is approx 1.25
7) The reflection coefficient 'r' of the line shows how much of the energy is supplied at
the
i/p is being reflected as consequence of the load decoupling.The reflection coefficient
is normally expressed in percentage and can be determined from the stationary wave
ratio through the following formula
r=(S-1)/(s+1)
At 100 Khz is approx 11%
9) Repeat the same procedure for open line &short circuited line
10)Try the experiment with other frequencies to see the effect of free on 's'
V.RESULT
stationary waves is studied
C.N.T.L. LAB
EXPERIMENT NO:VI
I.AIM
To measure signal phase shift along the line
III.THEORY
The propagation of the electromagnetic waves through the vacuum occures at a speed
aproximately equal to the light speed (3*108 m/s) in a line the propagation speed is of course
reduced by the characteristic of the line like the capacity and the inductance
In particular in the coaxial lines the propagation speed of the electromagnetic waves is
approximately between 60 % &80% of the light speed as function of the line characteristic.The
objective of this test is to measure the phase displacement between the i/p signal and the o/p
signal for the line in the trainer whose length is 100 m.As a consequence the phase speed and
the phase delay will be calculated related to the phenomenon of electromagnetic waves
propagating along the line
IV.PROCEDURE
5) Set the oscilloscope to XY mode
6) Measure phase angle by ellipse formula
7) When the value of phase displacement has been determined through the
measurement the phase speed can be calculated on the basis of the following formula
v=f*l*360 /phase displacement
the phase speed can be also expressed in another way by pointing out its relationship
with the characteristic parameters of the line on the basis of v=l/( LC )1/2
The phase delay 't' is calculated from the ratio of the line length and phase speed t=l/v
V.RESULT
signal phase shift along the line is measured
C.N.T.L. LAB
EXPERIMENT NO:VII
I.AIM
To measure fault localisation within line
III.THEORY
The localisation of the fault within the line can be performed following different methods.The
method shown here for performing this test is of special interest being based upon the use of
the phenomenon of the establishment of stationary waves. Let us assume that the line is broken
at unknown points between two ends If the line is connected to signal generator the wave will
be reflected from the break point and a stationary wave condition is established between the
input and the break point the waves along the line have the maximum and minimum points at
regular intervals corresponding to ¼ of the wave length of the input signal For the fault to
pinpointed it is necessary to determine the frequency value at which a voltage minimum
occures at the i/p This frequency is noted as f1.The same operation is repeated at the remote
end of broken cable and obtaining f2 value These values are substituted in the following
formula l'=[f2/(f1+f2) ]*l
Where l=line length in meters
l' = distance in mts of the point of fault refferred to the input of the line.
IV.PROCEDURE
Make connection as shown in fig
Note that the line is broken at 50m length
Set oscilloscope channel I to 0.1v/div
Adjust the frequency variable control at the minimum position
Gradually increase the frequency and note the frequency at which the signal on CRO falls
minimum
This frequency is f1
Repeat the test at the other end of the line as shown in fig and note the frequency at which
signal on CRO falls to minimum This is f2
Enter these values in the formula and calculate the distance of break point from the i/p
For the fault generated at 50m f1 and f2 are 900Khz approx
V.RESULT
Fault localisation within line is measured
C.N.T.L. LAB
EXPERIMENT NO:VIII
I.AIM
Study of line under pulsed condition
III.THEORY
If the line is supplied with a pulsed signal and the line is not matched at the ends the pulses
sent into the line will be more or less reflected as function of the mismatch. The reflected
fraction of the pulse moves along the line in opposite direction to the generator and when the
charateristic impedance of the line is not matched to the impedance of the genarator it is again
reflected to the other end The purpose of this test is to study the propagation of the pulse edges
along the line under different matching condition viz open line short circuited line &matched
line
IV.PROCEDURE
Adjust Ri and Rl for 18 ohm and 68ohm respectively with help of DMM
Observe the input and output wave shapes and also amplitude levels on the oscilloscope
Now make the load open and repeat the same procedure
Again repeat the experiment forr short circuited load
Note the observation for all 3 condition of load and compare them
V.RESULT
line under pulsed condition is studied
C.N.T.L. LAB
EXPERIMENT NO:IX
I.AIM
To measure the characteristic of a line
II.Apparatus required
C.N.T.L training kit,connecting probes
III.Theory
The co axial line used for the transmission of electromagnetic waves consist of an external
conductor of cyllindrical shape with an inner conductor arranged along the axis of the former
The two conductors are seperated by electric material of suitable features
one of the advantages of this kind of lines is that these lines are intrinsically self sheilding due
to the geomentry of arrangement of the two conductor
Moreover the shielding features of the coaxial lines improves when the frequency increases
From the electric point of view a coaxial line can be considered as cascade of line trunks.Each
one of them can be represented as being composed of resistive inductive and capacitive circuit
elements of concentrated kind as shown in fig
The transmission characteristic of line are described in terms of propagation constant and of
characteristic impedance Z.These parameter are typical values for each single line .The same is
true for the capacitance and conductance for length unit In the telecommunication field these
values are generally expressed per meter or kilometer for practical reason
In this case the symbol used to indicate these magnitude are common symbols
This experiment measures the characteristic parameters such as R,L,G,C, A
and propagation constant for the transmission line included in this trainer
IV.Procedure
Both inductance and ohmic resistance of the line are measured in series by short circuiting end
of the line and connecting the measuring instruments to the start of the line The capacitance
and the conductance are measured in parallel by operating on the open line
The resistance R and the conductance G can be measured with ohmeter or DMM for the
conductance to be measured an ohmmeter is required which is able to perform resistance
measurements with range greater than 100 Mohm
5. For the measurements of series inductance L and the parallel capacitance c a LCR
meter or measuring bridge is required
6. The result of these measurements give the value of RLC and G referred to the cable
length that in out case is of 100 meter
7. Z0 can be measured by using the following formula Z0=(L/C)1/2
Result
The characteristic of line is measured
EXPERIMENT 10
Object :
To study the Active High pass filter and to evaluate :
4. Oscilloscope
Circuit Diagram :
Circuit used to study Active High pass filter shown in Fig 4.
Procedure :
10. Connect Ohmmeter between Test point Vin and Test point 1. Adjust resistance value to 1.59K by varying the
potentiometer 22K of Low pass filter to set the high cutoff frequency (fH) at 10K.
Analog Lab.
13. Connect a sinusoidal signal of amplitude 1V (p-p) of frequency 1KHz to Vin of Low pass filter from external
source or ST2612 Analog Lab.
14. Observe output on oscilloscope by connecting Test point Vout to oscilloscope.
16. Tabulate values of Vout, gain, gain (db) at different values of input frequency shown in observation Table.
Observation Table :
Input
Sr. Gain(db) = 20
(Hz)
1 100
2 200
3 500
4 1K(fL)
5 5K
6 10 K
7 15 K
8 20 K
14. Plot the frequency response of high pass filter using the data obtained at different input frequencies.
Resistance () Capacitance (uF) 3 db frequency (Hz)
800 0.01 20K
1.59 K 0.01 10K
15.9 K 0.01 1K
29. Low cutoff frequency fL = 1/2RC
30. Gain at Low cutoff frequency fL = 0.707 * AF
31. Gain (db) at Low cutoff frequency fH = 20 log |Vout / Vin| where
Vout = (2)1/2 * Vin
Results :
Pass band gain(Af)
Low cutoff frequency (fL)
Gain at 3db frequency (fL ) in db

Computer Network
LIST OF EXPERIMENTS
 MAC LAYER
76. To Study and perform ALOHA.
77. To Study and perform CSMA.
78. To Study and perform CSMA/CD.
79. To Study and perform TOKEN BUS
80. To Study and perform TOKEN RING.
1. DATA LINK LAYER
13. To Study and perform packet transmission.
14. To Study and perform Stop and wait protocol.
15. To Study and perform Sliding window protocol.
1. APPLICATION LAYER
 To Study and perform File transfer protocol.
INTRODUCTON TO LAN –TRAINER KIT
To successfully use the LAN Trainer, a number of hardware and software components
must be properly used together. Each PC acts as two nodes in the network. Both are
connected to the Network Emulator Unit via the same cable. Thus, with 3 PC’s you can
experiment with a 6-node network. On the software side, the screen is divided into 2
windows, one for each node. This is accomplished using the LAN Trainer control panel
running under Windows-98-2e/windows 2000SP2
NIU CARD
Each PC that is a part of the LAN Trainer setup must have an NIU Card plugged into it.
This card has two independent full-duplex serial channels each of which can operate at
data rates between 8kbps and 1Mbps. The card supports DMA as well as programmed
I/O data transfers. With one such card, a PC acts as a two independent network nodes.
Once it is properly installed, the serial card should not require further attention. The
data rate is set from the Network Emulator Unit, and all other parameters can be set by
software.
NETWORK EMULATOR UNIT
The Network Emulator Unit acts as a network interconnecting up to 6 network nodes(3

NIU Cards in 3 PC’s). Each card is connected to the Network Emulator Unit via a cable
with DB-37 connects. Once properly installed, these should not normally be disturbed.
The Network Emulator Unit has a number of jumpers that must be properly wired up
depending on the type of network one wants –a bus, a ring, a star. This must correspond
to the setting of the Topology selector switch. The Network Emulator Unit also has
selector switches for Data Rate, Bit Delay, Error Rate and Frame Error Rate. These
should be set in accordance with the instructions of each experiment. In addition, there is
a Reset switch, which should be used before every experiment, and in case of trouble.
This manual provides easy steps to perform the experiments. The user should be familiar
with the LAN Trainer Kit, about its selection switches and about the software ‘LAN
train’.
So before going to do experiments, refer Appendix of ‘User Manual given with the kit.
------------------------------------------------------------------------------------------------------------------
---------
MAC LAYER
EXPERIMENT NO. 1
AIM - To implement the ALOHA Protocol for packet communication between a number
of nodes connected to a common Bus.
APPARATUS- Experimental kit, Connecting probes, Computer systems.
PROCEDURE
STEP-1
Find out the inter packet arrival time Ta from the equation.
G = (N*P) / (C*Ta)
Where Ta = Inter packet delay.
P = Packet length in bits.
N = No. of nodes.
C = Data rate in bits per second.
G = Offered load.
The equation becomes-
G = [ N*(P * 8)] /(C* Ta)

OR
Ta = [ N*(P*8)] / (C*G)
Here Packet length is multiplied by 8 in order to convert in bits.

Find the values of Ta by varying the offered load (G) by assuming the values of G from
0.1 to 4.
STEP-2
Set the following Parameters in Configuration windows (under the software dialog box in
configure pull down menu ) for all nodes.
Node ID = 0 for node 1 , 1 for node 2 (in each PC)
Baud rate(C) = 8kbps.
Direction = Sender for all nodes.
STEP-3
Substitute value of Ta in the Inter Packet Delay text box for any value of G, which you
have calculated from the above given formula.
STEP-4
Substitute Packet length(P) as 100 bytes(in the same dialog box) and the duration (D) of
the experiment as 100 sec. in the general dialog box under configure pull down menu.
Set the protocol as ALOHA. Set all these parameters in all the nodes.
STEP-5
First boot the NIU CARD after setting all parameters.
Start running the experiment. At the end of 100 sec all the nodes would have been
stopped in the transmission. This can be visualized at the top of the window.
STEP-6
Note down Tx packets and the collision count of all nodes.
Calculate the throughput form the readings.
Successfully Tx packets by a node = [ Tx packets – Collision count]
Throughout (X) =
Sum of successfully Tx packet of all nodes * P bytes * 8 / D sec* C bps
STEP-7
Repeat the above steps for different values of Ta, for different values of G (as mentioned
above).
Find throughout as above form the readings taken by varying Ta. G can also be
calculated the same way as throughput by using the sum of Tx packets.
STEP-8
Try to draw the throughput (X) Vs Offered load (G ) curve of ALOHA and find the peak
throughput and compare with graph given in the manual.
STEP-9
Using the equation –
X – G * e^ (-2G) and calculated G, find out X and plot the curve between X and G.Compare
this curve (theoretical) with that found in STEP-8 (Practical).
Formulae used:
G = (N*P)/(C*Ta)
Where
Ta = Inter Packet Delay
N= No. of nodes.
C= Data rate in bits per second.
G = Offered load.
2. Successfully Tx packets by a node = [Tx packets – Collision Count]
3. Throughput(X) =
Sum of successfully Tx Packet of all nodes * P* 8 /D sec* C bps
4. X = G * e^ (-2G)
OBSERVATION:
Table for X Vs G –
Tx=Successfully
Sr.No. G %G Ta Transmitted %X
packets
Exercises:
Repeat the above experiment for different values of N no. of nodes,

P-packets length and C- data rate.
2. Generate asymmetric traffic patterns by setting different packet lengths for various
nodes. Measure the throughput as above.
3. Other excercises suggest modifying or adding the source codes, compiling and
running. These can be taken up once the user becomes more familiar with the kit and
networking concepts.
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EXPERIMENT NO-2
AIM - To implement the CSMA Protocol for packet communication between a numbers
of nodes connected to a common Bus.
PROCEDURE
STEP-1
G = (N*P) / (C*Ta)
N = no. of nodes.
G = Offered load.
G = [N*(P * 8)] /(C* Ta)

OR
Ta = [N*(P*8)] / (C*G)
Find the values of Ta by varying the offered load (G) by assuming the values of G
from 0.1 to 4.
STEP-2
Set the following Parameters in Configuration windows (under the software dialog
box in configure pull down menu) for all nodes.
Node ID = 0 for node 1, 1 for node 2 (in each PC)

Bit delay = 0 bit (in NEU)
STEP-3
Substitute value of Ta in the Inter Packet Delay text box for any value of G, which
you have calculated from the above given formula.
STEP-4
Substitute Packet length(P) as 100 bytes(in the same dialog box) and the duration (D)
of the experiment as 100 sec. in the general dialog box under configure pull down
menu.
Set the protocol as CSMA . Set all these parameters in all the nodes.
STEP-5
STEP-6
Successfully Tx packets by a node = [Tx packets – Collision count]
Throughout (X) =
STEP-7
Repeat the above steps for different values of Ta, for different values of G (as
mentioned above).
Find throughout as above form the readings taken by varying Ta . G can also be
STEP-8
Try to draw the throughput (X) Vs Offered load (G ) curve of CSMA and find the
peak throughput and compare with graph given in the manual.
STEP-9
Increase the bit delay and take down the readings and calculate X and G. Repeat this step
for various delays (up to 15 bit delay). Plot all these curves
and compare them for the effect of increase in the distance. Show that the throughput of
CSMA is better compared to ALOHA.
STEP-10
Find the throughput from the theoretical equation.
X = G * e^ (-a G)
Where a = (bit delay * N) / P
N = No. of nodes used in the experiment.
Plot the curve X and G .Compare this curve (theoretical) with that found in STEP-8.
Formulae used
G = (N*P)/(C*Ta)
Where
Ta = Inter Packet Delay.
N = No. of nodes.
G = Offered load.
Successfully Tx packets by a node = [Tx packets – Collision Count]
Throughput(X) =
Sum of successfully Tx Packet of all nodes * P* 8 /D sec* C bps
X = G * e ^ (-a G)
Where a = (bit delay *N) / P
N = no. of nodes used in the experiment.
P =Packet length in bits.
OBSERVATION:
Table for X Vs G at different bit delays:
Bit delay = 0 bit
Tx=Successf
Sr.No. G %G Ta ully %X
Transmitted
packets
(b) Bit delay = 5 bit
Tx=Successf
Transmitted
packets
From such tables for other none zero bit delays as per your requirement.
Tables for X Vs G at various Data rates viz. 8, 16, 32 kbps etc.
Tx=Successf
Transmitted
packets
Don’t forget to amend the values of data in the formulae.

Excercises:
Repeat the above experiment for different values of N-no. of nodes, P-packet length
and C-data rate.
Generate asymmetric traffic patterns by setting different packet lengths for various
Other excercises suggest modifying or adding the source codes, compiling and
(Please refer the user manual as well as programmer manual also)
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EXPERIMENT NO. 3
AIM - To implement the CSMA Protocol for packet communication between a

numbers of nodes connected to a common Bus.
PROCEDURE
STEP-1
G = (N*P) / (C*Ta)
N = no. of nodes.
G = Offered load.
G = [N*(P * 8)] /(C* Ta)

OR
Ta = [N*(P*8)] / (C*G)
Find the values of Ta by varying the offered load (G) by assuming the values of G
from 0.1 to 4.
STEP-2
Set the following Parameters in Configuration windows (under the software dialog
box in configure pull down menu) for all nodes.
Node ID = 0 for node 1, 1 for node 2 (in each PC)

Bit delay = 0 bit (in NEU)
STEP-3
Substitute value of Ta in the Inter Packet Delay text box for any value of G, which
you have calculated from the above given formula.
STEP-4
Substitute Packet length (P) as 100 bytes (in the same dialog box) and the duration
(D) of the experiment as 100 sec. in the general dialog box under configure pull down
menu.
Set the protocol as CSMA /CD. Set all these parameters in all the nodes.
STEP-5
STEP-6
Successfully Tx packets by a node = [Tx packets – Collision count]
Throughout (X) =
STEP-7
Repeat the above steps for different values of Ta, for different values of G (as
mentioned above).
Find throughout as above form the readings taken by varying Ta. G can also be
STEP-8
Increase the bit delay and take down the readings and calculate X and G. Repeat this step
for various delays (up to 15 bit delay). Plot all these curves
and compare them for the effect of increase in the distance. Show that the throughput of
CSMA / CD is better compared to ALOHA or CSMA.
STEP-9
CSMA / CD is more complex than ALOHA and CSMA. But the throughput can be
approximated by-
X = 1 / (1+ K * a)
Where k is a constant that depends on various parameters such as back-off algorithm.
Typically K ranges from 3 to 6 for real CSMA /CD networks. For different parameter
values, find the value of K that best fits your measurements.
Show that CSMA/CD is better compared to ALOHA or CSMA.
Formulae used-
G = (N*P)/(C*Ta)
Where
Ta = Inter Packet Delay.
N = No. of nodes.
G = Offered load.
2. Successfully Tx packets by a node = [Tx packets – Collision Count]
3. Throughput(X) =
[Sum of successfully Tx Packet of all nodes * P* 8] / [D sec* C bps]
4. X = 1 / (1+ K * a)
Where k is a constant.
a = (bit delay * N) / P
Where N = no. of nodes used in the experiment.
P = packet length in bits.
OBSERVATION :
1. Table for X Vs G at different bit delays:

(a) Bit delay = 0 bit
Tx=Successfully
packets
(b) Bit delay = 5 bit
Tx=Successfully
packets
The values of offered load & IPD can be viewed from node windows.
Form such tables for other nonzero bit delays.
Exercises:
Repeat the above experiment for different values of N-no. of nodes , P-packet length
and C-data rate.
Generate asymmetric traffic patterns by setting different packet lengths for various
Other exercises suggest modifying or adding the source codes, compiling and
(Please refer the user manual as well as programmer manual also)
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EXPERIMENT NO. 4
AIM- To implement a token passing method for a bus LAN.
PROCEDURE-
STEP-1
Open the windows of the icon TOKEN BUS in the various nodes. Suppose you have
opened 4 nodes.
STEP-2
Open the configuration window of each node and feed the followings :
Node ID = 0 & 1 for two windows in each PC.
Protocol = CSMA/CD
Duration = 100sec.
Packet length = 100 bytes.
Inter packet delay = 3200 ms.
Data rate = 8000 bytes.
My address = 0,1,2,3…in different nodes.
Remain rest fields as it is.
STEP-3
Boot all nodes and start.
A block asking fro THT(token holding time) will appear.
Fill 5000 ms. in all nodes.
STEP-4
Click OK to node of ‘my address’= 1,2,3… and at the end click OK to node of ‘my
address’= 0 .
STEP-5
After completion of experiment note the readings coming in the window of each node viz.
successfully transmitted packets and avg. delay.
STEP-6
Calculate offered load, throughput and avg. delay
Offered load G = (N * P ) /(C * Ta )

Throughput(X) = Sum of successfully Tx packet of all nodes * P bytes * 8 / D sec * C
bps.
Avg. delay = Sum of avg. delays of all nodes / no. of nodes.
STEP-7
Repeat steps 1-6 for Inter Packet delay 1600,800,400,200ms etc.
STEP-8
Plot graphs of
Throughput Vs Offered load.
Average delay Vs throughput.
STEP-9
Repeat the above steps for various THT viz. at 0, 1000, 2000, 6000, 8000 ms.
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EXPERIMENT NO. 5
AIM- To implement a token passing access method for a ring LAN.
PROCEDURE-
STEP-1
Set patch cords for ring topology on NEU. (Consider installation manual)
Select topology selection switch as ‘RING’ on NEU.
STEP-2
Open the windows of the icon TOKEN RING in the various nodes.
Suppose you have opened 4 nodes.
Open the configuration window of each node and feed the follwings:
Node ID = 0 & 1 for two windows in each PC
Protocol = Ring
Duration = 100sec.
Packet length = 100 bytes.
Inter packet delay = 3200ms.
Data rate = 8000bps.
No. of nodes = 4.
Remain rest fields as it is.
STEP-3
Boot all nodes and start.
A block asking for THT (token holding time) will appear.
Fill 5000ms. in all nodes.
STEP-4
Click OK to all nodes one by one.
STEP-5
After completion of experiment note the readings coming in the window of each node viz.
successfully transmitted packets and avg. delay.
STEP-6
Calculate offered load, throughput and avg. delay
Offered load G = (N * P ) /(C * Ta )

Throughput(X) =
Sum of successfully Tx packet of all nodes * P bytes * 8 / D sec * C bps.
Avg. delay = Sum of avg. delays of all nodes / no. of nodes.
STEP-7
Repeat steps 1-6 for Inter Packet delay 1600,800,400,200ms etc.
STEP-8
Plot graphs of
1. Throughput Vs Offered load.
2. Average delay Vs throughput.
STEP-9
Repeat the above steps for various THT viz. at 0, 1000, 2000, 6000, 8000 ms
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DATA LINK LAYER
EXPERIMENT NO. 6
AIM- To transmit packets from one node to another. On node, the sender reads a message from
the key board and transmits it in a single packet. The other node, the receiver receives the
packet and writes the message to the display.
APPARATUS - Experimental kit. Connecting probes.
PROCEDURE-
STEP-1
Open two windows of the icons ‘PKT’ .You can choose the two windows in the same PC or
in different PC’s.
STEP-2
Open configuration view windows and feed the followings in both.
Node ID =0 & 1 (if you are using same PC)
=no need to change if you are using different PC’s

Inter packet delay= 40ms
Direction = sender in one node and receiver in another node
My address =0 for sender, 1 for receiver.
Click Ok for both the nodes.
STEP-3
Boot both the nodes. Start first receiver then sender.
Sender will ask for the destination address. Feed ‘1’ in the blank space as my address of
receiver is 1.
STEP-4
Sender will ask for the string. Type your message in the space and enter.The message will
reach to the receiver window and will be displayed.
STEP-5
You can give more messages in the same way.
STEP-6
Check the Tx and Rx packets and corresponding bytes.
STEP-7
Repeat the above experiment with various bit error rates (selection switch on NEU).
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EXPERIMENT NO. 7
AIM - To provide data transfer between two nodes over an unreliable network using stop
and wait protocol.
APPARATUS- Experimental kit, Connecting probes.
PROCEDURE-
STEP-1
Node ID = 0 &1 (if you are using same PC)
= no need to change if you are using different PC’s
Direction = sender in one node & receiver in another node
Protocol = CSMA/CD
Duration (D) =100sec.
Packet length (P) =100bytes
IPD = 40ms
Data rate (C) = 8kbps
BER = 0(in the NEU)
Bit delay = 0(in the NEU)
STEP-2
Run the experiment through start-run command.
STEP-3
Give the timeout value to 250ms when prompted by the sender (run the receiver first
before starting the sender).This is reliable protocol. These protocols involve
acknowledgement also and therefore the duration of the experiment is utilized to transmit
the packet and to receive the acknowledgement.
STEP-4
Calculate the transmission time of data packet and its acknowledgement. Duration of the
experiment divided by Tx packet count of the sender will give this. Since the data rate is
known, time taken to send this packet with the excess time indicates the software overload.
STEP-5
Find the best time out for the given packet length and the data rate by varying the timeout
values say from 100ms to 500ms.
STEP-6
Set the BER to non-zero value say 10^(-5).There will be time outs and retransmission and hence a
reduction in throughput. Throughput can be calculated using the Rx data packets of the receiver i.e.
X=(Rx data packets * Packet length *8)/(Duration*Data rate)
STEP-7
Plot the timeout Vs throughput.
STEP-8
For various BER’s find the throughput and plot BER Vs throughput.
STEP-9
Theoretically the throughput may be given by
X=D/[P+A+2C(1+Tau)]
Assuming there are no errors and the sender always has data to transmit and the users the fixed length
packet(to assume heavy traffic condition).
D is the no. of data bits in a packet.
P is the total no. of bits per packet= sum of D and header bits.
A is the no. of bits in an acknowledgement packet.
I is the processing time per packet.
Tau is the one-way propagation delay.
Tau can be assumed as 1 microsecond. If 0 bit delay is used.
If bit delays are used in between the nodes then
Tau=(N*bit delay)/C
Assume A=H=8 bytes and the X measured as above calculate the processing time’I’.
Formulae used:
Practical transmission time=Duration/Tx packet of sender

Theoretical transmission time=Packet length/Data rate.
X= (Rx data packets*Packet length*8)/(Duration*Data rate)
Theoretical X=D/[P+A+2C(1+Tau)]
Where D is the no. of data bits in a packet.
P is the total no. of bits/packet=sum of D and header bits.
A is the no. of bits in an acknowledgement packet.
I is the processing time/packet.
Tau is the one-way propagation delay.
Tau can be assumed as 1 microsecond if 0 bit delay is used.
If bit delays are used between the nodes then
Tau = (N*bit delay)/C
Assume A=H=8 bytes and the X measured as above

Calculate the processing time ‘I’.
OBSERVATIONS:
Use steps 1, 2,3,4,5 for the calculation of practical transmission time.
Calculate theoretical transmission time using formulae:
Transmission time=Packet length in bits/Data rate in bps.
Compare these practical & theoretical times.
3. Table for throughput at various IPD’s at BER=10^5(see step 5).
Sr. No. Ta Rx=Received %X

Packets
4. Table for throughput at various Timeout values at BER=0(see step 6)
Sr.No. Timeout Rx=Received %X

Packets
5. Table for throughput at various BER values (see step 8)
Sr.No. BER Rx=Received %X

Packets
6. Calculate theoretical throughput at various bit delays (see step 9)
Other exercises suggest modifying or adding the source codes, compiling and running the experiment.
These
can be taken up once the user becomes more familiar with the kit and the networking concepts.
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EXPERIMENT NO 8
AIM- To provide data transfer between two nodes over an unreliable network using sliding
window protocol.
APPARATUS-Experimental kit. Connection probes.
PROCESDURE-
STEP-1
Node ID = 0 &1 (if you are using same PC)
= no need to change if you are using different PC’s
Direction = sender in one node & receiver in another node
Protocol = CSMA/CD
Duration (D) =100sec.
Packet length (P) =100bytes
IPD = 40ms
Data rate (C) = 8kbps
No of packets=4/5/6/7
BER=0(in the NEU)
Bit delay = 0(in the NEU)
STEP-2
Run the experiment through start-run command.
STEP-3
Give the timeout value to 250ms when prompted by the sender (run the receiver first
before starting the sender).This is reliable protocol. These protocols involve
acknowledgement also and therefore the duration of the experiment is utilized to transmit
the packet and to receive the acknowledgement.
STEP-4
Note the total time taken. Calculate the transmission time per data packet. How does this
compare to the corresponding time with stop and wait above.
STEP-5
If there are no errors, the sender always has data to transmit, the windows size is large
enough that the sender never has to wait, and it uses fixed- lending packets(heavy traffic
assumption) the sender is able to transmit data packet continuously, separated only by
some processing time. The throughput is given by:
X=D/ (P+I)
STEP-6
Find the best time out for the given packet length and the data rate by varying the timeout
values say from 100ms to 1500ms.
STEP-7
If the network has a BER of p (the probability of a packet error) &
L= (1-P) ^p if the window size is large, the theoretical throughput is given by:
X= (I-L) D/ (P+I)
STEP-8
Plot the timeout Vs throughput.
STEP-9
For various BER’s find the throughput and plot BER Vs throughput.
Compare these graphs with that of stop & wait.
Formulae used:
1. Use steps 1, 2,3,4,5 for the calculation of practical transmission time.
2. Calculate theoretical transmission time using formulae.
Transmission time=Packet length in bits/Data rate in bps.
Compare these practical &theoretical times.
3. Table for throughput at various IPD’s at BER=0(step 5)
Sr. No. Ta Tx=Transmitted packets I=Duration/Tx X=D/

(P+I)
4. Table for throughput at various BER values (see step 6)

Sr.No. BER(p) L=(1-P) ^p Tx I=Duration/ Tx X=(I-L)D/
(P+I)
Make tables for steps 7, 8 &9 yourselves.

Other exercises suggest modifying or adding the source codes, compiling and running the experiment.
These
Can be taken up once the user becomes more familiar with the kit and the networking concepts.
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APPLICATION LAYER
EXPERIMENT NO 9
AIM-To check how the file is transferred from one node to another node and also how to
retrieve node.
APPARATUS- Experimental kit. Connecting probes.
PROCEDURE-
STEP-1
Select two nodes one as sender and other as receiver (in different PC’s)
STEP-2
Configure both nodes with desired parameters.
Duration =100sec.
Protocol = CSMA/CD
Inter packet delay = 1000 ms (choose accordingly)
My address =’1’ for sender and ‘2’ for receiver.
STEP-3
Run the experiment through start run command. The important point is you have to first
start the receiver.
STEP-4
You will find option for ‘1’ sends & ‘2’ get in sender windows. Select 1 for sending any file.
But before doing this, you have to make one file.
STEP-5
You will find the message as “Enter the file name’
Give the file name with path, which you have made earlier (which is saved in sender PC)
Now you enter the correct path of the file into the ‘Enter the file name text box’.
STEP-6
You will find ‘Enter the time out value’ for example: give any value say 2500ms.
Click Ok and wait for completion. You can see the display message on both windows.
STEP-7
You can see the received file on Desktop the receiver PC, after closing the receive & sender
windows.
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TV &RADAR LAB
EXPERIMENT- 1
OBJECTIVE- To study the circuit description of RF–Section (Tuner section).
The RF-Section is mainly consisting of RF Tuner. This tuner has RF amplifier, a

mixer and a local oscillator.
The antenna receives the radio frequency (RF) waves from the atmosphere and
converts them into corresponding signal variations. These RF variations are fed to RF
tuner. The input impedance of RF Tuner is 75 ohms. The antenna system and co-axial
cable should be properly matched. If a co-axial cable of 75 ohms impedance is
employed, there is no need of any extra matching device between cable and antenna
socket at the receiver. But in case of a feeder wire of 300 ohms is employed, and then
an impedance matching transformer (300–75ohms) is added between feeder and
antenna socket at the receiver. There is also a need of impedance matching between
output terminals of antenna and co-axial cable or feeder wire. The RF tuner selects the
signal of the desired channel amplifies it and converts in to Intermediate frequencies
(IF). The video IF is at 38.9MHz and sound IF is at 33.4MHz.
Tuner section has +12V approx. supply voltage at TP14 (MB). This voltage is used
for all the operations in this section +12V is provided from horizontal output section.
Transistors QA02, QA03, QA04 (BC558) are used to selecting the desired band from
tuner section. To switch on these transistors approx. 10.8V is provided at their base.
Output is obtained at IF terminal (TP20). AGC Voltage (2.8V approx.) is obtained
from pin 11 of IC7680 (IC101). This voltage is used for automatic gain controlling
purpose. AFT voltage is provided from pin 13 of IC7680. It is available at TP16.
Tuning pulse output from system control IC is fed in to the base of transistor Q903
(BC547). Which switch on the transistor and so tuning voltage is 0-33V approx. is
obtained at TV terminal (TP19).
Following are the various terminal of RF tuner, which are provided in the form of test
point (TP) in our trainer kit.
UB : The system control IC provides the UHF band selection voltage. This
voltage switch ON the transistor, hence UHF band is selected.
HB : VHF band III selection voltage available from system control IC through
switching transistor at HB pin.
LB : VHF band I selection voltage available at LB pin from system control IC
through switching transistor.
TU : Channel selection voltage is available at this pin through transistor. It is
varying from 0-33V during channel selection.
AGC: Automatic Gain Control voltage is available at this pin from IC7680.
AFT : Automatic Fine Tuning voltage is available at this pin from IC7680.
MB : It is tuner section's Power Supply pin. Here 12 volt approx. is available.
IF : Intermediate frequency output signal from tuner is available at IF pin
Experiment 2
OBJECTIVE- To study the RF section through test points.
TP21 Blue :
Tuner section (UB) 10.8V approx. if UHF band is selected otherwise 0V.
On selecting the UHF band system control IC feeds UHF band switching output from
pin 3 (10V approx) so 10.8V approx. is obtained here (for other band selection it is
0V)
TP19 Blue :
Tuner section (TU) selection 0-8V approx varying during channel.
Pin 33 of system control IC provides the tuning pulse output to TV terminal through
transistor Q903 (BC547)
TP18 Blue :
Tuner section (HB) otherwise 0V (VHF III) 10.8V approx. if VHF III band is
selected.
On selecting the VHF III band system control IC feeds VHF III band switching output
from pin no. 2 (10V approx.). So 10.8V approx. is obtained here & (for other band
selection it is 0V)
TP20 Blue :
Tuner section 6.8V approx (AGC) adjustable.
This voltage is used for automatic gain controlling purpose and coming from IC7680.
TP17 Blue :
Tuner section (LB) 10.8V approx. if VHF I band is selected otherwise 0V (VHF I)
On selecting VL band system control IC provides VL band I switching output from
pin 1 (10V approx.) So 10.8V approx. is obtained here & for other band selection it is
0V.
TP16 Blue :
Tuner section AFT. 5.7V approx.
This voltage is obtained from pin 13 of IC7680 for the purpose of automatic fine
tuning.
TP14 Red :
Tuner section (MB) 11V approx supply for Tuner section.
It is obtained from Horizontal output section.
TP15 Red :
Tuner section (IF) Tuner Output signals according to band selection.
EXPERIMENT – 3
OBJECTIVE- To study the fault simulation and step-by-step fault finding procedure of RF
section.
Fault Insertion :
Fault 1 : No picture only low contrast snow on screen.
Fault Insertion: Remove the shorting shunt from 2&3 pin and place it between pin
1&2 of jumpers J1
Symptoms : Even antenna is connected but then also there is no picture only sound is
present with low contrast.
Fault Section : Tuner Section
Procedure :
• Check power supply at TP14 (MB) of tuner section, it should be +12V if not
• Then Check +12V supply at TP13 if it is OK
• Remove the shorting shunt from pin 1&2 and place it between pin 2&3 of
jumpers J1.
• Result : Now you should get +12V at TP14.
Fault 2 : No picture, No transmitting sound.
Fault Insertion : Remove the shorting shunt from 2&3 pin and place it between pin
1&2 of jumper J3
Symptoms : No picture, No sound and tuning is not possible.
Fault Section : Tuner Section.
Procedure :
• Check the voltage at TP4(33V approx) if it is not present then,
• Track may be open or components are faulty.
• Remove the shorting shunt from pin 1&2 and connect it between 2&3 of jumper
J3.
• Result : Now you should get picture with OK sound.
Fault 3 : No Picture, No transmitting sound.
1&2 of jumper J4
Symptoms : No picture, there is only snow on & tuning not possible
Fault Section : Tuner section.
Procedure :
• First check the antenna wire and antenna. If it is properly connected then
• Select the auto tuning mode. It starts with VL Band
• During VL Band tuning period 12V will be obtained at TP-17,
• During VH Band tuning period 12V will be obtained at TP-18
• During VHF Band tuning period 12V will be obtained at TP-21, if it is not
happening then,
• Check voltage at collector of transistors QA02, QA03, QA04 it should be 12V,
if it is OK then,
• Check the voltage at Emitter of transistor QA02, QA03 and QA04, it should be
12V if it is OK then
• Transistor may be faulty or track may be open between TP-13 and emitter of
transistor, QA-02, QA-03, and QA-04.
• Remove the shorting shunt from pin 1&2 and place it between 2&3 of jumper
J4. Fault Insertion : Remove the shorting shunt from 2&3 pin and place it between pin
1&2 of jumper J3
Symptoms : No picture, No sound and tuning is not possible.
Fault Section : Tuner Section.
Procedure :
• Check the voltage at TP4(33V approx) if it is not present then,
• Track may be open or components are faulty.
• Remove the shorting shunt from pin 1&2 and connect it between 2&3 of jumper
J3.
• Result : Now you should get picture with OK sound.
Fault 3 : No Picture, No transmitting sound.
1&2 of jumper J4
Symptoms : No picture, there is only snow on & tuning not possible
Procedure :
• First check the antenna wire and antenna. If it is properly connected then
• Select the auto tuning mode. It starts with VL Band
• During VL Band tuning period 12V will be obtained at TP-17,
• During VH Band tuning period 12V will be obtained at TP-18
• During VHF Band tuning period 12V will be obtained at TP-21, if it is not
happening then,
• Check voltage at collector of transistors QA02, QA03, QA04 it should be 12V,
if it is OK then,
• Check the voltage at Emitter of transistor QA02, QA03 and QA04, it should be
12V if it is OK then
• Transistor may be faulty or track may be open between TP-13 and emitter of
transistor, QA-02, QA-03, and QA-04.
J4.
Result : Now you should get possible tuning and get picture.
Fault 4 : VH Band is not selected
Fault Insertion : Remove the shorting shunt from pin 2&3 and place it between pin
1&2 of jumper J5 Symptoms : No picture, no transmitting sound, only snow.but signal
received from
antenna in VH band. Is of good quality.
Procedure :
• First check the voltage at TP-13, it should be 12V approx, if it is not present
then,
• Check the voltage at TP18, if it is not present then,
• Check the voltage at transistor QA03, if it is not present then,
• Transistor may be faulty or track may be open between emitter of Transistor
QA03 & TP13.
• Remove the shorting shunt from pin 1&2 and place it between 2&3 of
jumperJ5.
• Result : Now you will get VH Band selected & good picture too.
Fault 5 : Picture tilted to one side. Sound OK.
1&2 of jumpers J6
Symptoms : Horizontal shaking is observed in the picture. (AGC preset is at higher
side)
Fault Section : Tuner section
Procedure :
• Vary the preset of AGC. If variation of picture is not found to be OK then.
• Check the voltage variation by keeping the test point at TP-20 by varying the
preset VR151. If no variation is present, check the preset. If it is proper then.
• Resistance R105 may be faulty, If it is OK then,
• Check the continuity between R105 and TP20. If it is not proper then.
J6.
• Result : Proper picture without any shaking symptoms is observed.
Experiment-4
OBJECTIVE - To study the detail circuit description of VIF section.
In VIF section of B/W T.V. Trainer ,one common IC TDA 8303 is used. Inbuilt VIF,
SIF, Horizontal Oscillator & Vertical Oscillator are present within this IC. The sub
Section of VIF block present within this IC are as mentioned below:-
54. VIF Amplifier Section
55. Video Detector section
56. RF ,IF,AGC&AFT Generator section
57. Video Amplifier Section
If signal obtained from TP14 (On tuner section) is given to base of preset IF amplifier
Transistor through Resistor R101 (47E) & Capacitor C102 (10K). The supply to the
Collector of transistor is fed through Resistor R110 (470E),R107(470E) & coil (L101).
For proper base biasing of the transistor, the supply is given through Resistor R 102
(4K7), R103 (1K) and emitter ground . The amplified signal obtained from the collector
of the transistor is given to the saw filter through capacitor C103 (0.1MF). Saw filter
now filter the IF signal . The signal is fed to Pin No. 8 & 9 of IC TDA 8303 through
saw filter. The IF signal from Pin No. 8 & 9 of the IC is given to IF amplifier section.
The IF amplifier section now amplifies the IF signal up to the peak level. The amplified
Signal is now fed to in built detector of the IC. Detector section detects this IF signal i.e.
It separates the IF signal to 2 parts viz . video IF signal is given to the video demodulator
Section built in within the IC. Video demodulator section demodulates the signal i.e. carrier
Frequency is separated from the video IF signal.
In this video signal, SYNC signal is also present which is termed as composite video
signal
-
AGC Generator section is a sub section of VIF in built within IC TDA 8303. Such that
the gain of RF signal can be controlled within the tuner.
Experiment-5
OBJECTIVE- To study the fault simulation and step-by-step faul

Finding procedure of VIF section.
Symptom: AGC preset does not work properly.
Fault section: Horizontal . Osc. Vertical. Osc., AFC, Sync, VIF,SIF Sect
1. check the variation of voltage at pin No. 1of IC 101. It should be between 2.2V &7.8V .
If it is not proper IC may be faulty otherwise.
2. the link between IC pin and preset VR101 is open.
3. Remove the short shunting between 1&2 and connect it between 2&3.
Experiment-6
OBJECTIVE- To study the circuit description of SIF section /sound

output section.
In this B/W TV Trainer IC TDA 8303 is used in SIF section which consists of following sub
section:-
81. SIF Amplifier section
82. FM Detector section
83. Audio pre Amplifier section
84. Electronic Attenuator (Volume Control)
The SIF signal is separated from the composite video signal obtained from pin No.17 of IC
TDA 8303. It is fed back to the pin No.15 of the same IC through a capacitor C 301 (68PF),
Ceramic filter x 301 (5.5MHz) and capacitor C302 (10KPF). SIF amplifier gets this SIF signal
from pin no. 15 of IC and amplifiers the signal up to the peak level. This amplified version of
SIF signal is given to the in built SIF Detector (FM Detector) section.
The main function of this section is to separate the carrier frequency from the SIF signal . The
carrier frequency SIF signal is termed as “Audio Signal”. This Audio signal is then feed to the
audio amplifier section of the IC TDA 8303. Amplifier section amplifies the audio signal and
passes it to the volume control sub section. The purpose of volume control is to control the
audio signal. To perform this control operation, volume control signal is given to pin No. 11 of
IC TDA 8303 Through pin No. 39 of system control IC.
This controlled audio signal is taken out from pin No. 12 of IC TDA 8303 and given to the
sound output section.
Experiment-7
OBJECTIVE- TO STUDY THE CIRCUIT DESCRIPTION OF

SOUND OUTPUT SECTOIN.
In this B/W TV Trainer, IC TDA 2611 is used in the sound output section . This is a 9 pin IC
which consists of following sub section:-
 Sound (audio) driver
 Sound output
The controlled signal obtained from pin No. 12 of IC TDA 8303 of SIF section is given to pin
No.7 through resistance R 303 (68E) &capacitor C 306 (0.022MFD 50V). The audio driver in
built within this IC get the signal. The purpose of the audio driver section is to amplify the
signal. The amplified version of the audio signal is further sent to the audio output section
which is also in -
built within the IC. Audio output section amplifies this audio signal up to the peak level . The
amplified signal is taken out from pin No. 2 of IC TDA 8303 and provided to the speaker
through capacitor C 310 (220 MFD 50V). proper audio is obtained from the speaker. The
supply of +18V is given to the pin No. 1 of the IC and pin No. 4 & 6 are grounded together.
Experiment-8
OBJECTIVE - To study the fault simulation and step-by-step

Finding procedure of sound section.
Symptom: No sound with proper picture

Fault section: sound section.
1.check the voltage at T.P.2. it is 19v dc approx. if proper voltage is obtained.
2.check the same voltage at T.P,3. Also. If it is not present here.
3. remove the shorting shunt between 2&3 and connect it between 1&2
Symptom: No sound with proper picture

Fault section: sound section.
1.check the sound signal at pin No.2 of IC 301.if proper.
2. place the volume control at mid position.
3.check the sound signal at pin No.2 of IC301 on oscilloscope, varying signal is
obtained.
Experiment-9
OBJECTIVE- To study the simulation and step-by-s Finding procedure

of video sect.
Symptom: plain raster on retrace line with line proper sound .
Fault section: video section.
1.check the boost voltage in horz o/section at diode D-601 +95v dc(approx) is
obtained here .If it is present.
2.Check the same voltage at D-201.If it is proper.
3. Check the voltage at collector terminal of Q203+16V dc (approx) is present .If it is

not proper.
4.remove the shorting shunt between 1&2 and connect it between 2&3.
Symptom: plain raster on retrace line with line proper sound .
Fault section: video section.
1.Check the blanking pulse at T.P,21. If it is proper.
2.check the same pulse at T.P.23.if it is proper
3.check the blanking pulse once more at the collector terminal of transistor
Q203. If it is not present.
4. remove the shorting shunt between 1&2 and connect it between 2&3.
Experiment-10
OBJECTIVE- To study the circuit description of (EHT) Horizontal

output section.
In this B/W T.V. Trainer, two transistors are being used in the EHT section out of these
Two. One is horizontal (line) driver transistor and the other one is horizontal (line) output
transistor.
The line signal obtained from pin No.26 of the IC TDA 8303 is further given to the base of
line driver transistor Q601. This is an NPN transistor. Positive supply is given to the
collector terminal of it through primary winding of line driver transformer and
resistance R606(82E). the emitter terminal of it is grounded. The function of this transistor
is to amplify the line signal. The amplified version of line signal is taken out of the
collector and is given to the primary winding of the line driver transformer .by the
process of natural induction, the signal reaches to the primary winding . through the
secondary winding of the line driver transformer, line signal is given to the base of the
line output transistor. the collector terminal obtain positive supply through the coil (L
601)&EHT winding NO.2&4. This transistor amplifiers the line signal. The line signal
is taken out from the collector terminal & given to the EHT which helps the EHT to
function properly. This line signal is given to the horizontal yoke coil in the form of
sweep signal through a capacitor C610(8.2MFD/25V) and coil (L 602) this enables proper
adjustment of the picture in the horizontal direction
In this TV trainer, from pin No.7 of the EHT, boost supply is obtained simultaneously
,AFC fly back pulse & horizontal blinking pulse is obtained from pin No.2 of it .
Experiment-11
OBJETIVE - To study the fault simulation and step-by-step fault

Finding procedure of vertical oscillator & vertical output section.
Symptom: picture Bottom Fold sound OK.

Fault section: vertical output section.
 Check the +18Vdc (approx) on L-601.if it is OK.

 Check the same voltage on R-507. IF IT IS ok.
 Check the +18Vdc voltage on the collector terminal q-502. If proper voltage is not
obtained.
 Remove the short shunting between 2&3 and connect it between 1&2.
Symptom: Bottom Fold with proper sound.
Fault section: : vertical output section.
1.Adjust the present VR 501 to obtain proper picture . if no changes in picture is

obtained.
2.check the feed back signal on TP.22. if it is proper then.
3.Remove the shorting shunt between 1&2 and connect it between 2&3.

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Basic Electronics

 Study of binary adders.

 Two Bit Binary Parallel Adder.

 Study of 2 Bit Binary Subtractor (Half Subtractor).

 Study of Binary to Gray Code Conversion.

 Study of Gray to Binary Code Conversion.

 Study of Binary to Excess -3 Code Conversion.

 To study Operational amplifier as a Differential amplifier.

 To study Operational amplifier as Inverting amplifier.

 To study Operational amplifier as a Non-inverting amplifier.

Logic diagrams and IC Pin diagrams

Input 1 Input 2 Output Input1 Input2 Output

AND Gate NAND Gate

Input1 Input2 Output Input1 Input2 Output

OR Gate NOR Gate

EX-OR Gate NOT Gate

4. Switch on the instrument

5. Observe output of Gate on 8 bits LED display

6. Outputs can also be observed on oscilloscope

7. Repeat steps 2, 3, 4 for different input combination

8. Verify Truth Table

4. Switch on the instrument

5. Observe output of Gate on 8 bits LED display

6. Outputs can also be observed on oscilloscope

7. Repeat steps 2, 3, 4 for different input combination

8. Verify Truth Table

4. Repeat step 4, 5, 6 of NAND Gate.

4. Repeat step 4, 5, 6 of NAND Gate.

4. Repeat step 4, 5, 6 of NAND Gate.

Logic diagram : Truth Table

Input1 Input2 Carry Sum

2. IC 7432 2 input OR Gate 1

Input Input Input Output

Observation and Result

Two Bit Binary Parallel Adder

Input 1 Input 2 Borrow Difference

Binary Code Gray Code

Observation and Result

Gray Code Binary Code

Study of Binary to Excess -3 Code Conversion

 The Differential output of two AC signal can be observe

S. No. VIN1 VIN2 VOUT VOUT

4. To study the characteristics of photo voltaic cell

5. To study and observe the characteristic of PIN Photo diode

6. To study the characteristic of platinum RTD

7. To study the operation of analog to digital converter

L1 = inductor with unknown inductance

1. Connect external power supply

Measured value of R2 is .............ohm

Now measure the value of Lx by the formula

Measured value of resistance Rx by the multimeter between socket .........ohm

The value of Rx can be calculated by formula

RX=R2C1/C3 The value of Cx can be calculated by the formula

1. Connect external powerr supply

2. connect functioon generator probe in between vin termminals

3. Make connectioon as shown in figure

4. Set 5Vpp,1 Khz input sinusoidal signal of function generatorr

5. Rotate the potentiometer R2 to find null or minimum sound is generated

8. calculate the value of capacitance Cxi and Rxi by there formula

10. Repeat the above steps for different values of Cx and Rx