International Journal of Computer Theory and Engineering, Vol. 3, No.

2, April 2011
ISSN: 1793-8201

FPGA Implementation of FFT Algorithm for

IEEE 802.16e (Mobile WiMAX)
K.Harikrishna 1, T. Rama Rao 2, Vladimir A. Labay 3
(UWB) applications, etc. A hardware oriented radix-22
algorithm [3] is developed by integrating a twiddle factor
decomposition technique in divide and conquer approach to
form a spatially regular Signal Flow Graph (SFG). Mapping
the algorithm to the cascading delay feedback structure
leads to the proposed architecture [4].
The next section describes architecture & design
methodology, followed by its implementation in VERILOG
Hardware Description Language (VERILOG) code and
utilization, performance and implementation in OFDM
systems. Finally we conclude with a comparison of
hardware requirement of R22SDF and several other popular
pipeline architectures.

AbstractMobile WiMAX (Worldwide Interoperability for

Microwave Access) or 802.16e standard was ratified by the
IEEE in late 2005 as a potential to emerge as a real viable
competitor to existing 3G technologies. Mobile WiMAX uses
an OFDMA technology called 1K-FFT. Orthogonal
Frequency-Division Multiple Access (OFDMA) is a multi-user
version of the popular Orthogonal frequency-division
multiplexing (OFDM) digital modulation scheme. In the
widely used OFDM systems, the FFT and IFFT pairs are used
to modulate and demodulate the data constellation on the subcarriers. This paper presents a high level implementation of a
high performance FFT for OFDM Modulator and
Demodulator. The design has been coded in Verilog and
targeted into Xilinx Spartan3 FPGAs. Radix-22 Algorithm is
proposed and used for the OFDM communication system. This
algorithm has the same multiplicative complexity as the radix4 algorithm, but retains the butterfly structure of radix-2
algorithm.

II. ARCHITECTURE AND DESIGN METHODOLOGY

A. Radix-22 Decimation in Frequency FFT Algorithm

Index TermsRadix 22 algorithm, Fast Fourier Transform,

Orthogonal Frequency Division Multiplexing, Mobile WiMAX.

I. INTRODUCTION
The true Mobile WiMAX standard of 802.16e is
divergent from Fixed WiMAX. While clearly based on the
same OFDM base technology adopted in 802.16-2004, the
802.16e version is designed to deliver service across many
more sub-channels than the OFDM 256-FFT. It is
important to note that both standards support single carrier,
OFDM 256-FFT and at least OFDMA 1K-FFT.
OFDM technology is used for many communication
systems such as Asymmetric digital subscriber line (ADSL),
Wireless Local Area Network (WLAN) or Multimedia
Communication Services [1]. One of the key components in
OFDM system is the Fast Fourier Transform (FFT). There
are more and more communication systems require higher
points FFT and higher symbol rates. The requirement
establishes challenges for low power and high speed FFT
design with large points.
The FFT algorithm eliminates the redundant calculation
which is needed in computing Discrete Fourier Transform
(DFT) and is thus very suitable for efficient hardware
implementation [2]. In addition to computing efficient DFT,
the FFT also finds applications in linear filtering, digital
spectral analysis and correlation analysis, Ultra Wide Band
Manuscript received July 22, 2010
1
Dept. of electronics and communication engineering, r.s.r engineering
college, kadanuthala, nellore, ap, India(email: kamathamhk@yahoo.com)
2
Dept. of telecommunication engineering, srm university, kattankulattur,
chennai, tn, India.
3
Dept. of electrical and computer engineering, gonzaga university,
spokane, wa, usa.

197

A useful state-of-the-art review of hardware architectures

for FFTs was given by He et al. [5] and different
approaches were put into functional blocks with unified
terminology. From the definition of DFT of size N [6]:
N 1

X (k ) = x(n)WNnk ,0 k < N

(1)

n =0

where WN denotes the primitive Nth root of unity, with its

exponent evaluated modulo N, x(n) is the input sequence
and X(k) is the DFT. He [5] applied a 3-dimensional linear
index map,

n=

N
N
n1 + n2 + n3
2
4

k = k1 + 2k 2 + 4k 3

(2)

and Common factor algorithm (CFA) to derive a set of 4

DFTs of length N/4 as,

X ( k1 + 2 k 2 + 4 k 3 ) =
N
1
4

[ H (k , k

n3 = 0

, n 3 )W Nn3 ( k1 + 2 k 2 ) ]W Nn 3 k 3

(3)

where n1,n2,n3 are the index terms of the input sample n and
k1,k2,k3 are the index terms of the output sample k and
where H(k1,k2,k3) is expressed in eqn (4).

H (k1 , k 2 , n3 ) = x(n3 ) + (1) k1 x n3 + +

2

N
3 N

( j ) ( k1 + 2 k2 ) x n3 + + (1) k1 x n3 +
(4)
4
4

International Journal of Computer Theory and Engineering, Vol. 3, No. 2, April 2011
ISSN: 1793-8201

Eqn (4) represents the first two stages of butterflies with

only trivial multiplications in the SFG, as BFI and BFII.
Full multipliers are required after the two butterflies in
order to compute the product of the decomposed twiddle
factor

Z1(n) = x(n) + x n +
2

N
N
N

Z1 n + = x(n) x n + ,0 n <
2
2
2

WNn3 ( k1 + 2 k2 ) in eqn (3). Note the order of the twiddle

factors is different from that of radix-4 algorithm.

Applying this CFA procedure recursively to the
remaining DFTs of length N/4 in eqn (3), the complete
radix-22 Decimation-in-frequency (DIF FFT) algorithm is
obtained. The corresponding FFT flow graph for N=16 is
shown in Fig. 1 where small diamonds represent trivial
N /4

multiplication by WN

(5)

The butterfly outputs Z1(n) and Z1(n + N/2) are

computed according to the equations given in eqn (5). Z1(n)
is sent to apply the twiddle factors, and Z1(n + N/2) is
sent back to the shift registers to be multiplied in still next
N/2 cycles when the first half of the next frame of time
sequence is loaded in. The operation of the second butterfly
is similar to that of the first one, except the distance of
butterfly input sequence are just N/4 and the trivial twiddle
factor multiplication has been implemented by realimaginary swapping with a commutator and controlled
add/subtract operations, as in Fig 3(i) (ii), which requires
two bit control signal from the synchronizing counter. The
data then goes through a full complex multiplier, working at
75% utility, accomplishes the result of first level of radix-4
DFT word by word. Further processing repeats this pattern
with the distance of the input data decreases by half at each
consecutive butterfly stages. After N-1 clock cycles, the
result of the complete DFT transform streams out to the
right, in bit-reversed order. The next frame of transform can
be computed without pausing due to the pipelined
processing of each stage.

= j , which involves only real-

imaginary swapping and sign inversion [5].

Fig 1. Radix-22 DIF FFT flow graph for N=16

B. Radix-22 FFT Architecture

Mapping radix-22 DIF FFT algorithm derived to the
radix-2 SDF architecture, a new architecture of R22SDF
approach is obtained [3]. Fig 2 outlines an implementation
of the R22SDF architecture for N=1024, note the similarity
of the data-path to R2SDF and the reduced number of
multipliers. The implementation uses two types of
butterflies; one identical to that in R2SDF, the other
contains also the logic to implement the trivial twiddle
factor multiplication, as shown in Fig 3 (i), (ii) respectively
[3].
Due to the spatial regularity of Radix-22 algorithm, the
synchronization control of the processor is very simple. A
(log2N)-bit binary counter serves two purposes:
synchronization controller and address counter for twiddle
factor reading in each stage. With the help of the butterfly
structures shown in Fig 3, the scheduled operation of the
R22SDF processor in Fig 2 is as follows.
On first N/2 cycles, the 2-to-1 multiplexers in the first
butterfly module switch to position 0, and the butterfly is
idle. The input data from left is directed to the shift
registers until they are filled. On next N/2 cycles, the
multiplexers turn to position 1, the butterfly computes a
2-point DFT with incoming data and the data stored in the
shift registers.

(i) BF2I

(ii) BF2II
Fig 3. Butterfly structure for R22SDF FFT

198

International Journal of Computer Theory and Engineering, Vol. 3, No. 2, April 2011
ISSN: 1793-8201

Fig 2. R22SDF pipeline FFT architecture for N=1024

renaming your other efforts. All these features of

VERILOG will help better in simulation and synthesis of
our proposed architecture.

III. INTRODUCTION TO VERILOG

VERILOG Hardware Description Language (VERILOG)
was introduced by Gateway Design Automation in 1984 as
a proprietary hardware description and simulation language
[7]. The introduction of Verilog-based synthesis tools
in1988 by then-fledging Synopsys and the 1989 acquisition
of Gateway by Candence Design Systems were important
events that led to wide-spread use of the language [7].
VERILOG synthesis tools can create logic-circuit
structures directly from VERILOG behavioral descriptions,
and target them to a selected technology for realization.
Using VERILOG, you can design, simulate, and synthesize
anything form a simple combinational circuit to a complete
microprocessor system on a chip.
VERILOG started out with and still has the following
features [7]:
1) Designs may be decomposed hierarchically.
2) Each design element has both a well-defined interface
and a precise functional specification.
3) Functional specifications can use either a behavioral
algorithm or an actual hardware structure to define
initially by an algorithm, to allow design verification
of higher level elements that use it; later, the
algorithmic definition can be replaced by a preferred
hardware structure.
4) Concurrency, timing, and clocking can all be modeled.
VERILOG handles asynchronous as well as
synchronous sequential-circuit synthesis.
5) The logical operation and timing behavior of a design
can be simulated.
Thus, VERILOG started out as a documentation and
modeling language, allowing the behavior of digital-system
designs to be precisely specified and simulated. The
VERILOG language specification allows multiple modules
to be stored in a single text file. When one VERILOG
module instantiates another, the compiler finds the other by
searching the current workspace, as well as predefined
libraries, for a module with the instantiated name. Thus,
when using VERILOG-1995, there should be only one
definition of each module, usually in a file with the same
name as the module.
However, VERILOG-2001 actually allows you to define
multiple versions of each module, and it provides a separate
configuration management facility that allows you to
specify which one to use for each different instantiation
during a particular compilation or synthesis run. This lets
you try out different approaches without throwing away or

IV. IMPLEMENTATION IN VERILOG

The R22SDF presented above has been fully coded in
VERILOG Hardware Description Language (VERILOG).
Once the design is coded in VERILOG, the Modelsim
XEIII 6.2c compiler [8] and the Xilinx Foundation ISA
Environment 9.1i [9] generate a net-list for FPGA
configuration. The net-list can then be downloaded into the
FPGA using the same Xilinx tools and Texas Instruments
prototyping board.
From the architecture of R22SDF in Fig 2, the butterfly
blocks BF2I and BF2II are described as building blocks in
VERILOG code. Booth multiplication algorithm for signed
binary numbers is used for complex multipliers. Thus, the
overall latency of the real implementation varies as the
processing word length changes [3]. Look-up-table (LUT)
based Random Access Memories (RAMs) and Flip-Flops
are used to implement feedback memory of the very last
stages where are the RAM blocks in the FPGA are used for
the rest of the stages. Similarly, LUT-based Read Only
Memories (ROMs) are used to implement twiddle ROMs of
the very last stages whereas Block RAMs are used for the
rest of stages [5]. The FFT is heavily pipelined to achieve
as highest clock frequency as possible. Twiddle factors are
generated by an external program and embedded to the
VHDL code.
The implementation results after implementing in Xilinx
Spartan3 FPGA (fig 4) [10] are listed in Table 1(a), 1(b).
Table 1(a) shows the implementation results where as table
1(b) shows the timing summary.
The resulting figures show that our implementation
outperforms the other implementations of that kind. Its
speed nearly matches that of the Xilinx core but its
throughput is more than 3 times higher due to its pipeline
nature.
TABLE 1(a) IMPLEMENTATION RESULT

199

Logic Utilization

Used

Available

Utilization

No. of Slices

3155

3584

88%

No. of Slice Flip flops

1514

7168

21%

No. of 4 input LUTs

5916

7168

82%

No. of bonded IOBs

32

97

32%

International Journal of Computer Theory and Engineering, Vol. 3, No. 2, April 2011
ISSN: 1793-8201
No. of Mult18x18s

16

16

100%

No. of GCLKs

12%

carrier being independently modulated commonly using

some type of quadrature amplitude modulation (QAM) or
phase-shift keying (PSK) [15]. This composite baseband
signal is typically used to modulate a main RF carrier. s[n]
is a serial stream of binary digits. By inverse multiplexing,
these are first demultiplexed into N parallel streams, and
each one mapped to a (possibly complex) symbol stream
using some modulation constellation (QAM, PSK, etc.).
Note that the constellations may be different, so some
streams may carry a higher bit-rate than others.
The receiver picks up the signal r(t), which is then
quadrature-mixed down to baseband using cosine and sine
waves at the carrier frequency. This also creates signals
centered on 2fc, so low-pass filters are used to reject these.
The baseband signals are then sampled and digitized using
analogue-to-digital converters (ADCs), and a forward FFT
is used to convert back to the frequency domain [15].

TABLE 1(b) TIMING SUMMARY

10.827ns (Maximum Frequency:
Minimum period
92.366MHz)
Minimum input arrival time before
5.406ns
clock
Maximum output required time after
6.216ns
clock

Fig 5(a) OFDM Transmitter

Fig 4. Xilinx Spartan 3 FPGA Kit

V. APPLICATIONS OF PROPOSED FFT IN IEEE 802.16E

COMMUNICATION STANDARD
Worldwide Interoperability for Microwave Access
(WiMAX) [11, 12], is a telecommunications technology that
provides wireless transmission of data using a variety of
transmission modes, from point-to-multipoint links to
portable and fully mobile internet access. The technology
provides up to 10 Mbps broadband speed without the need
for cables. The technology is based on the IEEE 802.16
standard (also called Broadband Wireless Access). The
802.16e standard [12] uses OFDMA with 2K-FFT, 1K-FFT,
512-FFT, and 256-FFT capability.
The fundamental principle of the OFDM system is to
decompose the high rate data stream (bandwidth = W) into
N lower rate data streams and then to transmit them
simultaneously over a large number of subcarriers [13]. The
IFFT and the FFT are used for, respectively, modulating
and demodulating the data constellations on the orthogonal
subcarriers [14].
In an OFDM system, the transmitter and receiver blocks
contain the FFT modules as shown in Fig 5(a) & (b). The
FFT processor must finish the transform within 312.5ns to
serve the purpose in the OFDM system. Our FFT
architecture effectively fits into the system since it has a
minimum required time period of 10.827ns (table 1(b)).
An OFDM carrier signal is the sum of a number of
orthogonal sub-carriers, with baseband data on each sub200

Fig 5(b) OFDM Receiver

Orthogonal Frequency-Division Multiple Access

(OFDMA) is a multi-user version of the popular
Orthogonal frequency-division multiplexing (OFDM)
digital modulation scheme. Multiple access is achieved in
OFDMA by assigning subsets of subcarriers to individual
users as shown in fig 6. This allows simultaneous low data
rate transmission from several users [15].

Fig 6. ODMA Subcarriers Pattern

OFDMA can be seen as an alternative to combining

OFDM with time division multiple access (TDMA) or timedomain statistical multiplexing, i.e. packet mode
communication. Low-data-rate users can send continuously
with low transmission power instead of using a "pulsed"
high-power carrier. Constant delay, and shorter delay, can
be achieved. OFDMA can also be described as a

International Journal of Computer Theory and Engineering, Vol. 3, No. 2, April 2011
ISSN: 1793-8201

It shows that the proposed design has less memory access

than the radix-4 FFT by 20 ~ 40%. Therefore, the proposed
architecture consumes much lower power.

combination of frequency domain and time domain multiple

access, where the resources are partitioned in the timefrequency space, and slots are assigned along the OFDM
symbol index as well as OFDM sub-carrier index. OFDMA
is considered as highly suitable for broadband wireless
networks, due to advantages including scalability and
MIMO-friendliness, and ability to take advantage of
channel frequency selectivity [15]. The trans-receiver
structure of OFDMA is shown in fig 7.

Fig 7. OFDMA Trans-receiver

VII. PERFORMANCE AND IMPLEMENTATION

A. Hardware Requirement
The radix-4 butterfly needs 3 complex adders and 1
complex multiplier[16], while the proposed butterfly
structure needs only 4 complex adders and 1 complex
multiplier. This is because our design implements the
constant multiplier by 4 reused complex adders. Fig. 8
shows memory addressing of SRAM0 and SRAM1 for
N=64. All of the above-mentioned use separated single
SRAM into 2 smaller SRAMs. This design can double
SRAM throughput with inter-leaving access. In table 2, the
hardware requirement of the proposed design is compared
with various pipelined designs.
TABLE 2 HARDWARE REQUIREMENT COMPARISON
Multiplier #

Adder #

Memory size

R2MDC [17]

2(log4N-1)

4log4N

3N/2 -2

R2SDF [18]

2(log4N-1)

4log4N

N-1

R4SDF [19]

log4N-1

8log4N

N-1

R4MDC [17]

3(log4N-1)

8log4N

5N/2 -4

R4SDC [20]

log4N-1

3log4N

2N-2

Proposed

log4N-1

4log4N

N-1

B. Power Consumption
The power consumption is measured by the number of
times of data transition. The data transition times are
proportional to the SRAM access times. Here we assume
that the adders and multipliers are active at each clock cycle
because of the pipelining architecture. The more the SRAM
access times, the higher the power consumption Fig. 9
shows the SRAM access times versus N points FFT. The
SRAM access times is linear to the number of the recursive
iterations in FFT as described in Eq(6).The SRAM is
accessed twice each clock cycle, so Eq(6) is multiplied by 2.
201

Fig 8. Memory addressing of SRAM0 and SRAM1 for N=64

SRAM access times = N * (iteration times) *2

(6)

International Journal of Computer Theory and Engineering, Vol. 3, No. 2, April 2011
ISSN: 1793-8201

generation. Power-gating technology shuts down the power

supply in the unused blocks inside the device, so that the
entire mobile WiMAX module consumes only 0.5mA,
extending battery life. The chip supports multiple operating
frequency and channel bandwidth profiles, as well as
various subcarrier allocation schemes.
The module would be able to support multiple channel
bandwidths such as 3.5MHz, 5MHz, 7MHz, 10MHz and
20MHz; and all the popular frequency bands such as
2.3GHz, 2.5GHz and 3.5GHz. The Dual-core processor
architecture best supports application-rich Mobile WiMAX
operations.
Fig 9. SRAM Access Times Vs N points FFT

C. Speed
With fixed clock frequency, the processing OFDM
symbol rate decreases as the FFT point N increases. A
comparison with fixed clock frequency of 50 MHz is shown
in Fig. 10 based on Eq. (7). It shows that the proposed
architecture is better than radix-4 FFT by 25~ 66% .
symbol rates =

Fig 11. A simplified block diagram of the Fujitsu

Mobile WiMAX SoC

(clock frequency)* N
Total cycles of each N points

Fig. 11 shows a simplified block diagram of the Fujitsu

Mobile WiMAX SoC, MB86K22. It shows the dual
processors and main hardware blocks that implement a
complete PHY-to-MAC wireless MAN solution [21]. This
SoC uses OFDMA PHY with FFT sizes of 512/1024 points.
We have implemented the FFT, designed for efficient
mobile WiMAX, by 16 bits word length and synthesized in
Xilinx ISE 9.1 design compiler. Table 3 shows the
processing time of IFFT/FFT in orientation with OFDMA
and the projected values for various word lengths at 80MHz
clock frequency. The OFDMA symbol period for mobile
WiMAX 802.16e is 102.9sec (including a guard time of
11.4sec). The results clearly indicate that the processing
time of the proposed FFT is below the OFDM symbol
period of 102.9sec, which ensures an appropriate
operation for the communication standard 802.16e. The
table also presents the normalized area occupied for 0.6m
technology.

(7)
For fixed analog-to-digital converter sampling rate, the
OFDM symbol rate in receiver is fixed too. It then requires
higher chip clock frequency to process higher point FFT.
We make a comparison with clock frequency and N-points
FFT as shown in Eq. (8).
Minimum clock frequency =

(OFDM symbol rates)* N

Total cycles of each N points
(8)
The proposed architecture is better than radix-4 [20] FFT
by 20~40% .

TABLE 2 MOBILE WIMAX APPLICATIONS FOR THE FFT

Word Length
Processing Time
Normalized Area
(N)
(sec)
(mm2)
16

1.55

9.76

64

2.38

14.51

256

6.21

20.75

512

31.54

51.37

1024

65.89

124.23

Fig 10. OFDM Symbol Rates Vs N points FFT

VIII. CONCLUSIONS

D. Implementation

We have proposed a memory based recursive FFT

design which has much less gate counts, lower power
consumption and higher speed. The proposed architecture
has three main advantages (1) fewer butterfly iteration to
reduce power consumption, (2) pipeline of radix-22
butterfly to speed up clock frequency, (3) even distribution

The Fujitsu Mobile WiMAX SoC, MB86K22, fully

complies with the IEEE 802.16e standard using an OFDMA
PHY [21]. This fully integrated baseband IC was built
using the Fujitsu 65nm advanced CMOS low-leakage
process technology. The operating power of the MB86K22
has been reduced by 36 percent from the previous
202

International Journal of Computer Theory and Engineering, Vol. 3, No. 2, April 2011
ISSN: 1793-8201

of memory access to make utilization efficiency in SRAM

ports.
In summary, the speed performance of our design easily
satisfies most application requirements of mobile WiMAX
802.16e, which uses OFDMA modulated wireless
communication system. Our design also occupies lesser
area, hence lower cost and power consumption.

K. Harikrishna was born on 15th May 1980 in

Andhra Pradesh, India. He is currently working as
Associate Professor & Head of the Department of
Electronics and Communication Engineering, R.S.R
Engineering College, Nellore, AP, India. He has
received his B.Tech from Jawaharlal Nehru
Technological University, Hyderabad, India in the
year 2001, and later did Master of Science in
Electrical and Computer Engineering from Southern
Illinois University, Carbondale, IL, USA in the year 2004. He is a Member
of International Association of Computer Science and Information
Technology MIACSIT. He has actively attended and published various
research papers in national and international conferences. He is currently
pursuing Ph.D. degree with SRM University, Chennai, India.

ACKNOWLEDGEMENT
The authors express their sincere thanks for the support
of the SRM University, Chennai, TN, to carry out this
research work.
REFERENCES
[1]

[2]

[3]

[4]

[5]
[6]
[7]
[8]
[9]
[10]
[11]
[12]
[13]
[14]
[15]
[16]
[17]
[18]
[19]
[20]
[21]

Lenart and Viktor wall. Architectures for dynamic data scaling in

2/4/8k pipeline FFT cores. IEEE transactions on Very Large Scale
Integration (VLSI) systems, vol. 14, no. 11, Pages: 1286-1290,
November 2006.
Mian Sijjad Minallah, Gulistan Raja. Real Time FFT Processor
Implementation. IEEEICET 2006 2nd International Conference on
Emerging Technologies. Peshawar, Pakistan 13-14, Pages: 192-195,
November 2006.
S Sukhsawas, K Benkrid. A High-level Implementation of a High
Performance Pipeline FFT on Virtex-E FPGAs. Proceedings of the
IEEE Comp. Society Annual Symp. on VLSI Emerging Trends in
Systems Design (ISVLSI04). 0-7695-2097-9/2004.
K. Harikrishna, T. Rama Rao and Vladimir A. Labay, A RADIX-22
Pipeline FFT for Ultra Wide Band Technology, International
Conference on Computer & Network Technology (ICCNT),
conference proceedings published by World Scientific Press,
Singapore. Chennai, India, Jul 24-28, 2009.
S. He and M. Torkelson. A new approach to pipeline FFT processor,
10th Int. Parallel Processing Symp. (IPPS96), p. 766770, 1996.
Digital Signal Processing: Principles, Algorithms and Applications
(3rd Edition) by John G. Proakis and Dimitris K Manolakis Prentice-Hall, Inc., - Oct 5, 1995.
Digital Design Principles and Practices, Fourth Edition, John F.
Wakerly, Pearson Education, Inc. 2006.
Modelsim
manual.
Mentor
Graphics
Corporation.
http://support.xilinx.com.
Xilinx, Inc. http://www.xilinx.com/.
Xilinx, Inc. High-Performance 1024-Point Complex FFT/IFFT V2.0.
http://www.xilinx.com/ipcenter/.
http://www.wimaxforum.org/.
http://www.ieee802.org/16/tgd/.
OFDM Towards Fixed and Mobile Broadband Wireless Access,
Uma Shanker Jha, and Ramjee Prasad, Artech House Inc., London,
2007.
OFDM For Wireless Communications Systems, Ramjee Prasad,
Artech House Inc., London, 2004.
http://www.wikipedia.org/.
Chi-Hong Su and Jen-Ming Wu, Member, IEEE, Reconfigurable FFT
Design for Low Power OFDM Communication Systems, 2006, IEEE.
L.R. Rabiner and B. Gold. Theory and Application of Digital Signal
Processing. Prentice-Hall, Inc., 1975.
E.H. Wold and A.M. Despain. Pipeline and parallel-pipeline FFT
processors for VLSI implementation. IEEE Trans. Comput., C33(5):414426, May 1984.
A.M. Despain. Fourier transform computer using CORDIC iterations.
IEEE Trans. Comput., C-23(10):9931001, Oct.1974.
G. Bi and E. V. Jones. A pipelined FFT processor for word sequential
data. IEEE Trans. Acoust., Speech, Signal Processing, 37(12):1982
1985, Dec. 1989.
http://www.fujitsu.com/

T. R. Rao was born on 10th June 1972 in Andhra

Pradesh, India. Currently, he is working as Professor
& Head of the Telecommunications Engineering
Department, Faculty of Engineering & Technology,
SRM University, India. He received his Ph.D. degree
in radio wave propagation studies for fixed and
mobile communications over Southern India from Sri
Venkateswara University, Tirupati, India in 2000. He
is a Member of the IEEE - Institute of Electrical and
Electronics Engineers; Senior member of the Association of Computer,
Electronics and Electrical Engineers - ACEEE and a Member of IACSIT International Association of Computer Science and Information
Technology. He was the recipient of Young Scientist award for the
XXVIth URSI (International Union of Radio Science) General Assembly,
University of Toronto, Canada, held during August 1999. And, he has been
selected as a participant to attend the School on Data and Multimedia
Communications using Terrestrial and Satellite Radio links organized by
the ICTP (International Centre for Theoretical Physics), Trieste, Italy, 7-25
Feb. 2000. He worked with Aalborg University, Denmark as assistant
research professor with Universidad Carlos III de Madrid, Spain and at the
University of Sydney, Australia as visiting professor. Also, he worked as
post-doctor research fellow at National Chio Tung Univeristy, Hsinchu,
Taiwan. He has a long-standing research history on radiowave propagation
studies for wireless communications. His research interests include radio
channel measurements & modeling, broadband wireless communications
and networks and wireless mesh networks. He authored papers in reputed
journals and transactions and international andnational conferences.

V. A. Labay was born in Winnipeg, Manitoba, Canada

in 1965. He is a professor and Chair of the Department
of Electrical and Computer Engineering at Gonzaga
University in Spokane, Washington, USA. He earned
B.Sc. and M.Sc. degrees from the University of
Manitoba in 1987 and 1990, respectively. After
graduating with a Ph.D. degree from the University of
Victoria in 1995, he remained in Victoria, British
Columbia, Canada as a lecturer and research engineer until he accepted an
assistant professor position in 1999 at Eastern Washington University
located in Cheney, Washington, USA. In 2007, he was a visiting professor
at SRM University in Chennai, India and has previously held adjunct
professorship positions at the University of Idaho, Moscow, Idaho, USA
and at Washington State University, Pullman, Washington, USA. His
research interests include modeling of and the development of
microwave/millimeter-wave integrated circuit devices used in wireless and
satellite communications.

203