Nexys4 PDM RefProj2 V2

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Pullman, WA 99163
509.334.6306
www.digilentinc.com
Nexys4 PDM Filter Project

Revised February 3, 2014
This manual applies to the Nexys4 rev. B
Introduction
This document aims to briefly explain the pulse-density modulation (PDM) [Ref. 2] interfacing design used to
acquire data from the Nexys4s on-board ADMP421 MEMS microphone [Ref. 1]. This design is a hardware Xilinx
Artix-7 FPGA implementation of the cascaded integrator-comb (CIC) decimation filter [Ref. 9] and finite impulse
response (FIR) filter [Ref. 20], outputting the 16-bit filtered data at a 96 kHz rate.
This project was compiled with Xilinx ISE 14.6 and written in VHDL.
Functional Description and Implementation Details
In order to complete the sigma-delta conversion [Ref. 3] [Ref. 4], the filtering stage has been implemented using a
multi-stage decimation strategy with one cascaded integrator-comb decimating filter, one half-band FIR filter, one
low-pass FIR filter, and a first-order high-pass filter, as shown in Figure 1.
ARTIX-7 FPGA
EXTERNAL
IBUFG
CLK
BUFR
MMCM
100 MHz
MEMS
Mic.
6.144
MHz
fs =
3.072 MHz
fs =
192 kHz
CIC
16
HB
2
BUFG
2
3.072
MHz
fs =
96 kHz
fs =
96 kHz
CLK
DATA
22
22
LP
16
HP
16
L/R
Figure 1. PDM filter block diagram.

Figure 1. PDM filter block diagram
The clock source to drive the PDM is generated by a mixed-mode clock manager proceeded by a regional primitive
buffer that further divides the 6.144 MHz clock, making it a 3.072 MHz clock. The L/R select input of the
microphone is tied to the ground, choosing the data to be sampled at the rising edge of Clk.
DOC#: 560-010
Copyright Digilent, Inc. All rights reserved.

Other product and company names mentioned may be trademarks of their
respective owners.
Page 1 of 12
1.1
The CIC Stage
This is the first filtering stage of the PDM filter. It is implemented using Xilinx LogiCORE CIC Compiler [Ref. 11] [Ref.
12] [Ref. 13]. Table 1 shows the parameters used in the current filter configuration:
Parameter Name
Value
Observations
Filter Type
Decimation
Calculated with equation 3.5 of Design and VLSI
Implementation of a Decimation filter for Hearing Aid
Applications [Ref. 10], and knowing that the microphone
[Ref. 1] has a fourth-order built-in sigma-delta modulator.
Number of unit delays employed in each comb filter [Ref.
13].
Number of Stages
Differential Delay
Number of Channels
Sample Rate Change
16
The actual decimation rate.
Hardware Oversampling Format
Frequency
Specification
The input sampling frequency is used for specifying the

hardware oversampling rate.
Input Sampling Frequency
3.072 MHz
The rate of the microphone output PDM data.
Clock Frequency
3.072 MHz
Input Data Width
Quantization
Full
Precision
The minimum value that is achieved by converting the

unipolar PDM data to bipolar (the LSB is always 1 and bit
1 is the PDM data).
Outputs the full 22-bit data without any truncation or
rounding.
Use XtremeDSP Slice
Yes
Use dedicated hardware DSP primitive.
Table 1. CIC compiler settings.

The CIC stage samples the input data at 3.072 MHz, with a resulting decimation rate of 16. The output sampling
rate is 192 kHz.
1.2
The Half-Band Filter

Parameter
FIR Order
Fs (Sampling frequency)
Fpass (Cut-off frequency)
Astop (Stop-band attenuation)
1
Coefficient width
Value
14
192 kHz
21.8 kHz
80 dB
15
Table 2. Half-band filter settings.

The second filtering stage is the half-band decimation filter [Ref. 16] [Ref. 17] that was implemented with the Xilinx
LogiCORE FIR Compiler [Ref. 21] [Ref. 22]. The filter coefficients were calculated using MATLAB, but they can also
be calculated with any other software (e.g. Scilab, Octave, etc.) and stored in a .coe file according to the
15-bit wide coefficients were chosen to spread across the full 80 dBs of magnitude band.

Other product and company names mentioned may be trademarks of their respective owners.
Page 2 of 12
specifications in Xilinxs LogiCORE IP FIR Compiler v6.3 [Ref. 21]. The filter settings for MATLAB are displayed in
Table 2, along with a visual representation of the filters magnitude response (Figure 2):
Magnitude Response (dB)

0
Magnitude (dB)
-20
Fpass =
21.8 kHz
Astop =
80 dB
-40
-60
-80
10
20
30
40
50
Frequency (kHz)
60
70
80
90
Figure 2. Half-band filter settings.

Having the coefficients calculated, the following settings were put in place for the FIR Compiler (Table 3):
Parameter Name
Value
Observations
Filter Type
Decimation
Decimation was selected at the Filter Type option.
Rate Change Type
Integer
Decimation rate value type
Decimation Rate Value
Hardware Oversampling Format
Frequency
Specification
0.192 MHz
A decimation of 2 was used to achieve the final sampling

rate of 96 kHz.
The input sampling frequency is used for specifying the
hardware oversampling rate.
The output data rate of the previous filtering stage (192
kHz).
Clock Frequency
3.072 MHz
Quantization
Integer
Coefficients
Coefficient Width
15
Coefficient Structure
Half-band
The type of filter according to the coefficient structure

[Ref. 22].
Input Data Type
Signed
The output data of the CIC stage is signed.
Input Data Width
22
Output Rounding Mode
Truncated
LSBs
Using Equations 3-4 from Digitally Removing a DC Offset:

DSP Without Mathematics [Ref. 22] would give an output
data width too large for this filters purpose; hence, a
truncation scheme for the output data has been used.
Output Width
22
Output signed data width truncated to fit a 22-bit bus.
The integer coefficients quantization option is used to let

the FIR Compiler analyze the coefficients and determine
the minimum number of bits required for representation.
Table 3. FIR compiler settings for half-band filter.

Page 3 of 12
1.3
The Low-Pass Filter
This filtering stage was implemented using the Xilinx LogiCORE FIR Compiler [Ref. 21][Ref. 22] by having the
coefficients calculated using the values in Table 4 (and Figure 3):
Parameter
FIR Order
Fs (Sampling frequency)
Fpass (end of pass-band)
Fstop (beginning of stop-band)
Wpass (weight in pass-band)
Wstop (weight in stop-band)
2
Coefficient width
Value
161
96 kHz
13 kHz
15 kHz
1 dB
100 dB
20
Table 4. Low-pass filter settings.

Magnitude Response (dB)
0
-10
Wpass =
1 dB
-20
Fstop =
15 kHz
Magnitude (dB)
-30
-40
Wstop =
100 dB
Fpass =
13 kHz
-50
-60
-70
-80
-90
-100
0
10
15
20
25
Frequency (kHz)
30
35
40
45
Figure 3. Low-pass FIR filter settings.

In order to properly configure the FIR Compiler, a description of its settings are shown in Table 5:
20-bit wide coefficients were chosen to spread across the full 100 dBs of magnitude band.

Page 4 of 12
Parameter Name
Value
Filter Type
Single rate
Hardware Oversampling
Format
Clock Frequency
Coefficient Type
Coefficient Width
Coefficient Structure
Input Data Type
Input Data Width
Frequency
Specification
0.096 MHz
3.072 MHz
Signed
20
Symmetric
Signed
22
Output Rounding Mode

Output Width
1.3
Observation
Since the decimation ratio is 1, single rate filter type was
selected.
The input sampling frequency is used to specify the hardware
oversampling rate.
The output data rate of the previous filtering stage (96 kHz).
Signed coefficients with twos complement representation.
See Chapter 3 of LogiCORE IP FIR Compiler v7.0 [Ref. 22].
The output data of the CIC stage is signed.
Using Equations 3-4 from LogiCORE IP FIR Compiler v7.0

[Ref. 22] would give an output data width too large for this
Truncate LSBs
filters purpose; thus, a truncation scheme for the output data
has been used.
22
Output signed data width truncated to fit a 22-bit bus.
Table 5. FIR Compiler settings for low-pass filter.
The High-Pass Filter
This represents the final filtering stage, used for removing any DC component induced by the sigma-delta
modulator or the microphone itself (offset error). It is an implementation of digitally removing an offset [Ref. 24],
but other methods can also be implemented, as described in DC Blocker Algorithms [Ref. 23] and in DSP Tricks:
DC Removal [Ref. 25].
After sign extending the input data (16-bit to 17-bit), it is subtracted from the most significant result (17-bit) of the
-12
1-tap integrator (the integral part of the integration [Ref. 24]). Using a multiplier value of 2 and one delay cell (z
1
) results in a cut-off frequency of 18.6 Hz with a 10 dB/decade slope.
Figure 4 shows the filter diagram.
[28:12]
29
17
x[n]
16
17
17
+
sign
extend
29
z-1
+
2-12
16
y[n]
Figure 4. High-pass filter schematic.

Page 5 of 12
Area and Performance
The actual, measured magnitude and phase responses of the resulting PDM filter are shown in Figure 5. Figure 6
3
shows the approximated impulse response.
Magnitude [dB]
50
0
-50
-100
-150
1
10
10
10
Frequency [Hz]
10
10
Angle [deg]
2000
0
-2000
-4000
-6000
1
10
10
10
Frequency [Hz]
10
10
Figure 5. Magnitude and phase response of the PDM filter.
2
1.5
Amplitude
1
0.5
0
-0.5
-1
-1.5
-2
100
200
300
Samples
400
500
Figure 6. Impulse response of the PDM filter.
In order to convert the acquired frequency response data to discrete-time filter numerator and denominator z
polynomials (its transfer function), a Gauss-Newton iterative search of linear equations was used (function invfreqz in
MATLAB) with an approximation error on the result as follows: magnitude response 1%, phase response 1.7%.

Page 6 of 12
Design Usage Example: Schroeder Reverberator
The Schroeder reverberator [Ref. 28] was used as a demo to prove the PDM filters utility. The following figure
illustrates the block diagram of the reverberator and its components:
Figure 7. (a) The block diagram of the

Schroeder reverberator, (b) the structure
of the comb filter, (c) and the structure of
the all-pass filter.
The output of the PDM filter is fed into four parallel comb filters, each with a different loop time to enhance the
acoustic resonance. After this, the samples are fed into two consecutive all-pass filters to further enlarge the
spectrum.
In all structures (comb and all-pass), the g multiplier constant and N number of delay stages are computed
automatically in the VHDL module by using the following equations [Ref. 27]:
= 10
=

= loop time
T60 = reverb time
fs = sampling frequency
Page 7 of 12
References
[1]
Analog Devices: Omnidirectional Microphone with Bottom Port and Digital Output, ADMP421 Data Sheet,
rev. D.
[2]
Wikipedia: Pulse-density modulation, http://en.wikipedia.org/wiki/Pulse-density_modulation, March 2013.
[3]
U. Beis: An Introduction to Delta Sigma Converters,

http://www.beis.de/Elektronik/DeltaSigma/DeltaSigma.html, 2008.
[4]
J. D. Reiss: Understanding Sigma-Delta Modulation: The Solved and Unsolved Issues, J. Audio Eng. Soc., Vol.
56, No. 1/2, January/February 2008.
[5]
Z. Milivojevi: Digital Filter Design, http://www.mikroe.com/products/view/268/digital-filter-design/.
[6]
N. Hegde: Seamlessly Interfacing MEMS Microphones with Blackfin Processors, EE-350 Engineer-toEngineer Note, rev. 1, August 2010.
[7]
Altera, Inc.: Understanding CIC Compensation Filters, Application Note 455, ver. 1.0, April 2007.
[8]
R. G. Lyons: Understanding cascaded integrator-comb filters,

http://www.embedded.com/design/configurable-systems/4006446/Understanding-cascadedintegrator-comb-filters, March 2005.
[9]
M. P. Donadio: CIC Filter Introduction, Free Publication by Iowegian, July 2000.
[10] S. Pandu: Design and VLSI Implementation of a Decimation filter for Hearing Aid Applications, Master of
Technology thesis, 2007.
[11] Xilinx, Inc.: LogiCORE CIC Compiler v3.0, DS845 Product Specification, ver. 1.0, June 2011.
[12] Xilinx, Inc.: Cascaded Integrator-Comb (CIC) Filter v3.0, Product Specification, March 2002.
[13] Xilinx, Inc.: LogiCORE CIC Compiler v4.0, PG140 Product Guide for Vivado Design Suite, ver. 1.0, March
2013.
[14] G. J. Dolecek, J. D. Carmona: On Design of CIC Decimators, Applications of MATLAB in Science and
Engineering, ISBN: 978-953-307-708-6, pp. 225-246, 2011.
[15] A. C. Cherik, E. Farshidi: A new Configurable Decimation Filter using Pascals Triangle Theorem, World
Academy of Science, Engineering and Technology 54, pp. 75-78, 2011.
[16] H. G. Gckler: Most Efficient Digital Filter Structures: The Potential of Halfband Filters in Digital Signal
Processing, Applications of Digital Signal Processing, ISBN: 978-953-307-406-1, pp. 237-278, 2011.
[17] T. Saramaki, T. Karema, T. Ritoniemi, H. Tenhunen: Multiplier-free Decimator Algorithms for Superresolution
Oversampled Converters, in Proc. 1990 IEEE International Symposium on Circuits and Systems (New
Orleans, Louisiana), pp. 3275-3278, May 1990.
[18] P. Zahradnik, B. Simak, M. Kopp, M. Vlcek: Design of Half-Band FIR Filters for Signal Compression,
International Journal on Advances in Telecommunications, vol. 4, no. 3 & 4, 2011.
Page 8 of 12
[19] P. P. Vaidyanathan, T. Q. Nguyen: A TRICK for the Design of FIR Half-Band Filters, IEEE Transactions on
Circuits and Systems, vol. CAS-32, no. 3, March 1987.
[20] R. Thakur, K. Khare: High Speed FPGA Implementation of FIR Filter for DSP Applications, International
Journal of Modeling and Optimization, Vol. 3, No. 1, February 2013.
[21] Xilinx, Inc.: LogiCORE IP FIR Compiler v6.3, DS795 Product Specification, ver. 1.3, October 2011.
[22] Xilinx, Inc.: LogiCORE IP FIR Compiler v7.0, PG149 Product Guide for Vivado Design Suite, ver. 1.0, March
2013.
[23] R. Yates, R. Lyons: DC Blocker Algorithms, IEEE Signal Processing Magazine, pp. 132-134, March 2008.
[24] K. Chapman: Digitally Removing a DC Offset: DSP Without Mathematics, WP279 Xilinx White Paper, ver.
1.0, July 2008.
[25] R. G. Lyons: DSP Tricks: DC Removal, http://www.embedded.com/design/configurablesystems/4007653/DSP-Tricks-DC-Removal, August 2008.
[26] E. Doering: Reverberation, http://cnx.org/content/m15471/latest/, March 2008.
[27] E. Doering: Schroeder Reverberator, http://cnx.org/content/m15491/1.2/, March 2008.
[28] J. Sun: Schroeders Reverberator: The Earliest Digital Solution of Sound Reverberation, EECS 195 Final
Project, March 2005.

Page 9 of 12
Appendix A: Half-Band Filter Coefficients

The following coefficients are used in the Xilinx FIR Compiler to implement the half-band filer:
radix = 10;
coefdata = -100, 0, 614, 0, -2295, 0, 9971, 16383, 9971, 0, -2295, 0, 614,
0,-100;
Appendix B: Low-Pass Filter Coefficients

The following coefficients are used in the Xilinx FIR Compiler to implement the low-pass filter:
radix = 16;
coefficient_width = 20;
coefdata = 00041,
ff81b,
ff54a,
ffaeb,
00ef5,
002f3,
fd7b5,
00902,
08fee,
46294,
06e10,
fd42d,
fe801,
0140d,
005c2,
ff49a,
ff9ae,
fffc5,
00111,
ff282,
ff600,
00457,
00ce1,
fed69,
fe4d3,
03e33,
0416c,
34c97,
00958,
fc42b,
0074f,
01520,
ff8b1,
ff567,
fffdd,
0067c,
002c8,
ff179,
ffbb8,
00a1b,
00003,
fe3ad,
00880,
049ba,
fa175,
19cd6,
fb0cb,
fdfa3,
01e2d,
006e7,
ff12c,
ffc13,
00380,
00a33,
0056d,
ff573,
002c4,
0078f,
ff133,
fee8d,
02984,
01bf8,
f18e6,
00982,
f9d13,
00e6b,
01d64,
ff4be,
ff3dd,
0036e,
0020f,
00a86,
0086d,
ffc43,
0063b,
ffde6,
febb2,
007ce,
02dc2,
fcff2,
f24d3,
f24d3,
fcff2,
02dc2,
007ce,
febb2,
ffde6,
0063b,
ffc43,
0086d,

00a86,
0020f,
0036e,
ff3dd,
ff4be,
01d64,
00e6b,
f9d13,
00982,
f18e6,
01bf8,
02984,
fee8d,
ff133,
0078f,
002c4,
ff573,
0056d,
00a33,
00380,
ffc13,
ff12c,
006e7,
01e2d,
fdfa3,
fb0cb,
19cd6,
fa175,
049ba,
00880,
fe3ad,
00003,
00a1b,
ffbb8,
ff179,
002c8,
0067c,
fffdd,
ff567,
ff8b1,
01520,
0074f,
fc42b,
00958,
34c97,
0416c,
03e33,
fe4d3,
fed69,
00ce1,
00457,
ff600,
ff282,
00111,
fffc5,
ff9ae,
ff49a,
005c2,
0140d,
fe801,
fd42d,
06e10,
46294,
08fee,
00902,
fd7b5,
002f3,
00ef5,
ffaeb,
ff54a,
ff81b,
00041;
Page 10 of 12
Appendix C: Overall FPGA Usage

Slice Logic Utilization
Number of Slice Registers
- Number used as Flip Flops
- Number used as Latches
- Number used as Latch-thrus
- Number used as AND/OR logics
Number of Slice LUTs
- Number used as logic
- Number using O6 output only
- Number using O5 and O6
- Number used as ROM
- Number used as Memory
- Number used as Dual Port RAM
- Number used as Single Port RAM
- Number used as Shift Register
- Number used exclusively as route-thrus
- Number with same-slice register load
- Number with same-slice carry load
- Number with other load
Number of occupied Slices
Number of LUT Flip Flop pairs used
- Number with an unused Flip Flop
- Number with an unused LUT
- Number of fully used LUT-FF pairs
- Number of slice register sites lost to control set restrictions
Usage
951
951
0
0
0
693
325
235
0
90
0
336
48
8
0
40
0
288
247
0
41
32
32
0
0
311
895
106
202
587
0
Total
126,800
Percentage
1
63,400
63,400
1
1
19,000
15,850
895
895
895
126,800
11
22
65
0
I/O Utilization
Number of bonded IOBs
- Number of LOCed IOBs
- IOB Flip Flops
Usage
14
14
0
Total
210
14
Percentage
6
100
Specific Feature Utilization

Number of RAMB36E1/FIFO36E1s
- Number using RAMB36E1 only
- Number using FIFO36E1 only
Number of RAMB18E1/FIFO18E1s
Number of BUFG/BUFGCTRLs
Usage
0
0
0
0
4
Total
135
Percentage
0
270
32
0
12

Page 11 of 12
- Number used as BUFGs

- Number used as BUFGCTRLs
Number of IDELAYE2/IDELAYE2_FINEDELAYs
Number of ILOGICE2/ILOGICE3/ISERDESE2s
- Number used as ILOGICE2s
Number used as ILOGICE3s
- Number used as ISERDESE2s
Number of ODELAYE2/ODELAYE2_FINEDELAYs
Number of OLOGICE2/OLOGICE3/OSERDESE2s
- Number used as OLOGICE2s
- Number used as OLOGICE3s
- Number used as OSERDESE2s
Number of PHASER_IN/PHASER_IN_PHYs
Number of PHASER_OUT/PHASER_OUT_PHYs
Number of BSCANs
Number of BUFHCEs
Number of BUFRs
Number of CAPTUREs
Number of DNA_PORTs
Number of DSP48E1s
Number of EFUSE_USRs
Number of FRAME_ECCs
Number of IBUFDS_GTE2s
Number of ICAPs
Number of IDELAYCTRLs
Number of IN_FIFOs
Number of MMCME2_ADVs
Number of OUT_FIFOs
Number of PCIE_2_1s
Number of PHASER_REFs
Number of PHY_CONTROLs
Number of PLLE2_ADVs
Number of STARTUPs
Number of XADCs

4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
16
0
0
0
0
0
0
1
0
0
0
0
0
0
0
300
300
0
0
300
24
24
4
96
24
1
1
240
1
1
4
2
6
24
6
24
1
6
6
6
1
1
0
0
0
0
4
0
0
6
0
0
0
0
0
0
16
0
0
0
0
0
0
0
Page 12 of 12

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Nexys4 PDM Filter Project

Functional Description and Implementation Details

Figure 1. PDM filter block diagram.

Copyright Digilent, Inc. All rights reserved.

Nexys4 PDM Filter Project

The CIC Stage

Sample Rate Change

The actual decimation rate.

Hardware Oversampling Format

The input sampling frequency is used for specifying the

Input Sampling Frequency

The rate of the microphone output PDM data.

Input Data Width

The minimum value that is achieved by converting the

Use XtremeDSP Slice

Use dedicated hardware DSP primitive.

Table 1. CIC compiler settings.

The Half-Band Filter

Table 2. Half-band filter settings.

Copyright Digilent, Inc. All rights reserved.

Nexys4 PDM Filter Project

Magnitude Response (dB)

Figure 2. Half-band filter settings.

Decimation was selected at the Filter Type option.

Rate Change Type

Decimation rate value type

Decimation Rate Value

Hardware Oversampling Format

Input Sampling Frequency

A decimation of 2 was used to achieve the final sampling

The type of filter according to the coefficient structure

Input Data Type

The output data of the CIC stage is signed.

Input Data Width

Output Rounding Mode

Using Equations 3-4 from Digitally Removing a DC Offset:

Output signed data width truncated to fit a 22-bit bus.

The integer coefficients quantization option is used to let

Table 3. FIR compiler settings for half-band filter.

Copyright Digilent, Inc. All rights reserved.

Nexys4 PDM Filter Project

The Low-Pass Filter

Table 4. Low-pass filter settings.

Figure 3. Low-pass FIR filter settings.

Copyright Digilent, Inc. All rights reserved.

Nexys4 PDM Filter Project

Output Rounding Mode

Using Equations 3-4 from LogiCORE IP FIR Compiler v7.0

The High-Pass Filter

Figure 4. High-pass filter schematic.

Copyright Digilent, Inc. All rights reserved.

Nexys4 PDM Filter Project

Area and Performance

Figure 5. Magnitude and phase response of the PDM filter.

Figure 6. Impulse response of the PDM filter.

Copyright Digilent, Inc. All rights reserved.

Nexys4 PDM Filter Project

Design Usage Example: Schroeder Reverberator

Figure 7. (a) The block diagram of the