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    Hands-on-Experience in Digital VLSI Design Using Cadence/Tanner

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    Kiran Pattnaik
    The 5-day workshop from May 5-15, 2014 aimed to provide hands-on training in digital VLSI design using CADENCE/TANNER tools. Organized by the Departments of Electronics & Communication Engineering and Applied Electronics & Instrumentation at Silicon Institute of Technology, the objective was to equip participants with the ability to design digital circuits for technologies like cell phones, laptops, and automobiles. The course covered MOSFET characteristics, logic gates, SPICE simulation, floorplanning, layout design, DRC, LVS, and the complete digital design flow. Registration was mandatory for students, faculty, and industry professionals at respective fees of Rs. 3,600, Rs. 5,000, and Rs

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    Hands-on-Experience in Digital VLSI Design Using Cadence/Tanner

    Uploaded by

    Kiran Pattnaik
    55 views2 pages
    The 5-day workshop from May 5-15, 2014 aimed to provide hands-on training in digital VLSI design using CADENCE/TANNER tools. Organized by the Departments of Electronics & Communication Engineering and Applied Electronics & Instrumentation at Silicon Institute of Technology, the objective was to equip participants with the ability to design digital circuits for technologies like cell phones, laptops, and automobiles. The course covered MOSFET characteristics, logic gates, SPICE simulation, floorplanning, layout design, DRC, LVS, and the complete digital design flow. Registration was mandatory for students, faculty, and industry professionals at respective fees of Rs. 3,600, Rs. 5,000, and Rs

    Original Description:

    DIGI

    Original Title

    Digital VLSI

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    The 5-day workshop from May 5-15, 2014 aimed to provide hands-on training in digital VLSI design using CADENCE/TANNER tools. Organized by the Departments of Electronics & Communication Engineering and Applied Electronics & Instrumentation at Silicon Institute of Technology, the objective was to equip participants with the ability to design digital circuits for technologies like cell phones, laptops, and automobiles. The course covered MOSFET characteristics, logic gates, SPICE simulation, floorplanning, layout design, DRC, LVS, and the complete digital design flow. Registration was mandatory for students, faculty, and industry professionals at respective fees of Rs. 3,600, Rs. 5,000, and Rs

    Copyright:

    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd
    Download as docx, pdf, or txt
    55 views2 pages

    Hands-on-Experience in Digital VLSI Design Using Cadence/Tanner

    Uploaded by

    Kiran Pattnaik
    The 5-day workshop from May 5-15, 2014 aimed to provide hands-on training in digital VLSI design using CADENCE/TANNER tools. Organized by the Departments of Electronics & Communication Engineering and Applied Electronics & Instrumentation at Silicon Institute of Technology, the objective was to equip participants with the ability to design digital circuits for technologies like cell phones, laptops, and automobiles. The course covered MOSFET characteristics, logic gates, SPICE simulation, floorplanning, layout design, DRC, LVS, and the complete digital design flow. Registration was mandatory for students, faculty, and industry professionals at respective fees of Rs. 3,600, Rs. 5,000, and Rs

    Copyright:

    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd
    Download as docx, pdf, or txt
    of 2

    Hands-on-Experience in Digital VLSI Design using

    CADENCE/TANNER
    5th - 15th May 2014
    ORGANIZED BY Department of Electronics & Communication Engineering & Department of Applied
    Electronics & Instrumentation

    OBJECTIVE
    Integrated Circuits are virtually part of every electronic component in the world today, such as cell phones,
    personal digital assistants, pagers, PC/Laptops, printers, set-top boxes, automobiles and so on. Most of these IC
    chips are digital in nature. This course addresses the design of digital circuits in deep submicron technologies.
    The main objective of this course is to train the participants to "think like a circuit designer." The goal is to
    provide intuition and models those are needed to enable somebody to analyze and design digital circuits in
    VLSI domain. The prime aim of the workshop is to provide some real world experience in digital VLSI design
    and how to make design trade-offs to achieve a good balance among speed, power consumption, and reliability
    by the professionals with industrial exposure. We strive to provide the understanding needed to anticipate the
    likely improvements and potential difficulties that may be encountered with future technologies.
    The Course will include presentation and hands-on by our own Professors and from Industries.

    Course Content
    1.
    2. MOSFET Characteristics
    3. Different types of Inverter and their Characteristics, VTC
    4. Static MOS Gate Circuits
    5. Transfer Gate and Dynamic logic Design
    6. SPICE
    7. Floor plan, Stick Diagram, Layout, Post-layout,
    8. DRC, LVS, RCX
    9. All levels of Simulation
    10. Complete Digital Design Flow

    Registration Details
    Registration is mandatory for participants
    1. For Students : Rs.3600/2. For Faculty : Rs.5000/3. For Industry : Rs.6000/-

    4. Amount includes registration kit, e-material, tea & snacks during break.
    5. Send your registration request to sushanta.pattnaik@silicon.ac.in
    6. Registration fees can be deposited on the spot. However registration should be done in advance by mail
    or through online process
    For further details contact
    Prof. Sushant Pattnaik, Course Coordinator, Contact No. 9437082906
    Electronics & Communication Engineering Department
    Silicon Institute of Technology
    Silicon Hills, Patia, Bhubaneswar- 751024
    Ph. No.: (0674) 2725448 Extn. 216/ 218
    Website: www.silicon.ac.in

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