CD4093BC Quad 2-Input NAND Schmitt Trigger: General Description

Revised January 1999
CD4093BC
Quad 2-Input NAND Schmitt Trigger
Equal source and sink currents
General Description
The CD4093B consists of four Schmitt-trigger circuits.
Each circuit functions as a 2-input NAND gate with Schmitttrigger action on both inputs. The gate switches at different
points for positive and negative-going signals. The difference between the positive (VT+) and the negative voltage
No limit on input rise and fall time

Standard B-series output drive
Hysteresis voltage (any input) TA = 25C
Typical
(VT) is defined as hysteresis voltage (VH).

All outputs have equal source and sink currents and conform to standard B-series output drive (see Static Electrical
Characteristics).
Features
VDD = 5.0V
VH = 1.5V
VDD = 10V
VH = 2.2V
VDD = 15V
Guaranteed
VH = 2.7V
VH = 0.1 VDD
Applications
Wave and pulse shapers
Wide supply voltage range:
3.0V to 15V
High-noise-environment systems
Schmitt-trigger on each input
Monostable multivibrators
with no external components
Astable multivibrators
Noise immunity greater than 50%
NAND logic
Ordering Code:
Package Number
Package Description
CD4093BCM
Order Number
M14A
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow Body
CD4093BCN
N14A
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter X to the ordering code.
Connection Diagram
Pin Assignments for SOIC and DIP
Top View
1999 Fairchild Semiconductor Corporation
DS005982.prf
www.fairchildsemi.com
CD4093BC Quad 2-Input NAND Schmitt Trigger
October 1987
CD4093BC
Absolute Maximum Ratings(Note 1)
Recommended Operating
Conditions (Note 2)
(Note 2)
0.5 to +18 VDC
DC Supply Voltage (VDD)

Input Voltage (VIN)
DC Supply Voltage (VDD)
0.5 to VDD +0.5 VDC

65C to +150C
Storage Temperature Range (TS)
700 mW
Small Outline
500 mW
Symbol
IDD
VOL
Parameter
IOL
Typ
+85C
Max
Min
Max
Units
1.0
7.5
2.0
2.0
15.0
VDD = 15V
4.0
4.0
30.0
LOW Level
HIGH Level
Negative-Going Threshold
Positive-Going Threshold
VIN = VDD, |IO| < 1 A

VDD = 5V
0.05
0.05
0.05
VDD = 10V
0.05
0.05
0.05
VDD = 15V
0.05
0.05
0.05
VIN = VSS, |IO| < 1 A

VDD = 5V
4.95
4.95
4.95
VDD = 10V
9.95
9.95
10
9.95
VDD = 15V
14.95
14.95
15
14.95
|IO| < 1 A
VDD = 5V, VO = 4.5V
1.3
2.25
1.5
1.8
2.25
1.5
2.3
VDD = 10V, VO = 9V
2.85
4.5
3.0
4.1
4.5
3.0
4.65
VDD = 15V, VO = 13.5V
4.35
6.75
4.5
6.3
6.75
4.5
6.9
V
V
|IO| < 1 A
VDD = 5V, VO = 0.5V
2.75
3.6
2.75
3.3
3.5
2.65
3.5
VDD = 10V, VO = 1V
5.5
7.15
5.5
6.2
7.0
5.35
7.0
VDD = 15V, VO = 1.5V
8.25
10.65
8.25
9.0
10.5
8.1
10.5
Hysteresis (VT+ VT)
VDD = 5V
0.5
2.35
0.5
1.5
2.0
0.35
2.0
(Any Input)
VDD = 10V
1.0
4.3
1.0
2.2
4.0
0.70
4.0
VDD = 15V
1.5
6.3
1.5
2.7
6.0
1.20
6.0
LOW Level Output
HIGH Level Output

Current (Note 3)
IIN
+25C
Min
1.0
Current (Note 3)
IOH
Max
VDD = 5V
Voltage (Any Input)
VH
Min
VDD = 10V
Voltage (Any Input)
VT+
40C
Conditions
Quiescent Device
Output Voltage
VT
(Note 2)
Current
Output Voltage
VOH
Note 2: VSS = 0V unless otherwise specified.
260C
DC Electrical Characteristics
40C to +85C
Note 1: Absolute Maximum Ratings are those values beyond which the
safety of the device cannot be guaranteed; they are not meant to imply that
the devices should be operated at these limits. The table of Recommended Operating Conditions and Electrical Characteristics provides
conditions for actual device operation.
Lead Temperature (TL)

(Soldering, 10 seconds)
0 to VDD VDC
Operating Temperature Range (TA)
Power Dissipation (PD)

Dual-In-Line
3 to 15 VDC
Input Voltage (VIN)
Input Current
VIN = VDD
VDD = 5V, VO = 0.4V
0.52
0.44
0.88
0.36
mA
VDD = 10V, VO = 0.5V
1.3
1.1
2.25
0.9
mA
VDD = 15V, VO = 1.5V
3.6
3.0
8.8
2.4
mA
VIN = VSS
VDD = 5V, VO = 4.6V
0.52
0.44
0.88
0.36
mA
VDD = 10V, VO = 9.5V
1.3
1.1
2.25
0.9
mA
VDD = 15V, VO = 13.5V
3.6
8.8
2.4
mA
0.3
105
0.3
1.0
VDD = 15V, VIN = 15V
0.3
105
0.3
1.0
Note 3: IOH and IOL are tested one output at a time.
3.0
VDD = 15V, VIN = 0V
(Note 4)
TA = 25C, CL = 50 pF, RL = 200k, Input tr, tf = 20 ns, unless otherwise specified

Symbol
tPHL, tPLH
tTHL, tTLH
Parameter
Propagation Delay Time
Transition Time
Typ
Max
Units
VDD = 5V
Conditions
Min
300
450
ns
VDD = 10V
120
210
ns
VDD = 15V
80
160
ns
VDD = 5V
90
145
ns
VDD = 10V
50
75
ns
VDD = 15V
40
60
ns
7.5
pF
CIN
Input Capacitance
(Any Input)
5.0
CPD
Power Dissipation Capacitance
(Per Gate)
24
pF
Note 4: AC Parameters are guaranteed by DC correlated testing.
CD4093BC
AC Electrical Characteristics
CD4093BC
Typical Applications
Gated Oscillator
Assume t1 + t2 >> tPHL + tPLH then:

t0 = RC ln [VDD/VT]
t1 = RC ln [(VDD VT)/(VDD VT+)]
t2 = RC ln [VT+/VT]
Gated One-Shot
(a) Negative-Edge Triggered
(b) Positive-Edge Triggered
Typical Transfer
Characteristics
Guaranteed Trigger Threshold

Voltage vs VDD
Guaranteed Hysteresis vs VDD
Guaranteed Hysteresis vs VDD
Input and Output Characteristics
VNML = VIH(MIN) VOL VIH(MIN) = V T+(MIN)

VNMH = VOH VIL(MAX) VDD VIL(MAX) = VDD VT(MAX)
CD4093BC
Typical Performance Characteristics
CD4093BC
AC Test Circuits and Switching Time Waveforms
CD4093BC
Physical Dimensions inches (millimeters) unless otherwise noted
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow Body
Package Number M14A
CD4093BC Quad 2-Input NAND Schmitt Trigger
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Package Number N14A
LIFE SUPPORT POLICY

FAIRCHILDS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
2. A critical component in any component of a life support
1. Life support devices or systems are devices or systems
device or system whose failure to perform can be reawhich, (a) are intended for surgical implant into the
sonably expected to cause the failure of the life support
body, or (b) support or sustain life, and (c) whose failure
device or system, or to affect its safety or effectiveness.
to perform when properly used in accordance with
instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the
user.
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.
This datasheet has been downloaded from:

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Revised January 1999

No limit on input rise and fall time

(VT) is defined as hysteresis voltage (VH).

Wide supply voltage range:

Schmitt-trigger on each input

with no external components

Noise immunity greater than 50%

14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

1999 Fairchild Semiconductor Corporation

CD4093BC Quad 2-Input NAND Schmitt Trigger

Absolute Maximum Ratings(Note 1)

DC Supply Voltage (VDD)

DC Supply Voltage (VDD)

0.5 to VDD +0.5 VDC

Storage Temperature Range (TS)

VIN = VDD, |IO| < 1 A

VIN = VSS, |IO| < 1 A

VDD = 15V, VO = 13.5V

VDD = 15V, VO = 1.5V

Hysteresis (VT+ VT)

LOW Level Output

HIGH Level Output

Voltage (Any Input)

Voltage (Any Input)

Note 2: VSS = 0V unless otherwise specified.

Lead Temperature (TL)

Operating Temperature Range (TA)

Power Dissipation (PD)

Input Voltage (VIN)

VDD = 10V, VO = 0.5V

VDD = 15V, VO = 1.5V

VDD = 10V, VO = 9.5V

VDD = 15V, VO = 13.5V

VDD = 15V, VIN = 15V

Note 3: IOH and IOL are tested one output at a time.

VDD = 15V, VIN = 0V

TA = 25C, CL = 50 pF, RL = 200k, Input tr, tf = 20 ns, unless otherwise specified

Power Dissipation Capacitance

Note 4: AC Parameters are guaranteed by DC correlated testing.

Assume t1 + t2 >> tPHL + tPLH then:

(b) Positive-Edge Triggered

Guaranteed Trigger Threshold

Guaranteed Hysteresis vs VDD

Guaranteed Hysteresis vs VDD

Input and Output Characteristics

VNML = VIH(MIN) VOL VIH(MIN) = V T+(MIN)

Typical Performance Characteristics

AC Test Circuits and Switching Time Waveforms

Physical Dimensions inches (millimeters) unless otherwise noted

CD4093BC Quad 2-Input NAND Schmitt Trigger

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

LIFE SUPPORT POLICY

This datasheet has been downloaded from:

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