Effect of Output Capacitor ESR On Dynamic Performance of Voltage-Mode Hysteretic Controlled Buck Converter

Effect of output capacitor ESR on dynamic
performance of voltage-mode hysteretic

controlled buck converter
Note that the switching period T = TON + TOFF is mainly determined by

the inductance, the output capacitor ESR and two references.
If the condition IL = 2Io can be satised, the inductor current iL
decreases to zero just at the end of this switching cycle, in this case
B.C. Bao, J. Yang, J.P. Xu, X. Zhang and G.H. Zhou
VH VL = rDIL = 2rIo =
Different types of capacitors have different parameters, e.g. equivalent

series resistance (ESR) and capacitance. In switching DCDC converters with voltage-mode (VM) hysteretic control, the output capacitor ESR has a signicant effect on dynamic performance. In this
reported work, two critical conditions of the output capacitor ESR
for mode shifting and normal operation of the VM hysteretic controlled
buck converter are derived. These results, veried by circuit simulations, illustrate that the larger output capacitor ESR is necessary for
the converter operating normally; otherwise, the converter operates
abnormally.
Introduction: With the benets of low cost and ease of implementation,

voltage-mode (VM) hysteretic control, a variable frequency control, is
very popular for power supplies of microprocessors and other
high-slew-rate transition loads [13]. As the same as constant on-time
control [4] and xed off-time control [5], when VM hysteretic control
is used for switching DCDC converters, a large output capacitor equivalent series resistance (ESR) is usually recommended for normal operation [3]. For the switching DCDC converters with VM hysteretic
control, a ceramic capacitor is not suitable owing to its very low ESR,
resulting in the converter generating large output voltage ripple and
operating in discontinuous conduction mode (DCM); whereas electrolytic capacitors and tantalum capacitors are good choices because of
their larger ESR [3], making the converter operate normally with continuous conduction mode (CCM). Therefore, in the VM hysteretic controlled switching DCDC converters, the output capacitor ESR has a
great inuence on the dynamic performance. In this Letter, a VM hysteretic controlled buck converter is taken as an example to deduce the
critical output capacitor ESRs for mode shifting and normal operation.
VM hysteretic controlled buck converter: The circuit schematic of the
VM hysteretic controlled buck converter and its main steady-state operation waveforms are shown in Figs. 1a and b. Compared with the xedfrequency pulse-width modulation control method, VM hysteretic
control does not have an oscillator and an error amplier. There is
only a hysteresis window with two references, high reference VH and
low reference VL as Fig. 1b shows. The output voltage is fed back to
keep tracking references within the hysteretic window. Both references
determine the turn-on and turn-off of the switch to control the output
voltage.
iL
S
+
iC
C
D
r
I
+ o +
vC
+ R vo
vESR
Q S
Q R
VH
VL
Io
iL
vC_ripple
vo
Dvo_ripple
VL
TOFF
Q TON
T1
T2
T
Fig. 1 VM hysteretic controlled buck converter and its steady-state

waveforms
a VM hysteretic controlled buck converter
b Steady-state waveforms
If the output ripple voltage is much smaller than the average output
voltage at the steady state, the output current Io is relatively constant
and the inductor current ripple IL ows completely through the
output capacitor. From Fig. 1b, it can be found that the following
relationship exists [3]
VH VL = rDIL =
r(E VL )TON rVH TOFF

=
L
L
(1)
Therefore, we have
TON =

L VH VL
,
r E VL
TOFF =

L VH VL
r
VH
R(VH VL )
(4)
VH + VL
is the critical condition for the operation mode of the buck converter
shifting between CCM and DCM.
r = rcritical, m =
Critical output capacitor ESR for normal operation: Let t = 1+ and t

= 2+ represent the beginning of the on-time interval and the off-time
interval in the nth switching cycle, respectively. From Fig. 1b, it can
be found that if the slope of output voltage vo_ripple is larger than or
equal to zero at the time instant 1+, vo will always be higher than VL
in the on-time interval; if the slope of vo_ripple is smaller than or equal
to zero at 2+, vo will always be lower than VH in the off-time interval.
Thus, the slope of vo_ripple equal to zero is the critical condition for
normal operation of the buck converter.
At t = 1+, the slopes of iL, vESR and vC_ripple are

diL
E VL
(5)
=
dt t=t1+
L

dvESR
d[r(iL Io )]
E VL
(6)
=
=r

dt
dt t=t1+
L
t=t1+

dvC ripple
iL Io
DIL
TON E VL
=
=
=
dt t=t1+
C t=t1+
2C
2C
L
(2)
(7)
respectively. Therefore, the slope of output ripple voltage vo_ripple yields

d vC ripple + vESR
dvo ripple
TON diL
=
= r
(8)

dt
dt
2C dt t=t1+
t=t1+
t=t1+
Similarly, at t = 2+, the slopes of iL and vo_ripple can be easily derived as

diL
VH
=
(9)
dt t=t2+
L

dvo ripple
TOFF diL
=
r
dt t=t2+
2C dt t=t2+
Thus, if the following condition can be satised

r . rcritical = max rcritical,1 , rcritical,2
(3)
Thus
Substitute (2) into (8) and (10), and let

L VH VL
rcritical,1 =
2C E VL

L VH VL
rcritical,2 =
VH
2C
vESR
VH
r(VH + VL )
R
(10)
(11)
(12)
the variation of output voltage vo follows the variation of inductor

current iL completely. Thus, to ensure normal operation, the ESR r
must be greater than rcritical. Otherwise, the converter will work abnormally due to the occurrence of output voltage lagging behind inductor
current.
As in steady state, vESR is in phase with iL and the phase of vC_ripple is
90 delay of the phase of iL, the phase of vo_ripple may not be consistent
with the iL phase, resulting in the output voltage exceeding the hysteretic
window.
Simulations under different ESRs: A simulation circuit model has been
built by using the PSIM software. The circuit parameters are E = 12 V,
VH = 5.03 V, VL = 4.97 V, L = 200 H, C = 470 F and R = 5 . vo is
regulated at 5 V. The simulation results of output voltage vo with two
references VH and VL, inductor current iL and ESR voltage vESR with
output capacitor ripple voltage vC_ripple of the VM hysteretic controlled
buck converter under different ESR are shown in Fig. 2.
ELECTRONICS LETTERS 26th September 2013 Vol. 49 No. 20 pp. 12931294
Conclusion: The output capacitor ESR is an important parameter in the

VM hysteretic controlled buck converter. When electrolytic capacitors
and tantalum capacitors with large ESRs are used for the output capacitor, the converter operates normally in CCM; whereas if a ceramic
capacitor is used as the output capacitor, the converter operates abnormally in DCM. The result can provide a useful guideline for the
design of the VM hysteretic controlled switching DCDC converters.
vo, V
5.03
VL VH
5
4.97
iL, A
1.6
vESR, mV
0.4
30
Acknowledgment: This work was supported by the National Natural

Science Foundation of China (grants 51177140 and 51277017).
0
vC_ripple
30
5.5
5.6
5.7
5.8
time, ms
5.9
vo, V
a
5.03
5
4.97
VL
The Institution of Engineering and Technology 2013

19 June 2013
doi: 10.1049/el.2013.2043
VH
B.C. Bao, J. Yang and X. Zhang (School of Information Science and

Engineering, Changzhou University, Changzhou 213164, Jiangsu,
Peoples Republic of China)
iL , A
2
1
vESR, mV
0
30
0
30
5.5
E-mail: mervinbao@126.com
vC_ripple
5.6
5.7
5.8
time, ms
5.9
Fig. 2 Simulation results of VM hysteretic controlled buck converter under

different ESRs
a r = 51 m
b r = 25 m
For the above parameters, the critical values of ESR can be calculated
as rcritical,1 = 42.6 m, rcritical,2 = 50.4 m and rcritical = 50.4 m from
(11) and (12). The output capacitor ESR in Fig. 2a is larger than rcritical,
implying that the converter operates in normal periodic oscillation;
whereas the output capacitor ESR in Fig. 2b is smaller than rcritical, indicating that the converter operates abnormally with larger output voltage
ripple. In addition, the output capacitor ESR in Fig. 2b is smaller than
rcritical,m = 30 m, implying that the converter operates in DCM.
J.P. Xu and G.H. Zhou (School of Electrical Engineering, Southwest

Jiaotong University, Chengdu 610031, Sichuan, Peoples Republic of
China)
References
1 Castilla, M., Garca de Vicua, L., Guerrero, J.M., Matas, J., and Miret,
J.: Design of voltage-mode hysteretic controllers for synchronous buck
converters supplying microprocessor loads, Proc. IEE, Electr. Power
Appl., 2005, 152, (5), pp. 11711178
2 Castilla, M., Guerrero, J.M., Matas, J., Miret, J., and Sosa, J.:
Comparative study of hysteretic controllers for single-phase voltage
regulators, IET Power Electron., 2008, 1, (1), pp. 132143
3 Monolithic Power Systems, Inc.: The MP2905 hysteresis voltage controller application note, MPS, 2011. [Online]. Available at http://www.
monolithicpower.com/DesignNoteDoc/AN023_r1.0.pdf
4 Wang, J.P., Xu, J.P., and Bao, B.C.: Pulse bursting phenomenon in constant on-time controlled buck converter, IEEE Trans. Ind. Electron.,
2011, 58, (12), pp. 54065410
5 Bao, B.C., Zhang, X., Xu, J.P., and Wang, J.P.: Critical ESR of output
capacitor for stability of xed off-time controlled buck converter,
Electron. Lett., 2013, 49, (4), pp. 540541
ELECTRONICS LETTERS 26th September 2013 Vol. 49 No. 20 pp. 12931294

Effect of Output Capacitor ESR On Dynamic Performance of Voltage-Mode Hysteretic Controlled Buck Converter

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Effect of output capacitor ESR on dynamic

performance of voltage-mode hysteretic

Note that the switching period T = TON + TOFF is mainly determined by

B.C. Bao, J. Yang, J.P. Xu, X. Zhang and G.H. Zhou

Different types of capacitors have different parameters, e.g. equivalent

Introduction: With the benets of low cost and ease of implementation,

Fig. 1 VM hysteretic controlled buck converter and its steady-state

r(E VL )TON rVH TOFF

Critical output capacitor ESR for normal operation: Let t = 1+ and t

respectively. Therefore, the slope of output ripple voltage vo_ripple yields

Thus, if the following condition can be satised

Substitute (2) into (8) and (10), and let

the variation of output voltage vo follows the variation of inductor

ELECTRONICS LETTERS 26th September 2013 Vol. 49 No. 20 pp. 12931294

Conclusion: The output capacitor ESR is an important parameter in the

Acknowledgment: This work was supported by the National Natural

The Institution of Engineering and Technology 2013

B.C. Bao, J. Yang and X. Zhang (School of Information Science and

Fig. 2 Simulation results of VM hysteretic controlled buck converter under

J.P. Xu and G.H. Zhou (School of Electrical Engineering, Southwest

ELECTRONICS LETTERS 26th September 2013 Vol. 49 No. 20 pp. 12931294

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