Processing Unit: A Which Performs Operations On Data, Which Stores
Processing Unit: A Which Performs Operations On Data, Which Stores
Processing Unit: A Which Performs Operations On Data, Which Stores
Memory
Programs (instructions)
Data
BUS
Processing Unit
e.g. ARM7TDMI
+ - = ? &
1
8 bits
1 byte
0xA1000040
0xA1000041
0xA1000042
0xA1000043
0xA1000044
0xA1000045
0xA1000046
0xA1000047
0xA1000048
0xA1000049
0xA100004A
0xA100004B
0xA100004C
0xA100004D
0xA100004E
0xA100004F
0xA1000050
??
??
??
??
h
e
l
l
o
??
??
??
??
??
??
??
??
Memory
2
ARM7TDMI is based on a
Load Store Architecture
Cannot directly perform
operations (e.g. addition,
subtraction, comparison, ... )
on values in memory
Only way to operate on a
value stored in memory is to
load it into a register, then
operate on the register
Only way to change a value
in memory is to store the
value from a register into
memory
RISC
CISC
(e.g. ARM)
(e.g. x86)
Simple
operations
Complex
operations
Small / simple
design
Large / complex
Design
More operations
per unit time
Fewer operations
per unit time
Trade-off
address = address + 1
char = Memory.byte[address]
}
}
8 bits
1 byte
0xA1000040
0xA1000041
0xA1000042
0xA1000043
0xA1000044
0xA1000045
0xA1000046
0xA1000047
0xA1000048
0xA1000049
0xA100004A
while (char 0)
{
if (char a AND char z)
{
char = char AND 0xFFFFFFDF
Memory.byte[address] = char
}
address = address + 1
char = Memory.byte[address]
}
0xA100004B
0xA100004C
0xA100004D
0xA100004E
0xA100004F
0xA1000050
??
??
??
??
h
e
l
l
o
00
??
??
??
??
??
??
??
Memory
5
Load Rd = Memory.<size>[<address>]
Store Memory.<size>[<address>] = Rd
start
LDR
wh1
ADD
LDRB
CMP
BNE
stop
B
CMP
BCC
CMP
BHI
BIC
STRB
endif1
testwh1
stop
Indirect Addressing
Endianness
0xA10000D9
0xA10000DA
0xA10000DB
0xA10000DC
02
03
04
Big-endian
05
0xA10000DD
00
01
02
03
04
05
06
07
Memory
05
04
03
02
Little-endian
11
??
??
32
04
85
EB
??
??
0xA1000042
0xA1000043
0xA1000044
0xA1000045
0xA1000046
0xA1000047
0xA1000048
0xA1000049
00
00
00
31
00
31
LDR
LDR
r0, =0xA1000044
r1, [r0]
EB
31
32
8 7
00
04
32
16 15
85
04
32
0
12
r0, =0xA1000044
r1, [r0]
00
00
00
31
32
8 7
0
0xA1000042
LDR
r0, =0xA1000044
LDRSH r1, [r0]
0xA1000043
00
31
00
04
32
16 15
0xA1000044
0xA1000045
0xA1000046
0xA1000047
0xA1000048
LDR
LDRSB
r0, =0xA1000046
r1, [r0]
FF
FF
FF
31
LDR
r0, =0xA1000046
LDRSH r1, [r0]
FF
31
8 7
FF
EB
16 15
0xA1000049
85
??
??
32
04
85
EB
??
??
Remember:
interpretation!!
85
0
13
LDR
r1, =teststr
start
...
...
<rest of program>
...
...
teststr
AREA
DCB
; address = 0xA1000000
...
...
END
14
DCD
DCD
DCB
DCB
2 half-word values
values
DCW
407, -208
15
AREA directive
Marks the beginning of a section and specifies attributes for
the section
Sections are indivisible sequences of instructions and/or data
Attribute examples: CODE, READONLY, DATA, READWRITE
Attributes define how a section is loaded into memory
Programs must contain at least one CODE section
END directive
Tells the assembler to stop processing the source file
16
Alignment
Not word-aligned
Half-word aligned
1 0
1 0 1 1 0 1 1
31 30
8 bits
1 byte
00
01
02
03
04
05
06
07
08
09
10
0xA10000D6
0xA10000D7
0xA10000D8
0xA10000D9
0xA10000DA
0xA10000DB
0xA10000DC
0xA10000DD
0xA10000DE
0xA10000D8
1 0
1 0 1 1 0 0 0
31 30
0xA10000DF
0xA10000E0
Memory
04
03
02
04
03
02
05
18
Immediate post-indexed
<address> = Rn
Rn = Rn +/- <12-bit offset>
r0,
r1,
r2,
r3,
=0xA1001000
[r0], #2
[r0], #2
[r0], #2
;
;
;
;
start
AREA
IMPORT
EXPORT
LDR
r1, =teststr
LDRB
CMP
BNE
; address = 0xA1000000
; while ( (char = Memory.byte[address])
testwh1
;
!= 0 ) {
r0, #'a'
; if (char >= 'a'
endif1
;
AND
r0, #'z'
;
char <= 'z')
endif1
; {
r0, #0x00000020 ;
char = char AND NOT 0x00000020
r2, r1, #1
;
store_address = address - 1
r0, [r2]
;
Memory.byte[store_addres] = char
; }
r0, [r1], #1
; }
r0, #0
;
wh1
;
stop
stop
teststr
AREA
DCB
wh1
endif1
testwh1
B
CMP
BCC
CMP
BHI
BIC
SUB
STRB
END
20
r0,
r1,
r2,
r3,
=0xA1001000
[r0]
[r0, #4]
[r0, #8]
;
;
;
;
21
start
AREA
IMPORT
EXPORT
LDR
r1, =teststr
LDRB
CMP
BNE
; address = teststr
; while ( (char = Memory.byte[address])
testwh1
;
!= 0 ) {
r0, #'a'
; if (char >= 'a'
endif1
;
AND
r0, #'z'
;
char <= 'z')
endif1
; {
r0, #0x00000020 ;
char = char AND NOT 0x00000020
r0, [r1, #-1]
;
Memory.byte[addres - 1] = char
; }
r0, [r1], #1
; }
r0, #0
;
wh1
;
stop
stop
teststr
AREA
DCB
wh1
endif1
testwh1
B
CMP
BCC
CMP
BHI
BIC
STRB
END
22
Register offset
<address> = Rn +/- Rm
r0,
r4,
r1,
r4,
r2,
r4,
r3,
=0xA1001000
=0
[r0, r4]
r4, #2
[r0, r4]
r4, #2
[r0, r4]
;
;
;
;
;
;
;
LDR
LDR
r1, =teststr
r2, =0
start
wh1
ADD
LDRB
CMP
BNE
stop
B
CMP
BCC
CMP
BHI
BIC
STRB
endif1
testwh1
stop
; address = teststr
; offset = 0
24
Option 1
Use offset for
loop condition
Option 2
Use separate
counter for
loop condition
EQU
100
MOV
LDR
MOV
LDR
R0,
R1,
R2,
R3,
#0
=nums
#0
=MAX
do1
LDR
ADD
ADD
SUBS
BCS
R4,
R0,
R2,
R3,
do1
[R1, R2]
R0, R4
R2, #4
R3, #1
stop
stop
nums
AREA
DCD
...
MAX
start
;
;
;
;
;
;
;
;
;
;
sum = 0
address = nums
offset = 0
count = MAX
do {
tmp = Memory.word[address + offset]
sum = sum + tmp
offset = offset + 4
count = count - 1
} while (count > 0)
END
26
r0,
r4,
r1,
r4,
r2,
r4,
r3,
MAX
AREA
IMPORT
EXPORT
EQU
100
MOV
LDR
MOV
R0, #0
R1, =nums
R2, #0
LDR
ADD
ADD
CMP
BCC
R0, R0, R3
R2, R2, #1
R2, #MAX
do1
stop
...
...
start
do1
stop
;
;
;
;
sum = 0
address = nums
offset = 0
do {
tmp = Memory.word[address
+ offset * 4]
; sum = sum + tmp
; offset = offset + 1
; } while (offset < MAX)
;
END
28
Syntax
W, B
H, SH, SB Operation
Immediate Offset
[<Rn>, #+/-<offset>]
Register Offset
[<Rn>, +/-<Rm>]
address Rn +/- Rm
Immediate Pre-Indexed
[<Rn>, #+/-<offset>]!
Rn Rn +/- offset
address Rn
Register Pre-Indexed
[<Rn>, +/-<Rm>]!
Rn Rn +/- Rm
address Rn
Immediate Post-Indexed
[<Rn>], #+/-<offset>
address Rn
Rn Rn +/- offset
Register Post-Indexed
[<Rn>], +/-<Rm>
address Rn
Rn Rn +/- Rm
address Rn
Rn Rn +/- (Rm <shift> <count>)
29
30
31
32