Opamp Design

CMOS Analog Design
Mini Project 1
PART 1: gm/ID Design Charts
NMOS
PMOS
PART 2: OTA Design
Sizing of input pair (M0, M1)
Justify why you used NMOS or PMOS input pair for each stage.
In the first stage we used PMOS because we want CMIR close to the
ground.
Choosing NMOS transistor for 2nd stage input to match the first stage
current mirror Load and 2nd stage load PMOS to match the first stage
tail current source.
gm/gds
Information about M0,M1

W L Vgs V* Vdsat gm gm/id id
16.63 400 886.7 119.9 95.61 83.38 17 V^- 5 uA
um nm mV mV mV uS 1
Sizing of current mirror load(M3,M4)
VGS
Information about M3,M4
2.14 um 450 nm 775 mV 153.8 127.2 65.01 13 V^-1 5 uA
mV mV uS
Vicm(min) = 0.082 V ➔ 0.082 V < 0.2 V

Note ➔ this Vicm(min) calculated by V* not Vdsat
This is good to give good margin about this value
When we calculate Vicm(min) by Vdsat Will be smaller than 0.08 V
Sizing of tail ( M2)
Information about M2
63.82 640 nm 819.2 119.3 85.28 167.7 17 V^-1 10 uA
um mV mV mV uS
Vicm(max) = 0.83 V ➔ 0.83 V > 0.8 V

Sizing of NMOS in second stage ( M7 )
Sizing of second stage load(M8)
We will do a sweep on the width of the NMOS load first stage to make
vds=0.9v.
W=13.35um
Note: we will make some fine tuning for the Cc,Rz,W of the second
stage input to adjust phase margin and slew rate.
Rz=1.6kΩ 1.8kΩ
Cc=2pF 1.7pF
W=34.38um 45um
A table showing W, L, 𝑔𝑚, 𝐼𝑑, 𝑔𝑚/𝐼𝑑 , 𝑉𝑑𝑠𝑎𝑡, 𝑉𝑜𝑣= 𝑉𝑔𝑠−𝑉𝑡ℎ , and 𝑉
∗=2*𝑔𝑚/𝐼𝑑 of all transistors (as calculated from gm/ID curves).
Transistor 1st stage 1st stage tail 2nd 2nd stage

input load stage load
&current
pair input
mirror
𝑾 16.63um 13.35um 63.82um 45um 239.3um
𝑳 400nm 450 nm 640nm 350nm 640n
𝒈𝒎 83.38 uS 97.76 uS 167.7 uS 628.6uS 633.5uS
𝑰𝑫 5 uA 5 uA 10 uA 37.5 uA 37.5 uA
𝒈𝒎 17 20 17 17 17
𝑰𝑫
𝑽∗ 119.9mv 102.3mv 119.3mv 119.3mv 118.4mv
𝑽𝒐𝒗 32.2 mv -37.8mv 31.2mv 2.8mv 28.7 mv
Note: Vov in the NMOS transistors have no meaning because they are
in the subsresthold.
PART 3: Open-Loop OTA Simulation
Schematic of the OTA and bias circuit with DC node voltages clearly annotated.
OTA Schematic
bias circuit with DC node voltages
Is the current (and gm) in the input pair exactly equal?

-YES
What is DC voltage at the output of the first stage? Why?
Vout1=Vds3=663.1mv (From the DC op), Because it depends on the value of VDS of
the current mirror load.
What is DC voltage at the output of the second stage? Why?
Vout2=Vds8=900.6mv≈900mV (From the DC op), because I designed it to be equal
to 0.9V to have maximum output swing.
Diff small signal ccs:

Using Cadence calculator expressions to calculate circuit parameters (Ao, Ao in dB,
BW, GBW, UGF).
Diff gain in dB with Frequency

Hand Analysis
Compare simulation results with hand calculations in a table.

Avd BW (kHz) GBW(MHz) Fu
(MHz)
Simulator 3.042k 2.444 7.434 7.085
(69.7 dB)
Hand 3.055k 2.544 7.77 7.77
analysis (69.66dB)
CM small signal ccs:
Plot CM gain in dB vs frequency.
Hand analysis

Avcm
Simulator 188.2m
(-14.51 dB)
Hand 259.05m
analysis (-11.73dB)
(Optional) CMRR:
Plot CMRR in dB vs frequency.
Hand Analysis

Avcm
Simulator 93.694 dB
Hand 81.434 dB
analysis
(Optional) Diff large signal ccs:
Plot VOUT vs VID.
From the plot, what is the value of Vout at VID = 0. Compare it with the value you
obtained in DC OP.
Vout At Vid=0 = 900.65mV, Vout (DC OP) = 900.6mV approximately equal.
Plot the derivative of VOUT vs VID.
Is the peak less than the value of Avd obtained from ac analysis? Why?
No, because in DC analysis I used a very small step 45 uV.
CM large signal ccs (region vs VICM):
Plot “region” OP parameter vs VICM for the input pair and the tail current source.
Hand Analysis

CMIRlow CMIRhigh
Simulator ≈0 0.878
Hand -0.15884≈0 0.802
analysis
(Optional) CM large signal ccs (GBW vs VICM)
Plot GBW vs VICM
Plot the results overlaid on the results of the previous method (region parameter).
Annotate the CM input range. Calculate the input range as the range over which
the GBW is within 90% of the max GBW
CM input range=888.67mV
PART 4: Closed-Loop OTA Simulation
Schematic of the OTA
bias circuit with DC OP point
Are the DC voltages at the input terminals of the op-amp exactly equal? Why?
No, because of the mismatch because there is negative feedback which leads to static
error it is very small because Aol is very high but not infinite.
Is the DC voltage at the output of the first stage exactly equal to the value in the open-
loop simulation? Why?
No, because there is negative feedback which leads to mismatch.
Is the current (and gm) in the input pair exactly equal? Why?
No, because there is negative feedback which leads to mismatch.
Loop gain
Plot loop gain in dB and phase vs frequency.
Phase
Simulator Results
Compare DC gain, fu, and GBW with those obtained from open-loop simulation.
Comment
(MHz)
Open loop 3.042k 2.444 7.434 7.085
(69.7 dB)
Closed loop 2.924k 2.539 7.442 7.082
(69.32dB)
Comment: since β=1 simulation results is approximately equal.

PM hand calculation
Compare with hand calculations.

PM
Simulator 70.33
Hand 70.18
analysis
Comment: since PM<76 we will see ringing in the time domain.
Hand Analysis
(MHz)
Closed loop 2.924k 2.539 7.442 7.082
(69.32dB)
Hand 2935.34 2.65 7.78 7.77
analysis (69.35dB)
Slew rate:
Report Vin and Vout overlaid.
Report the slew rate.
Note
when I runned first time the Slew rate was 4.763 I think this because parasitic capacitance and
current on tail equal 9.679 uA not exact 10 uA
Since slew rate = ( I tail / Cc+Cparasitic ) To achieve )SR=5) I will decrease the Cc slightly But phase
margin will affected so I will increase Rz slightly to achieve PM > 70 degree
This increase in Rz will make ZERO go to Wpnd so I will check graph with this fine tuning
𝑰𝑩𝟏
SR= =5.31
𝑪𝒄
Compare simulation results with hand calculations in a table

slew
rate(V/us)
Simulator 4.97
Hand analysis 5.31
Settling time
Calculate the output rise time from simulation
Hand analysis
Compare simulation results with hand calculations in a table

Trise(ns)
Simulator 32.55
Hand analysis 45.51
Vout vs Vin
Do you see any ringing? Why?

Yes, because PM is less than 74 degrees.
Part 5 (optional): DC Closed Loop AC Open-Loop OTA Simulation
Schematic of OTA
Bias circuit with DC OP

Diff small signal ccs:
Diff gain in dB with Frequency
Results from simulator
CM small signal ccs:

Plot CM gain in dB vs frequency.
(Optional) CMRR
(Optional) Diff large signal ccs:

Plot VOUT vs VID.
Plot the derivative of VOUT vs VID.

CM large signal ccs (region vs VICM):
Plot “region” OP parameter vs VICM for the input pair and the tail current source.
(Optional) CM large signal ccs (GBW vs VICM)

Plot GBW vs VICM
Plot the results overlaid on the results of the previous method (region parameter).

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CMOS Analog Design

Information about M0,M1

Vicm(min) = 0.082 V ➔ 0.082 V < 0.2 V

Vicm(max) = 0.83 V ➔ 0.83 V > 0.8 V

Transistor 1st stage 1st stage tail 2nd 2nd stage

𝑾 16.63um 13.35um 63.82um 45um 239.3um

𝑳 400nm 450 nm 640nm 350nm 640n

𝒈𝒎 83.38 uS 97.76 uS 167.7 uS 628.6uS 633.5uS

𝑽𝒐𝒗 32.2 mv -37.8mv 31.2mv 2.8mv 28.7 mv

bias circuit with DC node voltages

Is the current (and gm) in the input pair exactly equal?

Diff small signal ccs:

Diff gain in dB with Frequency

Compare simulation results with hand calculations in a table.

Compare simulation results with hand calculations in a table.

Compare simulation results with hand calculations in a table.

Plot the derivative of VOUT vs VID.

Compare simulation results with hand calculations in a table.

bias circuit with DC OP point

Comment: since β=1 simulation results is approximately equal.

Compare with hand calculations.

Report the slew rate.

Compare simulation results with hand calculations in a table

Compare simulation results with hand calculations in a table

Do you see any ringing? Why?

Bias circuit with DC OP

Results from simulator

CM small signal ccs:

(Optional) Diff large signal ccs:

Plot the derivative of VOUT vs VID.

(Optional) CM large signal ccs (GBW vs VICM)

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