Automotive Electronics

Product Information
Companion IC with 5 V ADC
Companion
CY100 IC with 5V ADC - CY100

The CY100 is designed to assist a low voltage

microcontroller in automotive applications. The eight
channel 10 bit analogue-to-digital converter ADC
operates half-automatically with 5 V-inputs. Because of
the possibility of slew rate limitation, the ISO interface
can operate both in BSS and LIN applications. Two
signal stages with diagnosis can be used to control small
signal loads like light emitting diodes (LEDs). With the
SPI interface the controller can communicate without
real time conditions up to 2 Mbaud.
Eight channel 10 bit A / D converter with 5 V
interface for 3.3 V or 2.5 V controllers for
automotive, truck and 42 V applications
Features
 Eight channel 10 bit A / D converter
 Approved ISO interface , slew rate limitation,
Customer benefits: bidirectional serial interface driver according
 Excellent system know-how ISO 9141
 Two small signal stages with diagnostics
 Smart concepts for system safety
 SPI interface
 Secured supply
 All I / O ports designed for 2.5 V to 3.6 V logic
 Long- term availability of manufacturing processes
level
and products  Package : LQFP32
 QS9000 and ISO/TS16949 certified

1
 Block diagram Pin description

Pin Name Function

AREF GNDA VDD5A CLK VDD5 16 RX Receiver output driver ISO 9141
15 TX Transmitter input driver ISO 9141
14 RT Input/output driver ISO 9141
AN_IN0..7
13 UB_REF UB-Reference for theISO 9141 receiver
RAM
AD Converter 9 A1 Output small signal stage 1
10 A2 Output small signal stage 2
8 Channel 8 E1 Input small signal stage 1
Reset
7 E2 Input small signal stage 2
INT + Logic
32 AN_IN0 Analog input 0
31 AN_IN1 Analog input 1
SI 30 AN_IN2 Analog input 2
SO 29 AN_IN3 Analog input 3
SPI-Interface 28 AN_IN4 Analog input 4
SCK 27 AN_IN5 Analog input 5 (only half sample rate
SPI
SS of the others channels )
(for diagnosis) Reset
26 AN_IN6 Analog input 6
25 AN_IN7 Analog input 7
22 CLK CLK-input for the A-to-D Converter
small signal ( Necessary to enable the CY100 )
stages 23 INT Interrupt-Output for the A-to-D
E1 Reset
UBREF Converter
ISO-Interface
-1 17 SS SPI slave-select signal
RX 19 SO Slave-Out signal ( SPI data output )
E2 2x ISO9141
18 SI Slave-In signal ( SPI data input )
20 SCK SPI serial clock input
A2 TX
-1
1 AREF Analog reference voltage for the ADC
2 VDD5A Analog supply voltage 5 V
A1 RT 3 GNDA Analog ground
Reset 12 UBat UBat Pin for ESD protection
RST TST GNDL GND2 VDDIO UBat 6 VDD5 5 V - digital supply
21 VDDIO 3.3 V / 2.5 V - supply for IO
5 GND1 Digital-ground mainly for on chip
digital modules
11 GND2 Digital-ground mainly for on chip
power modules like ISO, KSA and
SPI
4 RST Reset-input
24 TST not used -> to be connected to ground
Application example

VDD5
MUX

AN_IN0 Rmux Maximum ratings

Rmux S&H
Rmux Parameter Min Max Unit
GNDA Rmux Cs Maximum Voltage, RT -15 60 V
Rmux Maximum Voltage, UBat, UB_REF -2 60 V
Rmux Maximum Voltage, A1, A2 -0.6 60 V
Maximum Voltage, VDD5, -0.3 6 V
VDD5
Rmux
Rmux ADC (10 Bit; SAR) VDD5A, AREF -0.3 4 V
AN_IN3
Rin
Maximum Voltage, VDDIO -0.3 UVDD5 V
Maximum Voltage, AN_INx, CLK + 0.3
01 1011 0101

AREF
offset E1, E2, RST, SCK, SI, SS, TX -0.3 UVDDIO V
Cmax
channel
digital offset Maximum Voltage, INT, RX, SO + 0.3
Frequency operating range 2.5 12 MHz
GNDA compensation
Rmux
Maximum SPI transfer rate 2 MBd
TT estm 3
R offset
result register Operating temperature Tj -40 150 C
DSon
TESTM3
reference Thermal resistance 60 K/W
for compensation RAM ESD HBM, MIL883D 3015
GNDA Bank0 Bank1
100pF / 1.5k
A1, A2, RT -4 +4 kV
Control
INT ADC - SPI transfer
All other pins -2 +2 kV
internal bus register (BIOR)

fCCLK SPI
(= 2.5MHz or 3MHz)

fcycle Divider 2 Divider 1

(2500, 3000, (1,2,3 or 4)
5000 or 6000) CLK

2
A/D Converter (ADC) Serial Interface / ISO Driver

The CY100 uses a 10 Bit SAR (successive approximation Integrated in the CY100 is one bi-directional serial
register) Converter with S&H (sample and hold) interface driver, enabling data transfer according to ISO
element. The total error (gain, offset, non linearity) is 9141. The driver can be used, for example, as the
less than 2 LSB and less than 4 LSB near ground or diagnosis interface, for an immobilizer or for a generator
AREF. The CY100 has an internal offset compensation interface. If the interface is not used, the transmitter
algorithmus. The conversion and sample time for each side can be deployed as a small-signal stage.
channel is faster than 125 us. The ADC is mixed to 8
external input channels except channel 5, which is The input/output pin RT is protected against destruction
additional multiplexed with the internal channel for the from ISO impulses 3a and 3b.
CY100 offset compensation on chip.
So a converting time of 1 ms of channel 0 to 4 and 6 SPI-Bi ts
VDDIO VDDIO (SOT_EN, ISO_DL Y)
to 7 can reached, whereas channel 5 can be converted shut off time /
RT
shut off filter time
every 2 ms. All 8 channels are running in timed mode
without jitter.
Transmitter
The input voltage range is 0 V. 5.5 V. The input pins TX
AN_INx are clamped to VDD5 and GND by an ESD
protection diode. The ADC has a separate reference
other
input pin AREF. modules slew rate
SPI-Bit (ISO_SRC)

After conversion of all 8 channels the results are control

UB_REF
storaged in the result RAM. After ending the conversion Reset signal
of channel 7 the output INT becomes active (low). This RST

output can be used to trigger a microcontroller with

interrupt or DMA request.
Receiver
RX
Parameter Min Max Unit
Input range -0.3 UVDD5A V
+ 0.3
Switched capacitance 20 pF
Resolution for the input range 10 Bit
Conversion time for each 122 s
channel ( f=2,5 MHz ) divider on/off
Maximum sample rate 1 kHz
AREF = 5 V :
Resolution, 0.1 V < AN_INx < 2 LSB
4.9 V 4 LSB
Resolution, AN_INx 100 mV 4 LSB
Resolution, AN_INx 4.9 V Parameter Min Max Unit
RT low level at IRT = 40 mA 1.4 V
VDD5 RT nominal output current 50 mA
MUX RT off state input current -5 10 A
RT slew rate limitation, negative 1 3 V/ s
AN_IN0 Rmux edge, deactivatable
Rmux S&H RX1 low output voltage UVDDIO V
Rmux RX1 high output voltage UVDDIO V
GNDA Rmux Cs 0.4
Rmux TX1 low level -0.3 0.3 * V
Rmux UVDDIO
VDD5
Rmux TX1 high level 0.7 * UVDD5 + V
Rmux ADC (10 Bit; SAR) UVDDIO 0.3
Rin
AN_IN3
01 1011 0101

AREF
offset
channel
Cmax digital offset
GNDA compensation
Rmux

TT estm 3
R result register
DSon offset
TESTM3
reference
for compensation RAM
GNDA Bank0 Bank1

Control
INT ADC - SPI transfer
internal bus register (BIOR)

fCCLK SPI
(= 2.5MHz or 3MHz)

fcycle Divider 2 Divider 1

(2500, 3000, (1,2,3 or 4) 3
5000 or 6000) CLK
Small signal stags Parameter Min Max Unit
A1, A2 maximum voltage -0.6 60 V
A1, A2 nominal output current 50 mA
Two identical small-signal stages with open-drain A1, A2 regulated short circuit 50 120 mA
outputs are integrated in the CY100. The output stages current
A1, A2 on resistance 12
are mainly for digital outputs, for the control of semi-
Switching time E1 to A1, 2 s
intelligent actors (e.g. semi-conductor relays) and for E2 to A2
driving LEDs.
The OL diagnosis can be disabled individually via the SPI
The inputs E1 and E2 are realized as comparators with interface for each output stage for applications, for
VDDIO - dependent threshold. The inputs have pull-up which the diagnostic current can disturb (e.g. LEDs).
current sources, so that in case of an open input, the Disable means, zero diagnostic current for OL and
output stages are disabled. The phase of the outputs is deactivated error indication OL.
non-inverting.

The output stages are disabled (transistors switched SPI Interface

off), when the reset signal on RST is active.
The serial SPI interface establishes a communication link
between CY100 and the systems microcontroller. The
CY100 always operates in slave mode whereas the
VDDIO controller provides the master function. The maximum
SPI-Bits
baud rate is 2 MBaud.
diagnose

Ax Applying an active slave select signal at SS CY100 is

selected by the SPI master. SI is the slave in data input,
Ex & SO the slave out data output. Via the serial clock input
RST
SCK the SPI clock is provided by the SPI master. In case
of inactive slave select signal (high) or active reset the
data output SO is high impedance (tistate).

The first two bits of an instruction are used to realize an

The transmit-function has to be enabled via SPI soft extended device-addressing. This gives the opportunity
reset after an active RST (low). The open-drain outputs to operate up to 4 slave-devices sharing one common SS
are current-limited, in addition the output voltage on Ax signal from the master-unit.
(x=1; 2) is monitored for plausibility. If the voltage at Ax
still exceeds a certain defined threshold after switch on
the output transistor and after a predefined time tvoff, a
configuration status registers
short- circuit to battery is detected and the stage is reg. (read / write) (read only)

turned off.

The output stages can also be diagnosed. The error

conditions short-circuit to battery (SCB), short-circuit to
ground (SCG) and open-load (OL) are detected. Error
detection is done selectively according to the output SS
SPI Control:
stage condition: OL and SCG are detected when the SCK
State Machine
output stage is disabled; SCB is detected when the
SO
output stage is on. The errors OL, SCB and SCG are SI
SPI Shift Register

filtered.

ID registers ADC RAM

(read only) (read / write)

4
 System application example

Chipset

x Valves
Battery
CY320 CJ945
C x Relays
Sensor 18 Low Side
System Supply
e.g. Power Drivers
C Supply x
Infineon Inductivities
Sensor Sensor Supply
TC1796 6x 2A/70V
Watchdog x
Reset 6x 2A/45V Resistors
Sensor CAN Driver 2x 3A/45V
ISO Interface A/D 4x 1A/45V x
_

Lamps
+

CAN
Sleep/Wake RAM Fela

ISO CAN
Peripherals x
8 FLASH CK240
8x CY100 Ignition Drivers
e.g. 2 8x 10 Bit A/D 5V
_
+

LEDs Fela H-Bridge

Small Signal Out
ISO ISO Interface Concept
FLASH
CY30 CF173 CAN
RPM CAN Driver

CJ840 SMD085 CJ125

Direct Injection Pressure Sensor -Sensor Control

Contact

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