TAS5715

TAS5715
www.ti.com SLOS645 AUGUST 2010
25-W DIGITAL AUDIO POWER AMPLIFIER WITH EQ AND DRC

Check for Samples: TAS5715
1FEATURES
Audio Input/Output A
25-W Into an 8- Load From an 18-V Supply Benefits
50-W Support in PBTL Mode With 4- Load EQ: Speaker Equalization Improves Audio
Wide PVDD Range, From 8 V to 26 V Performance
Efficient Class-D Operation Eliminates DRC: Automatic Gain Limiter. Can Be Used
Need for Heatsinks As Power Limiter. Enables Speaker
Requires Only 3.3 V and PVDD Protection, Easy Listening
One Serial Audio Input (Two Audio Two-Band DRC: Set Two Different
Channels) Thresholds for Low- and High-Frequency
Content
I2C Address Selection via PIN (Chip Select)
Autobank Switching: Preload Coefficients
Supports 8-kHz to 48-kHz Sample Rate for Different Sample Rates. No Need to
(LJ/RJ/I2S) Write New Coefficients to the Part When
Headphone PWM Outputs Sample Rate Changes
Dedicated Pin for External Autodetect: Automatically Detects
Headphone-Amplifier Shutdown Sample-Rate Changes. No Need for
Single-Filter PBTL Support External Microprocessor Intervention
Audio/PWM Processing Single-Filter PBTL Support Reduces BOM
Independent Channel Volume Controls With Cost
24-dB to Mute Thgermal Dissipation, Improving System
Independent Headphone Volume Stability
Programmable Two-Band Dynamic Range
Control DESCRIPTION
Up to Eight User-Programmable Biquads The TAS5715 is a 25-W, efficient, digital audio-power
per Channel amplifier for driving stereo bridge-tied speakers. One
serial data input allows processing of up to two
Programmable Coefficients for DRC Filters discrete audio channels and seamless integration to
DC Blocking Filters and PWM DC Detect most digital audio processors and MPEG decoders.
CRC Checksum to Detect Biquad The device accepts a wide range of input data and
Coefficient Corruption data rates. A fully programmable data path routes
these channels to the internal speaker drivers.
General Features
Serial Control Interface Operational Without The TAS5715 is a slave-only device receiving all
clocks from external sources. The TAS5715 operates
MCLK
with a PWM carrier between a 384-kHz switching rate
Factory-Trimmed Internal Oscillator for and a 352-KHz switching rate, depending on the input
Automatic Rate Detection sample rate. Oversampling combined with a
Surface Mount, 48-Pin, 7-mm 7-mm fourth-order noise shaper provides a flat noise floor
HTQFP Package and excellent dynamic range from 20 Hz to 20 kHz.
Thermal and Short-Circuit Protection
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Copyright 2010, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
TAS5715
SLOS645 AUGUST 2010 www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
SIMPLIFIED APPLICATION DIAGRAM

3.3 V 8 V26 V
AVDD/DVDD AVCC/PVCC
OUT_A
LRCLK
Digital SCLK BST_A
Audio
Source MCLK LCBTL
BST_B
SDIN
OUT_B
2 SDA
I C OUT_C
Control SCL
BST_C
LCBTL
Control RESET BST_D
Inputs PDN
OUT_D
PLL_FLTP
Loop TPA6110A2
(1) (HP Amplifier)
Filter
PLL_FLTM
HPR_PWM
RC
Filter
HPL_PWM
A_SEL/HP_SD
B0264-12
(1)
See the TAS5715 User's Guide for loop-filter values.
2 Submit Documentation Feedback Copyright 2010, Texas Instruments Incorporated
Product Folder Link(s): TAS5715

TAS5715
FUNCTIONAL VIEW
OUT_A
2 HB
th FET Out
Serial 4 OUT_B
SDIN Audio S Order
Port Digital Audio Processor R Noise
(DAP) C Shaper
and OUT_C
PWM 2 HB
FET Out
OUT_D
Protection
Logic
MCLK Click and Pop

Sample Rate Control HPL
SCLK Autodetect Headphone
LRCLK and PLL Buffers
HPR
Microcontroller
SDA Serial Based
Control System
SCL Control
Terminal Control
B0262-09
Copyright 2010, Texas Instruments Incorporated Submit Documentation Feedback 3

TAS5715
FAULT
4
FAULT Under-
voltage 4
Protection
Power
On
Reset
Protection AGND
and
I/O Logic
Temp.
Sense GND
VALID
Overcurrent Isense
Protection
BST_D
PVDD_D
PWM_D PWM Gate
Ctrl Timing OUT_D
Rcv Drive
PWM Controller
Pulldown Resistor
GVDD PGND_CD
Regulator
GVDD_OUT
BST_C
PVDD_C
PWM_C PWM Gate
Ctrl Timing OUT_C
Rcv Drive
Pulldown Resistor
PGND_CD
BST_B
PVDD_B
PWM_B PWM Gate
Ctrl Timing OUT_B
Rcv Drive
Pulldown Resistor
GVDD PGND_AB
Regulator
BST_A
PVDD_A
PWM_A PWM Gate
Ctrl Timing OUT_A
Rcv Drive
Pulldown Resistor
PGND_AB
B0034-06
Figure 1. Power Stage Functional Block Diagram

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2
I C Subaddress in Red
DAP Process Structure
59 0x51[1]
L 0x70
1BQ +
0x72 + 7BQ Vol1
Copyright 2010, Texas Instruments Incorporated

+ +
0x290x2F
0x73 0x51[0]
1
DRC
0
Auto-lp
(0x46 Bit 5)
5D +
R 0x74 Vol2
1BQ
0x76 + 7BQ
+
0x300x36 0x52[1]
0x77
+
Vol
0x52[0]
+

2 2
I C:57 I C:56
DRC VDISTB VDISTA
+
Vol
Volc config reg 0x0E

B0321-07
Submit Documentation Feedback

SLOS645 AUGUST 2010
5
TAS5715
TAS5715
DEVICE INFORMATION
PIN ASSIGNMENT
PHP Package
(Top View)
PGND_CD
PGND_CD
PGND_AB
PGND_AB
PVDD_C
PVDD_C
PVDD_B
PVDD_B
OUT_C
OUT_B
BST_C
BST_B
48 47 46 45 44 43 42 41 40 39 38 37
OUT_A 1 36 OUT_D
PVDD_A 2 35 PVDD_D
PVDD_A 3 34 PVDD_D
BST_A 4 33 BST_D
HPR 5 32 GVDD_OUT
SSTIMER 6 31 VREG
TAS5715
HPL 7 30 AGND
PBTL 8 29 GND
AVSS 9 28 DVSS
PLL_FLTM 10 27 DVDD
PLL_FLTP 11 26 STEST
VR_ANA 12 25 RESET
13 14 15 16 17 18 19 20 21 22 23 24
LRCLK
MCLK
PDN
SCL
VR_DIG
SDIN
SDA
OSC_RES
DVSSO
AVDD
A_SEL
SCLK
P0075-10
PIN FUNCTIONS
PIN 5-V
TYPE (1) TERMINATION (2) DESCRIPTION
NAME NO. TOLERANT
AGND 30 P Analog ground for power stage
A_SEL 14 DIO This pin is monitored on the rising edge of RESET. A value of 0
makes the I2C dev address 0x54 and a value of 1 makes it 0x56.
This pin can be re-used after reset as external HP amplifer shutdown
signal.
AVDD 13 P 3.3-V analog power supply
AVSS 9 P Analog 3.3-V supply ground
BST_A 4 P High-side bootstrap supply for half-bridge A
BST_B 43 P High-side bootstrap supply for half-bridge B
BST_C 42 P High-side bootstrap supply for half-bridge C
BST_D 33 P High-side bootstrap supply for half-bridge D
DVDD 27 P 3.3-V digital power supply
DVSSO 17 P Oscillator ground
DVSS 28 P Digital ground
(1) TYPE: A = analog; D = 3.3-V digital; P = power/ground/decoupling; I = input; O = output

(2) All pullups are weak pullups and all pulldowns are weak pulldowns. The pullups and pulldowns are included to assure proper input logic
levels if the pins are left unconnected (pullups logic 1 input; pulldowns logic 0 input).

TAS5715
PIN FUNCTIONS (continued)

PIN 5-V
TYPE (1) TERMINATION (2) DESCRIPTION
NAME NO. TOLERANT
GND 29 P Analog ground for power stage
GVDD_OUT 32 P Gate drive internal regulator output
HPL 7 AO Headphone PWM out (HPL) (leave floating if unused)
HPR 5 AO Headphone PWM out (HPR) (leave floating if unused)
LRCLK 20 DI 5-V Pulldown Input serial audio data left/right clock (sample rate clock)
MCLK 15 DI 5-V Pulldown Master clock input
OSC_RES 16 AO Oscillator trim resistor. Connect an 18-k 1% resistor to DVSSO.
OUT_A 1 O Output, half-bridge A
OUT_B 46 O Output, half-bridge B
OUT_C 39 O Output, half-bridge C
OUT_D 36 O Output, half-bridge D
PBTL 8 DI Low means BTL or SE mode; high means PBTL mode. Information
goes directly to power stage.
PDN 19 DI 5-V Pullup Power down, active-low. PDN prepares the device for loss of power
supplies by shutting down the Noise Shaper and initiating PWM stop
sequence.
PGND_AB 47, 48 P Power ground for half-bridges A and B
PGND_CD 37, 38 P Power ground for half-bridges C and D
PLL_FLTM 10 AO PLL negative loop filter terminal
PLL_FLTP 11 AO PLL positive loop filter terminal
PVDD_A 2, 3 P Power supply input for half-bridge output A
PVDD_B 44, 45 P Power supply input for half-bridge output B
PVDD_C 40, 41 P Power supply input for half-bridge output C
PVDD_D 34, 35 P Power supply input for half-bridge output D
RESET 25 DI 5-V Pullup Reset, active-low. A system reset is generated by applying a logic
low to this pin. RESET is an asynchronous control signal that
restores the DAP to its default conditions, and places the PWM in
the hard mute state (tristated).
SCL 24 DI 5-V I2C serial control clock input
SCLK 21 DI 5-V Pulldown Serial audio data clock (shift clock). SCLK is the serial audio port
input data bit clock.
SDA 23 DIO 5-V I2C serial control data interface input/output
SDIN 22 DI 5-V Pulldown Serial audio data input. SDIN supports three discrete (stereo) data
formats.
SSTIMER 6 AI Controls ramp time of OUT_x to minimize pop. Leave this pin
floating for BD mode. Requires capacitor of 2.2 nF to GND in AD
mode. The capacitor determines the ramp time.
STEST 26 DI Factory test pin. Connect directly to DVSS.
VR_ANA 12 P Internally regulated 1.8-V analog supply voltage. This pin must not
be used to power external devices.
VR_DIG 18 P Internally regulated 1.8-V digital supply voltage. This pin must not be
used to power external devices.
VREG 31 P Digital regulator output. Not to be used for powering external
circuitry.

TAS5715
ABSOLUTE MAXIMUM RATINGS

(1)
over operating free-air temperature range (unless otherwise noted)
VALUE UNIT
DVDD, AVDD 0.3 to 3.6 V
Supply voltage
PVDD_x 0.3 to 30 V
3.3-V digital input 0.5 to DVDD + 0.5 V
Input voltage 5-V tolerant (2) digital input (except MCLK) 0.5 to DVDD + 2.5 (3) V
(3)
5-V tolerant MCLK input 0.5 to AVDD + 2.5 V
OUT_x to PGND_x 32 (4) V
BST_x to PGND_x 43 (4) V
Input clamp current, IIK 20 mA
Output clamp current, IOK 20 mA
Operating free-air temperature 0 to 85 C
Operating junction temperature range 0 to 150 C
Storage temperature range, Tstg 40 to 125 C
(1) Stresses beyond those listed under absolute ratings may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under recommended operation conditions are
not implied. Exposure to absolute-maximum conditions for extended periods may affect device reliability.
(2) 5-V tolerant inputs are PDN, RESET, SCLK, LRCLK, MCLK, SDIN, SDA, and SCL.
(3) Maximum pin voltage should not exceed 6.0V
(4) DC voltage + peak ac waveform measured at the pin should be below the allowed limit for all conditions.
DISSIPATION RATINGS (1)

DERATING FACTOR TA 25C TA = 45C TA = 70C
PACKAGE
ABOVE TA = 25C POWER RATING POWER RATING POWER RATING
7-mm 7-mm HTQFP 20 mW/C 2W 1.6 W 1.1 W
(1) This data was taken using 1 oz trace and copper pad that is soldered directly to a JEDEC standard high-k PCB. The thermal pad must
be soldered to a thermal land on the printed-circuit board. See TI Technical Briefs SLMA002 for more information about using the
HTQFP thermal pad
RECOMMENDED OPERATING CONDITIONS

MIN NOM MAX UNIT
Digital/analog supply voltage DVDD, AVDD 3 3.3 3.6 V
Half-bridge supply voltage PVDD_x 8 26 V
VIH High-level input voltage 5-V tolerant 2 V
VIL Low-level input voltage 5-V tolerant 0.8 V
TA Operating ambient temperature range 0 85 C
(1)
TJ Operating junction temperature range 0 125 C
RL (BTL) Load impedance Output filter: L = 15 mH, C = 680 nF. 4 8
Minimum output inductance under 10
LO (BTL) Output-filter inductance mH
short-circuit condition
(1) Continuous operation above the recommended junction temperature may result in reduced reliability and/or lifetime of the device.
PWM OPERATION AT RECOMMENDED OPERATING CONDITIONS

PARAMETER TEST CONDITIONS VALUE UNIT
11.025/22.05/44.1-kHz data rate 1% 352.8 kHz
Output sample rate
48/24/12/8/16/32-kHz data rate 1% 384

TAS5715
PLL INPUT PARAMETERS AND EXTERNAL FILTER COMPONENTS

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
fMCLKI MCLK Frequency 2.8224 12.288 MHz
MCLK duty cycle 40% 50% 60%
tr /
Rise/fall time for MCLK 5 ns
tf(MCLK)
LRCLK allowable drift before LRCLK reset 4 MCLKs
External PLL filter capacitor C1 SMD 0603 Y5V 47 nF
External PLL filter capacitor C2 SMD 0603 Y5V 4.7 nF
External PLL filter resistor R SMD 0603, metal film 470
ELECTRICAL CHARACTERISTICS
DC Characteristics
TA = 25, PVCC_x = 18 V, DVDD = AVDD = 3.3 V, RL= 8 , BTL AD Mode, fS = 48 KHz (unless otherwise noted)
IOH = 4 mA
VOH High-level output voltage A_SEL and SDA 2.4 V
DVDD = 3 V
IOL = 4 mA
VOL Low-level output voltage A_SEL and SDA 0.5 V
DVDD = 3 V
VI < VIL ; DVDD = AVDD
IIL Low-level input current 75 mA
= 3.6V
VI > VIH ; DVDD =
IIH High-level input current 75 (1) mA
AVDD = 3.6V
Normal mode 56 85
3.3 V supply voltage (DVDD,
IDD 3.3 V supply current Reset (RESET = low, 26 40 mA
AVDD)
PDN = high)
Normal mode 40 85
IPVDD Supply current No load (PVDD_x) Reset (RESET = low, 5 13 mA
PDN = high)
Drain-to-source resistance, LS TJ = 25C, includes metallization resistance 110
(2)
rDS(on) Drain-to-source resistance, m
TJ = 25C, includes metallization resistance 110
HS
I/O Protection
Vuvp Undervoltage protection limit PVDD falling 7.2 V
Vuvp,hyst Undervoltage protection limit PVDD rising 7.6 V
OTE (3) Overtemperature error 150 C
(3) Extra temperature drop
OTEHYST 30 C
required to recover from error
OLPC Overload protection counter fPWM = 384 kHz 0.63 ms
IOC Overcurrent limit protection 4.5 A
IOCT Overcurrent response time 150 ns
Internal pulldown resistor at Connected when drivers are tristated to provide bootstrap
RPD 3 k
the output of each half-bridge capacitor charge.
(1) IIH for the PBTL pin has a maximum limit of 200 A due to an internal pulldown on the pin.
(2) This does not include bond-wire or pin resistance.
(3) Specified by design

TAS5715
AC Characteristics (BTL, PBTL)

PVDD_x = 18 V, BTL AD mode, fS = 48 KHz, RL = 8 , ROCP = 22 K, CBST = 33 nF, audio frequency = 1 kHz, AES17 filter,
fPWM = 384 kHz, TA = 25C (unless otherwise specified). All performance is in accordance with recommended operating
conditions (unless otherwise specified).
PVDD = 18 V, 10% THD, 1-kHz input signal 21.5
PVDD = 8 V, 7% THD, 1-kHz input signal 4
PO Power output per channel PBTL mode, PVDD = 12 V, RL = 4 , W
18.7
10% THD, 1-kHz input signal
PBTL mode, PVDD = 12 V, RL = 4 ,
17.7
41.5
39
PVDD = 18 V, PO = 1 W 0.07%
THD+N Total harmonic distortion + noise PVDD = 12 V, PO = 1 W 0.03%
PVDD = 8 V, PO = 1 W 0.1%
Vn Output integrated noise (rms) A-weighted 56 mV
PO = 0.25 W, f = 1 kHz (BD Mode) 82 dB
Crosstalk
PO = 0.25 W, f = 1 kHz (AD Mode) 69 dB
(1) A-weighted, f = 1 kHz, maximum power at
SNR Signal-to-noise ratio 106 dB
THD < 1%
(1) SNR is calculated relative to 0-dBFS input level.

TAS5715
SERIAL AUDIO PORTS SLAVE MODE

over recommended operating conditions (unless otherwise noted)
TEST
PARAMETER MIN TYP MAX UNIT
CONDITIONS
fSCLKIN Frequency, SCLK 32 fS, 48 fS, 64 fS CL = 30 pF 1.024 3.072 MHz
tsu1 Setup time, LRCLK to SCLK rising edge 10 ns
th1 Hold time, LRCLK from SCLK rising edge 10 ns
tsu2 Setup time, SDIN to SCLK rising edge 10 ns
th2 Hold time, SDIN from SCLK rising edge 10 ns
LRCLK frequency 8 48 48 kHz
SCLK duty cycle 40% 50% 60%
LRCLK duty cycle 40% 50% 60%
SCLK
SCLK rising edges between LRCLK rising edges 32 64
edges
t(edge) SCLK
LRCLK clock edge with respect to the falling edge of SCLK 1/4 1/4
period
tr/tf Rise/fall time for SCLK/LRCLK 8 ns
tr tf
SCLK
(Input)
t(edge)
th1
tsu1
LRCLK
(Input)
th2
tsu2
SDIN
T0026-04
Figure 2. Slave Mode Serial Data Interface Timing

TAS5715
I2C SERIAL CONTROL PORT OPERATION

Timing characteristics for I2C Interface signals over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN MAX UNIT
fSCL Frequency, SCL No wait states 400 kHz
tw(H) Pulse duration, SCL high 0.6 ms
tw(L) Pulse duration, SCL low 1.3 ms
tr Rise time, SCL and SDA 300 ns
tf Fall time, SCL and SDA 300 ns
tsu1 Setup time, SDA to SCL 100 ns
th1 Hold time, SCL to SDA 0 ns
t(buf) Bus free time between stop and start condition 1.3 ms
tsu2 Setup time, SCL to start condition 0.6 ms
th2 Hold time, start condition to SCL 0.6 ms
tsu3 Setup time, SCL to stop condition 0.6 ms
CL Load capacitance for each bus line 400 pF
tw(H) tw(L) tr tf
SCL
tsu1 th1
SDA
T0027-01
Figure 3. SCL and SDA Timing
SCL
th2 t(buf)
tsu2 tsu3
SDA
Start Stop
Condition Condition
T0028-01
Figure 4. Start and Stop Conditions Timing

TAS5715
RESET TIMING (RESET)

Control signal parameters over recommended operating conditions (unless otherwise noted). Please refer to Recommended
Use Model section on usage of all terminals.
PARAMETER MIN TYP MAX UNIT
tw(RESET) Pulse duration, RESET active 100 ms
2
td(I2C_ready) Time to enable I C 12.0 ms
RESET
tw(RESET)
2 2
I C Active I C Active
td(I2C_ready)
System Initialization.
2
Enable via I C.
T0421-01
NOTES: On power up, it is recommended that the TAS5715 RESET be held LOW for at least 100 ms after DVDD has
reached 3 V.
If RESET is asserted LOW while PDN is LOW, then the RESET must continue to be held LOW for at least 100 ms
after PDN is deasserted (HIGH).
Figure 5. Reset Timing

TAS5715
TYPICAL CHARACTERISTICS, BTL CONFIGURATION, 8

TOTAL HARMONIC DISTORTION + NOISE TOTAL HARMONIC DISTORTION + NOISE
vs vs
FREQUENCY FREQUENCY
10 10
PVDD = 8V PVDD = 12V
RL = 8 RL = 8
T A = 25C T A = 25C
1 1 PO = 5W
PO = 2.5W
PO = 2.5W
THD+N (%)
THD+N (%)
0.1 0.1
PO = 0.5W
PO = 1W
PO = 1W
0.01 0.01
0.001 0.001
20 100 1k 10k 20k 20 100 1k 10k 20k
Frequency (Hz) G001
Frequency (Hz) G002
Figure 6. Figure 7.

vs vs
FREQUENCY FREQUENCY
10 10
RL = 8 RL = 8
T A = 25C T A = 25C
1 1
PO = 5W
PO = 5W
PO = 1W
THD+N (%)
THD+N (%)
0.1 0.1
PO = 1W PO = 2.5W PO = 2.5W
0.01 0.01
0.001 0.001
20 100 1k 10k 20k 20 100 1k 10k 20k
Frequency (Hz) G003
Frequency (Hz) G004
Figure 8. Figure 9.

TAS5715
TYPICAL CHARACTERISTICS, BTL CONFIGURATION, 8 (continued)

vs vs
OUTPUT POWER OUTPUT POWER
10 10
RL = 8 RL = 8
T A = 25C T A = 25C
1 1
f = 20Hz
f = 1kHz
THD+N (%)
THD+N (%)
0.1 0.1
f = 1kHz f = 20Hz
0.01 0.01
f = 10kHz
f = 10kHz
0.001 0.001
0.01 0.1 1 10 40 0.01 0.1 1 10 40
Output Power (W) G005
Figure 10. Figure 11.

vs vs
10 10
RL = 8 RL = 8
T A = 25C T A = 25C
1 1
f = 20Hz
f = 1kHz
f = 1kHz
THD+N (%)
THD+N (%)
f = 20Hz
0.1 0.1
0.01 0.01
f = 10kHz
f = 10kHz
0.001 0.001
0.01 0.1 1 10 40 0.01 0.1 1 10 40

TAS5715

OUTPUT POWER EFFICIENCY
vs vs
SUPPLY VOLTAGE TOTAL OUTPUT POWER
40 100
RL = 8
T A = 25C 90
35
80
30 PVDD = 24V
70
PVDD = 18V
Output Power (W)
25
60
Efficiency (%)
THD+N = 10%
PVDD = 12V
20 50
PVDD = 8V
40
15
30
THD+N = 1%
10
20
5 RL = 8
10
T A = 25C
0 0
8 10 12 14 16 18 20 22 24 26 0 5 10 15 20 25 30 35 40
Supply Voltage (V) G009
Total Output Power (W) G010
NOTE: Dashed lines represent thermally limited region. NOTE: Dashed lines represent thermally limited region.
CROSSTALK CROSSTALK
vs vs
FREQUENCY FREQUENCY
0 0
PO = 1W PO = 1W
-10 PVDD = 8V -10 PVDD = 12V
RL = 8 RL = 8
-20 T A = 25C -20 T A = 25C
-30 -30
Crosstalk (dB)
Crosstalk (dB)
-40 -40
-50 -50
-60 -60
Right to Left
-70 -70
Left to Right
-80 -80
Left to Right
-90 -90
Right to Left
-100 -100
20 100 1k 10k 20k 20 100 1k 10k 20k
Frequency (Hz) G011
Frequency (Hz) G012

TAS5715

CROSSTALK CROSSTALK
vs vs
FREQUENCY FREQUENCY
0 0
PO = 1W PO = 1W
-10 PVDD = 18V -10 PVDD = 24V
RL = 8 RL = 8
-20 T A = 25C -20 T A = 25C
-30 -30
Crosstalk (dB)
Crosstalk (dB)
-40 -40
-50 -50
-60 -60
Right to Left
-70 Right to Left -70
-80 -80
-90 -90
Left to Right Left to Right
-100 -100
20 100 1k 10k 20k 20 100 1k 10k 20k
Frequency (Hz) G013
Frequency (Hz) G014

TAS5715
TYPICAL CHARACTERISTICS, BTL CONFIGURATION, 4

vs vs
FREQUENCY FREQUENCY
10 10
RL = 4 RL = 4
T A = 25C T A = 25C
PO = 5W
1 1
PO = 2.5W
PO = 5W
THD+N (%)
THD+N (%)
0.1 0.1
PO = 1W PO = 1W
0.01 0.01
PO = 2.5W
0.001 0.001
20 100 1k 10k 20k 20 100 1k 10k 20k
Frequency (Hz) G021
Frequency (Hz) G022

vs vs
10 10
RL = 4 RL = 4
T A = 25C T A = 25C
1 1
f = 1kHz
f = 1kHz
THD+N (%)
THD+N (%)
0.1 0.1
f = 20Hz
0.01 0.01
f = 10kHz f = 10kHz
f = 20Hz
0.001 0.001
0.01 0.1 1 10 40 0.01 0.1 1 10 50

TAS5715

CROSSTALK CROSSTALK
vs vs
FREQUENCY FREQUENCY
0 0
PO = 1W PO = 1W
-10 PVDD = 12V -10 PVDD = 18V
RL = 4 RL = 4
-20 T A = 25C -20 T A = 25C
-30 -30
-40 -40
Crosstalk (dB)
Crosstalk (dB)
-50 -50
-60 -60
Right to Left
Right to Left
-70 -70
-80 -80
Left to Right
-90 -90 Left to Right
-100 -100
-110 -110
20 100 1k 10k 20k 20 100 1k 10k 20k
Frequency (Hz) G023
Frequency (Hz) G024

TAS5715
TYPICAL CHARACTERISTICS, PBTL CONFIGURATION, 4

vs vs
FREQUENCY FREQUENCY
10 10
RL = 4 RL = 4
T A = 25C T A = 25C
1 1
PO = 2.5W
PO = 5W
PO = 5W
PO = 2.5W
THD+N (%)
THD+N (%)
0.1 0.1
PO = 1W
0.01 0.01 PO = 1W
0.001 0.001
20 100 1k 10k 20k 20 100 1k 10k 20k
Frequency (Hz) G015
Frequency (Hz) G016

vs vs
10 10
RL = 4 RL = 4
T A = 25C T A = 25C
1 1
f = 1kHz
f = 20Hz
THD+N (%)
THD+N (%)
f = 20Hz
0.1 0.1
f = 1kHz
0.01 0.01
f = 10kHz f = 10kHz
0.001 0.001
0.01 0.1 1 10 50 0.01 0.1 1 10 40

TAS5715
TYPICAL CHARACTERISTICS, PBTL CONFIGURATION, 4 (continued)

OUTPUT POWER EFFICIENCY
vs vs
SUPPLY VOLTAGE TOTAL OUTPUT POWER
60 100
RL = 4
T A = 25C 90
50
80
THD+N = 10% PVDD = 24V
70
40 PVDD = 12V
Output Power (W)
60
Efficiency (%)
30 50
THD+N = 1% 40
20
30
20
10
10 RL = 4
T A = 25C
0 0
8 10 12 14 16 18 20 22 24 26 0 10 20 30 40 50 60
Supply Voltage (V) G019
Total Output Power (W) G020
NOTE: Dashed lines represent thermally limited region. NOTE: Dashed line represents thermally limited region.

TAS5715
DETAILED DESCRIPTION
POWER SUPPLY
To facilitate system design, the TAS5715 needs only a 3.3-V supply in addition to the (typical) 18-V power-stage
supply. An internal voltage regulator provides suitable voltage levels for the gate drive circuitry. Additionally, all
circuitry requiring a floating voltage supply, e.g., the high-side gate drive, is accommodated by built-in bootstrap
circuitry requiring only a few external capacitors.
In order to provide good electrical and acoustical characteristics, the PWM signal path for the output stage is
designed as identical, independent half-bridges. For this reason, each half-bridge has separate bootstrap pins
(BST_x) and power-stage supply pins (PVDD_x). The gate drive voltages (GVDD_AB and GVDD_CD) are
derived from the PVDD voltage. Special attention should be paid to placing all decoupling capacitors as close to
their associated pins as possible. In general, inductance between the power-supply pins and decoupling
capacitors must be avoided.
For a properly functioning bootstrap circuit, a small ceramic capacitor must be connected from each bootstrap pin
(BST_x) to the power-stage output pin (OUT_x). When the power-stage output is low, the bootstrap capacitor is
charged through an internal diode connected between the gate-drive regulator output pin (GVDD_x) and the
bootstrap pin. When the power-stage output is high, the bootstrap capacitor potential is shifted above the output
potential and thus provides a suitable voltage supply for the high-side gate driver. In an application with PWM
switching frequencies in the range from 352 kHz to 384 kHz, it is recommended to use 33-nF ceramic capacitors,
size 0603 or 0805, for the bootstrap supply. These 33-nF capacitors ensure sufficient energy storage, even
during minimal PWM duty cycles, to keep the high-side power stage FET (LDMOS) fully turned on during the
remaining part of the PWM cycle.
Special attention should be paid to the power-stage power supply; this includes component selection, PCB
placement, and routing. As indicated, each half-bridge has independent power-stage supply pins (PVDD_x). For
optimal electrical performance, EMI compliance, and system reliability, it is important that each PVDD_x pin is
decoupled with a 100-nF ceramic capacitor placed as close as possible to each supply pin.
The TAS5715 is fully protected against erroneous power-stage turnon due to parasitic gate charging.
I2C CHIP SELECT/HP_SHUTDOWN

A_SEL/HP_SD is an input pin during power up. It can be pulled high or low. HIGH indicates an I2C subaddress
of 0x56, and LOW a subaddress of 0x54.
When used in headphone mode, this pin can be re-assigned as an output after reset during the initialization
sequence. Then this pin functions as headphone shutdown (active-high shutdown). A device with a headphone
should use an external pulldown, so the address is 0x54.
SINGLE-FILTER PBTL MODE

The TAS5715 supports parallel BTL (PBTL) mode with OUT_A/OUT_B (and OUT_C/OUT_D) connected before
the LC filter. In order to put the part in PBTL configuration, drive PBTL (pin 8) HIGH. This synchronizes the
turnoff of half-bridges A and B (and similarly C/D) if an overcurrent condition is detected in either half-bridge.
There is a pulldown resistor on the PBTL pin that configures the part in BTL mode if the pin is left floating.
PWM output multiplexers should be updated to set the device in PBTL mode. Output Mux Register (0x25) should
be written with a value of 0x01 10 32 45. Also, the PWM shutdown register (0x19) should be written with a value
of 0x3A.
DEVICE PROTECTION SYSTEM
Overcurrent (OC) Protection With Current Limiting

The device has independent, fast-reacting current detectors on all high-side and low-side power-stage FETs. The
detector outputs are closely monitored by two protection systems. The first protection system controls the power
stage in order to prevent the output current further increasing, i.e., it performs a cycle-by-cycle current-limiting
function, rather than prematurely shutting down during combinations of high-level music transients and extreme
speaker load impedance drops. If the high-current condition situation persists, i.e., the power stage is being

TAS5715
overloaded, a second protection system triggers a latching shutdown, resulting in the power stage being set in
the high-impedance (Hi-Z) state. The device returns to normal operation once the fault condition (i.e., a short
circuit on the output) is removed. Current limiting and overcurrent protection are not independent for half-bridges.
That is, if the bridge-tied load between half-bridges A and B causes an overcurrent fault, half-bridges A, B, C,
and D are shut down.
Overtemperature Protection
The TAS5715 has an overtemperature-protection system. If the device junction temperature exceeds 150C
(nominal), the device is put into thermal shutdown, resulting in all half-bridge outputs being set in the
high-impedance (Hi-Z) state and FAULT being asserted low. The TAS5715 recovers automatically once the
temperature drops approximately 30.
Undervoltage Protection (UVP) and Power-On Reset (POR)

The UVP and POR circuits of the TAS5715 fully protect the device in any power-up/down and brownout situation.
While powering up, the POR circuit resets the overload circuit (OLP) and ensures that all circuits are fully
operational when the PVDD and AVDD supply voltages reach 7.6 V and 2.7 V, respectively. Although PVDD and
AVDD are independently monitored, a supply voltage drop below the UVP threshold on AVDD or on either PVDD
pin results in all half-bridge outputs immediately being set in the high-impedance (Hi-Z) state and FAULT being
asserted low.
SSTIMER FUNCTIONALITY
SSTIMER is used to reduced turnon pop. This is used only in AD mode. The SSTIMER pin uses a capacitor
connected between this pin and ground to control the output duty cycle when exiting all-channel shutdown. The
capacitor on the SSTIMER pin is slowly charged through an internal current source, and the charge time
determines the rate at which the output transitions from a near-zero duty cycle to the desired duty cycle. This
allows for a smooth transition that minimizes audible pops and clicks. When the part is shut down, the drivers are
high-impedance and transition slowly down through a 3-k resistor, similarly minimizing pops and clicks. The
shutdown transition time is independent of the SSTIMER pin capacitance. Larger capacitors increase the start-up
time, whereas capacitors smaller than 2.2 nF decrease the start-up time. The SSTIMER pin should be left
floating for BD modulation.
CLOCK, AUTO DETECTION, AND PLL

The TAS5715 is a slave device. It accepts MCLK, SCLK, and LRCLK. The digital audio processor (DAP)
supports all the sample rates and MCLK rates that are defined in the clock control register .
The TAS5715 checks to verify that SCLK is a specific value of 32 fS, 48 fS, or 64 fS. The DAP only supports a 1
fS LRCLK. The timing relationship of these clocks to SDIN is shown in subsequent sections. The clock section
uses MCLK or the internal oscillator clock (when MCLK is unstable, out of range, or absent) to produce the
internal clock (DCLK) running at 512 times the PWM switching frequency.
The DAP can autodetect and set the internal clock-control logic to the appropriate settings for all supported clock
rates as defined in the clock control register.
TAS5715 has robust clock error handling that uses the bulit-in trimmed oscillator clock to quickly detect
changes/errors. Once the system detects a clock change/error, it mutes the audio (through a single-step mute)
and then forces PLL to limp using the internal oscillator as a reference clock. Once the clocks are stable, the
system autodetects the new rate and reverts to normal operation. During this process, the default volume is
restored in a single step (also called hard unmute). The ramp process can be programmed to ramp back slowly
(also called soft unmute) as defined in volume register (0x0E).
SERIAL DATA INTERFACE

Serial data is input on SDIN. The PWM outputs are derived from SDIN. The TAS5715 DAP accepts serial data in
16-, 20-, or 24-bit left-justified, right-justified, or I2S serial data format.

TAS5715
PWM Section
The TAS5715 DAP device uses noise-shaping and sophisticated nonlinear correction algorithms to achieve high
power efficiency and high-performance digital audio reproduction. The DAP uses a fourth-order noise shaper to
increase dynamic range and SNR in the audio band. The PWM section accepts 24-bit PCM data from the DAP
and outputs two BTL PWM audio output channels.
The PWM section has individual-channel dc-blocking filters that can be enabled and disabled. The filter cutoff
frequency is less than 1 Hz. Individual-channel de-emphasis filters for 44.1- and 48-kHz are included and can be
enabled and disabled.
Finally, the PWM section has an adjustable maximum modulation limit of 93.8% to 99.2%.
For detailed description of using audio processing features like DRC, EQ, 3D, and bass boost, see the User's
Guide and TAS570X GDE software development tool documentation. Also see the GDE software development
tool for the device data path.
I2C COMPATIBLE SERIAL CONTROL INTERFACE

The TAS5715 DAP has an I2C serial control slave interface to receive commands from a system controller. The
serial control interface supports both normal-speed (100-kHz) and high-speed (400-kHz) operations without wait
states. As an added feature, this interface operates even if MCLK is absent.
The serial control interface supports both single-byte and multiple-byte read and write operations for status
registers and the general control registers associated with the PWM.
SERIAL INTERFACE CONTROL AND TIMING
I2S Timing
I2S timing uses LRCLK to define when the data being transmitted is for the left channel and when it is for the
right channel. LRCLK is low for the left channel and high for the right channel. A bit clock running at 32, 48, or
64 fS is used to clock in the data. There is a delay of one bit clock from the time the LRCLK signal changes
state to the first bit of data on the data lines. The data is written MSB-first and is valid on the rising edge of bit
clock. The DAP masks unused trailing data-bit positions.

TAS5715
2
2-Channel I S (Philips Format) Stereo Input
32 Clks 32 Clks
LRCLK (Note Reversed Phase) Left Channel Right Channel
SCLK SCLK
MSB LSB MSB LSB

24-Bit Mode
23 22 9 8 5 4 1 0 23 22 9 8 5 4 1 0
20-Bit Mode
19 18 5 4 1 0 19 18 5 4 1 0
16-Bit Mode
15 14 1 0 15 14 1 0
T0034-01
NOTE: All data presented in 2s-complement form with MSB first.
Figure 32. I2S 64-fS Format
2
2-Channel I S (Philips Format) Stereo Input/Output (24-Bit Transfer Word Size)
24 Clks 24 Clks
LRCLK Left Channel Right Channel
SCLK SCLK
MSB LSB MSB LSB

24-Bit Mode
23 22 17 16 9 8 5 4 3 2 1 0 23 22 17 16 9 8 5 4 3 2 1
20-Bit Mode
19 18 13 12 5 4 1 0 19 18 13 12 5 4 1 0
16-Bit Mode
15 14 9 8 1 0 15 14 9 8 1 0
T0092-01

TAS5715
2
2-Channel I S (Philips Format) Stereo Input
16 Clks 16 Clks
LRCLK Left Channel Right Channel
SCLK SCLK
MSB LSB MSB LSB

16-Bit Mode
15 14 13 12 11 10 9 8 5 4 3 2 1 0 15 14 13 12 11 10 9 8 5 4 3 2 1
T0266-01
Left-Justified
Left-justified (LJ) timing uses LRCLK to define when the data being transmitted is for the left channel and when it
is for the right channel. LRCLK is high for the left channel and low for the right channel. A bit clock running at 32,
48, or 64 fS is used to clock in the data. The first bit of data appears on the data lines at the same time LRCLK
toggles. The data is written MSB-first and is valid on the rising edge of the bit clock. The DAP masks unused
trailing data-bit positions.
2-Channel Left-Justified Stereo Input
32 Clks 32 Clks
LRCLK
Left Channel Right Channel
SCLK SCLK
MSB LSB MSB LSB

24-Bit Mode
23 22 9 8 5 4 1 0 23 22 9 8 5 4 1 0
20-Bit Mode
19 18 5 4 1 0 19 18 5 4 1 0
16-Bit Mode
15 14 1 0 15 14 1 0
T0034-02
Figure 35. Left-Justified 64-fS Format

TAS5715
2-Channel Left-Justified Stereo Input (24-Bit Transfer Word Size)
24 Clks 24 Clks
LRCLK
SCLK SCLK
MSB LSB MSB LSB

24-Bit Mode
23 22 21 17 16 9 8 5 4 1 0 23 22 21 17 16 9 8 5 4 1 0
20-Bit Mode
19 18 17 13 12 5 4 1 0 19 18 17 13 12 5 4 1 0
16-Bit Mode
15 14 13 9 8 1 0 15 14 13 9 8 1 0
T0092-02
2-Channel Left-Justified Stereo Input
16 Clks 16 Clks
LRCLK
SCLK SCLK
MSB LSB MSB LSB

16-Bit Mode
15 14 13 12 11 10 9 8 5 4 3 2 1 0 15 14 13 12 11 10 9 8 5 4 3 2 1 0
T0266-02
Right-Justified
Right-justified (RJ) timing uses LRCLK to define when the data being transmitted is for the left channel and when

TAS5715
it is for the right channel. LRCLK is high for the left channel and low for the right channel. A bit clock running at
32, 48, or 64 fS is used to clock in the data. The first bit of data appears on the data 8 bit-clock periods (for
24-bit data) after LRCLK toggles. In RJ mode the LSB of data is always clocked by the last bit clock before
LRCLK transitions. The data is written MSB-first and is valid on the rising edge of bit clock. The DAP masks
unused leading data-bit positions.
2-Channel Right-Justified (Sony Format) Stereo Input
32 Clks 32 Clks
LRCLK
SCLK SCLK
MSB LSB MSB LSB

24-Bit Mode
23 22 19 18 15 14 1 0 23 22 19 18 15 14 1 0
20-Bit Mode
19 18 15 14 1 0 19 18 15 14 1 0
16-Bit Mode
15 14 1 0 15 14 1 0
T0034-03
Figure 38. Right-Justified 64-fS Format

TAS5715
2-Channel Right-Justified Stereo Input (24-Bit Transfer Word Size)
24 Clks 24 Clks
LRCLK
SCLK SCLK
MSB LSB MSB LSB

24-Bit Mode
23 22 19 18 15 14 6 5 2 1 0 23 22 19 18 15 14 6 5 2 1 0
20-Bit Mode
19 18 15 14 6 5 2 1 0 19 18 15 14 6 5 2 1 0
16-Bit Mode
15 14 6 5 2 1 0 15 14 6 5 2 1 0
T0092-03

TAS5715
I2C SERIAL CONTROL INTERFACE
The TAS5715 DAP has a bidirectional I2C interface that is compatible with the Inter IC (I2C) bus protocol and
supports both 100-kHz and 400-kHz data transfer rates for single- and multiple-yte write and read operations.
This is a slave-only device that does not support a multimaster bus environment or wait-state insertion. The
control interface is used to program the registers of the device and to read device status.
The DAP supports the standard-mode I2C bus operation (100 kHz maximum) and the fast I2C bus operation
(400 kHz maximum). The DAP performs all I2C operations without I2C wait cycles.
General I2C Operation

The I2C bus employs two signals; SDA (data) and SCL (clock), to communicate between integrated circuits in a
system. Data is transferred on the bus serially, one bit at a time. The address and data can be transferred in byte
(8-bit) format, with the most significant bit (MSB) transferred first. In addition, each byte transferred on the bus is
acknowledged by the receiving device with an acknowledge bit. Each transfer operation begins with the master
device driving a start condition on the bus and ends with the master device driving a stop condition on the bus.
The bus uses transitions on the data pin (SDA) while the clock is high to indicate start and stop conditions. A
high-to-low transition on SDA indicates a start and a low-to-high transition indicates a stop. Normal data-bit
transitions must occur within the low time of the clock period. These conditions are shown in Figure 41. The
master generates the 7-bit slave address and the read/write (R/W) bit to open communication with another
device and then waits for an acknowledge condition. The TAS5715 holds SDA low during the acknowledge clock
period to indicate an acknowledgment. When this occurs, the master transmits the next byte of the sequence.
Each device is addressed by a unique 7-bit slave address plus R/W bit (1 byte). All compatible devices share the
same signals via a bidirectional bus using a wired-AND connection. An external pullup resistor must be used for
the SDA and SCL signals to set the high level for the bus.
R/ 8-Bit Register Data For 8-Bit Register Data For

SDA 7-Bit Slave Address A 8-Bit Register Address (N) A A A
W Address (N) Address (N)
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
SCL
Start Stop
T0035-01
Figure 41. Typical I2C Sequence
There is no limit on the number of bytes that can be transmitted between start and stop conditions. When the last
word transfers, the master generates a stop condition to release the bus. A generic data transfer sequence is
shown in Figure 41.
The 7-bit address for TAS5715 is 0101 010 (0x54) or 0101 011 (0x56) defined by A_SEL (external pulldown for
0x54 and pullup for 0x56).Stero device with Headphone should use 0x54 as its device address.
Single- and Multiple-Byte Transfers

The serial control interface supports both single-byte and multiple-byte read/write operations for subaddresses
0x00 to 0x1F. However, for the subaddresses 0x20 to 0xFF, the serial control interface supports only
multiple-byte read/write operations (in multiples of 4 bytes).
During multiple-byte read operations, the DAP responds with data, a byte at a time, starting at the subaddress
assigned, as long as the master device continues to respond with acknowledges. If a particular subaddress does
not contain 32 bits, the unused bits are read as logic 0.
During multiple-byte write operations, the DAP compares the number of bytes transmitted to the number of bytes
that are required for each specific subaddress. For example, if a write command is received for a biquad
subaddress, the DAP expects to receive five 32-bit words. If fewer than five 32-bit data words have been
received when a stop command (or another start command) is received, the data received is discarded.

TAS5715
Supplying a subaddress for each subaddress transaction is referred to as random I2C addressing. The TAS5715
also supports sequential I2C addressing. For write transactions, if a subaddress is issued followed by data for
that subaddress and the 15 subaddresses that follow, a sequential I2C write transaction has taken place, and the
data for all 16 subaddresses is successfully received by the TAS5715. For I2C sequential write transactions, the
subaddress then serves as the start address, and the amount of data subsequently transmitted, before a stop or
start is transmitted, determines how many subaddresses are written. As was true for random addressing,
sequential addressing requires that a complete set of data be transmitted. If only a partial set of data is written to
the last subaddress, the data for the last subaddress is discarded. However, all other data written is accepted;
only the incomplete data is discarded.
Single-Byte Write
As shown in Figure 42, a single-byte data-write transfer begins with the master device transmitting a start
condition followed by the I2C device address and the read/write bit. The read/write bit determines the direction of
the data transfer. For a data-write transfer, the read/write bit is 0. After receiving the correct I2C device address
and the read/write bit, the DAP responds with an acknowledge bit. Next, the master transmits the address byte or
bytes corresponding to the TAS5715 internal memory address being accessed. After receiving the address byte,
the TAS5715 again responds with an acknowledge bit. Next, the master device transmits the data byte to be
written to the memory address being accessed. After receiving the data byte, the TAS5715 again responds with
an acknowledge bit. Finally, the master device transmits a stop condition to complete the single-byte data-write
transfer.
Start
Condition Acknowledge Acknowledge Acknowledge
A6 A5 A4 A3 A2 A1 A0 R/W ACK A7 A6 A5 A4 A3 A2 A1 A0 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK
2 Stop
I C Device Address and Subaddress Data Byte
Read/Write Bit Condition
T0036-01
Figure 42. Single-Byte Write Transfer
Multiple-Byte Write
A multiple-byte data-write transfer is identical to a single-byte data write transfer except that multiple data bytes
are transmitted by the master device to the DAP as shown in Figure 43. After receiving each data byte, the
TAS5715 responds with an acknowledge bit.
Start
Condition Acknowledge Acknowledge Acknowledge Acknowledge Acknowledge
A6 A5 A1 A0 R/W ACK A7 A6 A5 A4 A3 A1 A0 ACK D7 D0 ACK D7 D0 ACK D7 D0 ACK
2 Stop
I C Device Address and Subaddress First Data Byte Other Data Bytes Last Data Byte
Read/Write Bit Condition
T0036-02
Figure 43. Multiple-Byte Write Transfer

TAS5715
Single-Byte Read
As shown in Figure 44, a single-byte data-read transfer begins with the master device transmitting a start
condition followed by the I2C device address and the read/write bit. For the data-read transfer, both a write
followed by a read are actually done. Initially, a write is done to transfer the address byte or bytes of the internal
memory address to be read. As a result, the read/write bit becomes a 0. After receiving the TAS5715 address
and the read/write bit, TAS5715 responds with an acknowledge bit. In addition, after sending the internal memory
address byte or bytes, the master device transmits another start condition followed by the TAS5715 address and
the read/write bit again. This time the read/write bit becomes a 1, indicating a read transfer. After receiving the
address and the read/write bit, the TAS5715 again responds with an acknowledge bit. Next, the TAS5715
transmits the data byte from the memory address being read. After receiving the data byte, the master device
transmits a not-acknowledge followed by a stop condition to complete the single-byte data-read transfer.
Repeat Start
Condition
Start Not
Condition Acknowledge Acknowledge Acknowledge Acknowledge
A6 A5 A1 A0 R/W ACK A7 A6 A5 A4 A0 ACK A6 A5 A1 A0 R/W ACK D7 D6 D1 D0 ACK
2 2
I C Device Address and Subaddress I C Device Address and Data Byte Stop
Read/Write Bit Read/Write Bit Condition
T0036-03
Figure 44. Single-Byte Read Transfer
Multiple-Byte Read
A multiple-byte data-read transfer is identical to a single-byte data-read transfer except that multiple data bytes
are transmitted by the TAS5715 to the master device as shown in Figure 45. Except for the last data byte, the
master device responds with an acknowledge bit after receiving each data byte.
Repeat Start
Condition
Start Not
Condition Acknowledge Acknowledge Acknowledge Acknowledge Acknowledge Acknowledge
A6 A0 R/W ACK A7 A6 A5 A0 ACK A6 A0 R/W ACK D7 D0 ACK D7 D0 ACK D7 D0 ACK
2 2
I C Device Address and Subaddress I C Device Address and First Data Byte Other Data Bytes Last Data Byte Stop
Read/Write Bit Read/Write Bit Condition
T0036-04
Figure 45. Multiple-Byte Read Transfer
Headphone Support in the TAS5715

The TAS5715 provides headphone PWM out that can drive a headphone amplifier. This feature cannot be used
in lineout mode, because once the headphone is selected, the speaker is muted. See the headphone use model
diagrams on how to use the headphone feature and quite turn on and off.
The headphone volume register is 0x0C. Headphone control bits are in the system control2 register (0x05).
Register 0x05 bit 4: This is headphone/speaker mode-select bit.
Bit 3: This bit selects the headphone volume to be same as speaker channel volume or headphone volume
register (0x0C).
Bit 1: This bit is used to drive pin A_SEL_HP_SDZ as an output. This must be set to 1 if that pin is used. This
pin is a multi-function pin. On reset, it is an input used for I2C address select. After coming out of reset, this pin
can be programmed to be an output. It drives HP_SDZ when coming out of shutdown in headphone mode. The
internal control state machine takes care of the timing on PWM switching and HP_SDZ going low to high to avoid
start/stop clicks.

TAS5715
Bit 0: This is bit should be 1 if the headphone function is used in the TAS5715. If the headphone is not used, this
bit can be cleared to 0. Then if bit 1 is also set to 1, the TAS5715 drives the FAULTZ signal out on the A_SEL
pin. FAULTZ is the internal power-stage fault signal asserted low during errors like overcurrent, overtemperature,
and UVP.
Figure 46 shows the connection of A_SEL_HP_SDZ pin to headphone shutdown.
2
I S Audio Left
TAS5715
Right
(HP Amplifier)
HPL
RC
HPR Filter
Addr = 0x54 A_sel_HP_SDZ
15 k
B0424-01
Figure 46. Headphone Shutdown (HP_SD)
Digital THD Manager

The THD manager can be used to achieve digitally the {specified ?} THD levels without voltage clipping. This
allows the customer to achieve the same THD (for example, 10% THD) for different power levels (15 W/10 W/5
W) with same PVCC level.
The waveform of Figure 47 shows digital clipping using the THD manager.
Figure 47. Digital Clipping Using the THD Manager
Register 0x57 is used to achieve the clipping. Register 0x56 is used to scale the clipped waveform to get the
desired power out.

TAS5715
PWM DC Detection
The TAS5715 supports a PWM dc-detect function. This is to detect dc present in the input source and generated
by another means in the blocks prior to PCM-to-PWM conversion.
If enabled (0x46, bit 10), the detection block checks for PWM duty cycle. If it is above the programmed threshold
(0x0F, bits 74]) for more than the programmed duration of time (0x0F, bits 30), the PWM dc error flag is set on
error register 0x02, bit 0.
This bit is set as long as the dc condition remains. Once the dc condition is gone, the bit is cleared automatically.
The bit is cleared if detection is disabled.
Biquad Corruption Control

The TAS5715 supports this function to prevent issues when a biquad value is corrupted due an error in the I2C
line while updating biquads. The system controller writes a checksum for the biquads into the checksum register.
Once the EQ CRC detect function is enabled (0x46, bit 25), the TAS5715 periodically calculates a checksum for
biquads in DAP memory and compare it with the expected checksum. If an error occurs, then the crc error flag is
set in register 0x02, bit 3.

TAS5715
Automatic Gain Limit (DRC)

The DRC scheme has a single programmable threshold. There is one ganged DRC for the high-band left/right
channels and one DRC for the low-band left/right channels.
The DRC input/output diagram is shown in Figure 48.
Output Level (dB)
1:1 Transfer Function
Implemented Transfer Function
T
Input Level (dB)
M0176-01
Professional-quality dynamic range compression automatically adjusts volume to flatten volume level.
Each DRC has adjustable threshold levels.
Programmable attack, release, and softening-filter constants
Transparent compression: compressors can attack fast enough to avoid apparent clipping before engaging,
and decay times can be set slow enough to avoid pumping.
Figure 48. Automatic Gain Limit
Attack/Release Softening Filter Threshold
DRC1 0x3C 0x3B 0x40
DRC2 0x3F 0x3E 0x43
Alpha Filter Structure
S
a w 1
Z
B0265-05
T = 9.23 format, all other DRC coefficients are 3.23 format
Figure 49. DRC Filter Structure
DRC acts more like a gain limiter (automatic gain limiter, AGL). The block works to reduce the peak of energy if it
goes beyond the programmable threshold level. DRC starts an attack event (reduces gain) if energy goes above
the threshold. Similarly, it starts a release event if the level goes below the threshold (increases gain back to the
original value).

TAS5715
Attack and release events occur only when level remains above or below the threshold continuously during the
time-constant time. And the constant time is controlled by the attack/release rate. If the attack/release rate is
short, DRC operates frequently. Attack time defines how fast to cut the signal to bring it under the threshold.
Similarly, release time defines how fast to release the cut back to normal. Attack and release are shown in
Figure 50.
Threshold
INPUT
Threshold
OUTPUT
Attack Rate Release Rate

W0003-01
Figure 50. Attack/Release
The device should be in all-channel shutdown when DRC parameters are changed. The TAS57X GDE (GUI)
takes care of this when changing DRC parameters.
TAS5715 supports two-band and one-band DRC. Two-band DRC helps to get the maximum sound levels out of
small, thin, low-cost speakers. It protects speakers from being overdriven/damaged and stops cabinet rattle
without sacrificing loudness.
In the two-band DRC mode, audio is split into to high-band and low-band. The bands have separate thresholds
and attack/decay filters.
Configuration is as shown in Figure 51. DRC1 (upper band) and DRC2 (lower band) can be programmed using
GDE. Default values for attack and decay filters cover most of the cases. Only thresholds require updating,
depending on the power levels for the upper and lower bands.

TAS5715
HPF DRC-1
L_IN Speaker EQ L_OUT
LPF DRC-2
B0425-01
Figure 51. Two-Band DRC
A crossover biquad should be used only for two-band DRC. It should be all-pass for the one-band DRC mode.
Only DRC1 (upper band) is used in the one-band DRC mode.

TAS5715
BANK SWITCHING
The TAS5715 uses an approach called bank switching together with automatic sample-rate detection. All
processing features that must be changed for different sample rates are stored internally in three banks. The
user can program which sample rates map to each bank. By default, bank 1 is used in 32-kHz mode, bank 2 is
used in 44.1/48-kHz mode, and bank 3 is used for all other rates. Combined with the clock-rate autodetection
feature, bank switching allows the TAS5715 to detect automatically a change in the input sample rate and switch
to the appropriate bank without any MCU intervention.
An external controller configures bankable locations (0x290x36, 0x3A0x3F, and 0x59,0x5D) for all three banks
during the initialization sequence.
If automatic bank switching is enabled (register 0x50, bits 2:0) , then the TAS5715 automatically swaps the
coefficients for subsequent sample rate changes, avoiding the need for any external controller intervention for a
sample-rate change.
By default, bits 2:0 have the value 000; indicating that bank switching is disabled. In that state, updates to
bankable locations take immediate effect. A write to register 0x50 with bits 2:0 being 001, 010, or 011 brings the
system into the coefficient-bank-update state update bank1, update bank2, or update bank3, respectively. Any
subsequent write to bankable locations updates the coefficient banks stored outside the DAP. After updating all
the three banks, the system controller should issue a write to register 0x50 with bits 2:0 being 100; this changes
the system state to automatic bank-switching mode. In automatic bank-switching mode, the TAS5715
automatically swaps banks based on the sample rate.
Command sequences for updating DAP coefficients can be summarized as follows:

1. Bank switching disabled (default): DAP coefficient writes take immediate effect and are not
influenced by subsequent sample rate changes.
OR
Bank switching enabled:
(a) Update bank-1 mode: Write 001 to bits 2:0 of reg 0x50. Load the 32-kHz coefficients.
(b) Update bank-2 mode: Write 010 to bits 2:0 of reg 0x50. Load the 48-kHz coefficients.
(c) Update bank-3 mode: Write 011 to bits 2:0 of reg 0x50. Load the other coefficients.
(d) Enable automatic bank switching by writing 100 to bits 2:0 of reg 0x50.
26-Bit 3.23 Number Format

All mixer gain coefficients are 26-bit coefficients using a 3.23 number format. Numbers formatted as 3.23
numbers means that there are 3 bits to the left of the binary point and 23 bits to the right of the binary point. This
is shown in Figure 52 .
23
2 Bit
5
2 Bit
1
2 Bit
0
2 Bit
1
2 Bit
Sign Bit
S_xx.xxxx_xxxx_xxxx_xxxx_xxxx_xxx
M0125-01
Figure 52. 3.23 Format

TAS5715
The decimal value of a 3.23 format number can be found by following the weighting shown in Figure 52. If the
most significant bit is logic 0, the number is a positive number, and the weighting shown yields the correct
number. If the most significant bit is a logic 1, then the number is a negative number. In this case every bit must
be inverted, a 1 added to the result, and then the weighting shown in Figure 53 applied to obtain the magnitude
of the negative number.
1 0 1 4 23
2 Bit 2 Bit 2 Bit 2 Bit 2 Bit
1 0 1 4 23
(1 or 0) 2 + (1 or 0) 2 + (1 or 0) 2 + ....... (1 or 0) 2 + ....... (1 or 0) 2
M0126-01
Figure 53. Conversion Weighting Factors3.23 Format to Floating Point
Gain coefficients, entered via the I2C bus, must be entered as 32-bit binary numbers. The format of the 32-bit
number (4-byte or 8-digit hexadecimal number) is shown in Figure 54
Sign Fraction
Bit Digit 6
Fraction Fraction Fraction Fraction Fraction

Integer Digit 1 Digit 2 Digit 3 Digit 4 Digit 5
Digit 1
u u u u u u S x x. x x x x x x x x x x x x x x x x x x x x x x x 0
Coefficient Coefficient Coefficient Coefficient Coefficient Coefficient Coefficient Coefficient

Digit 8 Digit 7 Digit 6 Digit 5 Digit 4 Digit 3 Digit 2 Digit 1
u = unused or dont care bits

Digit = hexadecimal digit
M0127-01
2
Figure 54. Alignment of 3.23 Coefficient in 32-Bit I C Word
Table 1. Sample Calculation for 3.23 Format

db Linear Decimal Hex (3.23 Format)
0 1 8,388,608 80 0000
5 1.77 14,917,288 00E3 9EA8
5 0.56 4,717,260 0047 FACC
X L = 10(X/20) D = 8388608 L H = dec2hex (D, 8)
Table 2. Sample Calculation for 9.17 Format

db Linear Decimal Hex (9.17 Format)
0 1 131,072 20 000
5 1.77 231,997 38 A3D
5 0.56 73,400 11 EB8
X L = 10(X/20) D = 131,072 L H = dec2hex (D, 8)

40
TAS5715
SLOS645 AUGUST 2010
Initialization Normal Operation Shutdown Powerdown

Recommended Use Model
Submit Documentation Feedback

AVDD/DVDD 3V 3V
0 ns
PDN
(1)
tPLL 50 ms
0 ns 2 ms
2 SCL DAP Other Exit Enter

I C Trim Config Config Volume and Mute Commands
SDA SD SD
(2) (2)
50 ms 1 ms + 1.3 tstart 1 ms + 1.3 tstop 2 ms
0 ns
100 ms
RESET 13.5 ms
(1)
tPLL
2 ms

100 s
10 ms
PVDD 8V 8V
6V 6V
(1) tPLL has to be greater than 240 ms + 1.3 tstart.

This constraint only applies to the first trim command following AVDD/DVDD power-up.
Figure 55. Recommended Command Sequence

It does not apply to trim commands following subsequent resets.
(2) tstart/tstop = PWM start/stop time as defined in register 0X1A
T0419-03
www.ti.com

TAS5715
AVDD/DVDD 3V
0 ns
PDN 2 ms
0 ns
2
I C
2 ms
RESET
2 ms
0 ns
8V
PVDD
6V
T0420-05
Figure 56. Power Loss Sequence
Initialization Sequence
Use the following sequence to power-up and initialize the device:
1. Hold all digital inputs low and ramp up AVDD/DVDD to at least 3V.
2. Initialize digital inputs and PVDD supply as follows:
Drive RESET = 0, PDN = 1, and other digital inputs to their desired state while ensuring that
all are never more than 2.5V above AVDD/DVDD. Wait at least 100s, drive RESET = 1, and
wait at least another 13.5ms.
Ramp up PVDD to at least 8V while ensuring that it remains below 6V for at least 100s after
AVDD/DVDD reaches 3V. Then wait at least another 10s.
3. Trim oscillator (write 0x00 to register 0x1B) and wait at least 50ms.
4. Configure the DAP via I2C (see Users's Guide for typical values).
5. Configure remaining registers.
6. Exit shutdown (sequence defined below).
Normal Operation
The following are the only events supported during normal operation:
1. Writes to master/channel volume registers.
2. Writes to soft mute register.
3. Enter and exit shutdown (sequence defined below).
4. Clock errors and rate changes.
Note: Events 3 and 4 are not supported for 240ms+1.3*Tstart after trim following AVDD/DVDD powerup
ramp (where Tstart is specified by register 0x1A).

TAS5715
Shutdown Sequence
Enter:
1. Ensure I2S clocks have been stable and valid for at least 50ms.
2. Write 0x40 to register 0x05.
3. Wait at least 1ms+1.3*Tstop (where Tstop is specified by register 0x1A).
4. Once in shutdown, stable clocks are not required while device remains idle.
5. If desired, reconfigure by ensuring that clocks have been stable and valid for at least 50ms before
returning to step 4 of initialization sequence.
Exit:
1. Ensure I2S clocks have been stable and valid for at least 50ms.
2. Write 0x00 to register 0x05 (exit shutdown command may not be serviced for as much as 240ms
after trim following AVDD/DVDD powerup ramp).
3. Wait at least 1ms+1.3*Tstart (where Tstart is specified by register 0x1A).
4. Proceed with normal operation.
Powerdown Sequence
Use the following sequence to powerdown the device and its supplies:
1. If time permits, enter shutdown (sequence defined above); else, in case of sudden power loss,
assert PDN = 0 and wait at least 2ms.
2. Assert RESET = 0.
3. Drive digital inputs low and ramp down PVDD supply as follows:
Drive all digital inputs low after RESET has been low for at least 2s.
Ramp down PVDD while ensuring that it remains above 8V until RESET has been low for at
least 2s.
4. Ramp down AVDD/DVDD while ensuring that it remains above 3V until PVDD is below 6V and
that it is never more than 2.5V below the digital inputs.

TAS5715
Headphone Usage
HP/SPKR
(SE/BTL)
VALID
PWM_A(L+)
SpkrL+/R+ 50% HPL/R SpkrL+/R+
PWM_C(R+)
t(mute) t(exitSDHP) t(mute) t(enterSDHPamp)

t(exitSDHPamp)
PWM_B(L)
SpkrL/R 50% SpkrL/R
PWM_D(R)
t(enterSD) t(exitSD)
FAULT = 1 Output
HPSD
(A0/FAULT)
Hi-Z (Ext. Pulldown)
I2C: SCL Enter HP Exit Enable Disable Enter Spkr Exit Unmute
Mute Config Unmute Mute Config
SDA ACSD ACSD FAULT FAULT ACSD ACSD (if not done in
Spkr Config)
PDN
T0452-01
Headphone/Speaker Configuration
PARAMETE
DESCRIPTION MIN TYP MAX UNIT
R
t(mute) Mute volume ramp wait time (t(volramp) given by register 0x0E <2:0>) 5 + 1.3 t(volramp) ms
Exit shutdown wait time before issuing further commands to device (t(start)
t(exitSD) 1 + 1.3 t(start) ms
given by regioster 0x1A<4:0>)
Enter shutdown wait time before issuing further commands to device (t(stop)
t(enterSD) 1 + 1.3 t(stop) ms
given by regioster 0x1A<4:0>)
Exit shutdown wait time before enabling external headphone amp (t(HPchg)
t(exitSDHP) 1 + 1.3 t(HPchg) ms
given by register 0x1A<6:5>)
Headphone amp exit shutdown wait time before unmuting (t(HPamp) given by
t(exitSDHPamp) 1 + 1.3 t(HPamp) ms
register 0x1C<7:4>)
Headphone amp enter shutdown wait time before entering ACSD (t(HPamp)
t(enterSDHPamp) 1 + 1.3 t(HPamp) ms
given by register 0x1C<7:4>)
Figure 57. Headphone Control Use Model
Speaker Configuration
Registers 0x070x0B Master/channel speaker volume
Register 0x19 SDG = 0x30 or 0x00 (no channels in SDG)
Registers 0x110x12 ICD1/2 = {0xB8, 0x60}
Register 0x1A<7> Clear bit for speaker mode (HP/SPKR = 0)
Register 0x1A<4:0> Set to 0 1000 for 16.5-ms start/stop period
Register 0x20<23> Set bit for Ch1 BD mode
Register 0x20<19> Set bit for Ch2 BD mode
Register 0x46<1:0> Set both bits to enable DRC1 and DRC2
Register 0x50<7> Clear bit to enable EQ

TAS5715
Headphone Configuration
Registers 0x070x0B Master/channel headphone volume
Register 0x19 SDG = 0x30 or 0x00 (PWM3/4 in SDG)
Registers 0x110x12 ICD1/2 = {0xAC, 0x54}
Register 0x1A<7> Clear bit for headphone mode (HP/SPKR = 0)
Register 0x1A<4:0> Set to 0 0000 for 0-ms start/stop period
Register 0x20<23> Clear bit for Ch1 AD mode
Register 0x20<19> Clear bit for Ch2 AD mode
Register 0x46<1:0> Clear both bits to disable DRC1 and DRC2
Register 0x50<7> Set bit to disable EQ
Headphone Mode Power Down

HP/SPKR
(SE/BTL)
VALID
PWM_A(L+)
PWM_C(R+) HPL/R HPL/R
t(exitSDHP)
t(HPamp) t(exitSDHPamp)
PWM_B(L)
PWM_D(R)
FAULT = 1 Output
HPSD
(A0/FAULT)
I2C: SCL Enable

SDA FAULT
t(PDN-HPSD)
PDN
T0453-01
PARAMETE
R
t(PDN-HPSD) Delay from power-down event to headphone amplifier shutdown assertion 2 ms
Headphone amp exit shutdown wait time before unmuting (t(HPamp) given by 1 + 1.3
t(exitSDHPamp) ms
register 0x1C<7:4>) t(HPamp)
t(HPamp) Headphone amp enable/disable wait time (given by register 0x1C<7:4>) t(HPamp) ms
Figure 58. Headphone Control Power Down

TAS5715
Headphone-Mode All-Channel Shutdown
HP/SPKR
(SE/BTL)
VALID
PWM_A(L+)
PWM_C(R+) HPL/R HPL/R
t(mute) t(exitSDHP)
t(enterSDHPamp) t(exitSDHPamp)
PWM_B(L)
PWM_D(R)
FAULT = 1 Output
HPSD
(A0/FAULT)
I2C: SCL Disable Enter HP Exit Enable

Mute Config Unmute
SDA FAULT ACSD ACSD FAULT
PDN
T0454-01
PARAMETE
R
5 + 1.3
t(mute) Mute volume ramp wait time (t(volramp) given by register 0x0E <2:0>) ms
t(volramp)
Headphone amp exit shutdown wait time before unmuting (t(HPamp) given by 1 + 1.3
t(exitSDHPamp) ms
register 0x1C<7:4>) t(HPamp)
Headphone amp enter shutdown wait time before entering ACSD (t(HPamp) 1 + 1.3
t(enterSDHPamp) ms
given by register 0x1C<7:4>) t(HPamp)
Figure 59. Headphone Control ACSD
Applying Soft Reset

To soft-reset the device, write 0x01 to register 0xC8. Once soft reset is applied, I2C commands should not be
sent for a duration of 2 (1 ms + 1.3 t(start/stop)) + 13.5 ms.
Restrictions in Using 432-kHz Output Switching

Only 48-kHz LRCLK is supported. The maximum allowed variance on LRCLK is 1%.
The maxmimum allowed MCLK frequency is 12.288 MHz + 1%.
Only 64-fS SCLK is supported.
PWM headphone output is not supported.
I2C Commands to enable 423-kHz Switching

All I2C write operations should be at 100 kHz when used in this higher switching mode.
No 400-kHz I2C is supported when used in this mode.
To switch into 432-kHz switching mode, send the following commands before sending the exit shutdown
command to register 0x05.
Write to register 0xF8 with a value of 0xA5A5A5A5.
TAS5715
Write to register 0xC9 with a value of 0x000600EA.

Write to register 0xCA with a value of 0x0000000000000098. Note that register 0xCA is a write-only register.
Reads from this register are prohibited.
Write to register 0x03 with a value of 0x88.
Write to register 0x00 with a value of 0x6D.
Write to register 0x00 with a value of 0x6C.

TAS5715
Table 3. Serial Control Interface Register Summary

NO. OF INITIALIZATION
SUBADDRESS REGISTER NAME CONTENTS
BYTES VALUE
A u indicates unused bits.
0x00 Clock control register 1 Description shown in subsequent section 0x6C
0x01 Device ID register 1 Description shown in subsequent section 0x42
0x02 Error status register 1 Description shown in subsequent section 0x00
0x03 System control register 1 1 Description shown in subsequent section 0xA0
0x04 Serial data interface 1 Description shown in subsequent section 0x05
register
0x05 System control register 2 1 Description shown in subsequent section 0x40
0x06 Soft mute register 1 Description shown in subsequent section 0x00
0x07 Master volume 1 Description shown in subsequent section 0xFF (mute)
0x08 Channel 1 vol 1 Description shown in subsequent section 0x30 (0 dB)
0x09 Channel 2 vol 1 Description shown in subsequent section 0x30 (0 dB)
0x0A Channel 3 vol 1 Description shown in subsequent section 0x30 (0 dB)
0x0B0x0D 1 Reserved (1)
0x0E Volume configuration 1 Description shown in subsequent section 0x90
register
0x0F Max duty cycle register 1 Description shown in subsequent section 0x97
0x10 Modulation limit register 1 Description shown in subsequent section 0x01
0x11 IC delay channel 1 1 Description shown in subsequent section 0xAC
0x12 IC delay channel 2 1 Description shown in subsequent section 0x54
0x13 IC delay channel 3 1 Description shown in subsequent section 0xAC
0x14 IC delay channel 4 1 Description shown in subsequent section 0x54
0x150x19 1 Reserved (1)
0x1A Start/stop period register 1 0x68
0x1B Oscillator trim register 1 0x82
0x1C BKND_ERR register 1 0x57
0x1D0x1F 1 Reserved (1)
0x20 Input MUX register 4 Description shown in subsequent section 0x0001 7772
(1)
0x21 4 Reserved 0x0000 4303
0x220x24 4 Reserved (1)
0x25 PWM MUX register 4 Description shown in subsequent section 0x0102 1345
(1)
0x260x28 4 Reserved
0x29 ch1_bq[0] 20 u[31:26], b0[25:0] 0x0080 0000
u[31:26], b1[25:0] 0x0000 0000
u[31:26], b2[25:0] 0x0000 0000
u[31:26], a1[25:0] 0x0000 0000
u[31:26], a2[25:0] 0x0000 0000
0x2A ch1_bq[1] 20 u[31:26], b0[25:0] 0x0080 0000
u[31:26], b1[25:0] 0x0000 0000
u[31:26], b2[25:0] 0x0000 0000
u[31:26], a1[25:0] 0x0000 0000
u[31:26], a2[25:0] 0x0000 0000
(1) Reserved registers should not be accessed.

TAS5715
Table 3. Serial Control Interface Register Summary (continued)

BYTES VALUE
0x2B ch1_bq[2] 20 u[31:26], b0[25:0] 0x0080 0000
u[31:26], b1[25:0] 0x0000 0000
u[31:26], b2[25:0] 0x0000 0000
u[31:26], a1[25:0] 0x0000 0000
u[31:26], a2[25:0] 0x0000 0000
0x2C ch1_bq[3] 20 u[31:26], b0[25:0] 0x0080 0000
u[31:26], b1[25:0] 0x0000 0000
u[31:26], b2[25:0] 0x0000 0000
u[31:26], a1[25:0] 0x0000 0000
u[31:26], a2[25:0] 0x0000 0000
0x2D ch1_bq[4] 20 u[31:26], b0[25:0] 0x0080 0000
u[31:26], b1[25:0] 0x0000 0000
u[31:26], b2[25:0] 0x0000 0000
u[31:26], a1[25:0] 0x0000 0000
u[31:26], a2[25:0] 0x0000 0000
0x2E ch1_bq[5] 20 u[31:26], b0[25:0] 0x0080 0000
u[31:26], b1[25:0] 0x0000 0000
u[31:26], b2[25:0] 0x0000 0000
u[31:26], a1[25:0] 0x0000 0000
u[31:26], a2[25:0] 0x0000 0000
0x2F ch1_bq[6] 20 u[31:26], b0[25:0] 0x0080 0000
u[31:26], b1[25:0] 0x0000 0000
u[31:26], b2[25:0] 0x0000 0000
u[31:26], a1[25:0] 0x0000 0000
u[31:26], a2[25:0] 0x0000 0000
0x30 ch2_bq[0] 20 u[31:26], b0[25:0] 0x0080 0000
u[31:26], b1[25:0] 0x0000 0000
u[31:26], b2[25:0] 0x0000 0000
u[31:26], a1[25:0] 0x0000 0000
u[31:26], a2[25:0] 0x0000 0000
0x31 ch2_bq[1] 20 u[31:26], b0[25:0] 0x0080 0000
u[31:26], b1[25:0] 0x0000 0000
u[31:26], b2[25:0] 0x0000 0000
u[31:26], a1[25:0] 0x0000 0000
u[31:26], a2[25:0] 0x0000 0000
0x32 ch2_bq[2] 20 u[31:26], b0[25:0] 0x0080 0000
u[31:26], b1[25:0] 0x0000 0000
u[31:26], b2[25:0] 0x0000 0000
u[31:26], a1[25:0] 0x0000 0000
u[31:26], a2[25:0] 0x0000 0000
0x33 ch2_bq[3] 20 u[31:26], b0[25:0] 0x0080 0000
u[31:26], b1[25:0] 0x0000 0000
u[31:26], b2[25:0] 0x0000 0000
u[31:26], a1[25:0] 0x0000 0000
u[31:26], a2[25:0] 0x0000 0000

TAS5715

BYTES VALUE
0x34 ch2_bq[4] 20 u[31:26], b0[25:0] 0x0080 0000
u[31:26], b1[25:0] 0x0000 0000
u[31:26], b2[25:0] 0x0000 0000
u[31:26], a1[25:0] 0x0000 0000
u[31:26], a2[25:0] 0x0000 0000
0x35 ch2_bq[5] 20 u[31:26], b0[25:0] 0x0080 0000
u[31:26], b1[25:0] 0x0000 0000
u[31:26], b2[25:0] 0x0000 0000
u[31:26], a1[25:0] 0x0000 0000
u[31:26], a2[25:0] 0x0000 0000
0x36 ch2_bq[6] 20 u[31:26], b0[25:0] 0x0080 0000
u[31:26], b1[25:0] 0x0000 0000
u[31:26], b2[25:0] 0x0000 0000
u[31:26], a1[25:0] 0x0000 0000
u[31:26], a2[25:0] 0x0000 0000
0x37 EQ CRC 4 u[31:16], EQ CRC [15:0] 0x0000 A14C
0x38 DRC CRC 4 u[31:16], DRC CRC [15:0] 0x0000 5395
0x39 Reserved (2) 0x0000 0000
0x3A 8 Reserved (2) 0x0080 0000
0x3B DRC1 softening filter alpha 8 u[31:26], ae[25:0] 0x0008 0000
DRC1 softening filter u[31:26], oe[25:0] 0x0078 0000
omega
0x3C DRC1 attack rate 8 0x0000 0100
DRC1 release rate 0xFFFF FF00
0x3D 8 Reserved (2) 0x0080 0000
0x3E DRC2 softening filter alpha 8 u[31:26], ae[25:0] 0x0008 0000
DRC2 softening filter u[31:26], oe[25:0] 0xFFF8 0000
omega
0x3F DRC2 attack rate 8 u[31:26], at[25:0] 0x0008 0000
DRC2 release rate u[31:26], rt[25:0] 0xFFF8 0000
0x40 DRC1 attack threshold 8 T1[31:0] (9.23 format) 0x0800 0000
DRC1 release threshold T1'[31:0] 0x07FF FFFF
0x42 4 Reserved (2) 0x0000 0000
0x43 DRC2 attack threshold 8 T2[31:0] (9.23 format) 0x0074 0000
DRC2 release threshold T2'[31:0] 0x0073 FFFF
0x45 4 Reserved (2) 0x0000 0000
0x46 DRC and DC DETECT 4 Description shown in subsequent section 0x0002 0020
control
0x470x4F 4 Reserved (2)
0x50 Bank switch control 4 Description shown in subsequent section 0x0F70 8000
0x51 Ch 1 output mixer 8 Ch 1 output mix1[1] 0x0080 0000
Ch 1 output mix1[0] 0x0000 0000
0x52 Ch 2 output mixer 8 Ch 2 output mix2[1] 0x0080 0000
Ch 2 output mix2[0] 0x0000 0000
2
0x53 Ch 1 input mixers 16 Channel-1 input mixers can be accessed using I C
subaddresses 0x700x73 using 4-byte access

TAS5715

BYTES VALUE
0x54 Ch 2 input mixers 16 Channel-2 input mixers can be accessed using I2C
subaddresses 0x740x77 using 4-byte access
0x56 Output post-scale 4 u[31:26], post[25:0] 0x0080 0000
0x57 Output pre-scale 4 u[31:26], pre[25:0] (9.17 format) 0x0002 0000
0x59 ch1 BQ[7] (DRC1 BQ) 20 u[31:26], b0[25:0] 0x0080 0000
u[31:26], b1[25:0] 0x0000 0000
u[31:26], b2[25:0] 0x0000 0000
u[31:26], a1[25:0] 0x0000 0000
u[31:26], a2[25:0] 0x0000 0000
0x5D ch2 BQ[8] (DRC2 BQ) 20 u[31:26], b0[25:0] 0x0080 0000
u[31:26], b1[25:0] 0x0000 0000
u[31:26], b2[25:0] 0x0000 0000
u[31:26], a1[25:0] 0x0000 0000
u[31:26], a2[25:0] 0x0000 0000
0x62 IDF post scale 4 0x0000 0080
0x630x6F Reserved (3) 0x0000 0000
0x70 ch1 DRC 4 Ch 1 Input mixer[3] 0x0080 0000
cross-over_mixer_1
0x71 4 Reserved (3) 0x0000 0000
0x72 4 Ch 1 Input mixer[1]; THIS NODE is RESERVED as 0x0000 0000
ZERO
0x73 ch1 Input Sclaer 4 Ch 1 Input mixer[0] 0x0080 0000
0x74 ch2 DRC 4 Ch 2 Input mixer[3] 0x0080 0000
cross-over_mixer_1
0x75 4 Reserved (3) 0x0000 0000
0x76 4 Ch 2 Input mixer[1]; THIS NODE is RESERVED as 0x0000 0000
ZERO
0x77 ch2 Input Scaler 4 Ch 2 Input mixer[0] 0x0080 0000
0x780xC7 Reserved (3) 0x0000 0000
0xC8 Soft Reset Register [bit 0] 4 Soft Reset Reg (bit [0] = 1 assert soft reset to the 0x0000 0000
device)
0xC90xF7 Reserved (3) 0x0000 0000
0xF8 4 Reserved (3) 0x0000 0000
0xF9 Update Dev Address Reg 4 u[31:8],New Dev Id[7:0] (New Dev Id = 0x38 for 0x0000 0036
TAS5715)
0xFE Repeat Sub Address 4 Append the write to previous write
0xFA0xFF 4 Reserved (3) 0x0000 0000
All DAP coefficients are 3.23 format unless specified otherwise.

Registers 0x3B through 0x46 should be altered only during the initialization phase.

TAS5715
CLOCK CONTROL REGISTER (0x00)

The clocks and data rates are automatically determined by the TAS5715. The clock control register contains the
auto-detected clock status. Bits D7D5 reflect the sample rate. Bits D4D2 reflect the MCLK frequency.
Table 4. Clock Control Register (0x00)

D7 D6 D5 D4 D3 D2 D1 D0 FUNCTION
0 0 0 fS = 32-kHz sample rate
0 0 1 Reserved (1)
0 1 0 Reserved (1)
(2)
0 1 1 fS = 44.1/48-kHz sample rate
1 0 1 fS = 22.05/24 -kHz sample rate
1 1 1 fS = 11.025/12-kHz sample rate
(3)
0 0 0 MCLK frequency = 64 fS
(3)
(4)
(2) (5)
1 1 0 Reserved (1)
1 1 1 Reserved (1)
0 Reserved (1)
(1)
0 Reserved

(2) Default values are in bold.
(3) Only available for 44.1-kHz and 48-kHz rates
(4) Rate only available for 32/44.1/48-KHz sample rates
(5) Not available at 8 kHz
DEVICE ID REGISTER (0x01)

The device ID register contains the ID code for the firmware revision.
Table 5. General Status Register (0x01)

0 1 0 0 0 0 1 0 Identification code

TAS5715
ERROR STATUS REGISTER (0x02)

The error bits are sticky and are not cleared by the hardware. This means that the software must clear the
register (write zeroes) and then read them to determine if they are persistent errors.
Error definitions:
MCLK error : MCLK frequency is changing. The number of MCLKs per LRCLK is changing.
SCLK error: The number of SCLKs per LRCLK is changing.
LRCLK error: LRCLK frequency is changing.
Frame slip: LRCLK phase is drifting with respect to internal frame sync.
DC detect: This flag is set if PWM dc detect is enabled and dc is detected in the PWM block.
Table 6. Error Status Register (0x02)

1 MCLK error
1 PLL autolock error
1 SCLK error
1 LRCLK error
1 EQ flag
1 DRC flag
1 Overcurrent, overtemperature, overvoltage, or undervoltage errors
1 PWM DC-detect flag
(1)
0 0 0 0 0 0 0 0 No errors
SYSTEM CONTROL REGISTER 1 (0x03)

The system control register 1 has several functions:
Bit D7: If 0, the dc-blocking filter for each channel is disabled.

If 1, the dc-blocking filter (3 dB cutoff <1 Hz) for each channel is enabled (default).
Bit D5: If 0, use soft unmute on recovery from clock error. This is a slow recovery. Unmute takes the
same time as the volume ramp defined in register 0x0E.
If 1, use hard unmute on recovery from clock error (default). This is a fast recovery, a single-step
volume ramp.
Bits D1D0: Select de-emphasis

TAS5715
Table 7. System Control Register 1 (0x03)

0 PWM high-pass (dc blocking) disabled
(1)
1 PWM high-pass (dc blocking) enabled
(1)
0 Reserved
0 Soft unmute on recovery from clock error
(1)
1 Hard unmute on recovery from clock error
(1)
1 Reserved
(1)
0 Reserved
0 Reserved (1)
(1)
0 0 No de-emphasis
0 1 De-emphasis for fS = 32 kHz
1 0 De-emphasis for fS = 44.1 kHz
1 1 De-emphasis for fS = 48 kHz
SERIAL DATA INTERFACE REGISTER (0x04)

As shown in Table 8, the TAS5715 supports nine serial data modes. The default is 24-bit, I2S mode.
Table 8. Serial Data Interface Control Register (0x04) Format

RECEIVE SERIAL DATA WORD
D7D4 D3 D2 D1 D0
INTERFACE FORMAT LENGTH
Right-justified 16 0000 0 0 0 0
2
I S 16 000 0 0 1 1
I2S 20 0000 0 1 0 0
I2S (1)
24 0000 0 1 0 1
Left-justified 16 0000 0 1 1 0
Reserved 0000 1 0 0 1
Reserved 0000 1 0 1 0
Reserved 0000 1 0 1 1
Reserved 0000 1 1 0 0
Reserved 0000 1 1 0 1
Reserved 0000 1 1 1 0
Reserved 0000 1 1 1 1

TAS5715
SYSTEM CONTROL REGISTER 2 (0x05)
When bit D6 is set low, the system exits all-channel shutdown and starts playing audio; otherwise, the outputs
are shut down (hard mute).
Table 9. System Control Register 2 (0x05)

0 Reserved (1)
0 Exit all-channel shutdown (normal operation) (2)
1 Enter all-channel shutdown (hard mute) (1)
(1)
0 - - Reserved
1 Headphone Mode
0 Speaker Mode
Channel Volume in Headphone Mode = 0x08/0x09 (same as speaker channel volume
1
reg)
(1)
0 Channel VOlume in Headphone Mode = 0x0C (headphone volume reg)
(1)
0 Reserved
0 A_SEL/HP_SD configured as input
A_SEL/HP_SD configured configured as output to use as external HP amplifier
1
shutdown signal
0 Internal power stage FAULT signal is the source of A_SEL/HP_SD pin
HPSDZ is the source of A_SEL/HP_SD pin (set this before switching to headphone
1
mode)

(2) When exiting all-channel shutdown, soft unmute is might not occur unless register 0x03, bit 5 is set to 1.
SOFT MUTE REGISTER (0x06)

Writing a 1 to any of the following bits sets the output of the respective channel to 50% duty cycle (soft mute).
Table 10. Soft Mute Register (0x06)

0 0 0 0 0 Reserved (1)
1 Soft mute channel 3
0 Soft unmute channel 3

TAS5715
VOLUME REGISTERS (0x07, 0x08, 0x09, 0x0C)

Step size is 0.5 dB.
Master volume 0x07 (default is mute)

Channel-1 volume 0x08 (default is 0 dB)
Channel-2 volume 0x09 (default is 0 dB)
Headphone volume 0x0C (default is 0 dB)
Volume in the TAS5715 is not intended for dynamic changes. Channel volumes are set during initialization.
Master volume is written with a value 0xFF to MUTE and with a value of 0x30 to UNMUTE during normal mode.
When DRC functionality is used, the maximum allowed volume (sum of channel and master volume ) is 15.5 dB.
When DRC is enabled, a MUTE command does not completely mute the system. The actual mute level depends
on the volume settings and modulation index.
FINE VOLUME SETTING:
TAS5715 has input mixers (0x73 , 0x77) that can be fine-tuned with a 3.23 format number to achieve the fine
volume setting.
To achieve 12.125 db of master volume, set the mixer to 0.125 db and set 0x07 (maser volume) to 12 db. The
advantage is 0x73 and 0x77 can be set to a much finer setting using 3.23 format numbers, providing the
flexibility to adjust output power precisely.
Table 11. Volume Registers (0x07, 0x08, 0x09, 0x0C)

D D D D D D D D
FUNCTION
7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 24 dB
(1)
0 0 1 1 0 0 0 0 0 dB (default for individual channel volume)
1 1 1 1 1 1 1 0 103 dB
1 1 1 1 1 1 1 1 Soft mute
Table 12. Master Volume Table

HEX dB HEX dB HEX dB HEX dB HEX dB HEX dB
00 24 30 0 60 24 90 48 C0 72 F0 96
01 23.5 31 0.5 61 24.5 91 48.5 C1 72.5 F1 96.5
02 23 32 1 62 25 92 49 C2 73 F2 97
03 22.5 33 1.5 63 25.5 93 49.5 C3 73.5 F3 97.5
04 22 34 2 64 26 94 50 C4 74 F4 98
05 21.5 35 2.5 65 26.5 95 50.5 C5 74.5 F5 98.5
06 21 36 3 66 27 96 51 C6 75 F6 99
07 20.5 37 3.5 67 27.5 97 51.5 C7 75.5 F7 99.5
08 20 38 4 68 28 98 52 C8 76 F8 100
09 19.5 39 4.5 69 28.5 99 52.5 C9 76.5 F8
0A 19 3A 5 6A 29 9A 53 CA 77 FA
0B 18.5 3B 5.5 6B 29.5 9B 53.5 CB 77.5 FB
0C 18 3C 6 6C 30 9C 54 CC 78 FC
0D 17.5 3D 6.5 6D 30.5 9D 54.5 CD 78.5 FD
0E 17 3E 7 6E 31 9E 55 CE 79 FE
0F 16.5 3F 7.5 6F 31.5 9F 55.5 CF 79.5 FF
10 16 40 8 70 32 A0 56 D0 80

TAS5715
Table 12. Master Volume Table (continued)

HEX dB HEX dB HEX dB HEX dB HEX dB HEX dB
11 15.5 41 8.5 71 32.5 A1 56.5 D1 80.5
12 15 42 9 72 33 A2 57 D2 81
13 14.5 43 9.5 73 33.5 A3 57.5 D3 81.5
14 14 44 10 74 34 A4 58 D4 82
15 13.5 45 10.5 75 34.5 A5 58.5 D5 82.5
16 13 46 11 76 35 A6 59 D6 83
17 12.5 37 11.5 77 35.5 A7 59.5 D7 83.5
18 12 38 12 78 36 A8 60 D8 84
19 11.5 39 12.5 79 36.5 A9 60.5 D9 84.5
1A 11 4A 13 7A 37 AA 61 DA 85
1B 10.5 4B 13.5 7B 37.5 AB 61.5 DB 85.5
1C 10 4C 14 7C 38 AC 62 DC 86
1D 9.5 4D 14.5 7D 38.5 AD 62.5 DD 86.5
1E 9 4E 15 7E 39 AE 63 DE 87
1F 8.5 4F 15.5 7F 39.5 AF 63.5 DF 87.5
20 8 50 16 80 40 B0 64 E0 88
21 7.5 51 16.5 81 40.5 B1 64.5 E1 88.5
22 7 52 17 82 41 B2 65 E2 89
23 6.5 53 17.5 83 41.5 B3 65.5 E3 89.5
24 6 54 18 84 42 B4 66 E4 90
25 5.5 55 18.5 85 42.5 B5 66.5 E5 90.5
26 5 56 19 86 43 B6 67 E6 91
27 4.5 547 19.5 87 43.5 B7 67.5 E7 91.5
28 4 58 20 88 44 B8 68 E8 92
29 3.5 59 20.5 89 44.5 B9 68.5 E9 92.5
2A 3 5A 21 8A 45 BA 69 EA 93
2B 2.5 5B 21.5 8B 45.5 BB 69.5 EB 93.5
2C 2 5C 22 8C 46 BC 70 EC 94
2D 1.5 5D 22.5 8D 46.5 BD 70.5 ED 94.5
2E 1 5E 23 8E 47 BE 71 EE 95
2F 0.5 5F 23.5 8F 47.5 BF 71.5 EF 95.5

TAS5715
VOLUME CONFIGURATION REGISTER (0x0E)
Bits Volume slew rate (Used to control volume change and MUTE ramp rates). These bits control the
D2D0: number of steps in a volume ramp. Volume steps occur at a rate that depends on the sample rate of
the I2S data as follows:
Sample rate (KHz) Approximate ramp rate
8/16/32 125 ms/step
11.025/22.05/44.1 90.7 ms/step
12/24/48 83.3 ms/step
Table 13. Volume Control Register (0x0E)

(1)
1 0 0 1 0 Reserved
0 0 0 Volume slew 512 steps (43 ms volume ramp time at 48 kHz) (1)
0 0 1 Volume slew 1024 steps (85 ms volume ramp time at 48 kHz)
1 X X Reserved
DC DETECT CONTROL REGISTER (0x0F)
Table 14. DC Detect Control Register (0x0F) (1)

D7 D6 D5 D4 D3 D2 D1 D0 Magnitude MAX + MAX
0 0 0 0 7 52.73% 47.27%
0 0 0 1 15 55.86% 44.14%
0 0 1 0 23 58.98% 41.02%
0 0 1 1 31 62.11% 37.89%
0 1 0 0 39 65.23% 34.77%
0 1 0 1 47 68.36% 31.64%
0 1 1 0 55 71.48% 28.52%
0 1 1 1 63 74.61% 25.39%
1 0 0 0 71 77.73% 22.27%
1 0 0 1 79 80.86% 19.14%
1 0 1 0 87 83.98% 16.02%
1 0 1 1 95 87.11% 12.89%
1 1 0 0 103 90.23% 9.77%
1 1 0 1 111 93.36% 6.64%
1 1 1 0 119 96.48% 3.52%
1 1 1 1 127 99.61% 0.39%
Time, ms
0 0 0 0 157.1
0 0 0 1 314.2
0 0 1 0 471.3
0 0 1 1 628.4
0 1 0 0 785.5
0 1 0 1 942.6
0 1 1 0 1099.7
(1) See register 0x46, bit D10 for enable/disable control of this feature.
TAS5715
Table 14. DC Detect Control Register (0x0F)(1) (continued)

D7 D6 D5 D4 D3 D2 D1 D0 Magnitude MAX + MAX
0 1 1 1 1256.8
1 0 0 0 1413.9
1 0 0 1 1571
1 0 1 0 1728.1
1 0 1 1 1885.2
1 1 0 0 2042.3
1 1 0 1 2199.4
1 1 1 0 2356.5
1 1 1 1 2513.6

TAS5715
MODULATION LIMIT REGISTER (0x10)
Table 15. Modulation Limit Register (0x10)

D7 D6 D5 D4 D3 D2 D1 D0 MODULATION LIMIT
0 0 0 0 0 Reserved
0 0 0 99.2%
(1)
0 0 1 98.4%
0 1 0 97.7%
0 1 1 96.9%
1 0 0 96.1%
1 0 1 95.3%
1 1 0 94.5%
1 1 1 93.8%
INTERCHANNEL DELAY REGISTERS (0x11, 0x12, 0x13, and 0x14)

Internal PWM Channels 1, 2, 1, and 2 are mapped into registers 0x11, 0x12, 0x13, and 0x14.
Table 16. Channel Interchannel Delay Register Format

BIT DEFINITION D7 D6 D5 D4 D3 D2 D1 D0 FUNCTION
0 0 0 0 0 0 Minimum absolute delay, 0 DCLK cycles
0 1 1 1 1 1 Maximum positive delay, 31 4 DCLK cycles
1 0 0 0 0 0 Maximum negative delay, 32 4 DCLK cycles
0 0 Reserved
SUBADDRESS D7 D6 D5 D4 D3 D2 D1 D0 Delay = (value) 4 DCLKs

(1)
0x11 1 0 1 0 1 1 Default value for channel 1
(1)
(1)
(1)
ICD settings have high impact on audio performance (e.g.: dynamic range, THD, crosstalk, etc.) Therefore,
appropriate ICD settings must be used. By default, the device has ICD settings for AD mode. If used in BD
mode, then update these registers before coming out of all-channel shutdown.
MODE AD MODE BD MODE

0x11 AC B8
0x12 54 60
0x13 AC A0
0x14 54 48

TAS5715
PWM SHUTDOWN GROUP REGISTER (0x19)

Settings of this register determine which PWM channels are active. The value should be 0x30 for BTL mode and
0x3A for PBTL mode. The default value of this register is 0x30. The functionality of this register is tied to the
state of bit D5 in the system control register.
This register defines which channels belong to the shutdown group (SDG). If a 1 is set in the shutdown group
register, that particular channel is not started following an exit out of all-channel shutdown command (if bit D5 is
set to 0 in system control register 2, 0x05).
Table 17. Shutdown Group Register

(1)
0 Reserved
(1)
0 Reserved
(1)
1 Reserved
(1)
1 Reserved
(1)
0 PWM channel 4 does not belong to shutdown group.
1 PWM channel 4 belongs to shutdown group.
(1)
(1)
(1)

TAS5715
START/STOP PERIOD REGISTER (0x1A)

This register is used to control the soft-start and soft-stop period following an enter/exit all-channel shutdown
command or change in the PDN state. This helps reduce pops and clicks at start-up and shutdown.The times are
only approximate and vary depending on device activity level and I2S clock stability.
Table 18. Start/Stop Period Register (0x1A)

(1)
0 1 0 PWM headphone start/stop time = 94.2 ms
0 0 X X X No 50% duty cycle start/stop period
0 1 0 0 0 16.5-ms 50% duty cycle start/stop period (1)
0 1 0 0 1 23.9-ms 50% duty cycle start/stop period
1 1 1 1 1 13,196.4-ms 50% duty cycle start/stop period

TAS5715
OSCILLATOR TRIM REGISTER (0x1B)

The TAS5715 PWM processor contains an internal oscillator to support autodetect of I2S clock rates. This
reduces system cost because an external reference is not required. Currently, TI recommends a reference
resistor value of 18.2 k (1%). This should be connected between OSC_RES and DVSSO.
Writing 0x00 to reg 0x1B enables the trim that was programmed at the factory.
Note that trim must always be run following reset of the device.
Table 19. Oscillator Trim Register (0x1B)

(1)
1 Reserved
(1)
0 Oscillator trim not done (read-only)
1 Oscillator trim done (read-only)
(1)
0 0 0 0 Reserved
0 Select factory trim (write a 0 to select factory trim; default is 1.)
(1)
1 Factory trim disabled
(1)
0 Reserved
BKND_ERR REGISTER (0x1C)

When a back-end error signal is received from the internal power stage, the power stage is reset stopping all
PWM activity. Subsequently, the modulator waits approximately for the time listed in Table 20 before attempting
to re-start the power stage.
Table 20. BKND_ERR Register (0x1C) (1)

0 0 1 1 Headphone start/stop time = 4 ms (2)
0 0 1 0 Set back-end reset period to 299 ms
0 1 1 1 Set back-end reset period to 1047 ms (2)
1 0 1 X Set back-end reset period to 1496 ms
1 1 X X Set back-end reset period to 1496 ms
(1) This register can be written only with a non-reserved value. Also, this register can be written once after a reset.

TAS5715
INPUT MULTIPLEXER REGISTER (0x20)

This register controls the modulation scheme (AD or BD mode) as well as the routing of I2S audio to the internal
channels.
Table 21. Input Multiplexer Register (0x20)

(1)
0 0 0 0 0 0 0 0 Reserved

(1)
0 Channel-1 AD mode
1 Channel-1 BD mode
(1)
0 0 0 SDIN-L to channel 1
0 0 1 SDIN-R to channel 1
0 1 0 Reserved
0 1 1 Reserved
1 0 0 Reserved
1 0 1 Reserved
1 1 0 Ground (0) to channel 1
1 1 1 Reserved
0 Channel 2 AD mode
1 Channel 2 BD mode
0 0 0 SDIN-L to channel 2
(1)
0 0 1 SDIN-R to channel 2
0 1 0 Reserved
0 1 1 Reserved
1 0 0 Reserved
1 0 1 Reserved
1 1 0 Ground (0) to channel 2
1 1 1 Reserved

(1)
0 1 1 1 0 1 1 1 Reserved
(1)
0 1 1 1 0 0 1 0 Reserved

TAS5715
RESERVED (0x210x24)
PWM OUTPUT MUX REGISTER (0x25)

This DAP output mux selects which internal PWM channel is output to the external pins. Any channel can be
output to any external output pin.
Bits D21D20: Selects which PWM channel is output to OUT_A

Bits D17D16: Selects which PWM channel is output to OUT_B
Bits D13D12: Selects which PWM channel is output to OUT_C
Bits D09D08: Selects which PWM channel is output to OUT_D
Note that channels are encoded so that channel 1 = 0x00, channel 2 = 0x01, , channel 4 = 0x03.
Table 22. PWM Output Mux Register (0x25)

(1)
0 0 0 0 0 0 0 1 Reserved

0 0 Reserved (1)
(1)
0 0 Multiplex channel 1 to OUT_A
(1)
0 0 Reserved
0 0 Multiplex channel 1 to OUT_B
(1)

(1)
0 0 Reserved
0 0 Multiplex channel 1 to OUT_C
0 1 Multiplex channel 2 to OUT_C (1)
(1)
0 0 Reserved
0 0 Multiplex channel 1 to OUT_D
(1)
0 1 0 0 0 1 0 1 Reserved (1)

TAS5715
DRC AND DC DETECT CONTROL (0x46)
Table 23. DRC AND DC DETECT CONTROL

(1)
0 0 0 0 0 0 0 0 Reserved

(1)
0 0 0 0 0 0 0 0 Reserved

(1)
0 0 0 0 0 Reserved
0 PWM DC detect disabled
1 PWM DC detect enabled
0 EQ CRC detect disabled
1 EQ CRC detect enabled
0 DRC CRC detect disabled
1 DRC CRC detect enabled
(1)
0 0 0 0 Reserved
0 Disable (1-H) complementary low-pass filter generation
(2) (3)
1 Enable (1-H) complementary low-pass filter generation
(2)
0 DRC2 turned OFF
1 DRC2 turned ON
(2)
0 DRC1 turned OFF
1 DRC1 turned ON

(3) If enabled, low-pass filter is generated by (1 high-pass filter output).

TAS5715
BANK SWITCH AND EQ CONTROL (0x50)
Table 24. Bank Switching Command

(1)
0 32 kHz, does not use bank 3
1 32 kHz, uses bank 3
0 Reserved
0 Reserved
(1)
0 44.1/48 kHz, does not use bank 3
1 44.1/48 kHz, uses bank 3
(1)
(1)
1 22.025/24 kHz, uses bank 3
(1)
0 11.025 kHz/12, does not use bank 3
(1)
1 11.025/12 kHz, uses bank 3

(1)
(1)
1 Reserved
(1)
1 Reserved
(1)
(1)
(1)
1 22.025/24 kHz, uses bank 2
(1)
(1)
1 11.025/12 kHz, uses bank 2

(1)
0 Reserved
0 Reserved
(1)
(1)
(1)
1 22.025/24 kHz, uses bank 1
(1)
(1)
1 11.025/12 kHz, uses bank 1

TAS5715
Table 24. Bank Switching Command (continued)

0 EQ ON
1 EQ OFF (bypass BQ 07 of channels 1 and 2)
(2)
0 Reserved
(2)
0 Ignore bank-mapping in bits D31D8.Use default mapping.
1 Use bank-mapping in bits D31D8.
(2) (3)
0 L and R can be written independently.
L and R are ganged for EQ biquads; a write to the left-channel
1 biquad is also written to the right-channel biquad. (0x290x2F is
ganged to 0x300x36. Also, 0x580x5B is ganged to 0x5C0x5F.
0 Enable DRC time constant filter banking
1 Disable DRC time constantfilter banking
(2)
0 0 0 No bank switching. All updates to DAP
0 0 1 Configure bank 1 (32 kHz by default)
0 1 0 Configure bank 2 (44.1/48 kHz by default)
0 1 1 Configure bank 3 (other sample rates by default)
1 0 0 Automatic bank selection
1 0 1 Reserved
1 1 X Reserved

(3) Biquad ganging reduces the number of I2C transactions. This is very useful if the left and right PEQ biquads have the same coefficients.
If ganging is ON (D4 = 1), then any write to left biquad is automatically copied to the corresponding right biquad.

PACKAGE OPTION ADDENDUM
www.ti.com 11-Apr-2013
PACKAGING INFORMATION
Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (C) Top-Side Markings Samples
(1) Drawing Qty (2) (3) (4)
TAS5715PHP ACTIVE HTQFP PHP 48 250 Green (RoHS CU NIPDAU Level-3-260C-168 HR 0 to 85 TAS5715
& no Sb/Br)
TAS5715PHPR ACTIVE HTQFP PHP 48 1000 Green (RoHS CU NIPDAU Level-3-260C-168 HR 0 to 85 TAS5715
& no Sb/Br)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com 9-May-2017
TAPE AND REEL INFORMATION
*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TAS5715PHPR HTQFP PHP 48 1000 330.0 16.4 9.6 9.6 1.5 12.0 16.0 Q2
TAS5715PHPR HTQFP PHP 48 1000 330.0 16.4 9.6 9.6 1.5 12.0 16.0 Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com 9-May-2017
*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TAS5715PHPR HTQFP PHP 48 1000 336.6 336.6 31.8
TAS5715PHPR HTQFP PHP 48 1000 367.0 367.0 38.0
Pack Materials-Page 2
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www.ti.com SLOS645 AUGUST 2010

25-W DIGITAL AUDIO POWER AMPLIFIER WITH EQ AND DRC

SIMPLIFIED APPLICATION DIAGRAM

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MCLK Click and Pop

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Figure 1. Power Stage Functional Block Diagram

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Copyright 2010, Texas Instruments Incorporated

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Volc config reg 0x0E

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(1) TYPE: A = analog; D = 3.3-V digital; P = power/ground/decoupling; I = input; O = output

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PIN FUNCTIONS (continued)

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ABSOLUTE MAXIMUM RATINGS

DISSIPATION RATINGS (1)

RECOMMENDED OPERATING CONDITIONS

PWM OPERATION AT RECOMMENDED OPERATING CONDITIONS

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PLL INPUT PARAMETERS AND EXTERNAL FILTER COMPONENTS

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AC Characteristics (BTL, PBTL)

(1) SNR is calculated relative to 0-dBFS input level.

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SERIAL AUDIO PORTS SLAVE MODE

Figure 2. Slave Mode Serial Data Interface Timing

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I2C SERIAL CONTROL PORT OPERATION

Figure 3. SCL and SDA Timing

Figure 4. Start and Stop Conditions Timing

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RESET TIMING (RESET)

Figure 5. Reset Timing

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TYPICAL CHARACTERISTICS, BTL CONFIGURATION, 8

TOTAL HARMONIC DISTORTION + NOISE TOTAL HARMONIC DISTORTION + NOISE

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TYPICAL CHARACTERISTICS, BTL CONFIGURATION, 8 (continued)

Figure 10. Figure 11.

TOTAL HARMONIC DISTORTION + NOISE TOTAL HARMONIC DISTORTION + NOISE

Figure 12. Figure 13.

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TYPICAL CHARACTERISTICS, BTL CONFIGURATION, 8 (continued)

Figure 16. Figure 17.

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TYPICAL CHARACTERISTICS, BTL CONFIGURATION, 8 (continued)

Figure 18. Figure 19.

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TYPICAL CHARACTERISTICS, BTL CONFIGURATION, 4

Figure 20. Figure 21.