stm8s105c4 956362

STM8S105C4/6 STM8S105K4/6
STM8S105S4/6
Access line, 16 MHz STM8S 8-bit MCU, up to 32 Kbyte Flash,
integrated EEPROM, 10-bit ADC, timers, UART, SPI, IC
Datasheet - production data
Features
Core
16 MHz advanced STM8 core with Harvard
architecture and 3-stage pipeline
LQFP48 (7x7 mm) LQFP44 (10x10 mm) LQFP32 (7x7 mm)
Extended instruction set
Memories

Program memory: up to 32 Kbyte Flash; data

retention 20 years at 55 C after 10 kcycle UFQFPN32 (5x5 mm)

SDIP32 400ml
Data memory: up to 1 Kbyte true data
EEPROM; endurance 300 kcycle 2x16-bit general purpose timer, with 2+3
CAPCOM channels (IC, OC or PWM)
RAM: up to 2 Kbyte
8-bit basic timer with 8-bit prescaler
Clock, reset and supply management Auto wake-up timer
2.95 to 5.5 V operating voltage Window watchdog and independent watchdog
Flexible clock control, 4 master clock sources timers
Low power crystal resonator oscillator
Communication interfaces
External clock input
UART with clock output for synchronous
Internal, user-trimmable 16 MHz RC
operation, SmartCard, IrDA, LIN master mode
Internal low-power 128 kHz RC
SPI interface up to 8 Mbit/s
Clock security system with clock monitor
I2C interface up to 400 kbit/s
Power management:
Low-power modes (wait, active-halt, halt) Analog to digital converter (ADC)
Switch-off peripheral clocks individually
10-bit, 1 LSB ADC with up to 10 multiplexed
Permanently active, low-consumption power- channels, scan mode and analog watchdog
on and power-down reset
I/Os
Interrupt management
Up to 38 I/Os on a 48-pin package including
Nested interrupt controller with 32 interrupts 16 high sink outputs
Up to 37 external interrupts on 6 vectors Highly robust I/O design, immune against
current injection
Timers
Advanced control timer: 16-bit, 4 CAPCOM Unique ID
channels, 3 complementary outputs, dead-time 96-bit unique key for each device
insertion and flexible synchronization
September 2015 DocID14771 Rev 15 1/121

This is information on a product in full production. www.st.com
Contents STM8S105x4/6
Contents
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4 Product overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.1 Central processing unit STM8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.2 Single wire interface module (SWIM) and debug module (DM) . . . . . . . . 14
4.3 Interrupt controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.4 Flash program and data EEPROM memory . . . . . . . . . . . . . . . . . . . . . . . 14
4.5 Clock controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.6 Power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.7 Watchdog timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.8 Auto wakeup counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.9 Beeper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.10 TIM1 - 16-bit advanced control timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.11 TIM2, TIM3 - 16-bit general purpose timers . . . . . . . . . . . . . . . . . . . . . . . 18
4.12 TIM4 - 8-bit basic timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.13 Analog-to-digital converter (ADC1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.14 Communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.14.1 UART2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.14.2 SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.14.3 I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5 Pinout and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

5.1 Alternate function remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
6 Memory and register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

6.1 Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
6.2 Register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
6.2.1 I/O port hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
6.2.2 General hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
2/121 DocID14771 Rev 15

STM8S105x4/6 Contents
6.2.3 CPU/SWIM/debug module/interrupt controller registers . . . . . . . . . . . . 42
7 Interrupt vector mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
8 Option byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
8.1 Alternate function remapping bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
9 Unique ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
10 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
10.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
10.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
10.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
10.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
10.1.4 Typical current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
10.1.5 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
10.1.6 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
10.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
10.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
10.3.1 VCAP external capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
10.3.2 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
10.3.3 External clock sources and timing characteristics . . . . . . . . . . . . . . . . . 66
10.3.4 Internal clock sources and timing characteristics . . . . . . . . . . . . . . . . . 69
10.3.5 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
10.3.6 I/O port pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
10.3.7 Typical output level curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
10.3.8 Reset pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
10.3.9 SPI serial peripheral interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
10.3.10 I2C interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
10.3.11 10-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
10.3.12 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
11 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
11.1 LQFP48 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
11.4 UFQFPN32 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
DocID14771 Rev 15 3/121

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Contents STM8S105x4/6
11.5 SDIP32 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
12 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

12.1 Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
12.2 Selecting the product temperature range . . . . . . . . . . . . . . . . . . . . . . . . 107
13 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

13.1 STM8S105 FASTROM microcontroller option list . . . . . . . . . . . . . . . . . 109
14 STM8 development tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

14.1 Emulation and in-circuit debugging tools . . . . . . . . . . . . . . . . . . . . . . . . .113
14.1.1 STice key features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
14.2 Software tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114
14.2.1 STM8 toolset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
14.2.2 C and assembly toolchains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
14.3 Programming tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115
15 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
4/121 DocID14771 Rev 15

STM8S105x4/6 List of tables
List of tables
Table 1. STM8S105x4/6 access line features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Table 2. Peripheral clock gating bit assignments in CLK_PCKENR1/2 registers . . . . . . . . . . . . . . . 16
Table 3. TIM timer features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 4. Legend/abbreviations for pin description tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 5. STM8S105x4/6 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 6. Flash, data EEPROM and RAM boundary address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 7. I/O port hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 8. General hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 9. CPU/SWIM/debug module/interrupt controller registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 10. Interrupt mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Table 11. Option byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 12. Option byte description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Table 13. Alternate function remapping bits [7:0] of OPT2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Table 14. Unique ID registers (96 bits) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Table 15. Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Table 16. Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Table 17. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Table 18. General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Table 19. Operating conditions at power-up/power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Table 20. Total current consumption with code execution in run mode at VDD = 5 V. . . . . . . . . . . . . 57
Table 21. Total current consumption with code execution in run mode at VDD = 3.3 V . . . . . . . . . . . 58
Table 22. Total current consumption in wait mode at VDD = 5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Table 23. Total current consumption in wait mode at VDD = 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Table 24. Total current consumption in active halt mode at VDD = 5 V . . . . . . . . . . . . . . . . . . . . . . . 59
Table 25. Total current consumption in active halt mode at VDD = 3.3 V . . . . . . . . . . . . . . . . . . . . . . 60
Table 26. Total current consumption in halt mode at VDD = 5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Table 27. Total current consumption in halt mode at VDD = 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Table 28. Wakeup times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Table 29. Total current consumption and timing in forced reset state . . . . . . . . . . . . . . . . . . . . . . . . 61
Table 30. Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Table 31. HSE user external clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Table 32. HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Table 33. HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Table 34. LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Table 35. RAM and hardware registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Table 36. Flash program memory/data EEPROM memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Table 37. I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Table 38. Output driving current (standard ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Table 39. Output driving current (true open drain ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Table 40. Output driving current (high sink ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Table 41. NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Table 42. SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Table 43. I2C characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Table 44. ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Table 45. ADC accuracy with RAIN< 10 k, VDDA = 5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Table 46. ADC accuracy with RAIN< 10 k, VDDA = 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Table 47. EMS data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Table 48. EMI data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
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6
List of tables STM8S105x4/6
Table 49. ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

Table 50. Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Table 51. LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package
mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Table 54. UFQFPN32 - 32-pin, 5x5 mm, 0.5 mm pitch ultra thin fine pitch quad flat
package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Table 55. SDIP32 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Table 56. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Table 57. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
6/121 DocID14771 Rev 15

STM8S105x4/6 List of figures
List of figures
Figure 1. STM8S105x4/6 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Figure 2. Flash memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 3. LQFP48 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 4. LQFP44 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 5. UFQFPN32/LQFP32 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 6. SDIP32 pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 7. Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 8. Supply current measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Figure 9. Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Figure 10. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Figure 11. fCPUmax versus VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Figure 12. External capacitor CEXT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Figure 13. Typ IDD(RUN) vs. VDD HSE user external clock, fCPU = 16 MHz . . . . . . . . . . . . . . . . . . . . 62
Figure 14. Typ IDD(RUN) vs. fCPU HSE user external clock, VDD = 5 V . . . . . . . . . . . . . . . . . . . . . . . . 63
Figure 15. Typ IDD(RUN) vs. VDD HSI RC osc, fCPU = 16 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Figure 16. Typ IDD(WFI) vs. VDD HSE external clock, fCPU = 16 MHz . . . . . . . . . . . . . . . . . . . . . . . . . 64
Figure 17. Typ IDD(WFI) vs. fCPU HSE external clock, VDD = 5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Figure 18. Typ IDD(WFI) vs. VDD HSI RC osc., fCPU = 16 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Figure 19. HSE external clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Figure 20. HSE oscillator circuit diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Figure 21. Typical HSI accuracy @ VDD = 5 V vs 5 temperatures. . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Figure 22. Typical HSI frequency variation vs VDD @ 4 temperatures . . . . . . . . . . . . . . . . . . . . . . . . 70
Figure 23. Typical LSI frequency variation vs VDD@ 4 temperatures . . . . . . . . . . . . . . . . . . . . . . . . . 71
Figure 24. Typical VIL and VIH vs VDD @ 4 temperatures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Figure 25. Typical pull-up current vs VDD @ 4 temperatures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Figure 26. Typical pull-up resistance vs VDD @ 4 temperatures . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Figure 27. Typ. VOL @ VDD = 3.3 V (standard ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Figure 28. Typ. VOL @ VDD = 5.0 V (standard ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Figure 29. Typ. VOL @ VDD = 3.3 V (true open drain ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Figure 30. Typ. VOL @ VDD = 5.0 V (true open drain ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Figure 31. Typ. VOL @ VDD = 3.3 V (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Figure 32. Typ. VOL @ VDD = 5.0 V (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Figure 33. Typ. VDD - VOH @ VDD = 3.3 V (standard ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Figure 34. Typ. VDD - VOH @ VDD = 5.0 V (standard ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Figure 35. Typ. VDD - VOH @ VDD = 3.3 V (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Figure 36. Typ. VDD - VOH @ VDD = 5.0 V (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Figure 37. Typical NRST VIL and VIH vs VDD @ 4 temperatures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Figure 38. Typical NRST pull-up resistance RPU vs VDD @ 4 temperatures . . . . . . . . . . . . . . . . . . . . 79
Figure 39. Typical NRST pull-up current Ipu vs VDD @ 4 temperatures. . . . . . . . . . . . . . . . . . . . . . . . 79
Figure 40. Recommended reset pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Figure 41. SPI timing diagram where slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Figure 42. SPI timing diagram where slave mode and CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Figure 43. SPI timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Figure 44. Typical application with I2C bus and timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Figure 45. ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Figure 46. Typical application with ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Figure 47. LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package outline . . . . . . . . . . . . . . . . . . . 91
Figure 48. LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package
DocID14771 Rev 15 7/121

8
List of figures STM8S105x4/6
recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Figure 49. LQFP48 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Figure 50. LQFP44 - 44-pin, 10 x 10 mm low-profile quad flat package outline . . . . . . . . . . . . . . . . . 94
recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Figure 52. LQFP44 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Figure 53. LQFP32 - 32-pin, 7 x 7 mm low-profile quad flat package outline . . . . . . . . . . . . . . . . . . . 98
recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Figure 55. LQFP32 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Figure 56. UFQFPN32 - 32-pin, 5x5 mm, 0.5 mm pitch ultra thin fine pitch quad flat
package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Figure 57. UFQFPN32 - 32-pin, 5 x5 mm, 0.5 mm pitch ultra thin fine pitch quad flat
package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Figure 58. UFQFPN32 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Figure 59. SDIP32 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Figure 60. SDIP32 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Figure 61. STM8S105x4/6 access line ordering information scheme(1) . . . . . . . . . . . . . . . . . . . . . . 108
8/121 DocID14771 Rev 15

STM8S105x4/6 Introduction
1 Introduction
This datasheet contains the description of the device features, pinout, electrical
characteristics, mechanical data and ordering information.
For complete information on the STM8S microcontroller memory, registers and
peripherals, please refer to the STM8S microcontroller family reference manual
(RM0016).
For information on programming, erasing and protection of the internal Flash memory
please refer to the STM8S Flash programming manual (PM0051).
For information on the debug and SWIM (single wire interface module) refer to the
STM8 SWIM communication protocol and debug module user manual (UM0470).
For information on the STM8 core, please refer to the STM8 CPU programming manual
(PM0044).
DocID14771 Rev 15 9/121

21
Description STM8S105x4/6
2 Description
The STM8S105x4/6 access line 8-bit microcontrollers offer from 16 to 32 Kbyte Flash
program memory, plus integrated true data EEPROM. The STM8S microcontroller family
reference manual (RM0016) refers to devices in this family as medium-density. All devices
of the STM8S105x4/6 access line provide the following benefits: reduced system cost,
performance and robustness, short development cycles, and product longevity.
The system cost is reduced thanks to an integrated true data EEPROM for up to 300 k
write/erase cycles and a high system integration level with internal clock oscillators,
watchdog and brown-out reset.
Device performance is ensured by a 16 MHz CPU clock frequency and enhanced
characteristics which include robust I/O, independent watchdogs (with a separate clock
source), and a clock security system.
Short development cycles are guaranteed due to application scalability across common
family product architecture with compatible pinout, memory map and modular peripherals.
Product longevity is ensured in the STM8S family thanks to their advanced core which is
made in a state-of-the-art technology for applications with 2.95 V to 5.5 V operating supply.
Full documentation is offered as well as a wide choice of development tools.
10/121 DocID14771 Rev 15

STM8S105x4/6 Description
Table 1. STM8S105x4/6 access line features

Device STM8S105C6 STM8S105C4 STM8S105S6 STM8S105S4 STM8S105K6 STM8S105K4
Pin count 48 48 44 44 32 32
Maximum
number of 38 38 34 34 25 25
GPIOs
Ext. Interrupt
35 35 31 31 23 23
pins
Timer
CAPCOM 9 9 8 8 8 8
channels
Timer
complementar 3 3 3 3 3 3
y outputs
A/D Converter
10 10 9 9 7 7
channels
High sink I/Os 16 16 15 15 12 12
Medium
density Flash
32K 16K 32K 16K 32K 16K
Program
memory (byte)
Data
EEPROM 1024 1024 1024 1024 1024 1024
(bytes)
RAM (bytes) 2K 2K 2K 2K 2K 2K
Advanced control timer (TIM1), General-purpose timers (TIM2 and TIM3), Basic timer (TIM4) SPI,
Peripheral set
I2C, UART, Window WDG, Independent WDG, ADC
DocID14771 Rev 15 11/121

21
Block diagram STM8S105x4/6
3 Block diagram
Figure 1. STM8S105x4/6 block diagram
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12/121 DocID14771 Rev 15

STM8S105x4/6 Product overview
4 Product overview
The following section provides an overview of the basic features of the device functional
modules and peripherals.
For more detailed information please refer to the corresponding family reference manual
(RM0016).
4.1 Central processing unit STM8

The 8-bit STM8 core is designed for code efficiency and performance.
It contains 6 internal registers which are directly addressable in each execution context, 20
addressing modes including indexed indirect and relative addressing and 80 instructions.
Architecture and registers

Harvard architecture,
3-stage pipeline,
32-bit wide program memory bus - single cycle fetching for most instructions,
X and Y 16-bit index registers - enabling indexed addressing modes with or without
offset and read-modify-write type data manipulations,
8-bit accumulator,
24-bit program counter - 16-Mbyte linear memory space,
16-bit stack pointer - access to a 64 K-level stack,
8-bit condition code register - 7 condition flags for the result of the last instruction.
Addressing
20 addressing modes,
Indexed indirect addressing mode for look-up tables located anywhere in the address
space,
Stack pointer relative addressing mode for local variables and parameter passing.
Instruction set
80 instructions with 2-byte average instruction size,
Standard data movement and logic/arithmetic functions,
8-bit by 8-bit multiplication,
16-bit by 8-bit and 16-bit by 16-bit division,
Bit manipulation,
Data transfer between stack and accumulator (push/pop) with direct stack access,
Data transfer using the X and Y registers or direct memory-to-memory transfers.
DocID14771 Rev 15 13/121

21
Product overview STM8S105x4/6
4.2 Single wire interface module (SWIM) and debug module (DM)
The single wire interface module and debug module permits non-intrusive, real-time in-
circuit debugging and fast memory programming.
SWIM
Single wire interface module for direct access to the debug module and memory
programming. The interface can be activated in all device operation modes. The maximum
data transmission speed is 145 bytes/ms.
Debug module
The non-intrusive debugging module features a performance close to a full-featured
emulator. Beside memory and peripherals, also CPU operation can be monitored in real-
time by means of shadow registers.
R/W to RAM and peripheral registers in real-time
R/W access to all resources by stalling the CPU
Breakpoints on all program-memory instructions (software breakpoints)
Two advanced breakpoints, 23 predefined configurations
4.3 Interrupt controller

Nested interrupts with three software priority levels,
32 interrupt vectors with hardware priority,
Up to 37 external interrupts on 6 vectors including TLI,
Trap and reset interrupts
4.4 Flash program and data EEPROM memory

Up to 32 Kbyte of Flash program single voltage Flash memory,
Up to 1 Kbyte true data EEPROM,
Read while write: writing in data memory possible while executing code in program
memory,
User option byte area.
Write protection (WP)

Write protection of Flash program memory and data EEPROM is provided to avoid
unintentional overwriting of memory that could result from a user software malfunction.
There are two levels of write protection. The first level is known as MASS (memory access
security system). MASS is always enabled and protects the main Flash program memory,
data EEPROM and option bytes.
To perform in-application programming (IAP), this write protection can be removed by
writing a MASS key sequence in a control register. This allows the application to write to
data EEPROM, modify the contents of main program memory or the device option bytes.
A second level of write protection, can be enabled to further protect a specific area of
memory known as UBC (user boot code). Refer to the figure below.
14/121 DocID14771 Rev 15

The size of the UBC is programmable through the UBC option byte, in increments of 1 page
(512 byte) by programming the UBC option byte in ICP mode.
This divides the program memory into two areas:
Main program memory: up to 32 Kbyte minus UBC
User-specific boot code (UBC): Configurable up to 32 Kbyte
The UBC area remains write-protected during in-application programming. This means that
the MASS keys do not unlock the UBC area. It protects the memory used to store the boot
program, specific code libraries, reset and interrupt vectors, the reset routine and usually
the IAP and communication routines.
Figure 2. Flash memory organization
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Read-out protection (ROP)

The read-out protection blocks reading and writing the Flash program memory and data
EEPROM memory in ICP mode (and debug mode). Once the read-out protection is
activated, any attempt to toggle its status triggers a global erase of the program and data
memory. Even if no protection can be considered as totally unbreakable, the feature
provides a very high level of protection for a general purpose microcontroller.
DocID14771 Rev 15 15/121

21
4.5 Clock controller

The clock controller distributes the system clock (fMASTER) coming from different
oscillators to the core and the peripherals. It also manages clock gating for low power
modes and ensures clock robustness.
Features
Clock prescaler: to get the best compromise between speed and current consumption
the clock frequency to the CPU and peripherals can be adjusted by a programmable
prescaler.
Safe clock switching: clock sources can be changed safely on the fly in run mode
through a configuration register. The clock signal is not switched until the new clock
source is ready. The design guarantees glitch-free switching.
Clock management: to reduce power consumption, the clock controller can stop the
clock to the core, individual peripherals or memory.
Master clock sources: four different clock sources can be used to drive the master
clock:
1-16 MHz high-speed external crystal (HSE)
Up to 16 MHz high-speed user-external clock (HSE user-ext)
16 MHz high-speed internal RC oscillator (HSI)
128 kHz low-speed internal RC (LSI)
Startup clock: After reset, the microcontroller restarts by default with an internal 2 MHz
clock (HSI/8). The prescaler ratio and clock source can be changed by the application
program as soon as the code execution starts.
Clock security system (CSS): This feature can be enabled by software. If an HSE
clock failure occurs, the internal RC (16 MHz/8) is automatically selected by the CSS
and an interrupt can optionally be generated.
Configurable main clock output (CCO): This outputs an external clock for use by the
application.
Table 2. Peripheral clock gating bit assignments in CLK_PCKENR1/2 registers

Peripheral Peripheral Peripheral Peripheral
Bit Bit Bit Bit
clock clock clock clock
PCKEN17 TIM1 PCKEN13 UART2 PCKEN27 Reserved PCKEN23 ADC

PCKEN16 TIM3 PCKEN12 Reserved PCKEN26 Reserved PCKEN22 AWU
PCKEN15 TIM2 PCKEN11 SPI PCKEN25 Reserved PCKEN21 Reserved
PCKEN14 TIM4 PCKEN10 I2C PCKEN24 Reserved PCKEN20 Reserved
16/121 DocID14771 Rev 15

4.6 Power management

For efficient power management, the application can be put in one of four different low-
power modes. You can configure each mode to obtain the best compromise between lowest
power consumption, fastest start-up time and available wakeup sources.
Wait mode: In this mode, the CPU is stopped, but peripherals are kept running. The
wakeup is performed by an internal or external interrupt or reset.
Active halt mode with regulator on: In this mode, the CPU and peripheral clocks are
stopped. An internal wakeup is generated at programmable intervals by the auto wake
up unit (AWU). The main voltage regulator is kept powered on, so current consumption
is higher than in active halt mode with regulator off, but the wakeup time is faster.
Wakeup is triggered by the internal AWU interrupt, external interrupt or reset.
Active halt mode with regulator off: This mode is the same as active halt with
regulator on, except that the main voltage regulator is powered off, so the wake up time
is slower.
Halt mode: In this mode the microcontroller uses the least power. The CPU and
peripheral clocks are stopped, the main voltage regulator is powered off. Wakeup is
triggered by external event or reset.
4.7 Watchdog timers

The watchdog system is based on two independent timers providing maximum security to
the applications.
Activation of the watchdog timers is controlled by option bytes or by software. Once
activated, the watchdogs cannot be disabled by the user program without performing a
reset.
Window watchdog timer

The window watchdog is used to detect the occurrence of a software fault, usually
generated by external interferences or by unexpected logical conditions, which cause the
application program to abandon its normal sequence.
The window function can be used to trim the watchdog behavior to match the application
perfectly.
The application software must refresh the counter before time-out and during a limited time
window.
A reset is generated in two situations:
1. Timeout: At 16 MHz CPU clock the time-out period can be adjusted between 75 s up
to 64 ms.
2. Refresh out of window: The downcounter is refreshed before its value is lower than the
one stored in the window register.
Independent watchdog timer

The independent watchdog peripheral can be used to resolve processor malfunctions due to
hardware or software failures.
It is clocked by the 128 kHz LSI internal RC clock source, and thus stays active even in case
of a CPU clock failure
DocID14771 Rev 15 17/121

21
The IWDG time base spans from 60 s to 1 s.
4.8 Auto wakeup counter

Used for auto wakeup from active halt mode,
Clock source: Internal 128 kHz internal low frequency RC oscillator or external clock,
LSI clock can be internally connected to TIM1 input capture channel 1 for calibration.
4.9 Beeper
The beeper function outputs a signal on the BEEP pin for sound generation. The signal is in
the range of 1, 2 or 4 kHz.
The beeper output port is only available through the alternate function remap option bit
AFR7.
4.10 TIM1 - 16-bit advanced control timer

This is a high-end timer designed for a wide range of control applications. With its
complementary outputs, dead-time control and center-aligned PWM capability, the field of
applications is extended to motor control, lighting and half-bridge driver
16-bit up, down and up/down autoreload counter with 16-bit prescaler
Four independent capture/compare channels (CAPCOM) configurable as input
capture, output compare, PWM generation (edge and center aligned mode) and single
pulse mode output
Synchronization module to control the timer with external signals
Break input to force the timer outputs into a defined state
Three complementary outputs with adjustable dead time
Encoder mode
Interrupt sources: 3 x input capture/output compare, 1 x overflow/update, 1 x break
4.11 TIM2, TIM3 - 16-bit general purpose timers

16-bit auto reload (AR) up-counter
15-bit prescaler adjustable to fixed power of 2 ratios 132768
Timers with 3 or 2 individually configurable capture/compare channels
PWM mode
Interrupt sources: 2 or 3 x input capture/output compare, 1 x overflow/update
18/121 DocID14771 Rev 15

4.12 TIM4 - 8-bit basic timer

8-bit auto reload, adjustable prescaler ratio to any power of 2 from 1 to 128
Clock source: CPU clock
Interrupt source: 1 x overflow/update
Table 3. TIM timer features

Timer
Counter Counting CAPCOM Complementary Ext.
Timer Prescaler synchronization/
size (bits) mode channels outputs trigger
chaining
Any integer
TIM1 16 from 1 to Up/down 4 3 Yes
65536
Any power
TIM2 16 of 2 from 1 Up 3 0 No
to 32768
No
Any power
to 32768
Any power
to 128
4.13 Analog-to-digital converter (ADC1)

The STM8S105x4/6 products contain a 10-bit successive approximation A/D converter
(ADC1) with up to 10 multiplexed input channels and the following main features:
Input voltage range: 0 to VDD
Conversion time: 14 clock cycles
Single and continuous and buffered continuous conversion modes
Buffer size (n x 10 bits) where n = number of input channels
Scan mode for single and continuous conversion of a sequence of channels
Analog watchdog capability with programmable upper and lower thresholds
Analog watchdog interrupt
External trigger input
Trigger from TIM1 TRGO
End of conversion (EOC) interrupt
Note: Additional AIN12 analog input is not selectable in ADC scan mode or with analog watchdog.
Values converted from AIN12 are stored only into the ADC_DRH/ADC_DRL registers.
DocID14771 Rev 15 19/121

21
4.14 Communication interfaces

The following communication interfaces are implemented:
UART1: Full feature UART, synchronous mode, SPI master mode, Smartcard mode,
IrDA mode, single wire mode, LIN2.1 master capability
SPI: Full and half-duplex, 8 Mbit/s
IC: Up to 400 kbit/s
4.14.1 UART2
Main features
1 Mbit/s full duplex SCI
SPI emulation
High precision baud rate generator
Smartcard emulation
IrDA SIR encoder decoder
LIN master mode
LIN slave mode
Asynchronous communication (UART mode)

Full duplex communication - NRZ standard format (mark/space)
Programmable transmit and receive baud rates up to 1 Mbit/s (fCPU/16) and capable
of following any standard baud rate regardless of the input frequency
Separate enable bits for transmitter and receiver
Two receiver wakeup modes:
Address bit (MSB)
Idle line (interrupt)
Transmission error detection with interrupt generation
Parity control
Synchronous communication
Full duplex synchronous transfers
SPI master operation
8-bit data communication
Maximum speed: 1 Mbit/s at 16 MHz (fCPU/16)
LIN master mode

Emission: Generates 13-bit synch. break frame
Reception: Detects 11-bit break frame
20/121 DocID14771 Rev 15

LIN slave mode

Autonomous header handling - one single interrupt per valid message header
Automatic baud rate synchronization - maximum tolerated initial clock deviation 15%
Synch delimiter checking
11-bit LIN synch break detection - break detection always active
Parity check on the LIN identifier field
LIN error management
Hot plugging support
4.14.2 SPI
Maximum speed: 8 Mbit/s (fMASTER/2) both for master and slave
Full duplex synchronous transfers
Simplex synchronous transfers on two lines with a possible bidirectional data line
Master or slave operation - selectable by hardware or software
CRC calculation
1 byte Tx and Rx buffer
Slave/master selection input pin
4.14.3 I2C
IC master features:
Clock generation
Start and stop generation
IC slave features:
Programmable I2C address detection
Stop bit detection
Generation and detection of 7-bit/10-bit addressing and general call
Supports different communication speeds:
Standard speed (up to 100 kHz)
Fast speed (up to 400 kHz)
DocID14771 Rev 15 21/121

21
Pinout and pin description STM8S105x4/6
5 Pinout and pin description
Table 4. Legend/abbreviations for pin description tables

Type I= Input, O = Output, S = Power supply
Input CM = CMOS
Level
Output HS = High sink
O1 = Slow (up to 2 MHz)
O2 = Fast (up to 10 MHz)
Output speed
O3 = Fast/slow programmability with slow as default state after reset
O4 = Fast/slow programmability with fast as default state after reset
float = floating,
Input
wpu = weak pull-up
Port and control
configuration T = True open drain,
Output OD = Open drain,
PP = Push pull
Bold X (pin state after internal reset release).
Reset state Unless otherwise specified, the pin state is the same during the reset
phase and after the internal reset release.
22/121 DocID14771 Rev 15

STM8S105x4/6 Pinout and pin description
Figure 3. LQFP48 pinout
3'+67,0B&+>7,0B%.,1@>&/.B&&2@
3'+67,0B&+>7,0B&+@
3'+67,0B&+>$'&B(75@
3'+67,0B&+>%((3@
3'7/,>7,0B&+@
3(+6&/.B&&2
3(7,&B6'$$
3(7,&B6&/
3'+66:,0
3'8$57B5;
3(7,0B%.,1
3'8$57B7;

1567 3*
26&,13$ 3*
26&2873$ 3&+663,B0,62
966,2B 3&+663,B026,
966 9'',2B
9&$3 966,2B
9'' 3&+663,B6&.
9'',2B 3&+67,0B&+
>7,0B&+@7,0B&+3$ 3&+67,0B&+
+63$ 3&+67,0B&+
+63$ 3&+67,0B&+8$57B&.
+63$ 3(63,B166

9''$
966$
$,13%
$,13%
$,13(
$,13(
>,&B6'$@$,13%
>,&B6&/@$,13%
>7,0B(75@$,13%
>7,0B&+1@$,13%
>7,0B&+1@$,13%
>7,0B&+1@$,13%
069
1. (HS) high sink capability.

2. (T) True open drain (P-buffer and protection diode to VDD not implemented).
3. [ ] alternate function remapping option (if the same alternate function is shown twice, it indicates an
exclusive choice not a duplication of the function).
DocID14771 Rev 15 23/121

30
Figure 4. LQFP44 pinout
3'+67,0B&+>7,0B%.,1@>&/.B&&2@
3'+67,0B&+>$'&B(75@
3'+67,0B&+>7,0B&+@
3'+67,0B&+>%((3@
3'7/,>7,0B&+@
3(+6&/.B&&2
3(7,&B6'$
3(7,&B6&/
3'+66:,0
3'8$57B5;
3'8$57B7;

1567 3*
26&,13$ 3*
26&2873$ 3&+663,B0,62
966,2B 3&+663,B026,
966 9'',2B
9&$3 966,2B
9'' 3&+663,B6&.
9'',2B 3&+67,0B&+
+63$ 3&+67,0B&+
+63$ 3&+67,0B&+8$57B&.
+63$ 3(63,B166

9''$
966$
$,13%
$,13%
$,13(
>,&B6'$@$,13%
>,&B6&/@$,13%
>7,0B(75@$,13%
>7,0B&+1@$,13%
>7,0B&+1@$,13%
>7,0B&+1@$,13%
069

24/121 DocID14771 Rev 15

Figure 5. UFQFPN32/LQFP32 pinout
3'+67,0B&+>7,0B%.,1@>&/.B&&2@
3'+67,0B&+>7,0B&+@
3'+67,0B&+>$'&B(75@
3'+67,0B&+>%((3@
3'7/,>7,0B&+@
3'8$57B5;
3'8$57B7;
3'+66:,0

1567 3&+663,B0,62
26&,13$ 3&+663,B026,
26&2873$ 3&+663,B6&.
966 3&+67,0B&+
9&$3 3&+67,0B&+
9'' 3&+67,0B&+
9'',2 3&+67,0B&+8$57B&.
$,13) 3(63,B166

9''$
966$
>,&B6'$@$,13%
>,&B6&/@$,13%
>7,0B(75@$,13%
>7,0B&+1@$,13%
>7,0B&+1@$,13%
>7,0B&+1@$,13%
069

DocID14771 Rev 15 25/121

30
Figure 6. SDIP32 pinout
$'&B(757,0B&++63' 3'+67,0B&+>7,0B&+@
>%((3@7,0B&++63' 3'+66:,0
8$57B7;3' 3'+67,0B&+>7,0B%.,1@>&/.B&&2@

8$57B5;3' 3&+663,B0,62
>7,0B&+@7/,3' 3&+663,B026,
1567 3&+663,B6&.
26&,13$ 3&+67,0B&+
26&2873$ 3&+67,0B&+
966 3&+67,0B&+
9&$3 3&+67,0B&+8$57B&.

9'' 3(63,B166
9'',2 3%$,1>7,0B&+1@
$,13) 3%$,1>7,0B&+1@
9''$ 3%$,1>7,0B&+1@
966$ 3%$,1>7,0B(75@
>,&B6'$@$,13% 3%$,1>,&B6&/@
069

Table 5. STM8S105x4/6 pin description

Pin number Input Output
Alternate
LQFP32/UFQFPN32
Main function
Ext. interrupt
Default
High sink
function after
Floating
LQFP48
LQFP44
SDIP32
Pin name Type alternate

Speed
wpu
(after remap
OD
PP
function
reset) [option
bit]
1 1 1 6 NRST I/O - X - - - - Reset -

Resonato
2 2 2 7 PA1/ OSC IN I/O X X - - O1 X X Port A1 r/ crystal
in
Resonato
PA2/ OSC
3 3 3 8 I/O X X - - O1 X X Port A1 r/ crystal
OUT
in
4 4 - - VSSIO_1 S - - - - - - - I/O ground -
5 5 4 9 VSS S - - - - - - - Digital ground -
1.8 V regulator
6 6 5 10 VCAP S - - - - - - - -
capacitor
26/121 DocID14771 Rev 15

Table 5. STM8S105x4/6 pin description (continued)

Alternate
LQFP32/UFQFPN32
Main function
Ext. interrupt
Default
High sink
function after
Floating
LQFP48
LQFP44
SDIP32
Speed
wpu
(after remap
OD
PP
function
reset) [option
bit]
7 7 6 11 VDD S - - - - - - - Digital power supply -

8 8 7 12 VDDIO_1 S - - - - - - - I/O power supply -
TIM3_
PA3/ TIM2_CH3 Timer 2 -
9 - - - I/O X X X - O1 X X Port A3 CH1
[TIM3_CH1] channel 3
[AFR1]
10 9 - - PA4 I/O X X X HS O3 X X Port A4 - -
Analog
- - 8 13 PF4/ AIN12(1) I/O X X - - O1 X X Port F4 input -
12(2)
13 12 9 14 VDDA S - - - - - - - Analog power supply -
14 13 10 15 VSSA S - - - - - - - Analog ground -
Analog
15 14 - - PB7/ AIN7 I/O X X X - O1 X X Port B7 -
input 7
Analog
16 15 - - PB6/ AIN6 I/O X X X - O1 X X Port B6 -
input 6
I
PB5/ AIN5 Analog
17 16 11 16 I/O X X X - O1 X X Port B5 2C_SDA
[I2C_ SDA] input 5
[AFR6]
PB4/ AIN4 Analog I2C_SCL
18 17 12 17 I/O X X X - O1 X X Port B4
[I2C_SCL] input 4 [AFR6]
PB3/ AIN3 Analog TIM1_ET
19 18 13 18 I/O X X X - O1 X X Port B3
[TIM1_ETR] input 3 R [AFR5]
TIM1_CH
PB2/ AIN2 Analog
20 19 14 19 I/O X X X - O1 X X Port B2 3N
[TIM1_CH3N] input 2
[AFR5]
TIM1_CH
PB1/ AIN1 Analog
21 20 15 20 I/O X X X - O1 X X Port B1 2N
[TIM1_CH2N] input 1
[AFR5]
TIM1_CH
PB0/ AIN0 Analog
22 21 16 21 I/O X X X - O1 X X Port B0 1N
[TIM1_CH1N] input 0
[AFR5]
Analog
23 - - - PE7/ AIN8 I/O X X X - O1 X X Port E7 -
input 8
DocID14771 Rev 15 27/121

30

Alternate
LQFP32/UFQFPN32
Main function
Ext. interrupt
Default
High sink
function after
Floating
LQFP48
LQFP44
SDIP32
Speed
wpu
(after remap
OD
PP
function
reset) [option
bit]
Analog
24 22 - - PE6/ AIN9 I/O X X X - O1 X X Port E6 -
input 9(3)
SPI
master/
25 23 17 22 PE5/ SPI_NSS I/O X X X - O1 X X Port E5 -
slave
select
Timer 1 -
PC1/ channel
26 24 18 23 TIM1_CH1/ I/O X X X HS O3 X X Port C1 1/ UART2 -
UART2_CK synchron
ous clock
PC2/ Timer 1-
27 25 19 24 I/O X X X HS O3 X X Port C2 -
TIM1_CH2 channel 2
PC3/ Timer 1 -
28 26 20 25 I/O X X X HS O3 X X Port C3 -
TIM1_CH3 channel 3
PC4/ Timer 1 -
29 - 21 26 I/O X X X HS O3 X X Port C4 -
TIM1_CH4 channel 4
30 27 22 27 PC5/ SPI_SCK I/O X X HS O3 X X Port C5 SPI clock -
31 28 - - VSSIO_2 S - - - - - - - I/O ground -
32 29 - - VDDIO_2 S - - - - - - - I/O power supply -
SPI
master
33 30 23 28 PC6/ SPI_MOSI I/O X X X HS O3 X X Port C6 -
out/slave
in
SPI
PC7/ SPI_
34 31 24 29 I/O X X X HS O3 X X Port C7 master in/ -
MISO
slave out
35 32 - - PG0 I/O X X - - O1 X X Port G0 - -
36 33 - - PG1 I/O X X - - O1 X X Port G1 - -
Timer 1 -
PE3/
37 - - - I/O X X X - O1 X X Port E3 break -
TIM1_BKIN
input
T
38 34 - - PE2/ I 2C_ SDA I/O X - X - O1 (4) - Port E2 I 2C data -
T
39 35 - - PE1/ I2C_ SCL I/O X - X - O1 (4) - Port E1 I 2C clock -
28/121 DocID14771 Rev 15


Alternate
LQFP32/UFQFPN32
Main function
Ext. interrupt
Default
High sink
function after
Floating
LQFP48
LQFP44
SDIP32
Speed
wpu
(after remap
OD
PP
function
reset) [option
bit]
Configura
40 36 - - PE0/ CLK_CCO I/O X X X HS O3 X X Port E0 ble clock -
output
TIM1_BK
PD0/
IN
TIM3_CH2 Timer 3 -
41 37 25 30 I/O X X X HS O3 X X Port D0 [AFR3]/
[TIM1_BKIN] channel 2
CLK_CC
[CLK_CCO]
O [AFR2]
SWIM
42 38 26 31 PD1/ SWIM(5) I/O X X X X HS O4 X Port D1 data -
interface
PD2/
Timer 3 - TIM2_CH
43 39 27 32 TIM3_CH1 I/O X X X HS O3 X X Port D2
channel 1 3 [AFR1]
[TIM2_CH3]
PD3/
Timer 2 - ADC_ET
44 40 28 1 TIM2_CH2 I/O X X X HS O3 X X Port D3
channel 2 R [AFR0]
[ADC_ETR]
PD4/ BEEP
Timer 2 -
45 41 29 2 TIM2_CH1 I/O X X X HS O3 X X Port D4 output
channel 1
[BEEP] [AFR7]
UART2
PD5/
46 42 30 3 I/O X X X - O1 X X Port D5 data -
UART2_TX
transmit
UART2
PD6/
47 43 31 4 I/O X X X - O1 X X Port D6 data -
UART2_RX
receive
PD7/ TLI Top level TIM1_CH
48 44 32 5 I/O X X X - O1 X X Port D7
[TIM1_CH4 interrupt 4 [AFR4]
1. A pull-up is applied to PF4 during the reset phase. This pin is input floating after reset release.
2. AIN12 is not selectable in ADC scan mode or with analog watchdog.
3. In 44-pin package, AIN9 cannot be used by ADC scan mode.
4. In the open-drain output column, T defines a true open-drain I/O (P-buffer, weak pull-up and protection diode to VDD are
not implemented).
5. The PD1 pin is in input pull-up during the reset phase and after internal reset release.
DocID14771 Rev 15 29/121

30
5.1 Alternate function remapping

As shown in the rightmost column of the pin description table, some alternate functions can
be remapped at different I/O ports by programming one of eight AFR (alternate function
remap) option bits. When the remapping option is active, the default alternate function is no
longer available.
To use an alternate function, the corresponding peripheral must be enabled in the peripheral
registers.
Alternate function remapping does not effect GPIO capabilities of the I/O ports (see the
GPIO section of the family reference manual, RM0016).
30/121 DocID14771 Rev 15

STM8S105x4/6 Memory and register map
6 Memory and register map
6.1 Memory map

Figure 7. Memory map
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[))
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5HVHUYHG
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5HVHUYHG
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LQWHUUXSWYHFWRUV
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[))))
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5HVHUYHG
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06Y9
The following table lists the boundary addresses for each memory size. The top of the stack
is at the RAM end address in each case.
DocID14771 Rev 15 31/121

50
Memory and register map STM8S105x4/6
Table 6. Flash, data EEPROM and RAM boundary address

Memory area Size (byte) Start address End address
32 K 0x00 8000 0x00 FFFF

Flash program memory
16 K 0x00 8000 0x00 BFFF
RAM 2K 0x00 0000 0x00 07FF
Data EEPROM 1024 0x00 4000 0x00 43FF
6.2 Register map
6.2.1 I/O port hardware register map
Table 7. I/O port hardware register map

Address Block Register label Register name Reset status
0x00 5000 PA_ODR Port A data output latch register 0x00

0x00 5001 PA_IDR Port A input pin value register 0xXX(1)
0x00 5002 Port A PA_DDR Port A data direction register 0x00
0x00 5003 PA_CR1 Port A control register 1 0x00
0x00 5004 PA_CR2 Port A control register 2 0x00
0x00 5005 PB_ODR Port B data output latch register 0x00
0x00 5006 PB_IDR Port B input pin value register 0xXX(1)
0x00 5007 Port B PB_DDR Port B data direction register 0x00
0x00 5008 PB_CR1 Port B control register 1 0x00
0x00 5009 PB_CR2 Port B control register 2 0x00
0x00 500A PC_ODR Port C data output latch register 0x00
0x00 500B PB_IDR Port C input pin value register 0xXX(1)
0x00 500C Port C PC_DDR Port C data direction register 0x00
0x00 500D PC_CR1 Port C control register 1 0x00
0x00 500E PC_CR2 Port C control register 2 0x00
0x00 500F PD_ODR Port D data output latch register 0x00
0x00 5010 PD_IDR Port D input pin value register 0xXX(1)
0x00 5011 Port D PD_DDR Port D data direction register 0x00
0x00 5012 PD_CR1 Port D control register 1 0x02
0x00 5013 PD_CR2 Port D control register 2 0x00
32/121 DocID14771 Rev 15

Table 7. I/O port hardware register map (continued)

0x00 5014 PE_ODR Port E data output latch register 0x00

0x00 5015 PE_IDR Port E input pin value register 0xXX(1)
0x00 5016 Port E PE_DDR Port E data direction register 0x00
0x00 5017 PE_CR1 Port E control register 1 0x00
0x00 5018 PE_CR2 Port E control register 2 0x00
0x00 5019 PF_ODR Port F data output latch register 0x00
0x00 501A PF_IDR Port F input pin value register 0xXX(1)
0x00 501B Port F PF_DDR Port F data direction register 0x00
0x00 501C PF_CR1 Port F control register 1 0x00
0x00 501D PF_CR2 Port F control register 2 0x00
0x00 501E PG_ODR Port G data output latch register 0x00
0x00 501F PG_IDR Port G input pin value register 0xXX(1)
0x00 5020 Port G PG_DDR Port G data direction register 0x00
0x00 5021 PG_CR1 Port G control register 1 0x00
0x00 5022 PG_CR2 Port G control register 2 0x00
0x00 5023 PH_ODR Port H data output latch register 0x00
0x00 5024 PH_IDR Port H input pin value register 0xXX(1)
0x00 5025 Port H PH_DDR Port H data direction register 0x00
0x00 5026 PH_CR1 Port H control register 1 0x00
0x00 5027 PH_CR2 Port H control register 2 0x00
0x00 5028 PI_ODR Port I data output latch register 0x00
0x00 5029 PI_IDR Port I input pin value register 0xXX(1)
0x00 502A Port I PI_DDR Port I data direction register 0x00
0x00 502B PI_CR1 Port I control register 1 0x00
0x00 502C PI_CR2 Port I control register 2 0x00
1. Depends on the external circuitry.
DocID14771 Rev 15 33/121

50
6.2.2 General hardware register map
Table 8. General hardware register map

0x00 5050 to 0x00 5059 Reserved area (10 byte)

0x00 505A FLASH_CR1 Flash control register 1 0x00
0x00 505B FLASH_CR2 Flash control register 2 0x00
Flash complementary control
0x00 505C FLASH_NCR2 0xFF
register 2
0x00 505D Flash FLASH _FPR Flash protection register 0x00
Flash complementary
0x00 505E FLASH _NFPR 0xFF
protection register
Flash in-application
0x00 505F FLASH _IAPSR 0x00
programming status register
0x00 5060 to 0x00 5061 Reserved area (2 byte)
Flash program memory
0x00 5062 Flash FLASH _PUKR 0x00
unprotection register
0x00 5063 Reserved area (1 byte)
Data EEPROM unprotection
0x00 5064 Flash FLASH _DUKR 0x00
register
0x00 5065 to 0x00 509F Reserved area (59 byte)
External interrupt control
0x00 50A0 EXTI_CR1 0x00
register 1
ITC
External interrupt control
0x00 50A1 EXTI_CR2 0x00
register 2
0x00 50A2 to 0x00 50B2 Reserved area (17 byte)
0x00 50B3 RST RST_SR Reset status register 0xXX(1)
0x00 50B4 to 0x00 50BF Reserved area (12 byte)
0x00 50C0 CLK_ICKR Internal clock control register 0x01
CLK
0x00 50C1 CLK_ECKR External clock control register 0x00
0x00 50C2 Reserved area (1 byte)
34/121 DocID14771 Rev 15

Table 8. General hardware register map (continued)

0x00 50C3 CLK_CMSR Clock master status register 0xE1

0x00 50C4 CLK_SWR Clock master switch register 0xE1
0x00 50C5 CLK_SWCR Clock switch control register 0xXX
0x00 50C6 CLK_CKDIVR Clock divider register 0x18
Peripheral clock gating
0x00 50C7 CLK_PCKENR1 0xFF
register 1
0x00 50C8 CLK CLK_CSSR Clock security system register 0x00
Configurable clock control
0x00 50C9 CLK_CCOR 0x00
register
Peripheral clock gating
0x00 50CA CLK_PCKENR2 0xFF
register 2
HSI clock calibration trimming
0x00 50CC CLK_HSITRIMR 0x00
register
0x00 50CD CLK_SWIMCCR SWIM clock control register 0bXXXX XXX0
0x00 50CE to 0x00 50D0 Reserved area (3 byte)
0x00 50D1 WWDG_CR WWDG control register 0x7F
WWDG
0x00 50D2 WWDG_WR WWDR window register 0x7F
0x00 50D3 to 00 50DF Reserved area (13 byte)
0x00 50E0 IWDG_KR IWDG key register 0xXX(2)
0x00 50E1 IWDG IWDG_PR IWDG prescaler register 0x00
0x00 50E2 IWDG_RLR IWDG reload register 0xFF
0x00 50E3 to 0x00 50EF Reserved area (13 byte)
0x00 50F0 AWU_CSR1 AWU control/status register 1 0x00
AWU asynchronous prescaler
0x00 50F1 AWU_APR 0x3F
AWU buffer register
AWU timebase selection
0x00 50F2 AWU_TBR 0x00
register
0x00 50F3 BEEP BEEP_CSR BEEP control/status register 0x1F
0x00 50F4 to 0x00 50FF Reserved area (12 byte)
0x00 5200 SPI_CR1 SPI control register 1 0x00
0x00 5201 SPI_CR2 SPI control register 2 0x00
0x00 5202 SPI_ICR SPI interrupt control register 0x00
0x00 5203 SPI_SR SPI status register 0x02
SPI
0x00 5204 SPI_DR SPI data register 0x00
0x00 5205 SPI_CRCPR SPI CRC polynomial register 0x07
0x00 5206 SPI_RXCRCR SPI Rx CRC register 0xFF
0x00 5207 SPI_TXCRCR SPI Tx CRC register 0xFF
DocID14771 Rev 15 35/121

50


0x00 5210 I2C_CR1 I2C control register 1 0x00
0x00 5211 I2C_CR2 I2C control register 2 0x00
0x00 5212 I2C_FREQR I2C frequency register 0x00
0x00 5213 I2C_OARL I2C Own address register low 0x00
I2C Own address register
0x00 5214 I2C_OARH 0x00
high
0x00 5215 Reserved
0x00 5216 I2C_DR I2C data register 0x00
0x00 5217 I2C I2C_SR1 I2C status register 1 0x00
0x00 5218 I2C_SR2 I2C status register 2 0x00
0x00 5219 I2C_SR3 I2C status register 3 0x0X
0x00 521A I2C_ITR I2C interrupt control register 0x00
0x00 521B I2C_CCRL I2C Clock control register low 0x00
0x00 521C I2C_CCRH I2C Clock control register high 0x00
0x00 521D I2C_TRISER I2C TRISE register 0x02
I2C packet error checking
0x00 521E I2C_PECR 0x00
register
0x00 521F to 0x00 522F Reserved area (17 byte)
0x00 5240 UART2_SR UART2 status register 0xC0
0x00 5241 UART2_DR UART2 data register 0xXX
0x00 5242 UART2_BRR1 UART2 baud rate register 1 0x00
0x00 5243 UART2_BRR2 UART2 baud rate register 2 0x00
0x00 5244 UART2_CR1 UART2 control register 1 0x00
UART2
0x00 524A UART2_GTR UART2 guard time register 0x00
0x00 524B UART2_PSCR UART2 prescaler register 0x00
0x00 524C to 0x00 524F Reserved area (4 byte)
36/121 DocID14771 Rev 15


0x00 5250 TIM1_CR1 TIM1 control register 1 0x00

TIM1 slave mode control
0x00 5252 TIM1_SMCR 0x00
register
0x00 5253 TIM1_ETR TIM1 external trigger register 0x00
0x00 5254 TIM1_IER TIM1 interrupt enable register 0x00
0x00 5255 TIM1_SR1 TIM1 status register 1 0x00
TIM1 event generation
0x00 5257 TIM1_EGR 0x00
register
TIM1 capture/compare mode
0x00 5258 TIM1_CCMR1 0x00
register 1
0x00 5259 TIM1_CCMR2 0x00
register 2
0x00 525A TIM1_CCMR3 0x00
register 3
0x00 525B TIM1_CCMR4 0x00
register 4
TIM1 capture/compare enable
0x00 525C TIM1_CCER1 0x00
register 1
TIM1
0x00 525D TIM1_CCER2 0x00
register 2
0x00 525E TIM1_CNTRH TIM1 counter high 0x00
0x00 525F TIM1_CNTRL TIM1 counter low 0x00
0x00 5260 TIM1_PSCRH TIM1 prescaler register high 0x00
0x00 5261 TIM1_PSCRL TIM1 prescaler register low 0x00
0x00 5262 TIM1_ARRH TIM1 auto-reload register high 0xFF
0x00 5263 TIM1_ARRL TIM1 auto-reload register low 0xFF
TIM1 repetition counter
0x00 5264 TIM1_RCR 0x00
register
TIM1 capture/compare
0x00 5265 TIM1_CCR1H 0x00
register 1 high
0x00 5266 TIM1_CCR1L 0x00
register 1 low
0x00 5267 TIM1_CCR2H 0x00
register 2 high
0x00 5268 TIM1_CCR2L 0x00
register 2 low
0x00 5269 TIM1_CCR3H 0x00
register 3 high
DocID14771 Rev 15 37/121

50

0x00 526A TIM1_CCR3L 0x00
register 3 low
0x00 526B TIM1_CCR4H 0x00
register 4 high
TIM1 TIM1 capture/compare

0x00 526C TIM1_CCR4L 0x00
register 4 low
0x00 526D TIM1_BKR TIM1 break register 0x00
0x00 526E TIM1_DTR TIM1 dead-time register 0x00
0x00 526F TIM1_OISR TIM1 output idle state register 0x00
0x00 5270 to 0x00 52FF Reserved area (147 byte)
38/121 DocID14771 Rev 15



0x00 5301 TIM2_IER TIM2 Interrupt enable register 0x00
0x00 5304 TIM2_EGR 0x00
register
0x00 5305 TIM2_CCMR1 0x00
register 1
0x00 5306 TIM2_CCMR2 0x00
register 2
0x00 5307 TIM2_CCMR3 0x00
register 3
0x00 5308 TIM2_CCER1 0x00
register 1
0x00 5309 TIM2_CCER2 0x00
register 2
0x00 530A TIM2_CNTRH TIM2 counter high 0x00
0x00 530B TIM2 TIM2_CNTRL TIM2 counter low 0x00
0x00 530C TIM2_PSCR IM2 prescaler register 0x00
0x00 530D TIM2_ARRH TIM2 auto-reload register high 0xFF
0x00 530E TIM2_ARRL TIM2 auto-reload register low 0xFF
0x00 530F TIM2_CCR1H 0x00
register 1 high
0x00 5310 TIM2_CCR1L 0x00
register 1 low
TIM2 capture/compare reg. 2
0x00 5311 TIM2_CCR2H 0x00
high
0x00 5312 TIM2_CCR2L 0x00
register 2 low
0x00 5313 TIM2_CCR3H 0x00
register 3 high
0x00 5314 TIM2_CCR3L 0x00
register 3 low
DocID14771 Rev 15 39/121

50


0x00 5321 TIM3_IER TIM3 Interrupt enable register 0x00
0x00 5324 TIM3_EGR 0x00
register
0x00 5325 TIM3_CCMR1 0x00
register 1
0x00 5326 TIM3_CCMR2 0x00
register 2
0x00 5327 TIM3_CCER1 0x00
register 1
0x00 5328 TIM3 TIM3_CNTRH TIM3 counter high 0x00
0x00 5329 TIM3_CNTRL TIM3 counter low 0x00
0x00 532A TIM3_PSCR TIM3 prescaler register 0x00
0x00 532B TIM3_ARRH TIM3 auto-reload register high 0xFF
0x00 532C TIM3_ARRL TIM3 auto-reload register low 0xFF
0x00 532D TIM3_CCR1H 0x00
register 1 high
0x00 532E TIM3_CCR1L 0x00
register 1 low
TIM3 capture/compare reg. 2
0x00 532F TIM3_CCR2H 0x00
high
0x00 5330 TIM3_CCR2L 0x00
register 2 low
0x00 5341 TIM4_IER TIM4 interrupt enable register 0x00
0x00 5342 TIM4_SR TIM4 status register 0x00
0x00 5343 TIM4 TIM4_EGR 0x00
register
0x00 5344 TIM4_CNTR TIM4 counter 0x00
0x00 5345 TIM4_PSCR TIM4 prescaler register 0x00
0x00 5346 TIM4_ARR TIM4 auto-reload register 0xFF
0x00 5347 to 0x00 53DF Reserved area (153 byte)
0x00 53E0 to 0x00 53F3 ADC1 ADC_DBxR ADC data buffer registers 0x00
0x00 53F4 to 0x00 53FF Reserved area (12 byte)
40/121 DocID14771 Rev 15


0x00 5400 ADC_CSR ADC control/status register 0x00

0x00 5401 ADC_CR1 ADC configuration register 1 0x00
0x00 5404 ADC_DRH ADC data register high 0xXX
0x00 5405 ADC_DRL ADC data register low 0xXX
ADC Schmitt trigger disable
0x00 5406 ADC_TDRH 0x00
register high
ADC Schmitt trigger disable
0x00 5407 ADC_TDRL 0x00
register low
ADC high threshold register
0x00 5408 ADC_HTRH 0x03
high
ADC1
contd ADC high threshold register
0x00 5409 ADC_HTRL 0xFF
low
ADC low threshold register
0x00 540A ADC_LTRH 0x00
high
ADC low threshold register
0x00 540B ADC_LTRL 0x00
low
ADC analog watchdog status
0x00 540C ADC_AWSRH 0x00
register high
ADC analog watchdog status
0x00 540D ADC_AWSRL 0x00
register low
ADC analog watchdog control
0x00 540E ADC _AWCRH 0x00
register high
ADC analog watchdog control
0x00 540F ADC_AWCRL 0x00
register low
0x00 5410 to 0x00 57FF Reserved area (1008 byte)
1. Depends on the previous reset source.
2. Write-only register.
DocID14771 Rev 15 41/121

50
6.2.3 CPU/SWIM/debug module/interrupt controller registers
Table 9. CPU/SWIM/debug module/interrupt controller registers

Reset
Address Block Register label Register name
status
0x00 7F00 A Accumulator 0x00

0x00 7F01 PCE Program counter extended 0x00
0x00 7F02 PCH Program counter high 0x00
0x00 7F03 PCL Program counter low 0x00
0x00 7F04 XH X index register high 0x00
(1)
0x00 7F05 CPU XL X index register low 0x00
0x00 7F06 YH Y index register high 0x00
0x00 7F07 YL Y index register low 0x00
0x00 7F08 SPH Stack pointer high 0x03
0x00 7F09 SPL Stack pointer low 0xFF
0x00 7F0A CCR Condition code register 0x28
0x00 7F0B to 0x00 7F5F Reserved area (85 byte)
Global configuration
0x00 7F60 CPU CFG_GCR 0x00
register
Interrupt software priority
0x00 7F70 ITC_SPR1 0xFF
register 1
register 2
register 3
register 4
ITC
register 5
register 6
register 7
register 8
0x00 7F78 to 0x00 7F79 Reserved area (2 byte)
SWIM control status
0x00 7F80 SWIM SWIM_CSR 0x00
register
0x00 7F81 to 0x00 7F8F Reserved area (15 byte)
42/121 DocID14771 Rev 15

Table 9. CPU/SWIM/debug module/interrupt controller registers (continued)

Reset
Address Block Register label Register name
status
DM breakpoint 1 register
0x00 7F90 DM_BK1RE 0xFF
extended byte
0x00 7F91 DM_BK1RH 0xFF
high byte
0x00 7F92 DM_BK1RL 0xFF
low byte
0x00 7F93 DM_BK2RE 0xFF
extended byte
0x00 7F94 DM_BK2RH 0xFF
high byte
DM DM breakpoint 2 register
0x00 7F95 DM_BK2RL 0xFF
low byte
DM debug module control
0x00 7F96 DM_CR1 0x00
register 1
DM debug module control
0x00 7F97 DM_CR2 0x00
register 2
DM debug module
0x00 7F98 DM_CSR1 0x10
control/status register 1
DM debug module
0x00 7F99 DM_CSR2 0x00
control/status register 2
0x00 7F9A DM_ENFCTR DM enable function register 0xFF
0x00 7F9B to 0x00 7F9F Reserved area (5 byte)
1. Accessible by debug module only.
DocID14771 Rev 15 43/121

50
Interrupt vector mapping STM8S105x4/6
7 Interrupt vector mapping
Table 10. Interrupt mapping

Wakeup from Wakeup from
IRQ no. Source block Description Vector address
halt mode active-halt mode
- RESET Reset Yes Yes 0x00 8000

- TRAP Software interrupt - - 0x00 8004
External top level
0 TLI - - 0x00 8008
interrupt
Auto wake up from
1 AWU - Yes 0x00 800C
halt
2 CLK Clock controller - - 0x00 8010
Port A external
3 EXTI0 Yes(1) Yes(1) 0x00 8014
interrupts
Port B external
4 EXTI1 Yes Yes 0x00 8018
interrupts
Port C external
5 EXTI2 Yes Yes 0x00 801C
interrupts
Port D external
interrupts
Port E external
interrupts
8 Reserved - - - 0x00 8028
9 Reserved - - - 0x00 802C
10 SPI End of transfer Yes Yes 0x00 8030
TIM1 update/
overflow/
11 TIM1 - - 0x00 8034
underflow/ trigger/
break
TIM1 capture/
12 TIM1 - - 0x00 8038
compare
TIM2 update/
13 TIM2 - - 0x00 803C
overflow
TIM2 capture/
14 TIM2 - - 0x00 8040
compare
TIM3 update/
15 TIM3 - - 0x00 8044
overflow
TIM3 capture/
16 TIM3 - - 0x00 8048
compare
17 Reserved - - - 0x00 804C
18 Reserved - - - 0x00 8050
19 I2C I2C interrupt Yes Yes 0x00 8054
44/121 DocID14771 Rev 15

STM8S105x4/6 Interrupt vector mapping
Table 10. Interrupt mapping (continued)

Wakeup from Wakeup from
IRQ no. Source block Description Vector address
halt mode active-halt mode
20 UART2 Tx complete - - 0x00 8058

Receive register
21 UART2 - - 0x00 805C
DATA FULL
ADC1 end of
22 ADC1 conversion/ analog - - 0x00 8060
watchdog interrupt
TIM4 update/
23 TIM4 - - 0x00 8064
overflow
24 Flash EOP/WR_PG_DIS - - 0x00 8068
0x00 806C to
Reserved
0x00 807C
1. Except PA1.
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Option byte STM8S105x4/6
8 Option byte
Option byte contain configurations for device hardware features as well as the memory
protection of the device. They are stored in a dedicated block of the memory. Except for the
ROP (read-out protection) byte, each option byte has to be stored twice, in a regular form
(OPTx) and a complemented one (NOPTx) for redundancy.
Option byte can be modified in ICP mode (via SWIM) by accessing the EEPROM address
shown in the table below.
Option byte can also be modified on the fly by the application in IAP mode, except the ROP
option that can only be modified in ICP mode (via SWIM).
Refer to the STM8S Flash programming manual (PM0051) and STM8 SWIM
communication protocol and debug module user manual (UM0470) for information on SWIM
programming procedures.
Table 11. Option byte

Option Option bits Factory
Option
Addr. byte default
name
no. 7 6 5 4 3 2 1 0 setting
Read-out
0x4800 protection OPT0 ROP [7:0] 0x00
(ROP)
0x4801 User boot OPT1 UBC [7:0] 0x00
0x4802 code (UBC) NOPT1 NUBC [7:0] 0xFF
0x4803 Alternate OPT2 AFR7 AFR6 AFR5 AFR4 AFR3 AFR2 AFR1 AFR0 0x00
function
0x4804 remapping NOPT2 NAFR7 NAFR6 NAFR5 NAFR4 NAFR3 NAFR2 NAFR1 NAFR0 0xFF
(AFR)
HSI IWDG WWDG WWDG

0x4805h OPT3 Reserved LSI _ EN 0x00
TRIM _HW _HW _HALT
Misc. option
NHSI NLSI NIWDG NWWDG NWWG
0x4806 NOPT3 Reserved 0xFF
TRIM _ EN _HW _HW _HALT
CKAWU
0x4807 OPT4 Reserved EXT CLK PRS C1 PRS C0 0x00
SEL
Clock option
NEXT NCKA
0x4808 NOPT4 Reserved NPRSC1 NPR SC0 0xFF
CLK WUSEL
0x4809 HSE clock OPT5 HSECNT [7:0] 0x00
0x480A startup NOPT5 NHSECNT [7:0] 0xFF
0x480B OPT6 Reserved 0x00

Reserved
0x480C NOPT6 Reserved 0xFF
0x480D OPT7 Reserved 0x00

Reserved
0x480E NOPT7 Reserved 0xFF
0x480F - Reserved -
Reserved
0x48FD - Reserved -
46/121 DocID14771 Rev 15

STM8S105x4/6 Option byte
Table 11. Option byte (continued)

Option Option bits Factory
Option
Addr. byte default
name
no. 7 6 5 4 3 2 1 0 setting
0x487E OPTBL BL[7:0] 0x00

Bootloader
0x487F NOPTBL NBL[7:0] 0xFF
Table 12. Option byte description

Option byte no. Description
ROP[7:0] Memory readout protection (ROP)

0xAA: Enable readout protection (write access via SWIM protocol)
OPT0
Note: Refer to the family reference manual (RM0016) section on
Flash/EEPROM memory readout protection for details.
UBC[7:0] User boot code area
0x00: no UBC, no write-protection
0x01: Page 0 to 1 defined as UBC, memory write-protected
OPT1
...
0x3E: Pages 0 to 63 defined as UBC, memory write-protected
Other values: Reserved
Note: Refer to the family reference manual (RM0016) section on Flash write
protection for more details.
AFR[7:0]
Refer to the following table for the description of the alternate function
OPT2
remapping description of bits [7:2].
HSITRIM: High speed internal clock trimming register size

0: 3-bit trimming supported in CLK_HSITRIMR register
1: 4-bit trimming supported in CLK_HSITRIMR register
LSI_EN: Low speed internal clock enable
0: LSI clock is not available as CPU clock source
1: LSI clock is available as CPU clock source
IWDG_HW: Independent watchdog
OPT3 0: IWDG Independent watchdog activated by software
1: IWDG Independent watchdog activated by hardware
WWDG_HW: Window watchdog activation
0: WWDG window watchdog activated by software
1: WWDG window watchdog activated by hardware
WWDG_HALT: Window watchdog reset on halt
0: No reset generated on halt if WWDG active
1: Reset generated on halt if WWDG active
DocID14771 Rev 15 47/121

50
Option byte STM8S105x4/6
Table 12. Option byte description (continued)

Option byte no. Description
EXTCLK: External clock selection

0: External crystal connected to OSCIN/OSCOUT
1: External clock signal on OSCIN
CKAWUSEL: Auto wake-up unit/clock
0: LSI clock source selected for AWU
OPT4
1: HSE clock with prescaler selected as clock source for AWU
PRSC[1:0] AWU clock prescaler
0x: 16 MHz to 128 kHz prescaler
10: 8 MHz to 128 kHz prescaler
11: 4 MHz to 128 kHz prescaler
HSECNT[7:0]: HSE crystal oscillator stabilization time
0x00: 2048 HSE cycles
OPT5 0xB4: 128 HSE cycles
0xD2: 8 HSE cycles
0xE1: 0.5 HSE cycles
OPT6 Reserved
OPT7 Reserved
BL[7:0]: Bootloader option byte
For STM8S products, this option is checked by the boot ROM code after
reset. Depending on the content of addresses 0x487E, 0x487F, and 0x8000
(reset vector), the CPU jumps to the bootloader or to the reset vector. Refer
OPTBL to the UM0560 (STM8L/S bootloader manual) for more details.
For STM8L products, the bootloader option bytes are on addresses 0xXXXX
and 0xXXXX+1 (2 byte). These option bytes control whether the bootloader is
active or not. For more details, refer to the UM0560 (STM8L/S bootloader
manual) for more details.
48/121 DocID14771 Rev 15

STM8S105x4/6 Option byte
8.1 Alternate function remapping bits
Table 13. Alternate function remapping bits [7:0] of OPT2

Option byte no. Description(1)
AFR7 Alternate function remapping option 7

0: AFR7 remapping option inactive: Default alternate functions.(2)
1: Port D4 alternate function = BEEP.
0: AFR6 remapping option inactive: Default alternate function.(2)
1: Port B5 alternate function = I2C_SDA; port B4 alternate function =
I2C_SCL.
1: Port B3 alternate function = TIM1_ETR; port B2 alternate function =
TIM1_NCC3; port B1 alternate function = TIM1_CH2N; port B0 alternate
function = TIM1_CH1N.
OPT2 1: Port D7 alternate function = TIM1_CH4.
1: Port D0 alternate function = TIM1_BKIN.
1: Port D0 alternate function = CLK_CCO. Note: AFR2 option has priority
over AFR3 if both are activated.
1: Port A3 alternate function = TIM3_CH1; port D2 alternate function
TIM2_CH3
1: Port D3 alternate function = ADC_ETR.
1. Do not use more than one remapping option in the same port.
2. Refer to STM8S105x4/6 pin descriptions.
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Unique ID STM8S105x4/6
9 Unique ID
The devices feature a 96-bit unique device identifier which provides a reference number that
is unique for any device and in any context. The 96 bits of the identifier can never be altered
by the user.
The unique device identifier can be read in single byte and may then be concatenated using
a custom algorithm.
The unique device identifier is ideally suited:
For use as serial numbers
For use as security keys to increase the code security in the program memory while
using and combining this unique ID with software cryptographic primitives and
protocols before programming the internal memory.
To activate secure boot processes
Table 14. Unique ID registers (96 bits)

Content
Address Unique ID bits
description
7 6 5 4 3 2 1 0
0x48CD X co-ordinate on U_ID[7:0]

0x48CE the wafer U_ID[15:8]
0x48CF Y co-ordinate on U_ID[23:16]
0x48D0 the wafer U_ID[31:24]
0x48D1 Wafer number U_ID[39:32]
0x48D2 U_ID[47:40]
0x48D3 U_ID[55:48]
0x48D4 U_ID[63:56]
0x48D5 Lot number U_ID[71:64]
0x48D6 U_ID[79:72]
0x48D7 U_ID[87:80]
0x48D8 U_ID[95:88]
50/121 DocID14771 Rev 15

STM8S105x4/6 Electrical characteristics
10 Electrical characteristics
10.1 Parameter conditions

Unless otherwise specified, all voltages are referred to VSS.
10.1.1 Minimum and maximum values

Unless otherwise specified the minimum and maximum values are guaranteed in the worst
conditions of ambient temperature, supply voltage and frequencies by tests in production on
100% of the devices with an ambient temperature at TA = 25 C, and TA = TAmax (given by
the selected temperature range).
Data based on characterization results, design simulation and/or technology characteristics
are indicated in the table footnotes and are not tested in production. Based on
characterization, the minimum and maximum values refer to sample tests and represent the
mean value plus or minus three times the standard deviation (mean 3 ).
10.1.2 Typical values

Unless otherwise specified, typical data are based on TA = 25 C, VDD = 5.0 V. They are
given only as design guidelines and are not tested.
Typical ADC accuracy values are determined by characterization of a batch of samples from
a standard diffusion lot over the full temperature range, where 95% of the devices have an
error less than or equal to the value indicated (mean 2 ).
10.1.3 Typical curves

Unless otherwise specified, all typical curves are given only as design guidelines and are
not tested.
10.1.4 Typical current consumption

For typical current consumption measurements, VDD, VDDIO and VDDA are connected
together in the configuration shown in the following figure.
Figure 8. Supply current measurement conditions
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DocID14771 Rev 15 51/121

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Electrical characteristics STM8S105x4/6
10.1.5 Loading capacitor

The loading conditions used for pin parameter measurement are shown in Figure 9.
Figure 9. Pin loading conditions
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10.1.6 Pin input voltage

The input voltage measurement on a pin of the device is described in Figure 10.
Figure 10. Pin input voltage
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52/121 DocID14771 Rev 15

10.2 Absolute maximum ratings

Stresses above those listed as absolute maximum ratings may cause permanent damage
to the device. This is a stress rating only and functional operation of the device under these
conditions is not implied. Exposure to maximum rating conditions for extended periods may
affect device reliability.
Table 15. Voltage characteristics

Symbol Ratings Min Max Unit
VDDx - VSS Supply voltage (including VDDA and VDDIO)(1) -0.3 6.5 V
Input voltage on true open drain pins (PE1, PE2)(2) VSS - 0.3 6.5
VIN V
Input voltage on any other pin(2) VSS - 0.3 VDD + 0.3
|VDDx - VDD| Variations between different power pins - 50

mV
|VSSx - VSS| Variations between all the different ground pins - 50
see Absolute maximum ratings
VESD Electrostatic discharge voltage (electrical sensitivity) on
page 89
1. All power (VDD) and ground (VSS) pins must always be connected to the external power supply
2. IINJ(PIN) must never be exceeded. This is implicitly insured if VIN maximum is respected. If VIN maximum
cannot be respected, the injection current must be limited externally to the IINJ(PIN) value. A positive
injection is induced by VIN > VDD while a negative injection is induced by VIN < VSS. For true open-drain
pads, there is no positive injection current, and the corresponding VIN maximum must always be respected
Table 16. Current characteristics

Symbol Ratings Max.(1) Unit
IVDD Total current into VDD power lines (source)(2) 100 mA

IVSS Total current out of VSS ground lines (sink)(1) 80
Output current sunk by any I/O and control pin 20
IIO
Output current source by any I/Os and control pin -20
Total output current sourced (sum of all I/O and control pins)
200
for devices with two VDDIO pins(3)
Total output current sourced (sum of all I/O and control pins)
100
for devices with one VDDIO pin(3)
IIO
Total output current sunk (sum of all I/O and control pins) for
160
devices with two VSSIO pins(3)
Total output current sunk (sum of all I/O and control pins) for
80
devices with one VSSIO pin(3)
Injected current on NRST pin 4
IINJ(PIN) (4) (5) Injected current on OSCIN pin 4
Injected current on any other pin(6) 4
IINJ(PIN)(4) Total injected current (sum of all I/O and control pins)(6) 20
1. Data based on characterization results, not tested in production.
2. All power (VDD, VDDIO, VDDA) and ground (VSS, VSSIO, VSSA) pins must always be connected to the external
supply.
DocID14771 Rev 15 53/121

90
3. I/O pins used simultaneously for high current source/sink must be uniformly spaced around the package
between the VDDIO/VSSIO pins.
4. IINJ(PIN) must never be exceeded. This condition is implicitly insured if VIN maximum is respected. If VIN
maximum cannot be respected, the injection current must be limited externally to the IINJ(PIN) value. A
positive injection is induced by VIN > VDD while a negative injection is induced by VIN < VSS. For true open-
drain pads, there is no positive injection current allowed and the corresponding VIN maximum must always
be respected.
5. Negative injection disturbs the analog performance of the device. See note in Section: TIM2, TIM3 - 16-bit
general purpose timers.
6. When several inputs are submitted to a current injection, the maximum IINJ(PIN) is the absolute sum of the
positive and negative injected currents (instantaneous values). These results are based on characterization
with IINJ(PIN) maximum current injection on four I/O port pins of the device.
Table 17. Thermal characteristics

Symbol Ratings Value Unit
TSTG Storage temperature range 65 to 150

C
TJ Maximum junction temperature 150
10.3 Operating conditions

The device must be used in operating conditions that respect the parameters described in
the table below. In addition, full account must be taken of all physical capacitor
characteristics and tolerances.
Table 18. General operating conditions

Symbol Parameter Conditions Min Max Unit
fCPU Internal CPU clock frequency - 0 16 MHz

VDD/VDDIO Standard operating voltage - 2.95 5.5 V
CEXT: capacitance of external
- 470 3300 nF
capacitor
VCAP(1)
ESR of external capacitor - 0.3
at 1 MHz(2)
ESL of external capacitor - 15 nH
44- and 48-pin
devices, with output
on eight standard
ports, two high sink - 443
ports and two open
Power dissipation at TA = 85 C drain ports
PD(3) for suffix 6 or TA= 125 C for simultaneously(4) mW
suffix 3
32-pin package, with
output on eight
standard ports and - 360
two high sink ports
simultaneously(4)
54/121 DocID14771 Rev 15

Table 18. General operating conditions (continued)

Ambient temperature for suffix Maximum power

TA -40 85
6 version dissipation
Ambient temperature for suffix Maximum power
TA -40 125 C
3 version dissipation
Suffix 6 version -40 105
TJ Junction temperature range
Suffix 3 version -40 130
1. Care should be taken when selecting the capacitor, due to its tolerance, as well as the parameter
dependency on temperature, DC bias and frequency in addition to other factors. The parameter maximum
value must be respected for the full application range.
2. This frequency of 1 MHz as a condition for VCAP parameters is given by design of internal regulator.
3. To calculate PDmax(TA), use the formula PDmax=(TJmax- TA)/JA (see Section 12: Thermal characteristics)
with the value for TJmax given in the previous table and the value for JA given in Section 12: Thermal
characteristics.
4. See Section 12: Thermal characteristics.
Figure 11. fCPUmax versus VDD
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Table 19. Operating conditions at power-up/power-down

Symbol Parameter Conditions Min Typ Max Unit
VDD rise time rate - 2(1) -

tVDD s/V
VDD fall time rate - 2(1) -
tTEMP Reset release delay VDD rising - - 1.7(1) ms
DocID14771 Rev 15 55/121

90
Table 19. Operating conditions at power-up/power-down (continued)

Power-on reset
VIT+ - 2.65 2.8 2.95
threshold
V
Brown-out reset
VIT- - 2.58 2.65 2.88
threshold
Brown-out reset
VHYS(BOR) - - 70 - mV
hysteresis
1. Guaranteed by design, not tested in production.
56/121 DocID14771 Rev 15

10.3.1 VCAP external capacitor

The stabilization for the main regulator is achieved by connecting an external capacitor
CEXT to the VCAP pin. CEXT is specified in Table 18. Care should be taken to limit the series
inductance to less than 15 nH.
Figure 12. External capacitor CEXT

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1. ESR is the equivalent series resistance and ESL is the equivalent inductance.
10.3.2 Supply current characteristics

The current consumption is measured as illustrated in Figure 10: Pin input voltage.
Total current consumption in run mode
Table 20. Total current consumption with code execution in run mode at VDD = 5 V
Symbol Parameter Conditions Typ Max(1) Unit
HSE crystal osc. (16 MHz) 3.2 -

HSE user ext. clock
fCPU = fMASTER = 16 MHz 2.6 3.2
(16 MHz)
Supply HSI RC osc. (16 MHz) 2.5 3.2
current in
Run mode, HSE user ext. clock
IDD(RUN) 1.6 2.2 mA
code fCPU = fMASTER /128 = 125 kHz (16 MHz)
executed HSI RC osc. (16 MHz) 1.3 2.0
from RAM
fCPU = fMASTER /128 =
HSI RC osc. (16 MHz/8) 0.75 -
15.625 kHz
fCPU = fMASTER = 128 kHz LSI RC osc. (128 kHz) 0.55 -
HSE user ext. clock
(16 MHz)
Supply
current in HSI RC osc. (16 MHz) 7.0 8.0
Run mode, fCPU = fMASTER = 2 MHz HSI RC osc. (16 MHz/8)(2) 1.5 -
IDD(RUN) mA
code
executed fCPU = fMASTER /128 = 125 kHz HSI RC osc. (16 MHz) 1.35 2.0
from Flash
HSI RC osc. (16 MHz/8) 0.75 -
15.625 kHz
2. Default clock configuration measured with all peripherals off.
DocID14771 Rev 15 57/121

90
Table 21. Total current consumption with code execution in run mode at VDD = 3.3 V

HSE user ext. clock
(16 MHz)
current in
Run mode, HSE user ext. clock
IDD(RUN) 1.6 2.2 mA
code fCPU = fMASTER /128 = 125 kHz (16 MHz)
executed HSI RC osc. (16 MHz) 1.3 2.0
from RAM
HSI RC osc. (16 MHz/8) 0.75 -
15.625 kHz
HSE user ext. clock
(16 MHz)
Supply
current in HSI RC osc. (16 MHz) 7.0 8.0
Run mode, fCPU = fMASTER = 2 MHz HSI RC osc. (16 MHz/8) (2)
1.5 -
IDD(RUN) mA
code
executed fCPU = fMASTER /128 = 125 kHz HSI RC osc. (16 MHz) 1.35 2.0
from Flash
HSI RC osc. (16 MHz/8) 0.75 -
15.625 kHz
Total current consumption in wait mode
Table 22. Total current consumption in wait mode at VDD = 5 V


HSE user ext. clock
(16 MHz)
IDD(WFI) current in mA
wait mode fCPU = fMASTER /128 = 125 kHz HSI RC osc. (16 MHz) 1.3 -
fCPU = fMASTER /s128 =
HSI RC osc. (16 MHz/8)(2) 0.7 -
15.625 kHz
58/121 DocID14771 Rev 15

Table 23. Total current consumption in wait mode at VDD = 3.3 V


HSE user ext. clock
(16 MHz)
IDD(WFI) current in mA
wait mode fCPU = fMASTER /128 = 125 kHz HSI RC osc. (16 MHz) 1.3 -
fCPU = fMASTER /s128 =
HSI RC osc. (16 MHz/8)(2) 0.7 -
15.625 kHz
Total current consumption in active halt mode
Table 24. Total current consumption in active halt mode at VDD = 5 V

Conditions
Main Max at Max at

Symbol Parameter voltage Typ Unit
85 C(1) 85 C(1)
regulator Flash mode(3) Clock source
(MVR)(2)
HSE crystal osc.

Operating mode 1080 - -
(16 MHz)
Operating mode LSI RC osc. (128 kHz) 200 320 400
On Power down HSE crystal osc.
Supply 1030 - -
current in mode (16 MHz)
IDD(AH) A
active halt Power down
mode LSI RC osc. (128 kHz) 140 270 350
mode
Off Power down
LSI RC osc. (128 kHz) 12 60 150
mode
2. Configured by the REGAH bit in the CLK_ICKR register.
3. Configured by the AHALT bit in the FLASH_CR1 register.
DocID14771 Rev 15 59/121

90
Table 25. Total current consumption in active halt mode at VDD = 3.3 V
Conditions
Main Max at Max at

Symbol Parameter voltage Typ Unit
85 C(1) 85 C(1)
regulator Flash mode(3) Clock source
(MVR)(2)
HSE crystal osc.

Operating mode 680 - -
(16 MHz)
On Power down HSE crystal osc.
Supply 630 - -
current in mode (16 MHz)
IDD(AH) A
active halt Power down
mode LSI RC osc. (128 kHz) 140 270 350
mode
Off Power down
LSI RC osc. (128 kHz) 10 60 150
mode
Total current consumption in halt mode
Table 26. Total current consumption in halt mode at VDD = 5 V

Max at Max at
Symbol Parameter Conditions Typ Unit
85 C(1) 85 C(1)
Flash in operating mode, HSI

62 90 150
Supply current in halt clock after wakeup
IDD(H) A
mode Flash in power-down mode,
6.5 25 80
HSI clock after wakeup
Table 27. Total current consumption in halt mode at VDD = 3.3 V

Max at Max at
Symbol Parameter Conditions Typ Unit
85 C(1) 85 C(1)
Flash in operating mode, HSI

60 90 150
Supply current in halt clock after wakeup
IDD(H) A
mode Flash in power-down mode,
4.5 20 80
HSI clock after wakeup
60/121 DocID14771 Rev 15

Low power mode wakeup times
Table 28. Wakeup times

Wakeup time from wait

tWU(WFI)
mode to run mode(2)
0 to 16 MHz - See note(3)
Wakeup time from run

tWU(WFI) fCPU= fMASTER= 16 MHz 0.56 -
mode(2)
Wakeup time active halt MVR voltage Flash in

HSI (after
tWU(AH) (2) regulator on(4) operating
wakeup) 1(6) 2(6)
mode to run mode mode(5)

HSI (after
tWU(AH) (2) regulator off (4) operating
wakeup) 3(6) -
mode to run mode mode(5)
s
HSI (after
tWU(AH)
regulator off(4)
operating 48(6) -
mode to run mode(2) mode(5)
wakeup)

HSI (after
tWU(AH) (4) power-down 50(6) -
mode to run mode(2) regulator off
mode(5)
wakeup)
Wakeup time from halt

tWU(H) Flash in operating mode(5) 52 -
mode to run mode(2)
Wakeup time from halt
tWU(H) Flash in power-down mode(5) 54 -
mode to run mode(2)
2. Measured from interrupt event to interrupt vector fetch
3. tWU(WFI) = 2 x 1/fmaster + 67 x 1/fCPU
6. Plus 1 LSI clock depending on synchronization.
Total current consumption and timing in forced reset state
Table 29. Total current consumption and timing in forced reset state
Supply current in reset VDD = 5 V 500 -

IDD(R) A
state(2) VDD = 3.3 V 400 -
Reset pin release to
tRESETBL - - 150 s
vector fetch
1. Data guaranteed by design, not tested in production.
2. Characterized with all I/Os tied to VSS.
Current consumption of on-chip peripherals

Subject to general operating conditions for VDD and TA.
DocID14771 Rev 15 61/121

90
HSI internal RC/fCPU= fMASTER = 16 MHz, VDD = 5 V
Table 30. Peripheral current consumption

Symbol Parameter Typ Unit
(1)
IDD(TIM1) TIM1 supply current 230
IDD(TIM2) TIM2 supply current(1) 115
(1)
(1)
A
IDD(UART2) (2)
UART2 supply current 110
IDD(SPI) SPI supply current (2) 45
IDD(I2C) I2C supply current(2) 65
IDD(ADC1) ADC1 supply current when converting(3) 955
1. Data based on a differential IDD measurement between reset configuration and timer counter running at
16 MHz. No IC/OC programmed (no I/O pads toggling). Not tested in production.
2. Data based on a differential IDD measurement between the on-chip peripheral when kept under reset and
not clocked and the on-chip peripheral when clocked and not kept under reset. No I/O pads toggling. Not
tested in production.
3. Data based on a differential IDD measurement between reset configuration and continuous A/D
conversions. Not tested in production.
Current consumption curves

The following figures show typical current consumption measured with code executing in
RAM.
Figure 13. Typ IDD(RUN) vs. VDD HSE user external clock, fCPU = 16 MHz
62/121 DocID14771 Rev 15

Figure 14. Typ IDD(RUN) vs. fCPU HSE user external clock, VDD = 5 V
Figure 15. Typ IDD(RUN) vs. VDD HSI RC osc, fCPU = 16 MHz
DocID14771 Rev 15 63/121

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Figure 16. Typ IDD(WFI) vs. VDD HSE external clock, fCPU = 16 MHz
Figure 17. Typ IDD(WFI) vs. fCPU HSE external clock, VDD = 5 V
64/121 DocID14771 Rev 15

Figure 18. Typ IDD(WFI) vs. VDD HSI RC osc., fCPU = 16 MHz
DocID14771 Rev 15 65/121

90
10.3.3 External clock sources and timing characteristics

HSE user external clock
Table 31. HSE user external clock characteristics

User external clock

fHSE_ext - 0 16 MHz
source frequency
OSCIN input pin high
VHSEH(1) - 0.7 x VDD VDD + 0.3 V
level voltage
V
OSCIN input pin low
VHSEL(1) - VSS 0.3 x VDD
level voltage
OSCIN input leakage
ILEAK_HSE VSS < VIN < VDD -1 +1 A
current
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66/121 DocID14771 Rev 15

HSE crystal/ceramic resonator oscillator

The HSE clock can be supplied with a 1 to 16 MHz crystal/ceramic resonator oscillator. All
the information given in this paragraph is based on characterization results with specified
typical external components. In the application, the resonator and the load capacitors have
to be placed as close as possible to the oscillator pins in order to minimize output distortion
and startup stabilization time. Refer to the crystal resonator manufacturer for more details
(frequency, package, accuracy...).
Table 32. HSE oscillator characteristics

External high speed

fHSE - 1 - 16 MHz
oscillator frequency
RF Feedback resistor - - 220 - k
Recommended load
C(1) - - - 20 pF
capacitance(2)
C = 20 pF 6 (start up)
- -
HSE oscillator power fOSC = 16 MHz 1.6 (stabilized)(3)
IDD(HSE) mA
consumption C = 10 pF 6 (start up)
- -
fOSC = 16 MHz 1.2 (stabilized)(3)
Oscillator
gm - 5 - - mA/V
transconductance
tSU(HSE)(4) Startup time VDD is stabilized - 1 - ms
1. C is approximately equivalent to 2 x crystal Cload.
2. The oscillator selection can be optimized in terms of supply current using a high quality resonator with small Rm value.
Refer to crystal manufacturer for more details
4. tSU(HSE) is the start-up time measured from the moment it is enabled (by software) to a stabilized 16 MHz oscillation is
reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer.
DocID14771 Rev 15 67/121

90
Figure 20. HSE oscillator circuit diagram
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Rm: Notional resistance (see crystal specification)

Lm: Notional inductance (see crystal specification)
Cm: Notional capacitance (see crystal specification)
Co: Shunt capacitance (see crystal specification)
CL1 = CL2 = C: Grounded external capacitance
g m g mcrit
68/121 DocID14771 Rev 15

10.3.4 Internal clock sources and timing characteristics

High speed internal RC oscillator (HSI)
Table 33. HSI oscillator characteristics

fHSI Frequency - - 16 - MHz

User-trimmed with
CLK_HSITRIMR register for
Accuracy of HSI oscillator - - 1(2)
given VDD and TA
conditions(1)
VDD V,
ACCHS -1.0 - 1.0 %
TA 25 C(3)
HSI oscillator accuracy VDD= 5 V,
-2.0 - 2.0
(factory calibrated) -25C TA 85 C
2.95 V VDD 5.5 V,
-3.0(3) - 3.0(3)
-40C TA 125 C
HSI oscillator wakeup
tsu(HSI) - - - 1.0(2) s
time including calibration
HSI oscillator power
IDD(HSI) - - 170 250(3) A
consumption
1. Refer to application note.
Figure 21. Typical HSI accuracy @ VDD = 5 V vs 5 temperatures
DocID14771 Rev 15 69/121

90
Figure 22. Typical HSI frequency variation vs VDD @ 4 temperatures
70/121 DocID14771 Rev 15

Low speed internal RC oscillator (LSI)

Table 34. LSI oscillator characteristics

fLSI Frequency - 110 128 150 kHz

tsu(LSI) LSI oscillator wakeup time - - - 7(1) s
IDD(LSI) LSI oscillator power consumption - - 5 - A
Figure 23. Typical LSI frequency variation vs VDD@ 4 temperatures
DocID14771 Rev 15 71/121

90
10.3.5 Memory characteristics

RAM and hardware registers
Table 35. RAM and hardware registers

Symbol Parameter Conditions Min Unit
VRM Data retention mode(1) Halt mode (or reset) VIT-max(2) V

1. Minimum supply voltage without losing data stored in RAM (in halt mode or under reset) or in hardware
registers (only in halt mode). Guaranteed by design, not tested in production.
2. Refer to Section 10.3: Operating conditions for the value of VIT-max.
Flash program memory/data EEPROM memory
Table 36. Flash program memory/data EEPROM memory

Symbol Parameter Conditions Min(1) Typ Max Unit
Operating voltage
VDD fCPU 16 MHz 2.95 - 5.5 V
(all modes, execution/write/erase)
Standard programming time (including
erase) for byte/word/block - - 6 6.6
tprog (1 byte/4 byte/128 byte)
ms
Fast programming time for 1 block
- - 3 3.33
(128 byte)
terase Erase time for 1 block (128 byte) - - 3 3.33
Erase/write cycles
TA = +85 C 10k - -
NRW (program memory)(2) cycle
Erase/write cycles (data memory)(2) TA = +125 C 300k 1M -
Data retention (program and data
memory) after 10k erase/write cycles TRET = 55 C 20 - -
at TA= +55 C
tRET year
Data retention (data memory) after
300k erase/write cycles at TRET = 85 C 1 - -
TA= +125C
Supply current (Flash programming or
IDD - - 2 - mA
erasing for 1 to 128 byte)
2. The physical granularity of the memory is 4 byte, so cycling is performed on 4 byte even when a
write/erase operation addresses a single byte.
72/121 DocID14771 Rev 15

10.3.6 I/O port pin characteristics

General characteristics
Subject to general operating conditions for VDD and TA unless otherwise specified. All
unused pins must be kept at a fixed voltage, using the output mode of the I/O for example or
an external pull-up or pull-down resistor.
Table 37. I/O static characteristics

VIL Input low level voltage -0.3 V - 0.3 x VDD

V
VIH Input high level voltage VDD = 5 V 0.7 x VDD - VDD + 0.3 V
Vhys Hysteresis(1) - 700 - mV
Rpu Pull-up resistor VDD = 5 V, VIN = VSS 30 55 80 k
Fast I/Os
- - 35(2)
Rise and fall time Load = 50 pF
tR, tF ns
(10% - 90%) Standard and high sink I/Os
- - 125(2)
Load = 50 pF
Fast I/Os
- - 20(2)
Rise and fall time Load = 20 pF
tR, tF ns
(10% - 90%) Standard and high sink I/Os (2)
- - 50
Load = 20 pF
Digital input leakage
Ilkg VSS VIN VDD - - 1(3) A
current
Analog input leakage
Ilkg ana VSS VIN VDD - - 250(3) nA
current
Leakage current in
Ilkg(inj) Injection current 4 mA - - 1(3) A
adjacent I/O
1. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not tested in production.
2. Data guaranteed by design.
3. Data based on characterization results, not tested in production
DocID14771 Rev 15 73/121

90
Figure 24. Typical VIL and VIH vs VDD @ 4 Figure 25. Typical pull-up current vs VDD @ 4
temperatures temperatures
Figure 26. Typical pull-up resistance vs VDD @ 4 temperatures
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Table 38. Output driving current (standard ports)

Output low level with 8 IIO= 10 mA,

- 2.0
pins sunk VDD = 5 V
VOL
- 1.0(1)
pins sunk VDD = 3.3 V
V
Output high level with 8 IIO= 10 mA,
2.4 -
pins sourced VDD = 5 V
VOH
2.0(1) -
pins sourced VDD = 3.3 V
74/121 DocID14771 Rev 15

Table 39. Output driving current (true open drain ports)


- 1.0
pins sunk VDD = 5 V
VOL
- 1.5(1) V
pins sunk VDD = 3.3 V
VOH - 2.0(1)
Table 40. Output driving current (high sink ports)


- 0.9
pins sunk VDD = 5 V
IIO= 10 mA,
VOL - 1.1(1)
Output low level with 4 VDD = 3.3 V
pins sunk IIO= 20 mA,
- 1.6(1)
VDD = 5 V
V
3.8 -
IIO= 10 mA,
VOH 1.9(1) -
Output high level with 4 VDD = 3.3 V
pins sourced IIO= 20 mA,
2.9(1) -
VDD = 5 V
10.3.7 Typical output level curves

The following figures show the typical output level curves measured with the output on a
single pin.
Figure 27. Typ. VOL @ VDD = 3.3 V (standard Figure 28. Typ. VOL @ VDD = 5.0 V (standard
ports) ports)
DocID14771 Rev 15 75/121

90
Figure 29. Typ. VOL @ VDD = 3.3 V (true open Figure 30. Typ. VOL @ VDD = 5.0 V (true open
drain ports) drain ports)
Figure 31. Typ. VOL @ VDD = 3.3 V (high sink Figure 32. Typ. VOL @ VDD = 5.0 V (high sink
ports) ports)
76/121 DocID14771 Rev 15

Figure 33. Typ. VDD - VOH @ VDD = 3.3 V Figure 34. Typ. VDD - VOH @ VDD = 5.0 V
(standard ports) (standard ports)
Figure 35. Typ. VDD - VOH @ VDD = 3.3 V (high Figure 36. Typ. VDD - VOH @ VDD = 5.0 V (high
sink ports) sink ports)
DocID14771 Rev 15 77/121

90
10.3.8 Reset pin characteristics

Subject to general operating conditions for VDD and TA unless otherwise specified.
Table 41. NRST pin characteristics

VIL(NRST) NRST input low level voltage(1) - -0.3 - 0.3 x VDD
VIH(NRST) NRST input high level voltage(1) IOL= 2 mA 0.7 x VDD - VDD+ 0.3 V
VOL(NRST) NRST output low level voltage(1) IOL= 3 mA - - 0.5

RPU(NRST) NRST pull-up resistor(2) - 30 55 80 k
tIFP(NRST) NRST input filtered pulse(3) - - - 75
ns
tINFP(NRST) NRST Input not filtered pulse(3) - 500 - -
tOP(NRST) NRST output pulse(3) - 20 - - s
2. The RPU pull-up equivalent resistor is based on a resistive transistor.
Figure 37. Typical NRST VIL and VIH vs VDD @ 4 temperatures
78/121 DocID14771 Rev 15

Figure 38. Typical NRST pull-up resistance RPU vs VDD @ 4 temperatures
Figure 39. Typical NRST pull-up current Ipu vs VDD @ 4 temperatures
The reset network shown in Figure 40 protects the device against parasitic resets. The user
must ensure that the level on the NRST pin can go below VIL(NRST) max (see Table 41:
NRST pin characteristics), otherwise the reset is not taken into account internally.
For power consumption sensitive applications, the external reset capacitor value can be
reduced to limit the charge/discharge current. If NRST signal is used to reset external
circuitry, attention must be taken to the charge/discharge time of the external capacitor to
fulfill the external devices reset timing conditions. Minimum recommended capacity is
100 nF.
DocID14771 Rev 15 79/121

90
Figure 40. Recommended reset pin protection
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10.3.9 SPI serial peripheral interface

Unless otherwise specified, the parameters given in Table 42 are derived from tests
performed under ambient temperature, fMASTER frequency and VDD supply voltage
conditions. tMASTER = 1/fMASTER.
Refer to I/O port characteristics for more details on the input/output alternate function
characteristics (NSS, SCK, MOSI, MISO).
Table 42. SPI characteristics

Symbol Parameter Conditions(1) Min Max Unit
fSCK Master mode 0 8

SPI clock frequency MHz
1/tc(SCK) Slave mode 0 6
80/121 DocID14771 Rev 15

Table 42. SPI characteristics (continued)

Symbol Parameter Conditions(1) Min Max Unit
tr(SCK) SPI clock rise and fall Capacitive load:

- 25
tf(SCK) time C = 30 pF
tsu(NSS)(2) NSS setup time Slave mode 4 * tMASTER -
th(NSS)(2) NSS hold time Slave mode 70 -
tw(SCKH) (2)
SCK high and low time Master mode tSCK/2 - 15 tSCK/2 + 15
tw(SCKL)(2)
tsu(MI)(2) Master mode 5 -

Data input setup time
tsu(SI)(2) Slave mode 5 -
th(MI)(2) Master mode 7 -

Data input hold time
th(SI)(2) Slave mode 10 - ns
ta(SO) (2)(3) Data output access time Slave mode - 3* tMASTER
(2)(4)
tdis(SO) Data output disable time Slave mode 25 -
Slave mode
tv(SO)(2) Data output valid time - 73
(after enable edge)
Master mode (after
tv(MO)(2) Data output valid time - 36
enable edge)
Slave mode (after
th(SO)(2) 28 -
enable edge)
Data output hold time
Master mode (after
th(MO)(2) 12 -
enable edge)
1. Parameters are given by selecting 10 MHz I/O output frequency.
2. Values based on design simulation and/or characterization results, and not tested in production.
3. Min time is for the minimum time to drive the output and the max time is for the maximum time to validate
the data.
4. Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put
the data in Hi-Z.
DocID14771 Rev 15 81/121

90
Figure 41. SPI timing diagram where slave mode and CPHA = 0
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Figure 42. SPI timing diagram where slave mode and CPHA = 1
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82/121 DocID14771 Rev 15

Figure 43. SPI timing diagram - master mode

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DocID14771 Rev 15 83/121

90
10.3.10 I2C interface characteristics
Table 43. I2C characteristics

Standard mode I2C Fast mode I2C(1)
Symbol Parameter Unit
Min(2) Max(2) Min(2) Max(2)
tw(SCLL) SCL clock low time 4.7 - 1.3 -

s
tw(SCLH) SCL clock high time 4.0 - 0.6 -
tsu(SDA) SDA setup time 250 - 100 -
th(SDA) SDA data hold time 0(3) - 0(4) 900(3)

tr(SDA) SDA and SCL rise time ns
- 1000 - 300
tr(SCL) (VDD = 3 to 5.5 V)
tf(SDA) SDA and SCL fall time
- 300 - 300
tf(SCL) (VDD = 3 to 5.5 V)
th(STA) START condition hold time 4.0 - 0.6 -
tsu(STA) Repeated START condition setup time 4.7 - 0.6 -
tsu(STO) STOP condition setup time 4.0 - 0.6 - s
STOP to START condition time

tw(STO:STA) 4.7 - 1.3 -
(bus free)
Cb Capacitive load for each bus line - 400 - 400 pF
1. fMASTER, must be at least 8 MHz to achieve max fast I2C speed (400 kHz)
2. Data based on standard I2C protocol requirement, not tested in production
3. The maximum hold time of the start condition has only to be met if the interface does not stretch the low
time
4. The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge the
undefined region of the falling edge of SCL
Figure 44. Typical application with I2C bus and timing diagram
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84/121 DocID14771 Rev 15

10.3.11 10-bit ADC characteristics

Subject to general operating conditions for VDDA, fMASTER, and TA unless otherwise
specified.
Table 44. ADC characteristics

VDD= 2.95 to 5.5 V 1 - 4

fADC ADC clock frequency MHz
VDD= 4.5 to 5.5 V 1 - 6
VDDA Analog supply - 3.0 - 5.5
VREF+ Positive reference voltage - 2.75(1) - VDDA V
VREF- Negative reference voltage - VSSA - 0.5(1)
- VSSA - VDDA
VAIN Conversion voltage range(2) Devices with V

external VREF- - VREF+
VREF+/VREF-
Internal sample and hold
CADC - - 3 - pF
capacitor
fADC = 4 MHz - 0.75 -
tS(2) Minimum sampling time s
fADC = 6 MHz - 0.5 -
tSTAB Wakeup time from standby - - 7.0 - s
fADC = 4 MHz 3.5 s
Minimum total conversion time
tCONV (including sampling time, 10- fADC = 6 MHz 2.33 s
bit resolution)
- 14 1/fADC
2. During the sample time, the sampling capacitance, CAIN (3 pF max), can be charged/discharged by the
external source. The internal resistance of the analog source must allow the capacitance to reach its final
voltage level within tS. After the end of the sample time tS, changes of the analog input voltage have no
effect on the conversion result. Values for the sample clock tS depend on programming.
DocID14771 Rev 15 85/121

90
Table 45. ADC accuracy with RAIN< 10 k, VDDA = 5 V

fADC = 2 MHz 1.0 2.5
|ET| Total unadjusted error(2) fADC = 4 MHz 1.4 3.0

fADC = 6 MHz 1.6 3.5
fADC = 2 MHz 0.6 2.0
|EO| Offset error(2) fADC = 4 MHz 1.1 2.5

fADC = 6 MHz 1.2 2.5
fADC = 2 MHz 0.2 2.0
|EG| Gain error(2) fADC = 4 MHz 0.6 2.5 LSB

fADC = 6 MHz 0.8 2.5
fADC = 2 MHz 0.7 1.5
|ED| Differential linearity error(2) fADC = 4 MHz 0.7 1.5

fADC = 6 MHz 0.8 1.5
fADC = 2 MHz 0.6 1.5
|EL| Integral linearity error(2) fADC = 4 MHz 0.6 1.5

fADC = 6 MHz 0.6 1.5
2. ADC accuracy vs. negative injection current: Injecting negative current on any of the analog input pins
should be avoided as this significantly reduces the accuracy of the conversion being performed on another
analog input. It is recommended to add a Schottky diode (pin to ground) to standard analog pins which may
potentially inject negative current. Any positive injection current within the limits specified for IINJ(PIN) and
IINJ(PIN) in Section 10.3.6 does not affect the ADC accuracy.
Table 46. ADC accuracy with RAIN< 10 k, VDDA = 3.3 V

fADC = 2 MHz 1.1 2.0

|ET| Total unadjusted error(2)
fADC = 4 MHz 1.6 2.5
fADC = 2 MHz 0.7 1.5
|EO| Offset error(2)
fADC = 4 MHz 1.3 2.0
fADC = 2 MHz 0.2 1.5
|EG| Gain error(2) LSB
fADC = 4 MHz 0.5 2.0
fADC = 2 MHz 0.7 1.0
|ED| Differential linearity error(2)
fADC = 4 MHz 0.7 1.0
fADC = 2 MHz 0.6 1.5
|EL| Integral linearity error(2)
fADC = 4 MHz 0.6 1.5
86/121 DocID14771 Rev 15

2. ADC accuracy vs. negative injection current: Injecting negative current on any of the analog input pins
should be avoided as this significantly reduces the accuracy of the conversion being performed on another
analog input. It is recommended to add a Schottky diode (pin to ground) to standard analog pins which may
potentially inject negative current. Any positive injection current within the limits specified for IINJ(PIN) and
IINJ(PIN) in Section 10.3.6 does not affect the ADC accuracy.
Figure 45. ADC accuracy characteristics

EG
1023
V V
1022 DDA SSA
1LSB = -----------------------------------------
1021 IDEAL 1024
(2)
ET
7 (3)
(1)
6
5
EO EL
4
3
ED
2
1 LSBIDEAL
1
0 1 2 3 4 5 6 7 1021102210231024
VSSA VDDA
1. Example of an actual transfer curve

2. The ideal transfer curve
3. End point correlation line
ET = Total unadjusted error: maximum deviation between the actual and the ideal transfer curves.
EO = Offset error: deviation between the first actual transition and the first ideal one.
EG = Gain error: deviation between the last ideal transition and the last actual one.
ED = Differential linearity error: maximum deviation between actual steps and the ideal one.
EL = Integral linearity error: maximum deviation between any actual transition and the end point correlation
line.
Figure 46. Typical application with ADC
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97
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9
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1. Legend: RAIN = external resistance, CAIN = capacitors, Csamp = internal sample and hold capacitor.
DocID14771 Rev 15 87/121

90
10.3.12 EMC characteristics

Susceptibility tests are performed on a sample basis during product characterization.
Functional EMS (electromagnetic susceptibility)

While executing a simple application (toggling 2 LEDs through I/O ports), the product is
stressed by two electromagnetic events until a failure occurs (indicated by the LEDs).
ESD: Electrostatic discharge (positive and negative) is applied on all pins of the device
until a functional disturbance occurs. This test conforms with the IEC 61000-4-2
standard.
FTB: A burst of fast transient voltage (positive and negative) is applied to VDD and VSS
through a 100 pF capacitor, until a functional disturbance occurs. This test conforms
with the IEC 61000-4-4 standard.
A device reset allows normal operations to be resumed. The test results are given in the
table below based on the EMS levels and classes defined in application note AN1709 (EMC
design guide for STM microcontrollers).
Designing hardened software to avoid noise problems

EMC characterization and optimization are performed at component level with a typical
application environment and simplified MCU software. It should be noted that good EMC
performance is highly dependent on the user application and the software in particular.
Therefore it is recommended that the user applies EMC software optimization and
prequalification tests in relation with the EMC level requested for his application.
Software recommendations
The software flowchart must include the management of runaway conditions such as:
Corrupted program counter
Unexpected reset
Critical data corruption (control registers...)
Prequalification trials
Most of the common failures (unexpected reset and program counter corruption) can be
recovered by applying a low state on the NRST pin or the oscillator pins for 1 second.
To complete these trials, ESD stress can be applied directly on the device, over the range of
specification values. When unexpected behavior is detected, the software can be hardened
to prevent unrecoverable errors occurring. See application note AN1015 (Software
techniques for improving microcontroller EMC performance).
Table 47. EMS data

Symbol Parameter Conditions Level/class
VDD 5 V, TA25 C,
Voltage limits to be applied on any I/O pin
VFESD fMASTER 16 MHz (HSI clock), 2/B(1)
to induce a functional disturbance
Conforms to IEC 1000-4-2
Fast transient voltage burst limits to be VDD 5 V, TA25 C,

VEFTB applied through 100 pF on VDD and VSS fMASTER 16 MHz (HSI clock), 4/A(1)
pins to induce a functional disturbance Conforms to IEC 1000-4-4
88/121 DocID14771 Rev 15

1. Data obtained with HSI clock configuration, after applying the hardware recommendations described in
AN2860 (EMC guidelines for STM8S microcontrollers).
Electromagnetic interference (EMI)

Based on a simple application running on the product (toggling 2 LEDs through the I/O
ports), the product is monitored in terms of emission. This emission test is in line with the
norm IEC 61967-2 which specifies the board and the loading of each pin.
Table 48. EMI data

Conditions
Max fHSE/fCPU(1)
Symbol Parameter Unit
Monitored
General conditions
frequency band 8 MHz/ 8 MHz/
8 MHz 16 MHz
VDD 5 V, 0.1 MHz to 30 MHz 13 14

Peak level TA 25 C, 30 MHz to 130 MHz 23 19 dBV
SEMI LQFP48 package.
Conforming to 130 MHz to 1 GHz -4.0 -4.0
EMI level IEC 61967-2 EMI level 2.0 1.5 -
Absolute maximum ratings (electrical sensitivity)

Based on two different tests (ESD, DLU and LU) using specific measurement methods, the
product is stressed to determine its performance in terms of electrical sensitivity. For more
details, refer to the application note AN1181.
Electrostatic discharge (ESD)

Electrostatic discharges (a positive then a negative pulse separated by 1 second) are
applied to the pins of each sample according to each pin combination. The sample size
depends on the number of supply pins in the device (3 parts x (n+1) supply pin). One model
can be simulated: Human body model. This test conforms to the JESD22-A114A/A115A
standard. For more details, refer to the application note AN1181.
Table 49. ESD absolute maximum ratings

Maximum
Symbol Ratings Conditions Class Unit
value(1)
Electrostatic discharge voltage TA 25C, conforming to

VESD(HBM) A 2000
(Human body model) JESD22-A114
V
Electrostatic discharge voltage TA 25C, conforming to
VESD(CDM) IV 1000
(Charge device model) SD22-C101
DocID14771 Rev 15 89/121

90
Static latch-up
Two complementary static tests are required on 10 parts to assess the latch-up
performance.
A supply overvoltage (applied to each power supply pin), and
A current injection (applied to each input, output and configurable I/O pin) are
performed on each sample.
This test conforms to the EIA/JESD 78 IC latch-up standard. For more details, refer to the
application note AN1181.
Table 50. Electrical sensitivities

Symbol Parameter Conditions Class(1)
TA 25 C
LU Static latch-up class TA 85 C A
TA 125 C
1. Class description: A Class is an STMicroelectronics internal specification. All its limits are higher than the
JEDEC specifications, that means when a device belongs to class A it exceeds the JEDEC standard. B
class strictly covers all the JEDEC criteria (international standard).
90/121 DocID14771 Rev 15

STM8S105x4/6 Package information
11 Package information
In order to meet environmental requirements, ST offers these devices in different grades of

ECOPACK packages, depending on their level of environmental compliance. ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK is an ST trademark.
11.1 LQFP48 package information

Figure 47. LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package outline
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DocID14771 Rev 15 91/121

107
Package information STM8S105x4/6

mechanical data
millimeters inches(1)
Symbol
Min Typ Max Min Typ Max
A - - 1.600 - - 0.0630
A1 0.050 - 0.150 0.0020 - 0.0059
A2 1.350 1.400 1.450 0.0531 0.0551 0.0571
b 0.170 0.220 0.270 0.0067 0.0087 0.0106
c 0.090 - 0.200 0.0035 - 0.0079
D 8.800 9.000 9.200 0.3465 0.3543 0.3622
D1 6.800 7.000 7.200 0.2677 0.2756 0.2835
D3 - 5.500 - - 0.2165 -
E 8.800 9.000 9.200 0.3465 0.3543 0.3622
E1 6.800 7.000 7.200 0.2677 0.2756 0.2835
E3 - 5.500 - - 0.2165 -
e - 0.500 - - 0.0197 -
L 0.450 0.600 0.750 0.0177 0.0236 0.0295
L1 - 1.000 - - 0.0394 -
k 0 3.5 7 0 3.5 7
ccc - - 0.080 - - 0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.
92/121 DocID14771 Rev 15


recommended footprint

AID
1. Dimensions are expressed in millimeters.
Device marking
The following figure gives an example of topside marking orientation versus pin 1 identifier
location.
Figure 49. LQFP48 marking example (package top view)
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1. Parts marked as "ES", "E" or accompanied by an Engineering Sample notification letter, are not yet
qualified and therefore not yet ready to be used in production and any consequences deriving from such
DocID14771 Rev 15 93/121

107
usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering
samples in production. ST Quality has to be contacted prior to any decision to use these Engineering
Samples to run qualification activity.

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94/121 DocID14771 Rev 15


mechanical data
Symbol
A - - 1.600 - - 0.0630
A1 0.050 - 0.150 0.0020 - 0.0059
A2 1.350 1.400 1.450 0.0531 0.0551 0.0571
b 0.300 0.370 0.450 0.0118 0.0146 0.0177
c 0.090 - 0.200 0.0035 - 0.0079
D 11.800 12.000 12.200 0.4646 0.4724 0.4803
D1 9.800 10.000 10.200 0.3858 0.3937 0.4016
D3 - 8.000 - - 0.3150 -
E 11.800 12.000 12.200 0.4646 0.4724 0.4803
E1 9.800 10.000 10.200 0.3858 0.3937 0.4016
E3 - 8.000 - - 0.3150 -
e - 0.800 - - 0.0315 -
L 0.450 0.600 0.750 0.0177 0.0236 0.0295
L1 - 1.000 - - 0.0394 -
k 0 3.5 7 0 3.5 7
ccc - - 0.100 - - 0.0039
DocID14771 Rev 15 95/121

107


<B)3
Device marking
location.
96/121 DocID14771 Rev 15

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1. Parts marked as "ES", "E" or accompanied by an Engineering Sample notification letter, are not yet
Samples to run qualification activity.
DocID14771 Rev 15 97/121

107

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98/121 DocID14771 Rev 15


mechanical data
Symbol
A - - 1.600 - - 0.0630
A1 0.050 - 0.150 0.0020 - 0.0059
A2 1.350 1.400 1.450 0.0531 0.0551 0.0571
b 0.300 0.370 0.450 0.0118 0.0146 0.0177
c 0.090 - 0.200 0.0035 - 0.0079
D 8.800 9.000 9.200 0.3465 0.3543 0.3622
D1 6.800 7.000 7.200 0.2677 0.2756 0.2835
D3 - 5.600 - - 0.2205 -
E 8.800 9.000 9.200 0.3465 0.3543 0.3622
E1 6.800 7.000 7.200 0.2677 0.2756 0.2835
E3 - 5.600 - - 0.2205 -
e - 0.800 - - 0.0315 -
L 0.450 0.600 0.750 0.0177 0.0236 0.0295
L1 - 1.000 - - 0.0394 -
k 0 3.5 7 0 3.5 7
ccc - - 0.100 - - 0.0039
DocID14771 Rev 15 99/121

107


6?&0?6
Device marking
location.
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1. Parts marked as ES,E or accompanied by an Engineering Sample notification letter, are not yet
samples to run qualification activity.
100/121 DocID14771 Rev 15

11.4 UFQFPN32 package information

Figure 56. UFQFPN32 - 32-pin, 5x5 mm, 0.5 mm pitch ultra thin fine pitch quad flat
package outline
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2. All leads/pads should be soldered to the PCB to improve the lead/pad solder joint life.
3. There is an exposed die pad on the underside of the UFQFPN package. It is recommended to connect and
solder this backside pad to PCB ground.
4. Dimensions are in millimeters.
DocID14771 Rev 15 101/121

107
Table 54. UFQFPN32 - 32-pin, 5x5 mm, 0.5 mm pitch ultra thin fine pitch quad flat
package mechanical data
Symbol
A 0.500 0.550 0.600 0.0197 0.0217 0.0236

A1 0.000 0.020 0.050 0.0000 0.0008 0.0020
A3 - 0.152 - - 0.0060 -
b 0.180 0.230 0.280 0.0071 0.0091 0.0110
D 4.900 5.000 5.100 0.1929 0.1969 0.2008
D1 3.400 3.500 3.600 0.1339 0.1378 0.1417
D2 3.400 3.500 3.600 0.1339 0.1378 0.1417
E 4.900 5.000 5.100 0.1929 0.1969 0.2008
E1 3.400 3.500 3.600 0.1339 0.1378 0.1417
E2 3.400 3.500 3.600 0.1339 0.1378 0.1417
e - 0.500 - - 0.0197 -
L 0.300 0.400 0.500 0.0118 0.0157 0.0197
ddd - - 0.080 - - 0.0031
Figure 57. UFQFPN32 - 32-pin, 5 x5 mm, 0.5 mm pitch ultra thin fine pitch quad flat
package recommended footprint

$%B)3B9
102/121 DocID14771 Rev 15

Device marking
location.
Figure 58. UFQFPN32 marking example (package top view)
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DocID14771 Rev 15 103/121

107
11.5 SDIP32 package information

Figure 59. SDIP32 package outline
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Table 55. SDIP32 package mechanical data

mm inches(1)
Dim.
A 3.556 3.759 5.080 0.1400 0.1480 0.2000

A1 0.508 - - 0.0200 - -
A2 3.048 3.556 4.572 0.1200 0.1400 0.1800
B 0.356 0.457 0.584 0.0140 0.0180 0.0230
B1 0.762 1.016 1.397 0.0300 0.0400 0.0550
C 0.203 0.254 0.356 0.0079 0.0100 0.0140
D 27.430 27.940 28.450 1.0799 1.1000 1.1201
E 9.906 10.410 11.050 0.3900 0.4098 0.4350
E1 7.620 8.890 9.398 0.3000 0.3500 0.3700
e - 1.778 - - 0.0700 -
eA - 10.160 - - 0.4000 -
104/121 DocID14771 Rev 15

Table 55. SDIP32 package mechanical data (continued)

mm inches(1)
Dim.
eB - - 12.700 - - 0.5000
L 2.540 3.048 3.810 0.1000 0.1200 0.1500
1. Values in inches are converted from mm and rounded to 4 decimal digits
Device marking
location.
Figure 60. SDIP32 marking example (package top view)
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DocID14771 Rev 15 105/121

107
Thermal characteristics STM8S105x4/6
12 Thermal characteristics
The maximum junction temperature (TJmax) of the device must never exceed the values
specified in Table 18: General operating conditions, otherwise the functionality of the device
cannot be guaranteed.
The maximum junction temperature TJmax, in degrees Celsius, may be calculated using the
following equation:
TJmax = TAmax + (PDmax x JA)
Where:
TAmax is the maximum ambient temperature in C
JA is the package junction-to-ambient thermal resistance in C/W
PDmax is the sum of PINTmax and PI/Omax (PDmax = PINTmax + PI/Omax)
PINTmax is the product of IDD and VDD, expressed in Watts. This is the maximum chip
internal power.
PI/Omax represents the maximum power dissipation on output pins
Where:
PI/Omax = (VOL*IOL) + ((VDD-VOH)*IOH),
taking into account the actual VOL/IOL and VOH/IOH of the I/Os at low and high level in
the application.
Table 56. Thermal characteristics(1)

Symbol Parameter Value Unit
Thermal resistance junction-ambient

LQFP48 - 7x7 mm
LQFP44 - 10x10 mm
JA C/W
LQFP32 - 7x7 mm
UFQFPN32 - 5x5 mm
SDIP32 - 400 ml
1. Thermal resistances are based on JEDEC JESD51-2 with 4-layer PCB in a natural convection
environment.
12.1 Reference document

JESD51-2 integrated circuits thermal test method environment conditions - natural
convection (still air). Available from www.jedec.org.
106/121 DocID14771 Rev 15

STM8S105x4/6 Thermal characteristics
12.2 Selecting the product temperature range

When ordering the microcontroller, the temperature range is specified in the order code (see
Section 13: Ordering information).
The following example shows how to calculate the temperature range needed for a given
application.
Assuming the following application conditions:
Maximum ambient temperature TAmax= 82C (measured according to JESD51-2),
IDDmax = 15 mA, VDD = 5.5 V
Maximum 8 standard I/Os used at the same time in output at low level with
IOL = 10 mA, VOL= 2 V
Maximum 4 high sink I/Os used at the same time in output at low level with
IOL = 20 mA, VOL= 1.5 V
Maximum 2 true open drain I/Os used at the same time in output at low level with
IOL = 20 mA, VOL= 2 V
PINTmax = 15 mA x 5.5 V= 82.5 mW
PIOmax = (10 mA x 2 V x 8) + (20 mA x 2 V x 2) + (20 mA x 1.5 V x 4) = 360 mW
This gives: PINTmax = 82.5 mW and PIOmax = 360 mW:
PDmax = 82.5 mW + 360 mW
Thus: PDmax = 443 mW.
Using the values obtained in Table 56: Thermal characteristics TJmax is calculated as
follows:
For LQFP32 60C/W
TJmax = 82C + (60C/W x 443 mW) = 82C + 27C = 109 C
This is within the range of the suffix 6 version parts (-40 < TJ < 131C).
Parts must be ordered at least with the temperature range suffix 3.
DocID14771 Rev 15 107/121

107
Ordering information STM8S105x4/6
13 Ordering information
Figure 61. STM8S105x4/6 access line ordering information scheme(1)
Example: STM8 S 105 K 4 T 6 TR

Product class
STM8 microcontroller
Family type
S = Standard
Sub-family type
10x = Access line
105 sub-family
Pin count
K = 32 pins
S = 44 pins
C = 48 pins
Program memory size

4 = 16 Kbyte
6 = 32 Kbyte
Package type
B = SDIP
T = LQFP
U = UFQFPN
Temperature range
3 = -40 to 125 C
6 = -40 to 85 C
Package pitch/thickness
Blank = 0.5 mm
C = 0.8 mm
A = 0.55 mm thickness for UFQFPN32
Packing
No character = Tray or tube
TR = Tape and reel
1. A dedicated ordering information scheme will be released if, in the future, memory programming service
(FastROM) is required The letter P will be added after STM8S. Three unique letters identifying the
customer application code will also be visible in the codification. Example: STM8SP103K3MACTR.
For a list of available options (for example memory size, package) and orderable part
numbers or for further information on any aspect of this device, please go to www.st.com or
contact the nearest ST Sales Office.
108/121 DocID14771 Rev 15

STM8S105x4/6 Ordering information
13.1 STM8S105 FASTROM microcontroller option list

(last update: September 2010)
Customer ...............................................................................
Address ...............................................................................
Contact ...............................................................................
Phone number ...............................................................................
FASTROM code reference(1) ...............................................................................
1. The FASTROM code name is assigned by STMicroelectronics.
The preferable format for programing code is .Hex (.s19 is accepted)

If data EEPROM programing is required, a separate file must be sent with the requested
data.
Note: See the option byte section in the datasheet for authorized option byte combinations and a
detailed explanation.
Device type/memory size/package (check only one option)

FASTROM device 16 Kbyte 32 Kbyte
LQFP32 [ ] STM8S105K4 [ ] STM8S105K6
LQFP44 [ ] STM8S105S4 [ ] STM8S105S6
LQFP48 [ ] STM8S105C4 [ ] STM8S105C6
Conditioning (check only one option)

[ ] Tape and reel or [ ] Tray
Special marking (check only one option)

[ ] No [ ] Yes
Authorized characters are letters, digits, '.', '-', '/' and spaces only. Maximum character
counts are:
LQFP32: 2 lines of 7 characters max: _ _ _ _ _ _ _ and _ _ _ _ _ _ _
LQFP44: 2 lines of 7 characters max: _ _ _ _ _ _ _ and _ _ _ _ _ _ _
LQFP48: 2 lines of 8 characters max: _ _ _ _ _ _ _ _ and _ _ _ _ _ _ _ _
Temperature range
[ ] -40C to +85C or [ ] -40C to +125C
DocID14771 Rev 15 109/121

115
Padding value for unused program memory (check only one option)
[ ] 0xFF Fixed value
[ ] 0x83 TRAP instruction code
[ ] 0x75 Illegal opcode (causes a reset when executed)
OTP0 memory readout protection (check only one option)

[ ] Disable or [ ] Enable
OTP1 user boot code area (UBC)

0x(_ _) fill in the hexadecimal value, referring to the datasheet and the binary format below:
[ ] 0: Reset
UBC, bit0
[ ] 1: Set
[ ] 0: Reset
UBC, bit1
[ ] 1: Set
[ ] 0: Reset
UBC, bit2
[ ] 1: Set
[ ] 0: Reset
UBC, bit3
[ ] 1: Set
[ ] 0: Reset
UBC, bit4
[ ] 1: Set
[ ] 0: Reset
UBC, bit5
[ ] 1: Set
OTP2 alternate function remapping
[ ] 0: Remapping option inactive. Default alternate functions

AFR0
used. Refer to pinout description
(check only one option)
[ ] 1: Port D3 alternate function = ADC_ETR
AFR1 used. Refer to pinout description
(check only one option) [ ] 1: Port A3 alternate function = TIM3_CH1, port D2 alternate
function = TIM2_CH3
AFR2
[ ] 1: Port D0 alternate function = CLK_CCO
Note: if both AFR2 and AFR3 are activated, AFR2 option has
priority over AFR3.
AFR3
[ ] 1: Port D0 alternate function = TIM1_BKIN
110/121 DocID14771 Rev 15

STM8S105x4/6 Ordering information

AFR4
[ ] 1: Port D7 alternate function = TIM1_CH4
AFR5
[ ] 1: Port B3 alternate function = TIM1_ETR, port B2 alternate
function = TIM1_NCC3, port B1 alternate function =
TIM1_CH2N, port B0 alternate function = TIM1_CH1N.
AFR6 used. Refer to pinout description
(check only one option) [ ] 1: Port B5 alternate function = I2C_SDA, port B4 alternate
function = I2C_SCL
AFR6
[ ] 1: Port D4 alternate function = BEEP.
OPT3 watchdog
WWDG_HALT [ ] 0: No reset generated on halt if WWDG active[
(check only one option) [ ] 1: Reset generated on halt if WWDG active
WWDG_HW [ ] 0: WWDG activated by software
(check only one option) [ ] 1: WWDG activated by hardware
IWDG_HW [ ] 0: IWDG activated by software
(check only one option) [ ] 1: IWDG activated by hardware
LSI_EN [ ] 0: LSI clock is not available as CPU clock source
(check only one option) [ ] 1: LSI clock is available as CPU clock source
HSITRIM [ ] 0: 3-bit trimming supported in CLK_HSITRIMR register
(check only one option) [ ] 1: 4-bit trimming supported in CLK_HSITRIMR register
OPT4 watchdog
[ ] for 16 MHz to 128 kHz prescaler
PRSC
CKAWUSEL [ ] LSI clock source selected for AWU
(check only one option) [ ] HSE clock with prescaler selected as clock source for AWU
EXTCLK [ ] External crystal connected to OSCIN/OSCOUT
(check only one option) [ ] External signal on OSCIN
DocID14771 Rev 15 111/121

115
OPT5 crystal oscillator stabilization HSECNT (check only one option)

[ ] 2048 HSE cycles
[ ] 128 HSE cycles
[ ] 8 HSE cycles
[ ] 0.5 HSE cycles
OTP6 is reserved
OTP7 is reserved
OTPBL bootloader option byte (check only one option)

Refer to the UM0560 (STM8L/S bootloader manual) for more details.
[ ] Disable (00h)
[ ] Enable (55h)
Comments: .........................................................................................
Supply operating range in the application: .........................................................................................
Notes: .........................................................................................
Date: .........................................................................................
Signature: .........................................................................................
112/121 DocID14771 Rev 15

STM8S105x4/6 STM8 development tools
14 STM8 development tools
Development tools for the STM8 microcontrollers include the full-featured STice emulation
system supported by a complete software tool package including C compiler, assembler and
integrated development environment with high-level language debugger. In addition, the
STM8 is to be supported by a complete range of tools including starter kits, evaluation
boards and a low-cost in-circuit debugger/programmer.
14.1 Emulation and in-circuit debugging tools

The STice emulation system offers a complete range of emulation and in-circuit debugging
features on a platform that is designed for versatility and cost-effectiveness. In addition,
STM8 application development is supported by a low-cost in-circuit debugger/programmer.
The STice is the fourth generation of full featured emulators from STMicroelectronics. It
offers new advanced debugging capabilities including profiling and coverage to help detect
and eliminate bottlenecks in application execution and dead code when fine tuning an
application.
In addition, STice offers in-circuit debugging and programming of STM8 microcontrollers via
the STM8 single wire interface module (SWIM), which allows non-intrusive debugging of an
application while it runs on the target microcontroller.
For improved cost effectiveness, STice is based on a modular design that allows you to
order exactly what you need to meet your development requirements and to adapt your
emulation system to support existing and future ST microcontrollers.
14.1.1 STice key features

Occurrence and time profiling and code coverage (new features),
Advanced breakpoints with up to 4 levels of conditions,
Data breakpoints,
Program and data trace recording up to 128 KB records,
Read/write on the fly of memory during emulation,
In-circuit debugging/programming via SWIM protocol,
8-bit probe analyzer,
1 input and 2 output triggers,
Power supply follower managing application voltages between 1.62 to 5.5 V,
Modularity that allows you to specify the components you need to meet your
development requirements and adapt to future requirements.
Supported by free software tools that include integrated development environment
(IDE), programming software interface and assembler for STM8.
DocID14771 Rev 15 113/121

115
STM8 development tools STM8S105x4/6
14.2 Software tools

STM8 development tools are supported by a complete, free software package from
STMicroelectronics that includes ST Visual Develop (STVD) IDE and the ST Visual
Programmer (STVP) software interface. STVD provides seamless integration of the Cosmic
and Raisonance C compilers for STM8, which are available in a free version that outputs up
to 16 Kbytes of code.
14.2.1 STM8 toolset

The STM8 toolset with STVD integrated development environment and STVP programming
software is available for free download at www.st.com. This package includes:
ST visual develop
Full-featured integrated development environment from STMicroelectronics, featuring:
Seamless integration of C and ASM toolsets
Full-featured debugger
Project management
Syntax highlighting editor
Integrated programming interface
Support of advanced emulation features for STice such as code profiling and coverage
ST visual programmer (STVP)

Easy-to-use, unlimited graphical interface allowing read, write and verification of the STM8
Flash program memory, data EEPROM and option bytes. STVP also offers project mode for
the saving of programming configurations and the automation of programming sequences.
14.2.2 C and assembly toolchains

Control of C and assembly toolchains is seamlessly integrated into the STVD integrated
development environment, making it possible to configure and control the building of user
applications directly from an easy-to-use graphical interface.
Available toolchains include:
C compiler for STM8

Available in a free version that outputs up to 16 Kbytes of code. For more information, see
www.cosmic-software.com.
STM8 assembler linker

Free assembly toolchain included in the STVD toolset, used to assemble and link the user
application source code.
114/121 DocID14771 Rev 15

STM8S105x4/6 STM8 development tools
14.3 Programming tools

During the development cycle, STice provides in-circuit programming of the STM8 Flash
microcontroller on the application board via the SWIM protocol. Additional tools include a
low-cost in-circuit programmer as well as ST socket boards, which provide dedicated
programming platforms with sockets for the STM8 programming.
For production environments, programmers will include a complete range of gang and
automated programming solutions from third-party tool developers already supplying
programmers for the STM8 family.
DocID14771 Rev 15 115/121

115
Revision history STM8S105x4/6
15 Revision history
Table 57. Document revision history

Date Revision Changes
05-Jun-2018 1 Initial release.

Corrected the number of high sink outputs to 9 in I/Os in
Features.
23-Jun-2018 2
Updated part numbers in STM8S105xx access line
features.
Updated the part numbers in STM8S105xx access line
features.
12-Aug-2008 3 USART renamed UART1, LINUART renamed UART2.
Added Table: Pin-to-pin comparison of pin 7 to 12 in 32-
pin access line devices.
Removed STM8S102xx and STM8S104xx root part
numbers corresponding to devices without data
EEPROM.
Updated STM8S103 pinout section
17-Sep-2008 4
Added low and medium density Flash memory
categories.
Added Note 1 in Section: Current characteristics.
Updated Section: Option bytes.
Updated STM8S103 pinout.
Updated number of High Sink I/Os in the pinout section.
TSSOP20 pinout modified (PD4 moved to pin 1 etc.)
05-Feb-2009 5
Added WFQFN20 package
Updated Section: Option bytes.
Added Section: Memory and register map.
Removed STM8S103x products (separate STM8S103
27-Feb-2009 6 datasheet created).
Updated Section: Electrical characteristics.
116/121 DocID14771 Rev 15

STM8S105x4/6 Revision history
Table 57. Document revision history (continued)

Added SDIP32 silhouette and package to Features and

Section: SDIP32 package mechanical data; updated
Section: Pinout and pin description.
Updated VDD range (2.95 V to 5.5 V) on Features.
Amended name of package VQFPN32.
Added Table 5 on page 22.
Updated Section: Auto wakeup counter.
Updated pins 25, 30, and 31 in Section: Pinout and pin
description.
Removed Table 7: Pin-to-pin comparison of pin 7 to 12
in 32-pin access line devices.
Added Table: Description of alternate function
remapping bits [7:0] of OPT2.
12-May-2009 7 Section: Electrical characteristics: Updated VCAP
specifications; updated Table 15, Table 18, Table 20,
Table 21, Table 22, Table 23, Table 24, Table 25, Table
26, Table 27, Table 29, Table 35, and Table 42; added
current consumption curves; removed Figure 20: typical
HSE frequency vs fcpu @ 4 temperatures; updated
Figure 13, Figure 14, Figure 15, Figure 16 and Figure
17; modified HSI accuracy in Table 33 ; added Figure
44; modified fSCK, tV(SO) and tV(MO) in Table 42; updated
figures and tables of High speed internal RC oscillator
(HSI); replaced Figure 23, Figure 24, Figure 26, and
Figure 39.
Section Package information: updated Section: Thermal
characteristics and removed Table 57: Junction
temperature range. Updated Section: STM8S105xx
access line ordering information scheme.
Document status changed from preliminary data to
datasheet.
10-Jun-2009 8 Standardized the name of the VFQFPN package.
Removed wpu from I2C pins Section: Pinout and pin
description
DocID14771 Rev 15 117/121

120

Added UFQFPN32 package silhouette to the title page.

In Features: added unique ID.
Section: Clock controller: updated bit positions for TIM2
and TIM3.
Section: Beeper: added information about availability of
the beeper output port through option bit AFR7.
Section: Analog-to-digital converter (ADC1): added a
note concerning additional AIN12 analog input.
Section: STM8S105 pinouts and pin description: added
UFQFPN32 package details; updated default alternate
function of PB2/AIN2[TIM1_CH3N] pin in the "Pin
description for STM8S105 microcontrollers" table.
Section: Option bytes: added description of STM8L
bootloader option bytes to the option byte description
table.
Added Section: Unique ID
Section: Operating conditions: added introductory text;
removed low power dissipation condition for TA,
replaced "CEXT" by "VCAP", and added ESR and ESL
data in table "general operating conditions".
Section: Total current consumption in halt mode:
replaced max value of IDD(H) at 85 C from 20 A to 25
A for the condition "Flash in powerdown mode, HSI
21-Apr-2010 9 clock after wakeup in the table "total current
consumption in halt mode at VDD = 5 V.
Section: Low power mode wakeup times: added first
condition (0 to 16 MHz) for the tWU(WFI) parameter in the
table "wakeup times".
Section: Internal clock sources and timing
characteristics: In the table: HSI oscillator
characteristics, replaced min and max values of
ACCHSI factory calibrated parameter and removed
footnote 4 concerning further characterization of results.
Section: Functional EMS (electromagnetic
susceptibility): IEC 1000 replaced with IEC 61000.
Section: Designing hardened software to avoid noise
problems: IEC 1000 replaced with IEC 61000.
Section: Electromagnetic interference (EMI): SAE J
1752/3 replaced with IEC61967-2.
Section: Thermal characteristics: Replaced the thermal
resistance junction ambient temperature of LQFP32 7X7
mm from 59 C to 60 C in the thermal characteristics
table.
Added Section: 32-lead UFQFPN package mechanical
data.
Added Section STM8S105 FASTROM microcontroller
option list.
118/121 DocID14771 Rev 15

STM8S105x4/6 Revision history

Table: Legend/Abbreviations for pinout tables: updated

"reset state"; removed "HS", (T), and "[ ]".
Section: Pin description for STM8S105 microcontrollers:
added footnotes to the PF4 and PD1 pins.
Table: I/O port hardware register map: changed reset
status of Px_IDR from 0x00 to 0xXX.
Table: General hardware register map: Standardized all
address and reset state values; updated the reset state
values of the RST_SR, CLK_SWCR, CLK_HSITRIMR,
CLK_SWIMCCR, IWDG_KR, UART2_DR, and
ADC_DRx registers; replaced reserved address "0x00
5248" with the UART2_CR5.
21-Sep-2010 10 Section: Recommended reset pin protection: replaced
0.01 F with 0.1 F
Updated Figure: Typical application with I2C bus and
timing diagram.
Updated Table: ADC accuracy with RAIN < 10 kohm ,
VDDA = 5 V footnote 1 in and Table: ADC accuracy with
RAIN < 10 kohm RAIN, VDDA = 3.3 V.
Section: STM8S105 FASTROM microcontroller option
list: removed bits 6 and 7 from OPT1 user boot code
area (UBC); added "disable" to 00h and "enable" to 55h
of OPTBL bootloader option byte.
Section: VFQFPN Package Mechanical data: replaced
note 1 and added note 2.
Removed VFQFPN32 package.
Modified Section: Description.
Remove weak pull-up input for PE1 and PE2 in Table:
Pin description for STM8S105 microcontrollers
Updated Table: Interrupt mapping for TIM2 and TIM4.
Updated notes related to VCAP in xm-replace_text
General operating conditions.
Added values of tR/tF for 50 pF load capacitance, and
04-Apr-2012 11 updated note in Section: I/O static characteristics.
Updated typical and maximum values of RPU in Table:
I/O static characteristics and Table: RST pin
characteristics.
Changed SCK input to SCK output in Table: SPI serial
peripheral interface.
Added JA for UFQFPN32 and SDIP32 in Table:
Thermal characteristics, and updated Section: Selecting
the product temperature range
Added UFQFPN package thickness in Figure:
28-Jun-2012 12
STM8S105xx access line ordering information scheme
DocID14771 Rev 15 119/121

120

UART2_CK mapped to correct pin (pin 24) in Figure:

LQFP 44-pin pinout.
07-Feb-2014 13 Reserved area updated in Table: Option bytes.
Package Information updated in Table: 32-lead ultra thin
fine pitch quad flat no-lead package mechanical data.
Added:
Figure 49: LQFP48 marking example (package top
view),
view),
view),
01-Jul-2015 14 Figure 58: UFQFPN32 marking example (package top
view),
Figure 60: SDIP32 marking example (package top
view).
Updated:
Figure 41: SPI timing diagram where slave mode and
CPHA = 0,
the standard for EMI data in Table 48: EMI data.
Added the footnotes related to Figure 56: UFQFPN32 -
23-Sep-2015 15 32-pin, 5x5 mm, 0.5 mm pitch ultra thin fine pitch quad
flat package outline.
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STM8S105x4/6
IMPORTANT NOTICE PLEASE READ CAREFULLY
STMicroelectronics NV and its subsidiaries (ST) reserve the right to make changes, corrections, enhancements, modifications, and
improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on
ST products before placing orders. ST products are sold pursuant to STs terms and conditions of sale in place at the time of order
acknowledgement.
Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or
the design of Purchasers products.
No license, express or implied, to any intellectual property right is granted by ST herein.
Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.
ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners.
Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
2015 STMicroelectronics All rights reserved
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STM8S105C4/6 STM8S105K4/6

Program memory: up to 32 Kbyte Flash; data

September 2015 DocID14771 Rev 15 1/121

5 Pinout and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

6 Memory and register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

2/121 DocID14771 Rev 15

6.2.3 CPU/SWIM/debug module/interrupt controller registers . . . . . . . . . . . . 42

7 Interrupt vector mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

DocID14771 Rev 15 3/121

11.5 SDIP32 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

12 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

13 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

14 STM8 development tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

15 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

4/121 DocID14771 Rev 15

Table 1. STM8S105x4/6 access line features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

DocID14771 Rev 15 5/121

Table 49. ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

6/121 DocID14771 Rev 15

Figure 1. STM8S105x4/6 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

DocID14771 Rev 15 7/121

8/121 DocID14771 Rev 15

DocID14771 Rev 15 9/121

10/121 DocID14771 Rev 15

Table 1. STM8S105x4/6 access line features

DocID14771 Rev 15 11/121

Figure 1. STM8S105x4/6 block diagram

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12/121 DocID14771 Rev 15

4.1 Central processing unit STM8

Architecture and registers

DocID14771 Rev 15 13/121

4.3 Interrupt controller

4.4 Flash program and data EEPROM memory

Write protection (WP)

14/121 DocID14771 Rev 15

Figure 2. Flash memory organization

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Read-out protection (ROP)

DocID14771 Rev 15 15/121

4.5 Clock controller

Table 2. Peripheral clock gating bit assignments in CLK_PCKENR1/2 registers

PCKEN17 TIM1 PCKEN13 UART2 PCKEN27 Reserved PCKEN23 ADC

16/121 DocID14771 Rev 15

4.6 Power management

4.7 Watchdog timers

Window watchdog timer

Independent watchdog timer

DocID14771 Rev 15 17/121

The IWDG time base spans from 60 s to 1 s.

4.8 Auto wakeup counter

4.10 TIM1 - 16-bit advanced control timer

4.11 TIM2, TIM3 - 16-bit general purpose timers

18/121 DocID14771 Rev 15

4.12 TIM4 - 8-bit basic timer

Table 3. TIM timer features

4.13 Analog-to-digital converter (ADC1)

DocID14771 Rev 15 19/121

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