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INA118
SBOS027A SEPTEMBER 2000 REVISED JANUARY 2016

INA118 Precision, Low Power Instrumentation Amplifier

1 Features 3 Description

1 Low Offset Voltage: 50-V Maximum The INA118 is a low-power, general-purpose

instrumentation amplifier offering excellent accuracy.
Low Drift: 0.5-V/C Maximum The device's versatile, 3-op amp design and small
Low Input Bias Current: 5-nA Maximum size make it ideal for a wide range of applications.
High CMR: 110-dB Minimum Current-feedback input circuitry provides wide
Inputs Protected to 40 V bandwidth, even at high gain (70 kHz at G = 100).
Wide Supply Range: 1.35 to 18 V A single external resistor sets any gain from 1 to
10000. Internal input protection can withstand up to
Low Quiescent Current: 350-A
40 V without damage.
8-Pin Plastic DIP, SO-8
The INA118 is laser-trimmed for low offset voltage
2 Applications (50 V), drift (0.5 V/C), and high common-mode
rejection (110 dB at G = 1000). The INA118 operates
Bridge Amplifiers with power supplies as low as 1.35 V, and quiescent
Thermocouple Amplifiers current is only 350 A, making the device ideal for
battery-operated systems.
RTD Sensor Amplifiers
Medical Instrumentation The INA118 is available in 8-pin plastic DIP and SO-8
surface-mount packages, specified for the 40C to
Data Acquisition
+85C temperature range.

Device Information(1)
PART NUMBER PACKAGE BODY SIZE (NOM)
SOIC (8) 3.91 mm 4.90 mm
INA118
PDIP (8) 6.35 mm 9.81 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.

Simplified Schematic
V+
7

2 Over-Voltage INA118
VIN
Protection
A1 50k
G=1+
60k 60k RG
1
25k

6
RG A3 VO

8
25k

5
A2 Ref
+ 3 Over-Voltage
VIN 60k 60k
Protection

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
INA118
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Table of Contents
1 Features .................................................................. 1 8 Application and Implementation ........................ 13
2 Applications ........................................................... 1 8.1 Application Information............................................ 13
3 Description ............................................................. 1 8.2 Typical Application ................................................. 13
4 Revision History..................................................... 2 9 Power Supply Recommendations...................... 17
5 Pin Configuration and Functions ......................... 3 9.1 Low Voltage Operation ........................................... 17
9.2 Single Supply Operation ......................................... 18
6 Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4 10 Layout................................................................... 19
6.2 ESD Ratings ............................................................ 4 10.1 Layout Guidelines ................................................. 19
6.3 Recommended Operating Conditions....................... 4 10.2 Layout Example .................................................... 20
6.4 Thermal Information .................................................. 4 11 Device and Documentation Support ................. 21
6.5 Electrical Characteristics........................................... 5 11.1 Device Support .................................................... 21
6.6 Typical Characteristics .............................................. 7 11.2 Documentation Support ........................................ 21
7 Detailed Description ............................................ 11 11.3 Community Resources.......................................... 21
7.1 Overview ................................................................. 11 11.4 Trademarks ........................................................... 21
7.2 Functional Block Diagram ....................................... 11 11.5 Electrostatic Discharge Caution ............................ 21
7.3 Feature Description................................................. 11 11.6 Glossary ................................................................ 21
7.4 Device Functional Modes........................................ 11 12 Mechanical, Packaging, and Orderable
Information ........................................................... 21

4 Revision History
Changes from Original (September 2000) to Revision A Page

Added ESD Ratings table, Feature Description section, Device Functional Modes section, Application and
Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation
Support section, and Mechanical, Packaging, and Orderable Information section. .............................................................. 1

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5 Pin Configuration and Functions

P and D Packages
8-Pin PDIP and SOIC
Top View

RG 1 8 RG

VIN 2 7 V+
+
V IN 3 6 VO

V 4 5 Ref

Pin Functions
PIN
I/O DESCRIPTION
NO. NAME
1 RG Gain setting pin. For gains greater than 1, place a gain resistor between pin 1 and pin 8.
2 VIN I Negative input
+
3 V IN I Positive input
4 V Negative supply
5 Ref I Reference input. This pin must be driven by low impedance or connected to ground.
6 VO O Output
7 V+ Positive supply
8 RG Gain setting pin. For gains greater than 1, place a gain resistor between pin 1 and pin 8.

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6 Specifications
6.1 Absolute Maximum Ratings
(1)
over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
Supply voltage 18 V
Analog input voltage 40 V
Output short-circuit (to ground) Continuous
Operating temperature 40 125 C
Junction temperature 150 C
Lead temperature (soldering, 10 s) 300 C
Tstg Storage temperature 40 125 C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

VALUE UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) 1000
V(ESD) Electrostatic discharge Charged-device model (CDM), per JEDEC specification JESD22- V
500
C101 (2)

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
V Power supply 2.25 15 18 V
VO = 0 Input common-mode voltage V + 1.1 V+ 1 V
TA Ambient temperature 55 150 C

6.4 Thermal Information

INA118
THERMAL METRIC (1) D (SOIC) P (PDIP) UNIT
8 PINS 8 PINS
RJA Junction-to-ambient thermal resistance 115 48 C/W
RJC(top) Junction-to-case (top) thermal resistance 62 37 C/W
RJB Junction-to-board thermal resistance 59 25 C/W
JT Junction-to-top characterization parameter 14 14 C/W
JB Junction-to-board characterization parameter 58 25 C/W
RJC(bot) Junction-to-case (bottom) thermal resistance N/A N/A C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.

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6.5 Electrical Characteristics

at TA = 25C, VS = 15 V, RL = 10 k unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
INPUT
INA118PB, UB 10 50/G 50 500/G
Initial TA = 25C 1251000/ V
INA118P, U 25 100/G
G
INA118PB, UB 0.2 2/G 0.5 20/G
Offset voltage, RTI vs Temperature TA = TMIN to TMAX V/C
INA118P, U 0.2 5/G 1 20/G
INA118PB, UB 1 10/G 5 100/G
vs Power supply VS = 1.35 V to 18 V V/V
INA118P, U 1 10/G 10 100/G
Long-term stability 0.4 5/G V/mo
Differential 10
10 || 1
Impedance || pF
Common-mode 1010 || 4
(V+) 1 (V+) 0.65
Linear input voltage range V

(V ) + 1.1 (V) + 0.95
Safe input voltage 40 V

VCM = 10 V, RS = 1 INA118PB, UB 80 90
k, G = 1 INA118P, U 73 90

VCM = 10 V, RS = 1 INA118PB, UB 97 110

k, G = 10 INA118P, U 89 110
Common-mode rejection dB
VCM = 10 V, RS = 1 INA118PB, UB 107 120
k, G = 100 INA118P, U 98 120

VCM = 10 V, RS = 1 INA118PB, UB 110 125

k, G = 1000 INA118P, U 100 125
INA118PB, UB 1 5
BIAS CURRENT nA
INA118P, U 1 10
vs temperature 40 pA/C
INA118PB, UB 1 5
OFFSET CURRENT nA
INA118P, U 1 10
vs temperature 40 pA/C
NOISE VOLTAGE, RTI
f = 10 Hz 11 nV/Hz
f = 100 Hz 10 nV/Hz
G = 1000, RS = 0
f = 1 kHz 10 nV/Hz
fB = 0.1 Hz to 10 Hz 0.28 Vp-p
f = 10 Hz 2
pA/Hz
Noise current f = 1 kHz 0.3
fB = 0.1 Hz to 10 Hz 80 pAp-p
GAIN
Gain equation 1 + (50 k/RG) V/V
Range of gain 1 10000 V/V
G=1 0.01% 0.024%
G = 10 0.02% 0.4%
Gain error
G = 100 0.05% 0.5%
G = 1000 0.5% 1%
Gain vs temperature G=1 1 10 ppm/C
50-k resistance (1) 25 100 ppm/C
G=1 0.0003 0.001
G = 10 0.0005 0.002
Nonlinearity % of FSR
G = 100 0.0005 0.002
G = 1000 0.002 0.01

(1) Temperature coefficient of the 50-k term in the gain equation.

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Electrical Characteristics (continued)

at TA = 25C, VS = 15 V, RL = 10 k unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
OUTPUT
Positive (V+) 1 (V+) 0.8
RL = 10 k

Negative (V ) + 0.35 (V) + 0.2 V
Voltage:
Single supply high 1.8 2
VS = 2.7 V/0 V (2), RL = 10 k
Single supply low 60 35 mV
Load capacitance stability 1000 pF
Short circuit current +5/12 mA
FREQUENCY RESPONSE
G=1 800
G = 10 500
Bandwidth, 3 dB kHz
G = 100 70
G = 1000 7
Slew rate VO = 10 V, G = 10 0.9 V/s
G=1 15
G = 10 15
Settling time, 0.01% s
G = 100 21
G = 1000 210
Overload recovery 50% Overdrive 20 s
POWER SUPPLY
Voltage range 1.35 15 18 V
Current VIN = 0 V 350 385 A
TEMPERATURE RANGE
Specification 40 85 C
Operating 40 125 C

(2) Common-mode input voltage range is limited. See text for discussion of low power supply and single power supply operation.

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6.6 Typical Characteristics

at TA = 25C, VS = 15 V (unless otherwise noted).

60 140
G = 1000
50

Common-Mode Rejection (dB)

120
40 G=1000
G = 100 100
G=100
30
Gain (dB)

80
G=10
20
G = 10 60
10 G=1
40
0
G=1
10 20

20 0
1k 10k 100k 1M 10M 1 10 100 1k 10k 100k
Frequency (Hz) Frequency (Hz)

Figure 1. Gain vs Frequency Figure 2. Common-Mode Rejection vs Frequency

15 5
G 10 G 10 G 10 G 10
4
10
Common-Mode Voltage (V)
Common-Mode Voltage (V)

3
G=1 G=1 G=1 G=1
2
5
+5V
+15V 1

VD/2 VO
VD/2 VO
0 + INA118 0 +
INA118
VD/2
VD/2 1 Ref
+ Ref +
5 VCM
VCM 2 5V
15V
3
10
All All 4 All All
Gains Gains Gains Gains
15 5
15 10 5 0 5 10 15 5 4 3 2 1 0 1 2 3 4 5
Output Voltage (V) Output Voltage (V)

Figure 3. Input Common-Mode Range vs Output Voltage Figure 4. Input Common-Mode Range vs Output Voltage
5 3

G 10 G 10
Common-Mode Voltage (V)

Common-Mode Voltage (V)

G=2 2
3 G=1
G=1 Single Supply
Single Supply
+3V
2 +5V
1 VD/2 VO
VD/2 VO + INA118
+
INA118 VD/2
1 VD/2 + Ref
+ Ref
VCM
VCM

0 0
0 1 2 3 4 5 0 1 2 3
Output Voltage (V) Output Voltage (V)

Figure 5. Input Common-Mode Range vs Output Voltage Figure 6. Input Common-Mode Range vs Output Voltage

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Typical Characteristics (continued)

at TA = 25C, VS = 15 V (unless otherwise noted).
160 160

140 140
G = 1000

Power Supply Rejection (dB)

Power Supply Rejection (dB)

120 120 G = 100

100 100 G = 10
G = 1000
80 80
G = 100 G=1
60 60
G = 10
40 G=1 40

20 20

0 0
1 10 100 1k 10k 100k 10 100 1k 10k 100k
Frequency (Hz) Frequency (Hz)

Figure 7. Positive Power Supply Rejection vs Frequency Figure 8. Negative Power Supply Rejection vs Frequency
1k 100 1000
Input-Referred Noise Voltage (nV/ Hz)

Input Bias Current Noise (pA/ Hz)

G=1
RL = 10k
Settling Time (s)

100 10
CL = 100pF

100
G = 10
G = 100, 1000 0.01%
10 1
G = 1000 BW Limit
0.1%
Current Noise
(All Gains)
1 0.1 10
1 10 100 1k 10k 1 10 100 1000
Frequency (Hz) Gain (V/V)

Figure 9. Input-Referred Noise Voltage vs Frequency Figure 10. Settling Time vs Gain
500 1.5 10
8
6
Quiescent Current (A)

Input Bias Current (mA)

ate
lew R 4
Slew Rate (V/s)

400 S 1
2
G = 1000
0 G=1
VS = 15V
IQ 2
300 0.5 G=1 G = 1000
4
VS = 1.35V
6
8
200 0 10
75 50 25 0 25 50 75 100 125 40 0 40
Temperature (C) Overload Voltage (V)

Figure 11. Quiescent Current and Slew Rate vs Temperature Figure 12. Input Bias Current vs Input Overload Voltage

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Typical Characteristics (continued)

at TA = 25C, VS = 15 V (unless otherwise noted).
10 5

Input Bias and Offset Current (nA)

8 4
IOS
Offset Voltage Change (V)

6 3
4 2
G = 1000 I b
2 1
0 0
2 1
4 2
6 3
8 4
10 5
0 0.5 1.0 1.5 2.0 2.5 3.0
75 50 25 0 25 50 75 100 125
Time from Power Supply Turn On (ms) Temperature (C)

Figure 13. Offset Voltage vs Warm-Up Time Figure 14. Input Bias and Offset Current vs Temperature
V+ V+
(V+) 0.2
Positive
(V+) 0.4 (V+) 0.4
Positive
Output Voltage Swing (V)

Output Voltage Swing (V)

VS 5V +85C +25C
(V+) 0.6
(V+) 0.8 (V+) 0.8
(V+) 1 40C
VS = 15V RL = 10k

(V) +0.4 +85C

(V)+0.8
Negative
+25C
Single Power Supply, V = 0V
(V)+0.4 (V) +0.2
Ground-Referred Load Negative
40C
V V
0 1 2 3 4 0 5 10 15 20
Output Current (mA) Power Supply Voltage (V)

Figure 15. Output Voltage Swing vs Output Current Figure 16. Output Voltage Swing vs Power Supply Voltage
16 32 G = 10, 100
Peak-to-Peak Output Voltage (V)

14 28 G=1
|ICL|
Short Circuit Current (mA)

12 24

10 20

8 16
G = 1000
6 12
+|ICL|
4 8

2 4

0 0
75 50 25 0 25 50 75 100 125 100 1k 10k 100k 1M
Temperature (C) Frequency (Hz)

Figure 17. Output Current Limit vs Temperature Figure 18. Maximum Output Swing vs Frequency

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Typical Characteristics (continued)

at TA = 25C, VS = 15 V (unless otherwise noted).
1

G = 10

0.1
THD + N (%)

0k
=1
RL
0.1V/div

0.01

(Noise Floor) RL =

0.001
20 100 1k 10k 20k
1s/div
Frequency (Hz)

Figure 19. THD + N vs Frequency Figure 20. Input-Referred Noise, 0.1 Hz to 10 Hz

G=1
G = 100

20mV/div 20mV/div

G = 10
G = 1000

10s/div
\ 100s/div

Figure 21. Small-Signal Response Figure 22. Small-Signal Response

G=1 G = 100

5V/div 5V/div

G = 10 G = 1000

100s/div 100s/div

Figure 23. Large-Signal Response Figure 24. Large-Signal Response

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7 Detailed Description

7.1 Overview
Figure 25 shows a simplified representation of the INA118 and provides insight into its operation. Each input is
protected by two FET transistors that provide a low series resistance under normal signal conditions, preserving
excellent noise performance. When excessive voltage is applied, these transistors limit input current to
approximately 1.5 to 5 mA.
The differential input voltage is buffered by Q1 and Q2 and impressed across RG, causing a signal current to flow
through RG, R1 and R2. The output difference amp, A3, removes the common-mode component of the input
signal and refers the output signal to the Ref terminal.
The equations in Figure 25 describe the output voltages of A1 and A2. The VBE and IR drop across R1 and R2
produce output voltages on A1 and A2 that are approximately 1-V lower than the input voltages.

7.2 Functional Block Diagram

A1 Out = VCM VBE (10A 25k) V O/2

A2 Out = VCM VBE (10A 25k) + V O/2
Output Swing Range A 1, A 2; (V+) 0.65V to (V) + 0.06V
Amplifier Linear Input Range: (V+) 0.65V to (V) + 0.98V

10A VB 10A
+
VO = G (VIN VIN)

Output Swing Range:

(V+) 0.8V to (V) + 0.35V
Input Bias Current A1 A2
Compensation C1 C2 60k

60k

60k A3 VO

60k

VIN Ref
Q1 R1 R2 Q2
25k 25k
VD/2 RG

(External)

VCM VD/2

+
VIN

Figure 25. INA118 Simplified Circuit Diagram

7.3 Feature Description

The INA118 input sections use junction field effect transistors (JFET) connected to provide protection up to
40 V. The current-feedback architecture provides maximum bandwidth over the full range of gain settings.

7.4 Device Functional Modes

7.4.1 Noise Performance

The INA118 provides low noise in most applications. For differential source impedances less than 1 k, the
INA103 may provide lower noise. For source impedances greater than 50 k, the INA111 FET-Input
Instrumentation Amplifier may provide lower noise.

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Device Functional Modes (continued)

Low-frequency noise of the INA118 is approximately 0.28 Vp-p, measured from 0.1 to 10 Hz (G100). This
provides dramatically improved noise when compared to state-of-the-art chopper-stabilized amplifiers.

7.4.2 Input Common-Mode Range

The linear input voltage range of the input circuitry of the INA118 is from approximately 0.6-V less than the
positive supply voltage to 1-V greater than the negative supply. As a differential input voltage causes the output
voltage to increase, however, the linear input range is limited by the output voltage swing of amplifiers A1 and A2.
Thus, the linear common-mode input range is related to the output voltage of the complete amplifier. This
behavior also depends on supply voltage; see Figure 6.
Input-overload can produce an output voltage that appears normal. For example, if an input overload condition
drives both input amplifiers to their positive output swing limit, the difference voltage measured by the output
amplifier is near zero. The output of the INA118 is near 0 V even though both inputs are overloaded.

7.4.3 Input Protection

The inputs of the INA118 are individually protected for voltages up to 40 V. For example, a condition of 40 V
on one input and +40 V on the other input does not cause damage. Internal circuitry on each input provides low
series impedance under normal signal conditions. To provide equivalent protection, series input resistors would
contribute excessive noise. If the input is overloaded, the protection circuitry limits the input current to a safe
value of approximately 1.5 to 5 mA. Figure 12 shows this input current limit behavior. The inputs are protected
even if the power supplies are disconnected or turned off.

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8 Application and Implementation

NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TIs customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.

8.1 Application Information

The INA118 measures a small differential voltage with a high common-mode voltage developed between the
noninverting and inverting input. The high common-mode rejection makes the INA118 suitable for a wide range
of applications. The ability to set the reference pin to adjust the functionality of the output signal offers additional
flexibility that is practical for multiple configurations

8.2 Typical Application

Figure 26 shows the basic connections required for operation of the INA118. Applications with noisy or high
impedance power supplies may require decoupling capacitors close to the device pins as shown. The output is
referred to the output reference (Ref) terminal, which is normally grounded. This must be a low-impedance
connection to assure good common-mode rejection. A resistance of 12 in series with the Ref pin causes a
typical device to degrade to approximately 80-dB CMR (G = 1).
Figure 26 depicts an input signal with a 5-mV, 1-kHz signal with a 1-Vp-p common-mode signal, a condition often
observed in process control systems. Figure 27 depicts the output of the INA118 (gain = 250) depicting the clean
recovered 1-kHz waveform.
V+

0.1F

2 Over-Voltage INA118
VIN
Protection
A1
DESIRED RG NEAREST 1% RG W +
VO = G (VIN VIN )
60k 60k
GAIN ( ) () 1 50k
25k G=1+
1 NC NC RG
2 50.00k 49.9k 6
5 12.50k 12.4k RG A3
10 5.556k 5.62k +
8
20 2.632k 2.61k 25k Load VO
50 1.02k 1.02k
100 505.1 511 5
A2
200 251.3 249 + 3 Over-Voltage Ref
500 100.2 100 VIN 60k 60k
Protection
1000 50.05 49.9
2000 25.01 24.9
4 0.1F
5000 10.00 10
10000 5.001 4.99

NC: No Connection.
V
Also drawn in simplified form:

VIN

RG INA118 VO

+ Ref
VIN

Figure 26. Basic Connections

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Typical Application (continued)

8.2.1 Design Requirements
Figure 30 and Figure 29 depict the performance of a typical application of the INA118 in a shop floor vibration
sensing application. Because industrial process control systems often involve the interconnecting of multiple
subsystems, ground loops are frequently encountered and often are not easily solved. The inherent common-
mode rejection of instrumentation amplifiers enables accurate measurements even in the presence of ground
loop potentials.
The typical application was tested in a system with these requirements:
Transducer signal 5 mVp-p
Transducer center frequency = 1 kHz
Common-Mode signal (required to be rejected): 1 Vp-p at 60 Hz

8.2.2 Detailed Design Procedure

8.2.2.1 Setting the Gain

As shown in Equation 1, the gain of the INA118 is set by connecting a single external resistor, RG, connected
between pins 1 and 8.
50k
G=1+
RG (1)
Commonly used gains and resistor values are shown in Figure 26.
The 50-k term in Equation 1 comes from the sum of the two internal feedback resistors of A1 and A2. These on-
chip metal film resistors are laser-trimmed to accurate absolute values. The accuracy and temperature coefficient
of these resistors are included in the gain accuracy and drift specifications of the INA118.
The stability and temperature drift of the external gain setting resistor, RG, also affects gain. The contribution of
RG to gain accuracy and drift can be directly inferred from Equation 1. Low resistor values required for high gain
can make wiring resistance important. Sockets add to the wiring resistance, which contributes additional gain
error (possibly an unstable gain error) in gains of approximately 100 or greater.

8.2.2.2 Dynamic Performance

The Figure 1 shows that, despite its low quiescent current, the INA118 achieves wide bandwidth, even at high
gain. This is due to the current-feedback topology of the INA118. Settling time also remains excellent at high
gain.
The INA118 exhibits approximately 3-dB peaking at 500 kHz in unity gain. This is a result of its current-feedback
topology and is not an indication of instability. Unlike an op amp with poor phase margin, the rise in response is a
predictable 6-dB/octave due to a response zero. A simple pole at 300 kHz or lower produces a flat passband
unity gain response.

8.2.2.3 Offset Trimming

The INA118 is laser-trimmed for low offset voltage and drift. Most applications require no external offset
adjustment. Figure 27 shows an optional circuit for trimming the output offset voltage. The voltage applied to the
Ref terminal is summed at the output. The op amp buffer provides low impedance at the Ref terminal to preserve
good common-mode rejection.

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Typical Application (continued)

VIN

V+
RG INA118 VO
100A
+ Ref 1/2 REF200
VIN

100
OPA177
10mV 10k
Adjustment Range
100

100A
1/2 REF200

Figure 27. Optional Trimming of Output Offset Voltage

8.2.2.4 Input Bias Current Return Path

The input impedance of the INA118 is extremely high at approximately 1010 . However, a path must be
provided for the input bias current of both inputs. This input bias current is approximately 5 nA. High input
impedance means that this input bias current changes very little with varying input voltage.
Input circuitry must provide a path for this input bias current for proper operation. Figure 28 shows various
provisions for an input bias current path. Without a bias current path, the inputs float to a potential which exceeds
the common-mode range of the INA118, and the input amplifiers saturates.
If the differential source resistance is low, the bias current return path can be connected to one input (see the
thermocouple example in Figure 28). With higher source impedance, using two equal resistors provides a
balanced input, with the possible advantages of lower input offset voltage due to bias current, and better high-
frequency common-mode rejection.

Copyright 20002016, Texas Instruments Incorporated Submit Documentation Feedback 15

Product Folder Links: INA118
INA118
SBOS027A SEPTEMBER 2000 REVISED JANUARY 2016 www.ti.com

Typical Application (continued)

Microphone,
Hydrophone INA118
etc.

47k 47k

Thermocouple INA118

10k

INA118

Center-tap provides
bias current return.

Figure 28. Providing an Input Common-Mode Current Path

8.2.3 Application Curves

1-kHz differential signal is also present but cannot be seen in this

waveform.
Figure 29. Input of Typical Application Showing 60-Hz Figure 30. Output of Typical Application Shows Desired
Common-Mode Signal 1-kHz Waveform With
Common-Mode Interference Rejected

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 INA118
www.ti.com SBOS027A SEPTEMBER 2000 REVISED JANUARY 2016

9 Power Supply Recommendations

9.1 Low Voltage Operation

The INA118 can be operated on power supplies as low as 1.35 V. Performance of the INA118 remains
excellent with power supplies ranging from 1.35 V to 18 V. Most parameters vary only slightly throughout this
supply voltage range; see Typical Characteristics. Operation at low supply voltage requires careful attention to
assure that the input voltages remain within their linear range. Voltage swing requirements of internal nodes limit
the input common-mode range with low power supply voltage. Figure 3 shows the range of linear operation for a
various supply voltages and gains.

VO
VIN RG INA118
+
Ref R1
C1
1M
0.1F

1
f3dB =
OPA602 2R1C1
= 1.59Hz

Figure 31. AC-Coupled Instrumentation Amplifier

V+
10.0V 6
REF102 2

R1 R2

Pt100

Cu
K VO
Cu RG INA118

R3 Ref
100 = RTD at 0C

ISA COEFFICIENT
TYPE MATERIAL (V/C) R1 , R 2
E + Chromel 58.5 66.5k
Constantan
J + Iron 50.2 76.8k
Constantan
K + Chromel 39.4 97.6k
Alumel
T + Copper 38.0 102k
Constantan

Figure 32. Thermocouple Amplifier With Cold Junction Compensation

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SBOS027A SEPTEMBER 2000 REVISED JANUARY 2016 www.ti.com

Low Voltage Operation (continued)

VIN
R1 IO = G
R1
VIN RG INA118
+
Ref
IB

A1 IO
Load
A1 IB Error
OPA177 1.5nA
OPA602 1pA
OPA128 75fA

Figure 33. Differential Voltage to Current Converter

2.8k

VO
LA RG/2 INA118
RA
Ref
2.8k G = 10
390k
1/2
1/2 OPA2604
RL OPA2604 10k
390k

Figure 34. ECG Amplifier With Right-Leg Drive

9.2 Single Supply Operation

The INA118 can be used on single power supplies of 2.7 V to 36 V. Figure 35 shows a basic single supply
circuit. The output Ref terminal is connected to ground. Zero differential input voltage demands an output voltage
of 0 V (ground). Actual output voltage swing is limited to approximately 35-mV above ground, when the load is
referred to ground as shown. Figure 15 shows how the output voltage swing varies with output current.
With single supply operation, V+IN and VIN must both be 0.98-V above ground for linear operation. It is not
possible, for example, to connect the inverting input to ground and measure a voltage connected to the
noninverting input.
To illustrate the issues affecting low voltage operation, consider the circuit in Figure 35, which shows the INA118
operating from a single 3-V supply. A resistor in series with the low side of the bridge assures that the bridge
output voltage is within the common-mode range of the amplifiers inputs. See Figure 3 for 3-V single supply
operation.

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 INA118
www.ti.com SBOS027A SEPTEMBER 2000 REVISED JANUARY 2016

Single Supply Operation (continued)

+3V 3V

2V DV

RG INA118 VO
300
Ref
2V + DV

150
R1 (1)

NOTE: (1) R1 required to create proper common-mode voltage,

only for low voltage operation see text.

Figure 35. Single-Supply Bridge Amplifier

10 Layout

10.1 Layout Guidelines

TI always recommends paying attention to good layout practices. For best operational performance of the device,
use good printed-circuit-board (PCB) layout practices, including:
Take care to ensure that both input paths are well-matched for source impedance and capacitance to avoid
converting common-mode signals into differential signals. In addition, parasitic capacitance at the gain-setting
pins can also affect CMRR over frequency. For example, in applications that implement gain switching using
switches or PhotoMOS relays to change the value of RG, select the component so that the switch
capacitance is as small as possible.
Noise can propagate into analog circuitry through the power pins of the circuit as a whole, and of the device
itself. Bypass capacitors are used to reduce the coupled noise by providing low-impedance power sources
local to the analog circuitry. Connect low-ESR, 0.1-F ceramic bypass capacitors between each supply pin
and ground, placed as close to the device as possible. A single bypass capacitor from V+ to ground is
applicable for single-supply applications.
Separate grounding for analog and digital portions of the circuitry is one of the simplest and most effective
methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes.
A ground plane helps distribute heat and reduces EMI noise pickup. Make sure to physically separate digital
and analog grounds, paying attention to the flow of the ground current. For more detailed information, see
Circuit Board Layout Techniques (SLOA089).
To reduce parasitic coupling, run the input traces as far away from the supply or output traces as possible. If
these traces cannot be kept separate, crossing the sensitive trace perpendicular is much better than in
parallel with the noisy trace.
Keep the traces as short as possible.

Copyright 20002016, Texas Instruments Incorporated Submit Documentation Feedback 19

Product Folder Links: INA118
INA118
SBOS027A SEPTEMBER 2000 REVISED JANUARY 2016 www.ti.com

10.2 Layout Example

Gain Resistor

Bypass
Capacitor
RG RG
- V+
VIN V-IN V+
V+IN VO VOUT
VIN
+
V- Ref
GND

Bypass
Capacitor

V- GND
Figure 36. Layout Recommendation

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Product Folder Links: INA118

 INA118
www.ti.com SBOS027A SEPTEMBER 2000 REVISED JANUARY 2016

11 Device and Documentation Support

11.1 Device Support

11.1.1 Development Support

Table 1. Design Kits and Evaluation Modules

NAME PART NUMBER TYPE
DIP Adapter Evaluation Module DIP-ADAPTER-EVM Evaluation Modules and Boards
Universal Instrumentation Amplifier Evaluation
INAEVM Evaluation Modules and Boards
Module

Table 2. Development Tools

NAME PART NUMBER TYPE
Calculate Input Common-Mode Range of
INA-CMV-CALC Calculation Tools
Instrumentation Amplifiers
SPICE-Based Analog Simulation Program TINA-TI Circuit Design and Simulation

11.2 Documentation Support

11.2.1 Related Documentation

For related documentation, refer to the following:

Circuit Board Layout Techniques (SLOA089)

11.3 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.

11.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.

11.6 Glossary
SLYZ022 TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

Copyright 20002016, Texas Instruments Incorporated Submit Documentation Feedback 21

Product Folder Links: INA118
 PACKAGE OPTION ADDENDUM

www.ti.com 25-Oct-2016

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)

INA118P ACTIVE PDIP P 8 50 Green (RoHS CU NIPDAU N / A for Pkg Type -40 to 85 INA118P
& no Sb/Br)
INA118PB ACTIVE PDIP P 8 50 Green (RoHS CU NIPDAU N / A for Pkg Type INA118P
& no Sb/Br) B
INA118PBG4 ACTIVE PDIP P 8 50 Green (RoHS CU NIPDAU N / A for Pkg Type INA118P
& no Sb/Br) B
INA118PG4 ACTIVE PDIP P 8 50 Green (RoHS CU NIPDAU N / A for Pkg Type -40 to 85 INA118P
& no Sb/Br)
INA118U ACTIVE SOIC D 8 75 Green (RoHS CU NIPDAU Level-3-260C-168 HR INA
& no Sb/Br) 118U
INA118U/2K5 ACTIVE SOIC D 8 2500 Green (RoHS CU NIPDAU Level-3-260C-168 HR INA
& no Sb/Br) 118U
INA118U/2K5G4 ACTIVE SOIC D 8 2500 Green (RoHS CU NIPDAU Level-3-260C-168 HR INA
& no Sb/Br) 118U
INA118UB ACTIVE SOIC D 8 75 Green (RoHS CU NIPDAU Level-3-260C-168 HR INA
& no Sb/Br) 118U
B
INA118UB/2K5 ACTIVE SOIC D 8 2500 Green (RoHS CU NIPDAU Level-3-260C-168 HR INA
& no Sb/Br) 118U
B
INA118UB/2K5G4 ACTIVE SOIC D 8 2500 Green (RoHS CU NIPDAU Level-3-260C-168 HR INA
& no Sb/Br) 118U
B
INA118UBG4 ACTIVE SOIC D 8 75 Green (RoHS CU NIPDAU Level-3-260C-168 HR INA
& no Sb/Br) 118U
B
INA118UG4 ACTIVE SOIC D 8 75 Green (RoHS CU NIPDAU Level-3-260C-168 HR INA
& no Sb/Br) 118U

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 25-Oct-2016

(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 9-Apr-2015

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
INA118U/2K5 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
INA118UB/2K5 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 9-Apr-2015

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
INA118U/2K5 SOIC D 8 2500 367.0 367.0 35.0
INA118UB/2K5 SOIC D 8 2500 367.0 367.0 35.0

Pack Materials-Page 2
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