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INA333
SBOS445C – JULY 2008 – REVISED DECEMBER 2015

INA333 Micro-Power (50μA), Zerø-Drift, Rail-to-Rail Out Instrumentation Amplifier

1 Features 3 Description
•
1 Low Offset Voltage: 25 μV (Maximum), G ≥ 100 The INA333 device is a low-power, precision
instrumentation amplifier offering excellent accuracy.
• Low Drift: 0.1 μV/°C, G ≥ 100 The versatile 3-operational amplifier design, small
• Low Noise: 50 nV/√Hz, G ≥ 100 size, and low power make it ideal for a wide range of
• High CMRR: 100 dB (Minimum), G ≥ 10 portable applications.
• Low Input Bias Current: 200 pA (Maximum) A single external resistor sets any gain from 1 to
• Supply Range: 1.8 V to 5.5 V 1000. The INA333 is designed to use an industry-
standard gain equation: G = 1 + (100 kΩ / RG).
• Input Voltage: (V–) +0.1 V to (V+) –0.1 V
• Output Range: (V–) +0.05 V to (V+) –0.05 V The INA333 device provides very low offset voltage
(25 μV, G ≥ 100), excellent offset voltage drift
• Low Quiescent Current: 50 μA
(0.1 μV/°C, G ≥ 100), and high common-mode
• Operating Temperature: –40°C to +125°C rejection (100 dB at G ≥ 10). It operates with power
• RFI Filtered Inputs supplies as low as 1.8 V (±0.9 V) and quiescent
• 8-Pin VSSOP and 8-Pin WSON Packages current is only 50 μA, making it ideal for battery-
operated systems. Using autocalibration techniques
to ensure excellent precision over the extended
2 Applications industrial temperature range, the INA333 device also
• Bridge Amplifiers offers exceptionally low noise density (50 nV/√Hz)
• ECG Amplifiers that extends down to DC.
• Pressure Sensors The INA333 device is available in both 8-pin VSSOP
• Medical Instrumentation and WSON surface-mount packages and is specified
over the TA = –40°C to +125°C temperature range.
• Portable Instrumentation
• Weigh Scales Device Information(1)
• Thermocouple Amplifiers PART NUMBER PACKAGE BODY SIZE (NOM)
• RTD Sensor Amplifiers VSSOP (8) 3.00 mm × 3.00 mm
INA333
• Data Acquisition WSON (8) 3.00 mm × 3.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.

Simplified Schematic
V+

2
VIN- RFI Filtered Inputs 150kW 150kW
A1
RFI Filtered Inputs
1
50kW
6
RG A3 VOUT
50kW
8

RFI Filtered Inputs 150kW 150kW

5
A2 REF
3
VIN+ RFI Filtered Inputs
INA333

4
100kW
V- G=1+
RG

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
INA333
SBOS445C – JULY 2008 – REVISED DECEMBER 2015 www.ti.com

Table of Contents
1 Features .................................................................. 1 7.4 Device Functional Modes........................................ 13
2 Applications ........................................................... 1 8 Application and Implementation ........................ 14
3 Description ............................................................. 1 8.1 Application Information............................................ 14
4 Revision History..................................................... 2 8.2 Typical Application ................................................. 14
5 Pin Configuration and Functions ......................... 3 9 Power Supply Recommendations...................... 19
6 Specifications......................................................... 4 10 Layout................................................................... 20
6.1 Absolute Maximum Ratings ...................................... 4 10.1 Layout Guidelines ................................................. 20
6.2 ESD Ratings.............................................................. 4 10.2 Layout Example .................................................... 20
6.3 Recommended Operating Conditions....................... 4 11 Device and Documentation Support ................. 21
6.4 Thermal Information ................................................. 4 11.1 Device Support...................................................... 21
6.5 Electrical Characteristics........................................... 5 11.2 Documentation Support ........................................ 22
6.6 Typical Characteristics .............................................. 7 11.3 Trademarks ........................................................... 22
7 Detailed Description ............................................ 13 11.4 Electrostatic Discharge Caution ............................ 22
7.1 Overview ................................................................. 13 11.5 Glossary ................................................................ 23
7.2 Functional Block Diagram ....................................... 13 12 Mechanical, Packaging, and Orderable
7.3 Feature Description................................................. 13 Information ........................................................... 23

4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision B (October 2008) to Revision C Page

• Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section ................................................................................................. 1

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5 Pin Configuration and Functions

DGK Package
8-Pin VSSOP DRG Package
Top View 8-Pin WSON
Top View

RG 1 8 RG
RG 1 8 RG
VIN- 2 7 V+ Exposed
VIN- 2 Thermal 7 V+
VIN+ 3 6 VOUT Die Pad
VIN+ 3 on 6 VOUT
V- 4 5 REF Underside
V- 4 5 REF

Pin Functions
PIN
I/O DESCRIPTION
NAME NO.
REF 5 I Reference input. This pin must be driven by low impedance or connected to ground.
RG 1, 8 — Gain setting pins. For gains greater than 1, place a gain resistor between pins 1 and 8.
V+ 7 — Positive supply
–
V 4 — Negative supply
VIN+ 3 I Positive input
VIN– 2 I Negative input
VOUT 6 O Output

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6 Specifications
6.1 Absolute Maximum Ratings
(1)
over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
Supply voltage 7 V
(2)
Analog input voltage (V–) – 0.3 (V+) + 0.3 V
Output short-circuit (3) Continuous
Operating temperature, TA –40 150 °C
Junction temperature, TJ 150 °C
Storage temperature, Tstg –65 150 °C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Input pins are diode-clamped to the power-supply rails. Input signals that can swing more than 0.3 V beyond the supply rails should be
current limited to 10 mA or less.
(3) Short-circuit to ground.

6.2 ESD Ratings

VALUE UNIT
(1)
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 ±4000
V(ESD) Electrostatic discharge Charged-device model (CDM), per JEDEC specification JESD22-C101 (2) ±1000 V
Machine model (MM) ±200

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
VS Supply voltage 1.8 5.5 V
Specified temperature –40 125 °C

6.4 Thermal Information

INA333
THERMAL METRIC (1) DGK (VSSOP) DRG (WSON) UNIT
8 PINS 8 PINS
RθJA Junction-to-ambient thermal resistance 169.5 60 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 62.7 60 °C/W
RθJB Junction-to-board thermal resistance 90.3 50 °C/W
ψJT Junction-to-top characterization parameter 7.6 — °C/W
ψJB Junction-to-board characterization parameter 88.7 — °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance — 6 °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.

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6.5 Electrical Characteristics

for VS = 1.8 V to 5.5 V at TA = 25°C, RL = 10 kΩ, VREF = VS / 2, and G = 1 (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
INPUT (1)
VOSI Offset voltage, RTI (2) ±10 ±25/G ±25 ±75/G μV
vs temperature TA = –40°C to +125°C ±0.1 ±0.5 / G μV/°C
PSR vs power supply 1.8 V ≤ VS ≤ 5.5 V ±1 ±5/G ±5 ±15/G μV/V
(3)
Long-term stability See
Turnon time to specified VOSI TA = –40°C to +125°C See Typical Characteristics
Impedance
ZIN Differential 100 || 3 GΩ || pF
ZIN Common-mode 100 || 3 GΩ || pF
VCM Common-mode voltage range VO = 0 V (V–) + 0.1 (V+) – 0.1 V
Common-mode rejection DC to 60 Hz
VCM = (V–) + 0.1 V
G=1 80 90 dB
to (V+) – 0.1 V
VCM = (V–) + 0.1 V
G = 10 100 110 dB
CMR to (V+) – 0.1 V
VCM = (V–) + 0.1 V
G = 100 100 115 dB
to (V+) – 0.1 V
VCM = (V–) + 0.1 V
G = 1000 100 115 dB
to (V+) – 0.1 V
INPUT BIAS CURRENT
Input bias current ±70 ±200 pA
IB
vs temperature TA = –40°C to +125°C See Figure 26 pA/°C
Input offset current ±50 ±200 pA
IOS
vs temperature TA = –40°C to +125°C See Figure 28 pA/°C
INPUT VOLTAGE NOISE
G = 100, RS = 0 Ω, f = 10 Hz 50 nV/√Hz
G = 100, RS = 0 Ω, f = 100 Hz 50 nV/√Hz
eNI Input voltage noise
G = 100, RS = 0 Ω, f = 1 kHz 50 nV/√Hz
G = 100, RS = 0 Ω, f = 0.1 Hz to 10 Hz 1 μVPP
f = 10 Hz 100 fA/√Hz
iN Input current noise
f = 0.1 Hz to 10 Hz 2 pAPP
GAIN
G Gain equation 1 + (100 kΩ/RG) V/V
Range of gain 1 1000 V/V
VS = 5.5 V, (V–) + 100 mV
≤ VO ≤ (V+) – 100 mV
G=1 ±0.01% ±0.1%
Gain error
G = 10 ±0.05% ±0.25%
G = 100 ±0.07% ±0.25%
G = 1000 ±0.25% ±0.5%
Gain vs temperature, G = 1 TA = –40°C to +125°C ±1 ±5 ppm/°C
Gain vs temperature, G > 1 (4) TA = –40°C to +125°C ±15 ±50 ppm/°C
VS = 5.5 V, (V–) + 100 mV
Gain nonlinearity
≤ VO ≤ (V+) – 100 mV
Gain nonlinearity, G = 1 to 1000 RL = 10 kΩ 10 ppm
OUTPUT
Output voltage swing from rail VS = 5.5 V, RL = 10 kΩ See Figure 29 50 mV
Capacitive load drive 500 pF
ISC Short-circuit current Continuous to common –40, +5 mA

(1) Total VOS, referred-to-input = (VOSI) + (VOSO / G)

(2) RTI = Referred-to-input
(3) 300-hour life test at 150°C demonstrated randomly distributed variation of approximately 1 μV
(4) Does not include effects of external resistor RG
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Electrical Characteristics (continued)

for VS = 1.8 V to 5.5 V at TA = 25°C, RL = 10 kΩ, VREF = VS / 2, and G = 1 (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
FREQUENCY RESPONSE
G=1 150 kHz
G = 10 35 kHz
Bandwidth, –3dB
G = 100 3.5 kHz
G = 1000 350 Hz
VS = 5 V, VO = 4-V step, G = 1 0.16 V/μs
SR Slew rate
VS = 5 V, VO = 4-V step, G = 100 0.05 V/μs
VSTEP = 4 V, G = 1 50 μs
tS Settling time to 0.01%
VSTEP = 4 V, G = 100 400 μs
VSTEP = 4 V, G = 1 60 μs
tS Settling time to 0.001%
VSTEP = 4 V, G = 100 500 μs
Overload recovery 50% overdrive 75 μs
REFERENCE INPUT
RIN 300 kΩ
Voltage range V– V+ V
POWER SUPPLY
Single voltage range +1.8 +5.5 V
Voltage range
Dual voltage range ±0.9 ±2.75 V
Quiescent current VIN = VS / 2 50 75 μA
IQ
vs temperature TA = –40°C to +125°C 80 μA
TEMPERATURE RANGE
Specified temperature range –40 125 °C
Operating temperature range –40 150 °C

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6.6 Typical Characteristics

at TA = 25°C, VS = 5 V, RL = 10 kΩ, VREF = midsupply, and G = 1 (unless otherwise noted)

VS = 5.5V VS = 5.5V

Population
Population

-0.10
-0.09
-0.08
-0.07
-0.06
-0.05
-0.04
-0.03
-0.02
-0.01
0
0.01
0.02
0.03
0.04
0.05
0.06
0.07
0.08
0.09
0.10
10.0
-25.0
-22.5
-20.0
-17.5
-15.0
-12.5
-10.0
-7.5
-5.0
-2.5
0
2.5
5.0
7.5

12.5
15.0
17.5
20.0
22.5
25.0
Input Offset Voltage (mV) Input Voltage Offset Drift (mV/°C)

Figure 1. Input Offset Voltage Figure 2. Input Voltage Offset Drift (–40°C to 125°C)

VS = 5.5V VS = 5.5V

Population
Population

-0.50
-0.45
-0.40
-0.35
-0.30
-0.25
-0.20
-0.15
-0.10
-0.05
0
0.05
0.10
0.15
0.20
0.25
0.30
0.35
0.40
0.45
0.50
30.0
-75.0
-67.5
-60.0
-52.5
-45.0
-37.5
-30.0
-22.5
-15.0
-7.5
0
7.5
15.0
22.5

37.5
45.0
52.5
60.0
67.5
75.0

Output Offset Voltage (mV) Output Voltage Offset Drift (mV/°C)

Figure 3. Output Offset Voltage Figure 4. Output Voltage Offset Drift (–40°C to 125°C)
0
Gain = 1
VS = 1.8V
-5
VS = 5V
Noise (1mV/div)

-10
VOS (mV)

-15

-20

-25
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 Time (1s/div)
VCM (V)

Figure 5. Offset Voltage vs Common-Mode Voltage Figure 6. 0.1-Hz to 10-Hz Noise

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Typical Characteristics (continued)

at TA = 25°C, VS = 5 V, RL = 10 kΩ, VREF = midsupply, and G = 1 (unless otherwise noted)
1000 1000
Gain = 100
Output Noise

Voltage Noise Density (nV/ÖHz)

Current Noise Density (fA/ÖHz)

Noise (0.5mV/div)

100 100

Current Noise
Input Noise
10 10
2
2
(Output Noise)
Total Input-Referred Noise = (Input Noise) +
G

1 1
Time (1s/div) 0.1 1 10 100 1k 10k
Frequency (Hz)

Figure 7. 0.1-Hz to 10-Hz Noise Figure 8. Spectral Noise Density

0.012
G = 1000 Gain = 1
DC Output Nonlinearity Error (%FSR)

VS = ±2.75V
G = 100
0.008
G = 10

Output Voltage (1V/div)

G=1
0.004

-0.004

-0.008

-0.012
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Time (25ms/div)
VOUT (V)

Figure 9. Nonlinearity Error Figure 10. Large Signal Response

Gain = 100 Gain = 1

Output Voltage (50mV/div)
Output Voltage (1V/div)

Time (100ms/div) Time (10ms/div)

Figure 11. Large-Signal Step Response Figure 12. Small-Signal Step Response

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Typical Characteristics (continued)

at TA = 25°C, VS = 5 V, RL = 10 kΩ, VREF = midsupply, and G = 1 (unless otherwise noted)
10000
Gain = 100
Output Voltage (50mV/div)

1000

Time (ms)
0.001%
100

0.01% 0.1%
10
Time (100ms/div) 1 10 100 1000
Gain (V/V)

Figure 13. Small-Signal Step Response Figure 14. Settling Time vs Gain
80
Gain = 1
Supply G = 1000
60
G = 100
VOUT 40
VOUT (50mV/div)
Supply (1V/div)

G = 10
Gain (dB)

20
G=1
0

-20

-40

-60
Time (50ms/div) 10 100 1k 10k 100k 1M
Frequency (Hz)

Figure 15. Start-Up Settling Time Figure 16. Gain vs Frequency

10
VS = 5.5V VS = ±2.75V
8
G=1 VS = ±0.9V
6
4
G = 10
CMRR (mV/V)
Population

2
0
-2
-4
G = 100,
-6 G = 1000
-8
-10
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
10
20
30
40
50
60
70
80
90
100

-50 -25 0 25 50 75 100 125 150

CMRR (mV/V) Temperature (°C)

Figure 17. Common-Mode Rejection Ratio Figure 18. Common-Mode Rejection Ratio vs Temperature

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Typical Characteristics (continued)

at TA = 25°C, VS = 5 V, RL = 10 kΩ, VREF = midsupply, and G = 1 (unless otherwise noted)
160 2.5
VS = ±2.5V
140 2.0
VREF = 0

Common-Mode Voltage (V)

G = 1000
120
G = 100 1.0
100 All Gains
CMRR (dB)

80 0

60
G=1 -1.0
40
G = 10
20 -2.0
0 2.5
10 100 1k 10k 100k -2.5 -2.0 -1.0 0 1.0 2.0 2.5
Frequency (Hz) Output Voltage (V)

Figure 19. Common-Mode Rejection Ratio vs Frequency Figure 20. Typical Common-Mode Range vs Output Voltage
5 0.9
VS = +5V VS = ±0.9V
VREF = 0 0.7 VREF = 0
Common-Mode Voltage (V)

Common-Mode Voltage (V)

4 0.5

0.3
3
0.1
All Gains All Gains
-0.1
2
-0.3

1 -0.5

-0.7

0 -0.9
0 1 2 3 4 5 -0.9 -0.7 -0.5 -0.3 -0.1 0.1 0.3 0.5 0.7 0.9
Output Voltage (V) Output Voltage (V)

Figure 21. Typical Common-Mode Range vs Output Voltage Figure 22. Typical Common-Mode Range vs Output Voltage
1.8 160
VS = +1.8V
1.6 VREF = 0 140
G = 1000
Common-Mode Voltage (V)

1.4 120
1.2
+PSRR (dB)

100
1.0 G = 100
All Gains 80
0.8
60
0.6
G = 10
40
0.4
G=1
0.2 20

0 0
0 0.2 0.4 0.5 0.8 1.0 1.2 1.4 1.6 1.8 1 10 100 1k 10k 100k 1M
Output Voltage (V) Frequency (Hz)

Figure 23. Typical Common-Mode Range vs Output Voltage Figure 24. Positive Power-Supply Rejection Ratio

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Typical Characteristics (continued)

at TA = 25°C, VS = 5 V, RL = 10 kΩ, VREF = midsupply, and G = 1 (unless otherwise noted)
160 1200
VS = 5V +IB
140
G = 100 1000 -IB
120
G = 1000 800
100
-PSRR (dB)

600

IB (pA)
80
G = 10
60 400
VS = ±0.9V VS = ±2.75V
40
G=1 200
20
0
0

-20 -200
0.1 1 10 100 1k 10k 100k 1M -50 -25 0 25 50 75 100 125 150
Frequency (Hz) Temperature (°C)

Figure 25. Negative Power-Supply Rejection Ratio Figure 26. Input Bias Current vs Temperature
200 250
180
200
160
140 150
| IB | (pA)

120
IOS (pA)

100
100 VS = ±2.75V
50
80
60 0
VS = 5V VS = ±0.9V
40
-50
20
VS = 1.8V
0 -100
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 -50 -25 0 25 50 75 100 125 150
VCM (V) Temperature (°C)

Figure 27. Input Bias Current vs Common-Mode Voltage Figure 28. Input Offset Current vs Temperature
(V+) 80
(V+) - 0.25 VS = ±2.75V
(V+) - 0.50 VS = ±0.9V 70
(V+) - 0.75 VS = 5V
(V+) - 1.00 60
(V+) - 1.25
(V+) - 1.50 50
VOUT (V)

IQ (mA)

(V+) - 1.75
40
(V-) + 1.75 VS = 1.8V
(V-) + 1.50 30
(V-) + 1.25
(V-) + 1.00 20
(V-) + 0.75 +125°C
(V-) + 0.50 +25°C 10
(V-) + 0.25 -40°C
(V-) 0
0 10 20 30 40 50 60 -50 -25 0 25 50 75 100 125 150
IOUT (mA) Temperature (°C)

Figure 29. Output Voltage Swing vs Output Current Figure 30. Quiescent Current vs Temperature

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Typical Characteristics (continued)

at TA = 25°C, VS = 5 V, RL = 10 kΩ, VREF = midsupply, and G = 1 (unless otherwise noted)
80

70
VS = 5V
60

50

IQ (mA)
40
VS = 1.8V
30

20

10

0
0 1.0 2.0 3.0 4.0 5.0
VCM (V)

Figure 31. Quiescent Current vs Common-Mode Voltage

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7 Detailed Description

7.1 Overview
The INA333 is a monolithic instrumentation amplifier (INA) based on the precision zero-drift OPA333 (operational
amplifier) core. The INA333 also integrates laser-trimmed resistors to ensure excellent common-mode rejection
and low gain error. The combination of the zero-drift amplifier core and the precision resistors allows this device
to achieve outstanding DC precision and makes the INA333 ideal for many 3.3-V and 5-V industrial applications.

7.2 Functional Block Diagram

V+

2
VIN- RFI Filtered Inputs 150kW 150kW
A1
RFI Filtered Inputs
1
50kW
6
RG A3 VOUT
50kW
8

RFI Filtered Inputs 150kW 150kW

5
A2 REF
3
VIN+ RFI Filtered Inputs
INA333

4
100kW
V- G=1+
RG

7.3 Feature Description

The INA333 is a low-power, zero-drift instrumentation amplifier offering excellent accuracy. The versatile three-
operational-amplifier design and small size make the amplifiers ideal for a wide range of applications. Zero-drift
chopper circuitry provides excellent DC specifications. A single external resistor sets any gain from 1 to 10,000.
The INA333 is laser trimmed for very high common-mode rejection (100 dB at G ≥ 100). This devices operate
with power supplies as low as 1.8 V, and quiescent current of 50 µA, typically.

7.4 Device Functional Modes

7.4.1 Internal Offset Correction
INA333 internal operational amplifiers use an auto-calibration technique with a time-continuous 350-kHz
operational amplifier in the signal path. The amplifier is zero-corrected every 8 µs using a proprietary technique.
Upon power up, the amplifier requires approximately 100 µs to achieve specified VOS accuracy. This design has
no aliasing or flicker noise.

7.4.2 Input Common-Mode Range

The linear input voltage range of the input circuitry of the INA333 is from approximately 0.1 V below the positive
supply voltage to 0.1 V above the negative supply. As a differential input voltage causes the output voltage to
increase, however, the linear input range is limited by the output voltage swing of amplifiers A1 and A2. Thus, the
linear common-mode input range is related to the output voltage of the complete amplifier. This behavior also
depends on supply voltage—see Figure 20.
Input overload conditions can produce an output voltage that appears normal. For example, if an input overload
condition drives both input amplifiers to the respective positive output swing limit, the difference voltage
measured by the output amplifier is near zero. The output of the INA333 is near 0 V even though both inputs are
overloaded.

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8 Application and Implementation

NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.

8.1 Application Information

The INA333 measures small differential voltage with high common-mode voltage developed between the
noninverting and inverting input. The high input impedance makes the INA333 suitable for a wide range of
applications. The ability to set the reference pin to adjust the functionality of the output signal offers additional
flexibility that is practical for multiple configurations.

8.2 Typical Application

Figure 32 shows the basic connections required for operation of the INA333 device. Good layout practice
mandates the use of bypass capacitors placed close to the device pins as shown.
The output of the INA333 device is referred to the output reference (REF) pin, which is normally grounded. This
connection must be low-impedance to assure good common-mode rejection. Although 15 Ω or less of stray
resistance can be tolerated while maintaining specified CMRR, small stray resistances of tens of Ωs in series
with the REF pin can cause noticeable degradation in CMRR.
V+

0.1mF

2
VIN- RFI Filter 150kW 150kW
A1
RFI Filter VO = G ´ (VIN+ - VIN-)
1 100kW
50kW G=1+
RG
6
RG A3
50kW +

8 Load VO
-
RFI Filter 150kW 150kW
5
A2
VIN+ 3 Ref
RFI Filter
INA333

4 0.1mF

Also drawn in simplified form: V-

VIN-

RG INA333 VO

Ref
VIN+

Figure 32. Basic Connections

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Typical Application (continued)

8.2.1 Design Requirements
The device can be configured to monitor the input differential voltage when the gain of the input signal is set by
the external resistor RG. The output signal references to the Ref pin. The most common application is where the
output is referenced to ground when no input signal is present by connecting the Ref pin to ground. When the
input signal increases, the output voltage at the OUT pin increases, too.

8.2.2 Detailed Design Procedure

8.2.2.1 Setting the Gain

Gain of the INA333 device is set by a single external resistor, RG, connected between pins 1 and 8. The value of
RG is selected according to Equation 1:
G = 1 + (100 kΩ / RG) (1)
Table 1 lists several commonly-used gains and resistor values. The 100 kΩ in Equation 1 comes from the sum of
the two internal feedback resistors of A1 and A2. These on-chip resistors are laser trimmed to accurate absolute
values. The accuracy and temperature coefficient of these resistors are included in the gain accuracy and drift
specifications of the INA333 device.
The stability and temperature drift of the external gain setting resistor, RG, also affects gain. The contribution of
RG to gain accuracy and drift can be directly inferred from the gain Equation 1. Low resistor values required for
high gain can make wiring resistance important. Sockets add to the wiring resistance and contribute additional
gain error (possibly an unstable gain error) in gains of approximately 100 or greater. To ensure stability, avoid
parasitic capacitance of more than a few picofarads at the RG connections. Careful matching of any parasitics on
both RG pins maintains optimal CMRR over frequency.

Table 1. Commonly-Used Gains and Resistor Values

DESIRED GAIN RG (Ω) NEAREST 1% RG (Ω)
(1)
1 NC NC
2 100k 100k
5 25k 24.9k
10 11.1k 11k
20 5.26k 5.23k
50 2.04k 2.05
100 1.01k 1k
200 502.5 499
500 200.4 200
1000 100.1 100

(1) NC denotes no connection. When using the SPICE model, the simulation will not converge unless a
resistor is connected to the RG pins; use a very large resistor value.
8.2.2.2 Internal Offset Correction
The INA333 device internal operational amplifiers use an auto-calibration technique with a time-continuous 350-
kHz operational amplifier in the signal path. The amplifier is zero-corrected every 8 μs using a proprietary
technique. Upon power-up, the amplifier requires approximately 100 μs to achieve specified VOS accuracy. This
design has no aliasing or flicker noise.

8.2.2.3 Offset Trimming

Most applications require no external offset adjustment; however, if necessary, adjustments can be made by
applying a voltage to the REF pin. Figure 33 shows an optional circuit for trimming the output offset voltage. The
voltage applied to REF pin is summed at the output. The operational amplifier buffer provides low impedance at
the REF pin to preserve good common-mode rejection.

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VIN-
V+
RG INA333 VO
100mA
Ref 1/2 REF200
VIN+

100W
OPA333
±10mV 10kW
Adjustment Range
100W

100mA
1/2 REF200

V-

Figure 33. Optional Trimming of Output Offset Voltage

8.2.2.4 Noise Performance

The auto-calibration technique used by the INA333 device results in reduced low frequency noise, typically only
50 nV/√Hz, (G = 100). The spectral noise density can be seen in detail in Figure 8. Low frequency noise of the
INA333 device is approximately 1 μVPP measured from 0.1 Hz to 10 Hz, (G = 100).

8.2.2.5 Input Bias Current Return Path

The input impedance of the INA333 device is extremely high—approximately 100 GΩ. However, a path must be
provided for the input bias current of both inputs. This input bias current is typically ±70 pA. High input
impedance means that this input bias current changes very little with varying input voltage.
Input circuitry must provide a path for this input bias current for proper operation. Figure 34 shows various
provisions for an input bias current path. Without a bias current path, the inputs float to a potential that exceeds
the common-mode range of the INA333 device, and the input amplifiers will saturate. If the differential source
resistance is low, the bias current return path can be connected to one input (see the thermocouple example in
Figure 34). With higher source impedance, using two equal resistors provides a balanced input with possible
advantages of lower input offset voltage as a result of bias current and better high-frequency common-mode
rejection.

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Microphone,
Hydrophone, INA333
etc.

47kW 47kW

Thermocouple INA333

10kW

INA333

Center tap provides

bias current return.

Figure 34. Providing an Input Common-Mode Current Path

8.2.2.6 Input Common-Mode Range

The linear input voltage range of the input circuitry of the INA333 device is from approximately 0.1 V below the
positive supply voltage to 0.1 V above the negative supply. As a differential input voltage causes the output
voltage to increase, however, the linear input range is limited by the output voltage swing of amplifiers A1 and A2.
Thus, the linear common-mode input range is related to the output voltage of the complete amplifier. This
behavior also depends on supply voltage—see Figure 20 to Figure 23 in the Typical Characteristics section.
Input overload conditions can produce an output voltage that appears normal. For example, if an input overload
condition drives both input amplifiers to the respective positive output swing limit, the difference voltage
measured by the output amplifier is near zero. The output of the INA333 is near 0 V even though both inputs are
overloaded.

8.2.2.7 Operating Voltage

The INA333 operates over a power-supply range of 1.8 V to 5.5 V (±0.9 V to ±2.75 V). Supply voltages higher
than 7 V (absolute maximum) can permanently damage the device. Parameters that vary over supply voltage or
temperature are shown in the Typical Characteristics section of this data sheet.

8.2.2.8 Low Voltage Operation

The INA333 device can be operated on power supplies as low as ±0.9 V. Most parameters vary only slightly
throughout this supply voltage range—see the Typical Characteristics section. Operation at very low supply
voltage requires careful attention to assure that the input voltages remain within the linear range. Voltage swing
requirements of internal nodes limit the input common-mode range with low power-supply voltage. Figure 20 to
Figure 23 show the range of linear operation for various supply voltages and gains.

8.2.2.9 Single-Supply Operation

The INA333 device can be used on single power supplies of 1.8 V to 5.5 V. Figure 35 shows a basic single-
supply circuit. The output REF pin is connected to mid-supply. Zero differential input voltage demands an output
voltage of mid-supply. Actual output voltage swing is limited to approximately 50 mV more than ground, when the
load is referred to ground as shown. Figure 29 shows how the output voltage swing varies with output current.

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With single-supply operation, VIN+ and VIN– must both be 0.1 V more than ground for linear operation. For
instance, the inverting input cannot be connected to ground to measure a voltage connected to the noninverting
input.
To show the issues affecting low voltage operation, consider the circuit in Figure 35. It shows the INA333 device
operating from a single 3-V supply. A resistor in series with the low side of the bridge assures that the bridge
output voltage is within the common-mode range of the amplifier inputs.
+3V 3V

2V - DV

RG INA333 VO
300W
Ref
2V + DV 1.5V

150W
(1)
R1

(1) R1 creates proper common-mode voltage, only for low-voltage operation—see Single-Supply Operation.

Figure 35. Single-Supply Bridge Amplifier

8.2.2.10 Input Protection

The input pins of the INA333 device are protected with internal diodes connected to the power-supply rails.
These diodes clamp the applied signal to prevent it from damaging the input circuitry. If the input signal voltage
can exceed the power supplies by more than 0.3 V, the input signal current should be limited to less than 10 mA
to protect the internal clamp diodes. This current limiting can generally be done with a series input resistor. Some
signal sources are inherently current-limited and do not require limiting resistors.

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8.2.3 Application Curves

Gain = 1 Gain = 100

Output Voltage (1V/div)

Output Voltage (1V/div)

Time (25ms/div) Time (100ms/div)

Figure 36. Large Signal Response Figure 37. Large-Signal Step Response

Gain = 1 Gain = 100

Output Voltage (50mV/div)

Output Voltage (50mV/div)

Time (10ms/div) Time (100ms/div)

Figure 38. Small-Signal Step Response Figure 39. Small-Signal Step Response

9 Power Supply Recommendations

The minimum power supply voltage for INA333 is 1.8 V and the maximum power supply voltage is 5.5 V. For
optimum performance, 3.3 V to 5 V is recommended. TI recommends adding a bypass capacitor at the input to
compensate for the layout and power supply source impedance.

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10 Layout

10.1 Layout Guidelines

Attention to good layout practices is always recommended. Keep traces short and, when possible, use a printed-
circuit-board (PCB) ground plane with surface-mount components placed as close to the device pins as possible.
Place a 0.1-μF bypass capacitor closely across the supply pins. These guidelines should be applied throughout
the analog circuit to improve performance and provide benefits such as reducing the electromagnetic-
interference (EMI) susceptibility.
Instrumentation amplifiers vary in the susceptibility to radio-frequency interference (RFI). RFI can generally be
identified as a variation in offset voltage or DC signal levels with changes in the interfering RF signal. The
INA333 device has been specifically designed to minimize susceptibility to RFI by incorporating passive RC
filters with an 8-MHz corner frequency at the VIN+ and VIN– inputs. As a result, the INA333 device demonstrates
remarkably low sensitivity compared to previous generation devices. Strong RF fields may continue to cause
varying offset levels, however, and may require additional shielding.

10.2 Layout Example

Gain Resistor

Bypass
Capacitor
RG RG
V+
VIN- V-IN V+
V+IN VO VOUT
VIN+
V- Ref GND

Bypass
Capacitor

V- GND

Figure 40. INA333 Layout

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11 Device and Documentation Support

11.1 Device Support

11.1.1 Development Support

11.1.1.1 TINA-TI (Free Download Software)

Using TINA-TI SPICE-Based Analog Simulation Program with the INA333
TINA is a simple, powerful, and easy-to-use circuit simulation program based on a SPICE engine. TINA-TI is a
free, fully functional version of the TINA software, preloaded with a library of macromodels in addition to a range
of both passive and active models. It provides all the conventional DC, transient, and frequency domain analysis
of SPICE as well as additional design capabilities.
Available as a free download from the Analog eLab Design Center, TINA-TI offers extensive post-processing
capability that allows users to format results in a variety of ways.
Virtual instruments offer users the ability to select input waveforms and probe circuit nodes, voltages, and
waveforms, creating a dynamic quick-start tool.
Figure 41 and Figure 42 show example TINA-TI circuits for the INA333 device that can be used to develop,
modify, and assess the circuit design for specific applications. Links to download these simulation files are given
below.

NOTE
These files require that either the TINA software (from DesignSoft) or TINA-TI software be
installed. Download the free TINA-TI software from the TINA-TI folder.

VoA1
1/2 of matched
monolithic dual RELATED PRODUCTS
NPN transistors For monolithic logarithmic amplifiers (such as LOG112 or LOG114) see the link in footnote 1.
(example: MMDT3904)

Vout

2 _ 4 U1 INA333
3
2 RG V-
R3 14k

- R8 10k -
+ 1
Out
Input I 10n 1 + 4 V 8 Ref 6 +
+ VM1 RG V+ +
5 U5 OPA369 U1 OPA335
C1 1n

+ 5
Vref+

Vref+

3 7 Vdiff
VCC

Vref+

VCC

Optional buffer for driving

VCC

1/2 of matched SAR converters with

monolithic dual sampling systems of ³ 33kHz.
NPN transistors
Vref+

VCC

(example: MMDT3904)

VoA2

Rset 2.5M uC Vref/2 2.5 V1 5

3
- 2

1 + NOTE: Temperature compensation

4
uC Vref/2 2.5

+ of logging transistors is not shown.

5 U6 OPA369
Vref+

VCC

(1) The following link launches the TI logarithmic amplifiers web page: Logarithmic Amplifier Products Home Page

Figure 41. Low-Power Log Function Circuit for Portable Battery-Powered Systems
(Example Glucose Meter)

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Device Support (continued)

To download a compressed file that contains the TINA-TI simulation file for this circuit, click the following link:
Log Circuit.
3V

R1
2kW

RWa
EMU21 RTD3 3W
-
Pt100 RTD RWb U2
3W OPA333
+
VT+ RTD+ + 2 _ 4 U1 INA333
VT 25 3V
VT- RTD- RG V- VDIFF
1 MSP430
RGAIN PGA112
Mon+ Mon- Out
100kW 8 Ref 6
RG V+
RWc
RZERO + 5
4W 3
Temp (°C) 100W 7
+
(Volts = °C) V
VREF+

VRTD 3V
RWd
RTD Resistance 3W
(Volts = Ohms)

+ +
A IREF1 A IREF2
3V

VREF 3V
U1 REF3212 VREF VREF
Use BF861A S Use BF861A 3V
EN OUTF
In + T3 BF256A
OUTS + +
T1 BF256A +
GNDF GNDS OPA3331 OPA333 U3
3V
C7 - OPA333
470nF G -

V4 3

RSET2
RSET1
2.5kW
2.5kW

RWa, RWb, RWc, and RWd simulate wire resistance. These resistors are included to show the four-wire sense technique immunity to line
mismatches. This method assumes the use of a four-wire RTD.

Figure 42. Four-Wire, 3-V Conditioner for a PT100 RTD With Programmable Gain Acquisition System

To download a compressed file that contains the TINA-TI simulation file for this circuit, click the following link:
PT100 RTD.

11.2 Documentation Support

11.2.1 Related Documentation
For related documentation see the following:
• Precision, Low-Noise, Rail-to-Rail Output, 36-V, Zero-Drift Operational Amplifiers, SBOS642
• 50μV VOS, 0.25μV/°C, 35μA CMOS OPERATIONAL AMPLIFIERS Zerø-Drift Series, SBOS432
• 4ppm/°C, 100μA, SOT23-6 SERIES VOLTAGE REFERENCE, SBVS058
• Circuit Board Layout Techniques, SLOA089

11.3 Trademarks
All trademarks are the property of their respective owners.
11.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.

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11.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback 23

Product Folder Links: INA333
 PACKAGE OPTION ADDENDUM

www.ti.com 20-Aug-2021

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

INA333AIDGKR ACTIVE VSSOP DGK 8 2500 RoHS & Green NIPDAU | NIPDAUAG Level-2-260C-1 YEAR -40 to 125 I333

INA333AIDGKRG4 ACTIVE VSSOP DGK 8 2500 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 I333

INA333AIDGKT ACTIVE VSSOP DGK 8 250 RoHS & Green NIPDAU | NIPDAUAG Level-2-260C-1 YEAR -40 to 125 I333

INA333AIDGKTG4 ACTIVE VSSOP DGK 8 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 I333

INA333AIDRGR ACTIVE SON DRG 8 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 I333A

INA333AIDRGT ACTIVE SON DRG 8 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 I333A

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 20-Aug-2021

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF INA333 :

• Automotive : INA333-Q1

NOTE: Qualified Version Definitions:

• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 3-Jun-2022

TAPE AND REEL INFORMATION

REEL DIMENSIONS TAPE DIMENSIONS

K0 P1

B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2 Q1 Q2

Q3 Q4 Q3 Q4 User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
INA333AIDGKR VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
INA333AIDGKT VSSOP DGK 8 250 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
INA333AIDRGR SON DRG 8 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
INA333AIDRGT SON DRG 8 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 3-Jun-2022

TAPE AND REEL BOX DIMENSIONS

Width (mm)
H
W

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
INA333AIDGKR VSSOP DGK 8 2500 366.0 364.0 50.0
INA333AIDGKT VSSOP DGK 8 250 366.0 364.0 50.0
INA333AIDRGR SON DRG 8 3000 356.0 356.0 35.0
INA333AIDRGT SON DRG 8 250 210.0 185.0 35.0

Pack Materials-Page 2
 PACKAGE OUTLINE
DRG0008B SCALE 4.000
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD

3.1 B
A
2.9

3.1
PIN 1 INDEX AREA 2.9

0.8
0.7

SEATING PLANE DIMENSION A

0.05 OPTION 01 (0.1)
0.00 0.05 C
OPTION 02 (0.2)

(DIM A) TYP
EXPOSED 1.45 0.1 OPT 01 SHOWN
THERMAL PAD

4
5

2X
1.5 2.4 0.1

8
1
6X 0.5
0.3
8X
0.2
PIN 1 ID 0.6
8X 0.1 C A B
(OPTIONAL) 0.4
0.08 C

4218886/A 01/2020
NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

www.ti.com
 EXAMPLE BOARD LAYOUT
DRG0008B WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD

(1.45)

8X (0.7) SYMM

1 8

8X (0.25)

(2.4)

6X (0.5) (0.95)
4
5

(R0.05) TYP

(0.475)
( 0.2) VIA
TYP (2.7)

LAND PATTERN EXAMPLE

SCALE:20X

0.07 MAX 0.07 MIN

ALL AROUND ALL AROUND

SOLDER MASK METAL METAL UNDER SOLDER MASK

OPENING SOLDER MASK OPENING
NON SOLDER MASK
SOLDER MASK
DEFINED
DEFINED
(PREFERRED)

SOLDER MASK DETAILS

4218886/A 01/2020
NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.

www.ti.com
 EXAMPLE STENCIL DESIGN
DRG0008B WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD

SYMM METAL
8X (0.7)
TYP

8X (0.25) 1 8

(0.635)
SYMM

6X (0.5)
4 (1.07)
5

(R0.05) TYP

(1.47)

(2.7)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD
82% PRINTED SOLDER COVERAGE BY AREA
SCALE:25X

4218886/A 01/2020

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.

www.ti.com
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