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Simulation Is The Process of Using Simulation Software (Simulator) To Verify The Functional

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Simulation is used to verify the functional correctness of a digital design modeled in a hardware description language, while synthesis translates the HDL description into a lower-level implementation consisting of logic gates. Specifically: - Simulation verifies timing and ensures the design functions as intended, while synthesis outputs a netlist specifying electronic components and their connections. - Simulation occurs before and after synthesis, with pre-synthesis functional simulation and post-synthesis timing simulation. - Synthesis translates the HDL description through steps like optimization and technology mapping to produce a gate-level implementation targeted to a specific technology.

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Simulation Is The Process of Using Simulation Software (Simulator) To Verify The Functional

Uploaded by

ShafiullaShaik
51 views2 pages
Simulation is used to verify the functional correctness of a digital design modeled in a hardware description language, while synthesis translates the HDL description into a lower-level implementation consisting of logic gates. Specifically: - Simulation verifies timing and ensures the design functions as intended, while synthesis outputs a netlist specifying electronic components and their connections. - Simulation occurs before and after synthesis, with pre-synthesis functional simulation and post-synthesis timing simulation. - Synthesis translates the HDL description through steps like optimization and technology mapping to produce a gate-level implementation targeted to a specific technology.

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Simulation is used to verify the functional correctness of a digital design modeled in a hardware description language, while synthesis translates the HDL description into a lower-level implementation consisting of logic gates. Specifically: - Simulation verifies timing and ensures the design functions as intended, while synthesis outputs a netlist specifying electronic components and their connections. - Simulation occurs before and after synthesis, with pre-synthesis functional simulation and post-synthesis timing simulation. - Synthesis translates the HDL description through steps like optimization and technology mapping to produce a gate-level implementation targeted to a specific technology.

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51 views2 pages

Simulation Is The Process of Using Simulation Software (Simulator) To Verify The Functional

Uploaded by

ShafiullaShaik
Simulation is used to verify the functional correctness of a digital design modeled in a hardware description language, while synthesis translates the HDL description into a lower-level implementation consisting of logic gates. Specifically: - Simulation verifies timing and ensures the design functions as intended, while synthesis outputs a netlist specifying electronic components and their connections. - Simulation occurs before and after synthesis, with pre-synthesis functional simulation and post-synthesis timing simulation. - Synthesis translates the HDL description through steps like optimization and technology mapping to produce a gate-level implementation targeted to a specific technology.

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Hardware Description Language

In electronics, a hardware description language (HDL) is a specialized computer language used


to describe the structure and behavior of electronic circuits, and most commonly, digital
logic circuits.

A hardware description language enables a precise, formal description of an electronic circuit that
allows for the automated analysis and simulation of an electronic circuit. It also allows for
the synthesis of a HDL description into a netlist (a specification of physical electronic components
and how they are connected together), which can then be placed and routed to produce the set of
masks used to create an integrated circuit.

Simulation is the process of using simulation software (simulator) to verify the functional
correctness of a digital design that is modeled using a HDL (hardware description language) like
Verilog.
Synthesis is a process in which a design behavior that is modeled using a HDL is translated into an
implementation consisting of logic gates. This is done by a synthesis tool which is another
software program.

They have different objects. The Simulation can verify the timing of the circuit. The synthesis can
output the netlist.

From SW designers' view, Simulation process is sth like the debugging process, while the
Synthesis process is sth like the compile-link-make process. what's more, the Synthesis process
is the key point of EDA technology, which makes the Automatic process possible, and also
interesting.
Simulation is verifying the functionality of the design and synthesis is the implementation of the
design in to the actual hardware.
Simulation comes after synthesis. Design must synthesize first prior to simulation.
The difference between simulation and synthesis is simple Simulation is nothing but whatever
expected logical functionality checking in Hardware world, with out considering the actual timing
issues i.e net delays and ckt delays where as synthesis is actually targetting your functionally rather
logically verified design to the proplerly targetted technology like 90nm technology etc After
synthesis you can check that whatever funtionality you are expecting is achived with repect to all
the reality deviced place
SYNTHESIS is related to ur Target devive architecture. SIMULATION is just verification of ur
logical design.
Simulation is to verify that the design would work as we intended synthesis is to translate the
design into a next level of abstraction.
For example from RTL level to gate level

Simulation is to verify your design. Thus it is first step after your design and coding is done. It is
totally software activity where you verify your design using simulators like ModelSim. This step is
also called as functional simulation. Once you have verified your design, you need to target your
design into hardware. So you need to convert your RTL into gate level design. Synthesis is divided
into three steps: Translation, Optimization and Technology Mapping. Translation: RTL to gate-
level netlists. Optimization: technology-independent logic-level optimization to reduce hardware
for required functionality. Technology Mapping: technology-independent netlists are transformed
into technology-dependent ones. Synthesis tools do all these steps. Designer needs to specify the
optimization constraints, which the synthesis tool tries to meet. After synthesis there is one more
simulation called Timing simulation. It may appear difficult for the first time but you will
understand it as you study more about it. You may not be familiar with some of the terms, feel free
to ask any doubts.

Synthesis is to transfer the RTL code to gate level. Simulation is to verify the RTL or gate level
function.
the difference between simulation and synthesis is that in simulation we r able to check the
expected output at a given time for which we write a rtl code while synthesis means the realization
of the rtl code in the physical circuit made from the standard libraries available.

In fact, there are two kinds of simulation


1- Behavioral (functional) simulation which is done pre-fit (before synthesis)
2- Timing simulation which is done post-fit (after synthesis) to ensure that it has achieved the
required timing.
Synthesis is process of convert RTL HDL design to Gate level netlist, then optimize and map this
netlist according to the vendor technology.

A lot of literature refers to functional simulation without synthesizing the code. However, this may
be a good way for an experience designer who has simulated similar modules in previous designs.
It may not be necessarliy wise to spend time on functional simulation prior to synthesis because
after all if the initial synthesized circuit is poor on area or speed, then several portions of the code
will be rewritten even though the design is functionally correct. Therefore early post-synthesis is
advisable to see what the expected results are.

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